diff --git a/.cdsinit b/.cdsinit new file mode 100644 index 00000000..7af8d64c --- /dev/null +++ b/.cdsinit @@ -0,0 +1,60 @@ +; TIGFET10nm Open Source Predictive Process Design Kit +; Copyright (c) [2019] [Laboratory for NanoIntegrated Systems] +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are +; met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its +; contributors may be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +; Customizations can be made at the end of this file + +; Load display.drf +envSetVal( "graphic" "drfPath" 'string strcat( getShellEnvVar("PDK_DIR") "/cdslib/setup/display.drf")) + +; Load Bind Keys +loadi( strcat( getShellEnvVar("PDK_DIR") "/cdslib/setup/common_bindkeys.il")) + +; Setup Calibre +if( getShellEnvVar("MGC_HOME") then + loadi( strcat( getShellEnvVar("MGC_HOME") "/shared/pkgs/icv/tools/queryskl/calibre.OA.skl")) +) ;if + +; Load SKILL code in skill directory +loadi( strcat( getShellEnvVar("PDK_DIR") "/cdslib/skill/loadSkill.il")) + +; Load default .cdsenv file +(envLoadVals ?envFile strcat( getShellEnvVar("PDK_DIR") "/cdslib/setup/cdsenv") ?tool "layout") + +printf( strcat( +"---------------------------------------------------------------------------\n" +"Welcome to the TIGFET10nm Free, Open-Source Process Design Kit\n" +"\n" +"---------------------------------------------------------------------------\n" +"\n" +"Done loading TIGFET10nm_PDK customizations.\n" +)) + +; Comment the line below to disable auto opening of the Library Manager +ddsOpenLibManager() diff --git a/.gitignore b/.gitignore index ea9d22d0..ca2ab583 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,12 @@ .vscode dump cdlForForum +*.log +*.log.* +*.cdslck +*.cdslck.* +*.txt +*.jpg +.cadence/ +*.oa- +*.bak diff --git a/Logic/.oalib b/Logic/.oalib new file mode 100644 index 00000000..21ffef89 --- /dev/null +++ b/Logic/.oalib @@ -0,0 +1,6 @@ + + + + + diff --git a/Logic/cdsinfo.tag b/Logic/cdsinfo.tag new file mode 100644 index 00000000..b75aa95c --- /dev/null +++ b/Logic/cdsinfo.tag @@ -0,0 +1,41 @@ +# +# This is a cdsinfo.tag file. +# +# See the "Cadence Application Infrastructure Reference Manual" for +# details on the format of this file, its semantics, and its use. +# +# The `#' character denotes a comment. Removing the leading `#' +# character from any of the entries below will activate them. +# +# CDSLIBRARY entry - add this entry if the directory containing +# this cdsinfo.tag file is the root of a Cadence library. +# CDSLIBRARY +# +# CDSLIBCHECK - set this entry to require that libraries have +# a cdsinfo.tag file with a CDSLIBRARY entry. Legal values are +# ON and OFF. By default (OFF), directories named in a cds.lib file +# do not have to have a cdsinfo.tag file with a CDSLIBRARY entry. +# CDSLIBCHECK ON +# +# DMTYPE - set this entry to define the DM system for Cadence's +# Generic DM facility. Values will be shifted to lower case. +# DMTYPE none +# DMTYPE crcs +# DMTYPE tdm +# DMTYPE sync +# +# NAMESPACE - set this entry to define the library namespace according +# to the type of machine on which the data is stored. Legal values are +# `LibraryNT' and +# `LibraryUnix'. +# NAMESPACE LibraryUnix +# +# Other entries may be added for use by specific applications as +# name-value pairs. Application documentation will describe the +# use and behaviour of these entries when appropriate. +# +# Current Settings: +# +CDSLIBRARY +DMTYPE none +NAMESPACE LibraryUnix diff --git a/Logic/data.dm b/Logic/data.dm new file mode 100644 index 00000000..d21b7180 Binary files /dev/null and b/Logic/data.dm differ diff --git a/Logic/hiz_inverter/schematic/data.dm b/Logic/hiz_inverter/schematic/data.dm new file mode 100644 index 00000000..b7f70776 Binary files /dev/null and b/Logic/hiz_inverter/schematic/data.dm differ diff --git a/Logic/hiz_inverter/schematic/master.tag b/Logic/hiz_inverter/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/Logic/hiz_inverter/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/Logic/hiz_inverter/schematic/sch.oa b/Logic/hiz_inverter/schematic/sch.oa new file mode 100644 index 00000000..b09cf76e Binary files /dev/null and b/Logic/hiz_inverter/schematic/sch.oa differ diff --git a/Logic/hiz_inverter/schematic/thumbnail_128x128.png b/Logic/hiz_inverter/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..e90ee035 Binary files /dev/null and b/Logic/hiz_inverter/schematic/thumbnail_128x128.png differ diff --git a/Logic/hiz_inverter/symbol/master.tag b/Logic/hiz_inverter/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/Logic/hiz_inverter/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/Logic/hiz_inverter/symbol/symbol.oa b/Logic/hiz_inverter/symbol/symbol.oa new file mode 100644 index 00000000..4a22c142 Binary files /dev/null and b/Logic/hiz_inverter/symbol/symbol.oa differ diff --git a/Logic/hiz_inverter/symbol/thumbnail_128x128.png b/Logic/hiz_inverter/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..ce4937f7 Binary files /dev/null and b/Logic/hiz_inverter/symbol/thumbnail_128x128.png differ diff --git a/Logic/hiz_inverter_neg/layout/layout.oa b/Logic/hiz_inverter_neg/layout/layout.oa new file mode 100644 index 00000000..fd6e5059 Binary files /dev/null and b/Logic/hiz_inverter_neg/layout/layout.oa differ diff --git a/Logic/hiz_inverter_neg/layout/master.tag b/Logic/hiz_inverter_neg/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/Logic/hiz_inverter_neg/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/Logic/hiz_inverter_neg/layout/thumbnail_128x128.png b/Logic/hiz_inverter_neg/layout/thumbnail_128x128.png new file mode 100644 index 00000000..0e9d3880 Binary files /dev/null and b/Logic/hiz_inverter_neg/layout/thumbnail_128x128.png differ diff --git a/Logic/hiz_inverter_neg/schematic/data.dm b/Logic/hiz_inverter_neg/schematic/data.dm new file mode 100644 index 00000000..b7f70776 Binary files /dev/null and b/Logic/hiz_inverter_neg/schematic/data.dm differ diff --git a/Logic/hiz_inverter_neg/schematic/master.tag b/Logic/hiz_inverter_neg/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/Logic/hiz_inverter_neg/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/Logic/hiz_inverter_neg/schematic/sch.oa b/Logic/hiz_inverter_neg/schematic/sch.oa new file mode 100644 index 00000000..85cdb974 Binary files /dev/null and b/Logic/hiz_inverter_neg/schematic/sch.oa differ diff --git a/Logic/hiz_inverter_neg/schematic/thumbnail_128x128.png b/Logic/hiz_inverter_neg/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..4dd32df4 Binary files /dev/null and b/Logic/hiz_inverter_neg/schematic/thumbnail_128x128.png differ diff --git a/Logic/hiz_inverter_neg/symbol/master.tag b/Logic/hiz_inverter_neg/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/Logic/hiz_inverter_neg/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/Logic/hiz_inverter_neg/symbol/symbol.oa b/Logic/hiz_inverter_neg/symbol/symbol.oa new file mode 100644 index 00000000..c2fce80b Binary files /dev/null and b/Logic/hiz_inverter_neg/symbol/symbol.oa differ diff --git a/Logic/hiz_inverter_neg/symbol/thumbnail_128x128.png b/Logic/hiz_inverter_neg/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..ff09c751 Binary files /dev/null and b/Logic/hiz_inverter_neg/symbol/thumbnail_128x128.png differ diff --git a/Logic/inverter/data.dm b/Logic/inverter/data.dm new file mode 100644 index 00000000..6801d1bf Binary files /dev/null and b/Logic/inverter/data.dm differ diff --git a/Logic/inverter/schematic/data.dm b/Logic/inverter/schematic/data.dm new file mode 100644 index 00000000..b5133320 Binary files /dev/null and b/Logic/inverter/schematic/data.dm differ diff --git a/Logic/inverter/schematic/master.tag b/Logic/inverter/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/Logic/inverter/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/Logic/inverter/schematic/sch.oa b/Logic/inverter/schematic/sch.oa new file mode 100644 index 00000000..296b943a Binary files /dev/null and b/Logic/inverter/schematic/sch.oa differ diff --git a/Logic/inverter/schematic/thumbnail_128x128.png b/Logic/inverter/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..870239e9 Binary files /dev/null and b/Logic/inverter/schematic/thumbnail_128x128.png differ diff --git a/Logic/inverter/symbol/master.tag b/Logic/inverter/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/Logic/inverter/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/Logic/inverter/symbol/symbol.oa b/Logic/inverter/symbol/symbol.oa new file mode 100644 index 00000000..c86760b5 Binary files /dev/null and b/Logic/inverter/symbol/symbol.oa differ diff --git a/Logic/inverter/symbol/thumbnail_128x128.png b/Logic/inverter/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..fc1465c5 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a/Logic/mux2_1/schematic/master.tag b/Logic/mux2_1/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/Logic/mux2_1/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/Logic/mux2_1/schematic/sch.oa b/Logic/mux2_1/schematic/sch.oa new file mode 100644 index 00000000..259d781d Binary files /dev/null and b/Logic/mux2_1/schematic/sch.oa differ diff --git a/Logic/mux2_1/schematic/thumbnail_128x128.png b/Logic/mux2_1/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..6a3a5086 Binary files /dev/null and b/Logic/mux2_1/schematic/thumbnail_128x128.png differ diff --git a/Logic/mux2_1/symbol/master.tag b/Logic/mux2_1/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/Logic/mux2_1/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/Logic/mux2_1/symbol/symbol.oa b/Logic/mux2_1/symbol/symbol.oa new file mode 100644 index 00000000..ecc332f4 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differ diff --git a/Logic/xor2_alt_layout/layout/master.tag b/Logic/xor2_alt_layout/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/Logic/xor2_alt_layout/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/Logic/xor2_alt_layout/layout/thumbnail_128x128.png b/Logic/xor2_alt_layout/layout/thumbnail_128x128.png new file mode 100644 index 00000000..dba1818e Binary files /dev/null and b/Logic/xor2_alt_layout/layout/thumbnail_128x128.png differ diff --git a/Logic/xor2_low_leakage/data.dm b/Logic/xor2_low_leakage/data.dm new file mode 100644 index 00000000..9781fb1d Binary files /dev/null and b/Logic/xor2_low_leakage/data.dm differ diff --git a/Logic/xor2_low_leakage/layout/layout.oa b/Logic/xor2_low_leakage/layout/layout.oa new file mode 100644 index 00000000..4e3cb9da Binary files /dev/null and b/Logic/xor2_low_leakage/layout/layout.oa differ diff --git a/Logic/xor2_low_leakage/layout/master.tag b/Logic/xor2_low_leakage/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/Logic/xor2_low_leakage/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/Logic/xor2_low_leakage/layout/thumbnail_128x128.png b/Logic/xor2_low_leakage/layout/thumbnail_128x128.png new file mode 100644 index 00000000..b45cdb29 Binary files /dev/null and b/Logic/xor2_low_leakage/layout/thumbnail_128x128.png differ diff --git a/Logic/xor2_low_leakage/schematic/data.dm b/Logic/xor2_low_leakage/schematic/data.dm new file mode 100644 index 00000000..b4e70ded Binary files /dev/null and b/Logic/xor2_low_leakage/schematic/data.dm differ diff --git a/Logic/xor2_low_leakage/schematic/master.tag b/Logic/xor2_low_leakage/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/Logic/xor2_low_leakage/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/Logic/xor2_low_leakage/schematic/sch.oa b/Logic/xor2_low_leakage/schematic/sch.oa new file mode 100644 index 00000000..508e1c8b Binary files /dev/null and b/Logic/xor2_low_leakage/schematic/sch.oa differ diff --git a/Logic/xor2_low_leakage/schematic/thumbnail_128x128.png b/Logic/xor2_low_leakage/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..dc83aa67 Binary files /dev/null and b/Logic/xor2_low_leakage/schematic/thumbnail_128x128.png differ diff --git a/Logic/xor2_low_leakage/symbol/master.tag b/Logic/xor2_low_leakage/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/Logic/xor2_low_leakage/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/Logic/xor2_low_leakage/symbol/symbol.oa b/Logic/xor2_low_leakage/symbol/symbol.oa new file mode 100644 index 00000000..5f8c8e38 Binary files /dev/null and b/Logic/xor2_low_leakage/symbol/symbol.oa differ diff --git a/Logic/xor2_low_leakage/symbol/thumbnail_128x128.png b/Logic/xor2_low_leakage/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..c54b3a2b Binary files /dev/null and b/Logic/xor2_low_leakage/symbol/thumbnail_128x128.png differ diff --git a/Logic/xor3/schematic/data.dm b/Logic/xor3/schematic/data.dm new file mode 100644 index 00000000..0ad2bbde Binary files /dev/null and b/Logic/xor3/schematic/data.dm differ diff --git a/Logic/xor3/schematic/master.tag b/Logic/xor3/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/Logic/xor3/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/Logic/xor3/schematic/sch.oa b/Logic/xor3/schematic/sch.oa new file mode 100644 index 00000000..3383f8d7 Binary files /dev/null and b/Logic/xor3/schematic/sch.oa differ diff --git a/Logic/xor3/schematic/thumbnail_128x128.png b/Logic/xor3/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..f02ba0c6 Binary files /dev/null and b/Logic/xor3/schematic/thumbnail_128x128.png differ diff --git a/Logic/xor3/symbol/master.tag b/Logic/xor3/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/Logic/xor3/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/Logic/xor3/symbol/symbol.oa b/Logic/xor3/symbol/symbol.oa new file mode 100644 index 00000000..b6d2eaaa Binary files /dev/null and b/Logic/xor3/symbol/symbol.oa differ diff --git a/Logic/xor3/symbol/thumbnail_128x128.png b/Logic/xor3/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..d172010a Binary files /dev/null and b/Logic/xor3/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/INVX1_LL/data.dm b/TIGFET10nm/INVX1_LL/data.dm new file mode 100644 index 00000000..759ae034 Binary files /dev/null and b/TIGFET10nm/INVX1_LL/data.dm differ diff --git a/TIGFET10nm/INVX1_LL/layout/data.dm b/TIGFET10nm/INVX1_LL/layout/data.dm new file mode 100644 index 00000000..16d3958b Binary files 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a/TIGFET10nm/INVX1_LL/schematic/master.tag b/TIGFET10nm/INVX1_LL/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/TIGFET10nm/INVX1_LL/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/TIGFET10nm/INVX1_LL/schematic/sch.oa b/TIGFET10nm/INVX1_LL/schematic/sch.oa new file mode 100644 index 00000000..715b653a Binary files /dev/null and b/TIGFET10nm/INVX1_LL/schematic/sch.oa differ diff --git a/TIGFET10nm/INVX1_LL/schematic/thumbnail_128x128.png b/TIGFET10nm/INVX1_LL/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..5841d835 Binary files /dev/null and b/TIGFET10nm/INVX1_LL/schematic/thumbnail_128x128.png differ diff --git a/TIGFET10nm/INVX1_LL/symbol/master.tag b/TIGFET10nm/INVX1_LL/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/INVX1_LL/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/INVX1_LL/symbol/symbol.oa b/TIGFET10nm/INVX1_LL/symbol/symbol.oa new file mode 100644 index 00000000..8011fdd6 Binary files /dev/null and b/TIGFET10nm/INVX1_LL/symbol/symbol.oa differ diff --git a/TIGFET10nm/INVX1_LL/symbol/thumbnail_128x128.png b/TIGFET10nm/INVX1_LL/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..7030303e Binary files /dev/null and b/TIGFET10nm/INVX1_LL/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_3GT/layout/layout.oa b/TIGFET10nm/TIGFET_3GT/layout/layout.oa index e4d6bc0c..83ee8594 100644 Binary files a/TIGFET10nm/TIGFET_3GT/layout/layout.oa and b/TIGFET10nm/TIGFET_3GT/layout/layout.oa differ diff --git a/TIGFET10nm/TIGFET_3GT/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_3GT/layout/thumbnail_128x128.png index 0392f248..20e2e88c 100644 Binary files a/TIGFET10nm/TIGFET_3GT/layout/thumbnail_128x128.png and b/TIGFET10nm/TIGFET_3GT/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_3GT_ALT/auCdl/master.tag b/TIGFET10nm/TIGFET_3GT_ALT/auCdl/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_3GT_ALT/auCdl/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_3GT_ALT/auCdl/symbol.oa b/TIGFET10nm/TIGFET_3GT_ALT/auCdl/symbol.oa new file mode 100644 index 00000000..adba1676 Binary files /dev/null and b/TIGFET10nm/TIGFET_3GT_ALT/auCdl/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_3GT_ALT/auCdl/thumbnail_128x128.png b/TIGFET10nm/TIGFET_3GT_ALT/auCdl/thumbnail_128x128.png new file mode 100644 index 00000000..84b64919 Binary files /dev/null and b/TIGFET10nm/TIGFET_3GT_ALT/auCdl/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_3GT_ALT/auLvs/master.tag b/TIGFET10nm/TIGFET_3GT_ALT/auLvs/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_3GT_ALT/auLvs/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_3GT_ALT/auLvs/symbol.oa b/TIGFET10nm/TIGFET_3GT_ALT/auLvs/symbol.oa new file mode 100644 index 00000000..06ae55f5 Binary files /dev/null and b/TIGFET10nm/TIGFET_3GT_ALT/auLvs/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_3GT_ALT/auLvs/thumbnail_128x128.png b/TIGFET10nm/TIGFET_3GT_ALT/auLvs/thumbnail_128x128.png new file mode 100644 index 00000000..84b64919 Binary files /dev/null and b/TIGFET10nm/TIGFET_3GT_ALT/auLvs/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_3GT_ALT/data.dm b/TIGFET10nm/TIGFET_3GT_ALT/data.dm new file mode 100644 index 00000000..e6d68a20 Binary files /dev/null and b/TIGFET10nm/TIGFET_3GT_ALT/data.dm differ diff --git a/TIGFET10nm/TIGFET_3GT_ALT/layout/layout.oa b/TIGFET10nm/TIGFET_3GT_ALT/layout/layout.oa new file mode 100644 index 00000000..124a6a17 Binary files /dev/null and b/TIGFET10nm/TIGFET_3GT_ALT/layout/layout.oa differ diff --git a/TIGFET10nm/TIGFET_3GT_ALT/layout/master.tag b/TIGFET10nm/TIGFET_3GT_ALT/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/TIGFET10nm/TIGFET_3GT_ALT/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/TIGFET10nm/TIGFET_3GT_ALT/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_3GT_ALT/layout/thumbnail_128x128.png new file mode 100644 index 00000000..8169ae8f Binary files /dev/null and b/TIGFET10nm/TIGFET_3GT_ALT/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_3GT_ALT/symbol/master.tag b/TIGFET10nm/TIGFET_3GT_ALT/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_3GT_ALT/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_3GT_ALT/symbol/symbol.oa b/TIGFET10nm/TIGFET_3GT_ALT/symbol/symbol.oa new file mode 100644 index 00000000..658a2aed Binary files /dev/null and b/TIGFET10nm/TIGFET_3GT_ALT/symbol/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_3GT_ALT/symbol/thumbnail_128x128.png b/TIGFET10nm/TIGFET_3GT_ALT/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..84b64919 Binary files /dev/null and b/TIGFET10nm/TIGFET_3GT_ALT/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_3GT_ALT/veriloga/data.dm b/TIGFET10nm/TIGFET_3GT_ALT/veriloga/data.dm new file mode 100644 index 00000000..02845c06 Binary files /dev/null and b/TIGFET10nm/TIGFET_3GT_ALT/veriloga/data.dm differ diff --git a/TIGFET10nm/TIGFET_3GT_ALT/veriloga/master.tag b/TIGFET10nm/TIGFET_3GT_ALT/veriloga/master.tag new file mode 100644 index 00000000..22b17e0c --- /dev/null +++ b/TIGFET10nm/TIGFET_3GT_ALT/veriloga/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +veriloga.va diff --git a/TIGFET10nm/TIGFET_3GT_ALT/veriloga/netlist.oa b/TIGFET10nm/TIGFET_3GT_ALT/veriloga/netlist.oa new file mode 100644 index 00000000..b60439d4 Binary files /dev/null and b/TIGFET10nm/TIGFET_3GT_ALT/veriloga/netlist.oa differ diff --git a/TIGFET10nm/TIGFET_3GT_ALT/veriloga/veriloga.va b/TIGFET10nm/TIGFET_3GT_ALT/veriloga/veriloga.va new file mode 100644 index 00000000..ba29cf13 --- /dev/null +++ b/TIGFET10nm/TIGFET_3GT_ALT/veriloga/veriloga.va @@ -0,0 +1,14 @@ +// VerilogA for NCSU_TechLib_FreePDK15, TIGFET_3GT, veriloga + +`include "constants.vams" +`include "disciplines.vams" + +module TIGFET_3GT_ALT(d,pgd,cg,pgs,s); + inout d,pgd,cg,pgs,s; + electrical d,pgd,cg,pgs,s; + parameter integer n = 4; + + analog begin + I(d,s) <+ n * $table_model(V(pgd,s),V(pgs,s),V(cg,s),V(d,s), "Id_NW10n4G.tbl","1,1,1,1"); + end +endmodule diff --git a/TIGFET10nm/TIGFET_GROUPED_2T/data.dm b/TIGFET10nm/TIGFET_GROUPED_2T/data.dm new file mode 100644 index 00000000..8b9ed0f6 Binary files /dev/null and b/TIGFET10nm/TIGFET_GROUPED_2T/data.dm differ diff --git a/TIGFET10nm/TIGFET_GROUPED_2T/layout/data.dm b/TIGFET10nm/TIGFET_GROUPED_2T/layout/data.dm new file mode 100644 index 00000000..ce4e9ccf Binary files /dev/null and b/TIGFET10nm/TIGFET_GROUPED_2T/layout/data.dm differ diff --git a/TIGFET10nm/TIGFET_GROUPED_2T/layout/layout.oa b/TIGFET10nm/TIGFET_GROUPED_2T/layout/layout.oa new file mode 100644 index 00000000..830d375c Binary files /dev/null and b/TIGFET10nm/TIGFET_GROUPED_2T/layout/layout.oa differ diff --git a/TIGFET10nm/TIGFET_GROUPED_2T/layout/master.tag b/TIGFET10nm/TIGFET_GROUPED_2T/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/TIGFET10nm/TIGFET_GROUPED_2T/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/TIGFET10nm/TIGFET_GROUPED_2T/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_GROUPED_2T/layout/thumbnail_128x128.png new file mode 100644 index 00000000..5f5488ac Binary files /dev/null and b/TIGFET10nm/TIGFET_GROUPED_2T/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_GROUPED_2T/schematic/data.dm b/TIGFET10nm/TIGFET_GROUPED_2T/schematic/data.dm new file mode 100644 index 00000000..a0bf9655 Binary files /dev/null and b/TIGFET10nm/TIGFET_GROUPED_2T/schematic/data.dm differ diff --git a/TIGFET10nm/TIGFET_GROUPED_2T/schematic/master.tag b/TIGFET10nm/TIGFET_GROUPED_2T/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/TIGFET10nm/TIGFET_GROUPED_2T/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/TIGFET10nm/TIGFET_GROUPED_2T/schematic/sch.oa b/TIGFET10nm/TIGFET_GROUPED_2T/schematic/sch.oa new file mode 100644 index 00000000..88dc3198 Binary files /dev/null and b/TIGFET10nm/TIGFET_GROUPED_2T/schematic/sch.oa differ diff --git a/TIGFET10nm/TIGFET_GROUPED_2T/schematic/thumbnail_128x128.png b/TIGFET10nm/TIGFET_GROUPED_2T/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..efdf1033 Binary files /dev/null and b/TIGFET10nm/TIGFET_GROUPED_2T/schematic/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_GROUPED_2T/symbol/master.tag b/TIGFET10nm/TIGFET_GROUPED_2T/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_GROUPED_2T/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_GROUPED_2T/symbol/symbol.oa b/TIGFET10nm/TIGFET_GROUPED_2T/symbol/symbol.oa new file mode 100644 index 00000000..cf006de6 Binary files /dev/null and b/TIGFET10nm/TIGFET_GROUPED_2T/symbol/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_GROUPED_2T/symbol/thumbnail_128x128.png b/TIGFET10nm/TIGFET_GROUPED_2T/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..6350c434 Binary files /dev/null and b/TIGFET10nm/TIGFET_GROUPED_2T/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/auCdl/master.tag b/TIGFET10nm/TIGFET_PCELL_SP15CP15/auCdl/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_PCELL_SP15CP15/auCdl/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/auCdl/symbol.oa b/TIGFET10nm/TIGFET_PCELL_SP15CP15/auCdl/symbol.oa new file mode 100644 index 00000000..7ac200eb Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/auCdl/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/auCdl/thumbnail_128x128.png b/TIGFET10nm/TIGFET_PCELL_SP15CP15/auCdl/thumbnail_128x128.png new file mode 100644 index 00000000..84b64919 Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/auCdl/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/auLvs/master.tag b/TIGFET10nm/TIGFET_PCELL_SP15CP15/auLvs/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_PCELL_SP15CP15/auLvs/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/auLvs/symbol.oa b/TIGFET10nm/TIGFET_PCELL_SP15CP15/auLvs/symbol.oa new file mode 100644 index 00000000..0d96a756 Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/auLvs/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/auLvs/thumbnail_128x128.png b/TIGFET10nm/TIGFET_PCELL_SP15CP15/auLvs/thumbnail_128x128.png new file mode 100644 index 00000000..84b64919 Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/auLvs/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/data.dm b/TIGFET10nm/TIGFET_PCELL_SP15CP15/data.dm new file mode 100644 index 00000000..ce3d8c04 Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/data.dm differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/hspiceD/data.dm b/TIGFET10nm/TIGFET_PCELL_SP15CP15/hspiceD/data.dm new file mode 100644 index 00000000..660f76a2 Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/hspiceD/data.dm differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/hspiceD/master.tag b/TIGFET10nm/TIGFET_PCELL_SP15CP15/hspiceD/master.tag new file mode 100644 index 00000000..902327eb --- /dev/null +++ b/TIGFET10nm/TIGFET_PCELL_SP15CP15/hspiceD/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +spice.spc diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/hspiceD/netlist.oa b/TIGFET10nm/TIGFET_PCELL_SP15CP15/hspiceD/netlist.oa new file mode 100644 index 00000000..f077e362 Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/hspiceD/netlist.oa differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/hspiceD/spice.spc b/TIGFET10nm/TIGFET_PCELL_SP15CP15/hspiceD/spice.spc new file mode 100644 index 00000000..874d38b2 --- /dev/null +++ b/TIGFET10nm/TIGFET_PCELL_SP15CP15/hspiceD/spice.spc @@ -0,0 +1,8 @@ +* "spice" description for "TIGFET10nm", "TIGFET_PCELL_SP15CP15", "hSpiceD" + + +simulator lang=spice + +.SUBCKT TIGFET_PCELL_SP15CP15 d pgd cg pgs s Cch_pg = 2.0763e-17 Cch_cg = 2.0763e-17 Cof_spg = 6.9637e-18 Cof_cgpg = 3.1661e-18 Cside_spgs = 5.3932e-18 Cside_scg = 3.4529e-18 Cside_spgd = 2.9376e-18 Cside_cgpg = 4.5154e-18 Cside_pgpg = 3.2916e-18 Cif_spgs = 3.4267e-18 Cif_scg = 1.4277e-18 Cif_spgd = 8.887e-19 + +.ENDS \ No newline at end of file diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/layout/data.dm b/TIGFET10nm/TIGFET_PCELL_SP15CP15/layout/data.dm new file mode 100644 index 00000000..27598eab Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/layout/data.dm differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/layout/layout.oa b/TIGFET10nm/TIGFET_PCELL_SP15CP15/layout/layout.oa new file mode 100644 index 00000000..af05774f Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/layout/layout.oa differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/layout/master.tag b/TIGFET10nm/TIGFET_PCELL_SP15CP15/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/TIGFET10nm/TIGFET_PCELL_SP15CP15/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_PCELL_SP15CP15/layout/thumbnail_128x128.png new file mode 100644 index 00000000..416cc06f Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/symbol/master.tag b/TIGFET10nm/TIGFET_PCELL_SP15CP15/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_PCELL_SP15CP15/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/symbol/symbol.oa b/TIGFET10nm/TIGFET_PCELL_SP15CP15/symbol/symbol.oa new file mode 100644 index 00000000..609d4237 Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/symbol/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/symbol/thumbnail_128x128.png b/TIGFET10nm/TIGFET_PCELL_SP15CP15/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..3fcf7697 Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/veriloga/data.dm b/TIGFET10nm/TIGFET_PCELL_SP15CP15/veriloga/data.dm new file mode 100644 index 00000000..02845c06 Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/veriloga/data.dm differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/veriloga/master.tag b/TIGFET10nm/TIGFET_PCELL_SP15CP15/veriloga/master.tag new file mode 100644 index 00000000..22b17e0c --- /dev/null +++ b/TIGFET10nm/TIGFET_PCELL_SP15CP15/veriloga/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +veriloga.va diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/veriloga/netlist.oa b/TIGFET10nm/TIGFET_PCELL_SP15CP15/veriloga/netlist.oa new file mode 100644 index 00000000..c81211d1 Binary files /dev/null and b/TIGFET10nm/TIGFET_PCELL_SP15CP15/veriloga/netlist.oa differ diff --git a/TIGFET10nm/TIGFET_PCELL_SP15CP15/veriloga/veriloga.va b/TIGFET10nm/TIGFET_PCELL_SP15CP15/veriloga/veriloga.va new file mode 100644 index 00000000..a0d0a32b --- /dev/null +++ b/TIGFET10nm/TIGFET_PCELL_SP15CP15/veriloga/veriloga.va @@ -0,0 +1,77 @@ +// VerilogA for NCSU_TechLib_FreePDK15, TIGFET_3GT, veriloga + +// ---------------------------------------------------------------------------- +// +// Filename: tigfet_lib.va +// Date: 2021-08-04 +// Version: 1.0 +// +// Description: +// Silicon-nanowire TIGFET model. The I(d,s) current table model is based on +// TCAD simulations done for the TIGFET High-Performance (HP) mode and one +// silicon-nanowire (SiNW). In DC analysis, this table model define the leakage +// power of TIGFET. Then, the model timing and energy accuracy is improved with +// the parasitic capacitance model, calibrated by COMSOL simulations, as +// presented in JEDS'21 paper ("Parasitic Capacitance Analysis of TIGFET"). +// +// Actual model limitations: +// - Stacked SiNW is fixed to 1 (nw=1), w.r.t TCAD simulations +// - Only the HP mode is supported, w.r.t. TCAD simulations +// - Supply voltage VDD is configured at 0.7V +// +// ---------------------------------------------------------------------------- +// +// Example of model parameters: +// - Ls = 15 nm (source length = drain length) +// - Lg = 15 nm (gate length) +// - Hg = 10 nm (gate height) +// - Lsp = 15 nm (spacer length CG-PGS, CG-PGD) +// - Lspk = 7.5 nm (spacer length PGS-S, PGD-D) +// - r = 4 nm (SiNW rayon) +// - tox = 6.92 nm (HfO2_thickness) +// - Flow: SiO2 spacer, HfO2 gate oxide +// +// CchPG CchCG CofSPG CofCGPG CsideSPGS CsideSCG CsideSPGD CsideCGPG CsidePGPG CifPGS CifCG CifPGD +// 2.0773E-17 2.0773E-17 7.3147E-18 3.1676E-18 5.4909E-18 3.4560E-18 2.9791E-18 4.4738E-18 3.2964E-18 3.4268E-18 1.5846E-18 9.7927E-19 [COMSOL results] +// 2.0763e-17 2.0763e-17 7.3028e-18 3.1661e-18 5.4895e-18 3.4659e-18 2.9434e-18 4.5154e-18 3.2916e-18 3.4267e-18 1.4277e-18 8.8870e-19 [Parasitic model] +// +// ---------------------------------------------------------------------------- + +`include "disciplines.vams" + +// Module name: TIGFET_SINW_HP_SP15 +// Model parameters: +// - Lg = 15 nm +// - Lsp = 15 nm +// - Lspk = 8 nm +module TIGFET_PCELL_SP15CP15(d, pgd, cg, pgs, s); + inout d, pgd, cg, pgs, s; + electrical d, pgd, cg, pgs, s; + + parameter real Cch_pg = 2.0763e-17; + parameter real Cch_cg = 2.0763e-17; + parameter real Cof_spg = 6.9637e-18; + parameter real Cof_cgpg = 3.1661e-18; + parameter real Cside_spgs = 5.3932e-18; + parameter real Cside_scg = 3.4529e-18; + parameter real Cside_spgd = 2.9376e-18; + parameter real Cside_cgpg = 4.5154e-18; + parameter real Cside_pgpg = 3.2916e-18; + parameter real Cif_spgs = 3.4267e-18; + parameter real Cif_scg = 1.4277e-18; + parameter real Cif_spgd = 8.8870e-19; + + analog begin + I(d,s) <+ $table_model(V(pgd,s),V(pgs,s),V(cg,s),V(d,s),"Id_NW10n4G.tbl","1,1,1,1"); + I(s,pgs) <+ ddt(V(s,pgs)) * (Cside_spgs + Cif_spgs + Cch_pg + Cof_spg); // Cs_pgs + I(d,pgd) <+ ddt(V(d,pgd)) * (Cside_spgs + Cif_spgs + Cch_pg + Cof_spg); // Cd_pgd + I(s,cg) <+ ddt(V(s,cg)) * (Cside_scg + Cif_scg + Cch_cg); // Cs_cg + I(d,cg) <+ ddt(V(d,cg)) * (Cside_scg + Cif_scg + Cch_cg); // Cd_cg + I(s,pgd) <+ ddt(V(s,pgd)) * (Cside_spgd + Cif_spgd + Cch_pg); // Cs_pgd + I(d,pgs) <+ ddt(V(d,pgs)) * (Cside_spgd + Cif_spgd + Cch_pg); // Cd_pgs + I(cg,pgs) <+ ddt(V(cg,pgs)) * (Cside_cgpg + Cof_cgpg); // Ccg_pgs + I(cg,pgd) <+ ddt(V(cg,pgd)) * (Cside_cgpg + Cof_cgpg); // Ccg_pgs + I(pgs,pgd) <+ ddt(V(pgs,pgd)) * (Cside_pgpg); // Cpg_pg + end +endmodule + diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15/data.dm b/TIGFET10nm/TIGFET_TILEG1_SP15CP15/data.dm new file mode 100644 index 00000000..1656af73 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG1_SP15CP15/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/data.dm b/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/data.dm new file mode 100644 index 00000000..b8592d07 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/layout.oa b/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/layout.oa new file mode 100644 index 00000000..2cacdd7e Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/layout.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/layout.oa- b/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/layout.oa- new file mode 100644 index 00000000..4321fa7b Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/layout.oa- differ diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/master.tag b/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG1_SP15CP15/layout/thumbnail_128x128.png new file mode 100644 index 00000000..ce73d6c1 Binary files /dev/null and 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--- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/layout/thumbnail_128x128.png new file mode 100644 index 00000000..da29a96f Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/schematic/data.dm b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/schematic/data.dm new file mode 100644 index 00000000..31f0f3d9 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/schematic/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/schematic/master.tag b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/schematic/sch.oa b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/schematic/sch.oa new file mode 100644 index 00000000..c8377778 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/schematic/sch.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/schematic/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..6bf7b717 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/schematic/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/symbol/master.tag b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_TILEG1_SP15CP15_INV/symbol/symbol.oa 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a/TIGFET10nm/TIGFET_TILEG2_SP15CP15/layout/layout.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/layout/layout.oa new file mode 100644 index 00000000..32f8988d Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/layout/layout.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15/layout/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/layout/thumbnail_128x128.png new file mode 100644 index 00000000..d22d3d36 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15/schematic/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/schematic/data.dm new file mode 100644 index 00000000..b88ea3f3 Binary files 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b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15/symbol/symbol.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/symbol/symbol.oa new file mode 100644 index 00000000..469297de Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/symbol/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15/symbol/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..3fa61157 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/data.dm new file mode 100644 index 00000000..b0c3da94 Binary files /dev/null and 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a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/layout/thumbnail_128x128.png new file mode 100644 index 00000000..fda0c997 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/schematic/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/schematic/data.dm new file mode 100644 index 00000000..48f9e093 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/schematic/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/schematic/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/schematic/sch.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/schematic/sch.oa new file mode 100644 index 00000000..4509debe Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/schematic/sch.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/schematic/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..8b411cce Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/schematic/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/symbol/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/symbol/symbol.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/symbol/symbol.oa new file mode 100644 index 00000000..fa3f50e3 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/symbol/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/symbol/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..9e25122e Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_Full_Adder/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/data.dm new file mode 100644 index 00000000..16fbf0c7 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/layout/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/layout/data.dm new file mode 100644 index 00000000..808c1178 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/layout/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/layout/layout.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/layout/layout.oa new file mode 100644 index 00000000..34b85a77 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/layout/layout.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/layout/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/layout/thumbnail_128x128.png new file mode 100644 index 00000000..42cd3dcf Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/schematic/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/schematic/data.dm new file mode 100644 index 00000000..0fd5f732 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/schematic/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/schematic/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/schematic/sch.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/schematic/sch.oa new file mode 100644 index 00000000..2439921e Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/schematic/sch.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/schematic/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..388581ab Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/schematic/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/symbol/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/symbol/symbol.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/symbol/symbol.oa new file mode 100644 index 00000000..7e7df74e Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/symbol/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/symbol/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..f92baf5c Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_INV/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/data.dm new file mode 100644 index 00000000..ecb79c90 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/layout/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/layout/data.dm new file mode 100644 index 00000000..f5070db0 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/layout/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/layout/layout.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/layout/layout.oa new file mode 100644 index 00000000..69e9fdf8 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/layout/layout.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/layout/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/layout/thumbnail_128x128.png new file mode 100644 index 00000000..8abd093b Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/schematic/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/schematic/data.dm new file mode 100644 index 00000000..a6eef579 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/schematic/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/schematic/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/schematic/sch.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/schematic/sch.oa new file mode 100644 index 00000000..bedefeca Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/schematic/sch.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/schematic/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..ca35810e Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/schematic/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/symbol/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/symbol/symbol.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/symbol/symbol.oa new file mode 100644 index 00000000..0fab7845 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/symbol/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/symbol/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..e0e58e8e Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_Cout/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/data.dm new file mode 100644 index 00000000..87458095 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/layout/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/layout/data.dm new file mode 100644 index 00000000..f5070db0 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/layout/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/layout/layout.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/layout/layout.oa new file mode 100644 index 00000000..15144928 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/layout/layout.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/layout/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/layout/thumbnail_128x128.png new file mode 100644 index 00000000..6a72edf8 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/schematic/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/schematic/data.dm new file mode 100644 index 00000000..a6eef579 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/schematic/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/schematic/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/schematic/sch.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/schematic/sch.oa new file mode 100644 index 00000000..9c080abd Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/schematic/sch.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/schematic/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..dd5c24fa Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/schematic/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/symbol/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/symbol/symbol.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/symbol/symbol.oa new file mode 100644 index 00000000..c570f75a Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/symbol/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/symbol/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..f059d224 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_MAJ_CoutBAR/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/data.dm new file mode 100644 index 00000000..75821295 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/layout/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/layout/data.dm new file mode 100644 index 00000000..e1fa6893 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/layout/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/layout/layout.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/layout/layout.oa new file mode 100644 index 00000000..241c7235 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/layout/layout.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/layout/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/layout/thumbnail_128x128.png new file mode 100644 index 00000000..164c7f25 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/schematic/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/schematic/data.dm new file mode 100644 index 00000000..94483679 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/schematic/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/schematic/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/schematic/sch.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/schematic/sch.oa new file mode 100644 index 00000000..7d523ea2 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/schematic/sch.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/schematic/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..f5279b76 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/schematic/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/symbol/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/symbol/symbol.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/symbol/symbol.oa new file mode 100644 index 00000000..92657f2d Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/symbol/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/symbol/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..03c353a5 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NOR2/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/data.dm new file mode 100644 index 00000000..27f01fca Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/layout/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/layout/data.dm new file mode 100644 index 00000000..c7e69c09 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/layout/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/layout/layout.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/layout/layout.oa new file mode 100644 index 00000000..4011af89 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/layout/layout.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/layout/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/layout/thumbnail_128x128.png new file mode 100644 index 00000000..65915015 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/schematic/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/schematic/data.dm new file mode 100644 index 00000000..b88ea3f3 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/schematic/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/schematic/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/schematic/sch.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/schematic/sch.oa new file mode 100644 index 00000000..d3104aa1 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/schematic/sch.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/schematic/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..a7c2310d Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/schematic/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/symbol/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/symbol/symbol.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/symbol/symbol.oa new file mode 100644 index 00000000..56b6e71b Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/symbol/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/symbol/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..cff89cc4 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_NoConnection/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/data.dm new file mode 100644 index 00000000..508f67d0 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/layout/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/layout/data.dm new file mode 100644 index 00000000..f5070db0 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/layout/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/layout/layout.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/layout/layout.oa new file mode 100644 index 00000000..75466a07 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/layout/layout.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/layout/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/layout/master.tag new file mode 100644 index 00000000..431d8f04 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/layout/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/layout/thumbnail_128x128.png new file mode 100644 index 00000000..10083b99 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/layout/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/schematic/data.dm b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/schematic/data.dm new file mode 100644 index 00000000..a6eef579 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/schematic/data.dm differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/schematic/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/schematic/master.tag new file mode 100644 index 00000000..26be1bef --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/schematic/sch.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/schematic/sch.oa new file mode 100644 index 00000000..dca80235 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/schematic/sch.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/schematic/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/schematic/thumbnail_128x128.png new file mode 100644 index 00000000..0f80a04f Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/schematic/thumbnail_128x128.png differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/symbol/master.tag b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/symbol/master.tag new file mode 100644 index 00000000..e1024da0 --- /dev/null +++ b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/symbol/symbol.oa b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/symbol/symbol.oa new file mode 100644 index 00000000..6c3a2703 Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/symbol/symbol.oa differ diff --git a/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/symbol/thumbnail_128x128.png b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/symbol/thumbnail_128x128.png new file mode 100644 index 00000000..3cef00fb Binary files /dev/null and b/TIGFET10nm/TIGFET_TILEG2_SP15CP15_XOR/symbol/thumbnail_128x128.png differ diff --git a/TIGFET10nm/data.dm b/TIGFET10nm/data.dm new file mode 100644 index 00000000..80f18cd6 Binary files /dev/null and b/TIGFET10nm/data.dm differ diff --git a/calibre/calibreDRC.rul b/calibre/calibreDRC.rul index b631dc91..651515fe 100644 --- a/calibre/calibreDRC.rul +++ b/calibre/calibreDRC.rul @@ -124,7 +124,7 @@ SDC_OVERLAP = SDC AND IL //////////////////////////////////////////////////////////////////////////////////// CONNECT SDC IL CONNECT GC IL -CONNECT Il M1 by VM0 +CONNECT IL M1 by VM0 CONNECT M1 M2 by VM1 CONNECT M2 M3 by VM2 CONNECT M3 M4 by VM3 @@ -146,9 +146,9 @@ CONNECT M9 M10 by VM9 // ________RULE_ACT001 RULE_ACT001{ @ RULE_ACT001 - @ Minimum vertical width of ACT layer is 48nm + @ Minimum vertical width of ACT layer is 128nm ACT_HORIZONTAL_EDGES = ACT ANGLE == 0 - INTERNAL ACT_HORIZONTAL_EDGES < 0.048 + INTERNAL ACT_HORIZONTAL_EDGES < 0.128 } // ________RULE_ACT002 @@ -185,33 +185,31 @@ RULE_ACT002{ // ________ RULE_ACT003 RULE_ACT003{ @ RULE_ACT003 - @ Minimum vertical spacing of ACT is 62nm + @ Minimum vertical spacing of ACT is 80nm ACT_HORIZONTAL_EDGES = ACT ANGLE == 0 - EXTERNAL ACT_HORIZONTAL_EDGES < 0.062 + EXTERNAL ACT_HORIZONTAL_EDGES < 0.080 } //________ RULE_ACT004 RULE_ACT004{ @ RULE_ACT004 - @ Minimum horizontal width of ACT is 96nm + @ Minimum horizontal width of ACT is 166nm ACT_VERTICAL_EDGES = ACT ANGLE == 90 - INTERNAL ACT_VERTICAL_EDGES < 0.096 + INTERNAL ACT_VERTICAL_EDGES < 0.166 } //________ RULE_ACT005 RULE_ACT005{ @ RULE_ACT005 - @ Horizontal spacing of ACT must be 32nm, 96nm or >= 160nm + @ Horizontal spacing of ACT must be 80nm ACT_VERTICAL_EDGES = ACT ANGLE == 90 - EXTERNAL ACT_VERTICAL_EDGES > 0 < 0.032 OPPOSITE - EXTERNAL ACT_VERTICAL_EDGES > 0.032 < 0.096 OPPOSITE - EXTERNAL ACT_VERTICAL_EDGES > 0.096 < 0.16 OPPOSITE + EXTERNAL ACT_VERTICAL_EDGES < 0.080 } //________ RULE_ACT006 RULE_ACT006{ @ RULE_ACT006 - @ Minimum notch of ACT is 112nm - EXTERNAL ACT < 0.112 NOTCH + @ Minimum notch of ACT is 166nm + EXTERNAL ACT < 0.166 NOTCH } //________ RULE_ACT008A @@ -238,17 +236,16 @@ GATE_horizontal_edges = GATE ANGLE ==0 //________ RULE_GATE001 RULE_GATE001{ @ RULE_GATE001 - @ Exact horizontal width of GATE is 20, 16 or 14 nm - INTERNAL GATE_vertical_edges < 0.014 - INTERNAL GATE_vertical_edges > 0.014 < 0.016 - INTERNAL GATE_vertical_edges > 0.016 < 0.020 - INTERNAL GATE_vertical_edges > 0.020 < 0.200 + @ Exact horizontal width of GATE is 20nm + INTERNAL GATE_vertical_edges < 0.020 + + } //________ RULE_GATE002 RULE_GATE002{ @ RULE_GATE002 - @ Min horizontal pitch of GATE is 34 nm + @ Horizontal pitch of GATE is 35 nm //select vertical edge pairs on same polygons, constraint is 1 to include all edge pairs x = INT GATE_vertical_edges < 1 //derive centerlines between edge pairs @@ -256,8 +253,8 @@ RULE_GATE002{ //expand the centerlines by a very small value to form very thin polygons y_copy = EXPAND EDGE y INSIDE BY 0.0001 y_copy_vertical_edge = y_copy ANGLE == 90 - //output gate polygons that have a horizontal pitch less than 128nm - EXT y_copy_vertical_edge < 0.033 OPPOSITE + //output gate polygons that have a horizontal pitch less than 35nm + EXT y_copy_vertical_edge < 0.035 OPPOSITE } //////////////////////////////////////////////////////////////////////////////////// @@ -272,8 +269,8 @@ RULE_GATE004{ //________ RULE_GATE005 RULE_GATE005{ @ RULE_GATE005 - @ Minimum extension of ACT past GATE is 38nm - ENCLOSURE GATE ACT < 0.038 + @ Minimum extension of ACT past GATE is 15nm + ENCLOSURE GATE ACT < 0.015 } //////////////////////////////////////////////////////////////////////////////////// @@ -288,8 +285,8 @@ RULE_GATE006{ // ________ RULE_GATE007A RULE_GATE007A{ @ RULE_GATE007A -@ Minimum length of Gate 200nm -LENGTH GATE_vertical_edges < 0.200 +@ Minimum length of Gate 168nm +LENGTH GATE_vertical_edges < 0.168 } //////////////////////////////////////////////////////////////////////////////////// @@ -330,9 +327,9 @@ RULE_SDC004{ // ______RULE_SDC005 RULE_SDC005{ @ RULE_SDC005 - @ Minimum Vertical length of SDC is 58nm + @ Minimum Vertical length of SDC is 128nm SDC_HORIZONTAL_EDGES = SDC ANGLE == 0 - INTERNAL SDC_HORIZONTAL_EDGES < 0.058 + INTERNAL SDC_HORIZONTAL_EDGES < 0.128 } //////////////////////////////////////////////////////////////////////////////////// @@ -375,8 +372,8 @@ RULE_IL002{ //////////////////////////////////////////////////////////////////////////////////// RULE_IL003A{ @ RULE_IL003A - @ Minimum spacing between IL and GATE is 2nm - EXTERNAL IL GATE < 0.001 + @ Minimum spacing between IL and GATE is 10nm + EXTERNAL IL GATE < 0.010 } //////////////////////////////////////////////////////////////////////////////////// @@ -389,17 +386,17 @@ RULE_IL004{ //////////////////////////////////////////////////////////////////////////////////// RULE_IL005{ @ RULE_IL005 - @ Minimum Vertical overlap of SDC and IL is 6nm + @ Minimum Vertical overlap of SDC and IL is 58nm OVERLAP_HORIZONTAL_EDGES = SDC_OVERLAP ANGLE == 0 - INT OVERLAP_HORIZONTAL_EDGES < 0.006 + INT OVERLAP_HORIZONTAL_EDGES < 0.058 } //////////////////////////////////////////////////////////////////////////////////// RULE_IL006{ @ RULE_IL006 - @ Vertical length of IL is 24nm + @ Vertical length of IL is 68nm IL_HORIZ_EDGES = IL ANGLE == 0 - INTERNAL IL_HORIZ_EDGES < 0.024 + INTERNAL IL_HORIZ_EDGES < 0.068 } //////////////////////////////////////////////////////////////////////////////////// RULE_IL007{ @@ -450,9 +447,9 @@ RULE_GC002{ //////////////////////////////////////////////////////////////////////////////////// RULE_GC003{ @ RULE_GC003 - @ Minimum vertical spacing of GC is 32nm + @ Minimum vertical spacing of GC is 40nm ALL_HORIZ_EDGES = ANGLE GC == 0 - EXTERNAL ALL_HORIZ_EDGES < 0.032 + EXTERNAL ALL_HORIZ_EDGES < 0.040 } //////////////////////////////////////////////////////////////////////////////////// RULE_GC004{ @@ -478,31 +475,31 @@ RULE_GC006{ //////////////////////////////////////////////////////////////////////////////////// RULE_GC007{ @ RULE_GC007 - @ Minimum horizontal space of GC to IL is 8nm + @ Minimum horizontal space of GC to IL is 4nm GC_VERTICAL_EDGES = GC ANGLE == 90 - EXT GC_VERTICAL_EDGES IL < 0.008 NOT CONNECTED + EXT GC_VERTICAL_EDGES IL < 0.004 NOT CONNECTED } //////////////////////////////////////////////////////////////////////////////////// RULE_GC008{ @ RULE_GC008 - @ Minimum vertical space of GC to IL is 5nm + @ Minimum vertical space of GC to IL is 4nm GC_HORIZONTAL_EDGES = GC ANGLE == 0 EXT GC_HORIZONTAL_EDGES IL < 0.005 } //////////////////////////////////////////////////////////////////////////////////// RULE_GC009A{ @ RULE_GC009A - @ Minimum horizontal space of SDC to GATE is 9nm + @ Minimum horizontal space of SDC to GATE is 10nm SDC_VERTICAL_EDGES = SDC ANGLE == 90 - EXT SDC_VERTICAL_EDGES GATE < 0.008 + EXT SDC_VERTICAL_EDGES GATE < 0.010 } //////////////////////////////////////////////////////////////////////////////////// RULE_GC010{ @ RULE_GC010 - @ Minimum horizontal overlap of GC and IL is 2nm + @ Minimum horizontal overlap of GC and IL is 24nm IL_VERTICAL_EDGES = IL ANGLE == 90 - ENC IL_VERTICAL_EDGES GC < 0.002 CONNECTED + ENC IL_VERTICAL_EDGES GC < 0.024 CONNECTED } //////////////////////////////////////////////////////////////////////////////////// RULE_GC011{ diff --git a/calibre/calibreLVS.rul b/calibre/calibreLVS.rul index d2fee719..5af32ac0 100644 --- a/calibre/calibreLVS.rul +++ b/calibre/calibreLVS.rul @@ -1,5 +1,3 @@ - - LVS POWER NAME VDD LVS GROUND NAME VSS LVS REDUCE PARALLEL MOS yes diff --git a/cds.lib b/cds.lib new file mode 100644 index 00000000..fe815ad9 --- /dev/null +++ b/cds.lib @@ -0,0 +1,5 @@ +DEFINE basic $CDSHOME/tools/dfII/etc/cdslib/basic +DEFINE analogLib $CDSHOME/tools/dfII/etc/cdslib/artist/analogLib +DEFINE TIGFET10nm $PDK_DIR/TIGFET10nm +DEFINE TIGFET10nm_IMAGE /research/ece/lnis/USERS/enginger/TIGFETS/TIGFET-10nm-PDK/TIGFET10nm_IMAGE +DEFINE TIGFET10nm_TEST /research/ece/lnis/USERS/enginger/TIGFETS/TIGFET-10nm-PDK/TIGFET10nm_TEST diff --git a/cdslib/setup/cds.lib b/cdslib/setup/cds.lib deleted file mode 100644 index f5067b07..00000000 --- a/cdslib/setup/cds.lib +++ /dev/null @@ -1,3 +0,0 @@ -DEFINE basic $CDSHOME/tools/dfII/etc/cdslib/basic -DEFINE analogLib $CDSHOME/tools/dfII/etc/cdslib/artist/analogLib -DEFINE TIGFET10nm $PDK_DIR/TIGFET10nm diff --git a/cdslib/setup/launch_tigfet10nm.sh b/launch_tigfet10nm.sh old mode 100644 new mode 100755 similarity index 81% rename from cdslib/setup/launch_tigfet10nm.sh rename to launch_tigfet10nm.sh index fea4a0d2..85475e96 --- a/cdslib/setup/launch_tigfet10nm.sh +++ b/launch_tigfet10nm.sh @@ -9,6 +9,8 @@ setenv PDK_DIR "$PWD" setenv MGC_CALIBRE_DRC_RUNSET_FILE "./.runset.calibre.drc" setenv MGC_CALIBRE_LVS_RUNSET_FILE "./.runset.calibre.lvs" setenv MGC_CALIBRE_PEX_RUNSET_FILE "./.runset.calibre.pex" +setenv MGC_HOME $mentor_dir/aok_cal_2021.2_37.20 +set path=($path $MGC_HOME/bin) # Start Virtuoso \virtuoso &