firtool-1.62.0

What's Changed

• [FIRRTL] Enable lowersigs and passive wires by @darthscsi in #6479
• [InstancePath] Add accessors to allow ops to reference multiple targets by @nandor in #6446
• [Debug] Make paths in HGLDD files relative by @fabianschuiki in #6451
• [Debug] Add scope op by @fabianschuiki in #6454
• [CombToArith] Fix lowering of concat with single operand by @fabianschuiki in #6505
• [Arc] Partially enable reset/enable detection by @fabianschuiki in #6506
• [Arc] Add support for struct and array states by @fabianschuiki in #6508
• [ESI] Fix pycde integration tests by @teqdruid in #6514
• [Scheduling] Define problem to model operator chaining in cyclic problem. by @leothaud in #6485
• [ESI] Fix pycde integration tests by @teqdruid in #6518
• [FIRRTL] Add options and instance choices by @nandor in #6504
• [SVExtractTestCode] Privatize generated modules by @uenoku in #6519
• [FIREmitter] Bump the version to 4.0.0 by @nandor in #6522
• [FIRRTL] Add a pass to specialize instance choices by @nandor in #6507
• [FIRRTL] Add a parser for firrtl.instance_choice by @nandor in #6509
• [Debug] Add inline scope support to HGLDD emission by @fabianschuiki in #6511
• [NFC] Make CHIRRTL more normal in preparation for moving some stuff in by @darthscsi in #6521
• [FIRRTL] Add an emitter for options and instance choices by @nandor in #6520
• [HW to BTOR2] btor2 conversion pass by @dobios in #6378
• [FIRRTL] Framework for intrinsic lowering by @nandor in #6527
• [LowerToHW] Fix output port index mapping by @prithayan in #6530
• [FIRRTL] Intrinsics: Fix lifetime issues in lambda. by @dtzSiFive in #6534
• [OM] Use type replacer to handle block arguments. by @mikeurbach in #6532
• [ModuleInliner] Donot retop a HierPathOp if flattening the root by @prithayan in #6515
• [LowerSignatures] Fix potential UAF by @uenoku in #6537
• [ESI][Runtime][NFC] Minor refactor and cleanup by @teqdruid in #6539
• [ESI][Runtime] Add design hierarchy printing to esiquery by @teqdruid in #6540
• [ESI][Runtime] Add type serialization support to Python bindings by @teqdruid in #6541
• [PyCDE] Fix ESI integration tests by @teqdruid in #6542
• [PyCDE] Fix ESI service implementations by @teqdruid in #6545
• [Support][FIRRTL] Debug Cleanup by @seldridge in #6546
• [CI] Fix release asset upload job permissions, support manual runs. by @dtzSiFive in #6547
• [CI] Bump runner for windows release artifacts 2019 -> 2022. by @dtzSiFive in #6548
• [LowerSignatures] Fix instance locations by @fabianschuiki in #6550
• [CI] Add option to control whether workflow_dispatch has asserts+debug. by @dtzSiFive in #6549
• [Docs] fix typos in Dialects/ by @shuoer86 in #6555
• [FIRRTL] Update InstanceGraph on erase in LowerClasses. by @mikeurbach in #6558
• [FIRRTL] Fix the lowering of internal paths in LowerSignatures by @nandor in #6556
• [HW][Seq] Select the better name when dropping wires and casts by @nandor in #6559
• [NFC] Bump LLVM over mnemonic change by @darthscsi in #6563

New Contributors

• @leothaud made their first contribution in #6485
• @shuoer86 made their first contribution in #6555

Full Changelog: firtool-1.61.0...firtool-1.62.0

Firtool 1.59.1 Release

What's Changed

• [LowerToHW] Pass through attributes on FModuleOp by @uenoku in #6400
• [LowerToHW] Fix output port index mapping by @prithayan in #6530

Full Changelog: firtool-1.59.0...firtool-1.59.1

Firtool 1.61.0 Release

What's Changed

• [HW] Fix getPortList to avoid n^2 location gathering. by @dtzSiFive in #6469
• [firtool] Fix missing option setter by @seldridge in #6470
• [FIRRTL] Create LowerSignatures to handle module signatures. by @darthscsi in #6359
• [ESI] Function call std service by @teqdruid in #6465
• [Python] Add debug dialect bindings by @fabianschuiki in #6471
• [ESI] Add std service name to manifest by @teqdruid in #6472
• [FIRRTL][CAPI] Add the rest of setters for options by @SpriteOvO in #6438
• [Debug] Add option to only mention existing files in HGLDD by @fabianschuiki in #6452
• [ESI][Runtime] Filling out the type system by @teqdruid in #6476
• [ESI][Runtime] Get build working on Windows by @teqdruid in #6478
• [FIRRTL] Passive Wires pass by @darthscsi in #6475
• [FIRRTL][NFC] Add clockgate instName to FirtoolOptions setters. by @prithayan in #6460
• [Arc] Add option to observe registers and memories by @fabianschuiki in #6477
• [OM] Update result type for EmptyPathOp. by @mikeurbach in #6481
• [NFC] Disable -misc-include-cleaner by @nandor in #6483
• [FIRRTL] Add helpers for the implementation of FIRRTL instance-like ops by @nandor in #6484
• [HardwareToHW]Fix wrong lowering of arith.shli by @HahaLan97 in #6487
• [Pipeline] Use Block::BlockArgListType to avoid const. by @dtzSiFive in #6489
• [FIRRTL][WireDFT] Wire test-en to ClockGateIntrinsic. by @dtzSiFive in #6488
• [ESI][Integration test] Fix requires and run commands by @teqdruid in #6480
• [FIRRTL][Parser] Improve rwprobe parsing, support inst results. by @dtzSiFive in #6258
• [FIRRTL][CAPI] Build open bundle for fields containing non-base types by @SpriteOvO in #6482
• Bump LLVM by @jackkoenig in #6494
• [FlattenIO] Fix module input and output port name order. by @prithayan in #6495
• [firtool] Add option to treat EICG_wrapper as intrinsic by @fabianschuiki in #6499
• [NFC][ESI] Refactor runtime headers and design hierarchy by @teqdruid in #6503
• [Arc] Use seq.clock_gate op by @fabianschuiki in #6501

New Contributors

• @HahaLan97 made their first contribution in #6487

Full Changelog: firtool-1.60.0...firtool-1.61.0

Firtool 1.60.0 Release

What's Changed

• [Arc] Fix InlineArcs pass performance by @maerhart in #6379
• [ExportVerilog] Make ExprEmitter sensitive to assignment-like context by @fabianschuiki in #6329
• [HW] Verify dimensions for hw.aggregate_constant ops by @fzi-hielscher in #6380
• [ESI][Runtime] Read a manifest and build the design hierarchy by @teqdruid in #6384
• [CI] Update Python wheel action for MacOS. by @mikeurbach in #6386
• [FIRRTL] Simplify muxes when a particular bit value selects the same value. by @darthscsi in #6382
• [Docs] Fixed typo in VerilogGeneration.md by @dobios in #6394
• [Docs] Fix documentation typos, NFC by @tymcauley in #6393
• [ESI][Runtime] Create a 'trace' accelerator backend by @teqdruid in #6396
• [Seq] Add the Clocked trait to FIR mem read/write ops by @nandor in #6401
• [ESI][Runtime] Start of types by @teqdruid in #6397
• [OM] Tweak PathAttr syntax to be more amenable to bytecode. by @mikeurbach in #6403
• [OM] Remove enum type. by @mikeurbach in #6408
• [FIRRTL] Remove Map property type and expressions. by @mikeurbach in #6407
• [HWLegalizeModules] Lower types-like packed array handling (#5355) by @yupferris in #6402
• [ESI][Runtime] Wire up services and ports into the design tree by @teqdruid in #6406
• [ESI][Runtime][NFC] Cleanup runtime code by @teqdruid in #6411
• [Seq] Move the HWMemSimImpl pass to seq by @nandor in #6409
• [Seq] Add shiftreg op by @mortbopet in #6038
• [Comb] Disallow canonicalization across MLIR blocks by @mortbopet in #6235
• [FIRRTL] Add GroupMerge pass by @seldridge in #6412
• [FIRRTL][CAPI] Add functions for property types by @SpriteOvO in #6413
• [HWMemSimImpl] Add a mode to set disabled outputs to zero by @nandor in #6414
• Bump LLVM by @girishpai in #6404
• [HW] Fix bug with unknown location by @leonardt in #6416
• [HW] Move getPortVerilogName helper into HW PortInfo; NFC by @fabianschuiki in #6421
• [firtool] Remove -dedup option by @seldridge in #6191
• [Debug] Add expression support to HGLDD emission by @fabianschuiki in #6334
• [Firtool][CAPI] Remove dedup option from C API by @fzi-hielscher in #6423
• [FIRRTL][OM] Rebase path operations throughout the module hierarchy by @youngar in #6420
• [Seq] Move register & memory macro headers to SeqToSV by @nandor in #6419
• Bump LLVM by @uenoku in #6424
• [FIRRTL][LowerType] Handle unrealized_conversion_cast of other dialects by @prithayan in #6422
• [ESI] Cosim: punt endpoint naming to users by @teqdruid in #6427
• [ESI][Runtime] Add cosimulation support to new runtime by @teqdruid in #6428
• [ESI][Runtime] Access children and ports by name by @teqdruid in #6429
• [PyCDE] Fixing everything unexpectedly broken by @teqdruid in #6430
• [ESI][Runtime] Make GCC happy too by @teqdruid in #6431
• [LowerToHW] Pass through attributes on FModuleOp by @uenoku in #6400
• [FIRRTL] Verify public FModuleLike's don't have input probes. by @dtzSiFive in #6434
• [InstanceGraph] Remove the module lookup helper by @nandor in #6425
• [Comb]: Canonicalize and(x,y) and or(x,y) when x and y are defined by opposite comparisons by @devins2518 in #6374
• [ESI] Fix AppID index walk by @teqdruid in #6442
• [FIRRTL] Internally Rename "Groups" to "Layers" by @seldridge in #6443
• [FIRRTLFolds] Fix FoldZeroWidthMemory to write zero for zero bit wire by @uenoku in #6238
• [InferResets] Transition the pass to use the InstancePathCache by @nandor in #6440
• [HWMemSimImpl] Set visibility of generated modules private by @uenoku in #6444
• [FIRTOOL] Make firtool options behave like the rest of llvm. by @darthscsi in #6435
• [PyCDE] Use bundles for ESI services by @teqdruid in #6436
• [HW] Introduce the hw.instance_choice op by @nandor in #6447
• [ESI] Move Cosim manifest into separate module by @teqdruid in #6456
• [HW][FlattenIO] Fix extern module instances by @prithayan in #6441
• [ExportVerilog] Skip debug dialect ops by @fabianschuiki in #6453
• [firrtl] Add 4.0.0 public modules by @seldridge in #6448
• [ESI] Enable i0 sends and recvs over cosim by @teqdruid in #6459
• [ESI][Manifest] Make service records required by @teqdruid in #6461
• [ESI][Runtime] When a service cannot be created, ignore it by @teqdruid in #6462
• [PyCDE] Fixing integration tests by @teqdruid in #6463
• Add lowering for ILA Probe Intrinsic by @adkian-sifive in #6415

New Contributors

• @yupferris made their first contribution in #6402

Full Changelog: firtool-1.59.0...firtool-1.60.0

Firtool 1.59.0 Release

What's Changed

• [Debug] Honor dbg dialect ops in DebugInfo analysis by @fabianschuiki in #6310
• [ESI] Service requests now track AppIDs rather than instance hierarchy by @teqdruid in #6328
• [FIRRTL] Add debug info materialization pass by @fabianschuiki in #6309
• [firtool] Move -g option into firtool library by @fabianschuiki in #6332
• [ESI][Services] Leave breadcrumbs while connecting services by @teqdruid in #6331
• Rename sel on calyx.mux to cond by @rachitnigam in #6333
• [ESI] Add HasAppID op interface by @teqdruid in #6337
• [FIRRTL][LowerTypes] Keep the order of bundle fields in lowered cat by @SpriteOvO in #6339
• Disable MLIR install of CIRCT projects by @GeorgeLyon in #6340
• [ESI] Build AppID hierarchy for building manifest by @teqdruid in #6338
• [FIRRTL] Add a new pass to detect static asserts by @prithayan in #6341
• [FIRRTL] Add bool isFlip argument to walkGroundTypes callback by @prithayan in #6344
• [ESI] Add AppID design hierarchy manifest data to the manifest by @teqdruid in #6345
• Bump LLVM to 7ce613fc77af092dd6e9db71ce3747b75bc5616e by @fabianschuiki in #6342
• [Debug] Add debug-only value/op analysis by @fabianschuiki in #6335
• [ESI] Include designer-specified and service info in manifest by @teqdruid in #6346
• [CMake] Re-add install targets for CIRCT libraries by @GeorgeLyon in #6347
• [CI] Don't include deleted Python files in yapf check by @teqdruid in #6350
• [ESI] Rip out Cap'nProto schema generation by @teqdruid in #6349
• [OM] Convert list create ops for lists of paths in FreezePaths. by @mikeurbach in #6336
• [CAPI][MSFT]: Remove include of C++ header in C-API by @devins2518 in #6353
• [ESI] Move Cap'nProto into ESI runtime by @teqdruid in #6354
• [ESI] Not every build has zlib by @teqdruid in #6356
• [Ibis] Mark all not-illegal ops as legal by @teqdruid in #6355
• [OM] Add Python bindings for path types. by @mikeurbach in #6361
• [ESI][Cosim] DPI support for manifests by @teqdruid in #6357
• [ESI] Compressed manifest lowering for cosim by @teqdruid in #6358
• [Arc] Align >=128-bit integers to 16 bytes by @maerhart in #6366
• [Arc] Support lowering of seq clock type and conversion operations by @maerhart in #6367
• [Ibis] Refactor to use inner symbols by @mortbopet in #6369
• [ExportVerilog] Support parameterized length unpacked arrays by @teqdruid in #6362
• [CombToArith] Explicitly handle wide shifts to avoid UB by @fzi-hielscher in #6352
• [HW] Reference struct/union fields by index by @fzi-hielscher in #6266
• [HW] Resolve parametric types in the InstanceOp builder by @teqdruid in #6364
• [ESI] Major cosim fixup/cleanup/update by @teqdruid in #6365
• [ESI] Cosim integration test without runtime by @teqdruid in #6370
• [Arc] Remove hw.wire once it is tapped by @maerhart in #6372
• [ESI] Basic Python runtime for manifests by @teqdruid in #6371
• Bump LLVM to 3026c1361294a6d20c0d7dd5a3947b2c793873de by @fabianschuiki in #6375
• [Comb] Update Python binding decorators to wrap in the right order. by @mikeurbach in #6377

New Contributors

• @devins2518 made their first contribution in #6353

Full Changelog: firtool-1.58.0...firtool-1.59.0

Firtool 1.58.0 Release

What's Changed

• [MSFT] Add multicycle path op by @mortbopet in #6262
• [PyCDE] Support ESI bundles by @teqdruid in #6288
• [ESI] Start of system manifest: types by @teqdruid in #6290
• Remove old workflow by @GeorgeLyon in #6306
• [Debug] Include Verilog instance names in HGLDD output by @fabianschuiki in #6299
• [ESI] Rip out C++ API generator for cosim by @teqdruid in #6300
• [ESI] Ditching service metadata by @teqdruid in #6301
• [ESI][NFC] Misc improvements for bundle ops by @teqdruid in #6312
• [MergeConnections] Handle type alias by @uenoku in #6314
• [ESI] Move services over to bundles by @teqdruid in #6302
• firtoolPopulateCHIRRTLToLowFIRRTL doesn't need a module by @GeorgeLyon in #6304
• [LowerToHW] Avoid uninit plusargs.value reg by @seldridge in #6313
• [ExportVerilog] Fix struct inject op emisson by @uenoku in #6325
• [Debug] Add debug dialect by @fabianschuiki in #6308
• LLVM Bump by @debs-sifive in #6322
• [OM] Add evaluator support for paths by @youngar in #6320
• [ESI] Fix operation deletion in services connecting by @teqdruid in #6323
• [FIRRTL] Update ExtractInstances to use the new instance symbol. by @mikeurbach in #6327
• [FIRRTL] LowerAnnotations: Allow annotationRecords to be extended externally by @uenoku in #6296

Full Changelog: firtool-1.57.1...firtool-1.58.0

Firtool 1.57.1 Release

What's Changed

• Fix performance regression in verifiers by @darthscsi in #6293

Full Changelog: firtool-1.57.0...firtool-1.57.1

Firtool 1.57.0 Release

What's Changed

• [FIRRTL][HoistPassthrough] Add pass to hoist must-driven output ports. by @dtzSiFive in #6115
• Remove GlobalRefOp, GlobalRefAttr by @seldridge in #6173
• [FIRRTL][DropConst] Mark InstanceGraph preserved. by @dtzSiFive in #6183
• [firtool] Add LowerGroups pass by @seldridge in #6182
• [FIRRTL][Hoist] Mark all analyses preserved if no changes. by @dtzSiFive in #6185
• [firtool] Deprecate -dedup option by @seldridge in #6188
• [Ibis] Allow tunneling from hw.modules by @mortbopet in #6195
• [Pipeline] Remove internal clock, reset,stall signals. by @mortbopet in #6196
• [Ibis] Print offending port name and use count on containers-to-hw error by @blakep-msft in #6186
• [FIRRTL][LOA] If no changes made, mark all analyses preserved. by @dtzSiFive in #6187
• [Ibis] Fix clean selfdrivers in case of external reads by @mortbopet in #6201
• [ExportVerilog] Format specifiers: hierpath separation character by @teqdruid in #6192
• [FIRRTL] Add GroupSink pass by @seldridge in #6184
• [FIRRTL] Cause "weak" OMIR Annotations to not block optimizations by @seldridge in #6200
• [Ibis] Fix issues in Tunneling and PortRef lowering by @mortbopet in #6202
• [Python] Use Ninja and LLD when building wheel if available by @uenoku in #6165
• [FIRRTL][RefSubOp] Add getAccessedField helper method. by @dtzSiFive in #6208
• [OM][Bindings] Make Python Evaluator Object hashable by @prithayan in #6204
• [ExportVerilog] Fix line count in debug verilog locations by @prithayan in #6210
• [FIRRTL] Simplify getFieldRefFromValue, add+use FieldRefCache. by @dtzSiFive in #6181
• Bump LLVM by @rwy7 in #6207
• llvm: Small bump to get version that passes tests. by @dtzSiFive in #6211
• [Seq][FirMemLowering] Create correct width constant for missing mask input by @prithayan in #6214
• [Ibis] Add ibistool by @mortbopet in #6206
• [Ibis] Reblock should also create blocks around non-delimited ops by @mortbopet in #6218
• [Ibis] Add ibis-prepare-scheduling pass by @mortbopet in #6166
• [FIRRTL][LOA][NFCI] Use FieldRefCache. by @dtzSiFive in #6215
• [FIRRTL] Bump FIRRTL version to 3.3.0 for parsing by @seldridge in #6217
• [Arc] Move LegalizeStateUpdate before StateAlloc by @zyedidia in #5830
• [HW] Change printer for modules by @darthscsi in #6205
• [MSFT] Remove Python extensions for non-existant structure ops. by @mikeurbach in #6221
• [ibis] Fix reblock use of erased ops by @seldridge in #6222
• [FIRRTL][Parser] Update groups version check to 3.2.0. by @dtzSiFive in #6219
• [Calyx] Add calyx.undef by @rachitnigam in #5964
• [HW] Disallow duplicate field names in HW aggregate types by @fzi-hielscher in #6225
• [Firtool][CAPI] Add C-API for Firtool lib by @SpriteOvO in #6036
• [Ibis] Add ibis.sblock.isolated by @mortbopet in #6230
• [OM] Implement PathAttr CAPI and Python binding by @uenoku in #6229
• [Ibis] Add handshake to DC conversion by @mortbopet in #6231
• [FIRRTL] Preserve port orders when lowering to HW. by @darthscsi in #6224
• [FIRRTL] Input probe support. by @dtzSiFive in #6121
• [ExportVerilog] Bound type size considered for decl alignment by @fabianschuiki in #6171
• [FirRegLowering] Implement refined check for mux-to-if conversion. by @mikeurbach in #6203
• [ESI] Lower bundles to channels by @teqdruid in #6216
• [Ibis] Add methods-to-containers pass by @mortbopet in #6232
• [Firtool] Rerun IMCP after register optimizations by @uenoku in #6179
• [FIRRTL][ExpandWhens] Support flow checking for local and remote objects by @rwy7 in #6212
• [Ibis] Added missing ibistool to integration test by @dobios in #6241
• [OM] Load post-export dialects in om-linker. by @mikeurbach in #6242
• [FIRRTL] Update LowerClasses to use the defname for ExtModules. by @mikeurbach in #6243
• [Arc] Add LowerArcsToFuncs pass by @zyedidia in #6227
• [ESI][Python] Expose BundleType to Python by @teqdruid in #6248
• [FIRRTL] Add canonicalizations for mux comparing its high and low operands by @trilorez in #6246
• [FIRRTLFolds] Remove InvalidValue canonicalization by @uenoku in #6080
• [Ibis] Add scheduling prototype by @mortbopet in #6239
• [Arc] Lower models into eval functions by @fabianschuiki in #6247
• [OM] Update FreezePaths to root paths at the nearest public module. by @mikeurbach in #6244
• [Debug] Add basic DebugInfo analysis and emission by @fabianschuiki in #6148
• [PyCDE] Fixing tests by @teqdruid in #6252
• [OM] Add more path types by @youngar in #6250
• [OM] Evaluator: Support graph regions by @uenoku in #6249
• [SV] Mark sv.xmr.ref op as pure by @fabianschuiki in #6260
• [FIRRTL][FIRParser] Prefer RWProbe op as much as possible. by @dtzSiFive in #5835
• [FIRRTL][MergeConnections] Reject non-passive aggregates. by @dtzSiFive in #6264
• [FIRRTL][NFC] Move FieldRef -> InnerSymTarget to utility. by @dtzSiFive in #6265
• [Seq] Add optional power-on value to compreg ops by @mortbopet in #6255
• [Seq][NFC] More flexible builders for compregs by @nandor in #6270
• [firtool] Add infra for pass plugins by @uenoku in #6254
• [Seq] Remove custom printer/parser for seq.compreg(.ce) ops by @mortbopet in #6267
• [PipelineToHW] Add optional power-on values to control registers by @mortbopet in #6269
• [Seq] Fix the canonicalization of seq registers with a clock type by @nandor in #6274
• [OM] Add location info to EvaluatorValue by @prithayan in #6240
• [FIRRTL][GrandCentral] Add a mode to drop companion modules by @nandor in #6268
• [circt-opt] Export symbols for MLIR plugins by @uenoku in #6278
• [CI] Install LLVM utils to release artifacts by @uenoku in #6279
• [OM] Overhaul of path operations by @youngar in #6253
• [Namespace] Return an empty string for empty string. by @uenoku in #6284
• [NFC] LLVM Bump by @trilorez in #6280
• [FIRRTL] Add strip option to DropName by @uenoku in #6281
• [LowerToHW] Fix symbol creation for empty names by @uenoku in #6282
• [ExtractTestCode] Specify non-empty unqiue port names by @prithayan in #6283
• Add emission for calyx std_signext by @rachitnigam in #6285
• [FIRRTL] Remove RecursiveMemoryEffects and RecursivelySpeculatable from When op, add canonicalizers by @uenoku in #6236
• [HW] round trip ModuleType non-ssa values by @darthscsi in #6287

New Contributors

• @dobios made their first contribution in #6241

Full Changelog: firtool-1.56.1...firtool-1.57.0

Firtool 1.56.1 Release

What's Changed

• [MSFT] Finally move away from GlobalRefOp by @teqdruid in #6168
• [FIRRTL] Add Double property type. by @dtzSiFive in #6167
• [MSFT] Rip out MSFTModule et. al. by @teqdruid in #6161
• [HW] Allow for quoted struct field names by @fabianschuiki in #6174
• [MSFT] Remove DiscoverAppIDs pass by @teqdruid in #6175
• [Python] Remove CI options that only applied to MacOS universal. by @mikeurbach in #6169
• [NFC][ESI][MSFT] Move AppIDs over to ESI by @teqdruid in #6177
• [Ibis] Add Ibis CF to Handshake conversion by @mortbopet in #6164
• [Python] Downgrade setuptools_scm, drop python 3.7 as EOL by @uenoku in #6180

Full Changelog: firtool-1.56.0...firtool-1.56.1

Firtool 1.56.0 Release

What's Changed

• [Pipeline] Add non-stallable pipeline stages by @mortbopet in #6018
• [OM] Handle AnyType casts in Evaluator. by @mikeurbach in #6106
• [OM][firtool] Add FreezePaths pass by @youngar in #6069
• [CI] Use macOS universal wheels for M-series, add Python 3.9 and 3.11 support by @leonardt in #5822
• Add OMInstanceTarget path kind by @youngar in #6123
• [Arc] Introduce vectorize operation by @maerhart in #6120
• [Pipeline] Fix issue in ExplicitRegs by @mortbopet in #6118
• [Ibis] Add ibis reblock pass by @mortbopet in #6089
• [HW] Support parametric UnpackedArrayType in hw-specialize by @mortbopet in #6119
• [Ibis] Rename ibis.block -> ibis.sblock by @mortbopet in #6125
• [FIRRTL][IMCP] Fix handling of refsub, send/resolve, fields. by @dtzSiFive in #6100
• [FIRRTL][Parser] Wires of non-agg non-hw should have droppable names. by @dtzSiFive in #6102
• [FIRRTL][Inliner] Use wires for all. by @dtzSiFive in #6127
• [FIRRTL][LowerClasses] Handle InstanceTarget. by @dtzSiFive in #6126
• [PyCDE] Move off of msft.module to hw.module by @teqdruid in #6122
• [OM] Add path append op by @prithayan in #6073
• [HW] Unify port location arrays and port attribute arrays by @darthscsi in #6116
• [FIRRTL][Dedup] An extmodule without defname is unique. by @dtzSiFive in #6129
• [FIRRTL][Dedup] Skip modules with syms we can't drop, classes. by @dtzSiFive in #6133
• [Arc] Include pass base only where needed by @maerhart in #6140
• [Arc] Improve performance of state update legalization by @fabianschuiki in #6137
• [Arc] Add LowerVectorizations pass by @maerhart in #6141
• [Arc] Allow top-level logic in LowerState; detect clock edges by @fabianschuiki in #6142
• [Handshake] Allow handshake ops to be used outside of a handshake.func by @mortbopet in #6132
• [Seq] Convert seq.clock_gate to use the clock type exclusively by @nandor in #6134
• [Seq] Switch all seq ops to use seq.clock by @nandor in #6139
• [Seq] Lower clock types nested within aggregates by @nandor in #6138
• [FIRRTL][FIRParser] Add AnyRef cast as-needed for agg prop expr's. by @dtzSiFive in #6135
• [scf-to-calyx]Support for function call by @linuxlonelyeagle in #5965
• [Firtool] Move the remaining pass additions into lib by @SpriteOvO in #6094
• [Ibis] Add ibis.sblock inlining operations and passes by @mortbopet in #6145
• [HW][Python] Add name getters for ModuleType by @uenoku in #6149
• [OM] Python bindings for om integer by @prithayan in #6042
• [Ibis] Allow multiple return values for ibis.method by @mortbopet in #6151
• [NFC][Handshake] Adjust handshake interface defs and file locs by @mortbopet in #6150
• [ExportVerilog] Support CallSiteLoc and NameLoc emission by @mortbopet in #6131
• [ExportVerilog] Add verilog debug locations to output MLIR by @prithayan in #6092
• [FIRRTL][IMDCE] Mark all objects as alive by @rwy7 in #6157
• [ExportVerilog] Remove useless assert from NameCollector by @fabianschuiki in #6147
• [CI] Hotfix macosx python wheel by @leonardt in #6158
• [MSFT] Make AppID discovery an index rather than a pass by @teqdruid in #6152
• [PyCDE] Switch over to new AppIDIndex by @teqdruid in #6160
• [HW] Align instance_like_impl verification with getReferencedModule by @mortbopet in #6155
• [NFC][ExportVerilog] Move location emission functions to class by @mortbopet in #6154
• [CFToHandshake] Refactor towards genericness by @mortbopet in #6156
• [Ibis] Add ibis.method.df operation by @mortbopet in #6163
• [HW] Fix ModuleType::getInputType to return InOutType for InOut port by @uenoku in #6162

New Contributors

• @leonardt made their first contribution in #5822

Full Changelog: firtool-1.55.0...firtool-1.56.0