From bdaeec1abaef13ff79dba4691a17aeee4e8f3363 Mon Sep 17 00:00:00 2001 From: Jaakko Laurikainen Date: Thu, 7 Apr 2016 14:56:36 +0300 Subject: [PATCH] RCE target RCExplorer F3 board support for Cleanflight --- Makefile | 25 +- src/main/config/config.c | 17 +- src/main/drivers/pwm_mapping.c | 47 ++++ src/main/drivers/timer.c | 16 ++ src/main/sensors/initialisation.c | 2 +- src/main/sensors/sonar.c | 12 + src/main/target/RCE/system_stm32f30x.c | 372 +++++++++++++++++++++++++ src/main/target/RCE/system_stm32f30x.h | 76 +++++ src/main/target/RCE/target.h | 191 +++++++++++++ 9 files changed, 753 insertions(+), 5 deletions(-) create mode 100644 src/main/target/RCE/system_stm32f30x.c create mode 100644 src/main/target/RCE/system_stm32f30x.h create mode 100644 src/main/target/RCE/target.h diff --git a/Makefile b/Makefile index 1ad32369a93..ef74991fec2 100755 --- a/Makefile +++ b/Makefile @@ -35,7 +35,7 @@ FLASH_SIZE ?= FORKNAME = triflight -VALID_TARGETS = ALIENWIIF1 ALIENWIIF3 CC3D CHEBUZZF3 CJMCU COLIBRI_RACE LUX_RACE EUSTM32F103RC MOTOLAB NAZE NAZE32PRO OLIMEXINO PORT103R RMDO SPARKY SPRACINGF3 SPRACINGF3MINI STM32F3DISCOVERY +VALID_TARGETS = ALIENWIIF1 ALIENWIIF3 CC3D CHEBUZZF3 CJMCU COLIBRI_RACE LUX_RACE EUSTM32F103RC MOTOLAB NAZE NAZE32PRO OLIMEXINO PORT103R RCE RMDO SPARKY SPRACINGF3 SPRACINGF3MINI STM32F3DISCOVERY # Configure default flash sizes for the targets ifeq ($(FLASH_SIZE),) @@ -43,7 +43,7 @@ ifeq ($(TARGET),$(filter $(TARGET),CJMCU)) FLASH_SIZE = 64 else ifeq ($(TARGET),$(filter $(TARGET),ALIENWIIF1 CC3D NAZE OLIMEXINO RMDO)) FLASH_SIZE = 128 -else ifeq ($(TARGET),$(filter $(TARGET),ALIENWIIF3 CHEBUZZF3 COLIBRI_RACE LUX_RACE EUSTM32F103RC MOTOLAB NAZE32PRO PORT103R SPARKY SPRACINGF3 SPRACINGF3MINI STM32F3DISCOVERY)) +else ifeq ($(TARGET),$(filter $(TARGET),ALIENWIIF3 CHEBUZZF3 COLIBRI_RACE LUX_RACE EUSTM32F103RC MOTOLAB NAZE32PRO PORT103R RCE SPARKY SPRACINGF3 SPRACINGF3MINI STM32F3DISCOVERY)) FLASH_SIZE = 256 else $(error FLASH_SIZE not configured for target) @@ -70,7 +70,7 @@ FATFS_SRC = $(notdir $(wildcard $(FATFS_DIR)/*.c)) CSOURCES := $(shell find $(SRC_DIR) -name '*.c') -ifeq ($(TARGET),$(filter $(TARGET),ALIENWIIF3 CHEBUZZF3 COLIBRI_RACE LUX_RACE MOTOLAB NAZE32PRO RMDO SPARKY SPRACINGF3 SPRACINGF3MINI STM32F3DISCOVERY)) +ifeq ($(TARGET),$(filter $(TARGET),ALIENWIIF3 CHEBUZZF3 COLIBRI_RACE LUX_RACE MOTOLAB NAZE32PRO RCE RMDO SPARKY SPRACINGF3 SPRACINGF3MINI STM32F3DISCOVERY)) STDPERIPH_DIR = $(ROOT)/lib/main/STM32F30x_StdPeriph_Driver @@ -590,6 +590,25 @@ ALIENWIIF3_SRC = \ $(HIGHEND_SRC) \ $(COMMON_SRC) \ $(VCP_SRC) + +RCE_SRC = \ + $(STM32F30x_COMMON_SRC) \ + drivers/accgyro_mpu.c \ + drivers/accgyro_spi_mpu6000.c \ + drivers/accgyro_mpu6050.c \ + drivers/barometer_ms5611.c \ + drivers/compass_hmc5883l.c \ + drivers/compass_ak8975.c \ + drivers/display_ug2864hsweg01.c \ + drivers/serial_usb_vcp.c \ + drivers/flash_m25p16.c \ + drivers/light_ws2811strip.c \ + drivers/light_ws2811strip_stm32f30x.c \ + drivers/sonar_hcsr04.c \ + io/flashfs.c \ + $(HIGHEND_SRC) \ + $(COMMON_SRC) \ + $(VCP_SRC) RMDO_SRC = \ $(STM32F30x_COMMON_SRC) \ diff --git a/src/main/config/config.c b/src/main/config/config.c index 1455cc0cb89..dc7fc82e32e 100755 --- a/src/main/config/config.c +++ b/src/main/config/config.c @@ -249,7 +249,11 @@ static void resetBatteryConfig(batteryConfig_t *batteryConfig) batteryConfig->vbatmaxcellvoltage = 43; batteryConfig->vbatmincellvoltage = 33; batteryConfig->vbatwarningcellvoltage = 35; +#if defined(RCE) + batteryConfig->currentMeterScale = 360; // for the built-in current sensor on RCExplorer board +#else batteryConfig->currentMeterScale = 400; // for Allegro ACS758LCB-100U (40mV/A) +#endif batteryConfig->currentMeterType = CURRENT_SENSOR_ADC; } @@ -280,6 +284,13 @@ void resetSerialConfig(serialConfig_t *serialConfig) // This allows MSP connection via USART & VCP so the board can be reconfigured. serialConfig->portConfigs[1].functionMask = FUNCTION_MSP; #endif +#if defined(RCE) + // On RCExplorer board, UART1 is serial RX by default + serialConfig->portConfigs[1].functionMask = FUNCTION_RX_SERIAL; + // UART2 and UART3 as MSP for safety + serialConfig->portConfigs[2].functionMask = FUNCTION_MSP; + serialConfig->portConfigs[3].functionMask = FUNCTION_MSP; +#endif serialConfig->reboot_character = 'R'; } @@ -320,8 +331,12 @@ static void resetMixerConfig(mixerConfig_t *mixerConfig) { mixerConfig->tri_servo_min_adc = 0; mixerConfig->tri_servo_mid_adc = 0; mixerConfig->tri_servo_max_adc = 0; +#if defined(RCE) + mixerConfig->tri_servo_feedback = TRI_SERVO_FB_RSSI; +#else mixerConfig->tri_servo_feedback = TRI_SERVO_FB_VIRTUAL; #endif +#endif } uint8_t getCurrentProfile(void) @@ -367,7 +382,7 @@ STATIC_UNIT_TESTED void resetConf(void) masterConfig.version = EEPROM_CONF_VERSION; masterConfig.mixerMode = MIXER_TRI; featureClearAll(); -#if defined(CJMCU) || defined(SPARKY) || defined(COLIBRI_RACE) || defined(MOTOLAB) || defined(SPRACINGF3MINI) || defined(LUX_RACE) +#if defined(CJMCU) || defined(SPARKY) || defined(COLIBRI_RACE) || defined(MOTOLAB) || defined(SPRACINGF3MINI) || defined(LUX_RACE) || defined(RCE) featureSet(FEATURE_RX_PPM); #endif diff --git a/src/main/drivers/pwm_mapping.c b/src/main/drivers/pwm_mapping.c index 05d97d664c6..08ed68e773b 100755 --- a/src/main/drivers/pwm_mapping.c +++ b/src/main/drivers/pwm_mapping.c @@ -559,6 +559,46 @@ static const uint16_t airPWM[] = { }; #endif +#ifdef RCE +static const uint16_t multiPPM[] = { + PWM6 | (MAP_TO_PPM_INPUT << 8), // PPM input + PWM3 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM3 + PWM2 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM17 - can be switched to servo + PWM4 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM3 + PWM1 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM1 + PWM5 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM3 + 0xFFFF +}; + +static const uint16_t multiPWM[] = { + PWM3 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM3 + PWM2 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM17 - can be switched to servo + PWM4 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM3 + PWM1 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM1 + PWM5 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM3 + 0xFFFF +}; + +static const uint16_t airPPM[] = { + PWM6 | (MAP_TO_PPM_INPUT << 8), // PPM input + PWM3 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM3 + PWM2 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM17 - can be switched to servo + PWM4 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM3 + PWM1 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM1 + PWM5 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM3 + 0xFFFF +}; + +static const uint16_t airPWM[] = { + PWM3 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM3 + PWM2 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM17 - can be switched to servo + PWM4 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM3 + PWM1 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM1 + PWM5 | (MAP_TO_MOTOR_OUTPUT << 8), // TIM3 + 0xFFFF +}; +#endif + static const uint16_t * const hardwareMaps[] = { multiPWM, multiPPM, @@ -710,6 +750,13 @@ pwmIOConfiguration_t *pwmInit(drv_pwm_config_t *init) type = MAP_TO_SERVO_OUTPUT; #endif +#if defined(RCE) + if (timerIndex == PWM2) + { + type = MAP_TO_SERVO_OUTPUT; + } +#endif + #if defined(NAZE32PRO) || (defined(STM32F3DISCOVERY) && !defined(CHEBUZZF3)) // remap PWM 5+6 or 9+10 as servos - softserial pin pairs require timer ports that use the same timer if (init->useSoftSerial) { diff --git a/src/main/drivers/timer.c b/src/main/drivers/timer.c index 7ee2dc9725a..b629ca9f013 100755 --- a/src/main/drivers/timer.c +++ b/src/main/drivers/timer.c @@ -334,6 +334,22 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { #define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4) #define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM15 | RCC_APB2Periph_TIM16 | RCC_APB2Periph_TIM17) #define TIMER_AHB_PERIPHERALS (RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB) +#endif +#if defined(RCE) +const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { + { TIM3, GPIOA, Pin_4, TIM_Channel_2, TIM3_IRQn, 1, Mode_AF_PP, GPIO_PinSource4, GPIO_AF_2}, // PWM1 - PA4 + { TIM17, GPIOA, Pin_7, TIM_Channel_1, TIM1_TRG_COM_TIM17_IRQn, 1, Mode_AF_PP, GPIO_PinSource7, GPIO_AF_1}, // PWM2 - PA7 + { TIM1, GPIOA, Pin_8, TIM_Channel_1, TIM1_CC_IRQn, 1, Mode_AF_PP, GPIO_PinSource8, GPIO_AF_6}, // PWM3 - PA8 + { TIM3, GPIOB, Pin_0, TIM_Channel_3, TIM3_IRQn, 1, Mode_AF_PP, GPIO_PinSource0, GPIO_AF_2}, // PWM4 - PB0 + { TIM3, GPIOB, Pin_1, TIM_Channel_4, TIM3_IRQn, 1, Mode_AF_PP, GPIO_PinSource1, GPIO_AF_2}, // PWM5 - PB1 + { TIM2, GPIOA, Pin_1, TIM_Channel_2, TIM2_IRQn, 0, Mode_AF_PP, GPIO_PinSource1, GPIO_AF_1}, // PWM6 - PPM +}; + +#define USED_TIMERS (TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(17)) + +#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3) +#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM17) +#define TIMER_AHB_PERIPHERALS (RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB) #endif diff --git a/src/main/sensors/initialisation.c b/src/main/sensors/initialisation.c index b6f8d90ad51..1917a74fda0 100755 --- a/src/main/sensors/initialisation.c +++ b/src/main/sensors/initialisation.c @@ -138,7 +138,7 @@ const extiConfig_t *selectMPUIntExtiConfig(void) return &cc3dMPUIntExtiConfig; #endif -#ifdef MOTOLAB +#if defined(MOTOLAB) || defined(RCE) static const extiConfig_t MotolabF3MPUIntExtiConfig = { .gpioAHBPeripherals = RCC_AHBPeriph_GPIOA, .gpioPort = GPIOA, diff --git a/src/main/sensors/sonar.c b/src/main/sensors/sonar.c index bbcb878f79e..27cec051873 100644 --- a/src/main/sensors/sonar.c +++ b/src/main/sensors/sonar.c @@ -127,6 +127,18 @@ const sonarHardware_t *sonarGetHardwareConfiguration(batteryConfig_t *batteryCon .exti_irqn = EXTI1_IRQn }; return &sonarHardware; +#elif defined(RCE) + UNUSED(batteryConfig); + static const sonarHardware_t const sonarHardware = { + .trigger_pin = Pin_6, // PWM5 (PA5) - only 3.3v ( add a 1K Ohms resistor ) + .trigger_gpio = GPIOA, + .echo_pin = Pin_1, // PWM6 (PB1) - only 3.3v ( add a 1K Ohms resistor ) + .echo_gpio = GPIOB, + .exti_line = EXTI_Line1, + .exti_pin_source = EXTI_PinSource1, + .exti_irqn = EXTI1_IRQn + }; + return &sonarHardware; #elif defined(UNIT_TEST) UNUSED(batteryConfig); return 0; diff --git a/src/main/target/RCE/system_stm32f30x.c b/src/main/target/RCE/system_stm32f30x.c new file mode 100644 index 00000000000..fca6969825b --- /dev/null +++ b/src/main/target/RCE/system_stm32f30x.c @@ -0,0 +1,372 @@ +/** + ****************************************************************************** + * @file system_stm32f30x.c + * @author MCD Application Team + * @version V1.1.1 + * @date 28-March-2014 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F30x devices, + * and is generated by the clock configuration tool + * stm32f30x_Clock_Configuration_V1.0.0.xls + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f30x.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define + * in "stm32f30x.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + * Supported STM32F30x device + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 72000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 72000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 8000000 + *---------------------------------------------------------------------------- + * PLLMUL | 9 + *----------------------------------------------------------------------------- + * PREDIV | 1 + *----------------------------------------------------------------------------- + * USB Clock | ENABLE + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 2 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f30x_system + * @{ + */ + +/** @addtogroup STM32F30x_System_Private_Includes + * @{ + */ + +#include "stm32f30x.h" + +uint32_t hse_value = HSE_VALUE; + +/** + * @} + */ + +/* Private typedef -----------------------------------------------------------*/ + +/** @addtogroup STM32F30x_System_Private_Defines + * @{ + */ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @addtogroup STM32F30x_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 72000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_FunctionPrototypes + * @{ + */ + +void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR &= 0xF87FC00C; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + + /* Reset USARTSW[1:0], I2CSW and TIMs bits */ + RCC->CFGR3 &= (uint32_t)0xFF00FCCC; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + //SetSysClock(); // called from main() + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer and set Flash Latency */ + FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK / 1 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 1 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK / 2 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + + /* PLL configuration */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/src/main/target/RCE/system_stm32f30x.h b/src/main/target/RCE/system_stm32f30x.h new file mode 100644 index 00000000000..4f999d3058c --- /dev/null +++ b/src/main/target/RCE/system_stm32f30x.h @@ -0,0 +1,76 @@ +/** + ****************************************************************************** + * @file system_stm32f30x.h + * @author MCD Application Team + * @version V1.1.1 + * @date 28-March-2014 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F30x devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f30x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F30X_H +#define __SYSTEM_STM32F30X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/** @addtogroup STM32F30x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F30X_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/main/target/RCE/target.h b/src/main/target/RCE/target.h new file mode 100644 index 00000000000..deee2a57d69 --- /dev/null +++ b/src/main/target/RCE/target.h @@ -0,0 +1,191 @@ +/* + * This file is part of Cleanflight. + * + * Cleanflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Cleanflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Cleanflight. If not, see . + */ + +#pragma once + +#define TARGET_BOARD_IDENTIFIER "RCE" + +#define LED0_GPIO GPIOB +#define LED0_PIN Pin_4 // Blue - PB4 +#define LED0_PERIPHERAL RCC_AHBPeriph_GPIOB +#define LED1_GPIO GPIOB +#define LED1_PIN Pin_5 // Orange - PB5 +#define LED1_PERIPHERAL RCC_AHBPeriph_GPIOB + +#define BEEP_GPIO GPIOA +#define BEEP_PIN Pin_0 // PA0 (Beeper) +#define BEEP_PERIPHERAL RCC_AHBPeriph_GPIOA +#define BEEPER_INVERTED + +#define USABLE_TIMER_CHANNEL_COUNT 6 + +#define EXTI15_10_CALLBACK_HANDLER_COUNT 1 // MPU_INT + +#define USE_MPU_DATA_READY_SIGNAL + +#define GYRO +//#define USE_FAKE_GYRO +#define USE_GYRO_SPI_MPU6000 +#define USE_ACC_SPI_MPU6000 + +#define MPU6000_CS_GPIO GPIOB +#define MPU6000_CS_PIN GPIO_Pin_12 +#define MPU6000_SPI_INSTANCE SPI2 + +#define ACC +//#define USE_FAKE_ACC +#define USE_ACC_MPU6000 + +#define ACC_MPU6000_ALIGN CW180_DEG // TODO: check +#define GYRO_MPU6000_ALIGN CW180_DEG // TODO: check + +#define BARO +#define USE_BARO_MS5611 + +#define MAG +#define USE_MPU9250_MAG // Enables bypass configuration +#define USE_MAG_AK8975 +#define USE_MAG_HMC5883 // External + +#define MAG_AK8975_ALIGN CW180_DEG + +#define SONAR +#define BEEPER +#define LED0 +#define LED1 + +#define USB_IO + +#define USE_VCP +#define USE_USART1 +#define USE_USART2 +#define USE_USART3 +//#define USE_SOFTSERIAL1 // TODO: check softserial +#define SERIAL_PORT_COUNT 4 + +#ifndef UART1_GPIO +#define UART1_TX_PIN GPIO_Pin_6 // PB6 +#define UART1_RX_PIN GPIO_Pin_7 // PB7 +#define UART1_GPIO GPIOB +#define UART1_GPIO_AF GPIO_AF_7 +#define UART1_TX_PINSOURCE GPIO_PinSource6 +#define UART1_RX_PINSOURCE GPIO_PinSource7 +#endif + +#define UART2_TX_PIN GPIO_Pin_2 // PA2 +#define UART2_RX_PIN GPIO_Pin_3 // PA3 +#define UART2_GPIO GPIOA +#define UART2_GPIO_AF GPIO_AF_7 +#define UART2_TX_PINSOURCE GPIO_PinSource2 +#define UART2_RX_PINSOURCE GPIO_PinSource3 + +#ifndef UART3_GPIO +#define UART3_TX_PIN GPIO_Pin_10 // PB10 (AF7) +#define UART3_RX_PIN GPIO_Pin_11 // PB11 (AF7) +#define UART3_GPIO_AF GPIO_AF_7 +#define UART3_GPIO GPIOB +#define UART3_TX_PINSOURCE GPIO_PinSource10 +#define UART3_RX_PINSOURCE GPIO_PinSource11 +#endif + +//#define SOFTSERIAL_1_TIMER TIM2 +//#define SOFTSERIAL_1_TIMER_RX_HARDWARE 9 // PA0 / PAD3 +//#define SOFTSERIAL_1_TIMER_TX_HARDWARE 10 // PA1 / PAD4 + +#define USE_I2C +#define I2C_DEVICE (I2CDEV_2) // SDA (PA10/AF4), SCL (PA9/AF4) + +#define I2C2_SCL_GPIO GPIOA +#define I2C2_SCL_GPIO_AF GPIO_AF_4 +#define I2C2_SCL_PIN GPIO_Pin_9 +#define I2C2_SCL_PIN_SOURCE GPIO_PinSource9 +#define I2C2_SCL_CLK_SOURCE RCC_AHBPeriph_GPIOA +#define I2C2_SDA_GPIO GPIOA +#define I2C2_SDA_GPIO_AF GPIO_AF_4 +#define I2C2_SDA_PIN GPIO_Pin_10 +#define I2C2_SDA_PIN_SOURCE GPIO_PinSource10 +#define I2C2_SDA_CLK_SOURCE RCC_AHBPeriph_GPIOA + +#define USE_SPI +#define USE_SPI_DEVICE_2 // PB12,13,14,15 on AF5 +// +#define SPI2_GPIO GPIOB +#define SPI2_GPIO_PERIPHERAL RCC_AHBPeriph_GPIOB +#define SPI2_NSS_PIN Pin_12 +#define SPI2_NSS_PIN_SOURCE GPIO_PinSource12 +#define SPI2_SCK_PIN Pin_13 +#define SPI2_SCK_PIN_SOURCE GPIO_PinSource13 +#define SPI2_MISO_PIN Pin_14 +#define SPI2_MISO_PIN_SOURCE GPIO_PinSource14 +#define SPI2_MOSI_PIN Pin_15 +#define SPI2_MOSI_PIN_SOURCE GPIO_PinSource15 + +#define USE_ADC +#define BOARD_HAS_VOLTAGE_DIVIDER + +#define ADC_INSTANCE ADC2 +#define ADC_AHB_PERIPHERAL RCC_AHBPeriph_DMA2 +#define ADC_DMA_CHANNEL DMA2_Channel1 + +#define VBAT_ADC_GPIO GPIOA +#define VBAT_ADC_GPIO_PIN GPIO_Pin_5 +#define VBAT_ADC_CHANNEL ADC_Channel_2 + +#define CURRENT_METER_ADC_GPIO GPIOB +#define CURRENT_METER_ADC_GPIO_PIN GPIO_Pin_2 +#define CURRENT_METER_ADC_CHANNEL ADC_Channel_12 + +#define RSSI_ADC_GPIO GPIOA +#define RSSI_ADC_GPIO_PIN GPIO_Pin_6 +#define RSSI_ADC_CHANNEL ADC_Channel_3 + + +#define LED_STRIP // LED strip configuration using PWM motor output pin 5. +#define LED_STRIP_TIMER TIM16 + +#define WS2811_GPIO GPIOB +#define WS2811_GPIO_AHB_PERIPHERAL RCC_AHBPeriph_GPIOB +#define WS2811_GPIO_AF GPIO_AF_1 +#define WS2811_PIN GPIO_Pin_8 // TIM16_CH1 +#define WS2811_PIN_SOURCE GPIO_PinSource8 +#define WS2811_TIMER TIM16 +#define WS2811_TIMER_APB2_PERIPHERAL RCC_APB2Periph_TIM16 +#define WS2811_DMA_CHANNEL DMA1_Channel3 +#define WS2811_IRQ DMA1_Channel3_IRQn +#define WS2811_DMA_TC_FLAG DMA1_FLAG_TC3 +#define WS2811_DMA_HANDLER_IDENTIFER DMA1_CH3_HANDLER + +#define GPS +#define BLACKBOX +#define TELEMETRY +#define SERIAL_RX +#define AUTOTUNE +#define DISPLAY +#define USE_SERVOS +#define USE_CLI + +#define SPEKTRUM_BIND +// USART3, +#define BIND_PORT GPIOA +#define BIND_PIN Pin_3 + +#define USE_SERIAL_1WIRE + +#define S1W_TX_GPIO UART1_GPIO +#define S1W_TX_PIN UART1_TX_PIN +#define S1W_RX_GPIO UART1_GPIO +#define S1W_RX_PIN UART1_RX_PIN