From 5bc6c9d57c93e4a0f3e68f2c28b76f7c18951e26 Mon Sep 17 00:00:00 2001
From: litneet64 <litneet64@gmail.com>
Date: Fri, 31 May 2024 09:29:15 -0400
Subject: [PATCH] fix: bare bones tests

---
 test/Makefile | 2 +-
 test/tb.v     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/test/Makefile b/test/Makefile
index 4413db2..e7e1d81 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -5,7 +5,7 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v
+PROJECT_SOURCES = arbiter.v counter.v mux_16.v ring_osc.v puf_bit.v tt_um_ro_puf.v
 
 ifneq ($(GATES),yes)
 
diff --git a/test/tb.v b/test/tb.v
index 2fc848c..3157b62 100644
--- a/test/tb.v
+++ b/test/tb.v
@@ -24,7 +24,7 @@ module tb ();
   wire [7:0] uio_oe;
 
   // Replace tt_um_example with your module name:
-  tt_um_example user_project (
+  tt_um_litneet64_ro_puf user_project (
 
       // Include power ports for the Gate Level test:
 `ifdef GL_TEST