From b6d397f448eb060b8b59e0ac7dfbbf8cf26f3b35 Mon Sep 17 00:00:00 2001 From: Matteo Golin Date: Sun, 16 Jul 2023 14:27:07 -0400 Subject: [PATCH] Implemented microcode for branching instructions and updated hardware to suppport condition code output signal. --- schematic/gol_16.circ | 210 +++++++++++++++++++++++--------------- schematic/microcode.orgmc | 22 ++++ schematic/src/hashmap.c | 6 +- spec/hardware.txt | 1 + spec/instructionRTL.txt | 1 - 5 files changed, 153 insertions(+), 87 deletions(-) diff --git a/schematic/gol_16.circ b/schematic/gol_16.circ index a854076..05e3a29 100644 --- a/schematic/gol_16.circ +++ b/schematic/gol_16.circ @@ -66,9 +66,9 @@ - + - + @@ -115,6 +115,28 @@ + + + + + + + + + + + + + + + + + + + + + + @@ -135,28 +157,6 @@ - - - - - - - - - - - - - - - - - - - - - - @@ -194,8 +194,12 @@ - - + + + + + + @@ -210,11 +214,6 @@ - - - - - @@ -235,18 +234,30 @@ - - - - + + + + + + + + + + + + + + + - + + - + - + @@ -259,29 +270,15 @@ - - + + - + - - - - - - - - - - - - - - - - + + @@ -339,14 +336,14 @@ - + - + - + - + @@ -381,6 +378,9 @@ + + + @@ -534,6 +534,11 @@ + + + + + @@ -591,6 +596,9 @@ + + + @@ -661,6 +669,28 @@ + + + + + + + + + + + + + + + + + + + + + + @@ -781,7 +811,7 @@ - + @@ -791,11 +821,6 @@ - - - - - @@ -806,6 +831,11 @@ + + + + + @@ -875,6 +905,11 @@ + + + + + @@ -941,7 +976,6 @@ - @@ -960,6 +994,10 @@ + + + + @@ -975,11 +1013,6 @@ - - - - - @@ -993,13 +1026,13 @@ + - @@ -1010,7 +1043,10 @@ - + + + + @@ -1025,12 +1061,6 @@ - - - - - - @@ -1044,6 +1074,8 @@ + + @@ -1056,17 +1088,19 @@ - + + + @@ -1081,7 +1115,7 @@ - + @@ -1110,6 +1144,7 @@ + @@ -1128,6 +1163,7 @@ + @@ -1148,6 +1184,12 @@ + + + + + + @@ -1172,6 +1214,8 @@ + + diff --git a/schematic/microcode.orgmc b/schematic/microcode.orgmc index 3ecdf1f..ab42f6c 100644 --- a/schematic/microcode.orgmc +++ b/schematic/microcode.orgmc @@ -121,3 +121,25 @@ ex16: ; t2 <- [t1] + sext(imm7) ; FORM 5 --------------------------------------------------------------------------------------------------------------- lea: ; t2 <- [t1] + sext(imm9) t1oe, si9, aadd, t2ce, #t2_to_rd + +; BRANCHING ------------------------------------------------------------------------------------------------------------ +; Checking condition truthiness requires its own state + +; Execution states for Bcc ------------------------------------------------------------------------- +check_cc: + froe, ccoe, anop, #branch ; Only move on to branch if condition code is true + +branch: ; t2 <- [t1] + sext(imm7) iff cc + t1oe, si7, aadd, t2ce, #replace_pc + +replace_pc: ; PC <- [t2] + pcoe, regw, t2oe, anop, #fetch + +; Execution states for BLcc ------------------------------------------------------------------------ +; Note that pc++ is already in t2 right after decode state +check_cc_bl: + froe, ccoe, anop, #link + +link: ; LR <- [t2] + lroe, regw, t2oe, anop, #branch + diff --git a/schematic/src/hashmap.c b/schematic/src/hashmap.c index 94ceab4..865cfee 100644 --- a/schematic/src/hashmap.c +++ b/schematic/src/hashmap.c @@ -6,9 +6,9 @@ #include static const char *VALID_SIGNALS[] = { - "t1oe", "t1ce", "t2oe", "t2ce", "rd", "rx", "ry", "regw", "regr", "pcoe", "spoe", "lroe", - "froe", "frce", "ui4", "ui7", "ui9", "si7", "si9", "aadd", "asub", "anop", "aop", "coe", - "irce", "iroe", "marce", "maroe", "mdrce", "mdroe", "mdrput", "mdrget", "ibread", "ibwrite", + "t1oe", "t1ce", "t2oe", "t2ce", "rd", "rx", "ry", "ccoe", "regw", "regr", "pcoe", "spoe", + "lroe", "froe", "frce", "ui4", "ui7", "ui9", "si7", "si9", "aadd", "asub", "anop", "aop", + "coe", "irce", "iroe", "marce", "maroe", "mdrce", "mdroe", "mdrput", "mdrget", "ibread", "ibwrite", }; static const unsigned SIGNAL_COUNT = sizeof(VALID_SIGNALS) / sizeof(char *); diff --git a/spec/hardware.txt b/spec/hardware.txt index 4e10170..0cfda08 100644 --- a/spec/hardware.txt +++ b/spec/hardware.txt @@ -81,6 +81,7 @@ t2ce | Write to t2 from alu output. rd | Output bits 6&7 of the instruction register onto the internal address bus. rx | Output bits 8&9 of the instruction register onto the internal address bus. ry | Output bits 10&11 of the instruction register onto the internal address bus. +ccoe | Output bits 6-9 of the instruction register on the condition code bus. regw | Write data bus contents to the register on the internal address bus. regr | Read contents of the register on the internal address bus onto the internal data bus. pcoe | Output the address of the program counter onto the internal address bus. diff --git a/spec/instructionRTL.txt b/spec/instructionRTL.txt index 90a725d..4fe5c20 100644 --- a/spec/instructionRTL.txt +++ b/spec/instructionRTL.txt @@ -210,7 +210,6 @@ t2 <- [t1] + sext(imm7) iff cc PC <- [t2] BLcc imm7 -t2 <- [PC] LR <- [t2] iff cc t2 <- [t1] + sext(imm7) PC <- [t2]