From 6d6a1ee71ce88eaabc463db9deb461e3ef4a7c7f Mon Sep 17 00:00:00 2001 From: Lekcyjna <309016@uwr.edu.pl> Date: Sun, 24 Mar 2024 19:45:27 +0100 Subject: [PATCH 1/3] Remove riscvmodel. --- coreblocks/params/instr.py | 37 +++++++++++++++++++++++++++++++++++++ requirements-dev.txt | 1 - test/test_core.py | 10 ++++------ 3 files changed, 41 insertions(+), 7 deletions(-) diff --git a/coreblocks/params/instr.py b/coreblocks/params/instr.py index 8f14d6b11..aeb2ca23f 100644 --- a/coreblocks/params/instr.py +++ b/coreblocks/params/instr.py @@ -53,6 +53,10 @@ def __init__( def pack(self) -> Value: return Cat(C(0b11, 2), self.opcode, self.rd, self.funct3, self.rs1, self.rs2, self.funct7) + @staticmethod + def encode(opcode: int, rd: int, funct3: int, rs1: int, rs2: int, funct7: int): + return int(f"{funct7:07b}{rs2:05b}{rs1:05b}{funct3:03b}{rd:05b}{opcode:05b}11", 2) + class ITypeInstr(RISCVInstr): def __init__(self, opcode: ValueLike, rd: ValueLike, funct3: ValueLike, rs1: ValueLike, imm: ValueLike): @@ -65,6 +69,10 @@ def __init__(self, opcode: ValueLike, rd: ValueLike, funct3: ValueLike, rs1: Val def pack(self) -> Value: return Cat(C(0b11, 2), self.opcode, self.rd, self.funct3, self.rs1, self.imm) + @staticmethod + def encode(opcode: int, rd: int, funct3: int, rs1: int, imm: int): + return int(f"{imm:012b}{rs1:05b}{funct3:03b}{rd:05b}{opcode:05b}11", 2) + class STypeInstr(RISCVInstr): def __init__(self, opcode: ValueLike, imm: ValueLike, funct3: ValueLike, rs1: ValueLike, rs2: ValueLike): @@ -77,6 +85,11 @@ def __init__(self, opcode: ValueLike, imm: ValueLike, funct3: ValueLike, rs1: Va def pack(self) -> Value: return Cat(C(0b11, 2), self.opcode, self.imm[0:5], self.funct3, self.rs1, self.rs2, self.imm[5:12]) + @staticmethod + def encode(opcode: int, imm: int, funct3: int, rs1: int, rs2: int): + imm_str = f"{imm:012b}" + return int(f"{imm_str[5:12]:07b}{rs2:05b}{rs1:05b}{funct3:03b}{imm_str[0:5]:05b}{opcode:05b}11", 2) + class BTypeInstr(RISCVInstr): def __init__(self, opcode: ValueLike, imm: ValueLike, funct3: ValueLike, rs1: ValueLike, rs2: ValueLike): @@ -99,6 +112,15 @@ def pack(self) -> Value: self.imm[12], ) + @staticmethod + def encode(opcode: int, imm: int, funct3: int, rs1: int, rs2: int): + imm_str = f"{imm:013b}" + return int( + f"{imm_str[12]:01b}{imm_str[5:11]:06b}{rs2:05b}{rs1:05b}{funct3:03b}{imm_str[1:5]:04b}" + + f"{imm_str[11]:01b}{opcode:05b}11", + 2, + ) + class UTypeInstr(RISCVInstr): def __init__(self, opcode: ValueLike, rd: ValueLike, imm: ValueLike): @@ -109,6 +131,10 @@ def __init__(self, opcode: ValueLike, rd: ValueLike, imm: ValueLike): def pack(self) -> Value: return Cat(C(0b11, 2), self.opcode, self.rd, self.imm[12:]) + @staticmethod + def encode(opcode: int, rd: int, imm: int): + return int(f"{imm:020b}{rd:05b}{opcode:05b}11", 2) + class JTypeInstr(RISCVInstr): def __init__(self, opcode: ValueLike, rd: ValueLike, imm: ValueLike): @@ -119,6 +145,13 @@ def __init__(self, opcode: ValueLike, rd: ValueLike, imm: ValueLike): def pack(self) -> Value: return Cat(C(0b11, 2), self.opcode, self.rd, self.imm[12:20], self.imm[11], self.imm[1:11], self.imm[20]) + @staticmethod + def encode(opcode: int, rd: int, imm: int): + imm_str = f"{imm:021b}" + return int( + f"{imm_str[20]:01b}{imm_str[1:11]:010b}{imm_str[11]:01b}{imm_str[12:20]:08b}{rd:05b}{opcode:05b}11", 2 + ) + class IllegalInstr(RISCVInstr): def __init__(self): @@ -127,6 +160,10 @@ def __init__(self): def pack(self) -> Value: return C(1).replicate(32) # Instructions with all bits set to 1 are reserved to be illegal. + @staticmethod + def encode(opcode: int, rd: int, imm: int): + return int("1" * 32, 2) + class EBreakInstr(ITypeInstr): def __init__(self): diff --git a/requirements-dev.txt b/requirements-dev.txt index 1d9530305..1f68b2f1f 100644 --- a/requirements-dev.txt +++ b/requirements-dev.txt @@ -3,7 +3,6 @@ black==23.3.0 docutils==0.15.2 flake8==6.0.0 pep8-naming==0.13.3 -git+https://github.com/kristopher38/riscv-python-model@b5d0737#riscv-model markupsafe==2.0.1 myst-parser==0.18.0 numpydoc==1.5.0 diff --git a/test/test_core.py b/test/test_core.py index a2cfd1d88..dbb8692f8 100644 --- a/test/test_core.py +++ b/test/test_core.py @@ -7,7 +7,9 @@ from transactron.testing import TestCaseWithSimulator, TestbenchIO from coreblocks.core import Core +from coreblocks.frontend.decoder import Opcode, Funct3 from coreblocks.params import GenParams +from coreblocks.params.instr import * from coreblocks.params.configurations import CoreConfiguration, basic_core_config, full_core_config from coreblocks.peripherals.wishbone import WishboneSignature, WishboneMemorySlave @@ -16,10 +18,6 @@ import subprocess import tempfile from parameterized import parameterized_class -from riscvmodel.insn import ( - InstructionADDI, - InstructionLUI, -) class CoreTestElaboratable(Elaboratable): @@ -81,8 +79,8 @@ def push_register_load_imm(self, reg_id, val): if val & 0x800: lui_imm = (lui_imm + 1) & (0xFFFFF) - yield from self.push_instr(InstructionLUI(reg_id, lui_imm).encode()) - yield from self.push_instr(InstructionADDI(reg_id, reg_id, addi_imm).encode()) + yield from self.push_instr(UTypeInstr.encode(Opcode.LUI, reg_id, lui_imm)) + yield from self.push_instr(ITypeInstr.encode(Opcode.OP_IMM, reg_id, Funct3.ADD, reg_id, addi_imm)) class TestCoreAsmSourceBase(TestCoreBase): From b75479f26506f26de3db6a82f4f58e5bce12af55 Mon Sep 17 00:00:00 2001 From: Lekcyjna <309016@uwr.edu.pl> Date: Sun, 24 Mar 2024 20:04:23 +0100 Subject: [PATCH 2/3] Fixed, but dirty. --- coreblocks/params/instr.py | 7 ++++++- test/test_core.py | 21 +++++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/coreblocks/params/instr.py b/coreblocks/params/instr.py index aeb2ca23f..370d25b84 100644 --- a/coreblocks/params/instr.py +++ b/coreblocks/params/instr.py @@ -3,7 +3,7 @@ from amaranth.hdl import ValueCastable from amaranth import * -from transactron.utils import ValueLike +from transactron.utils import ValueLike, int_to_signed from coreblocks.params.isa_params import * from coreblocks.frontend.decoder.isa import * @@ -71,6 +71,7 @@ def pack(self) -> Value: @staticmethod def encode(opcode: int, rd: int, funct3: int, rs1: int, imm: int): + imm = int_to_signed(imm, 12) return int(f"{imm:012b}{rs1:05b}{funct3:03b}{rd:05b}{opcode:05b}11", 2) @@ -87,6 +88,7 @@ def pack(self) -> Value: @staticmethod def encode(opcode: int, imm: int, funct3: int, rs1: int, rs2: int): + imm = int_to_signed(imm, 12) imm_str = f"{imm:012b}" return int(f"{imm_str[5:12]:07b}{rs2:05b}{rs1:05b}{funct3:03b}{imm_str[0:5]:05b}{opcode:05b}11", 2) @@ -114,6 +116,7 @@ def pack(self) -> Value: @staticmethod def encode(opcode: int, imm: int, funct3: int, rs1: int, rs2: int): + imm = int_to_signed(imm, 13) imm_str = f"{imm:013b}" return int( f"{imm_str[12]:01b}{imm_str[5:11]:06b}{rs2:05b}{rs1:05b}{funct3:03b}{imm_str[1:5]:04b}" @@ -133,6 +136,7 @@ def pack(self) -> Value: @staticmethod def encode(opcode: int, rd: int, imm: int): + imm = int_to_signed(imm, 20) return int(f"{imm:020b}{rd:05b}{opcode:05b}11", 2) @@ -147,6 +151,7 @@ def pack(self) -> Value: @staticmethod def encode(opcode: int, rd: int, imm: int): + imm = int_to_signed(imm, 21) imm_str = f"{imm:021b}" return int( f"{imm_str[20]:01b}{imm_str[1:11]:010b}{imm_str[11]:01b}{imm_str[12:20]:08b}{rd:05b}{opcode:05b}11", 2 diff --git a/test/test_core.py b/test/test_core.py index dbb8692f8..eded5978a 100644 --- a/test/test_core.py +++ b/test/test_core.py @@ -58,6 +58,11 @@ def elaborate(self, platform): return m +from riscvmodel.insn import ( + InstructionADDI, + InstructionLUI, +) +import logging class TestCoreBase(TestCaseWithSimulator): gen_params: GenParams @@ -79,6 +84,22 @@ def push_register_load_imm(self, reg_id, val): if val & 0x800: lui_imm = (lui_imm + 1) & (0xFFFFF) + + lui_org = InstructionLUI(reg_id, lui_imm).encode() + lui_my = UTypeInstr.encode(Opcode.LUI, reg_id, lui_imm) + #logging.debug(lui_my) + if (lui_org != lui_my): + logging.error("LUI") + assert False + addi_org = InstructionADDI(reg_id, reg_id, addi_imm).encode() + addi_my = ITypeInstr.encode(Opcode.OP_IMM, reg_id, Funct3.ADD, reg_id, addi_imm) + if (addi_org != addi_my): + logging.error("MY") + logging.error(addi_imm) + logging.error(f"{addi_my:032b}") + logging.error(f"{addi_org:032b}") + assert False + yield from self.push_instr(UTypeInstr.encode(Opcode.LUI, reg_id, lui_imm)) yield from self.push_instr(ITypeInstr.encode(Opcode.OP_IMM, reg_id, Funct3.ADD, reg_id, addi_imm)) From b4e5e7dfc8099e36b58b901ba230af6c8b127879 Mon Sep 17 00:00:00 2001 From: Lekcyjna <309016@uwr.edu.pl> Date: Sun, 24 Mar 2024 20:05:22 +0100 Subject: [PATCH 3/3] Cleaning. --- test/test_core.py | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/test/test_core.py b/test/test_core.py index eded5978a..dbb8692f8 100644 --- a/test/test_core.py +++ b/test/test_core.py @@ -58,11 +58,6 @@ def elaborate(self, platform): return m -from riscvmodel.insn import ( - InstructionADDI, - InstructionLUI, -) -import logging class TestCoreBase(TestCaseWithSimulator): gen_params: GenParams @@ -84,22 +79,6 @@ def push_register_load_imm(self, reg_id, val): if val & 0x800: lui_imm = (lui_imm + 1) & (0xFFFFF) - - lui_org = InstructionLUI(reg_id, lui_imm).encode() - lui_my = UTypeInstr.encode(Opcode.LUI, reg_id, lui_imm) - #logging.debug(lui_my) - if (lui_org != lui_my): - logging.error("LUI") - assert False - addi_org = InstructionADDI(reg_id, reg_id, addi_imm).encode() - addi_my = ITypeInstr.encode(Opcode.OP_IMM, reg_id, Funct3.ADD, reg_id, addi_imm) - if (addi_org != addi_my): - logging.error("MY") - logging.error(addi_imm) - logging.error(f"{addi_my:032b}") - logging.error(f"{addi_org:032b}") - assert False - yield from self.push_instr(UTypeInstr.encode(Opcode.LUI, reg_id, lui_imm)) yield from self.push_instr(ITypeInstr.encode(Opcode.OP_IMM, reg_id, Funct3.ADD, reg_id, addi_imm))