From f935944bc535ec0b17b97853024ce7213d81fb39 Mon Sep 17 00:00:00 2001 From: tilk Date: Tue, 12 Mar 2024 17:22:16 +0000 Subject: [PATCH] Enable division and bit manipulation extensions in benchmarks (#616) --- .doctrees/api.doctree | Bin 21036 -> 21036 bytes .doctrees/auto_graph.doctree | Bin 44192 -> 44190 bytes .doctrees/current-graph.doctree | Bin 45413 -> 45411 bytes .doctrees/environment.pickle | Bin 447745 -> 447745 bytes _sources/auto_graph.rst.txt | 302 ++++++++++---------- api.html | 2 +- assumptions.html | 2 +- auto_graph.html | 304 ++++++++++----------- components/icache.html | 2 +- coreblocks.cache.html | 2 +- coreblocks.frontend.html | 2 +- coreblocks.fu.html | 2 +- coreblocks.fu.unsigned_multiplication.html | 2 +- coreblocks.html | 2 +- coreblocks.lsu.html | 2 +- coreblocks.params.html | 2 +- coreblocks.peripherals.html | 2 +- coreblocks.scheduler.html | 2 +- coreblocks.stages.html | 2 +- coreblocks.structs_common.html | 2 +- coreblocks.utils.html | 2 +- current-graph.html | 304 ++++++++++----------- development-environment.html | 2 +- genindex.html | 2 +- home.html | 2 +- index.html | 2 +- miscellany/exceptions-summary.html | 2 +- modules-coreblocks.html | 2 +- modules-transactron.html | 2 +- problem-checklist.html | 2 +- py-modindex.html | 2 +- scheduler/overview.html | 2 +- search.html | 2 +- shared-structs/implementation/rs-impl.html | 2 +- shared-structs/rs.html | 2 +- synthesis/synthesis.html | 2 +- transactions.html | 2 +- transactron.html | 2 +- transactron.lib.html | 2 +- transactron.testing.html | 2 +- transactron.utils.amaranth_ext.html | 2 +- transactron.utils.html | 2 +- 42 files changed, 490 insertions(+), 490 deletions(-) diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index 3673dd013aea0f5163110ba26ee12d665a8afbb4..9cd8d93868454a866dd74a9b5f400f543aa07886 100644 GIT binary patch delta 479 zcmZvYze)o^5XMO`jWIEQOmcx>&@>Xb3n|Q9IKej%>}(`#HfwIl?e4L=2ijR!E`sb8 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z0Dm3OUI2o0KnDTnqyst&KsN?pzQ@#E0D9?w5CI6+0p$?_(pQH>3P6kwh!ubY9grvh zDLSB^01VUtg9Kox4j3i?X*wWX07jHE2>*j(BL!rP4j3x{6Li2t0hpo#rV2og4wxnY zGj+f$0m#(>CIQIT0Oh6v0hz}j{O_5~7l2|NP$B@OI$((aEY|^L0 z)aZaU0#LqQhinj#O*&w+0BqF(bpo(W2iz|J59olM0LJSYGU>wvui@R$|gevfIN zfE?fusynCl;Z7N!W@e5S#a$n?7C`pZUf|fZ2nD;hpkNmZ6zpDrf(7m<*t^as#HXnF zXO+=np)Lv*i=w#e^V00a13>?izAr79v3L|bSty5s#abxX-Ezv7;^K93K@tB;bmMTr OTfW8e+FNRj;r{^neavA1 diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 6de9999e7..301ff78d5 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -4,43 +4,43 @@ subgraph TransactionModule["TransactionModule"] subgraph CoreTestElaboratable["elaboratable CoreTestElaboratable"] subgraph Core["core Core"] - Core_DiscardBranchVerify["DiscardBranchVerify"] Core_InitFreeRFFifo["InitFreeRFFifo"] + Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] WishboneMaster_request["request"] WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_result["result"] subgraph Forwarder["result Forwarder"] - Forwarder_read["read"] Forwarder_write["write"] + Forwarder_read["read"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] + WishboneMaster1_result["result"] WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] - Forwarder1_read["read"] Forwarder1_write["write"] + Forwarder1_read["read"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_get_write_response["get_write_response"] - WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_request_read["request_read"] + WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] @@ -67,13 +67,13 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] subgraph Forwarder2["address_fwd Forwarder"] Forwarder2_write["write"] Forwarder2_read["read"] @@ -81,10 +81,10 @@ end subgraph ICache["icache ICache"] ICache_ICache["ICache"] + ICache_issue_req["issue_req"] ICache_ICache1["ICache"] ICache_accept_res["accept_res"] ICache_ICache2["ICache"] - ICache_issue_req["issue_req"] ICache_ICache3["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] @@ -117,29 +117,29 @@ FIFO2_read["read"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_commit["commit"] RRAT_peek["peek"] + RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] - RegisterFile_read2["read2"] RegisterFile_free["free"] RegisterFile_write["write"] + RegisterFile_read1["read1"] + RegisterFile_read2["read2"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_retire["retire"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_peek["peek"] + ReorderBuffer_retire["retire"] + ReorderBuffer_put["put"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] LatencyMeasurer1__start["_start"] LatencyMeasurer1__stop["_stop"] @@ -155,8 +155,8 @@ subgraph Fetch["fetch Fetch"] Fetch_Fetch["Fetch"] Fetch_resume["resume"] - Fetch_stall_exception["stall_exception"] Fetch_Fetch1["Fetch"] + Fetch_stall_exception["stall_exception"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] BasicFifo3_write["write"] BasicFifo3_read["read"] @@ -164,11 +164,11 @@ end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] ExceptionCauseRegister_get["get"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_clear["clear"] + ExceptionCauseRegister_report["report"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] - BasicFifo4_read["read"] BasicFifo4_write["write"] + BasicFifo4_read["read"] end subgraph ConnectTrans["report_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -197,24 +197,24 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] + RSFuncBlock_get_result["get_result"] RSFuncBlock_select["select"] RSFuncBlock_update["update"] RSFuncBlock_insert["insert"] - RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] - RS_select["select"] - RS_update["update"] - RS_insert["insert"] RS_RS["RS"] + RS_take["take"] RS_RS1["RS"] RS_RS2["RS"] RS_RS3["RS"] - RS_take["take"] RS_RS4["RS"] + RS_update["update"] + RS_select["select"] + RS_insert["insert"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph FIFO4["fifo FIFO"] FIFO4_write["write"] FIFO4_read["read"] @@ -224,11 +224,11 @@ WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO5["fifo FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] @@ -251,8 +251,8 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -262,8 +262,8 @@ ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] subgraph FIFO8["fifo FIFO"] - FIFO8_read["read"] FIFO8_write["write"] + FIFO8_read["read"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -274,8 +274,8 @@ PrivilegedFuncUnit_precommit["precommit"] PrivilegedFuncUnit_accept["accept"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] - BasicFifo5_write["write"] BasicFifo5_read["read"] + BasicFifo5_write["write"] end end subgraph WakeupSelect4["wakeup_select_4 WakeupSelect"] @@ -284,8 +284,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_read["read"] Forwarder5_write["write"] + Forwarder5_read["read"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans4["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -307,48 +307,48 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_update["update"] - LSUDummy_LSUDummy["LSUDummy"] LSUDummy_insert["insert"] - LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_update["update"] + LSUDummy_select["select"] LSUDummy_precommit["precommit"] + LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_get_result["get_result"] - LSUDummy_select["select"] + LSUDummy_LSUDummy2["LSUDummy"] subgraph Forwarder6["forwarder Forwarder"] - Forwarder6_read["read"] Forwarder6_write["write"] + Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond0["issue_cond0"] LSURequester_issue_cond2["issue_cond2"] - LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue["issue"] + LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond0["issue_cond0"] LSURequester_accept["accept"] LSURequester_accept_cond1["accept_cond1"] - LSURequester_issue_cond1["issue_cond1"] - LSURequester_issue["issue"] + LSURequester_accept_cond0["accept_cond0"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] CSRUnit_insert["insert"] - CSRUnit_fetch_resume["fetch_resume"] - CSRUnit_select["select"] - CSRUnit_update["update"] CSRUnit_precommit["precommit"] + CSRUnit_fetch_resume["fetch_resume"] CSRUnit_get_result["get_result"] + CSRUnit_select["select"] CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_update["update"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] + MethodTryProduct_method["method"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] - MethodTryProduct_method["method"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_write["write"] Forwarder7_read["read"] + Forwarder7_write["write"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans9["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -365,8 +365,8 @@ end subgraph InterruptController["interrupt_controller InterruptController"] InterruptController_report_interrupt["report_interrupt"] - InterruptController_entry["entry"] InterruptController_mret["mret"] + InterruptController_entry["entry"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] @@ -377,15 +377,15 @@ CSRRegister__fu_read["_fu_read"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_write["_fu_write"] - CSRRegister1_read["read"] CSRRegister1__fu_read["_fu_read"] + CSRRegister1_read["read"] + CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2__fu_write["_fu_write"] - CSRRegister2_write["write"] - CSRRegister2_read["read"] CSRRegister2__fu_read["_fu_read"] + CSRRegister2_read["read"] + CSRRegister2_write["write"] + CSRRegister2__fu_write["_fu_write"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] @@ -396,9 +396,9 @@ CSRRegister3_write["write"] end subgraph CSRRegister4["register_high CSRRegister"] - CSRRegister4_read["read"] - CSRRegister4_write["write"] CSRRegister4__fu_read["_fu_read"] + CSRRegister4_write["write"] + CSRRegister4_read["read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] @@ -416,8 +416,8 @@ end end subgraph FIFO9["fifo_decode FIFO"] - FIFO9_read["read"] FIFO9_write["write"] + FIFO9_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -470,24 +470,24 @@ end subgraph Retirement["retirement Retirement"] Retirement_Retirement_cond1["Retirement_cond1"] - Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement1["Retirement"] Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement4["Retirement"] + Retirement_core_state["core_state"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] + CSRRegister7_write["write"] CSRRegister7_read["read"] CSRRegister7__fu_read["_fu_read"] - CSRRegister7_write["write"] end subgraph CSRRegister8["register_high CSRRegister"] CSRRegister8__fu_read["_fu_read"] - CSRRegister8_read["read"] CSRRegister8_write["write"] + CSRRegister8_read["read"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -508,40 +508,40 @@ end subgraph TransactionManager["transactionManager TransactionManager"] TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] - TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] + TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] + TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] + TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] end end Core_InitFreeRFFifo --> BasicFifo2_write - Retirement_Retirement2 --> BasicFifo2_write - TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write + Retirement_Retirement4 --> BasicFifo2_write TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write + TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write Forwarder2_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request - ICache_ICache <--> HwCounter4__incr - ICache_ICache3 <--> HwCounter3__incr - ICache_ICache3 <--> HwCounter2__incr - ICache_ICache3 <--> HwCounter1__incr - ICache_ICache3 --> Forwarder3_write - ICache_ICache1 --> SimpleCommonBusCacheRefiller_start_refill + ICache_ICache3 <--> HwCounter4__incr + ICache_ICache2 <--> HwCounter3__incr + ICache_ICache2 <--> HwCounter2__incr + ICache_ICache2 <--> HwCounter1__incr + ICache_ICache2 --> Forwarder3_write + ICache_ICache --> SimpleCommonBusCacheRefiller_start_refill + ICache_ICache --> Forwarder2_write ICache_ICache1 --> Forwarder2_write - ICache_ICache2 --> Forwarder2_write - SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache2 - WishboneMasterAdapter_get_read_response --> ICache_ICache2 - Serializer_Serializer1 --> ICache_ICache2 - BasicFifo_read --> ICache_ICache2 - WishboneMaster_result --> ICache_ICache2 - Forwarder_read --> ICache_ICache2 + SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 + WishboneMasterAdapter_get_read_response --> ICache_ICache1 + Serializer_Serializer --> ICache_ICache1 + BasicFifo_read --> ICache_ICache1 + WishboneMaster_result --> ICache_ICache1 + Forwarder_read --> ICache_ICache1 Fetch_Fetch --> ICache_issue_req Fetch_Fetch <--> HwCounter__incr Fetch_Fetch <--> LatencyMeasurer__start @@ -571,7 +571,7 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename - Retirement_Retirement2 --> FRAT_rename + Retirement_Retirement4 --> FRAT_rename TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation @@ -579,18 +579,18 @@ ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write - FIFO12_read --> RSSelection_RSSelection2 - RSSelection_RSSelection2 --> Forwarder8_write + FIFO12_read --> RSSelection_RSSelection3 + RSSelection_RSSelection3 --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection + Forwarder8_read --> RSSelection_RSSelection2 Forwarder8_read --> RSSelection_RSSelection1 - Forwarder8_read --> RSSelection_RSSelection3 RSFuncBlock_select --> RSSelection_RSSelection RS_select --> RSSelection_RSSelection RSSelection_RSSelection --> FIFO13_write + RSSelection_RSSelection2 --> FIFO13_write RSSelection_RSSelection1 --> FIFO13_write - RSSelection_RSSelection3 --> FIFO13_write - RSSelection_RSSelection1 <--> LSUDummy_select - RSSelection_RSSelection3 <--> CSRUnit_select + RSSelection_RSSelection2 <--> LSUDummy_select + RSSelection_RSSelection1 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -606,7 +606,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume - Retirement_Retirement4 --> Fetch_resume + Retirement_Retirement --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -627,7 +627,7 @@ RS_RS4 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write - RS_RS2 --> WakeupSelect2_WakeupSelect + RS_RS3 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -642,7 +642,7 @@ RS_RS1 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write - RS_RS3 --> WakeupSelect4_WakeupSelect + RS_RS2 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -662,10 +662,10 @@ ConnectTrans8_ConnectTrans --> BasicFifo5_write LSUDummy_LSUDummy --> Forwarder6_write TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write - TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write - TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write - TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write - TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write + TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write + TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write + TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write + TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -695,37 +695,37 @@ ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans - ReorderBuffer_peek --> Retirement_Retirement + ReorderBuffer_peek --> Retirement_Retirement1 ReorderBuffer_peek --> Retirement_Retirement3 - ReorderBuffer_peek --> Retirement_Retirement2 - ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement --> MethodTryProduct_method + ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement1 --> MethodTryProduct_method ExceptionCauseRegister_get --> Retirement_Retirement3 - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement2 <--> ReorderBuffer_retire - TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire + ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement4 <--> ReorderBuffer_retire TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire - Retirement_Retirement2 <--> LatencyMeasurer1__stop - TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop + TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire + Retirement_Retirement4 <--> LatencyMeasurer1__stop TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop - FIFO3_read --> Retirement_Retirement2 - FIFO3_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop + FIFO3_read --> Retirement_Retirement4 FIFO3_read --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement2 --> HwExpHistogram1__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add + FIFO3_read --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement4 --> HwExpHistogram1__add TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add - CoreInstructionCounter_decrement --> Retirement_Retirement2 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add + CoreInstructionCounter_decrement --> Retirement_Retirement4 CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement - RRAT_peek --> Retirement_Retirement2 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement + RRAT_peek --> Retirement_Retirement4 RRAT_peek --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement2 --> RegisterFile_free - TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free + Retirement_Retirement4 --> RegisterFile_free TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free - CSRRegister1_read --> Retirement_Retirement4 - Retirement_Retirement4 <--> ExceptionCauseRegister_clear + TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free + CSRRegister1_read --> Retirement_Retirement + Retirement_Retirement <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -737,19 +737,48 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement2 + TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement2 + TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write + TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write + TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write + TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write + TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry + TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy - Serializer1_Serializer2 --> TransactionManager_accept_cond1_LSUDummy + Serializer1_Serializer --> TransactionManager_accept_cond1_LSUDummy BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy - BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 + BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy - WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 + WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy - Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 - TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy1 - TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy1 + Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy + TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy2 + TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy2 LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy - LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 + LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy + TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 + TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 + TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read + TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer2 + TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write + TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write + TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request + TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request + TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 + TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write + TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3 + TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy + Serializer1_Serializer1 --> TransactionManager_accept_cond0_LSUDummy TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 TransactionManager_Retirement_cond0_Retirement --> RRAT_commit TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment @@ -758,32 +787,3 @@ CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement1 - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement1 - TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write - TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry - TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 - TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy2 - TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy2 - TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy2 - TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 - TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 - TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request - TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request - TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 - Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond0 - TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 - TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 - TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read - TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer3 diff --git a/api.html b/api.html index d69b62c02..7ba5956ab 100644 --- a/api.html +++ b/api.html @@ -282,7 +282,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/assumptions.html b/assumptions.html index a1890fbfc..ec701735f 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/auto_graph.html b/auto_graph.html index a990eb38e..fa6df419c 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -83,43 +83,43 @@ subgraph TransactionModule["TransactionModule"] subgraph CoreTestElaboratable["elaboratable CoreTestElaboratable"] subgraph Core["core Core"] - Core_DiscardBranchVerify["DiscardBranchVerify"] Core_InitFreeRFFifo["InitFreeRFFifo"] + Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] WishboneMaster_request["request"] WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_result["result"] subgraph Forwarder["result Forwarder"] - Forwarder_read["read"] Forwarder_write["write"] + Forwarder_read["read"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] + WishboneMaster1_result["result"] WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] - Forwarder1_read["read"] Forwarder1_write["write"] + Forwarder1_read["read"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_get_write_response["get_write_response"] - WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_request_read["request_read"] + WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] @@ -146,13 +146,13 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] subgraph Forwarder2["address_fwd Forwarder"] Forwarder2_write["write"] Forwarder2_read["read"] @@ -160,10 +160,10 @@ end subgraph ICache["icache ICache"] ICache_ICache["ICache"] + ICache_issue_req["issue_req"] ICache_ICache1["ICache"] ICache_accept_res["accept_res"] ICache_ICache2["ICache"] - ICache_issue_req["issue_req"] ICache_ICache3["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] @@ -196,29 +196,29 @@ FIFO2_read["read"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_commit["commit"] RRAT_peek["peek"] + RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] - RegisterFile_read2["read2"] RegisterFile_free["free"] RegisterFile_write["write"] + RegisterFile_read1["read1"] + RegisterFile_read2["read2"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_retire["retire"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_peek["peek"] + ReorderBuffer_retire["retire"] + ReorderBuffer_put["put"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] LatencyMeasurer1__start["_start"] LatencyMeasurer1__stop["_stop"] @@ -234,8 +234,8 @@ subgraph Fetch["fetch Fetch"] Fetch_Fetch["Fetch"] Fetch_resume["resume"] - Fetch_stall_exception["stall_exception"] Fetch_Fetch1["Fetch"] + Fetch_stall_exception["stall_exception"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] BasicFifo3_write["write"] BasicFifo3_read["read"] @@ -243,11 +243,11 @@ end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] ExceptionCauseRegister_get["get"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_clear["clear"] + ExceptionCauseRegister_report["report"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] - BasicFifo4_read["read"] BasicFifo4_write["write"] + BasicFifo4_read["read"] end subgraph ConnectTrans["report_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -276,24 +276,24 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] + RSFuncBlock_get_result["get_result"] RSFuncBlock_select["select"] RSFuncBlock_update["update"] RSFuncBlock_insert["insert"] - RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] - RS_select["select"] - RS_update["update"] - RS_insert["insert"] RS_RS["RS"] + RS_take["take"] RS_RS1["RS"] RS_RS2["RS"] RS_RS3["RS"] - RS_take["take"] RS_RS4["RS"] + RS_update["update"] + RS_select["select"] + RS_insert["insert"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph FIFO4["fifo FIFO"] FIFO4_write["write"] FIFO4_read["read"] @@ -303,11 +303,11 @@ WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO5["fifo FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] @@ -330,8 +330,8 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -341,8 +341,8 @@ ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] subgraph FIFO8["fifo FIFO"] - FIFO8_read["read"] FIFO8_write["write"] + FIFO8_read["read"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -353,8 +353,8 @@ PrivilegedFuncUnit_precommit["precommit"] PrivilegedFuncUnit_accept["accept"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] - BasicFifo5_write["write"] BasicFifo5_read["read"] + BasicFifo5_write["write"] end end subgraph WakeupSelect4["wakeup_select_4 WakeupSelect"] @@ -363,8 +363,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_read["read"] Forwarder5_write["write"] + Forwarder5_read["read"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans4["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -386,48 +386,48 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_update["update"] - LSUDummy_LSUDummy["LSUDummy"] LSUDummy_insert["insert"] - LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_update["update"] + LSUDummy_select["select"] LSUDummy_precommit["precommit"] + LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_get_result["get_result"] - LSUDummy_select["select"] + LSUDummy_LSUDummy2["LSUDummy"] subgraph Forwarder6["forwarder Forwarder"] - Forwarder6_read["read"] Forwarder6_write["write"] + Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond0["issue_cond0"] LSURequester_issue_cond2["issue_cond2"] - LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue["issue"] + LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond0["issue_cond0"] LSURequester_accept["accept"] LSURequester_accept_cond1["accept_cond1"] - LSURequester_issue_cond1["issue_cond1"] - LSURequester_issue["issue"] + LSURequester_accept_cond0["accept_cond0"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] CSRUnit_insert["insert"] - CSRUnit_fetch_resume["fetch_resume"] - CSRUnit_select["select"] - CSRUnit_update["update"] CSRUnit_precommit["precommit"] + CSRUnit_fetch_resume["fetch_resume"] CSRUnit_get_result["get_result"] + CSRUnit_select["select"] CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_update["update"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] + MethodTryProduct_method["method"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] - MethodTryProduct_method["method"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_write["write"] Forwarder7_read["read"] + Forwarder7_write["write"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans9["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -444,8 +444,8 @@ end subgraph InterruptController["interrupt_controller InterruptController"] InterruptController_report_interrupt["report_interrupt"] - InterruptController_entry["entry"] InterruptController_mret["mret"] + InterruptController_entry["entry"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] @@ -456,15 +456,15 @@ CSRRegister__fu_read["_fu_read"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_write["_fu_write"] - CSRRegister1_read["read"] CSRRegister1__fu_read["_fu_read"] + CSRRegister1_read["read"] + CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2__fu_write["_fu_write"] - CSRRegister2_write["write"] - CSRRegister2_read["read"] CSRRegister2__fu_read["_fu_read"] + CSRRegister2_read["read"] + CSRRegister2_write["write"] + CSRRegister2__fu_write["_fu_write"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] @@ -475,9 +475,9 @@ CSRRegister3_write["write"] end subgraph CSRRegister4["register_high CSRRegister"] - CSRRegister4_read["read"] - CSRRegister4_write["write"] CSRRegister4__fu_read["_fu_read"] + CSRRegister4_write["write"] + CSRRegister4_read["read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] @@ -495,8 +495,8 @@ end end subgraph FIFO9["fifo_decode FIFO"] - FIFO9_read["read"] FIFO9_write["write"] + FIFO9_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -549,24 +549,24 @@ end subgraph Retirement["retirement Retirement"] Retirement_Retirement_cond1["Retirement_cond1"] - Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement1["Retirement"] Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement4["Retirement"] + Retirement_core_state["core_state"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] + CSRRegister7_write["write"] CSRRegister7_read["read"] CSRRegister7__fu_read["_fu_read"] - CSRRegister7_write["write"] end subgraph CSRRegister8["register_high CSRRegister"] CSRRegister8__fu_read["_fu_read"] - CSRRegister8_read["read"] CSRRegister8_write["write"] + CSRRegister8_read["read"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -587,40 +587,40 @@ end subgraph TransactionManager["transactionManager TransactionManager"] TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] - TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] + TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] + TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] + TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] end end Core_InitFreeRFFifo --> BasicFifo2_write -Retirement_Retirement2 --> BasicFifo2_write -TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write +Retirement_Retirement4 --> BasicFifo2_write TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write +TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write Forwarder2_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request -ICache_ICache <--> HwCounter4__incr -ICache_ICache3 <--> HwCounter3__incr -ICache_ICache3 <--> HwCounter2__incr -ICache_ICache3 <--> HwCounter1__incr -ICache_ICache3 --> Forwarder3_write -ICache_ICache1 --> SimpleCommonBusCacheRefiller_start_refill +ICache_ICache3 <--> HwCounter4__incr +ICache_ICache2 <--> HwCounter3__incr +ICache_ICache2 <--> HwCounter2__incr +ICache_ICache2 <--> HwCounter1__incr +ICache_ICache2 --> Forwarder3_write +ICache_ICache --> SimpleCommonBusCacheRefiller_start_refill +ICache_ICache --> Forwarder2_write ICache_ICache1 --> Forwarder2_write -ICache_ICache2 --> Forwarder2_write -SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache2 -WishboneMasterAdapter_get_read_response --> ICache_ICache2 -Serializer_Serializer1 --> ICache_ICache2 -BasicFifo_read --> ICache_ICache2 -WishboneMaster_result --> ICache_ICache2 -Forwarder_read --> ICache_ICache2 +SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 +WishboneMasterAdapter_get_read_response --> ICache_ICache1 +Serializer_Serializer --> ICache_ICache1 +BasicFifo_read --> ICache_ICache1 +WishboneMaster_result --> ICache_ICache1 +Forwarder_read --> ICache_ICache1 Fetch_Fetch --> ICache_issue_req Fetch_Fetch <--> HwCounter__incr Fetch_Fetch <--> LatencyMeasurer__start @@ -650,7 +650,7 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename -Retirement_Retirement2 --> FRAT_rename +Retirement_Retirement4 --> FRAT_rename TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation @@ -658,18 +658,18 @@ ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write -FIFO12_read --> RSSelection_RSSelection2 -RSSelection_RSSelection2 --> Forwarder8_write +FIFO12_read --> RSSelection_RSSelection3 +RSSelection_RSSelection3 --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection +Forwarder8_read --> RSSelection_RSSelection2 Forwarder8_read --> RSSelection_RSSelection1 -Forwarder8_read --> RSSelection_RSSelection3 RSFuncBlock_select --> RSSelection_RSSelection RS_select --> RSSelection_RSSelection RSSelection_RSSelection --> FIFO13_write +RSSelection_RSSelection2 --> FIFO13_write RSSelection_RSSelection1 --> FIFO13_write -RSSelection_RSSelection3 --> FIFO13_write -RSSelection_RSSelection1 <--> LSUDummy_select -RSSelection_RSSelection3 <--> CSRUnit_select +RSSelection_RSSelection2 <--> LSUDummy_select +RSSelection_RSSelection1 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -685,7 +685,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume -Retirement_Retirement4 --> Fetch_resume +Retirement_Retirement --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -706,7 +706,7 @@ RS_RS4 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write -RS_RS2 --> WakeupSelect2_WakeupSelect +RS_RS3 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -721,7 +721,7 @@ RS_RS1 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write -RS_RS3 --> WakeupSelect4_WakeupSelect +RS_RS2 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -741,10 +741,10 @@ ConnectTrans8_ConnectTrans --> BasicFifo5_write LSUDummy_LSUDummy --> Forwarder6_write TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write -TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write -TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write -TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write -TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write +TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write +TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write +TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write +TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -774,37 +774,37 @@ ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans -ReorderBuffer_peek --> Retirement_Retirement +ReorderBuffer_peek --> Retirement_Retirement1 ReorderBuffer_peek --> Retirement_Retirement3 -ReorderBuffer_peek --> Retirement_Retirement2 -ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement +ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement --> MethodTryProduct_method +ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement +Retirement_Retirement1 --> MethodTryProduct_method ExceptionCauseRegister_get --> Retirement_Retirement3 -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement2 <--> ReorderBuffer_retire -TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire +ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement +Retirement_Retirement4 <--> ReorderBuffer_retire TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire -Retirement_Retirement2 <--> LatencyMeasurer1__stop -TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop +TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire +Retirement_Retirement4 <--> LatencyMeasurer1__stop TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop -FIFO3_read --> Retirement_Retirement2 -FIFO3_read --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop +FIFO3_read --> Retirement_Retirement4 FIFO3_read --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement2 --> HwExpHistogram1__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add +FIFO3_read --> TransactionManager_Retirement_cond0_Retirement +Retirement_Retirement4 --> HwExpHistogram1__add TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add -CoreInstructionCounter_decrement --> Retirement_Retirement2 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add +CoreInstructionCounter_decrement --> Retirement_Retirement4 CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement -RRAT_peek --> Retirement_Retirement2 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement +RRAT_peek --> Retirement_Retirement4 RRAT_peek --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement2 --> RegisterFile_free -TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free +Retirement_Retirement4 --> RegisterFile_free TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free -CSRRegister1_read --> Retirement_Retirement4 -Retirement_Retirement4 <--> ExceptionCauseRegister_clear +TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free +CSRRegister1_read --> Retirement_Retirement +Retirement_Retirement <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -816,19 +816,48 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement2 +TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement2 +TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write +TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write +TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write +TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write +TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry +TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy -Serializer1_Serializer2 --> TransactionManager_accept_cond1_LSUDummy +Serializer1_Serializer --> TransactionManager_accept_cond1_LSUDummy BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy -BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 +BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy -WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 +WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy -Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 -TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy1 -TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy1 +Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy +TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy2 +TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy2 LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy -LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 +LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy +TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 +TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 +TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read +TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer2 +TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write +TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write +TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request +TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request +TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 +TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write +TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3 +TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy +Serializer1_Serializer1 --> TransactionManager_accept_cond0_LSUDummy TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 TransactionManager_Retirement_cond0_Retirement --> RRAT_commit TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment @@ -837,35 +866,6 @@ CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement1 -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement1 -TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write -TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry -TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 -TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy2 -TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy2 -TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy2 -TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 -TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write -TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 -TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write -TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write -TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request -TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request -TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 -Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond0 -TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 -TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 -TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read -TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer3 @@ -876,7 +876,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/components/icache.html b/components/icache.html index 42ab7af40..ac76c0396 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index ea0d301a5..2ffb3663c 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -241,7 +241,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 8887b3ee1..be1c4b726 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -368,7 +368,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/coreblocks.fu.html b/coreblocks.fu.html index ede40fea8..83de9f350 100644 --- a/coreblocks.fu.html +++ b/coreblocks.fu.html @@ -965,7 +965,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/coreblocks.fu.unsigned_multiplication.html b/coreblocks.fu.unsigned_multiplication.html index 082b0ef4a..a6ddbefb8 100644 --- a/coreblocks.fu.unsigned_multiplication.html +++ b/coreblocks.fu.unsigned_multiplication.html @@ -237,7 +237,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/coreblocks.html b/coreblocks.html index f7cefb66c..a98830bb0 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -234,7 +234,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/coreblocks.lsu.html b/coreblocks.lsu.html index 0d9206e5d..787221d79 100644 --- a/coreblocks.lsu.html +++ b/coreblocks.lsu.html @@ -236,7 +236,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/coreblocks.params.html b/coreblocks.params.html index 5ef863bcc..1daeb5209 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -2701,7 +2701,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index 42657879a..41b4d780f 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -598,7 +598,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 158d3d305..a1cb8ce5a 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/coreblocks.stages.html b/coreblocks.stages.html index 7e3c1bfa5..08c2228bd 100644 --- a/coreblocks.stages.html +++ b/coreblocks.stages.html @@ -263,7 +263,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/coreblocks.structs_common.html b/coreblocks.structs_common.html index 42c4afc4a..db9efd1a6 100644 --- a/coreblocks.structs_common.html +++ b/coreblocks.structs_common.html @@ -522,7 +522,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/coreblocks.utils.html b/coreblocks.utils.html index 324478ab6..8e6edfc86 100644 --- a/coreblocks.utils.html +++ b/coreblocks.utils.html @@ -149,7 +149,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/current-graph.html b/current-graph.html index bc9b99aca..91e187d73 100644 --- a/current-graph.html +++ b/current-graph.html @@ -89,43 +89,43 @@

Full transaction-method graph

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diff --git a/development-environment.html b/development-environment.html index 1e8b6df7c..71e7a5741 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/genindex.html b/genindex.html index e1923bc56..facb82102 100644 --- a/genindex.html +++ b/genindex.html @@ -3863,7 +3863,7 @@

Z

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diff --git a/home.html b/home.html index 87a8ddc7b..ee64ff9fb 100644 --- a/home.html +++ b/home.html @@ -129,7 +129,7 @@

Documentation

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diff --git a/index.html b/index.html index a855b9b2e..d35774b8c 100644 --- a/index.html +++ b/index.html @@ -229,7 +229,7 @@

Coreblocks

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html index 80bf4a9e5..3b5cd1515 100644 --- a/miscellany/exceptions-summary.html +++ b/miscellany/exceptions-summary.html @@ -271,7 +271,7 @@

Summary

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diff --git a/modules-coreblocks.html b/modules-coreblocks.html index 0214cd594..b8bea3a4d 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -203,7 +203,7 @@

coreblocks

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/modules-transactron.html b/modules-transactron.html index ad91b1628..de2fa9d42 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -149,7 +149,7 @@

transactron

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diff --git a/problem-checklist.html b/problem-checklist.html index e78673975..d51b0a15f 100644 --- a/problem-checklist.html +++ b/problem-checklist.html @@ -105,7 +105,7 @@

Problem checklist

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diff --git a/py-modindex.html b/py-modindex.html index d12b0fcaf..4b8515c76 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -618,7 +618,7 @@

Python Module Index

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diff --git a/scheduler/overview.html b/scheduler/overview.html index daa73c4d2..8be51bd4b 100644 --- a/scheduler/overview.html +++ b/scheduler/overview.html @@ -146,7 +146,7 @@

More detailed description of each block

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diff --git a/search.html b/search.html index 673bff0e2..841ec4533 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 16:50 2024-03-12. + Last updated on 17:22 2024-03-12.

diff --git a/shared-structs/implementation/rs-impl.html b/shared-structs/implementation/rs-impl.html index 41d139737..e18519bf7 100644 --- a/shared-structs/implementation/rs-impl.html +++ b/shared-structs/implementation/rs-impl.html @@ -252,7 +252,7 @@

Read and clean row

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External interface signals

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Submodules

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