From f70f80a8897b8d408c15b24bee73470dcdb53c2d Mon Sep 17 00:00:00 2001 From: tilk Date: Thu, 14 Mar 2024 11:29:00 +0000 Subject: [PATCH] Hardware Logging (#595) --- .doctrees/api.doctree | Bin 21036 -> 21036 bytes .doctrees/auto_graph.doctree | Bin 44184 -> 44185 bytes .doctrees/coreblocks.peripherals.doctree | Bin 219996 -> 221693 bytes .doctrees/current-graph.doctree | Bin 45405 -> 45406 bytes .doctrees/environment.pickle | Bin 455643 -> 460539 bytes .doctrees/transactron.lib.doctree | Bin 684906 -> 820861 bytes .doctrees/transactron.testing.doctree | Bin 265437 -> 269103 bytes .doctrees/transactron.utils.doctree | Bin 415260 -> 393990 bytes _sources/auto_graph.rst.txt | 342 ++++++++++---------- _sources/transactron.lib.rst.txt | 8 + _sources/transactron.testing.rst.txt | 16 +- _sources/transactron.utils.rst.txt | 8 - api.html | 6 +- assumptions.html | 2 +- auto_graph.html | 344 ++++++++++----------- components/icache.html | 2 +- coreblocks.cache.html | 2 +- coreblocks.frontend.html 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8aiUV7fkaei0aa(Ha($)7 z>r#1j<$aa8o!Rmj#bC^tB`*^^lnp=y8XMmijH4AfRCZ=nTQr(a-b~}3zx3^d)XGjH zyV=9W4Bjoe+dacUT5bW+aQ$jAAFAA6`MSS>uDkWmV2=mb<01CAeg-{mVvi#zw#Z-2 z9=rj6&f0TeE=jJ)a)K?7=1XGA78o*uw?^OW*`S4iRALmK5`N(*cDbtpb8oLjrLJ ztIS*3ci<4;yqWffIB)vr7**nTllju<_glK4xO6^a?^&9SPyV zYp7C(u?N>=GnjTOu!pUpEP+!+$MRHkyj&_*Jf}K}q^f$X60&+5SXItok3Wz}?EjfP zEJ0{tJcwDh&>)JG1 z?_!T*H_+pF_ITwB=<#ay_|H@6@icqfc{)Ab#vYr`pvTMDE@h9;y^tRFu}Aeq^r*AP6X(<8SL{){kRDgC#{n;<$8z>~U=uwa zVvl!irpNo)#Fp)kv%T<>2Vo*4DF!DbJ*iO>~R-+T-KmRkv;Cdf*$v>$G*Ghv6wx6 z%N|d%$C9h)aWH#)f;~RV9w%K(kM->F>Feq7IrjL%E9r4Rdt7xBJ+5buhhIaF$JpcK z*VE%v_TZ+|u3PEtP3&P41(v``6t-s{3?l^0QWv`2?M+cw_b|M&!RJ{fiFL4|1vMtNUi@TpV^ev(IjD=678A>>@0F>aov` zM&?KM`0QLCzIVxI8=QF9fX`wJxZ~Yt-g$01b6+6$FVoWHqqHP zI)UW#l6}innufB84b4@=7dFjT>BIym`bDIpi8M_k$F?e(;%3_U4T+ N_lNWph%Phy{{eowXC?pu diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 8914fae17..3e7ddc44c 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -4,15 +4,15 @@ subgraph TransactionModule["TransactionModule"] subgraph CoreTestElaboratable["elaboratable CoreTestElaboratable"] subgraph Core["core Core"] - Core_InitFreeRFFifo["InitFreeRFFifo"] Core_DiscardBranchVerify["DiscardBranchVerify"] + Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_request["request"] + WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_result["result"] subgraph Forwarder["result Forwarder"] - Forwarder_read["read"] Forwarder_write["write"] + Forwarder_read["read"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] @@ -20,13 +20,13 @@ WishboneMaster1_request["request"] WishboneMaster1_WishboneMaster["WishboneMaster"] subgraph Forwarder1["result Forwarder"] - Forwarder1_read["read"] Forwarder1_write["write"] + Forwarder1_read["read"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] @@ -37,9 +37,9 @@ end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] + WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_read["request_read"] WishboneMasterAdapter1_get_read_response["get_read_response"] - WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] @@ -57,8 +57,8 @@ CoreInstructionCounter_increment["increment"] end subgraph FIFO["fifo_fetch FIFO"] - FIFO_write["write"] FIFO_read["read"] + FIFO_write["write"] end subgraph MethodMap["core_counter_increment_discard_map MethodMap"] MethodMap_method["method"] @@ -72,19 +72,19 @@ end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] subgraph Forwarder2["address_fwd Forwarder"] Forwarder2_read["read"] Forwarder2_write["write"] end end subgraph ICache["icache ICache"] - ICache_accept_res["accept_res"] ICache_ICache["ICache"] - ICache_ICache1["ICache"] ICache_issue_req["issue_req"] + ICache_ICache1["ICache"] ICache_ICache2["ICache"] + ICache_accept_res["accept_res"] ICache_ICache3["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] @@ -108,8 +108,8 @@ HwExpHistogram__add["_add"] end subgraph FIFO1["fifo FIFO"] - FIFO1_write["write"] FIFO1_read["read"] + FIFO1_write["write"] end end subgraph FIFO2["req_fifo FIFO"] @@ -125,24 +125,24 @@ FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_peek["peek"] RRAT_commit["commit"] + RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] RegisterFile_read2["read2"] - RegisterFile_write["write"] - RegisterFile_read1["read1"] RegisterFile_free["free"] + RegisterFile_read1["read1"] + RegisterFile_write["write"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_peek["peek"] + ReorderBuffer_mark_done["mark_done"] ReorderBuffer_retire["retire"] + ReorderBuffer_peek["peek"] ReorderBuffer_get_indices["get_indices"] ReorderBuffer_put["put"] - ReorderBuffer_mark_done["mark_done"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] - LatencyMeasurer1__stop["_stop"] LatencyMeasurer1__start["_start"] + LatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram1["histogram HwExpHistogram"] HwExpHistogram1__add["_add"] end @@ -154,9 +154,9 @@ end subgraph Fetch["fetch Fetch"] Fetch_Fetch["Fetch"] + Fetch_Fetch1["Fetch"] Fetch_resume["resume"] Fetch_stall_exception["stall_exception"] - Fetch_Fetch1["Fetch"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] BasicFifo3_read["read"] BasicFifo3_write["write"] @@ -164,8 +164,8 @@ end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] ExceptionCauseRegister_report["report"] - ExceptionCauseRegister_get["get"] ExceptionCauseRegister_clear["clear"] + ExceptionCauseRegister_get["get"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] BasicFifo4_read["read"] BasicFifo4_write["write"] @@ -197,24 +197,24 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] + RSFuncBlock_insert["insert"] RSFuncBlock_select["select"] RSFuncBlock_update["update"] - RSFuncBlock_insert["insert"] RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] - RS_take["take"] RS_RS["RS"] RS_RS1["RS"] RS_select["select"] RS_RS2["RS"] + RS_update["update"] RS_RS3["RS"] RS_RS4["RS"] RS_insert["insert"] - RS_update["update"] + RS_take["take"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph FIFO4["fifo FIFO"] FIFO4_write["write"] FIFO4_read["read"] @@ -224,22 +224,22 @@ WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_issue["issue"] ShiftFuncUnit_accept["accept"] + ShiftFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] - FIFO5_write["write"] FIFO5_read["read"] + FIFO5_write["write"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO6["fifo_branch_resolved FIFO"] - FIFO6_write["write"] FIFO6_read["read"] + FIFO6_write["write"] end subgraph HwCounter5["perf_jumps HwCounter"] HwCounter5__incr["_incr"] @@ -259,11 +259,11 @@ WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] + ExceptionFuncUnit_accept["accept"] subgraph FIFO8["fifo FIFO"] - FIFO8_read["read"] FIFO8_write["write"] + FIFO8_read["read"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -271,11 +271,11 @@ end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] PrivilegedFuncUnit_issue["issue"] - PrivilegedFuncUnit_precommit["precommit"] PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_precommit["precommit"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] - BasicFifo5_read["read"] BasicFifo5_write["write"] + BasicFifo5_read["read"] end end subgraph WakeupSelect4["wakeup_select_4 WakeupSelect"] @@ -307,42 +307,42 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] + LSUDummy_update["update"] + LSUDummy_select["select"] LSUDummy_LSUDummy["LSUDummy"] LSUDummy_precommit["precommit"] LSUDummy_get_result["get_result"] LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_LSUDummy2["LSUDummy"] - LSUDummy_select["select"] LSUDummy_insert["insert"] - LSUDummy_update["update"] subgraph Forwarder6["forwarder Forwarder"] Forwarder6_write["write"] Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_accept["accept"] - LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue_cond0["issue_cond0"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond2["issue_cond2"] LSURequester_issue["issue"] - LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept["accept"] LSURequester_accept_cond1["accept_cond1"] - LSURequester_issue_cond2["issue_cond2"] + LSURequester_accept_cond0["accept_cond0"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_precommit["precommit"] - CSRUnit_get_result["get_result"] - CSRUnit_fetch_resume["fetch_resume"] CSRUnit_insert["insert"] - CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_fetch_resume["fetch_resume"] CSRUnit_select["select"] CSRUnit_update["update"] + CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_get_result["get_result"] + CSRUnit_precommit["precommit"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] + MethodTryProduct_method["method"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] - MethodTryProduct_method["method"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] @@ -364,28 +364,28 @@ ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"] end subgraph InterruptController["interrupt_controller InterruptController"] - InterruptController_report_interrupt["report_interrupt"] InterruptController_entry["entry"] InterruptController_mret["mret"] + InterruptController_report_interrupt["report_interrupt"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] - CSRRegister__fu_read["_fu_read"] - CSRRegister_write["write"] CSRRegister__fu_write["_fu_write"] + CSRRegister_write["write"] + CSRRegister__fu_read["_fu_read"] end subgraph CSRRegister1["mtvec CSRRegister"] + CSRRegister1__fu_read["_fu_read"] CSRRegister1__fu_write["_fu_write"] CSRRegister1_read["read"] - CSRRegister1__fu_read["_fu_read"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2_read["read"] + CSRRegister2__fu_read["_fu_read"] CSRRegister2__fu_write["_fu_write"] CSRRegister2_write["write"] - CSRRegister2__fu_read["_fu_read"] + CSRRegister2_read["read"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] @@ -396,8 +396,8 @@ CSRRegister3__fu_read["_fu_read"] end subgraph CSRRegister4["register_high CSRRegister"] - CSRRegister4_read["read"] CSRRegister4__fu_read["_fu_read"] + CSRRegister4_read["read"] CSRRegister4_write["write"] end end @@ -405,13 +405,13 @@ DoubleCounterCSR1_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] CSRRegister5_write["write"] - CSRRegister5_read["read"] CSRRegister5__fu_read["_fu_read"] + CSRRegister5_read["read"] end subgraph CSRRegister6["register_high CSRRegister"] CSRRegister6_write["write"] - CSRRegister6__fu_read["_fu_read"] CSRRegister6_read["read"] + CSRRegister6__fu_read["_fu_read"] end end end @@ -427,8 +427,8 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO10["alloc_rename_buf FIFO"] - FIFO10_write["write"] FIFO10_read["read"] + FIFO10_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -470,19 +470,19 @@ end subgraph Retirement["retirement Retirement"] Retirement_Retirement["Retirement"] - Retirement_core_state["core_state"] Retirement_Retirement1["Retirement"] - Retirement_Retirement2["Retirement"] Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_Retirement_cond0["Retirement_cond0"] + Retirement_core_state["core_state"] + Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] Retirement_Retirement4["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] - CSRRegister7__fu_read["_fu_read"] - CSRRegister7_write["write"] CSRRegister7_read["read"] + CSRRegister7_write["write"] + CSRRegister7__fu_read["_fu_read"] end subgraph CSRRegister8["register_high CSRRegister"] CSRRegister8_read["read"] @@ -507,41 +507,41 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] - TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] - TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] + TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] + TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] end end Core_InitFreeRFFifo --> BasicFifo2_write - Retirement_Retirement3 --> BasicFifo2_write - TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write - TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write + Retirement_Retirement2 --> BasicFifo2_write + TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write + TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write Forwarder2_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request - ICache_ICache2 <--> HwCounter4__incr - ICache_ICache <--> HwCounter3__incr - ICache_ICache <--> HwCounter2__incr - ICache_ICache <--> HwCounter1__incr - ICache_ICache --> Forwarder3_write - ICache_ICache3 --> SimpleCommonBusCacheRefiller_start_refill - ICache_ICache3 --> Forwarder2_write - ICache_ICache1 --> Forwarder2_write - SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 - WishboneMasterAdapter_get_read_response --> ICache_ICache1 - Serializer_Serializer --> ICache_ICache1 - BasicFifo_read --> ICache_ICache1 - WishboneMaster_result --> ICache_ICache1 - Forwarder_read --> ICache_ICache1 + ICache_ICache3 <--> HwCounter4__incr + ICache_ICache1 <--> HwCounter3__incr + ICache_ICache1 <--> HwCounter2__incr + ICache_ICache1 <--> HwCounter1__incr + ICache_ICache1 --> Forwarder3_write + ICache_ICache --> SimpleCommonBusCacheRefiller_start_refill + ICache_ICache --> Forwarder2_write + ICache_ICache2 --> Forwarder2_write + SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache2 + WishboneMasterAdapter_get_read_response --> ICache_ICache2 + Serializer_Serializer1 --> ICache_ICache2 + BasicFifo_read --> ICache_ICache2 + WishboneMaster_result --> ICache_ICache2 + Forwarder_read --> ICache_ICache2 Fetch_Fetch1 --> ICache_issue_req Fetch_Fetch1 <--> HwCounter__incr Fetch_Fetch1 <--> LatencyMeasurer__start @@ -571,26 +571,26 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename - Retirement_Retirement3 --> FRAT_rename - TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename + Retirement_Retirement2 --> FRAT_rename + TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write - FIFO12_read --> RSSelection_RSSelection2 - RSSelection_RSSelection2 --> Forwarder8_write + FIFO12_read --> RSSelection_RSSelection1 + RSSelection_RSSelection1 --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection3 - Forwarder8_read --> RSSelection_RSSelection1 Forwarder8_read --> RSSelection_RSSelection + Forwarder8_read --> RSSelection_RSSelection2 RSFuncBlock_select --> RSSelection_RSSelection3 RS_select --> RSSelection_RSSelection3 RSSelection_RSSelection3 --> FIFO13_write - RSSelection_RSSelection1 --> FIFO13_write RSSelection_RSSelection --> FIFO13_write - RSSelection_RSSelection1 <--> LSUDummy_select - RSSelection_RSSelection <--> CSRUnit_select + RSSelection_RSSelection2 --> FIFO13_write + RSSelection_RSSelection <--> LSUDummy_select + RSSelection_RSSelection2 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -616,7 +616,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update - RS_RS --> WakeupSelect_WakeupSelect + RS_RS4 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -624,10 +624,10 @@ RS_take --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO4_write - RS_RS2 --> WakeupSelect1_WakeupSelect + RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write - RS_RS3 --> WakeupSelect2_WakeupSelect + RS_RS2 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -639,7 +639,7 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write - RS_RS4 --> WakeupSelect3_WakeupSelect + RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write RS_RS1 --> WakeupSelect4_WakeupSelect @@ -661,11 +661,11 @@ CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write LSUDummy_LSUDummy --> Forwarder6_write - TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write - TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write - TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write + TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write + TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write + TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -687,43 +687,43 @@ LSUDummy_get_result --> ConnectTrans2_ConnectTrans Forwarder6_read --> ConnectTrans2_ConnectTrans CSRUnit_get_result --> ConnectTrans3_ConnectTrans - MethodTryProduct_MethodTryProduct2 --> PrivilegedFuncUnit_precommit - MethodTryProduct_MethodTryProduct2 <--> InterruptController_mret - MethodTryProduct_MethodTryProduct --> LSUDummy_precommit + MethodTryProduct_MethodTryProduct --> PrivilegedFuncUnit_precommit + MethodTryProduct_MethodTryProduct <--> InterruptController_mret + MethodTryProduct_MethodTryProduct2 --> LSUDummy_precommit MethodTryProduct_MethodTryProduct1 --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans - ReorderBuffer_peek --> Retirement_Retirement2 - ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> Retirement_Retirement3 - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement2 --> MethodTryProduct_method - ExceptionCauseRegister_get --> Retirement_Retirement4 - ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 - ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement3 <--> ReorderBuffer_retire - TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire - TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire - Retirement_Retirement3 <--> LatencyMeasurer1__stop - TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop - TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop - FIFO3_read --> Retirement_Retirement3 - FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 - FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement3 --> HwExpHistogram1__add - TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add - TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add - CoreInstructionCounter_decrement --> Retirement_Retirement3 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 - RRAT_peek --> Retirement_Retirement3 - RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement3 --> RegisterFile_free - TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free - TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free + ReorderBuffer_peek --> Retirement_Retirement1 + ReorderBuffer_peek --> Retirement_Retirement2 + ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement + ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement3 --> MethodTryProduct_method + ExceptionCauseRegister_get --> Retirement_Retirement1 + ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement + ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement2 <--> ReorderBuffer_retire + TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire + TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire + Retirement_Retirement2 <--> LatencyMeasurer1__stop + TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop + TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop + FIFO3_read --> Retirement_Retirement2 + FIFO3_read --> TransactionManager_Retirement_cond1_Retirement + FIFO3_read --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement2 --> HwExpHistogram1__add + TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add + TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add + CoreInstructionCounter_decrement --> Retirement_Retirement2 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement + CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement + RRAT_peek --> Retirement_Retirement2 + RRAT_peek --> TransactionManager_Retirement_cond1_Retirement + Retirement_Retirement2 --> RegisterFile_free + TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free + TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free CSRRegister1_read --> Retirement_Retirement Retirement_Retirement <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment @@ -737,53 +737,53 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt - TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement1 - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write - TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry - TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry - TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit - TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment - CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write - CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write - TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 - TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy2 - TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy2 - TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy2 - TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue - TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue - TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 - TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read - TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer - TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write - TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request - TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 - TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy1 - TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy1 - LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue + TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue + TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy2 + TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2 LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 - TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 - Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond0 - BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 + LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 + Serializer1_Serializer1 --> TransactionManager_LSUDummy_accept_cond1 BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 - WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 + BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 - Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 + WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 - TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 - TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write - TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer1 - TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 - Serializer1_Serializer2 --> TransactionManager_LSUDummy_accept_cond1 + Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 + Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement4 + TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement4 + TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write + TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write + TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write + TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write + TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry + TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry + TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_cond0_Retirement --> RRAT_commit + TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment + CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write + CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write + TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr + TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 + TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write + TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer2 + TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write + TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write + TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request + TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request + TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 + TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read + TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer diff --git a/_sources/transactron.lib.rst.txt b/_sources/transactron.lib.rst.txt index 1e131e50f..6136a9de0 100644 --- a/_sources/transactron.lib.rst.txt +++ b/_sources/transactron.lib.rst.txt @@ -44,6 +44,14 @@ transactron.lib.fifo module :undoc-members: :show-inheritance: +transactron.lib.logging module +------------------------------ + +.. automodule:: transactron.lib.logging + :members: + :undoc-members: + :show-inheritance: + transactron.lib.metrics module ------------------------------ diff --git a/_sources/transactron.testing.rst.txt b/_sources/transactron.testing.rst.txt index 5fc1e426e..7fa085555 100644 --- a/_sources/transactron.testing.rst.txt +++ b/_sources/transactron.testing.rst.txt @@ -4,14 +4,6 @@ transactron.testing package Submodules ---------- -transactron.testing.assertion module ------------------------------------- - -.. automodule:: transactron.testing.assertion - :members: - :undoc-members: - :show-inheritance: - transactron.testing.functions module ------------------------------------ @@ -36,6 +28,14 @@ transactron.testing.infrastructure module :undoc-members: :show-inheritance: +transactron.testing.logging module +---------------------------------- + +.. automodule:: transactron.testing.logging + :members: + :undoc-members: + :show-inheritance: + transactron.testing.profiler module ----------------------------------- diff --git a/_sources/transactron.utils.rst.txt b/_sources/transactron.utils.rst.txt index 7761c4d15..d864a4557 100644 --- a/_sources/transactron.utils.rst.txt +++ b/_sources/transactron.utils.rst.txt @@ -12,14 +12,6 @@ Subpackages Submodules ---------- -transactron.utils.assertion module ----------------------------------- - -.. automodule:: transactron.utils.assertion - :members: - :undoc-members: - :show-inheritance: - transactron.utils.assign module ------------------------------- diff --git a/api.html b/api.html index 5a9044c0d..5b806fd80 100644 --- a/api.html +++ b/api.html @@ -220,6 +220,7 @@

transactrontransactron.lib.connectors module
  • transactron.lib.dependencies module
  • transactron.lib.fifo module
    • +
  • transactron.lib.logging module
  • transactron.lib.metrics module
  • transactron.lib.reqres module
  • transactron.lib.simultaneous module
    • @@ -230,10 +231,10 @@

    transactrontransactron.testing package
  • get_src_loc() (in module transactron.utils.transactron_helpers) +
    • +
  • get_trigger_bit() (in module transactron.lib.logging)
  • get_write_response (coreblocks.peripherals.bus_adapter.BusMasterInterface attribute)
    • @@ -1977,6 +1995,8 @@

    H

    - + + + + @@ -562,11 +567,6 @@

    Python Module Index

    - - -
    -
  • locked (transactron.profiler.RunStat attribute) +
    • +
  • log() (transactron.lib.logging.HardwareLogger method) +
    • +
  • logger_name (transactron.lib.logging.LogRecordInfo attribute)
  • LOGIC (coreblocks.params.optypes.OpType attribute) +
    • +
  • LogKey (class in transactron.lib.logging) +
    • +
  • LogRecord (class in transactron.lib.logging) +
    • +
  • LogRecordInfo (class in transactron.lib.logging) +
    • +
  • logs (transactron.utils.gen.GenerationInfo attribute)
  • LSUBlockComponent (class in coreblocks.lsu.dummyLsu)
    • @@ -2226,9 +2262,9 @@

    M

  • (transactron.profiler.RunStatNode static method)
    • -
  • make_assert_handler() (in module transactron.testing.assertion) -
  • make_hashable() (in module transactron.utils.data_repr) +
    • +
  • make_logging_process() (in module transactron.testing.logging)
  • ManyToOneConnectTrans (class in transactron.lib.connectors)
    • @@ -2475,6 +2511,8 @@

    M

  • transactron.lib.dependencies
  • transactron.lib.fifo +
    • +
  • transactron.lib.logging
  • transactron.lib.metrics
    • @@ -2489,14 +2527,14 @@

    M

  • transactron.profiler
  • transactron.testing -
    • -
  • transactron.testing.assertion
  • transactron.testing.functions
  • transactron.testing.gtkw_extension
  • transactron.testing.infrastructure +
    • +
  • transactron.testing.logging
  • transactron.testing.profiler
    • @@ -2513,8 +2551,6 @@

    M

  • transactron.utils.amaranth_ext.elaboratables
  • transactron.utils.amaranth_ext.functions -
    • -
  • transactron.utils.assertion
  • transactron.utils.assign
    • @@ -2720,6 +2756,8 @@

    P

  • params (coreblocks.peripherals.bus_adapter.BusMasterInterface attribute) +
    • +
  • parse_logging_level() (in module transactron.testing.logging)
  • pc (coreblocks.params.layouts.CommonLayoutFields attribute)
    • @@ -3027,16 +3065,18 @@

    S

  • SchedulerLayouts (class in coreblocks.params.layouts)
    • -
  • schema() (transactron.lib.metrics.MetricModel class method) +
  • schema() (transactron.lib.logging.LogRecordInfo class method)
    		• -
  • to_dict() (transactron.lib.metrics.MetricModel method) +
  • to_dict() (transactron.lib.logging.LogRecordInfo method)
    • -
  • to_json() (transactron.lib.metrics.MetricModel method) +
  • to_json() (transactron.lib.logging.LogRecordInfo method)
  • Transformer (class in transactron.lib.transformers) +
    • +
  • trigger (transactron.lib.logging.LogRecord attribute) +
    • +
  • trigger_location (transactron.utils.gen.GeneratedLog attribute)
  • trivial_roundrobin_cc_scheduler() (in module transactron.core)
    • @@ -3701,6 +3747,8 @@

    W

  • wait_until_done() (transactron.testing.testbenchio.TestbenchIO method)
  • WakeupSelect (class in coreblocks.scheduler.wakeup_select) +
    • +
  • warning() (transactron.lib.logging.HardwareLogger method)
  • wb (coreblocks.peripherals.wishbone.PipelinedWishboneMaster attribute)
    • @@ -3717,11 +3765,11 @@

    W

  • width (transactron.lib.metrics.MetricRegisterModel attribute)
  • WishboneArbiter (class in coreblocks.peripherals.wishbone) -
    • -
  • WishboneInterface (class in coreblocks.peripherals.wishbone)
    		•     transactron.lib.fifo
        + transactron.lib.logging +
        @@ -505,22 +510,22 @@

    Python Module Index

        - transactron.testing.assertion + transactron.testing.functions
        - transactron.testing.functions + transactron.testing.gtkw_extension
        - transactron.testing.gtkw_extension + transactron.testing.infrastructure
        - transactron.testing.infrastructure + transactron.testing.logging
        transactron.utils.amaranth_ext.functions
        - transactron.utils.assertion -
        @@ -618,7 +618,7 @@

    Python Module Index

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:48 2024-03-14. + Last updated on 11:28 2024-03-14.

    diff --git a/scheduler/overview.html b/scheduler/overview.html index 48429d785..0a2b0b6d7 100644 --- a/scheduler/overview.html +++ b/scheduler/overview.html @@ -146,7 +146,7 @@

    More detailed description of each block

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:48 2024-03-14. + Last updated on 11:28 2024-03-14.

    diff --git a/search.html b/search.html index 4a7055c1e..8915a7843 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:48 2024-03-14. + Last updated on 11:28 2024-03-14.

    diff --git a/searchindex.js b/searchindex.js index 9067cef2e..4898666f5 100644 --- a/searchindex.js +++ b/searchindex.js @@ -1 +1 @@ -Search.setIndex({"docnames": ["api", "assumptions", "auto_graph", "components/icache", "coreblocks", "coreblocks.cache", "coreblocks.frontend", "coreblocks.fu", "coreblocks.fu.unsigned_multiplication", "coreblocks.lsu", "coreblocks.params", "coreblocks.peripherals", "coreblocks.scheduler", "coreblocks.stages", "coreblocks.structs_common", "coreblocks.utils", "current-graph", "development-environment", "home", "index", "miscellany/exceptions-summary", "modules-coreblocks", "modules-transactron", "problem-checklist", "scheduler/overview", "shared-structs/implementation/rs-impl", "shared-structs/rs", "synthesis/synthesis", "transactions", "transactron", "transactron.lib", "transactron.testing", "transactron.utils", "transactron.utils.amaranth_ext"], "filenames": ["api.md", "assumptions.md", "auto_graph.rst", "components/icache.md", "coreblocks.rst", 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20], "occur": [3, 5], "arbitrarili": 3, "long": [3, 26, 27, 30], "ensur": [3, 27], "ani": [3, 6, 11, 12, 20, 23, 30, 31, 32, 33], "refetch": 3, "howev": [3, 30], "guarante": [3, 20], "have": [3, 9, 11, 13, 14, 17, 20, 23, 27, 28, 29, 30, 31, 32, 33], "alreadi": [3, 13, 20, 30, 32], "been": 3, "still": [3, 20, 26, 29], "wait": [3, 11, 13, 14, 17, 20, 25, 26, 29, 31], "accept": [3, 5, 7, 8, 14, 15, 27, 29, 30, 32], "inform": [3, 9, 12, 17, 29, 30, 32], "regard": 3, "error": [3, 5, 10, 11, 29, 30, 32], "mean": [3, 12, 17, 26, 29, 30], "dure": [3, 9, 19, 24, 30, 31], "line": [3, 5, 10, 17, 19], "subsequ": 3, "access": [3, 10, 11, 14, 20, 28, 30, 31, 32], "trigger": [3, 14], "which": [3, 5, 6, 7, 9, 10, 11, 12, 13, 17, 18, 20, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33], "most": [3, 20, 28, 29, 30], "like": [3, 6, 20, 28, 29, 30], "For": [3, 10, 17, 25, 26, 28, 29, 30, 32, 33], "32": [3, 7, 8, 10, 11, 20, 28, 30], "128": [3, 10], "set": [3, 5, 6, 7, 9, 10, 12, 13, 14, 19, 25, 27, 29, 30, 32, 33], "size": [3, 10, 11, 20, 28, 30, 32], "equal": [3, 14], "31": [3, 10], "15": [3, 10], "14": [3, 10], "13": [3, 10], "12": [3, 10], "11": [3, 10, 17, 27], "10": [3, 10, 20], "09": 3, "08": 3, "07": 3, "06": [3, 31], "05": 3, "04": 3, "03": 3, "02": 3, "01": 3, "00": 3, "tag": [3, 11, 20, 25, 26], "index": [3, 10, 29, 33], "offset": 3, "unsigned_multipl": [4, 7], "common": [4, 7, 11, 30, 32], "fast_recurs": [4, 7], "sequenc": [4, 7, 12, 30], "shift": [4, 7, 10], "class": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 28, 29, 30, 31, 32, 33], "base": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 20, 29, 30, 31, 32, 33], "elaborat": [4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 28, 29, 30, 31, 32], "__init__": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 28, 29, 30, 31, 32, 33], "gen_param": [4, 6, 7, 8, 9, 10, 12, 13, 14], "wb_instr_bu": 4, "wishboneinterfac": [4, 11], "wb_data_bu": 4, "cacheinterfac": [5, 6], "A": [5, 10, 11, 27, 28, 29, 30, 32], "simpl": [5, 6, 9, 12, 13, 29, 30, 32, 33], "associ": [5, 10, 30], "instruct": [5, 6, 7, 9, 10, 12, 13, 14, 19, 20, 24, 25, 27], "replac": [5, 8, 10, 25], "polici": 5, "pseudo": 5, "random": [5, 31], "scheme": 5, "everi": [5, 7, 11, 17, 27, 29, 30], "time": [5, 11, 14, 20, 29, 30], "trash": 5, "we": [5, 9, 11, 13, 20, 24, 25, 26, 27, 28, 31], "select": [5, 6, 7, 9, 11, 12, 13, 14, 15, 17], "next": [5, 6, 9, 12, 13, 14, 20, 29, 33], "wai": [5, 7, 11, 17, 20, 27, 28, 29, 30, 32], "keep": [5, 29], "global": [5, 14, 20], "counter": [5, 10, 14, 17, 30], "abstract": [5, 8, 10, 27, 30, 32], "awai": 5, "need": [5, 11, 17, 20, 25, 28, 29], "two": [5, 10, 14, 20, 23, 27, 28, 29, 30, 31, 32], "refiller_start": 5, "call": [5, 7, 12, 14, 17, 23, 25, 28, 29, 30, 31, 32], "whenev": 5, "refiller_accept": 5, "readi": [5, 9, 10, 11, 12, 13, 14, 19, 25, 29, 30], "word": [5, 10], "written": [5, 14, 26, 27, 30], "last": [5, 10, 12, 14, 29, 30], "when": [5, 11, 14, 17, 20, 23, 25, 26, 28, 29, 30, 31, 32, 33], "either": [5, 11, 28, 29, 30, 32, 33], "transfer": [5, 11, 29, 30], "over": [5, 14, 29, 30], "shouldn": [5, 27], "t": [5, 6, 9, 10, 17, 20, 23, 25, 27, 28, 29, 30, 31, 32], "until": [5, 20, 30], "start": [5, 7, 9, 10, 11, 20, 29, 30], "icachelayout": [5, 10], "icacheparamet": [5, 10], "cacherefillerinterfac": 5, "none": [5, 6, 7, 9, 10, 13, 14, 29, 30, 31, 32, 33], "paramet": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 28, 29, 30, 31, 32, 33], "instanc": [5, 6, 7, 9, 12, 13, 27, 29, 30, 31, 32], "us": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 19, 20, 23, 27, 28, 29, 30, 31, 32, 33], "creat": [5, 8, 11, 17, 27, 28, 29, 30, 31, 32, 33], "gener": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 18, 20, 23, 27, 29, 30, 31, 32], "input": [5, 6, 7, 11, 13, 14, 20, 25, 26, 28, 29, 30, 33], "start_refil": 5, "accept_refil": 5, "deserialize_addr": 5, "raw_addr": 5, "valu": [5, 6, 7, 9, 10, 11, 12, 13, 14, 19, 23, 25, 26, 29, 30, 31, 32, 33], "dict": [5, 11, 28, 29, 30, 31, 32, 33], "str": [5, 10, 11, 29, 30, 31, 32, 33], "amaranth": [5, 6, 7, 10, 11, 23, 27, 28, 29, 30, 31, 32, 33], "hdl": [5, 6, 7, 10, 29, 30, 31, 32, 33], "_ast": [5, 6, 7, 10, 29, 30, 31, 32, 33], "serialize_addr": 5, "addr": [5, 9, 10, 11, 30], "view": [5, 7, 9, 29, 30, 31, 32, 33], "icachebypass": 5, "bus_mast": 5, "busmasterinterfac": [5, 9, 10, 11], "haselabor": [5, 11, 15, 29, 30, 31, 33], "interfac": [5, 6, 8, 9, 11, 12, 13, 14, 19, 27, 28, 29, 30], "whole": [5, 18, 20, 30], "given": [5, 7, 9, 10, 17, 25, 28, 29, 30, 31, 32, 33], "simplecommonbuscacherefil": 5, "decodestag": 6, "decod": [6, 7, 10, 12, 29, 32], "transact": [6, 10, 11, 14, 17, 19, 25, 29, 30, 33], "instanti": [6, 29], "instrdecod": 6, "make": [6, 7, 17, 18, 20, 23, 27, 28, 29, 31], "actual": [6, 17, 19, 28], "combinatori": [6, 28], "manner": [6, 11], "get_raw": 6, "push_decod": 6, "raw": 6, "previou": [6, 11, 20, 30], "step": [6, 12, 17, 20, 27, 28], "e": [6, 10, 17, 20, 23, 28, 30, 32, 33], "g": [6, 10, 17, 20, 23, 28, 30, 32, 33], "fetchlayout": [6, 10], "send": [6, 10, 11, 12, 13], "It": [6, 7, 8, 9, 11, 12, 13, 17, 20, 24, 25, 27, 28, 29, 30, 31, 32, 33], "describ": [6, 10, 12, 13, 20, 27, 29, 30, 31], "decodelayout": [6, 10, 12], "pc": [6, 10, 14, 19], "insid": [6, 27, 28, 29, 30], "increment": [6, 14], "ilen_byt": 6, "cont": [6, 31], "unalignedfetch": 6, "work": [6, 12, 20, 23, 27, 28, 29], "unalign": 6, "perform": [6, 7, 8, 10, 12, 14, 17, 27, 28, 29, 30, 32, 33], "elementari": 6, "compon": [6, 10, 11, 18, 29, 30], "opcod": [6, 10, 25, 26], "funct3": [6, 7, 10], "etc": [6, 10, 28], "connect": [6, 11, 13, 14, 20, 28, 29, 30], "via": [6, 28, 29], "its": [6, 12, 13, 14, 20, 27, 28, 29, 30, 32, 33], "attribut": [6, 7, 8, 9, 10, 11, 13, 14, 29, 30, 32, 33], "signal": [6, 7, 9, 10, 11, 19, 23, 29, 30, 31, 32, 33], "ilen": [6, 10], "out": [6, 7, 8, 11, 13, 18, 19, 29, 30, 33], "identifi": [6, 10, 25, 30, 32], "funct3_v": 6, "1": [6, 7, 8, 10, 12, 14, 20, 25, 26, 27, 28, 29, 30, 31, 32, 33], "funct7": [6, 7, 10], "seven": 6, "funct7_v": 6, "funct12": [6, 10], "twelv": 6, "funct12_v": 6, "rd": [6, 10], "reg_cnt_log": 6, "address": [6, 9, 10, 11, 14, 19, 20], "regist": [6, 10, 12, 14, 20, 24, 30, 32], "rd_v": 6, "rs1": [6, 10], "hold": [6, 11, 14, 30], "first": [6, 7, 10, 12, 20, 25, 26, 27, 28, 30, 31, 32], "rs1_v": 6, "take": [6, 11, 13, 24, 25, 28, 29, 30, 31, 32], "form": [6, 10, 14, 20, 27, 30], "rs2": [6, 10], "second": [6, 7, 10, 12, 25, 26, 27, 30], "rs2_v": 6, "imm": [6, 10], "xlen": [6, 7, 10, 14, 32], "immedi": [6, 10, 11], "provid": [6, 7, 10, 12, 14, 27, 28, 30, 31, 32], "were": [6, 20, 28], "succ": 6, "fencetarget": [6, 10], "successor": 6, "fenc": [6, 10], "pred": 6, "predecessor": 6, "fm": 6, "fencefm": [6, 10], "mode": [6, 10, 17, 20], "csr_alen": [6, 10], "control": [6, 10, 11, 14, 27, 29, 30, 33], "sourc": [6, 10, 12, 17, 25, 29, 30, 32], "type": [6, 7, 10, 17, 29, 30, 31, 32], "defin": [6, 9, 14, 28, 29, 30, 32, 33], "kind": [6, 7, 12, 30, 32], "illeg": 6, "wa": [6, 10, 14, 17, 20, 28, 29, 30, 32], "success": [6, 11, 31], "do": [6, 10, 20, 23, 28, 29], "fit": 6, "support": [6, 9, 10, 12, 17, 19, 29, 30], "constructor": [6, 28, 29, 32], "encod": [6, 20, 29, 32, 33], "object": [6, 7, 9, 10, 11, 27, 28, 29, 30, 31, 32], "repres": [6, 14, 29, 30], "singl": [6, 7, 8, 10, 12, 13, 14, 28, 29, 30, 32], "option": [6, 7, 10, 14, 17, 28, 29, 30, 31, 32, 33], "exist": [6, 28, 32], "instr_type_overrid": 6, "instrtyp": [6, 10], "specifi": [6, 10, 11, 14, 26, 30, 31, 32], "determin": [6, 20, 27, 30, 32], "instrust": 6, "almost": 6, "correct": [6, 9, 20, 25, 26, 27], "rd_zero": 6, "bool": [6, 7, 9, 10, 14, 29, 30, 31, 32, 33], "field": [6, 9, 10, 14, 17, 25, 26, 28, 29, 30, 31, 32], "constant": 6, "zero": [6, 10, 14, 25, 30, 33], "other": [6, 14, 17, 19, 28, 29, 30, 33], "accordingli": 6, "default": [6, 11, 17, 28, 29, 30, 32, 33], "fals": [6, 7, 9, 10, 17, 28, 29, 30, 32, 33], "rs1_zero": 6, "instrdecompress": 6, "decompr_reg": 6, "rvc_reg": 6, "instr_mux": 6, "sel": [6, 11], "list": [6, 7, 10, 11, 14, 17, 19, 23, 27, 29, 30, 31, 32, 33], "int": [6, 7, 8, 9, 10, 11, 13, 14, 29, 30, 31, 32, 33], "enum": [6, 7, 10, 29, 30, 31, 32], "valuecast": [6, 10, 29, 30, 31, 32], "tupl": [6, 7, 10, 11, 12, 13, 14, 29, 30, 32], "is_instr_compress": 6, "alucompon": [7, 10], "functionalcomponentparam": [7, 10, 13], "zba_en": 7, "zbb_enabl": 7, "get_modul": [7, 9, 10, 13, 14], "funcunit": [7, 10, 13, 15], "get_optyp": [7, 9, 10, 13, 14], "alufuncunit": 7, "alu_fn": 7, "alufn": 7, "divcompon": 7, "ipc": [7, 27], "3": [7, 10, 14, 17, 29, 32], "div_fn": 7, "divfn": 7, "decodermanag": 7, "fn": 7, "intflag": [7, 10, 29], "div": [7, 10], "divu": [7, 10], "2": [7, 8, 10, 11, 14, 27, 29, 30, 32], "rem": [7, 10], "remu": [7, 10], "8": [7, 8, 10, 11, 29, 30], "__new__": [7, 10, 14, 29], "get_instruct": 7, "valid": [7, 10, 11, 12, 25, 30, 32, 33], "implement": [7, 9, 11, 18, 19, 20, 24, 30, 32, 33], "format": [7, 17, 27, 28, 29, 30, 32], "divunit": 7, "get_input": 7, "arg": [7, 11, 28, 29, 30, 31, 32, 33], "exceptionfuncunit": 7, "unit_fn": 7, "exceptionunitfn": 7, "exceptionunitcompon": [7, 10], "respons": [7, 11, 12, 17, 29, 30, 31], "decode_fn": 7, "exec_fn": [7, 10], "op": [7, 10], "check_optyp": 7, "manag": [7, 17, 19, 29, 30, 32], "enumer": 7, "get_decod": 7, "auto": 7, "pass": [7, 13, 14, 17, 19, 27, 29, 30, 31, 32], "contructor": 7, "get_funct": 7, "get_op_typ": 7, "jumpbranchfuncunit": 7, "jb_fn": 7, "jumpbranchfn": 7, "jumpcompon": [7, 10], "mulcompon": 7, "mul_unit_typ": 7, "multyp": 7, "dsp_width": [7, 8], "mul_fn": 7, "mulfn": 7, "hot": [7, 20, 33], "wire": [7, 32], "5": [7, 10, 24, 30, 31], "differ": [7, 11, 13, 17, 18, 20, 23, 27, 29, 30, 32], "mul": [7, 10], "mulh": [7, 10], "mulhsu": [7, 10], "mulhu": [7, 10], "intenum": [7, 10, 14], "recursive_mul": 7, "fastest": 7, "multipli": [7, 8], "onli": [7, 11, 14, 20, 27, 28, 29, 30, 31, 32], "costli": [7, 20], "term": 7, "resourc": [7, 14, 20, 27, 28], "sequence_mul": 7, "dsp": [7, 8], "balanc": 7, "between": [7, 17, 20, 28, 29, 30, 32, 33], "cost": [7, 19, 28], "shift_mul": 7, "cheapest": 7, "russian": [7, 8], "peasant": [7, 8], "algorithm": [7, 8], "mulunit": 7, "unsign": [7, 8], "integ": [7, 10, 32], "standard": [7, 14, 20, 27, 33], "funcunitlayout": [7, 10, 12, 13], "comput": [7, 8, 9, 14, 20, 30, 32], "mul_typ": 7, "privilegedfn": 7, "mret": [7, 10], "classmethod": [7, 29, 30, 32], "privilegedfuncunit": 7, "gp": [7, 10, 14], "privilegedunitcompon": [7, 10], "shiftfuncunit": 7, "shift_unit_fn": 7, "shiftunitfn": 7, "shiftunitcompon": [7, 10], "clmultipli": 7, "carri": [7, 10, 27], "less": [7, 10], "product": [7, 30], "i1": [7, 8], "n": [7, 8, 10], "factor": 7, "i2": [7, 8], "reset": [7, 14, 19, 29], "new": [7, 9, 11, 14, 19, 20, 29, 30, 32, 33], "busi": 7, "while": [7, 29, 31], "progress": 7, "bit_width": 7, "recursion_depth": 7, "width": [7, 8, 10, 11, 14, 30, 32, 33], "depth": [7, 11, 27, 30], "recurs": [7, 8, 27, 28, 29, 32], "parallel": 7, "assum": [7, 13, 20, 30, 32], "power": [7, 32], "iterative_modul": 7, "recursive_modul": 7, "zbccompon": 7, "zbc_fn": 7, "zbcfn": 7, "clmul": [7, 10], "clmulh": [7, 10], "clmulr": [7, 10], "zbcunit": 7, "execut": [7, 10, 11, 12, 13, 17, 19, 24, 26, 28, 29, 30, 31], "zbsfunction": 7, "in1": 7, "in2": 7, "zbscompon": 7, "bclr": [7, 10], "bext": [7, 10], "binv": [7, 10], "bset": [7, 10], "zbsunit": 7, "zbs_fn": 7, "dspmulunit": 8, "clock": [8, 24, 27, 28, 29, 30], "design": [8, 20, 28, 29], "synthesi": [8, 19], "tool": [8, 17, 27, 29], "o": [8, 20, 28, 29], "same": [8, 9, 17, 28, 29, 30, 32], "number": [8, 10, 11, 13, 17, 20, 27, 29, 30, 31, 32, 33], "mulbaseunsign": 8, "unsignedmulunitlayout": [8, 10], "recursiveunsignedmul": 8, "see": [8, 23, 27, 28, 30], "fast": 8, "within": [8, 17], "sequentialunsignedmul": 8, "sequenti": [8, 11], "classic": [8, 20], "shiftunsignedmul": 8, "cheap": 8, "multi": 8, "lsublockcompon": [9, 10], "blockcomponentparam": [9, 10, 13, 14], "funcblock": [9, 10, 12, 13, 14, 15], "get_rs_entry_count": [9, 10, 13, 14], "lsudummi": 9, "veri": [9, 20, 28], "serial": [9, 13, 30], "all": [9, 10, 11, 14, 17, 19, 20, 23, 28, 29, 30, 32, 33], "store": [9, 10, 13, 14, 20, 25, 26, 29, 30, 32], "load": [9, 10, 20, 30, 32], "isn": [9, 27, 29], "compliant": [9, 27], "riscv": [9, 27], "spec": 9, "doesn": [9, 20, 23, 28, 30], "check": [9, 17, 20, 23, 25, 26, 27, 29, 32], "rang": [9, 29, 30, 31, 32, 33], "reserv": [9, 10, 14, 19, 20], "place": [9, 11, 14, 20, 25, 27, 28, 29, 30], "intruct": 9, "insert": [9, 12, 13, 14, 15, 19, 20, 24, 25], "put": [9, 14, 25, 27, 30], "receiv": [9, 11, 14, 28, 29, 30], "calcul": [9, 30], "end": [9, 10, 13, 20, 30, 32], "further": [9, 17, 30], "get_result": [9, 13, 14, 15, 30], "To": [9, 17, 20, 27, 30, 32], "precommit": [9, 13, 17], "processor": [9, 18, 19, 24], "master": [9, 11, 27], "pmacheck": 9, "physic": [9, 10, 12, 20], "memori": [9, 10, 11, 20, 30], "checker": 9, "mai": [9, 17, 30, 31, 32], "part": [9, 14, 20, 24, 28, 29, 30], "combin": [9, 13, 19, 23, 29, 30, 32], "circuit": [9, 27, 28, 29, 30, 32], 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"icache_wai": 10, "icache_sets_bit": 10, "log": [10, 20], "icache_block_size_bit": 10, "allow_partial_extens": 10, "allow": [10, 18, 20, 27, 28, 29, 30, 33], "partial": [10, 29, 30, 32], "_implied_extens": 10, "extenst": 10, "flag": 10, "intern": [10, 19, 28, 29, 30], "definit": [10, 19, 29], "per": [10, 27], "segment": 10, "abc": [10, 29, 30, 31, 32, 33], "func_unit": [10, 13], "csrblockcompon": [10, 14], "6": [10, 20], "7": 10, "factori": [10, 29, 30, 32], "kwarg": [10, 11, 29, 30, 31, 32, 33], "optypes_support": 10, "iter": [10, 13, 14, 29, 30, 31, 32, 33], "dependentcach": [10, 32], "cfg": 10, "addr_width": [10, 11], "length": [10, 20, 29, 32], "word_width": 10, "machin": [10, 14], "num_of_wai": 10, "num_of_sets_bit": 10, "block_size_bit": 10, "btypeinstr": 10, "riscvinstr": 10, "pack": 10, "ebreakinstr": 10, "itypeinstr": 10, "illegalinstr": 10, "jtypeinstr": 10, "rtypeinstr": 10, "stypeinstr": 10, "utypeinstr": 10, "exceptioncaus": 10, "breakpoint": 10, "environment_call_from_m": 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"t6": 10, "tp": [10, 32], "x1": 10, "x10": 10, "x11": 10, "x12": 10, "x13": 10, "x14": 10, "x15": 10, "x16": 10, "x17": 10, "x18": 10, "x19": 10, "x2": 10, "x20": 10, "x21": 10, "x22": 10, "x23": 10, "x24": 10, "x25": 10, "x26": 10, "x27": 10, "x28": 10, "x29": 10, "x3": 10, "x30": 10, "x31": 10, "x4": 10, "x5": 10, "x6": 10, "x7": 10, "x8": 10, "x9": 10, "asyncinterruptinsertsignalkei": 10, "simplekei": [10, 29, 30, 32], "branchverifykei": 10, "commonbusdatakei": 10, "exceptionreportkei": 10, "fetchresumekei": 10, "unifierkei": [10, 13, 30], "unifi": [10, 30], "alia": 10, "collector": [10, 30], "genericcsrregisterskei": 10, "genericcsrregist": [10, 14], "instructionprecommitkei": 10, "methodtryproduct": [10, 30], "mretkei": 10, "csrlayout": 10, "commonlayoutfield": 10, "commonli": 10, "layoutlistfield": 10, "caus": [10, 20, 30, 32], "piec": 10, "rais": [10, 20, 29, 30, 31, 32], "exec_fn_layout": 10, "op_typ": 10, "reg_id": 10, "id": [10, 12, 25, 26, 29], "reg_val": 10, "some": [10, 14, 20, 23, 28, 29, 30, 32], "regs_l": 10, "logic": [10, 20, 26, 27, 28], "manual": [10, 19, 28], "thei": [10, 11, 14, 17, 20, 24, 27, 28, 29, 30], "regs_p": 10, "rl_dst": 10, "destin": 10, "operand": [10, 20, 25, 26], "rl_s1": 10, "rl_s2": 10, "rob_id": 10, "entri": [10, 12, 13, 20, 24, 25, 26, 30, 32], "rp_dst": 10, "rp_s1": 10, "rp_s2": 10, "s1_val": 10, "s2_val": 10, "side_fx": 10, "side": [10, 14, 20, 25, 26], "effect": [10, 14, 20, 25, 26, 29, 30], "fetcher": 10, "access_fault": 10, "fail": [10, 20, 32], "produc": [10, 17], "jumpbranchlayout": 10, "verify_branch": 10, "predictor": 10, "about": [10, 17, 19, 29, 30, 32], "lsulayout": 10, "ratlayout": [10, 12], "tabl": [10, 19], "old_rp_dst": 10, "previous": [10, 11], "rrat": [10, 14], "rflayout": [10, 12], "roblayout": [10, 12], "done": [10, 20, 27, 28, 29, 30, 31], "yet": [10, 29], "latest": [10, 27, 30], "rob_data": 10, "earliest": [10, 14], "rsinterfacelayout": 10, "rs_entries_bit": 10, "data_layout": [10, 12, 30, 32], "shapelik": [10, 29, 30, 32], "layoutlist": [10, 29, 30, 32], "rslayout": [10, 12], "ready_list": 10, "bitmask": 10, "run": [10, 17, 27, 28, 29, 30, 31, 33], "retirementlayout": 10, "current": [10, 12, 14, 20, 29], "schedulerlayout": 10, "regs_l_rob_in": 10, "befor": [10, 11, 14, 17, 23, 24, 28, 30], "alloc": [10, 12, 24, 25, 26], "regs_p_alloc_out": 10, "rs_entry_id": 10, "rs_select": 10, "confus": 10, "address_gener": 10, "arithmet": 10, "bit_manipul": 10, "bit_rot": 10, "compar": [10, 19], "csr_imm": [10, 14], "csr_reg": [10, 14], "div_rem": 10, "34": 10, "33": 10, "single_bit_manipul": 10, "unary_bit_manipulation_1": 10, "unary_bit_manipulation_2": 10, "unary_bit_manipulation_3": 10, "unary_bit_manipulation_4": 10, "unary_bit_manipulation_5": 10, "unknown": [10, 17, 29, 30, 32], "optypes_required_by_extens": 10, "resolve_impl": 10, "ignore_unsupport": 10, "axiliteinterfac": 11, "abstractinterfac": 11, "abstractsignatur": 11, "read_address": 11, "axilitereadaddressinterfac": 11, "read_data": 11, "axilitereaddatainterfac": 11, "write_address": 11, "axilitewriteaddressinterfac": 11, "write_data": 11, "axilitewritedatainterfac": 11, "write_respons": 11, "axilitewriteresponseinterfac": 11, "axilitemast": 11, "axi": 11, "lite": 11, "axil_param": 11, "axiliteparamet": 11, "ra_request": 11, "channel": 11, "being": [11, 17, 30, 32, 33], "ra_request_layout": 11, "argument": [11, 12, 17, 19, 26, 27, 29, 30, 31, 32, 33], "rd_respons": 11, "availab": 11, "state": [11, 19, 20, 28, 29, 30, 31], "rd_response_layout": 11, "wa_request": 11, "wa_request_layout": 11, "wd_request": 11, "wd_request_layout": 11, "wr_respons": 11, "wr_response_layout": 11, "axil_mast": 11, "result_handl": 11, "tmodul": [11, 14, 28, 29, 30], "start_request_transact": 11, "is_address_channel": 11, "state_machine_request": 11, "request_sign": 11, "data_width": 11, "must": [11, 29, 30, 32], "axilitesignatur": 11, "signatur": 11, "patamet": 11, "axilitemasteradapt": 11, "where": [11, 12, 17, 20, 25, 26, 28, 29, 30, 31, 32], "expect": 11, "busparametersinterfac": 11, "method_layout": 11, "commonbusmastermethodlayout": 11, "request_read": 11, "underli": 11, "request_read_layout": 11, "request_writ": 11, "request_write_layout": 11, "get_read_respons": 11, "action": [11, 14, 29, 30, 32], "read_response_layout": 11, "get_write_respons": 11, "write_response_layout": 11, "prefer": [11, 28], "gain": 11, "simplifi": 11, "interchang": 11, "buse": 11, "sent": [11, 13, 31], "wishbonemasteradapt": 11, "wishbonemast": 11, "pipelinedwishbonemast": 11, "wb_param": 11, "wishboneparamet": 11, "max_req": 11, "limit": [11, 28, 30], "pend": 11, "wb": 11, "request_layout": 11, "complet": [11, 13, 20], "result_layout": 11, "requests_finish": 11, "generate_method_layout": 11, "wishbonearbit": 11, "arbit": 11, "slave": 11, "cyc": 11, "grant": [11, 28, 29, 30, 33], "round": [11, 29, 32, 33], "robin": [11, 29, 33], "num_slav": 11, "devic": 11, "slave_wb": 11, "intefac": 11, "num_mast": 11, "ack": 11, "adr": 11, "dat_r": 11, "dat_w": 11, "err": 11, "lock": [11, 17, 20, 28, 29, 30], "rst": 11, "rty": 11, "stall": [11, 14, 20], "stb": 11, "wb_master": 11, "becom": 11, "wishbonemastermethodlayout": 11, "wishbonememoryslav": 11, "underneath": 11, "keyword": [11, 28, 29, 30, 31, 32], "re": [11, 20, 23, 28, 29], "infer": [11, 29], "wishbonemux": 11, "muxer": 11, "multiplex": [11, 28], "ssel_tga": 11, "corespond": 11, "tga": 11, "so": [11, 13, 20, 27, 28, 29, 30], "note": [11, 14, 30], "stare": 11, "finish": [11, 13, 14, 30], "clear": [11, 25, 26, 30], "delai": [11, 28], "deassert": [11, 33], "master_wb": 11, "singal": 11, "granular": [11, 30], "smallest": 11, "port": [11, 30, 32, 33], "capabl": 11, "wishbonesignatur": 11, "path": [11, 29, 30, 32], "src_loc_at": [11, 32], "prepar": [12, 17, 20, 29], "In": [12, 17, 18, 19, 26, 27, 28, 29, 32], "renam": [12, 24], "without": [12, 13, 20, 30, 32], "stuck": 12, "get_instr": 12, "get_free_reg": 12, "rat_renam": 12, "rob_put": 12, "rf_read1": 12, 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"trap_entri": 13, "rsfuncblock": 13, "With": 13, "csrlistkei": 14, "listkei": [14, 30, 32], "csrregist": 14, "dependencymanag": [14, 29, 30, 31, 32], "behaviour": [14, 27], "automat": [14, 17, 27, 32], "csrunit": 14, "bodi": [14, 28, 29, 30], "csr_val": 14, "els": [14, 20, 28, 29], "_fu_read": 14, "_fu_writ": 14, "ignor": 14, "prioriti": [14, 28, 29, 30], "csr_number": 14, "ro_bit": 14, "mask": [14, 30], "those": [14, 20, 29], "upper": 14, "0b11": 14, "discard": 14, "regitst": 14, "unitl": 14, "resum": 14, "privilegelevel": 14, "csr_access_privileg": 14, "csr_addr": 14, "csraddress": 14, "3072": 14, "cycleh": 14, "3200": 14, "instret": 14, "3074": 14, "instreth": 14, "3202": 14, "mcaus": 14, "834": 14, "mepc": 14, "833": 14, "mtvec": 14, "773": 14, "3073": 14, "timeh": 14, "3201": 14, "doublecountercsr": 14, "group": 14, "At": 14, "overflow": [14, 30], "low_addr": 14, "high_addr": 14, "lower": [14, 32], "higher": 14, "synthetis": 14, "machinemodecsrregist": 14, "exceptioncauseregist": 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"tag": [3, 11, 20, 25, 26], "index": [3, 10, 29, 33], "offset": 3, "unsigned_multipl": [4, 7], "common": [4, 7, 11, 30, 32], "fast_recurs": [4, 7], "sequenc": [4, 7, 12, 30], "shift": [4, 7, 10], "class": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 28, 29, 30, 31, 32, 33], "base": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 20, 29, 30, 31, 32, 33], "elaborat": [4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 28, 29, 30, 31, 32], "__init__": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 28, 29, 30, 31, 32, 33], "gen_param": [4, 6, 7, 8, 9, 10, 12, 13, 14], "wb_instr_bu": 4, "wishboneinterfac": [4, 11], "wb_data_bu": 4, "cacheinterfac": [5, 6], "A": [5, 10, 11, 27, 28, 29, 30, 32], "simpl": [5, 6, 9, 12, 13, 29, 30, 32, 33], "associ": [5, 10, 30], "instruct": [5, 6, 7, 9, 10, 12, 13, 14, 19, 20, 24, 25, 27], "replac": [5, 8, 10, 25], "polici": 5, "pseudo": 5, "random": [5, 31], "scheme": 5, "everi": [5, 7, 11, 17, 27, 29, 30], "time": [5, 11, 14, 20, 29, 30], "trash": 5, "we": [5, 9, 11, 13, 20, 24, 25, 26, 27, 28, 31], "select": [5, 6, 7, 9, 11, 12, 13, 14, 15, 17], "next": [5, 6, 9, 12, 13, 14, 20, 29, 33], "wai": [5, 7, 11, 17, 20, 27, 28, 29, 30, 32], "keep": [5, 29], "global": [5, 14, 20], "counter": [5, 10, 14, 17, 30], "abstract": [5, 8, 10, 27, 30, 32], "awai": 5, "need": [5, 11, 17, 20, 25, 28, 29], "two": [5, 10, 14, 20, 23, 27, 28, 29, 30, 31, 32], "refiller_start": 5, "call": [5, 7, 12, 14, 17, 23, 25, 28, 29, 30, 31, 32], "whenev": [5, 30], "refiller_accept": 5, "readi": [5, 9, 10, 11, 12, 13, 14, 19, 25, 29, 30], "word": [5, 10], "written": [5, 14, 26, 27, 30], "last": [5, 10, 12, 14, 29, 30], "when": [5, 11, 14, 17, 20, 23, 25, 26, 28, 29, 30, 31, 32, 33], "either": [5, 11, 28, 29, 30, 31, 32, 33], "transfer": [5, 11, 29, 30], "over": [5, 14, 29, 30], "shouldn": [5, 27], "t": [5, 6, 9, 10, 17, 20, 23, 25, 27, 28, 29, 30, 31, 32], "until": [5, 20, 30], "start": [5, 7, 9, 10, 11, 20, 29, 30], "icachelayout": [5, 10], "icacheparamet": [5, 10], "cacherefillerinterfac": 5, "none": [5, 6, 7, 9, 10, 13, 14, 29, 30, 31, 32, 33], "paramet": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 28, 29, 30, 31, 32, 33], "instanc": [5, 6, 7, 9, 12, 13, 27, 29, 30, 31, 32], "us": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 19, 20, 23, 27, 28, 29, 30, 31, 32, 33], "creat": [5, 8, 11, 17, 27, 28, 29, 30, 31, 32, 33], "gener": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 18, 20, 23, 27, 29, 30, 31, 32], "input": [5, 6, 7, 11, 13, 14, 20, 25, 26, 28, 29, 30, 33], "start_refil": 5, "accept_refil": 5, "deserialize_addr": 5, "raw_addr": 5, "valu": [5, 6, 7, 9, 10, 11, 12, 13, 14, 19, 23, 25, 26, 29, 30, 31, 32, 33], "dict": [5, 11, 28, 29, 30, 31, 32, 33], "str": [5, 10, 11, 29, 30, 31, 32, 33], "amaranth": [5, 6, 7, 10, 11, 23, 27, 28, 29, 30, 31, 32, 33], "hdl": [5, 6, 7, 10, 29, 30, 31, 32, 33], "_ast": [5, 6, 7, 10, 29, 30, 31, 32, 33], "serialize_addr": 5, "addr": [5, 9, 10, 11, 30], "view": [5, 7, 9, 29, 30, 31, 32, 33], "icachebypass": 5, "bus_mast": 5, "busmasterinterfac": [5, 9, 10, 11], "haselabor": [5, 11, 15, 29, 30, 31, 33], "interfac": [5, 6, 8, 9, 11, 12, 13, 14, 19, 27, 28, 29, 30], "whole": [5, 18, 20, 30], "given": [5, 7, 9, 10, 17, 25, 28, 29, 30, 31, 32, 33], "simplecommonbuscacherefil": 5, "decodestag": 6, "decod": [6, 7, 10, 12, 29, 32], "transact": [6, 10, 11, 14, 17, 19, 25, 29, 30, 33], "instanti": [6, 29], "instrdecod": 6, "make": [6, 7, 17, 18, 20, 23, 27, 28, 29, 31], "actual": [6, 17, 19, 28], "combinatori": [6, 28], "manner": [6, 11], "get_raw": 6, "push_decod": 6, "raw": 6, "previou": [6, 11, 20, 30], "step": [6, 12, 17, 20, 27, 28], "e": [6, 10, 17, 20, 23, 28, 30, 32, 33], "g": [6, 10, 17, 20, 23, 28, 30, 32, 33], "fetchlayout": [6, 10], "send": [6, 10, 11, 12, 13], "It": [6, 7, 8, 9, 11, 12, 13, 17, 20, 24, 25, 27, 28, 29, 30, 31, 32, 33], "describ": [6, 10, 12, 13, 20, 27, 29, 30, 31], "decodelayout": [6, 10, 12], "pc": [6, 10, 14, 19], "insid": [6, 27, 28, 29, 30], "increment": [6, 14], "ilen_byt": 6, "cont": [6, 31], "unalignedfetch": 6, "work": [6, 12, 20, 23, 27, 28, 29, 30], "unalign": 6, "perform": [6, 7, 8, 10, 12, 14, 17, 27, 28, 29, 30, 32, 33], "elementari": 6, "compon": [6, 10, 11, 18, 29, 30], "opcod": [6, 10, 25, 26], "funct3": [6, 7, 10], "etc": [6, 10, 28], "connect": [6, 11, 13, 14, 20, 28, 29, 30], "via": [6, 28, 29], "its": [6, 12, 13, 14, 20, 27, 28, 29, 30, 32, 33], "attribut": [6, 7, 8, 9, 10, 11, 13, 14, 29, 30, 32, 33], "signal": [6, 7, 9, 10, 11, 19, 23, 29, 30, 31, 32, 33], "ilen": [6, 10], "out": [6, 7, 8, 11, 13, 18, 19, 29, 30, 33], "identifi": [6, 10, 25, 30], "funct3_v": 6, "1": [6, 7, 8, 10, 12, 14, 20, 25, 26, 27, 28, 29, 30, 31, 32, 33], "funct7": [6, 7, 10], "seven": 6, "funct7_v": 6, "funct12": [6, 10], "twelv": 6, "funct12_v": 6, "rd": [6, 10], "reg_cnt_log": 6, "address": [6, 9, 10, 11, 14, 19, 20], "regist": [6, 10, 12, 14, 20, 24, 30, 32], "rd_v": 6, "rs1": [6, 10], "hold": [6, 11, 14, 30], "first": [6, 7, 10, 12, 20, 25, 26, 27, 28, 30, 31, 32], "rs1_v": 6, "take": [6, 11, 13, 24, 25, 28, 29, 30, 31, 32], "form": [6, 10, 14, 20, 27, 30], "rs2": [6, 10], "second": [6, 7, 10, 12, 25, 26, 27, 30], "rs2_v": 6, "imm": [6, 10], "xlen": [6, 7, 10, 14, 32], "immedi": [6, 10, 11], "provid": [6, 7, 10, 12, 14, 27, 28, 30, 31, 32], "were": [6, 20, 28], "succ": 6, "fencetarget": [6, 10], "successor": 6, "fenc": [6, 10], "pred": 6, "predecessor": 6, "fm": 6, "fencefm": [6, 10], "mode": [6, 10, 17, 20], "csr_alen": [6, 10], "control": [6, 10, 11, 14, 27, 29, 30, 33], "sourc": [6, 10, 12, 17, 25, 29, 30], "type": [6, 7, 10, 17, 29, 30, 31, 32], "defin": [6, 9, 14, 28, 29, 30, 32, 33], "kind": [6, 7, 12, 30, 32], "illeg": 6, "wa": [6, 10, 14, 17, 20, 28, 29, 30, 32], "success": [6, 11, 31], "do": [6, 10, 20, 23, 28, 29], "fit": 6, "support": [6, 9, 10, 12, 17, 19, 29, 30], "constructor": [6, 28, 29, 32], "encod": [6, 20, 29, 32, 33], "object": [6, 7, 9, 10, 11, 27, 28, 29, 30, 31, 32], "repres": [6, 14, 29, 30], "singl": [6, 7, 8, 10, 12, 13, 14, 28, 29, 30, 32], "option": [6, 7, 10, 11, 14, 17, 28, 29, 30, 31, 32, 33], "exist": [6, 28], "instr_type_overrid": 6, "instrtyp": [6, 10], "specifi": [6, 10, 11, 14, 26, 30, 31, 32], "determin": [6, 20, 27, 30, 32], "instrust": 6, "almost": 6, "correct": [6, 9, 20, 25, 26, 27], "rd_zero": 6, "bool": [6, 7, 9, 10, 14, 29, 30, 31, 32, 33], "field": [6, 9, 10, 14, 17, 25, 26, 28, 29, 30, 31, 32], "constant": 6, "zero": [6, 10, 14, 25, 30, 33], "other": [6, 14, 17, 19, 28, 29, 30, 33], "accordingli": 6, "default": [6, 11, 17, 28, 29, 30, 32, 33], "fals": [6, 7, 9, 10, 17, 28, 29, 30, 32, 33], "rs1_zero": 6, "instrdecompress": 6, "decompr_reg": 6, "rvc_reg": 6, "instr_mux": 6, "sel": [6, 11], "list": [6, 7, 10, 11, 14, 17, 19, 23, 27, 29, 30, 31, 32, 33], "int": [6, 7, 8, 9, 10, 11, 13, 14, 29, 30, 31, 32, 33], "enum": [6, 7, 10, 29, 30, 31, 32], "valuecast": [6, 10, 29, 30, 31, 32], "tupl": [6, 7, 10, 11, 12, 13, 14, 29, 30, 32], "is_instr_compress": 6, "alucompon": [7, 10], "functionalcomponentparam": [7, 10, 13], "zba_en": 7, "zbb_enabl": 7, "get_modul": [7, 9, 10, 13, 14], "funcunit": [7, 10, 13, 15], "get_optyp": [7, 9, 10, 13, 14], "alufuncunit": 7, "alu_fn": 7, "alufn": 7, "divcompon": 7, "ipc": [7, 27], "3": [7, 10, 14, 17, 29, 32], "div_fn": 7, "divfn": 7, "decodermanag": 7, "fn": 7, "intflag": [7, 10, 29], "div": [7, 10], "divu": [7, 10], "2": [7, 8, 10, 11, 14, 27, 29, 30, 32], "rem": [7, 10], "remu": [7, 10], "8": [7, 8, 10, 11, 29, 30], "__new__": [7, 10, 14, 29], "get_instruct": 7, "valid": [7, 10, 11, 12, 25, 30, 32, 33], "implement": [7, 9, 11, 18, 19, 20, 24, 30, 32, 33], "format": [7, 17, 27, 28, 29, 30, 32], "divunit": 7, "get_input": 7, "arg": [7, 11, 28, 29, 30, 31, 32, 33], "exceptionfuncunit": 7, "unit_fn": 7, "exceptionunitfn": 7, "exceptionunitcompon": [7, 10], "respons": [7, 11, 12, 17, 29, 30, 31], "decode_fn": 7, "exec_fn": [7, 10], "op": [7, 10], "check_optyp": 7, "manag": [7, 17, 19, 29, 30, 32], "enumer": 7, "get_decod": 7, "auto": 7, "pass": [7, 13, 14, 17, 19, 27, 29, 30, 31, 32], "contructor": 7, "get_funct": 7, "get_op_typ": 7, "jumpbranchfuncunit": 7, "jb_fn": 7, "jumpbranchfn": 7, "jumpcompon": [7, 10], "mulcompon": 7, "mul_unit_typ": 7, "multyp": 7, "dsp_width": [7, 8], "mul_fn": 7, "mulfn": 7, "hot": [7, 20, 33], "wire": 7, "5": [7, 10, 24, 30, 31], "differ": [7, 11, 13, 17, 18, 20, 23, 27, 29, 30, 32], "mul": [7, 10], "mulh": [7, 10], "mulhsu": [7, 10], "mulhu": [7, 10], "intenum": [7, 10, 14], "recursive_mul": 7, "fastest": 7, "multipli": [7, 8], "onli": [7, 11, 14, 20, 27, 28, 29, 30, 31, 32], "costli": [7, 20], "term": 7, "resourc": [7, 14, 20, 27, 28], "sequence_mul": 7, "dsp": [7, 8], "balanc": 7, "between": [7, 17, 20, 28, 29, 30, 32, 33], "cost": [7, 19, 28], "shift_mul": 7, "cheapest": 7, "russian": [7, 8], "peasant": [7, 8], "algorithm": [7, 8], "mulunit": 7, "unsign": [7, 8], "integ": [7, 10, 31, 32], "standard": [7, 14, 20, 27, 30, 33], "funcunitlayout": [7, 10, 12, 13], "comput": [7, 8, 9, 14, 20, 30, 32], "mul_typ": 7, "privilegedfn": 7, "mret": [7, 10], "classmethod": [7, 29, 30, 32], "privilegedfuncunit": 7, "gp": [7, 10, 14], "privilegedunitcompon": [7, 10], "shiftfuncunit": 7, "shift_unit_fn": 7, "shiftunitfn": 7, "shiftunitcompon": [7, 10], "clmultipli": 7, "carri": [7, 10, 27], "less": [7, 10], "product": [7, 30], "i1": [7, 8], "n": [7, 8, 10], "factor": 7, "i2": [7, 8], "reset": [7, 14, 19, 29], "new": [7, 9, 11, 14, 19, 20, 29, 30, 32, 33], "busi": 7, "while": [7, 29, 31], "progress": 7, "bit_width": 7, "recursion_depth": 7, "width": [7, 8, 10, 11, 14, 30, 32, 33], "depth": [7, 11, 27, 30], "recurs": [7, 8, 27, 28, 29, 32], "parallel": [7, 30], "assum": [7, 13, 20, 30, 32], "power": [7, 32], "iterative_modul": 7, "recursive_modul": 7, "zbccompon": 7, "zbc_fn": 7, "zbcfn": 7, "clmul": [7, 10], "clmulh": [7, 10], "clmulr": [7, 10], "zbcunit": 7, "execut": [7, 10, 11, 12, 13, 17, 19, 24, 26, 28, 29, 30, 31], "zbsfunction": 7, "in1": 7, "in2": 7, "zbscompon": 7, "bclr": [7, 10], "bext": [7, 10], "binv": [7, 10], "bset": [7, 10], "zbsunit": 7, "zbs_fn": 7, "dspmulunit": 8, "clock": [8, 24, 27, 28, 29, 30], "design": [8, 20, 28, 29], "synthesi": [8, 19], "tool": [8, 17, 27, 29], "o": [8, 20, 28, 29], "same": [8, 9, 17, 28, 29, 30, 32], "number": [8, 10, 11, 13, 17, 20, 27, 29, 30, 31, 32, 33], "mulbaseunsign": 8, "unsignedmulunitlayout": [8, 10], "recursiveunsignedmul": 8, "see": [8, 23, 27, 28, 30], "fast": 8, "within": [8, 17], "sequentialunsignedmul": 8, "sequenti": [8, 11], "classic": [8, 20], "shiftunsignedmul": 8, "cheap": 8, "multi": 8, "lsublockcompon": [9, 10], "blockcomponentparam": [9, 10, 13, 14], "funcblock": [9, 10, 12, 13, 14, 15], "get_rs_entry_count": [9, 10, 13, 14], "lsudummi": 9, "veri": [9, 20, 28], "serial": [9, 13, 30], "all": [9, 10, 11, 14, 17, 19, 20, 23, 28, 29, 30, 32, 33], "store": [9, 10, 13, 14, 20, 25, 26, 29, 30, 32], "load": [9, 10, 20, 30, 32], "isn": [9, 27, 29], "compliant": [9, 27], "riscv": [9, 27], "spec": 9, "doesn": [9, 20, 23, 28, 30], "check": [9, 17, 20, 23, 25, 26, 27, 29, 32], "rang": [9, 29, 30, 31, 32, 33], "reserv": [9, 10, 14, 19, 20], "place": [9, 11, 14, 20, 25, 27, 28, 29, 30], "intruct": 9, "insert": [9, 12, 13, 14, 15, 19, 20, 24, 25], "put": [9, 14, 25, 27, 30], "receiv": [9, 11, 14, 28, 29, 30], "calcul": [9, 30], "end": [9, 10, 13, 20, 30], "further": [9, 17, 30], "get_result": [9, 13, 14, 15, 30], "To": [9, 17, 20, 27, 30, 32], "precommit": [9, 13, 17], "processor": [9, 18, 19, 24], "master": [9, 11, 27], "pmacheck": 9, "physic": [9, 10, 12, 20], "memori": [9, 10, 11, 20, 30], "checker": 9, "mai": [9, 17, 30, 31, 32], "part": [9, 14, 20, 24, 28, 29, 30], "combin": [9, 13, 19, 23, 29, 30, 32], "circuit": [9, 27, 28, 29, 30, 32], "pmalayout": 9, "structlayout": [9, 29, 30, 32], "pmaregion": [9, 10], "contigu": [9, 10], "region": [9, 20], "includ": [9, 27, 28, 29, 30, 32, 33], "both": [9, 25, 28, 29, 30, 32], "begin": [9, 20], "mmio": 9, "true": [9, 10, 11, 28, 29, 30, 31, 32, 33], "indic": [9, 20, 26, 29, 30], "coreconfigur": 10, "func_units_config": 10, "collect": [10, 13, 14, 18, 27, 29, 30, 31, 32, 33], "station": [10, 19], "exampl": [10, 14, 17, 19, 25, 28, 29, 30, 33], "rsblockcompon": [10, 13], "rs_entri": [10, 13, 14], "compress": 10, "enabl": [10, 30, 31, 32], "embed": 10, "reduc": [10, 20, 29], "debug": [10, 17, 30, 32], "hardwar": [10, 19, 24, 28, 30], "disabl": [10, 29, 30, 31], "them": [10, 17, 20, 27, 28, 29, 30, 32], "synthes": [10, 27, 30], "phys_regs_bit": 10, "file": [10, 17, 20, 27, 32], "rob_entries_bit": 10, "reorder": [10, 20, 30], "buffer": [10, 11, 20, 25, 30], "start_pc": 10, "initi": [10, 11, 19, 30, 31], "program": [10, 20, 27, 28], "icache_en": 10, "bypass": 10, "directli": [10, 28, 29], "icache_wai": 10, "icache_sets_bit": 10, "icache_block_size_bit": 10, "allow_partial_extens": 10, "allow": [10, 18, 20, 27, 28, 29, 30, 33], "partial": [10, 29, 30, 32], "_implied_extens": 10, "extenst": 10, "flag": 10, "intern": [10, 19, 28, 29, 30], "definit": [10, 19, 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b/shared-structs/implementation/rs-impl.html index 71695ebba..476b704ad 100644 --- a/shared-structs/implementation/rs-impl.html +++ b/shared-structs/implementation/rs-impl.html @@ -252,7 +252,7 @@

    Read and clean row

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:48 2024-03-14. + Last updated on 11:28 2024-03-14.

    diff --git a/shared-structs/rs.html b/shared-structs/rs.html index 5aec6e868..9b016d0f1 100644 --- a/shared-structs/rs.html +++ b/shared-structs/rs.html @@ -222,7 +222,7 @@

    External interface signals

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:48 2024-03-14. + Last updated on 11:28 2024-03-14.

    diff --git a/synthesis/synthesis.html b/synthesis/synthesis.html index 211789d72..05b533d67 100644 --- a/synthesis/synthesis.html +++ b/synthesis/synthesis.html @@ -266,7 +266,7 @@

    Regression tests manual execution

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:48 2024-03-14. + Last updated on 11:28 2024-03-14.

    diff --git a/transactions.html b/transactions.html index 191734064..b1131fafc 100644 --- a/transactions.html +++ b/transactions.html @@ -409,7 +409,7 @@

    Transaction and method nesting

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:48 2024-03-14. + Last updated on 11:28 2024-03-14.

    diff --git a/transactron.html b/transactron.html index 6cabac317..9869c1bcd 100644 --- a/transactron.html +++ b/transactron.html @@ -94,6 +94,7 @@

    Subpackagestransactron.lib.connectors module
  • transactron.lib.dependencies module
  • transactron.lib.fifo module
    • +
  • transactron.lib.logging module
  • transactron.lib.metrics module
  • transactron.lib.reqres module
  • transactron.lib.simultaneous module
    • @@ -104,10 +105,10 @@

    Subpackagestransactron.testing package