From e85081acd576a2e6e7e2c216f0e8d8d73488f813 Mon Sep 17 00:00:00 2001 From: Piotr Wegrzyn Date: Tue, 19 Nov 2024 23:38:04 +0100 Subject: [PATCH] Config changes --- coreblocks/params/configurations.py | 11 ++++++++++- test/params/test_configurations.py | 6 +++--- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/coreblocks/params/configurations.py b/coreblocks/params/configurations.py index f777954a7..104e447f6 100644 --- a/coreblocks/params/configurations.py +++ b/coreblocks/params/configurations.py @@ -32,6 +32,13 @@ [ALUComponent(), ShiftUnitComponent(), JumpComponent(), ExceptionUnitComponent(), PrivilegedUnitComponent()], rs_entries=4, ), + RSBlockComponent( + [ + MulComponent(mul_unit_type=MulType.SEQUENCE_MUL), + DivComponent(), + ], + rs_entries=2, + ), RSBlockComponent([LSUComponent()], rs_entries=2, rs_type=FifoRS), CSRBlockComponent(), ) @@ -139,7 +146,9 @@ def __post_init__(self): _implied_extensions: Extension = Extension(0) _generate_test_hardware: bool = False - pma: list[PMARegion] = field(default_factory=list) + pma: list[PMARegion] = field( + default_factory=lambda: [PMARegion(0xE0000000, 0xFFFFFFFF, mmio=True)] + ) # defult I/O region used in LiteX coreblocks class CoreConfiguration(_CoreConfigurationDataClass): diff --git a/test/params/test_configurations.py b/test/params/test_configurations.py index 13c0be1f3..dcfac4eb4 100644 --- a/test/params/test_configurations.py +++ b/test/params/test_configurations.py @@ -18,9 +18,9 @@ class ISAStrTest: TEST_CASES = [ ISAStrTest( basic_core_config, - "rv32izicsr_zifencei_xintmachinemode", - "rv32izicsr_zifencei_xintmachinemode", - "rv32izicsr_zifencei_xintmachinemode", + "rv32imzicsr_zifencei_xintmachinemode", + "rv32imzicsr_zifencei_xintmachinemode", + "rv32imzicsr_zifencei_xintmachinemode", ), ISAStrTest( full_core_config,