diff --git a/.doctrees/Current_graph.doctree b/.doctrees/Current_graph.doctree index cc1b06915..2150abb59 100644 Binary files a/.doctrees/Current_graph.doctree and b/.doctrees/Current_graph.doctree differ diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index 108aafbeb..eb2aa50d9 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index 3e91e23c9..1218b60f5 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index a7ccf8086..a3aae2c8d 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/.doctrees/transactron.doctree b/.doctrees/transactron.doctree index f0c4ca70f..bcb62222c 100644 Binary files a/.doctrees/transactron.doctree and b/.doctrees/transactron.doctree differ diff --git a/Assumptions.html b/Assumptions.html index 1f4cd3d88..f659b3cbd 100644 --- a/Assumptions.html +++ b/Assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/Current_graph.html b/Current_graph.html index 8989972f0..3aa9aecdf 100644 --- a/Current_graph.html +++ b/Current_graph.html @@ -89,21 +89,21 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/Development_environment.html b/Development_environment.html index 5f84422be..5485be1e2 100644 --- a/Development_environment.html +++ b/Development_environment.html @@ -178,7 +178,7 @@

build_docs.sh

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/Home.html b/Home.html index e03e370cd..7e3aad155 100644 --- a/Home.html +++ b/Home.html @@ -129,7 +129,7 @@

Documentation

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/Problem-checklist.html b/Problem-checklist.html index 14b46ff35..f7a2d8159 100644 --- a/Problem-checklist.html +++ b/Problem-checklist.html @@ -105,7 +105,7 @@

Problem checklist

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/Transactions.html b/Transactions.html index 2cad11b3b..a894a2774 100644 --- a/Transactions.html +++ b/Transactions.html @@ -409,7 +409,7 @@

Transaction and method nesting

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 04914eb58..963ad54ce 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -6,21 +6,21 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] + WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_request["request"] WishboneMaster_result["result"] - WishboneMaster_WishboneMaster["WishboneMaster"] subgraph Forwarder["result Forwarder"] Forwarder_write["write"] Forwarder_read["read"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] + WishboneMaster1_result["result"] WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] - Forwarder1_write["write"] Forwarder1_read["read"] + Forwarder1_write["write"] end end subgraph FIFO["fifo_fetch FIFO"] @@ -28,13 +28,13 @@ FIFO_read["read"] end subgraph BasicFifo["free_rf_fifo BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"] SimpleWBCacheRefiller_accept_refill["accept_refill"] - SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] SimpleWBCacheRefiller_start_refill["start_refill"] + SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] subgraph Forwarder2["address_fwd Forwarder"] Forwarder2_read["read"] Forwarder2_write["write"] @@ -42,17 +42,17 @@ end subgraph ICache["icache ICache"] ICache_ICache["ICache"] - ICache_accept_res["accept_res"] ICache_ICache1["ICache"] - ICache_issue_req["issue_req"] + ICache_accept_res["accept_res"] ICache_ICache2["ICache"] + ICache_issue_req["issue_req"] subgraph FIFO1["req_fifo FIFO"] - FIFO1_write["write"] FIFO1_read["read"] + FIFO1_write["write"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end subgraph Fetch["fetch Fetch"] @@ -72,8 +72,8 @@ end subgraph RegisterFile["RF RegisterFile"] RegisterFile_read2["read2"] - RegisterFile_write["write"] RegisterFile_free["free"] + RegisterFile_write["write"] RegisterFile_read1["read1"] end subgraph ReorderBuffer["ROB ReorderBuffer"] @@ -84,8 +84,8 @@ ReorderBuffer_peek["peek"] end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_report["report"] end subgraph FuncBlocksUnifier["func_blocks_unifier FuncBlocksUnifier"] subgraph Collector["result_collector Collector"] @@ -107,23 +107,23 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] + RSFuncBlock_select["select"] + RSFuncBlock_insert["insert"] RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] - RSFuncBlock_insert["insert"] - RSFuncBlock_select["select"] subgraph RS["rs RS"] RS_RS["RS"] RS_RS1["RS"] RS_RS2["RS"] RS_update["update"] RS_take["take"] + RS_RS3["RS"] RS_insert["insert"] RS_select["select"] - RS_RS3["RS"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph FIFO2["fifo FIFO"] FIFO2_write["write"] FIFO2_read["read"] @@ -136,8 +136,8 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] @@ -163,8 +163,8 @@ ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] subgraph FIFO6["fifo FIFO"] - FIFO6_write["write"] FIFO6_read["read"] + FIFO6_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -173,8 +173,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_read["read"] Forwarder5_write["write"] + Forwarder5_read["read"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans2["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -193,11 +193,11 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_precommit["precommit"] - LSUDummy_insert["insert"] LSUDummy_update["update"] + LSUDummy_insert["insert"] LSUDummy_get_result["get_result"] LSUDummy_select["select"] + LSUDummy_precommit["precommit"] subgraph LSUDummyInternals["internal LSUDummyInternals"] LSUDummyInternals_LSUDummyInternals["LSUDummyInternals"] LSUDummyInternals_LSUDummyInternals1["LSUDummyInternals"] @@ -224,12 +224,12 @@ subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister2["register_low CSRRegister"] - CSRRegister2_read["read"] CSRRegister2_write["write"] + CSRRegister2_read["read"] end subgraph CSRRegister3["register_high CSRRegister"] - CSRRegister3_write["write"] CSRRegister3_read["read"] + CSRRegister3_write["write"] end end subgraph CSRRegister4["mcause CSRRegister"] @@ -237,16 +237,16 @@ end end subgraph FIFO7["fifo_decode FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end subgraph Decode["decode Decode"] Decode_Decode["Decode"] end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO8["alloc_rename_buf FIFO"] - FIFO8_read["read"] FIFO8_write["write"] + FIFO8_read["read"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -291,12 +291,12 @@ subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_write["write"] CSRRegister5_read["read"] + CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_read["read"] CSRRegister6_write["write"] + CSRRegister6_read["read"] end end end @@ -319,13 +319,13 @@ WishboneMaster1_WishboneMaster --> Forwarder1_write Forwarder2_read --> SimpleWBCacheRefiller_SimpleWBCacheRefiller SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request - ICache_ICache --> Forwarder3_write + ICache_ICache2 --> Forwarder3_write ICache_ICache1 --> SimpleWBCacheRefiller_start_refill ICache_ICache1 --> Forwarder2_write - ICache_ICache2 --> Forwarder2_write - SimpleWBCacheRefiller_accept_refill --> ICache_ICache2 - WishboneMaster_result --> ICache_ICache2 - Forwarder_read --> ICache_ICache2 + ICache_ICache --> Forwarder2_write + SimpleWBCacheRefiller_accept_refill --> ICache_ICache + WishboneMaster_result --> ICache_ICache + Forwarder_read --> ICache_ICache Fetch_Fetch --> ICache_issue_req Fetch_Fetch --> FIFO1_write Fetch_Fetch --> BasicFifo1_write @@ -346,15 +346,15 @@ FIFO9_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation --> FIFO10_write - FIFO10_read --> RSSelection_RSSelection1 - RSSelection_RSSelection1 --> Forwarder6_write - Forwarder6_read --> RSSelection_RSSelection2 + FIFO10_read --> RSSelection_RSSelection2 + RSSelection_RSSelection2 --> Forwarder6_write Forwarder6_read --> RSSelection_RSSelection - RSFuncBlock_select --> RSSelection_RSSelection2 - RS_select --> RSSelection_RSSelection2 - RSSelection_RSSelection2 --> FIFO11_write + Forwarder6_read --> RSSelection_RSSelection1 + RSFuncBlock_select --> RSSelection_RSSelection + RS_select --> RSSelection_RSSelection RSSelection_RSSelection --> FIFO11_write - RSSelection_RSSelection <--> LSUDummy_select + RSSelection_RSSelection1 --> FIFO11_write + RSSelection_RSSelection1 <--> LSUDummy_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -373,26 +373,26 @@ ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update - RS_RS1 --> WakeupSelect_WakeupSelect + RS_RS --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect RS_take --> WakeupSelect3_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO2_write - RS_RS2 --> WakeupSelect1_WakeupSelect + RS_RS1 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write - RS_RS --> WakeupSelect2_WakeupSelect + RS_RS2 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> ExceptionCauseRegister_report WakeupSelect3_WakeupSelect --> ExceptionCauseRegister_report - LSUDummyInternals_LSUDummyInternals2 --> ExceptionCauseRegister_report LSUDummyInternals_LSUDummyInternals --> ExceptionCauseRegister_report + LSUDummyInternals_LSUDummyInternals1 --> ExceptionCauseRegister_report ReorderBuffer_get_indices --> WakeupSelect2_WakeupSelect ReorderBuffer_get_indices --> WakeupSelect3_WakeupSelect - ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals2 ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals + ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals1 WakeupSelect2_WakeupSelect --> FIFO4_write WakeupSelect2_WakeupSelect --> FIFO5_write RS_RS3 --> WakeupSelect3_WakeupSelect @@ -410,9 +410,9 @@ FIFO4_read --> ConnectTrans4_ConnectTrans ExceptionFuncUnit_accept --> ConnectTrans5_ConnectTrans FIFO6_read --> ConnectTrans5_ConnectTrans - LSUDummyInternals_LSUDummyInternals1 --> WishboneMaster1_request - WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals - Forwarder1_read --> LSUDummyInternals_LSUDummyInternals + LSUDummyInternals_LSUDummyInternals2 --> WishboneMaster1_request + WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals1 + Forwarder1_read --> LSUDummyInternals_LSUDummyInternals1 ConnectTrans_ConnectTrans --> Forwarder4_write ConnectTrans1_ConnectTrans --> Forwarder4_write RSFuncBlock_get_result --> ConnectTrans_ConnectTrans diff --git a/api.html b/api.html index 8175dd87a..d37270aff 100644 --- a/api.html +++ b/api.html @@ -240,7 +240,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/auto_graph.html b/auto_graph.html index 9a5e1a70c..4d42b429b 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -85,21 +85,21 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] + WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_request["request"] WishboneMaster_result["result"] - WishboneMaster_WishboneMaster["WishboneMaster"] subgraph Forwarder["result Forwarder"] Forwarder_write["write"] Forwarder_read["read"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] + WishboneMaster1_result["result"] WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] - Forwarder1_write["write"] Forwarder1_read["read"] + Forwarder1_write["write"] end end subgraph FIFO["fifo_fetch FIFO"] @@ -107,13 +107,13 @@ FIFO_read["read"] end subgraph BasicFifo["free_rf_fifo BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"] SimpleWBCacheRefiller_accept_refill["accept_refill"] - SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] SimpleWBCacheRefiller_start_refill["start_refill"] + SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] subgraph Forwarder2["address_fwd Forwarder"] Forwarder2_read["read"] Forwarder2_write["write"] @@ -121,17 +121,17 @@ end subgraph ICache["icache ICache"] ICache_ICache["ICache"] - ICache_accept_res["accept_res"] ICache_ICache1["ICache"] - ICache_issue_req["issue_req"] + ICache_accept_res["accept_res"] ICache_ICache2["ICache"] + ICache_issue_req["issue_req"] subgraph FIFO1["req_fifo FIFO"] - FIFO1_write["write"] FIFO1_read["read"] + FIFO1_write["write"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end subgraph Fetch["fetch Fetch"] @@ -151,8 +151,8 @@ end subgraph RegisterFile["RF RegisterFile"] RegisterFile_read2["read2"] - RegisterFile_write["write"] RegisterFile_free["free"] + RegisterFile_write["write"] RegisterFile_read1["read1"] end subgraph ReorderBuffer["ROB ReorderBuffer"] @@ -163,8 +163,8 @@ ReorderBuffer_peek["peek"] end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_report["report"] end subgraph FuncBlocksUnifier["func_blocks_unifier FuncBlocksUnifier"] subgraph Collector["result_collector Collector"] @@ -186,23 +186,23 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] + RSFuncBlock_select["select"] + RSFuncBlock_insert["insert"] RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] - RSFuncBlock_insert["insert"] - RSFuncBlock_select["select"] subgraph RS["rs RS"] RS_RS["RS"] RS_RS1["RS"] RS_RS2["RS"] RS_update["update"] RS_take["take"] + RS_RS3["RS"] RS_insert["insert"] RS_select["select"] - RS_RS3["RS"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph FIFO2["fifo FIFO"] FIFO2_write["write"] FIFO2_read["read"] @@ -215,8 +215,8 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] @@ -242,8 +242,8 @@ ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] subgraph FIFO6["fifo FIFO"] - FIFO6_write["write"] FIFO6_read["read"] + FIFO6_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -252,8 +252,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_read["read"] Forwarder5_write["write"] + Forwarder5_read["read"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans2["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -272,11 +272,11 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_precommit["precommit"] - LSUDummy_insert["insert"] LSUDummy_update["update"] + LSUDummy_insert["insert"] LSUDummy_get_result["get_result"] LSUDummy_select["select"] + LSUDummy_precommit["precommit"] subgraph LSUDummyInternals["internal LSUDummyInternals"] LSUDummyInternals_LSUDummyInternals["LSUDummyInternals"] LSUDummyInternals_LSUDummyInternals1["LSUDummyInternals"] @@ -303,12 +303,12 @@ subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister2["register_low CSRRegister"] - CSRRegister2_read["read"] CSRRegister2_write["write"] + CSRRegister2_read["read"] end subgraph CSRRegister3["register_high CSRRegister"] - CSRRegister3_write["write"] CSRRegister3_read["read"] + CSRRegister3_write["write"] end end subgraph CSRRegister4["mcause CSRRegister"] @@ -316,16 +316,16 @@ end end subgraph FIFO7["fifo_decode FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end subgraph Decode["decode Decode"] Decode_Decode["Decode"] end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO8["alloc_rename_buf FIFO"] - FIFO8_read["read"] FIFO8_write["write"] + FIFO8_read["read"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -370,12 +370,12 @@ subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_write["write"] CSRRegister5_read["read"] + CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_read["read"] CSRRegister6_write["write"] + CSRRegister6_read["read"] end end end @@ -398,13 +398,13 @@ WishboneMaster1_WishboneMaster --> Forwarder1_write Forwarder2_read --> SimpleWBCacheRefiller_SimpleWBCacheRefiller SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request -ICache_ICache --> Forwarder3_write +ICache_ICache2 --> Forwarder3_write ICache_ICache1 --> SimpleWBCacheRefiller_start_refill ICache_ICache1 --> Forwarder2_write -ICache_ICache2 --> Forwarder2_write -SimpleWBCacheRefiller_accept_refill --> ICache_ICache2 -WishboneMaster_result --> ICache_ICache2 -Forwarder_read --> ICache_ICache2 +ICache_ICache --> Forwarder2_write +SimpleWBCacheRefiller_accept_refill --> ICache_ICache +WishboneMaster_result --> ICache_ICache +Forwarder_read --> ICache_ICache Fetch_Fetch --> ICache_issue_req Fetch_Fetch --> FIFO1_write Fetch_Fetch --> BasicFifo1_write @@ -425,15 +425,15 @@ FIFO9_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation --> FIFO10_write -FIFO10_read --> RSSelection_RSSelection1 -RSSelection_RSSelection1 --> Forwarder6_write -Forwarder6_read --> RSSelection_RSSelection2 +FIFO10_read --> RSSelection_RSSelection2 +RSSelection_RSSelection2 --> Forwarder6_write Forwarder6_read --> RSSelection_RSSelection -RSFuncBlock_select --> RSSelection_RSSelection2 -RS_select --> RSSelection_RSSelection2 -RSSelection_RSSelection2 --> FIFO11_write +Forwarder6_read --> RSSelection_RSSelection1 +RSFuncBlock_select --> RSSelection_RSSelection +RS_select --> RSSelection_RSSelection RSSelection_RSSelection --> FIFO11_write -RSSelection_RSSelection <--> LSUDummy_select +RSSelection_RSSelection1 --> FIFO11_write +RSSelection_RSSelection1 <--> LSUDummy_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -452,26 +452,26 @@ ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update -RS_RS1 --> WakeupSelect_WakeupSelect +RS_RS --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect RS_take --> WakeupSelect3_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO2_write -RS_RS2 --> WakeupSelect1_WakeupSelect +RS_RS1 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write -RS_RS --> WakeupSelect2_WakeupSelect +RS_RS2 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> ExceptionCauseRegister_report WakeupSelect3_WakeupSelect --> ExceptionCauseRegister_report -LSUDummyInternals_LSUDummyInternals2 --> ExceptionCauseRegister_report LSUDummyInternals_LSUDummyInternals --> ExceptionCauseRegister_report +LSUDummyInternals_LSUDummyInternals1 --> ExceptionCauseRegister_report ReorderBuffer_get_indices --> WakeupSelect2_WakeupSelect ReorderBuffer_get_indices --> WakeupSelect3_WakeupSelect -ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals2 ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals +ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals1 WakeupSelect2_WakeupSelect --> FIFO4_write WakeupSelect2_WakeupSelect --> FIFO5_write RS_RS3 --> WakeupSelect3_WakeupSelect @@ -489,9 +489,9 @@ FIFO4_read --> ConnectTrans4_ConnectTrans ExceptionFuncUnit_accept --> ConnectTrans5_ConnectTrans FIFO6_read --> ConnectTrans5_ConnectTrans -LSUDummyInternals_LSUDummyInternals1 --> WishboneMaster1_request -WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals -Forwarder1_read --> LSUDummyInternals_LSUDummyInternals +LSUDummyInternals_LSUDummyInternals2 --> WishboneMaster1_request +WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals1 +Forwarder1_read --> LSUDummyInternals_LSUDummyInternals1 ConnectTrans_ConnectTrans --> Forwarder4_write ConnectTrans1_ConnectTrans --> Forwarder4_write RSFuncBlock_get_result --> ConnectTrans_ConnectTrans @@ -530,7 +530,7 @@

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/components/icache.html b/components/icache.html index f15665770..c1a2280eb 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index c1047878e..de37b8242 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -399,7 +399,7 @@

Submodules

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diff --git a/coreblocks.fu.html b/coreblocks.fu.html index 692668e5d..26d66a2d4 100644 --- a/coreblocks.fu.html +++ b/coreblocks.fu.html @@ -898,7 +898,7 @@

Submodules

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diff --git a/coreblocks.fu.unsigned_multiplication.html b/coreblocks.fu.unsigned_multiplication.html index 33e032214..13c0f68ec 100644 --- a/coreblocks.fu.unsigned_multiplication.html +++ b/coreblocks.fu.unsigned_multiplication.html @@ -237,7 +237,7 @@

Submodules

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diff --git a/coreblocks.html b/coreblocks.html index ea78503a8..6abd5561a 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -215,7 +215,7 @@

Submodules

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diff --git a/coreblocks.params.html b/coreblocks.params.html index 9e39249c8..5fa92e2c6 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -2663,7 +2663,7 @@

Submodules

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diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index 34c458ea8..0b579112c 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -348,7 +348,7 @@

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diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index f7f7579c4..1389e4048 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

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diff --git a/coreblocks.stages.html b/coreblocks.stages.html index f1fb7f968..4df237d67 100644 --- a/coreblocks.stages.html +++ b/coreblocks.stages.html @@ -263,7 +263,7 @@

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diff --git a/coreblocks.structs_common.html b/coreblocks.structs_common.html index a7d932798..8a0f24588 100644 --- a/coreblocks.structs_common.html +++ b/coreblocks.structs_common.html @@ -454,7 +454,7 @@

Submodules

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diff --git a/coreblocks.utils.html b/coreblocks.utils.html index dd8af740f..56ede6215 100644 --- a/coreblocks.utils.html +++ b/coreblocks.utils.html @@ -165,7 +165,7 @@

Submodules

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diff --git a/genindex.html b/genindex.html index 4dc93ab3b..5ced64628 100644 --- a/genindex.html +++ b/genindex.html @@ -2871,7 +2871,7 @@

Z

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diff --git a/index.html b/index.html index 0e3a45de2..5bbf69e2d 100644 --- a/index.html +++ b/index.html @@ -221,7 +221,7 @@

Coreblocks

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diff --git a/miscellany/exceptionsSummary.html b/miscellany/exceptionsSummary.html index 783637670..c9972d0cc 100644 --- a/miscellany/exceptionsSummary.html +++ b/miscellany/exceptionsSummary.html @@ -271,7 +271,7 @@

Summary

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diff --git a/modules-coreblocks.html b/modules-coreblocks.html index 8e24a28e9..17560f176 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -184,7 +184,7 @@

coreblocks

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diff --git a/modules-transactron.html b/modules-transactron.html index c4bd2d5f5..d43c09b80 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -126,7 +126,7 @@

transactron

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diff --git a/py-modindex.html b/py-modindex.html index 4115c44e3..134515089 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -458,7 +458,7 @@

Python Module Index

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diff --git a/scheduler/Overview.html b/scheduler/Overview.html index 1466af130..5a497e1eb 100644 --- a/scheduler/Overview.html +++ b/scheduler/Overview.html @@ -146,7 +146,7 @@

More detailed description of each block

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diff --git a/search.html b/search.html index 229ba1224..3e9bf82b4 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

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"sphinx.domains.index": 1, "sphinx.domains.javascript": 2, "sphinx.domains.math": 2, "sphinx.domains.python": 3, "sphinx.domains.rst": 2, "sphinx.domains.std": 2, "sphinx.ext.todo": 2, "sphinx": 56}}) \ No newline at end of file diff --git a/shared_structs/Implementation/RS_impl.html b/shared_structs/Implementation/RS_impl.html index 182cd2c05..77bc063d0 100644 --- a/shared_structs/Implementation/RS_impl.html +++ b/shared_structs/Implementation/RS_impl.html @@ -252,7 +252,7 @@

Read and clean row

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/shared_structs/RS.html b/shared_structs/RS.html index c9648f9f6..fd4f167e4 100644 --- a/shared_structs/RS.html +++ b/shared_structs/RS.html @@ -222,7 +222,7 @@

External interface signals

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/synthesis/Synthesis.html b/synthesis/Synthesis.html index 946448531..4cb255c39 100644 --- a/synthesis/Synthesis.html +++ b/synthesis/Synthesis.html @@ -151,7 +151,7 @@

Benchmarks

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/transactron.html b/transactron.html index 1ec55c788..84be2cbb5 100644 --- a/transactron.html +++ b/transactron.html @@ -185,7 +185,7 @@

Submodules
-body(m: ~transactron.core.TModule, *, ready: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1), out: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 0'd0)) → Iterator[Record]
+body(m: ~transactron.core.TModule, *, ready: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1), out: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 0'd0), validate_arguments: ~typing.Optional[~collections.abc.Callable[[...], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable]] = None) → Iterator[Record]

Define method body

The body context manager can be used to define the actions performed by a Method when it’s run. Each assignment added to @@ -207,6 +207,12 @@

SubmodulesReturns @@ -545,7 +551,7 @@

Submodules
-transactron.core.def_method(m: ~transactron.core.TModule, method: ~transactron.core.Method, ready: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1))
+transactron.core.def_method(m: ~transactron.core.TModule, method: ~transactron.core.Method, ready: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1), validate_arguments: ~typing.Optional[~collections.abc.Callable[[...], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable]] = None)

Define a method.

This decorator allows to define transactional methods in an elegant way using Python’s def syntax. Internally, def_method @@ -567,6 +573,12 @@

Submodules
-body(m: ~transactron.core.TModule, *, ready: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1), out: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 0'd0)) → Iterator[Record]
+body(m: ~transactron.core.TModule, *, ready: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1), out: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 0'd0), validate_arguments: ~typing.Optional[~collections.abc.Callable[[...], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable]] = None) → Iterator[Record]

Define method body

The body context manager can be used to define the actions performed by a Method when it’s run. Each assignment added to @@ -929,6 +941,12 @@

SubmodulesReturns @@ -1243,7 +1261,7 @@

Submodules
-transactron.def_method(m: ~transactron.core.TModule, method: ~transactron.core.Method, ready: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1))
+transactron.def_method(m: ~transactron.core.TModule, method: ~transactron.core.Method, ready: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1), validate_arguments: ~typing.Optional[~collections.abc.Callable[[...], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable]] = None)

Define a method.

This decorator allows to define transactional methods in an elegant way using Python’s def syntax. Internally, def_method @@ -1265,6 +1283,12 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/transactron.lib.html b/transactron.lib.html index 326d0a9f7..ad7f3299d 100644 --- a/transactron.lib.html +++ b/transactron.lib.html @@ -897,7 +897,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.

diff --git a/transactron.utils.html b/transactron.utils.html index f6bdf2321..ef7aab781 100644 --- a/transactron.utils.html +++ b/transactron.utils.html @@ -420,7 +420,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:57 2023-11-14. + Last updated on 12:57 2023-11-14.