From dcc9692e9994313dcf163fb8ec90e4a2faa2b773 Mon Sep 17 00:00:00 2001 From: tilk Date: Mon, 1 Apr 2024 14:50:26 +0000 Subject: [PATCH] More metrics for RF, RS and ROB (#632) --- .doctrees/api.doctree | Bin 21253 -> 21253 bytes .doctrees/auto_graph.doctree | Bin 45216 -> 49013 bytes .doctrees/coreblocks.func_blocks.lsu.doctree | Bin 53003 -> 54557 bytes .doctrees/coreblocks.params.doctree | Bin 372086 -> 373215 bytes .doctrees/current-graph.doctree | Bin 46437 -> 50234 bytes .doctrees/environment.pickle | Bin 508297 -> 510305 bytes .doctrees/transactron.lib.doctree | Bin 855172 -> 901330 bytes _sources/auto_graph.rst.txt | 475 +++++++++-------- api.html | 2 +- assumptions.html | 2 +- auto_graph.html | 477 ++++++++++-------- components/icache.html | 2 +- coreblocks.backend.html | 2 +- coreblocks.cache.html | 2 +- coreblocks.core_structs.html | 2 +- coreblocks.frontend.decoder.html | 2 +- coreblocks.frontend.fetch.html | 2 +- coreblocks.frontend.html | 2 +- coreblocks.func_blocks.fu.html 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b/_sources/auto_graph.rst.txt index 5d0d74fa6..6c23526fd 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -4,12 +4,12 @@ subgraph TransactionModule["TransactionModule"] subgraph CoreTestElaboratable["elaboratable CoreTestElaboratable"] subgraph Core["core Core"] - Core_DiscardBranchVerify["DiscardBranchVerify"] Core_InitFreeRFFifo["InitFreeRFFifo"] + Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_request["request"] WishboneMaster_result["result"] WishboneMaster_WishboneMaster["WishboneMaster"] + WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] Forwarder_read["read"] Forwarder_write["write"] @@ -25,8 +25,8 @@ end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_get_read_response["get_read_response"] WishboneMasterAdapter_request_read["request_read"] + WishboneMasterAdapter_get_read_response["get_read_response"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] @@ -37,28 +37,28 @@ end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] + WishboneMasterAdapter1_request_read["request_read"] WishboneMasterAdapter1_get_write_response["get_write_response"] - WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_write["request_write"] - WishboneMasterAdapter1_request_read["request_read"] + WishboneMasterAdapter1_get_read_response["get_read_response"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_read["read"] BasicFifo1_write["write"] + BasicFifo1_read["read"] end end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_decrement["decrement"] CoreInstructionCounter_increment["increment"] + CoreInstructionCounter_decrement["decrement"] end subgraph FIFO["fifo_fetch FIFO"] - FIFO_write["write"] FIFO_read["read"] + FIFO_write["write"] end subgraph MethodMap["core_counter_increment_discard_map MethodMap"] MethodMap_method["method"] @@ -67,25 +67,25 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_write["write"] BasicFifo2_read["read"] + BasicFifo2_write["write"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_read["read"] Forwarder2_write["write"] + Forwarder2_read["read"] end end subgraph ICache["icache ICache"] - ICache_ICache["ICache"] - ICache_issue_req["issue_req"] ICache_accept_res["accept_res"] - ICache_ICache1["ICache"] ICache_MemRead["MemRead"] + ICache_issue_req["issue_req"] + ICache_ICache["ICache"] + ICache_ICache1["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -101,9 +101,9 @@ subgraph HwCounter4["perf_flushes HwCounter"] HwCounter4__incr["_incr"] end - subgraph LatencyMeasurer["req_latency LatencyMeasurer"] - LatencyMeasurer__start["_start"] - LatencyMeasurer__stop["_stop"] + subgraph FIFOLatencyMeasurer["req_latency FIFOLatencyMeasurer"] + FIFOLatencyMeasurer__start["_start"] + FIFOLatencyMeasurer__stop["_stop"] subgraph HwExpHistogram["histogram HwExpHistogram"] HwExpHistogram__add["_add"] end @@ -113,10 +113,10 @@ end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_write_results["write_results"] ArgumentsToResultsZipper_read["read"] - ArgumentsToResultsZipper_peek_arg["peek_arg"] ArgumentsToResultsZipper_write_args["write_args"] + ArgumentsToResultsZipper_write_results["write_results"] + ArgumentsToResultsZipper_peek_arg["peek_arg"] subgraph BasicFifo3["fifo BasicFifo"] BasicFifo3_peek["peek"] BasicFifo3_read["read"] @@ -136,28 +136,47 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] + RegisterFile_perf["perf"] RegisterFile_read2["read2"] - RegisterFile_write["write"] - RegisterFile_read1["read1"] RegisterFile_free["free"] + RegisterFile_read1["read1"] + RegisterFile_write["write"] + subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] + TaggedLatencyMeasurer__stop["_stop"] + TaggedLatencyMeasurer__start["_start"] + subgraph HwExpHistogram1["histogram HwExpHistogram"] + HwExpHistogram1__add["_add"] + end + subgraph AsyncMemoryBank["slots AsyncMemoryBank"] + AsyncMemoryBank_write["write"] + AsyncMemoryBank_read["read"] + end + end + subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] + HwExpHistogram2__add["_add"] + end end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_peek["peek"] ReorderBuffer_put["put"] - ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_mark_done["mark_done"] ReorderBuffer_retire["retire"] - subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] - LatencyMeasurer1__start["_start"] - LatencyMeasurer1__stop["_stop"] - subgraph HwExpHistogram1["histogram HwExpHistogram"] - HwExpHistogram1__add["_add"] + ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_peek["peek"] + ReorderBuffer_perf["perf"] + subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] + FIFOLatencyMeasurer1__stop["_stop"] + FIFOLatencyMeasurer1__start["_start"] + subgraph HwExpHistogram3["histogram HwExpHistogram"] + HwExpHistogram3__add["_add"] end subgraph FIFO2["fifo FIFO"] FIFO2_write["write"] FIFO2_read["read"] end end + subgraph HwExpHistogram4["perf_rob_size HwExpHistogram"] + HwExpHistogram4__add["_add"] + end end subgraph Fetch["fetch Fetch"] Fetch_Fetch["Fetch"] @@ -165,14 +184,14 @@ Fetch_Fetch1["Fetch"] Fetch_stall_exception["stall_exception"] subgraph BasicFifo4["fetch_target_queue BasicFifo"] - BasicFifo4_read["read"] BasicFifo4_write["write"] + BasicFifo4_read["read"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] ExceptionCauseRegister_clear["clear"] + ExceptionCauseRegister_report["report"] subgraph BasicFifo5["fu_report_fifo BasicFifo"] BasicFifo5_read["read"] BasicFifo5_write["write"] @@ -185,8 +204,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_read["read"] Forwarder4_write["write"] + Forwarder4_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -209,47 +228,62 @@ RSFuncBlock_get_result["get_result"] RSFuncBlock_select["select"] subgraph RS["rs RS"] + RS_update["update"] RS_RS["RS"] - RS_take["take"] RS_RS1["RS"] + RS_perf["perf"] RS_RS2["RS"] - RS_insert["insert"] + RS_select["select"] + RS_take["take"] RS_RS3["RS"] RS_RS4["RS"] - RS_update["update"] - RS_select["select"] + RS_insert["insert"] + subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] + TaggedLatencyMeasurer1__stop["_stop"] + TaggedLatencyMeasurer1__start["_start"] + subgraph HwExpHistogram5["histogram HwExpHistogram"] + HwExpHistogram5__add["_add"] + end + subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] + AsyncMemoryBank1_write["write"] + AsyncMemoryBank1_read["read"] + end + end + subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] + HwExpHistogram6__add["_add"] + end end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph TaggedCounter["perf_instr TaggedCounter"] TaggedCounter__incr["_incr"] end subgraph FIFO3["fifo FIFO"] - FIFO3_read["read"] FIFO3_write["write"] + FIFO3_read["read"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_issue["issue"] ShiftFuncUnit_accept["accept"] + ShiftFuncUnit_issue["issue"] subgraph FIFO4["fifo FIFO"] - FIFO4_read["read"] FIFO4_write["write"] + FIFO4_read["read"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_issue["issue"] JumpBranchFuncUnit_accept["accept"] + JumpBranchFuncUnit_issue["issue"] subgraph FIFO5["fifo_branch_resolved FIFO"] - FIFO5_write["write"] FIFO5_read["read"] + FIFO5_write["write"] end subgraph TaggedCounter1["perf_instr TaggedCounter"] TaggedCounter1__incr["_incr"] @@ -266,20 +300,20 @@ WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] + ExceptionFuncUnit_issue["issue"] subgraph FIFO7["fifo FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] - PrivilegedFuncUnit_accept["accept"] - PrivilegedFuncUnit_precommit["precommit"] PrivilegedFuncUnit_issue["issue"] + PrivilegedFuncUnit_precommit["precommit"] + PrivilegedFuncUnit_accept["accept"] subgraph BasicFifo6["fetch_resume_fifo BasicFifo"] BasicFifo6_read["read"] BasicFifo6_write["write"] @@ -291,8 +325,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_write["write"] Forwarder5_read["read"] + Forwarder5_write["write"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans4["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -314,36 +348,36 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] + LSUDummy_insert["insert"] + LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_update["update"] + LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_select["select"] LSUDummy_precommit["precommit"] - LSUDummy_LSUDummy["LSUDummy"] LSUDummy_get_result["get_result"] - LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_insert["insert"] LSUDummy_LSUDummy2["LSUDummy"] - LSUDummy_update["update"] subgraph Forwarder6["forwarder Forwarder"] Forwarder6_read["read"] Forwarder6_write["write"] end subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond2["issue_cond2"] - LSURequester_accept_cond1["accept_cond1"] - LSURequester_issue_cond0["issue_cond0"] - LSURequester_issue["issue"] LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue["issue"] + LSURequester_accept_cond1["accept_cond1"] + LSURequester_issue_cond2["issue_cond2"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond0["issue_cond0"] LSURequester_accept["accept"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] + CSRUnit_insert["insert"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_select["select"] + CSRUnit_fetch_resume["fetch_resume"] CSRUnit_update["update"] - CSRUnit_CSRUnit["CSRUnit"] - CSRUnit_precommit["precommit"] CSRUnit_get_result["get_result"] - CSRUnit_insert["insert"] - CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_precommit["precommit"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] @@ -379,46 +413,46 @@ GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] - CSRRegister__fu_write["_fu_write"] - CSRRegister_write["write"] CSRRegister__fu_read["_fu_read"] + CSRRegister_write["write"] + CSRRegister__fu_write["_fu_write"] end subgraph CSRRegister1["mtvec CSRRegister"] + CSRRegister1__fu_write["_fu_write"] CSRRegister1__fu_read["_fu_read"] CSRRegister1_read["read"] - CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] + CSRRegister2_read["read"] + CSRRegister2__fu_write["_fu_write"] CSRRegister2_write["write"] CSRRegister2__fu_read["_fu_read"] - CSRRegister2__fu_write["_fu_write"] - CSRRegister2_read["read"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] + CSRRegister3__fu_read["_fu_read"] CSRRegister3_read["read"] CSRRegister3_write["write"] - CSRRegister3__fu_read["_fu_read"] end subgraph CSRRegister4["register_high CSRRegister"] CSRRegister4_read["read"] - CSRRegister4__fu_read["_fu_read"] CSRRegister4_write["write"] + CSRRegister4__fu_read["_fu_read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_write["write"] CSRRegister5__fu_read["_fu_read"] CSRRegister5_read["read"] + CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] CSRRegister6_write["write"] - CSRRegister6__fu_read["_fu_read"] CSRRegister6_read["read"] + CSRRegister6__fu_read["_fu_read"] end end end @@ -441,8 +475,8 @@ RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO10["rename_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] @@ -455,8 +489,8 @@ ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO12["rs_select_out_buf FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -476,24 +510,24 @@ ConnectTrans11_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_core_state["core_state"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement["Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement1["Retirement"] Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] Retirement_Retirement4["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] CSRRegister7_read["read"] - CSRRegister7__fu_read["_fu_read"] CSRRegister7_write["write"] + CSRRegister7__fu_read["_fu_read"] end subgraph CSRRegister8["register_high CSRRegister"] - CSRRegister8__fu_read["_fu_read"] CSRRegister8_write["write"] + CSRRegister8__fu_read["_fu_read"] CSRRegister8_read["read"] end end @@ -514,32 +548,34 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] + TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] + TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] + TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] - TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] - TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] - TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] - TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] end end Core_InitFreeRFFifo --> BasicFifo2_write - Retirement_Retirement2 --> BasicFifo2_write - TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write - TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write + Retirement_Retirement4 --> BasicFifo2_write + TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write + TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write FIFO5_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Serializer_Serializer1 - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> BasicFifo_write - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMaster_request - WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Forwarder2_write + RegisterFile_perf --> HwExpHistogram2__add + ReorderBuffer_perf --> HwExpHistogram4__add + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request + WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + Serializer_Serializer1 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write ICache_ICache1 <--> HwCounter4__incr ArgumentsToResultsZipper_peek_arg --> ICache_MemRead BasicFifo3_peek --> ICache_MemRead @@ -551,28 +587,28 @@ SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache Forwarder2_read --> ICache_ICache ICache_ICache <--> HwCounter3__incr - Fetch_Fetch --> ICache_issue_req - Fetch_Fetch <--> HwCounter__incr - Fetch_Fetch <--> LatencyMeasurer__start - Fetch_Fetch --> FIFO1_write - Fetch_Fetch --> ArgumentsToResultsZipper_write_args - Fetch_Fetch --> BasicFifo3_write - Fetch_Fetch --> BasicFifo4_write - BasicFifo4_read --> Fetch_Fetch1 - ICache_accept_res --> Fetch_Fetch1 - Fetch_Fetch1 <--> LatencyMeasurer__stop - FIFO1_read --> Fetch_Fetch1 - Fetch_Fetch1 --> HwExpHistogram__add - ArgumentsToResultsZipper_read --> Fetch_Fetch1 - BasicFifo3_read --> Fetch_Fetch1 - Forwarder3_read --> Fetch_Fetch1 - Fetch_Fetch1 --> MethodProduct_method + Fetch_Fetch1 --> ICache_issue_req + Fetch_Fetch1 <--> HwCounter__incr + Fetch_Fetch1 <--> FIFOLatencyMeasurer__start + Fetch_Fetch1 --> FIFO1_write + Fetch_Fetch1 --> ArgumentsToResultsZipper_write_args + Fetch_Fetch1 --> BasicFifo3_write + Fetch_Fetch1 --> BasicFifo4_write + BasicFifo4_read --> Fetch_Fetch + ICache_accept_res --> Fetch_Fetch + Fetch_Fetch <--> FIFOLatencyMeasurer__stop + FIFO1_read --> Fetch_Fetch + Fetch_Fetch --> HwExpHistogram__add + ArgumentsToResultsZipper_read --> Fetch_Fetch + BasicFifo3_read --> Fetch_Fetch + Forwarder3_read --> Fetch_Fetch + Fetch_Fetch --> MethodProduct_method AdapterTrans_AdapterTrans_method --> MethodProduct_method - Fetch_Fetch1 --> FIFO_write + Fetch_Fetch --> FIFO_write AdapterTrans_AdapterTrans_method --> FIFO_write - Fetch_Fetch1 --> MethodMap_method + Fetch_Fetch --> MethodMap_method AdapterTrans_AdapterTrans_method --> MethodMap_method - Fetch_Fetch1 <--> CoreInstructionCounter_increment + Fetch_Fetch <--> CoreInstructionCounter_increment AdapterTrans_AdapterTrans_method <--> CoreInstructionCounter_increment FIFO_read --> DecodeStage_DecodeStage DecodeStage_DecodeStage <--> HwCounter6__incr @@ -582,32 +618,34 @@ RegAllocation_RegAllocation --> FIFO9_write FIFO9_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename - Retirement_Retirement2 --> FRAT_rename - TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename + Retirement_Retirement4 --> FRAT_rename + TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO10_write FIFO10_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put - ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start + ROBAllocation_ROBAllocation <--> FIFOLatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO2_write ROBAllocation_ROBAllocation --> FIFO11_write - FIFO11_read --> RSSelection_RSSelection - RSSelection_RSSelection --> Forwarder8_write - Forwarder8_read --> RSSelection_RSSelection3 - Forwarder8_read --> RSSelection_RSSelection2 + FIFO11_read --> RSSelection_RSSelection3 + RSSelection_RSSelection3 --> Forwarder8_write + Forwarder8_read --> RSSelection_RSSelection Forwarder8_read --> RSSelection_RSSelection1 - RSFuncBlock_select --> RSSelection_RSSelection3 - RS_select --> RSSelection_RSSelection3 - RSSelection_RSSelection3 --> FIFO12_write - RSSelection_RSSelection2 --> FIFO12_write + Forwarder8_read --> RSSelection_RSSelection2 + RSFuncBlock_select --> RSSelection_RSSelection + RS_select --> RSSelection_RSSelection + RSSelection_RSSelection --> FIFO12_write RSSelection_RSSelection1 --> FIFO12_write - RSSelection_RSSelection2 <--> LSUDummy_select - RSSelection_RSSelection1 <--> CSRUnit_select + RSSelection_RSSelection2 --> FIFO12_write + RSSelection_RSSelection1 <--> LSUDummy_select + RSSelection_RSSelection2 <--> CSRUnit_select FIFO12_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion Retirement_core_state --> RSInsertion_RSInsertion RSInsertion_RSInsertion --> RSFuncBlock_insert RSInsertion_RSInsertion --> RS_insert + RSInsertion_RSInsertion --> TaggedLatencyMeasurer1__start + RSInsertion_RSInsertion --> AsyncMemoryBank1_write RSInsertion_RSInsertion --> LSUDummy_insert RSInsertion_RSInsertion --> CSRUnit_insert BasicFifo5_read --> ConnectTrans_ConnectTrans @@ -617,22 +655,40 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume - Retirement_Retirement1 --> Fetch_resume + Retirement_Retirement --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done ResultAnnouncement_ResultAnnouncement --> RegisterFile_write + ResultAnnouncement_ResultAnnouncement --> TaggedLatencyMeasurer__start + ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_write ResultAnnouncement_ResultAnnouncement --> MethodProduct1_method ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update - RS_RS --> WakeupSelect_WakeupSelect + RS_perf --> HwExpHistogram6__add + RS_RS2 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect RS_take --> WakeupSelect3_WakeupSelect RS_take --> WakeupSelect4_WakeupSelect + WakeupSelect_WakeupSelect --> TaggedLatencyMeasurer1__stop + WakeupSelect1_WakeupSelect --> TaggedLatencyMeasurer1__stop + WakeupSelect2_WakeupSelect --> TaggedLatencyMeasurer1__stop + WakeupSelect3_WakeupSelect --> TaggedLatencyMeasurer1__stop + WakeupSelect4_WakeupSelect --> TaggedLatencyMeasurer1__stop + AsyncMemoryBank1_read --> WakeupSelect_WakeupSelect + AsyncMemoryBank1_read --> WakeupSelect1_WakeupSelect + AsyncMemoryBank1_read --> WakeupSelect2_WakeupSelect + AsyncMemoryBank1_read --> WakeupSelect3_WakeupSelect + AsyncMemoryBank1_read --> WakeupSelect4_WakeupSelect + WakeupSelect_WakeupSelect --> HwExpHistogram5__add + WakeupSelect1_WakeupSelect --> HwExpHistogram5__add + WakeupSelect2_WakeupSelect --> HwExpHistogram5__add + WakeupSelect3_WakeupSelect --> HwExpHistogram5__add + WakeupSelect4_WakeupSelect --> HwExpHistogram5__add WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter__incr WakeupSelect_WakeupSelect --> FIFO3_write @@ -650,7 +706,7 @@ ConnectTrans3_ConnectTrans --> BasicFifo5_write WakeupSelect2_WakeupSelect --> FIFO6_write WakeupSelect2_WakeupSelect --> FIFO5_write - RS_RS2 --> WakeupSelect3_WakeupSelect + RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO7_write RS_RS1 --> WakeupSelect4_WakeupSelect @@ -671,12 +727,12 @@ PrivilegedFuncUnit_accept --> ConnectTrans8_ConnectTrans CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo6_write - LSUDummy_LSUDummy2 --> Forwarder6_write + LSUDummy_LSUDummy --> Forwarder6_write TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write - TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write - TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write - TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write + TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write + TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write + TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -698,45 +754,54 @@ LSUDummy_get_result --> ConnectTrans2_ConnectTrans Forwarder6_read --> ConnectTrans2_ConnectTrans CSRUnit_get_result --> ConnectTrans3_ConnectTrans - MethodTryProduct_MethodTryProduct1 --> PrivilegedFuncUnit_precommit - MethodTryProduct_MethodTryProduct1 <--> InterruptController_mret + MethodTryProduct_MethodTryProduct2 --> PrivilegedFuncUnit_precommit + MethodTryProduct_MethodTryProduct2 <--> InterruptController_mret MethodTryProduct_MethodTryProduct --> LSUDummy_precommit - MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit + MethodTryProduct_MethodTryProduct1 --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo6_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans - ReorderBuffer_peek --> Retirement_Retirement - ReorderBuffer_peek --> Retirement_Retirement3 + ReorderBuffer_peek --> Retirement_Retirement1 ReorderBuffer_peek --> Retirement_Retirement2 - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 - ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement --> MethodTryProduct_method - ExceptionCauseRegister_get --> Retirement_Retirement3 - ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement2 <--> ReorderBuffer_retire - TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire - TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire - Retirement_Retirement2 <--> LatencyMeasurer1__stop - TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop - TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop - FIFO2_read --> Retirement_Retirement2 - FIFO2_read --> TransactionManager_Retirement_Retirement_cond1 - FIFO2_read --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement2 --> HwExpHistogram1__add - TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add - CoreInstructionCounter_decrement --> Retirement_Retirement2 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement - RRAT_peek --> Retirement_Retirement2 - RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement2 --> RegisterFile_free - TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free - TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free - CSRRegister1_read --> Retirement_Retirement1 - Retirement_Retirement1 <--> ExceptionCauseRegister_clear + ReorderBuffer_peek --> Retirement_Retirement4 + ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement1 --> MethodTryProduct_method + ExceptionCauseRegister_get --> Retirement_Retirement2 + ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement + ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement4 <--> ReorderBuffer_retire + TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire + TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire + Retirement_Retirement4 <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop + FIFO2_read --> Retirement_Retirement4 + FIFO2_read --> TransactionManager_Retirement_cond1_Retirement + FIFO2_read --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement4 --> HwExpHistogram3__add + TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram3__add + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add + CoreInstructionCounter_decrement --> Retirement_Retirement4 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 + RRAT_peek --> Retirement_Retirement4 + RRAT_peek --> TransactionManager_Retirement_cond1_Retirement + Retirement_Retirement4 --> RegisterFile_free + TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free + TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free + Retirement_Retirement4 --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_cond1_Retirement --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop + AsyncMemoryBank_read --> Retirement_Retirement4 + AsyncMemoryBank_read --> TransactionManager_Retirement_cond1_Retirement + AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement4 --> HwExpHistogram1__add + TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add + CSRRegister1_read --> Retirement_Retirement + Retirement_Retirement <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -749,52 +814,52 @@ GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 - TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 - TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 - TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy2 + TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy2 + TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy2 TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue - TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue - TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy - TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy - LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy - TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 - Serializer1_Serializer1 --> TransactionManager_LSUDummy_accept_cond0 - BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 + TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write + TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer + TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write + TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write + TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request + TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request + TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy + Serializer1_Serializer1 --> TransactionManager_accept_cond0_LSUDummy + BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy - WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 + WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy - Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 + Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement4 - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement4 - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write - TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry - TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 - TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy - Serializer1_Serializer --> TransactionManager_accept_cond1_LSUDummy - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_cond0_Retirement --> RRAT_commit - TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment - CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write - CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write - TransactionManager_Retirement_cond0_Retirement <--> HwCounter7__incr + TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy1 + LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy + LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3 - TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write - TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write - TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request - TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request - TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 - TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write - TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer2 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3 + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement3 + TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write + TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write + TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit + TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment + CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write + CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond0 <--> HwCounter7__incr + TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy + Serializer1_Serializer2 --> TransactionManager_accept_cond1_LSUDummy diff --git a/api.html b/api.html index 301606e39..a64d2a0d0 100644 --- a/api.html +++ b/api.html @@ -259,7 +259,7 @@

    transactron

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/assumptions.html b/assumptions.html index 5714ab429..2949bba04 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

    List of assumptions made during development

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/auto_graph.html b/auto_graph.html index ef3752d69..91bc261ff 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -83,12 +83,12 @@ subgraph TransactionModule["TransactionModule"] subgraph CoreTestElaboratable["elaboratable CoreTestElaboratable"] subgraph Core["core Core"] - Core_DiscardBranchVerify["DiscardBranchVerify"] Core_InitFreeRFFifo["InitFreeRFFifo"] + Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_request["request"] WishboneMaster_result["result"] WishboneMaster_WishboneMaster["WishboneMaster"] + WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] Forwarder_read["read"] Forwarder_write["write"] @@ -104,8 +104,8 @@ end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_get_read_response["get_read_response"] WishboneMasterAdapter_request_read["request_read"] + WishboneMasterAdapter_get_read_response["get_read_response"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] @@ -116,28 +116,28 @@ end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] + WishboneMasterAdapter1_request_read["request_read"] WishboneMasterAdapter1_get_write_response["get_write_response"] - WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_write["request_write"] - WishboneMasterAdapter1_request_read["request_read"] + WishboneMasterAdapter1_get_read_response["get_read_response"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_read["read"] BasicFifo1_write["write"] + BasicFifo1_read["read"] end end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_decrement["decrement"] CoreInstructionCounter_increment["increment"] + CoreInstructionCounter_decrement["decrement"] end subgraph FIFO["fifo_fetch FIFO"] - FIFO_write["write"] FIFO_read["read"] + FIFO_write["write"] end subgraph MethodMap["core_counter_increment_discard_map MethodMap"] MethodMap_method["method"] @@ -146,25 +146,25 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_write["write"] BasicFifo2_read["read"] + BasicFifo2_write["write"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_read["read"] Forwarder2_write["write"] + Forwarder2_read["read"] end end subgraph ICache["icache ICache"] - ICache_ICache["ICache"] - ICache_issue_req["issue_req"] ICache_accept_res["accept_res"] - ICache_ICache1["ICache"] ICache_MemRead["MemRead"] + ICache_issue_req["issue_req"] + ICache_ICache["ICache"] + ICache_ICache1["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -180,9 +180,9 @@ subgraph HwCounter4["perf_flushes HwCounter"] HwCounter4__incr["_incr"] end - subgraph LatencyMeasurer["req_latency LatencyMeasurer"] - LatencyMeasurer__start["_start"] - LatencyMeasurer__stop["_stop"] + subgraph FIFOLatencyMeasurer["req_latency FIFOLatencyMeasurer"] + FIFOLatencyMeasurer__start["_start"] + FIFOLatencyMeasurer__stop["_stop"] subgraph HwExpHistogram["histogram HwExpHistogram"] HwExpHistogram__add["_add"] end @@ -192,10 +192,10 @@ end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_write_results["write_results"] ArgumentsToResultsZipper_read["read"] - ArgumentsToResultsZipper_peek_arg["peek_arg"] ArgumentsToResultsZipper_write_args["write_args"] + ArgumentsToResultsZipper_write_results["write_results"] + ArgumentsToResultsZipper_peek_arg["peek_arg"] subgraph BasicFifo3["fifo BasicFifo"] BasicFifo3_peek["peek"] BasicFifo3_read["read"] @@ -215,28 +215,47 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] + RegisterFile_perf["perf"] RegisterFile_read2["read2"] - RegisterFile_write["write"] - RegisterFile_read1["read1"] RegisterFile_free["free"] + RegisterFile_read1["read1"] + RegisterFile_write["write"] + subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] + TaggedLatencyMeasurer__stop["_stop"] + TaggedLatencyMeasurer__start["_start"] + subgraph HwExpHistogram1["histogram HwExpHistogram"] + HwExpHistogram1__add["_add"] + end + subgraph AsyncMemoryBank["slots AsyncMemoryBank"] + AsyncMemoryBank_write["write"] + AsyncMemoryBank_read["read"] + end + end + subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] + HwExpHistogram2__add["_add"] + end end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_peek["peek"] ReorderBuffer_put["put"] - ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_mark_done["mark_done"] ReorderBuffer_retire["retire"] - subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] - LatencyMeasurer1__start["_start"] - LatencyMeasurer1__stop["_stop"] - subgraph HwExpHistogram1["histogram HwExpHistogram"] - HwExpHistogram1__add["_add"] + ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_peek["peek"] + ReorderBuffer_perf["perf"] + subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] + FIFOLatencyMeasurer1__stop["_stop"] + FIFOLatencyMeasurer1__start["_start"] + subgraph HwExpHistogram3["histogram HwExpHistogram"] + HwExpHistogram3__add["_add"] end subgraph FIFO2["fifo FIFO"] FIFO2_write["write"] FIFO2_read["read"] end end + subgraph HwExpHistogram4["perf_rob_size HwExpHistogram"] + HwExpHistogram4__add["_add"] + end end subgraph Fetch["fetch Fetch"] Fetch_Fetch["Fetch"] @@ -244,14 +263,14 @@ Fetch_Fetch1["Fetch"] Fetch_stall_exception["stall_exception"] subgraph BasicFifo4["fetch_target_queue BasicFifo"] - BasicFifo4_read["read"] BasicFifo4_write["write"] + BasicFifo4_read["read"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] ExceptionCauseRegister_clear["clear"] + ExceptionCauseRegister_report["report"] subgraph BasicFifo5["fu_report_fifo BasicFifo"] BasicFifo5_read["read"] BasicFifo5_write["write"] @@ -264,8 +283,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_read["read"] Forwarder4_write["write"] + Forwarder4_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -288,47 +307,62 @@ RSFuncBlock_get_result["get_result"] RSFuncBlock_select["select"] subgraph RS["rs RS"] + RS_update["update"] RS_RS["RS"] - RS_take["take"] RS_RS1["RS"] + RS_perf["perf"] RS_RS2["RS"] - RS_insert["insert"] + RS_select["select"] + RS_take["take"] RS_RS3["RS"] RS_RS4["RS"] - RS_update["update"] - RS_select["select"] + RS_insert["insert"] + subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] + TaggedLatencyMeasurer1__stop["_stop"] + TaggedLatencyMeasurer1__start["_start"] + subgraph HwExpHistogram5["histogram HwExpHistogram"] + HwExpHistogram5__add["_add"] + end + subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] + AsyncMemoryBank1_write["write"] + AsyncMemoryBank1_read["read"] + end + end + subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] + HwExpHistogram6__add["_add"] + end end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph TaggedCounter["perf_instr TaggedCounter"] TaggedCounter__incr["_incr"] end subgraph FIFO3["fifo FIFO"] - FIFO3_read["read"] FIFO3_write["write"] + FIFO3_read["read"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_issue["issue"] ShiftFuncUnit_accept["accept"] + ShiftFuncUnit_issue["issue"] subgraph FIFO4["fifo FIFO"] - FIFO4_read["read"] FIFO4_write["write"] + FIFO4_read["read"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_issue["issue"] JumpBranchFuncUnit_accept["accept"] + JumpBranchFuncUnit_issue["issue"] subgraph FIFO5["fifo_branch_resolved FIFO"] - FIFO5_write["write"] FIFO5_read["read"] + FIFO5_write["write"] end subgraph TaggedCounter1["perf_instr TaggedCounter"] TaggedCounter1__incr["_incr"] @@ -345,20 +379,20 @@ WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] + ExceptionFuncUnit_issue["issue"] subgraph FIFO7["fifo FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] - PrivilegedFuncUnit_accept["accept"] - PrivilegedFuncUnit_precommit["precommit"] PrivilegedFuncUnit_issue["issue"] + PrivilegedFuncUnit_precommit["precommit"] + PrivilegedFuncUnit_accept["accept"] subgraph BasicFifo6["fetch_resume_fifo BasicFifo"] BasicFifo6_read["read"] BasicFifo6_write["write"] @@ -370,8 +404,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_write["write"] Forwarder5_read["read"] + Forwarder5_write["write"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans4["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -393,36 +427,36 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] + LSUDummy_insert["insert"] + LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_update["update"] + LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_select["select"] LSUDummy_precommit["precommit"] - LSUDummy_LSUDummy["LSUDummy"] LSUDummy_get_result["get_result"] - LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_insert["insert"] LSUDummy_LSUDummy2["LSUDummy"] - LSUDummy_update["update"] subgraph Forwarder6["forwarder Forwarder"] Forwarder6_read["read"] Forwarder6_write["write"] end subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond2["issue_cond2"] - LSURequester_accept_cond1["accept_cond1"] - LSURequester_issue_cond0["issue_cond0"] - LSURequester_issue["issue"] LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue["issue"] + LSURequester_accept_cond1["accept_cond1"] + LSURequester_issue_cond2["issue_cond2"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond0["issue_cond0"] LSURequester_accept["accept"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] + CSRUnit_insert["insert"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_select["select"] + CSRUnit_fetch_resume["fetch_resume"] CSRUnit_update["update"] - CSRUnit_CSRUnit["CSRUnit"] - CSRUnit_precommit["precommit"] CSRUnit_get_result["get_result"] - CSRUnit_insert["insert"] - CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_precommit["precommit"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] @@ -458,46 +492,46 @@ GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] - CSRRegister__fu_write["_fu_write"] - CSRRegister_write["write"] CSRRegister__fu_read["_fu_read"] + CSRRegister_write["write"] + CSRRegister__fu_write["_fu_write"] end subgraph CSRRegister1["mtvec CSRRegister"] + CSRRegister1__fu_write["_fu_write"] CSRRegister1__fu_read["_fu_read"] CSRRegister1_read["read"] - CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] + CSRRegister2_read["read"] + CSRRegister2__fu_write["_fu_write"] CSRRegister2_write["write"] CSRRegister2__fu_read["_fu_read"] - CSRRegister2__fu_write["_fu_write"] - CSRRegister2_read["read"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] + CSRRegister3__fu_read["_fu_read"] CSRRegister3_read["read"] CSRRegister3_write["write"] - CSRRegister3__fu_read["_fu_read"] end subgraph CSRRegister4["register_high CSRRegister"] CSRRegister4_read["read"] - CSRRegister4__fu_read["_fu_read"] CSRRegister4_write["write"] + CSRRegister4__fu_read["_fu_read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_write["write"] CSRRegister5__fu_read["_fu_read"] CSRRegister5_read["read"] + CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] CSRRegister6_write["write"] - CSRRegister6__fu_read["_fu_read"] CSRRegister6_read["read"] + CSRRegister6__fu_read["_fu_read"] end end end @@ -520,8 +554,8 @@ RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO10["rename_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] @@ -534,8 +568,8 @@ ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO12["rs_select_out_buf FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -555,24 +589,24 @@ ConnectTrans11_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_core_state["core_state"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement["Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement1["Retirement"] Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] Retirement_Retirement4["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] CSRRegister7_read["read"] - CSRRegister7__fu_read["_fu_read"] CSRRegister7_write["write"] + CSRRegister7__fu_read["_fu_read"] end subgraph CSRRegister8["register_high CSRRegister"] - CSRRegister8__fu_read["_fu_read"] CSRRegister8_write["write"] + CSRRegister8__fu_read["_fu_read"] CSRRegister8_read["read"] end end @@ -593,32 +627,34 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] + TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] + TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] + TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] - TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] - TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] - TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] - TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] end end Core_InitFreeRFFifo --> BasicFifo2_write -Retirement_Retirement2 --> BasicFifo2_write -TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write -TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write +Retirement_Retirement4 --> BasicFifo2_write +TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write +TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write FIFO5_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMasterAdapter_request_read -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Serializer_Serializer1 -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> BasicFifo_write -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMaster_request -WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Forwarder2_write +RegisterFile_perf --> HwExpHistogram2__add +ReorderBuffer_perf --> HwExpHistogram4__add +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request +WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +Serializer_Serializer1 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write ICache_ICache1 <--> HwCounter4__incr ArgumentsToResultsZipper_peek_arg --> ICache_MemRead BasicFifo3_peek --> ICache_MemRead @@ -630,28 +666,28 @@ SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache Forwarder2_read --> ICache_ICache ICache_ICache <--> HwCounter3__incr -Fetch_Fetch --> ICache_issue_req -Fetch_Fetch <--> HwCounter__incr -Fetch_Fetch <--> LatencyMeasurer__start -Fetch_Fetch --> FIFO1_write -Fetch_Fetch --> ArgumentsToResultsZipper_write_args -Fetch_Fetch --> BasicFifo3_write -Fetch_Fetch --> BasicFifo4_write -BasicFifo4_read --> Fetch_Fetch1 -ICache_accept_res --> Fetch_Fetch1 -Fetch_Fetch1 <--> LatencyMeasurer__stop -FIFO1_read --> Fetch_Fetch1 -Fetch_Fetch1 --> HwExpHistogram__add -ArgumentsToResultsZipper_read --> Fetch_Fetch1 -BasicFifo3_read --> Fetch_Fetch1 -Forwarder3_read --> Fetch_Fetch1 -Fetch_Fetch1 --> MethodProduct_method +Fetch_Fetch1 --> ICache_issue_req +Fetch_Fetch1 <--> HwCounter__incr +Fetch_Fetch1 <--> FIFOLatencyMeasurer__start +Fetch_Fetch1 --> FIFO1_write +Fetch_Fetch1 --> ArgumentsToResultsZipper_write_args +Fetch_Fetch1 --> BasicFifo3_write +Fetch_Fetch1 --> BasicFifo4_write +BasicFifo4_read --> Fetch_Fetch +ICache_accept_res --> Fetch_Fetch +Fetch_Fetch <--> FIFOLatencyMeasurer__stop +FIFO1_read --> Fetch_Fetch +Fetch_Fetch --> HwExpHistogram__add +ArgumentsToResultsZipper_read --> Fetch_Fetch +BasicFifo3_read --> Fetch_Fetch +Forwarder3_read --> Fetch_Fetch +Fetch_Fetch --> MethodProduct_method AdapterTrans_AdapterTrans_method --> MethodProduct_method -Fetch_Fetch1 --> FIFO_write +Fetch_Fetch --> FIFO_write AdapterTrans_AdapterTrans_method --> FIFO_write -Fetch_Fetch1 --> MethodMap_method +Fetch_Fetch --> MethodMap_method AdapterTrans_AdapterTrans_method --> MethodMap_method -Fetch_Fetch1 <--> CoreInstructionCounter_increment +Fetch_Fetch <--> CoreInstructionCounter_increment AdapterTrans_AdapterTrans_method <--> CoreInstructionCounter_increment FIFO_read --> DecodeStage_DecodeStage DecodeStage_DecodeStage <--> HwCounter6__incr @@ -661,32 +697,34 @@ RegAllocation_RegAllocation --> FIFO9_write FIFO9_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename -Retirement_Retirement2 --> FRAT_rename -TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename +Retirement_Retirement4 --> FRAT_rename +TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO10_write FIFO10_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put -ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start +ROBAllocation_ROBAllocation <--> FIFOLatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO2_write ROBAllocation_ROBAllocation --> FIFO11_write -FIFO11_read --> RSSelection_RSSelection -RSSelection_RSSelection --> Forwarder8_write -Forwarder8_read --> RSSelection_RSSelection3 -Forwarder8_read --> RSSelection_RSSelection2 +FIFO11_read --> RSSelection_RSSelection3 +RSSelection_RSSelection3 --> Forwarder8_write +Forwarder8_read --> RSSelection_RSSelection Forwarder8_read --> RSSelection_RSSelection1 -RSFuncBlock_select --> RSSelection_RSSelection3 -RS_select --> RSSelection_RSSelection3 -RSSelection_RSSelection3 --> FIFO12_write -RSSelection_RSSelection2 --> FIFO12_write +Forwarder8_read --> RSSelection_RSSelection2 +RSFuncBlock_select --> RSSelection_RSSelection +RS_select --> RSSelection_RSSelection +RSSelection_RSSelection --> FIFO12_write RSSelection_RSSelection1 --> FIFO12_write -RSSelection_RSSelection2 <--> LSUDummy_select -RSSelection_RSSelection1 <--> CSRUnit_select +RSSelection_RSSelection2 --> FIFO12_write +RSSelection_RSSelection1 <--> LSUDummy_select +RSSelection_RSSelection2 <--> CSRUnit_select FIFO12_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion Retirement_core_state --> RSInsertion_RSInsertion RSInsertion_RSInsertion --> RSFuncBlock_insert RSInsertion_RSInsertion --> RS_insert +RSInsertion_RSInsertion --> TaggedLatencyMeasurer1__start +RSInsertion_RSInsertion --> AsyncMemoryBank1_write RSInsertion_RSInsertion --> LSUDummy_insert RSInsertion_RSInsertion --> CSRUnit_insert BasicFifo5_read --> ConnectTrans_ConnectTrans @@ -696,22 +734,40 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume -Retirement_Retirement1 --> Fetch_resume +Retirement_Retirement --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done ResultAnnouncement_ResultAnnouncement --> RegisterFile_write +ResultAnnouncement_ResultAnnouncement --> TaggedLatencyMeasurer__start +ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_write ResultAnnouncement_ResultAnnouncement --> MethodProduct1_method ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update -RS_RS --> WakeupSelect_WakeupSelect +RS_perf --> HwExpHistogram6__add +RS_RS2 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect RS_take --> WakeupSelect3_WakeupSelect RS_take --> WakeupSelect4_WakeupSelect +WakeupSelect_WakeupSelect --> TaggedLatencyMeasurer1__stop +WakeupSelect1_WakeupSelect --> TaggedLatencyMeasurer1__stop +WakeupSelect2_WakeupSelect --> TaggedLatencyMeasurer1__stop +WakeupSelect3_WakeupSelect --> TaggedLatencyMeasurer1__stop +WakeupSelect4_WakeupSelect --> TaggedLatencyMeasurer1__stop +AsyncMemoryBank1_read --> WakeupSelect_WakeupSelect +AsyncMemoryBank1_read --> WakeupSelect1_WakeupSelect +AsyncMemoryBank1_read --> WakeupSelect2_WakeupSelect +AsyncMemoryBank1_read --> WakeupSelect3_WakeupSelect +AsyncMemoryBank1_read --> WakeupSelect4_WakeupSelect +WakeupSelect_WakeupSelect --> HwExpHistogram5__add +WakeupSelect1_WakeupSelect --> HwExpHistogram5__add +WakeupSelect2_WakeupSelect --> HwExpHistogram5__add +WakeupSelect3_WakeupSelect --> HwExpHistogram5__add +WakeupSelect4_WakeupSelect --> HwExpHistogram5__add WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter__incr WakeupSelect_WakeupSelect --> FIFO3_write @@ -729,7 +785,7 @@ ConnectTrans3_ConnectTrans --> BasicFifo5_write WakeupSelect2_WakeupSelect --> FIFO6_write WakeupSelect2_WakeupSelect --> FIFO5_write -RS_RS2 --> WakeupSelect3_WakeupSelect +RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO7_write RS_RS1 --> WakeupSelect4_WakeupSelect @@ -750,12 +806,12 @@ PrivilegedFuncUnit_accept --> ConnectTrans8_ConnectTrans CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo6_write -LSUDummy_LSUDummy2 --> Forwarder6_write +LSUDummy_LSUDummy --> Forwarder6_write TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write -TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write -TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write -TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write +TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write +TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write +TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -777,45 +833,54 @@ LSUDummy_get_result --> ConnectTrans2_ConnectTrans Forwarder6_read --> ConnectTrans2_ConnectTrans CSRUnit_get_result --> ConnectTrans3_ConnectTrans -MethodTryProduct_MethodTryProduct1 --> PrivilegedFuncUnit_precommit -MethodTryProduct_MethodTryProduct1 <--> InterruptController_mret +MethodTryProduct_MethodTryProduct2 --> PrivilegedFuncUnit_precommit +MethodTryProduct_MethodTryProduct2 <--> InterruptController_mret MethodTryProduct_MethodTryProduct --> LSUDummy_precommit -MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit +MethodTryProduct_MethodTryProduct1 --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo6_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans -ReorderBuffer_peek --> Retirement_Retirement -ReorderBuffer_peek --> Retirement_Retirement3 +ReorderBuffer_peek --> Retirement_Retirement1 ReorderBuffer_peek --> Retirement_Retirement2 -ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 -ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement --> MethodTryProduct_method -ExceptionCauseRegister_get --> Retirement_Retirement3 -ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement2 <--> ReorderBuffer_retire -TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire -TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire -Retirement_Retirement2 <--> LatencyMeasurer1__stop -TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop -TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop -FIFO2_read --> Retirement_Retirement2 -FIFO2_read --> TransactionManager_Retirement_Retirement_cond1 -FIFO2_read --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement2 --> HwExpHistogram1__add -TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add -CoreInstructionCounter_decrement --> Retirement_Retirement2 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement -RRAT_peek --> Retirement_Retirement2 -RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement2 --> RegisterFile_free -TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free -TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free -CSRRegister1_read --> Retirement_Retirement1 -Retirement_Retirement1 <--> ExceptionCauseRegister_clear +ReorderBuffer_peek --> Retirement_Retirement4 +ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement1 --> MethodTryProduct_method +ExceptionCauseRegister_get --> Retirement_Retirement2 +ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement +ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement4 <--> ReorderBuffer_retire +TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire +TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire +Retirement_Retirement4 <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop +FIFO2_read --> Retirement_Retirement4 +FIFO2_read --> TransactionManager_Retirement_cond1_Retirement +FIFO2_read --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement4 --> HwExpHistogram3__add +TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram3__add +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add +CoreInstructionCounter_decrement --> Retirement_Retirement4 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 +RRAT_peek --> Retirement_Retirement4 +RRAT_peek --> TransactionManager_Retirement_cond1_Retirement +Retirement_Retirement4 --> RegisterFile_free +TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free +TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free +Retirement_Retirement4 --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_cond1_Retirement --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop +AsyncMemoryBank_read --> Retirement_Retirement4 +AsyncMemoryBank_read --> TransactionManager_Retirement_cond1_Retirement +AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement4 --> HwExpHistogram1__add +TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add +CSRRegister1_read --> Retirement_Retirement +Retirement_Retirement <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -828,55 +893,55 @@ GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 -TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 -TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 -TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy2 +TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy2 +TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy2 TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue -TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue -TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy -TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy -LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 -LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy -TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 -Serializer1_Serializer1 --> TransactionManager_LSUDummy_accept_cond0 -BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 +TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 +TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write +TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer +TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write +TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write +TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request +TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request +TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy +Serializer1_Serializer1 --> TransactionManager_accept_cond0_LSUDummy +BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy -WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 +WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy -Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 +Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement4 -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement4 -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write -TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry -TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 -TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy -Serializer1_Serializer --> TransactionManager_accept_cond1_LSUDummy -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_cond0_Retirement --> RRAT_commit -TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment -CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write -CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write -TransactionManager_Retirement_cond0_Retirement <--> HwCounter7__incr +TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy1 +LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy +LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3 -TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write -TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write -TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request -TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request -TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 -TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write -TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer2 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3 +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement3 +TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write +TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write +TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit +TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment +CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write +CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond0 <--> HwCounter7__incr +TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy +Serializer1_Serializer2 --> TransactionManager_accept_cond1_LSUDummy @@ -887,7 +952,7 @@

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/components/icache.html b/components/icache.html index e96773535..c6a54353a 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

    Address mapping example

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.backend.html b/coreblocks.backend.html index 6b16ac5e1..b687a5ff0 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -165,7 +165,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.cache.html b/coreblocks.cache.html index 8f4c36569..b6b2ebbf2 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -241,7 +241,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index 0add71774..103adfc17 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -157,7 +157,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index 9e1e61bc2..075541877 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -1726,7 +1726,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index a39f1a4eb..41f0a6d81 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -161,7 +161,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 58eb738bd..4dfaf214e 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -125,7 +125,7 @@

    Subpackages

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index 37e6a4fc3..628d98a62 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -867,7 +867,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index e31dfa4db..f8000c85e 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -238,7 +238,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index 06e9fb6ee..5bd3fe0db 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -148,7 +148,7 @@

    Subpackages

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index 6e0b86fdf..b756d465d 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -169,7 +169,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.func_blocks.lsu.html b/coreblocks.func_blocks.lsu.html index 170136aa4..cb7f92ee0 100644 --- a/coreblocks.func_blocks.lsu.html +++ b/coreblocks.func_blocks.lsu.html @@ -94,6 +94,11 @@

    Submodules class coreblocks.func_blocks.lsu.dummyLsu.LSUBlockComponent

    Bases: BlockComponentParams

    +
    +
    +__init__() → None
    +
    +
    get_module(gen_params: GenParams) → FuncBlock
    @@ -248,7 +253,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.html b/coreblocks.html index 22b554c91..da6fe331d 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -255,7 +255,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.params.html b/coreblocks.params.html index 57e94ff20..8b7279954 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -135,7 +135,7 @@

    Submodules
    -__init__(*, xlen: int = 32, func_units_config: ~collections.abc.Collection[~coreblocks.params.fu_params.BlockComponentParams] = (RSBlockComponent(func_units=[<coreblocks.func_blocks.fu.alu.ALUComponent object>, <coreblocks.func_blocks.fu.shift_unit.ShiftUnitComponent object>, <coreblocks.func_blocks.fu.jumpbranch.JumpComponent object>, <coreblocks.func_blocks.fu.exception.ExceptionUnitComponent object>, <coreblocks.func_blocks.fu.priv.PrivilegedUnitComponent object>], rs_entries=4), <coreblocks.func_blocks.lsu.dummyLsu.LSUBlockComponent object>, <coreblocks.func_blocks.csr.csr.CSRBlockComponent object>), compressed: bool = False, embedded: bool = False, debug_signals: bool = True, phys_regs_bits: int = 6, rob_entries_bits: int = 7, start_pc: int = 0, icache_enable: bool = True, icache_ways: int = 2, icache_sets_bits: int = 7, icache_line_bytes_log: int = 5, fetch_block_bytes_log: int = 2, allow_partial_extensions: bool = False, _implied_extensions: ~coreblocks.params.isa_params.Extension = Extension.None, pma: list[coreblocks.func_blocks.lsu.pma.PMARegion] = <factory>) → None
    +__init__(*, xlen: int = 32, func_units_config: ~collections.abc.Collection[~coreblocks.params.fu_params.BlockComponentParams] = (RSBlockComponent(func_units=[<coreblocks.func_blocks.fu.alu.ALUComponent object>, <coreblocks.func_blocks.fu.shift_unit.ShiftUnitComponent object>, <coreblocks.func_blocks.fu.jumpbranch.JumpComponent object>, <coreblocks.func_blocks.fu.exception.ExceptionUnitComponent object>, <coreblocks.func_blocks.fu.priv.PrivilegedUnitComponent object>], rs_entries=4, rs_number=-1), LSUBlockComponent(), CSRBlockComponent()), compressed: bool = False, embedded: bool = False, debug_signals: bool = True, phys_regs_bits: int = 6, rob_entries_bits: int = 7, start_pc: int = 0, icache_enable: bool = True, icache_ways: int = 2, icache_sets_bits: int = 7, icache_line_bytes_log: int = 5, fetch_block_bytes_log: int = 2, allow_partial_extensions: bool = False, _implied_extensions: ~coreblocks.params.isa_params.Extension = Extension.None, pma: list[coreblocks.func_blocks.lsu.pma.PMARegion] = <factory>) → None

    @@ -165,7 +165,7 @@

    Submodules
    -func_units_config: Collection[BlockComponentParams] = (RSBlockComponent(func_units=[<coreblocks.func_blocks.fu.alu.ALUComponent object>, <coreblocks.func_blocks.fu.shift_unit.ShiftUnitComponent object>, <coreblocks.func_blocks.fu.jumpbranch.JumpComponent object>, <coreblocks.func_blocks.fu.exception.ExceptionUnitComponent object>, <coreblocks.func_blocks.fu.priv.PrivilegedUnitComponent object>], rs_entries=4), <coreblocks.func_blocks.lsu.dummyLsu.LSUBlockComponent object>, <coreblocks.func_blocks.csr.csr.CSRBlockComponent object>)
    +func_units_config: Collection[BlockComponentParams] = (RSBlockComponent(func_units=[<coreblocks.func_blocks.fu.alu.ALUComponent object>, <coreblocks.func_blocks.fu.shift_unit.ShiftUnitComponent object>, <coreblocks.func_blocks.fu.jumpbranch.JumpComponent object>, <coreblocks.func_blocks.fu.exception.ExceptionUnitComponent object>, <coreblocks.func_blocks.fu.priv.PrivilegedUnitComponent object>], rs_entries=4, rs_number=-1), LSUBlockComponent(), CSRBlockComponent())

    @@ -227,6 +227,11 @@

    Submodules class coreblocks.params.fu_params.BlockComponentParams

    Bases: ABC

    +
    +
    +__init__() → None
    +
    +
    abstract get_module(gen_params: GenParams) → FuncBlock
    @@ -1166,7 +1171,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index 7788073ca..c57a350f2 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -746,7 +746,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html index 357d0ad47..76bb70ac1 100644 --- a/coreblocks.priv.csr.html +++ b/coreblocks.priv.csr.html @@ -327,7 +327,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.priv.html b/coreblocks.priv.html index 68487b7c8..f60d39fb4 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -123,7 +123,7 @@

    Subpackages

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index d3cce6f96..e2915e761 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -171,7 +171,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index d886f47c2..b12a31b2c 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/current-graph.html b/current-graph.html index ebc7b7044..a6d72482c 100644 --- a/current-graph.html +++ b/current-graph.html @@ -89,12 +89,12 @@

    Full transaction-method graph

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/development-environment.html b/development-environment.html index c81561767..decc9a959 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

    tprof.py

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:39 2024-04-01. + Last updated on 14:50 2024-04-01.

    diff --git a/genindex.html b/genindex.html index c12ee6cb6..2e2647e54 100644 --- a/genindex.html +++ b/genindex.html @@ -193,6 +193,8 @@

    _

  1. (coreblocks.func_blocks.fu.zbs.ZbsUnit method)
  2. (coreblocks.func_blocks.interface.func_blocks_unifier.FuncBlocksUnifier method) +
    3. +
  3. (coreblocks.func_blocks.lsu.dummyLsu.LSUBlockComponent method)
  4. (coreblocks.func_blocks.lsu.dummyLsu.LSUDummy method)
    5. @@ -203,6 +205,8 @@

    _

  5. (coreblocks.func_blocks.lsu.pma.PMARegion method)
  6. (coreblocks.params.configurations.CoreConfiguration method) +
    7. +
  7. (coreblocks.params.fu_params.BlockComponentParams method)
  8. (coreblocks.params.genparams.GenParams method)
    9. @@ -327,6 +331,8 @@

    _

  9. (transactron.lib.logging.LogRecord method)
  10. (transactron.lib.logging.LogRecordInfo method) +
    11. +
  11. (transactron.lib.metrics.FIFOLatencyMeasurer method)
  12. (transactron.lib.metrics.HardwareMetricsManager method)
    13. @@ -337,18 +343,20 @@

    _

  13. (transactron.lib.metrics.HwMetric method)
  14. (transactron.lib.metrics.HwMetricsEnabledKey method) -
    15. -
  15. (transactron.lib.metrics.LatencyMeasurer method)
  16. (transactron.lib.metrics.MetricModel method)
  17. (transactron.lib.metrics.MetricRegisterModel method)
  18. (transactron.lib.metrics.TaggedCounter method) +
    19. +
  19. (transactron.lib.metrics.TaggedLatencyMeasurer method)
  20. (transactron.lib.reqres.ArgumentsToResultsZipper method)
  21. (transactron.lib.reqres.Serializer method) +
    22. +
  22. (transactron.lib.storage.AsyncMemoryBank method)
  23. (transactron.lib.storage.MemoryBank method)
    24. @@ -525,10 +533,10 @@

    A

  24. ADDRESS_GENERATION (coreblocks.frontend.decoder.optypes.OpType attribute)
    25. - - +