From db05a4bde1a737cc23f260dc2ca8087acdc78e30 Mon Sep 17 00:00:00 2001 From: tilk Date: Mon, 23 Oct 2023 18:20:28 +0000 Subject: [PATCH] Autumn cleaning: types (#479) --- .doctrees/Current_graph.doctree | Bin 24027 -> 24025 bytes .doctrees/api.doctree | Bin 31312 -> 31312 bytes .doctrees/auto_graph.doctree | Bin 23260 -> 23258 bytes .doctrees/coreblocks.fu.doctree | Bin 244523 -> 244584 bytes .doctrees/coreblocks.scheduler.doctree | Bin 42146 -> 42169 bytes .doctrees/coreblocks.stages.doctree | Bin 75024 -> 75075 bytes .doctrees/coreblocks.structs_common.doctree | Bin 129980 -> 130028 bytes .doctrees/coreblocks.utils.doctree | Bin 171032 -> 166086 bytes .doctrees/environment.pickle | Bin 312069 -> 312944 bytes .doctrees/transactron.doctree | Bin 542082 -> 516826 bytes .doctrees/transactron.lib.doctree | Bin 434470 -> 358853 bytes Assumptions.html | 2 +- Current_graph.html | 120 ++++++++++---------- Development_environment.html | 2 +- Home.html | 2 +- Problem-checklist.html | 2 +- Transactions.html | 2 +- _sources/auto_graph.rst.txt | 118 +++++++++---------- api.html | 2 +- auto_graph.html | 120 ++++++++++---------- components/icache.html | 2 +- coreblocks.frontend.html | 2 +- coreblocks.fu.html | 4 +- coreblocks.fu.unsigned_multiplication.html | 2 +- coreblocks.html | 2 +- coreblocks.params.html | 2 +- coreblocks.peripherals.html | 2 +- coreblocks.scheduler.html | 2 +- coreblocks.stages.html | 2 +- coreblocks.structs_common.html | 2 +- coreblocks.utils.html | 10 +- genindex.html | 2 +- index.html | 2 +- miscellany/exceptionsSummary.html | 2 +- modules-coreblocks.html | 2 +- modules-transactron.html | 2 +- py-modindex.html | 2 +- scheduler/Overview.html | 2 +- search.html | 2 +- searchindex.js | 2 +- shared_structs/Implementation/RS_impl.html | 2 +- shared_structs/RS.html | 2 +- synthesis/Synthesis.html | 2 +- transactron.html | 18 +-- transactron.lib.html | 26 ++--- 45 files changed, 235 insertions(+), 235 deletions(-) diff --git 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List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/Current_graph.html b/Current_graph.html index 1aa01fb55..6cef0203b 100644 --- a/Current_graph.html +++ b/Current_graph.html @@ -89,8 +89,8 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/Development_environment.html b/Development_environment.html index 1ef47ed75..d7c699716 100644 --- a/Development_environment.html +++ b/Development_environment.html @@ -178,7 +178,7 @@

build_docs.sh

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/Home.html b/Home.html index ba0476552..be47ecf8b 100644 --- a/Home.html +++ b/Home.html @@ -129,7 +129,7 @@

Documentation

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/Problem-checklist.html b/Problem-checklist.html index 56b0511a7..57539c3af 100644 --- a/Problem-checklist.html +++ b/Problem-checklist.html @@ -105,7 +105,7 @@

Problem checklist

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/Transactions.html b/Transactions.html index abe6222cf..8be34374d 100644 --- a/Transactions.html +++ b/Transactions.html @@ -267,7 +267,7 @@

Transaction and method nesting

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 0080bb978..552d900d9 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -6,8 +6,8 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_request["request"] WishboneMaster_result["result"] + WishboneMaster_request["request"] end subgraph WishboneMaster1["wb_master_data WishboneMaster"] WishboneMaster1_result["result"] @@ -18,27 +18,27 @@ FIFO_read["read"] end subgraph BasicFifo["free_rf_fifo BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"] - SimpleWBCacheRefiller_start_refill["start_refill"] - SimpleWBCacheRefiller_accept_refill["accept_refill"] SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] + SimpleWBCacheRefiller_accept_refill["accept_refill"] + SimpleWBCacheRefiller_start_refill["start_refill"] end subgraph ICache["icache ICache"] + ICache_issue_req["issue_req"] ICache_ICache["ICache"] ICache_ICache1["ICache"] - ICache_accept_res["accept_res"] ICache_ICache2["ICache"] - ICache_issue_req["issue_req"] + ICache_accept_res["accept_res"] subgraph FIFO1["req_fifo FIFO"] - FIFO1_read["read"] FIFO1_write["write"] + FIFO1_read["read"] end subgraph Forwarder["res_fwd Forwarder"] - Forwarder_write["write"] Forwarder_read["read"] + Forwarder_write["write"] end end subgraph Fetch["fetch Fetch"] @@ -46,8 +46,8 @@ Fetch_verify_branch["verify_branch"] Fetch_Fetch1["Fetch"] subgraph BasicFifo1["fetch_target_queue BasicFifo"] - BasicFifo1_read["read"] BasicFifo1_write["write"] + BasicFifo1_read["read"] end end subgraph FRAT["FRAT FRAT"] @@ -57,28 +57,28 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read2["read2"] - RegisterFile_write["write"] RegisterFile_read1["read1"] + RegisterFile_write["write"] RegisterFile_free["free"] + RegisterFile_read2["read2"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_peek["peek"] + ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_retire["retire"] + ReorderBuffer_peek["peek"] ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_put["put"] + ReorderBuffer_retire["retire"] end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_report["report"] end subgraph FuncBlocksUnifier["func_blocks_unifier FuncBlocksUnifier"] subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder1["forwarder Forwarder"] - Forwarder1_write["write"] Forwarder1_read["read"] + Forwarder1_write["write"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -93,26 +93,26 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_select["select"] - RSFuncBlock_update["update"] RSFuncBlock_insert["insert"] + RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] + RSFuncBlock_select["select"] subgraph RS["rs RS"] RS_RS["RS"] - RS_take["take"] - RS_insert["insert"] - RS_select["select"] + RS_update["update"] RS_RS1["RS"] + RS_insert["insert"] + RS_take["take"] RS_RS2["RS"] + RS_select["select"] RS_RS3["RS"] - RS_update["update"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph FIFO2["fifo FIFO"] - FIFO2_write["write"] FIFO2_read["read"] + FIFO2_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] @@ -122,8 +122,8 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] @@ -138,19 +138,19 @@ FIFO4_write["write"] end subgraph FIFO5["fifo_branch FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] + ExceptionFuncUnit_issue["issue"] subgraph FIFO6["fifo FIFO"] - FIFO6_write["write"] FIFO6_read["read"] + FIFO6_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -159,8 +159,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder2["forwarder Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans2["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -179,11 +179,11 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_insert["insert"] LSUDummy_get_result["get_result"] LSUDummy_select["select"] LSUDummy_precommit["precommit"] LSUDummy_update["update"] + LSUDummy_insert["insert"] subgraph LSUDummyInternals["internal LSUDummyInternals"] LSUDummyInternals_LSUDummyInternals["LSUDummyInternals"] LSUDummyInternals_LSUDummyInternals1["LSUDummyInternals"] @@ -214,8 +214,8 @@ CSRRegister2_write["write"] end subgraph CSRRegister3["register_high CSRRegister"] - CSRRegister3_read["read"] CSRRegister3_write["write"] + CSRRegister3_read["read"] end end subgraph CSRRegister4["mcause CSRRegister"] @@ -231,8 +231,8 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO8["alloc_rename_buf FIFO"] - FIFO8_write["write"] FIFO8_read["read"] + FIFO8_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -277,12 +277,12 @@ subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_write["write"] CSRRegister5_read["read"] + CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_write["write"] CSRRegister6_read["read"] + CSRRegister6_write["write"] end end end @@ -303,17 +303,17 @@ Retirement_Retirement1 --> BasicFifo_write SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request ICache_ICache2 --> Forwarder_write - ICache_ICache --> SimpleWBCacheRefiller_start_refill - SimpleWBCacheRefiller_accept_refill --> ICache_ICache1 - WishboneMaster_result --> ICache_ICache1 - Fetch_Fetch --> ICache_issue_req - Fetch_Fetch --> FIFO1_write - Fetch_Fetch --> BasicFifo1_write - BasicFifo1_read --> Fetch_Fetch1 - ICache_accept_res --> Fetch_Fetch1 - FIFO1_read --> Fetch_Fetch1 - Forwarder_read --> Fetch_Fetch1 - Fetch_Fetch1 --> FIFO_write + ICache_ICache1 --> SimpleWBCacheRefiller_start_refill + SimpleWBCacheRefiller_accept_refill --> ICache_ICache + WishboneMaster_result --> ICache_ICache + Fetch_Fetch1 --> ICache_issue_req + Fetch_Fetch1 --> FIFO1_write + Fetch_Fetch1 --> BasicFifo1_write + BasicFifo1_read --> Fetch_Fetch + ICache_accept_res --> Fetch_Fetch + FIFO1_read --> Fetch_Fetch + Forwarder_read --> Fetch_Fetch + Fetch_Fetch --> FIFO_write AdapterTrans_AdapterTrans_write --> FIFO_write FIFO_read --> Decode_Decode Decode_Decode --> FIFO7_write @@ -326,13 +326,13 @@ FIFO9_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation --> FIFO10_write - FIFO10_read --> RSSelection_RSSelection1 - RSSelection_RSSelection1 --> Forwarder3_write - Forwarder3_read --> RSSelection_RSSelection + FIFO10_read --> RSSelection_RSSelection + RSSelection_RSSelection --> Forwarder3_write + Forwarder3_read --> RSSelection_RSSelection1 Forwarder3_read --> RSSelection_RSSelection2 - RSFuncBlock_select --> RSSelection_RSSelection - RS_select --> RSSelection_RSSelection - RSSelection_RSSelection --> FIFO11_write + RSFuncBlock_select --> RSSelection_RSSelection1 + RS_select --> RSSelection_RSSelection1 + RSSelection_RSSelection1 --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write RSSelection_RSSelection2 <--> LSUDummy_select FIFO11_read --> RSInsertion_RSInsertion @@ -353,29 +353,29 @@ ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update - RS_RS --> WakeupSelect_WakeupSelect + RS_RS1 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect RS_take --> WakeupSelect3_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO2_write - RS_RS3 --> WakeupSelect1_WakeupSelect + RS_RS --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write - RS_RS2 --> WakeupSelect2_WakeupSelect + RS_RS3 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> ExceptionCauseRegister_report WakeupSelect3_WakeupSelect --> ExceptionCauseRegister_report + LSUDummyInternals_LSUDummyInternals --> ExceptionCauseRegister_report LSUDummyInternals_LSUDummyInternals1 --> ExceptionCauseRegister_report - LSUDummyInternals_LSUDummyInternals2 --> ExceptionCauseRegister_report ReorderBuffer_get_indices --> WakeupSelect2_WakeupSelect ReorderBuffer_get_indices --> WakeupSelect3_WakeupSelect + ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals1 - ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals2 WakeupSelect2_WakeupSelect --> FIFO4_write WakeupSelect2_WakeupSelect --> FIFO5_write - RS_RS1 --> WakeupSelect3_WakeupSelect + RS_RS2 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO6_write ConnectTrans2_ConnectTrans --> Forwarder2_write @@ -390,8 +390,8 @@ FIFO4_read --> ConnectTrans4_ConnectTrans ExceptionFuncUnit_accept --> ConnectTrans5_ConnectTrans FIFO6_read --> ConnectTrans5_ConnectTrans - LSUDummyInternals_LSUDummyInternals --> WishboneMaster1_request - WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals2 + LSUDummyInternals_LSUDummyInternals2 --> WishboneMaster1_request + WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals1 ConnectTrans_ConnectTrans --> Forwarder1_write ConnectTrans1_ConnectTrans --> Forwarder1_write RSFuncBlock_get_result --> ConnectTrans_ConnectTrans diff --git a/api.html b/api.html index bcbe84ad8..167683a03 100644 --- a/api.html +++ b/api.html @@ -235,7 +235,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/auto_graph.html b/auto_graph.html index aba249506..5df546717 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -85,8 +85,8 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_request["request"] WishboneMaster_result["result"] + WishboneMaster_request["request"] end subgraph WishboneMaster1["wb_master_data WishboneMaster"] WishboneMaster1_result["result"] @@ -97,27 +97,27 @@ FIFO_read["read"] end subgraph BasicFifo["free_rf_fifo BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"] - SimpleWBCacheRefiller_start_refill["start_refill"] - SimpleWBCacheRefiller_accept_refill["accept_refill"] SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] + SimpleWBCacheRefiller_accept_refill["accept_refill"] + SimpleWBCacheRefiller_start_refill["start_refill"] end subgraph ICache["icache ICache"] + ICache_issue_req["issue_req"] ICache_ICache["ICache"] ICache_ICache1["ICache"] - ICache_accept_res["accept_res"] ICache_ICache2["ICache"] - ICache_issue_req["issue_req"] + ICache_accept_res["accept_res"] subgraph FIFO1["req_fifo FIFO"] - FIFO1_read["read"] FIFO1_write["write"] + FIFO1_read["read"] end subgraph Forwarder["res_fwd Forwarder"] - Forwarder_write["write"] Forwarder_read["read"] + Forwarder_write["write"] end end subgraph Fetch["fetch Fetch"] @@ -125,8 +125,8 @@ Fetch_verify_branch["verify_branch"] Fetch_Fetch1["Fetch"] subgraph BasicFifo1["fetch_target_queue BasicFifo"] - BasicFifo1_read["read"] BasicFifo1_write["write"] + BasicFifo1_read["read"] end end subgraph FRAT["FRAT FRAT"] @@ -136,28 +136,28 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read2["read2"] - RegisterFile_write["write"] RegisterFile_read1["read1"] + RegisterFile_write["write"] RegisterFile_free["free"] + RegisterFile_read2["read2"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_peek["peek"] + ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_retire["retire"] + ReorderBuffer_peek["peek"] ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_put["put"] + ReorderBuffer_retire["retire"] end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_report["report"] end subgraph FuncBlocksUnifier["func_blocks_unifier FuncBlocksUnifier"] subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder1["forwarder Forwarder"] - Forwarder1_write["write"] Forwarder1_read["read"] + Forwarder1_write["write"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -172,26 +172,26 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_select["select"] - RSFuncBlock_update["update"] RSFuncBlock_insert["insert"] + RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] + RSFuncBlock_select["select"] subgraph RS["rs RS"] RS_RS["RS"] - RS_take["take"] - RS_insert["insert"] - RS_select["select"] + RS_update["update"] RS_RS1["RS"] + RS_insert["insert"] + RS_take["take"] RS_RS2["RS"] + RS_select["select"] RS_RS3["RS"] - RS_update["update"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph FIFO2["fifo FIFO"] - FIFO2_write["write"] FIFO2_read["read"] + FIFO2_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] @@ -201,8 +201,8 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] @@ -217,19 +217,19 @@ FIFO4_write["write"] end subgraph FIFO5["fifo_branch FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] + ExceptionFuncUnit_issue["issue"] subgraph FIFO6["fifo FIFO"] - FIFO6_write["write"] FIFO6_read["read"] + FIFO6_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -238,8 +238,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder2["forwarder Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans2["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -258,11 +258,11 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_insert["insert"] LSUDummy_get_result["get_result"] LSUDummy_select["select"] LSUDummy_precommit["precommit"] LSUDummy_update["update"] + LSUDummy_insert["insert"] subgraph LSUDummyInternals["internal LSUDummyInternals"] LSUDummyInternals_LSUDummyInternals["LSUDummyInternals"] LSUDummyInternals_LSUDummyInternals1["LSUDummyInternals"] @@ -293,8 +293,8 @@ CSRRegister2_write["write"] end subgraph CSRRegister3["register_high CSRRegister"] - CSRRegister3_read["read"] CSRRegister3_write["write"] + CSRRegister3_read["read"] end end subgraph CSRRegister4["mcause CSRRegister"] @@ -310,8 +310,8 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO8["alloc_rename_buf FIFO"] - FIFO8_write["write"] FIFO8_read["read"] + FIFO8_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -356,12 +356,12 @@ subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_write["write"] CSRRegister5_read["read"] + CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_write["write"] CSRRegister6_read["read"] + CSRRegister6_write["write"] end end end @@ -382,17 +382,17 @@ Retirement_Retirement1 --> BasicFifo_write SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request ICache_ICache2 --> Forwarder_write -ICache_ICache --> SimpleWBCacheRefiller_start_refill -SimpleWBCacheRefiller_accept_refill --> ICache_ICache1 -WishboneMaster_result --> ICache_ICache1 -Fetch_Fetch --> ICache_issue_req -Fetch_Fetch --> FIFO1_write -Fetch_Fetch --> BasicFifo1_write -BasicFifo1_read --> Fetch_Fetch1 -ICache_accept_res --> Fetch_Fetch1 -FIFO1_read --> Fetch_Fetch1 -Forwarder_read --> Fetch_Fetch1 -Fetch_Fetch1 --> FIFO_write +ICache_ICache1 --> SimpleWBCacheRefiller_start_refill +SimpleWBCacheRefiller_accept_refill --> ICache_ICache +WishboneMaster_result --> ICache_ICache +Fetch_Fetch1 --> ICache_issue_req +Fetch_Fetch1 --> FIFO1_write +Fetch_Fetch1 --> BasicFifo1_write +BasicFifo1_read --> Fetch_Fetch +ICache_accept_res --> Fetch_Fetch +FIFO1_read --> Fetch_Fetch +Forwarder_read --> Fetch_Fetch +Fetch_Fetch --> FIFO_write AdapterTrans_AdapterTrans_write --> FIFO_write FIFO_read --> Decode_Decode Decode_Decode --> FIFO7_write @@ -405,13 +405,13 @@ FIFO9_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation --> FIFO10_write -FIFO10_read --> RSSelection_RSSelection1 -RSSelection_RSSelection1 --> Forwarder3_write -Forwarder3_read --> RSSelection_RSSelection +FIFO10_read --> RSSelection_RSSelection +RSSelection_RSSelection --> Forwarder3_write +Forwarder3_read --> RSSelection_RSSelection1 Forwarder3_read --> RSSelection_RSSelection2 -RSFuncBlock_select --> RSSelection_RSSelection -RS_select --> RSSelection_RSSelection -RSSelection_RSSelection --> FIFO11_write +RSFuncBlock_select --> RSSelection_RSSelection1 +RS_select --> RSSelection_RSSelection1 +RSSelection_RSSelection1 --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write RSSelection_RSSelection2 <--> LSUDummy_select FIFO11_read --> RSInsertion_RSInsertion @@ -432,29 +432,29 @@ ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update -RS_RS --> WakeupSelect_WakeupSelect +RS_RS1 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect RS_take --> WakeupSelect3_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO2_write -RS_RS3 --> WakeupSelect1_WakeupSelect +RS_RS --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write -RS_RS2 --> WakeupSelect2_WakeupSelect +RS_RS3 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> ExceptionCauseRegister_report WakeupSelect3_WakeupSelect --> ExceptionCauseRegister_report +LSUDummyInternals_LSUDummyInternals --> ExceptionCauseRegister_report LSUDummyInternals_LSUDummyInternals1 --> ExceptionCauseRegister_report -LSUDummyInternals_LSUDummyInternals2 --> ExceptionCauseRegister_report ReorderBuffer_get_indices --> WakeupSelect2_WakeupSelect ReorderBuffer_get_indices --> WakeupSelect3_WakeupSelect +ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals1 -ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals2 WakeupSelect2_WakeupSelect --> FIFO4_write WakeupSelect2_WakeupSelect --> FIFO5_write -RS_RS1 --> WakeupSelect3_WakeupSelect +RS_RS2 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO6_write ConnectTrans2_ConnectTrans --> Forwarder2_write @@ -469,8 +469,8 @@ FIFO4_read --> ConnectTrans4_ConnectTrans ExceptionFuncUnit_accept --> ConnectTrans5_ConnectTrans FIFO6_read --> ConnectTrans5_ConnectTrans -LSUDummyInternals_LSUDummyInternals --> WishboneMaster1_request -WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals2 +LSUDummyInternals_LSUDummyInternals2 --> WishboneMaster1_request +WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals1 ConnectTrans_ConnectTrans --> Forwarder1_write ConnectTrans1_ConnectTrans --> Forwarder1_write RSFuncBlock_get_result --> ConnectTrans_ConnectTrans @@ -509,7 +509,7 @@

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/components/icache.html b/components/icache.html index 740d44e5b..109da84b9 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index d87bd4c23..e2b4f5495 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -399,7 +399,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/coreblocks.fu.html b/coreblocks.fu.html index 8bde7b9ea..304136841 100644 --- a/coreblocks.fu.html +++ b/coreblocks.fu.html @@ -226,7 +226,7 @@

Submodules
-coreblocks.fu.div_unit.get_input(arg: Record) → Tuple[Value, Value]
+coreblocks.fu.div_unit.get_input(arg: Record) → tuple[amaranth.hdl.ast.Value, amaranth.hdl.ast.Value]
@@ -817,7 +817,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/coreblocks.fu.unsigned_multiplication.html b/coreblocks.fu.unsigned_multiplication.html index 39f60effd..cfce9701d 100644 --- a/coreblocks.fu.unsigned_multiplication.html +++ b/coreblocks.fu.unsigned_multiplication.html @@ -237,7 +237,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/coreblocks.html b/coreblocks.html index 2ffa12823..03f2f0090 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -218,7 +218,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/coreblocks.params.html b/coreblocks.params.html index 939a8c008..2511048b5 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -2404,7 +2404,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index f5775aaa4..cd054d859 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -348,7 +348,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 583bce67e..f01367dd9 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/coreblocks.stages.html b/coreblocks.stages.html index e004ed0b1..71e1466f1 100644 --- a/coreblocks.stages.html +++ b/coreblocks.stages.html @@ -266,7 +266,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/coreblocks.structs_common.html b/coreblocks.structs_common.html index 2b5111dd6..d10588fbc 100644 --- a/coreblocks.structs_common.html +++ b/coreblocks.structs_common.html @@ -454,7 +454,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/coreblocks.utils.html b/coreblocks.utils.html index 36f311398..0fb19f207 100644 --- a/coreblocks.utils.html +++ b/coreblocks.utils.html @@ -91,7 +91,7 @@

Submodules

coreblocks.utils.debug_signals module

-coreblocks.utils.debug_signals.auto_debug_signals(thing) → Union[Signal, Record, View, Iterable[Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]], Mapping[str, Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]]]
+coreblocks.utils.debug_signals.auto_debug_signals(thing) → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

Automatic debug signal generation.

Exposes class attributes with debug signals (Amaranth Signals, Records, Arrays and Elaboratables, Methods, classes @@ -124,7 +124,7 @@

Submodules
-__init__(layout: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]], depth: int) → None
+__init__(layout: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]], depth: int) → None
Parameters
@@ -350,7 +350,7 @@

Submodules
-coreblocks.utils.utils.assign(lhs: Union[Value, int, Enum, ValueCastable, Mapping[str, Union[Value, int, Enum, ValueCastable, Mapping[str, AssignArg]]]], rhs: Union[Value, int, Enum, ValueCastable, Mapping[str, Union[Value, int, Enum, ValueCastable, Mapping[str, AssignArg]]]], *, fields: Union[AssignType, Iterable[str], Mapping[str, Union[AssignType, Iterable[str], Mapping[str, AssignFields]]]] = AssignType.RHS, lhs_strict=False, rhs_strict=False) → Iterable[Assign]
+coreblocks.utils.utils.assign(lhs: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, AssignArg]], rhs: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, AssignArg]], *, fields: coreblocks.utils.utils.AssignType | collections.abc.Iterable[str] | collections.abc.Mapping[str, coreblocks.utils.utils.AssignType | collections.abc.Iterable[str] | collections.abc.Mapping[str, AssignFields]] = AssignType.RHS, lhs_strict=False, rhs_strict=False) → Iterable[Assign]

Safe record assignment.

This function recursively generates assignment statements for field-containing structures. This includes: Amaranth Records, @@ -424,7 +424,7 @@

Submodules
-coreblocks.utils.utils.flatten_signals(signals: Union[Signal, Record, View, Iterable[Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]], Mapping[str, Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]]]) → Iterable[Signal]
+coreblocks.utils.utils.flatten_signals(signals: amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]) → Iterable[Signal]

Flattens input data, which can be either a signal, a record, a list (or a dict) of SignalBundle items.

@@ -456,7 +456,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/genindex.html b/genindex.html index a9507f702..75549ce0f 100644 --- a/genindex.html +++ b/genindex.html @@ -2774,7 +2774,7 @@

Z

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diff --git a/index.html b/index.html index 52f612ad7..490cc151b 100644 --- a/index.html +++ b/index.html @@ -214,7 +214,7 @@

Coreblocks

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/miscellany/exceptionsSummary.html b/miscellany/exceptionsSummary.html index 77a0b01fb..a84280cb1 100644 --- a/miscellany/exceptionsSummary.html +++ b/miscellany/exceptionsSummary.html @@ -271,7 +271,7 @@

Summary

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/modules-coreblocks.html b/modules-coreblocks.html index 683a3cd4a..8c2c70082 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -187,7 +187,7 @@

coreblocks

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/modules-transactron.html b/modules-transactron.html index 49daae0b1..a85bb47ac 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -118,7 +118,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/py-modindex.html b/py-modindex.html index 186531bae..ed7ff6fbc 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -453,7 +453,7 @@

Python Module Index

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/scheduler/Overview.html b/scheduler/Overview.html index 773ff2063..6876de9c4 100644 --- a/scheduler/Overview.html +++ b/scheduler/Overview.html @@ -146,7 +146,7 @@

More detailed description of each block

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/search.html b/search.html index 8a6fa05c3..924dd7735 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/searchindex.js b/searchindex.js index c2ccd97f9..10778bb83 100644 --- a/searchindex.js +++ b/searchindex.js @@ -1 +1 @@ -Search.setIndex({"docnames": ["Assumptions", "Current_graph", "Development_environment", "Home", "Problem-checklist", "Transactions", "api", "auto_graph", "components/icache", "coreblocks", "coreblocks.frontend", "coreblocks.fu", "coreblocks.fu.unsigned_multiplication", "coreblocks.params", "coreblocks.peripherals", "coreblocks.scheduler", "coreblocks.stages", "coreblocks.structs_common", "coreblocks.utils", "index", "miscellany/exceptionsSummary", "modules-coreblocks", "modules-transactron", "scheduler/Overview", "shared_structs/Implementation/RS_impl", "shared_structs/RS", "synthesis/Synthesis", "transactron", "transactron.lib"], "filenames": ["Assumptions.md", "Current_graph.md", "Development_environment.md", "Home.md", "Problem-checklist.md", "Transactions.md", "api.md", "auto_graph.rst", "components/icache.md", "coreblocks.rst", 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+++ b/shared_structs/Implementation/RS_impl.html @@ -252,7 +252,7 @@

Read and clean row

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/shared_structs/RS.html b/shared_structs/RS.html index e60218f4d..bbf5663d9 100644 --- a/shared_structs/RS.html +++ b/shared_structs/RS.html @@ -222,7 +222,7 @@

External interface signals

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/synthesis/Synthesis.html b/synthesis/Synthesis.html index f7a83dc6d..f0361ae1c 100644 --- a/synthesis/Synthesis.html +++ b/synthesis/Synthesis.html @@ -151,7 +151,7 @@

Benchmarks

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/transactron.html b/transactron.html index b9b06e605..d27cae86b 100644 --- a/transactron.html +++ b/transactron.html @@ -148,7 +148,7 @@

Submodules
-__init__(*, name: Optional[str] = None, i: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]] = (), o: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]] = (), nonexclusive: bool = False, single_caller: bool = False)
+__init__(*, name: Optional[str] = None, i: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]] = (), o: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]] = (), nonexclusive: bool = False, single_caller: bool = False)
Parameters
@@ -221,7 +221,7 @@

Submodules
-debug_signals() → Union[Signal, Record, View, Iterable[Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]], Mapping[str, Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]]]
+debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -450,7 +450,7 @@

Submodules
-debug_signals() → Union[Signal, Record, View, Iterable[Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]], Mapping[str, Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]]]
+debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -496,7 +496,7 @@

Submodules
-debug_signals() → Union[Signal, Record, View, Iterable[Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]], Mapping[str, Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]]]
+debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -870,7 +870,7 @@

Submodules
-__init__(*, name: Optional[str] = None, i: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]] = (), o: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]] = (), nonexclusive: bool = False, single_caller: bool = False)
+__init__(*, name: Optional[str] = None, i: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]] = (), o: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]] = (), nonexclusive: bool = False, single_caller: bool = False)
Parameters
@@ -943,7 +943,7 @@

Submodules
-debug_signals() → Union[Signal, Record, View, Iterable[Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]], Mapping[str, Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]]]
+debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -1148,7 +1148,7 @@

Submodules
-debug_signals() → Union[Signal, Record, View, Iterable[Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]], Mapping[str, Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]]]
+debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -1194,7 +1194,7 @@

Submodules
-debug_signals() → Union[Signal, Record, View, Iterable[Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]], Mapping[str, Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]]]
+debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -1297,7 +1297,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.

diff --git a/transactron.lib.html b/transactron.lib.html index 8a9ef6cff..94962194d 100644 --- a/transactron.lib.html +++ b/transactron.lib.html @@ -111,7 +111,7 @@

Submodules
-__init__(*, name: Optional[str] = None, i: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]] = (), o: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]] = ())
+__init__(*, name: Optional[str] = None, i: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]] = (), o: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]] = ())
Parameters
@@ -147,7 +147,7 @@

Submodules
-debug_signals() → Union[Signal, Record, View, Iterable[Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]], Mapping[str, Union[Signal, Record, View, Iterable[SignalBundle], Mapping[str, SignalBundle]]]]
+debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -216,7 +216,7 @@

Submodules
-__init__(layout: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]])
+__init__(layout: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]])
Parameters
@@ -252,7 +252,7 @@

Submodules
-__init__(layout: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]])
+__init__(layout: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]])
Parameters
@@ -292,7 +292,7 @@

Submodules
-__init__(layout: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]] = (), rev_layout: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]] = ())
+__init__(layout: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]] = (), rev_layout: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]] = ())
Parameters
@@ -355,7 +355,7 @@

Submodules
-__init__(layout: ~typing.Union[~amaranth.hdl._rec.Layout, ~typing.Sequence[~typing.Union[~typing.Tuple[str, ~typing.Union[~amaranth.hdl.ast.Shape, ~amaranth.hdl.ast.ShapeCastable, int, range, ~typing.Type[~enum.Enum], LayoutLike]], ~typing.Tuple[str, ~typing.Union[~amaranth.hdl.ast.Shape, ~amaranth.hdl.ast.ShapeCastable, int, range, ~typing.Type[~enum.Enum], LayoutLike], ~amaranth.hdl._rec.Direction]]]], depth: int, fifo_type=<class 'amaranth.lib.fifo.SyncFIFO'>)
+__init__(layout: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]], depth: int, fifo_type=<class 'amaranth.lib.fifo.SyncFIFO'>)
Parameters
@@ -397,7 +397,7 @@

Submodules
-__init__(layout: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]])
+__init__(layout: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]])
Parameters
@@ -475,7 +475,7 @@

Submodules
-__init__(args_layout: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]], results_layout: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]])
+__init__(args_layout: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]], results_layout: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]])
Parameters
@@ -609,7 +609,7 @@

Submodules
-__init__(*, data_layout: Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]], elem_count: int, granularity: Optional[int] = None, safe_writes: bool = True)
+__init__(*, data_layout: amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]], elem_count: int, granularity: Optional[int] = None, safe_writes: bool = True)
Parameters
@@ -770,7 +770,7 @@

SubmodulesElaboratable

-__init__(targets: list[transactron.core.Method], combiner: Optional[Tuple[Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]], Callable[[TModule, list[amaranth.hdl._rec.Record]], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]]] = None)
+__init__(targets: list[transactron.core.Method], combiner: Optional[tuple[amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]], collections.abc.Callable[[transactron.core.TModule, list[amaranth.hdl._rec.Record]], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None)

Method product.

Takes arbitrary, non-zero number of target methods, and constructs a method which calls all of the target methods using the same @@ -820,7 +820,7 @@

Submodules
-__init__(target: Method, *, i_transform: Optional[Tuple[Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]], Callable[[TModule, Record], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]]] = None, o_transform: Optional[Tuple[Union[Layout, Sequence[Union[Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike]], Tuple[str, Union[Shape, ShapeCastable, int, range, Type[Enum], LayoutLike], Direction]]]], Callable[[TModule, Record], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]]] = None)
+__init__(target: Method, *, i_transform: Optional[tuple[amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]], collections.abc.Callable[[transactron.core.TModule, amaranth.hdl._rec.Record], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, o_transform: Optional[tuple[amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]], collections.abc.Callable[[transactron.core.TModule, amaranth.hdl._rec.Record], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None)
Parameters
@@ -847,7 +847,7 @@

SubmodulesElaboratable

-__init__(targets: list[transactron.core.Method], combiner: Mapping[str, 'RecordDict']]]] = None)
+__init__(targets: list[transactron.core.Method], combiner: Optional[tuple[amaranth.hdl._rec.Layout | collections.abc.Sequence[tuple[str, 'ShapeLike | LayoutLike'] | tuple[str, 'ShapeLike | LayoutLike', amaranth.hdl._rec.Direction]], collections.abc.Callable[[transactron.core.TModule, list[tuple[amaranth.hdl.ast.Value, amaranth.hdl._rec.Record]]], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None)

Method product with optional calling.

Takes arbitrary, non-zero number of target methods, and constructs a method which tries to call all of the target methods using the same @@ -895,7 +895,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 20:45 2023-10-22. + Last updated on 18:20 2023-10-23.