diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index 3750a2e9d..99f236510 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index 294def7a2..f1d8703e6 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/coreblocks.doctree b/.doctrees/coreblocks.doctree index 2e23b6fd8..8511456a1 100644 Binary files a/.doctrees/coreblocks.doctree and b/.doctrees/coreblocks.doctree differ diff --git a/.doctrees/coreblocks.peripherals.doctree b/.doctrees/coreblocks.peripherals.doctree index 70b859ab2..0aec6e3f5 100644 Binary files a/.doctrees/coreblocks.peripherals.doctree and b/.doctrees/coreblocks.peripherals.doctree differ diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree index 8e9da7bac..373b42245 100644 Binary files a/.doctrees/current-graph.doctree and b/.doctrees/current-graph.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index 3c8ce594c..5a9e0babe 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index c2ec50b71..d75831106 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -7,40 +7,40 @@ Core_InitFreeRFFifo["InitFreeRFFifo"] Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_result["result"] + WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] - Forwarder_write["write"] Forwarder_read["read"] + Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_WishboneMaster["WishboneMaster"] WishboneMaster1_result["result"] WishboneMaster1_request["request"] + WishboneMaster1_WishboneMaster["WishboneMaster"] subgraph Forwarder1["result Forwarder"] Forwarder1_read["read"] Forwarder1_write["write"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_get_read_response["get_read_response"] WishboneMasterAdapter_request_read["request_read"] + WishboneMasterAdapter_get_read_response["get_read_response"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_write["write"] BasicFifo_read["read"] + BasicFifo_write["write"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_read["request_read"] - WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_write["request_write"] + WishboneMasterAdapter1_get_write_response["get_write_response"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] @@ -67,23 +67,23 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["address_fwd Forwarder"] - Forwarder2_read["read"] Forwarder2_write["write"] + Forwarder2_read["read"] end end subgraph ICache["icache ICache"] + ICache_accept_res["accept_res"] ICache_ICache["ICache"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] - ICache_accept_res["accept_res"] ICache_ICache3["ICache"] ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] @@ -117,29 +117,29 @@ FIFO2_write["write"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_commit["commit"] RRAT_peek["peek"] + RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] RegisterFile_read1["read1"] + RegisterFile_read2["read2"] RegisterFile_free["free"] RegisterFile_write["write"] - RegisterFile_read2["read2"] end subgraph ReorderBuffer["ROB ReorderBuffer"] ReorderBuffer_put["put"] - ReorderBuffer_retire["retire"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_peek["peek"] - ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_retire["retire"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] LatencyMeasurer1__start["_start"] LatencyMeasurer1__stop["_stop"] @@ -154,18 +154,18 @@ end subgraph Fetch["fetch Fetch"] Fetch_Fetch["Fetch"] - Fetch_resume["resume"] - Fetch_Fetch1["Fetch"] Fetch_stall_exception["stall_exception"] + Fetch_Fetch1["Fetch"] + Fetch_resume["resume"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] BasicFifo3_write["write"] BasicFifo3_read["read"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] + ExceptionCauseRegister_report["report"] ExceptionCauseRegister_clear["clear"] ExceptionCauseRegister_get["get"] - ExceptionCauseRegister_report["report"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] BasicFifo4_read["read"] BasicFifo4_write["write"] @@ -178,8 +178,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_read["read"] Forwarder4_write["write"] + Forwarder4_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -197,24 +197,24 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_update["update"] + RSFuncBlock_select["select"] RSFuncBlock_insert["insert"] + RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] - RSFuncBlock_select["select"] subgraph RS["rs RS"] - RS_select["select"] - RS_update["update"] RS_RS["RS"] RS_RS1["RS"] - RS_RS2["RS"] + RS_select["select"] RS_insert["insert"] - RS_RS3["RS"] RS_take["take"] + RS_RS2["RS"] + RS_RS3["RS"] + RS_update["update"] RS_RS4["RS"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph FIFO4["fifo FIFO"] FIFO4_write["write"] FIFO4_read["read"] @@ -224,22 +224,22 @@ WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_issue["issue"] ShiftFuncUnit_accept["accept"] + ShiftFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_issue["issue"] JumpBranchFuncUnit_accept["accept"] + JumpBranchFuncUnit_issue["issue"] subgraph FIFO6["fifo_branch_resolved FIFO"] - FIFO6_read["read"] FIFO6_write["write"] + FIFO6_read["read"] end subgraph HwCounter5["perf_jumps HwCounter"] HwCounter5__incr["_incr"] @@ -251,8 +251,8 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -270,8 +270,8 @@ WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] - PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_precommit["precommit"] + PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_accept["accept"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] BasicFifo5_read["read"] @@ -307,48 +307,48 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] + LSUDummy_insert["insert"] LSUDummy_LSUDummy["LSUDummy"] - LSUDummy_update["update"] - LSUDummy_precommit["precommit"] LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_update["update"] LSUDummy_select["select"] - LSUDummy_insert["insert"] + LSUDummy_precommit["precommit"] LSUDummy_get_result["get_result"] - LSUDummy_LSUDummy2["LSUDummy"] subgraph Forwarder6["forwarder Forwarder"] - Forwarder6_read["read"] Forwarder6_write["write"] + Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond0["issue_cond0"] LSURequester_issue_cond2["issue_cond2"] - LSURequester_issue_cond1["issue_cond1"] - LSURequester_accept_cond0["accept_cond0"] LSURequester_accept["accept"] LSURequester_issue["issue"] LSURequester_accept_cond1["accept_cond1"] + LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond0["issue_cond0"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_CSRUnit["CSRUnit"] CSRUnit_insert["insert"] CSRUnit_fetch_resume["fetch_resume"] - CSRUnit_precommit["precommit"] + CSRUnit_get_result["get_result"] CSRUnit_select["select"] CSRUnit_update["update"] - CSRUnit_get_result["get_result"] + CSRUnit_precommit["precommit"] + CSRUnit_CSRUnit["CSRUnit"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] + MethodTryProduct_method["method"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] - MethodTryProduct_method["method"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_read["read"] Forwarder7_write["write"] + Forwarder7_read["read"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans9["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -364,41 +364,41 @@ ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"] end subgraph InterruptController["interrupt_controller InterruptController"] - InterruptController_mret["mret"] InterruptController_report_interrupt["report_interrupt"] InterruptController_entry["entry"] + InterruptController_mret["mret"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] - CSRRegister_write["write"] CSRRegister__fu_read["_fu_read"] CSRRegister__fu_write["_fu_write"] + CSRRegister_write["write"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_read["_fu_read"] CSRRegister1__fu_write["_fu_write"] CSRRegister1_read["read"] + CSRRegister1__fu_read["_fu_read"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2_read["read"] - CSRRegister2_write["write"] CSRRegister2__fu_write["_fu_write"] CSRRegister2__fu_read["_fu_read"] + CSRRegister2_read["read"] + CSRRegister2_write["write"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] - CSRRegister3_read["read"] CSRRegister3__fu_read["_fu_read"] CSRRegister3_write["write"] + CSRRegister3_read["read"] end subgraph CSRRegister4["register_high CSRRegister"] CSRRegister4__fu_read["_fu_read"] - CSRRegister4_read["read"] CSRRegister4_write["write"] + CSRRegister4_read["read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] @@ -409,9 +409,9 @@ CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_write["write"] - CSRRegister6__fu_read["_fu_read"] CSRRegister6_read["read"] + CSRRegister6__fu_read["_fu_read"] + CSRRegister6_write["write"] end end end @@ -427,15 +427,15 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO10["alloc_rename_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO11["rename_out_buf FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] @@ -448,8 +448,8 @@ ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO13["rs_select_out_buf FIFO"] - FIFO13_read["read"] FIFO13_write["write"] + FIFO13_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -457,8 +457,8 @@ RSSelection_RSSelection2["RSSelection"] RSSelection_RSSelection3["RSSelection"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_read["read"] Forwarder8_write["write"] + Forwarder8_read["read"] end end subgraph RSInsertion["rs_insertion RSInsertion"] @@ -470,24 +470,24 @@ end subgraph Retirement["retirement Retirement"] Retirement_Retirement["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement1["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_core_state["core_state"] Retirement_Retirement2["Retirement"] Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement3["Retirement"] - Retirement_core_state["core_state"] Retirement_Retirement4["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] + CSRRegister7_write["write"] CSRRegister7_read["read"] CSRRegister7__fu_read["_fu_read"] - CSRRegister7_write["write"] end subgraph CSRRegister8["register_high CSRRegister"] - CSRRegister8__fu_read["_fu_read"] CSRRegister8_read["read"] CSRRegister8_write["write"] + CSRRegister8__fu_read["_fu_read"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -507,19 +507,19 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] + TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] - TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] - TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] end end Core_InitFreeRFFifo --> BasicFifo2_write - Retirement_Retirement2 --> BasicFifo2_write - TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write - TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write + Retirement_Retirement --> BasicFifo2_write + TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write + TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write @@ -528,20 +528,20 @@ SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request - ICache_ICache2 <--> HwCounter4__incr - ICache_ICache3 <--> HwCounter3__incr - ICache_ICache3 <--> HwCounter2__incr - ICache_ICache3 <--> HwCounter1__incr - ICache_ICache3 --> Forwarder3_write - ICache_ICache1 --> SimpleCommonBusCacheRefiller_start_refill - ICache_ICache1 --> Forwarder2_write + ICache_ICache1 <--> HwCounter4__incr + ICache_ICache2 <--> HwCounter3__incr + ICache_ICache2 <--> HwCounter2__incr + ICache_ICache2 <--> HwCounter1__incr + ICache_ICache2 --> Forwarder3_write + ICache_ICache --> SimpleCommonBusCacheRefiller_start_refill ICache_ICache --> Forwarder2_write - SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache - WishboneMasterAdapter_get_read_response --> ICache_ICache - Serializer_Serializer --> ICache_ICache - BasicFifo_read --> ICache_ICache - WishboneMaster_result --> ICache_ICache - Forwarder_read --> ICache_ICache + ICache_ICache3 --> Forwarder2_write + SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3 + WishboneMasterAdapter_get_read_response --> ICache_ICache3 + Serializer_Serializer --> ICache_ICache3 + BasicFifo_read --> ICache_ICache3 + WishboneMaster_result --> ICache_ICache3 + Forwarder_read --> ICache_ICache3 Fetch_Fetch --> ICache_issue_req Fetch_Fetch <--> HwCounter__incr Fetch_Fetch <--> LatencyMeasurer__start @@ -571,26 +571,26 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename - Retirement_Retirement2 --> FRAT_rename - TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename + Retirement_Retirement --> FRAT_rename + TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write - FIFO12_read --> RSSelection_RSSelection2 - RSSelection_RSSelection2 --> Forwarder8_write - Forwarder8_read --> RSSelection_RSSelection - Forwarder8_read --> RSSelection_RSSelection3 + FIFO12_read --> RSSelection_RSSelection + RSSelection_RSSelection --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection1 - RSFuncBlock_select --> RSSelection_RSSelection - RS_select --> RSSelection_RSSelection - RSSelection_RSSelection --> FIFO13_write - RSSelection_RSSelection3 --> FIFO13_write + Forwarder8_read --> RSSelection_RSSelection3 + Forwarder8_read --> RSSelection_RSSelection2 + RSFuncBlock_select --> RSSelection_RSSelection1 + RS_select --> RSSelection_RSSelection1 RSSelection_RSSelection1 --> FIFO13_write + RSSelection_RSSelection3 --> FIFO13_write + RSSelection_RSSelection2 --> FIFO13_write RSSelection_RSSelection3 <--> LSUDummy_select - RSSelection_RSSelection1 <--> CSRUnit_select + RSSelection_RSSelection2 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -606,7 +606,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume - Retirement_Retirement3 --> Fetch_resume + Retirement_Retirement2 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -616,7 +616,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update - RS_RS2 --> WakeupSelect_WakeupSelect + RS_RS1 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -624,10 +624,10 @@ RS_take --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO4_write - RS_RS --> WakeupSelect1_WakeupSelect + RS_RS2 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write - RS_RS1 --> WakeupSelect2_WakeupSelect + RS_RS3 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -639,7 +639,7 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write - RS_RS3 --> WakeupSelect3_WakeupSelect + RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write RS_RS4 --> WakeupSelect4_WakeupSelect @@ -664,8 +664,8 @@ TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write - TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write + TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -687,45 +687,45 @@ LSUDummy_get_result --> ConnectTrans2_ConnectTrans Forwarder6_read --> ConnectTrans2_ConnectTrans CSRUnit_get_result --> ConnectTrans3_ConnectTrans - MethodTryProduct_MethodTryProduct --> PrivilegedFuncUnit_precommit - MethodTryProduct_MethodTryProduct <--> InterruptController_mret - MethodTryProduct_MethodTryProduct1 --> LSUDummy_precommit - MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit + MethodTryProduct_MethodTryProduct2 --> PrivilegedFuncUnit_precommit + MethodTryProduct_MethodTryProduct2 <--> InterruptController_mret + MethodTryProduct_MethodTryProduct --> LSUDummy_precommit + MethodTryProduct_MethodTryProduct1 --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans - ReorderBuffer_peek --> Retirement_Retirement + ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> Retirement_Retirement1 - ReorderBuffer_peek --> Retirement_Retirement2 - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement --> MethodTryProduct_method + ReorderBuffer_peek --> Retirement_Retirement + ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement + Retirement_Retirement4 --> MethodTryProduct_method ExceptionCauseRegister_get --> Retirement_Retirement1 - ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 - ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement2 <--> ReorderBuffer_retire - TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire - TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire - Retirement_Retirement2 <--> LatencyMeasurer1__stop - TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop - TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop - FIFO3_read --> Retirement_Retirement2 - FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 - FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement2 --> HwExpHistogram1__add - TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add - TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add - CoreInstructionCounter_decrement --> Retirement_Retirement2 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 - RRAT_peek --> Retirement_Retirement2 - RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement2 --> RegisterFile_free - TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free - TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free - CSRRegister1_read --> Retirement_Retirement3 - Retirement_Retirement3 <--> ExceptionCauseRegister_clear + ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement + ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement + Retirement_Retirement <--> ReorderBuffer_retire + TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire + TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire + Retirement_Retirement <--> LatencyMeasurer1__stop + TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop + TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop + FIFO3_read --> Retirement_Retirement + FIFO3_read --> TransactionManager_Retirement_cond0_Retirement + FIFO3_read --> TransactionManager_Retirement_cond1_Retirement + Retirement_Retirement --> HwExpHistogram1__add + TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add + TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add + CoreInstructionCounter_decrement --> Retirement_Retirement + CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement + CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement + RRAT_peek --> Retirement_Retirement + RRAT_peek --> TransactionManager_Retirement_cond1_Retirement + Retirement_Retirement --> RegisterFile_free + TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free + TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free + CSRRegister1_read --> Retirement_Retirement2 + Retirement_Retirement2 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -737,22 +737,29 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement4 - TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement4 - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write - TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry - TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 + TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_cond0_Retirement --> RRAT_commit + TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment + CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write + CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write + TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr + TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement3 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3 + TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write + TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write + TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write + TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write + TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry + TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy1 TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy1 LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 - Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond1 + Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond1 BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 @@ -760,30 +767,23 @@ Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy - TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy + TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 + TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer2 TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 - Serializer1_Serializer2 --> TransactionManager_LSUDummy_accept_cond0 - TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit - TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment - CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write - CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write - TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr + Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read - TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer - TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 + TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer1 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 diff --git a/api.html b/api.html index fbb9295eb..b563ca069 100644 --- a/api.html +++ b/api.html @@ -282,7 +282,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/assumptions.html b/assumptions.html index 22864825f..c488796fe 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/auto_graph.html b/auto_graph.html index 5545689e9..aa0de148d 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -86,40 +86,40 @@ Core_InitFreeRFFifo["InitFreeRFFifo"] Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_result["result"] + WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] - Forwarder_write["write"] Forwarder_read["read"] + Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_WishboneMaster["WishboneMaster"] WishboneMaster1_result["result"] WishboneMaster1_request["request"] + WishboneMaster1_WishboneMaster["WishboneMaster"] subgraph Forwarder1["result Forwarder"] Forwarder1_read["read"] Forwarder1_write["write"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_get_read_response["get_read_response"] WishboneMasterAdapter_request_read["request_read"] + WishboneMasterAdapter_get_read_response["get_read_response"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_write["write"] BasicFifo_read["read"] + BasicFifo_write["write"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_read["request_read"] - WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_write["request_write"] + WishboneMasterAdapter1_get_write_response["get_write_response"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] @@ -146,23 +146,23 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["address_fwd Forwarder"] - Forwarder2_read["read"] Forwarder2_write["write"] + Forwarder2_read["read"] end end subgraph ICache["icache ICache"] + ICache_accept_res["accept_res"] ICache_ICache["ICache"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] - ICache_accept_res["accept_res"] ICache_ICache3["ICache"] ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] @@ -196,29 +196,29 @@ FIFO2_write["write"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_commit["commit"] RRAT_peek["peek"] + RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] RegisterFile_read1["read1"] + RegisterFile_read2["read2"] RegisterFile_free["free"] RegisterFile_write["write"] - RegisterFile_read2["read2"] end subgraph ReorderBuffer["ROB ReorderBuffer"] ReorderBuffer_put["put"] - ReorderBuffer_retire["retire"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_peek["peek"] - ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_retire["retire"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] LatencyMeasurer1__start["_start"] LatencyMeasurer1__stop["_stop"] @@ -233,18 +233,18 @@ end subgraph Fetch["fetch Fetch"] Fetch_Fetch["Fetch"] - Fetch_resume["resume"] - Fetch_Fetch1["Fetch"] Fetch_stall_exception["stall_exception"] + Fetch_Fetch1["Fetch"] + Fetch_resume["resume"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] BasicFifo3_write["write"] BasicFifo3_read["read"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] + ExceptionCauseRegister_report["report"] ExceptionCauseRegister_clear["clear"] ExceptionCauseRegister_get["get"] - ExceptionCauseRegister_report["report"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] BasicFifo4_read["read"] BasicFifo4_write["write"] @@ -257,8 +257,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_read["read"] Forwarder4_write["write"] + Forwarder4_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -276,24 +276,24 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_update["update"] + RSFuncBlock_select["select"] RSFuncBlock_insert["insert"] + RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] - RSFuncBlock_select["select"] subgraph RS["rs RS"] - RS_select["select"] - RS_update["update"] RS_RS["RS"] RS_RS1["RS"] - RS_RS2["RS"] + RS_select["select"] RS_insert["insert"] - RS_RS3["RS"] RS_take["take"] + RS_RS2["RS"] + RS_RS3["RS"] + RS_update["update"] RS_RS4["RS"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph FIFO4["fifo FIFO"] FIFO4_write["write"] FIFO4_read["read"] @@ -303,22 +303,22 @@ WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_issue["issue"] ShiftFuncUnit_accept["accept"] + ShiftFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_issue["issue"] JumpBranchFuncUnit_accept["accept"] + JumpBranchFuncUnit_issue["issue"] subgraph FIFO6["fifo_branch_resolved FIFO"] - FIFO6_read["read"] FIFO6_write["write"] + FIFO6_read["read"] end subgraph HwCounter5["perf_jumps HwCounter"] HwCounter5__incr["_incr"] @@ -330,8 +330,8 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -349,8 +349,8 @@ WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] - PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_precommit["precommit"] + PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_accept["accept"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] BasicFifo5_read["read"] @@ -386,48 +386,48 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] + LSUDummy_insert["insert"] LSUDummy_LSUDummy["LSUDummy"] - LSUDummy_update["update"] - LSUDummy_precommit["precommit"] LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_update["update"] LSUDummy_select["select"] - LSUDummy_insert["insert"] + LSUDummy_precommit["precommit"] LSUDummy_get_result["get_result"] - LSUDummy_LSUDummy2["LSUDummy"] subgraph Forwarder6["forwarder Forwarder"] - Forwarder6_read["read"] Forwarder6_write["write"] + Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond0["issue_cond0"] LSURequester_issue_cond2["issue_cond2"] - LSURequester_issue_cond1["issue_cond1"] - LSURequester_accept_cond0["accept_cond0"] LSURequester_accept["accept"] LSURequester_issue["issue"] LSURequester_accept_cond1["accept_cond1"] + LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond0["issue_cond0"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_CSRUnit["CSRUnit"] CSRUnit_insert["insert"] CSRUnit_fetch_resume["fetch_resume"] - CSRUnit_precommit["precommit"] + CSRUnit_get_result["get_result"] CSRUnit_select["select"] CSRUnit_update["update"] - CSRUnit_get_result["get_result"] + CSRUnit_precommit["precommit"] + CSRUnit_CSRUnit["CSRUnit"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] + MethodTryProduct_method["method"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] - MethodTryProduct_method["method"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_read["read"] Forwarder7_write["write"] + Forwarder7_read["read"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans9["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -443,41 +443,41 @@ ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"] end subgraph InterruptController["interrupt_controller InterruptController"] - InterruptController_mret["mret"] InterruptController_report_interrupt["report_interrupt"] InterruptController_entry["entry"] + InterruptController_mret["mret"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] - CSRRegister_write["write"] CSRRegister__fu_read["_fu_read"] CSRRegister__fu_write["_fu_write"] + CSRRegister_write["write"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_read["_fu_read"] CSRRegister1__fu_write["_fu_write"] CSRRegister1_read["read"] + CSRRegister1__fu_read["_fu_read"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2_read["read"] - CSRRegister2_write["write"] CSRRegister2__fu_write["_fu_write"] CSRRegister2__fu_read["_fu_read"] + CSRRegister2_read["read"] + CSRRegister2_write["write"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] - CSRRegister3_read["read"] CSRRegister3__fu_read["_fu_read"] CSRRegister3_write["write"] + CSRRegister3_read["read"] end subgraph CSRRegister4["register_high CSRRegister"] CSRRegister4__fu_read["_fu_read"] - CSRRegister4_read["read"] CSRRegister4_write["write"] + CSRRegister4_read["read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] @@ -488,9 +488,9 @@ CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_write["write"] - CSRRegister6__fu_read["_fu_read"] CSRRegister6_read["read"] + CSRRegister6__fu_read["_fu_read"] + CSRRegister6_write["write"] end end end @@ -506,15 +506,15 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO10["alloc_rename_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO11["rename_out_buf FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] @@ -527,8 +527,8 @@ ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO13["rs_select_out_buf FIFO"] - FIFO13_read["read"] FIFO13_write["write"] + FIFO13_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -536,8 +536,8 @@ RSSelection_RSSelection2["RSSelection"] RSSelection_RSSelection3["RSSelection"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_read["read"] Forwarder8_write["write"] + Forwarder8_read["read"] end end subgraph RSInsertion["rs_insertion RSInsertion"] @@ -549,24 +549,24 @@ end subgraph Retirement["retirement Retirement"] Retirement_Retirement["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement1["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_core_state["core_state"] Retirement_Retirement2["Retirement"] Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement3["Retirement"] - Retirement_core_state["core_state"] Retirement_Retirement4["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] + CSRRegister7_write["write"] CSRRegister7_read["read"] CSRRegister7__fu_read["_fu_read"] - CSRRegister7_write["write"] end subgraph CSRRegister8["register_high CSRRegister"] - CSRRegister8__fu_read["_fu_read"] CSRRegister8_read["read"] CSRRegister8_write["write"] + CSRRegister8__fu_read["_fu_read"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -586,19 +586,19 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] + TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] - TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] - TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] end end Core_InitFreeRFFifo --> BasicFifo2_write -Retirement_Retirement2 --> BasicFifo2_write -TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write -TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write +Retirement_Retirement --> BasicFifo2_write +TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write +TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write @@ -607,20 +607,20 @@ SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request -ICache_ICache2 <--> HwCounter4__incr -ICache_ICache3 <--> HwCounter3__incr -ICache_ICache3 <--> HwCounter2__incr -ICache_ICache3 <--> HwCounter1__incr -ICache_ICache3 --> Forwarder3_write -ICache_ICache1 --> SimpleCommonBusCacheRefiller_start_refill -ICache_ICache1 --> Forwarder2_write +ICache_ICache1 <--> HwCounter4__incr +ICache_ICache2 <--> HwCounter3__incr +ICache_ICache2 <--> HwCounter2__incr +ICache_ICache2 <--> HwCounter1__incr +ICache_ICache2 --> Forwarder3_write +ICache_ICache --> SimpleCommonBusCacheRefiller_start_refill ICache_ICache --> Forwarder2_write -SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache -WishboneMasterAdapter_get_read_response --> ICache_ICache -Serializer_Serializer --> ICache_ICache -BasicFifo_read --> ICache_ICache -WishboneMaster_result --> ICache_ICache -Forwarder_read --> ICache_ICache +ICache_ICache3 --> Forwarder2_write +SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3 +WishboneMasterAdapter_get_read_response --> ICache_ICache3 +Serializer_Serializer --> ICache_ICache3 +BasicFifo_read --> ICache_ICache3 +WishboneMaster_result --> ICache_ICache3 +Forwarder_read --> ICache_ICache3 Fetch_Fetch --> ICache_issue_req Fetch_Fetch <--> HwCounter__incr Fetch_Fetch <--> LatencyMeasurer__start @@ -650,26 +650,26 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename -Retirement_Retirement2 --> FRAT_rename -TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename +Retirement_Retirement --> FRAT_rename +TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write -FIFO12_read --> RSSelection_RSSelection2 -RSSelection_RSSelection2 --> Forwarder8_write -Forwarder8_read --> RSSelection_RSSelection -Forwarder8_read --> RSSelection_RSSelection3 +FIFO12_read --> RSSelection_RSSelection +RSSelection_RSSelection --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection1 -RSFuncBlock_select --> RSSelection_RSSelection -RS_select --> RSSelection_RSSelection -RSSelection_RSSelection --> FIFO13_write -RSSelection_RSSelection3 --> FIFO13_write +Forwarder8_read --> RSSelection_RSSelection3 +Forwarder8_read --> RSSelection_RSSelection2 +RSFuncBlock_select --> RSSelection_RSSelection1 +RS_select --> RSSelection_RSSelection1 RSSelection_RSSelection1 --> FIFO13_write +RSSelection_RSSelection3 --> FIFO13_write +RSSelection_RSSelection2 --> FIFO13_write RSSelection_RSSelection3 <--> LSUDummy_select -RSSelection_RSSelection1 <--> CSRUnit_select +RSSelection_RSSelection2 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -685,7 +685,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume -Retirement_Retirement3 --> Fetch_resume +Retirement_Retirement2 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -695,7 +695,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update -RS_RS2 --> WakeupSelect_WakeupSelect +RS_RS1 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -703,10 +703,10 @@ RS_take --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO4_write -RS_RS --> WakeupSelect1_WakeupSelect +RS_RS2 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write -RS_RS1 --> WakeupSelect2_WakeupSelect +RS_RS3 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -718,7 +718,7 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write -RS_RS3 --> WakeupSelect3_WakeupSelect +RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write RS_RS4 --> WakeupSelect4_WakeupSelect @@ -743,8 +743,8 @@ TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write -TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write +TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -766,45 +766,45 @@ LSUDummy_get_result --> ConnectTrans2_ConnectTrans Forwarder6_read --> ConnectTrans2_ConnectTrans CSRUnit_get_result --> ConnectTrans3_ConnectTrans -MethodTryProduct_MethodTryProduct --> PrivilegedFuncUnit_precommit -MethodTryProduct_MethodTryProduct <--> InterruptController_mret -MethodTryProduct_MethodTryProduct1 --> LSUDummy_precommit -MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit +MethodTryProduct_MethodTryProduct2 --> PrivilegedFuncUnit_precommit +MethodTryProduct_MethodTryProduct2 <--> InterruptController_mret +MethodTryProduct_MethodTryProduct --> LSUDummy_precommit +MethodTryProduct_MethodTryProduct1 --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans -ReorderBuffer_peek --> Retirement_Retirement +ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> Retirement_Retirement1 -ReorderBuffer_peek --> Retirement_Retirement2 -ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 -ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement --> MethodTryProduct_method +ReorderBuffer_peek --> Retirement_Retirement +ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement +ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement +Retirement_Retirement4 --> MethodTryProduct_method ExceptionCauseRegister_get --> Retirement_Retirement1 -ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 -ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement2 <--> ReorderBuffer_retire -TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire -TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire -Retirement_Retirement2 <--> LatencyMeasurer1__stop -TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop -TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop -FIFO3_read --> Retirement_Retirement2 -FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 -FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement2 --> HwExpHistogram1__add -TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add -TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add -CoreInstructionCounter_decrement --> Retirement_Retirement2 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 -RRAT_peek --> Retirement_Retirement2 -RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement2 --> RegisterFile_free -TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free -TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free -CSRRegister1_read --> Retirement_Retirement3 -Retirement_Retirement3 <--> ExceptionCauseRegister_clear +ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement +ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement +Retirement_Retirement <--> ReorderBuffer_retire +TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire +TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire +Retirement_Retirement <--> LatencyMeasurer1__stop +TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop +TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop +FIFO3_read --> Retirement_Retirement +FIFO3_read --> TransactionManager_Retirement_cond0_Retirement +FIFO3_read --> TransactionManager_Retirement_cond1_Retirement +Retirement_Retirement --> HwExpHistogram1__add +TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add +TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add +CoreInstructionCounter_decrement --> Retirement_Retirement +CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement +CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement +RRAT_peek --> Retirement_Retirement +RRAT_peek --> TransactionManager_Retirement_cond1_Retirement +Retirement_Retirement --> RegisterFile_free +TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free +TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free +CSRRegister1_read --> Retirement_Retirement2 +Retirement_Retirement2 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -816,22 +816,29 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement4 -TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement4 -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write -TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry -TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 +TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_cond0_Retirement --> RRAT_commit +TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment +CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write +CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write +TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr +TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement3 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3 +TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write +TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write +TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write +TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write +TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry +TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy1 TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy1 LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 -Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond1 +Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond1 BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 @@ -839,33 +846,26 @@ Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy -TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy +TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write -TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 +TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer2 TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 -Serializer1_Serializer2 --> TransactionManager_LSUDummy_accept_cond0 -TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit -TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment -CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write -CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write -TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr +Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond0 +TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read -TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer -TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 +TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer1 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 @@ -876,7 +876,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/components/icache.html b/components/icache.html index 7c98971c3..c44be0b31 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index 8e4f49a6a..c1efeb535 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -241,7 +241,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index d99f79f28..c965e7203 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -368,7 +368,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/coreblocks.fu.html b/coreblocks.fu.html index 319af5f94..294d3b1e9 100644 --- a/coreblocks.fu.html +++ b/coreblocks.fu.html @@ -965,7 +965,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/coreblocks.fu.unsigned_multiplication.html b/coreblocks.fu.unsigned_multiplication.html index 09e92f2a0..25447c615 100644 --- a/coreblocks.fu.unsigned_multiplication.html +++ b/coreblocks.fu.unsigned_multiplication.html @@ -237,7 +237,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/coreblocks.html b/coreblocks.html index 72d1c648e..f59c8f5bc 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -211,7 +211,7 @@

SubmodulesElaboratable

-__init__(*, gen_params: GenParams, wb_instr_bus: WishboneBus, wb_data_bus: WishboneBus)
+__init__(*, gen_params: GenParams, wb_instr_bus: WishboneInterface, wb_data_bus: WishboneInterface)
@@ -234,7 +234,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/coreblocks.lsu.html b/coreblocks.lsu.html index 934095744..c261c33c9 100644 --- a/coreblocks.lsu.html +++ b/coreblocks.lsu.html @@ -236,7 +236,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/coreblocks.params.html b/coreblocks.params.html index 8877218d7..c3ad994ad 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -2701,7 +2701,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index 57c01f6e8..d4e44e520 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -89,10 +89,41 @@

Submodules

coreblocks.peripherals.axi_lite module

+
+
+class coreblocks.peripherals.axi_lite.AXILiteInterface
+

Bases: AbstractInterface[AbstractSignature], Protocol

+
+
+read_address: AXILiteReadAddressInterface
+
+ +
+
+read_data: AXILiteReadDataInterface
+
+ +
+
+write_address: AXILiteWriteAddressInterface
+
+ +
+
+write_data: AXILiteWriteDataInterface
+
+ +
+
+write_response: AXILiteWriteResponseInterface
+
+ +
+
class coreblocks.peripherals.axi_lite.AXILiteMaster
-

Bases: Elaboratable

+

Bases: Component

AXI-Lite master interface.

Parameters
@@ -131,9 +162,14 @@

Submodules__init__(axil_params: AXILiteParameters)

+
+
+axil_master: AXILiteInterface
+
+
-result_handler(m: TModule, forwarder: Forwarder, *, data: bool, channel: Record)
+result_handler(m: TModule, forwarder: Forwarder, *, channel: coreblocks.peripherals.axi_lite.AXILiteWriteResponseInterface | coreblocks.peripherals.axi_lite.AXILiteReadDataInterface)
@@ -143,7 +179,7 @@

Submodules
-state_machine_request(m: TModule, method: Method, *, channel: Record, request_signal: Signal)
+state_machine_request(m: TModule, method: Method, *, channel: coreblocks.peripherals.axi_lite.AXILiteWriteAddressInterface | coreblocks.peripherals.axi_lite.AXILiteWriteDataInterface | coreblocks.peripherals.axi_lite.AXILiteReadAddressInterface, request_signal: Signal)

@@ -170,6 +206,26 @@

Submodules +
+class coreblocks.peripherals.axi_lite.AXILiteSignature
+

Bases: Signature

+

AXI-Lite bus signature

+
+
Parameters
+
+
axil_params: AXILiteParameters

Patameters used to generate AXI-Lite signature

+
+
+
+
+
+
+__init__(axil_params: AXILiteParameters)
+
+ +
+

coreblocks.peripherals.bus_adapter module

@@ -319,7 +375,7 @@

Submodules
class coreblocks.peripherals.wishbone.PipelinedWishboneMaster
-

Bases: Elaboratable

+

Bases: Component

Pipelined Wishbone bus master interface.

Parameters
@@ -332,7 +388,7 @@

SubmodulesAttributes
-
wb: Record (like WishboneLayout)

Wishbone bus output.

+
wb: WishboneInterface

Wishbone bus output.

request: Method

Transactional method to start a new Wishbone request. Ready if new request can be immediately sent. @@ -357,77 +413,122 @@

Submodulesgenerate_method_layouts(wb_params: WishboneParameters)

+
+
+wb: WishboneInterface
+
+

class coreblocks.peripherals.wishbone.WishboneArbiter
-

Bases: Elaboratable

+

Bases: Component

Wishbone Arbiter.

Connects multiple masters to one slave. Bus is requested by asserting CYC signal and is granted to masters in a round robin manner.

Parameters
-
slave_wb: Record (like WishboneLayout)

Record of slave inteface.

+
wb_params: WishboneParameters

Parameters for bus generation.

+
+
num_slaves: int

Number of master devices.

+
+
+
+
Attributes
+
+
slave_wb: WishboneInterface

Slave inteface.

-
masters: List[Record]

List of master interface Records.

+
masters: list of WishboneInterface

List of master interfaces.

-__init__(slave_wb: Record, masters: List[Record])
+__init__(wb_params: WishboneParameters, num_masters: int)
-
+
+
+masters: list[coreblocks.peripherals.wishbone.WishboneInterface]
+
-
-
-class coreblocks.peripherals.wishbone.WishboneBus
-

Bases: Record

-

Wishbone bus.

-
-
Parameters
-
-
wb_params: WishboneParameters

Parameters for bus generation.

-
-
-
-
-
-
-__init__(wb_params: WishboneParameters, **kwargs)
+
+
+slave_wb: WishboneInterface
-
-class coreblocks.peripherals.wishbone.WishboneLayout
-

Bases: object

-

Wishbone bus Layout generator.

-
-
Parameters
-
-
wb_params: WishboneParameters

Parameters used to generate Wishbone layout

-
-
master: Boolean

Whether the layout should be generated for the master side -(otherwise it’s generated for the slave side)

-
-
-
-
Attributes
-
-
wb_layout: Record

Record of a Wishbone bus.

-
-
-
-
-
-
-__init__(wb_params: WishboneParameters, master=True)
+
+class coreblocks.peripherals.wishbone.WishboneInterface
+

Bases: AbstractInterface[AbstractSignature], Protocol

+
+
+ack: Signal
+
+ +
+
+adr: Signal
+
+ +
+
+cyc: Signal
+
+ +
+
+dat_r: Signal
+
+ +
+
+dat_w: Signal
+
+ +
+
+err: Signal
+
+ +
+
+lock: Signal
+
+ +
+
+rst: Signal
+
+ +
+
+rty: Signal
+
+ +
+
+sel: Signal
+
+ +
+
+stall: Signal
+
+ +
+
+stb: Signal
+
+ +
+
+we: Signal
@@ -435,7 +536,7 @@

Submodules
class coreblocks.peripherals.wishbone.WishboneMaster
-

Bases: Elaboratable

+

Bases: Component

Wishbone bus master interface.

Parameters
@@ -446,7 +547,7 @@

SubmodulesAttributes
-
wb_master: Record (like WishboneLayout)

Wishbone bus output.

+
wb_master: WishboneInterface

Wishbone bus output.

request: Method

Transactional method to start a new Wishbone request. Ready when no request is being executed and previous result is read. @@ -464,6 +565,11 @@

Submodules__init__(wb_params: WishboneParameters)

+
+
+wb_master: WishboneInterface
+
+

@@ -497,7 +603,7 @@

Submodules
class coreblocks.peripherals.wishbone.WishboneMemorySlave
-

Bases: Elaboratable

+

Bases: Component

Wishbone slave with memory Wishbone slave interface with addressable memory underneath.

@@ -513,7 +619,7 @@

SubmodulesAttributes
-
bus: Record (like WishboneLayout)

Wishbone bus record.

+
bus: WishboneInterface

Wishbone bus interface.

@@ -523,20 +629,25 @@

Submodules__init__(wb_params: WishboneParameters, **kwargs)

+
+
+bus: WishboneInterface
+
+

class coreblocks.peripherals.wishbone.WishboneMuxer
-

Bases: Elaboratable

+

Bases: Component

Wishbone Muxer.

Connects one master to multiple slaves.

Parameters
-
master_wb: Record (like WishboneLayout)

Record of master inteface.

+
wb_params: WishboneParameters

Parameters for bus generation.

-
slaves: List[Record]

List of connected slaves’ Wishbone Records (like WishboneLayout).

+
num_slaves: int

Number of slave devices to multiplex.

ssel_tga: Signal

Signal that selects the slave to connect. Signal width is the number of slaves and each bit coresponds to a slave. This signal is a Wishbone TGA (address tag), so it needs to be valid every time Wishbone STB @@ -548,10 +659,28 @@

SubmodulesAttributes +
+
master_wb: WishboneInterface

Master inteface.

+
+
slaves: list of WishboneInterface

List of connected slaves’ Wishbone interfaces.

+
+
+

-__init__(master_wb: Record, slaves: List[Record], ssel_tga: Signal)
+__init__(wb_params: WishboneParameters, num_slaves: int, ssel_tga: Signal) +
+ +
+
+master_wb: WishboneInterface
+
+ +
+
+slaves: list[coreblocks.peripherals.wishbone.WishboneInterface]
@@ -580,6 +709,23 @@

Submodules +
+class coreblocks.peripherals.wishbone.WishboneSignature
+

Bases: Signature

+
+
+__init__(wb_params: WishboneParameters)
+
+ +
+
+create(*, path: tuple[str | int, ...] = (), src_loc_at: int = 0)
+

Create a WishboneInterface.

+
+ +

+

diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index ff0feec30..bac87e6f0 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/coreblocks.stages.html b/coreblocks.stages.html index 78f576efd..96d0ac310 100644 --- a/coreblocks.stages.html +++ b/coreblocks.stages.html @@ -263,7 +263,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/coreblocks.structs_common.html b/coreblocks.structs_common.html index d1655edce..e05bc67b4 100644 --- a/coreblocks.structs_common.html +++ b/coreblocks.structs_common.html @@ -522,7 +522,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/coreblocks.utils.html b/coreblocks.utils.html index 997034936..b64d42b2f 100644 --- a/coreblocks.utils.html +++ b/coreblocks.utils.html @@ -149,7 +149,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/current-graph.html b/current-graph.html index 56a25c6d6..ae10765e5 100644 --- a/current-graph.html +++ b/current-graph.html @@ -92,40 +92,40 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/development-environment.html b/development-environment.html index 4c4455510..730af3fa4 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:21 2024-03-12. + Last updated on 09:58 2024-03-13.

diff --git a/genindex.html b/genindex.html index 93fc1672f..a9084ea4d 100644 --- a/genindex.html +++ b/genindex.html @@ -265,6 +265,8 @@

_

  • (coreblocks.peripherals.axi_lite.AXILiteMaster method)
  • (coreblocks.peripherals.axi_lite.AXILiteParameters method) +
    • +
  • (coreblocks.peripherals.axi_lite.AXILiteSignature method)
  • (coreblocks.peripherals.bus_adapter.AXILiteMasterAdapter method)
    • @@ -273,10 +275,6 @@

    _

  • (coreblocks.peripherals.wishbone.PipelinedWishboneMaster method)
  • (coreblocks.peripherals.wishbone.WishboneArbiter method) -
    • -
  • (coreblocks.peripherals.wishbone.WishboneBus method) -
    • -
  • (coreblocks.peripherals.wishbone.WishboneLayout method)
  • (coreblocks.peripherals.wishbone.WishboneMaster method)
    • @@ -287,6 +285,8 @@

    _

  • (coreblocks.peripherals.wishbone.WishboneMuxer method)
  • (coreblocks.peripherals.wishbone.WishboneParameters method) +
    • +
  • (coreblocks.peripherals.wishbone.WishboneSignature method)
  • (coreblocks.scheduler.scheduler.Scheduler method)
    • @@ -542,6 +542,8 @@

    A

  • accept_res (coreblocks.cache.iface.CacheInterface attribute)
  • access_fault (coreblocks.params.layouts.FetchLayouts attribute) +
    • +
  • ack (coreblocks.peripherals.wishbone.WishboneInterface attribute)
  • Adapter (class in transactron.lib.adapters)
    • @@ -582,6 +584,8 @@

    A

  • addr (coreblocks.params.layouts.CommonLayoutFields attribute)
  • ADDRESS_GENERATION (coreblocks.params.optypes.OpType attribute) +
    • +
  • adr (coreblocks.peripherals.wishbone.WishboneInterface attribute)
  • align_down_to_power_of_two() (in module transactron.utils.data_repr)
    • @@ -651,11 +655,17 @@

    A

  • (transactron.TModule method)
    • +
  • axil_master (coreblocks.peripherals.axi_lite.AXILiteMaster attribute) +
    • +
  • AXILiteInterface (class in coreblocks.peripherals.axi_lite) +
  • AXILiteMaster (class in coreblocks.peripherals.axi_lite)
  • AXILiteMasterAdapter (class in coreblocks.peripherals.bus_adapter)
  • AXILiteParameters (class in coreblocks.peripherals.axi_lite) +
    • +
  • AXILiteSignature (class in coreblocks.peripherals.axi_lite)
    • @@ -707,10 +717,10 @@

    B

  • BIT_ROTATION (coreblocks.params.optypes.OpType attribute)
    • - - + +
  • create() (coreblocks.peripherals.wishbone.WishboneSignature method) +
  • csr (coreblocks.params.layouts.CommonLayoutFields attribute)
  • csr_access_privilege() (in module coreblocks.structs_common.csr) @@ -1388,6 +1402,8 @@

    C

  • (coreblocks.params.isa.Funct7 attribute)
    • +
  • cyc (coreblocks.peripherals.wishbone.WishboneInterface attribute) +
  • CYCLE (coreblocks.structs_common.csr_generic.CSRAddress attribute)
  • CYCLEH (coreblocks.structs_common.csr_generic.CSRAddress attribute) @@ -1406,6 +1422,10 @@

    D

  • (coreblocks.params.isa.Funct3 attribute)
    • +
  • dat_r (coreblocks.peripherals.wishbone.WishboneInterface attribute) +
    • +
  • dat_w (coreblocks.peripherals.wishbone.WishboneInterface attribute) +
  • data (coreblocks.params.layouts.CommonLayoutFields attribute)
  • data_in (transactron.lib.adapters.AdapterBase attribute) @@ -1635,6 +1655,8 @@

    E

  • ENVIRONMENT_CALL_FROM_S (coreblocks.params.isa.ExceptionCause attribute)
  • ENVIRONMENT_CALL_FROM_U (coreblocks.params.isa.ExceptionCause attribute) +
    • +
  • err (coreblocks.peripherals.wishbone.WishboneInterface attribute)
  • error (coreblocks.params.layouts.CommonLayoutFields attribute) @@ -2161,6 +2183,8 @@

    L

  • LOAD_PAGE_FAULT (coreblocks.params.isa.ExceptionCause attribute)
  • location (transactron.utils.gen.AssertLocation attribute) +
    • +
  • lock (coreblocks.peripherals.wishbone.WishboneInterface attribute)
  • lock_on_get (transactron.lib.dependencies.DependencyKey attribute) @@ -2207,6 +2231,10 @@

    M

  • make_hashable() (in module transactron.utils.data_repr)
  • ManyToOneConnectTrans (class in transactron.lib.connectors) +
    • +
  • master_wb (coreblocks.peripherals.wishbone.WishboneMuxer attribute) +
    • +
  • masters (coreblocks.peripherals.wishbone.WishboneArbiter attribute)
  • MAX (coreblocks.params.isa.Funct3 attribute) @@ -2780,6 +2808,10 @@

    R

  • RATLayouts (class in coreblocks.params.layouts)
  • rd_zero (coreblocks.frontend.instr_description.Encoding attribute) +
    • +
  • read_address (coreblocks.peripherals.axi_lite.AXILiteInterface attribute) +
    • +
  • read_data (coreblocks.peripherals.axi_lite.AXILiteInterface attribute)
  • ready_list (coreblocks.params.layouts.RSLayouts attribute)
    • @@ -2924,6 +2956,10 @@

    R

  • RSInterfaceLayouts (class in coreblocks.params.layouts)
  • RSLayouts (class in coreblocks.params.layouts) +
    • +
  • rst (coreblocks.peripherals.wishbone.WishboneInterface attribute) +
    • +
  • rty (coreblocks.peripherals.wishbone.WishboneInterface attribute)
  • RTypeInstr (class in coreblocks.params.instr)
    • @@ -3007,6 +3043,8 @@

    S

  • (transactron.utils.gen.MetricLocation class method)
    • +
  • sel (coreblocks.peripherals.wishbone.WishboneInterface attribute) +
  • select (coreblocks.utils.protocols.FuncBlock attribute)
  • Semaphore (class in transactron.lib.fifo) @@ -3071,10 +3109,10 @@

    S

  • SHIFT_MUL (coreblocks.fu.mul_unit.MulType attribute)
    • - - +
  • stack (transactron.utils.dependencies.DependencyContext attribute) +
    • +
  • stall (coreblocks.peripherals.wishbone.WishboneInterface attribute)
  • start (coreblocks.lsu.pma.PMARegion attribute) @@ -3154,6 +3198,8 @@

    S

  • state_machine_request() (coreblocks.peripherals.axi_lite.AXILiteMaster method) +
    • +
  • stb (coreblocks.peripherals.wishbone.WishboneInterface attribute)
  • stop() (transactron.lib.metrics.LatencyMeasurer method)
    • @@ -3655,6 +3701,12 @@

    W

  • wait_until_done() (transactron.testing.testbenchio.TestbenchIO method)
  • WakeupSelect (class in coreblocks.scheduler.wakeup_select) +
    • +
  • wb (coreblocks.peripherals.wishbone.PipelinedWishboneMaster attribute) +
    • +
  • wb_master (coreblocks.peripherals.wishbone.WishboneMaster attribute) +
    • +
  • we (coreblocks.peripherals.wishbone.WishboneInterface attribute)
  • WFI (coreblocks.params.isa.Funct12 attribute) @@ -3666,12 +3718,10 @@

    W

  • WishboneArbiter (class in coreblocks.peripherals.wishbone)
    • -
  • WishboneBus (class in coreblocks.peripherals.wishbone) +
  • WishboneInterface (class in coreblocks.peripherals.wishbone)