From d0fc018fecf396d18148a54d742885c6fea0e03b Mon Sep 17 00:00:00 2001 From: tilk Date: Mon, 15 Apr 2024 12:31:09 +0000 Subject: [PATCH] Move tests after #620 (#644) --- .doctrees/api.doctree | Bin 21256 -> 21256 bytes .doctrees/auto_graph.doctree | Bin 62318 -> 62324 bytes .doctrees/current-graph.doctree | Bin 63539 -> 63545 bytes .doctrees/environment.pickle | Bin 515040 -> 515040 bytes _sources/auto_graph.rst.txt | 454 ++++++++--------- api.html | 2 +- assumptions.html | 2 +- auto_graph.html | 456 +++++++++--------- components/icache.html | 2 +- coreblocks.backend.html | 2 +- coreblocks.cache.html | 2 +- coreblocks.core_structs.html | 2 +- coreblocks.frontend.decoder.html | 2 +- coreblocks.frontend.fetch.html | 2 +- coreblocks.frontend.html | 2 +- coreblocks.func_blocks.fu.html | 2 +- coreblocks.func_blocks.fu.lsu.html | 2 +- ...unc_blocks.fu.unsigned_multiplication.html | 2 +- coreblocks.func_blocks.html | 2 +- coreblocks.func_blocks.interface.html | 2 +- coreblocks.html | 2 +- coreblocks.params.html | 2 +- coreblocks.peripherals.html | 2 +- coreblocks.priv.csr.html | 2 +- coreblocks.priv.html | 2 +- coreblocks.priv.traps.html | 2 +- coreblocks.scheduler.html | 2 +- current-graph.html | 456 +++++++++--------- development-environment.html | 2 +- genindex.html | 2 +- home.html | 2 +- index.html | 2 +- miscellany/exceptions-summary.html | 2 +- modules-coreblocks.html | 2 +- modules-transactron.html | 2 +- problem-checklist.html | 2 +- py-modindex.html | 2 +- scheduler/overview.html | 2 +- search.html | 2 +- shared-structs/implementation/rs-impl.html | 2 +- shared-structs/rs.html | 2 +- synthesis/synthesis.html | 2 +- transactions.html | 2 +- transactron.core.html | 2 +- transactron.html | 2 +- transactron.lib.html | 2 +- transactron.testing.html | 2 +- transactron.utils.amaranth_ext.html | 2 +- transactron.utils.html | 2 +- 49 files changed, 725 insertions(+), 725 deletions(-) diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index fb57eb1fa91dfa06716182856cf6a1a435c59778..9cbcae6bad2f64a630b9ce79b87ce62396dd1039 100644 GIT binary patch delta 504 zcmYjOJx|;~5S0ZqK#{vse0L&3d{h+YBN5_kauTAVg&qWZ>jAIM-Zi^xCsedZ*(RAS zQl+Fq2#Mc8LqX3!;2*%6kKk@T-n@D9=KR7tzwoZ_*E{VPN=QYX0oOg?C6j_zF`h(i zyo;Ln5VpJ)?hae{wBE%|_+_)HXaaGOg6xYDWXa%%H7#|@bpnd1{{P5TsgN*A1s$v4 z$T4f+F+N6f=tT<%;Q}s3%UcaC30H(_2M7wyQf1Bb$DlPcHGnmZk5-TqNiv1u#)@w~ z*Xxp%ft$+l*Px4Q;S&Cf=5ckfb~c%a44kkUWuQT6#*eLO*C?v+KxtV}?exqLrHU-q zOmLSqaw$eBWIbmD9j8obYi8dWUm>5~)9R>-%O?A#OYz&FGhvO7Uk5(^4wrYDwUr}6 z$Ic*YrWlXmr`w|vA|dX*$>__<8B%C*aO`eNUcAV1!QH=9pHbrE+#GIPdQ;nHdslz4 RG5quPx|7JixgCD@p8@x@!x#Vn delta 473 zcmYk2u};EJ6o%7896*$&&{`IausBfSAZ-bQui$E8%=Pv{8|l5}-V4#yiJ_CHvm=WO z35l;@VvM8jV2p{6-~}RfJ30T!`TqZ(&a~-Fn}2j_g@^{^HVZG)A{t9}HQ*=-!SPHu zb1l1u87J36hHr$E@Mz*lC5tRQfp@nKP2Yw`*VJ_pB2I#qkbI1#Xmgl*HeC31&4BZs zQO!~vvp8XtP^Cr~;gG;?*E-z_Sxi>yKLv3VD}tRP_c^1I(7@>vi9>ktn&lm3gbIXZ z#HfHT_h_f|w^7IN?Kj}wuWF|9X&z*0CHHNG&(h*%1+Q)c%3fpN3dn>ESrRLsEkY-e zdbONkJH&>#qcS8S679{DrF$F1y1gtdAtAgdGxr2m~;J02*YCh^QYV6P+NOkpdUS_(mCpkP{%4Rl}&*XZKaAGb!t!N%(SEPzK8MY%X^DozqXe574^L3#z6`h4MJ4&!jbWw6q`7+=BcB&jClTXC zxC7nKn@J&0pvPg36B5z=m-P7px zqE0SWOZ@PR&%@2_Jj|B(!mLoBvBHHuE=l3w<^gXkm1V=tS&vTXPPEISEm4u{9E%QT zfA;Ltg(85+6DYwP5C{NCj?WV>i^m;7}8j(92;(i`M5F3u@6Y`jus3{kkz zKPx31sNNSK)nf}r+~b+dFFJ|nE{_Th)_JR;Gw_i}Rwg-_w-_hAH{iIBKL)%daPz4_ zqfv?%OQiI$&)+Dxn1T_vREiURLF9lt`S~N(e;P7W_feq!H+HF|z!FuRL;`Q66lKvO zddu{B3JC!-Y)m*2+5YV5fL>e(+=7i74OVMhVbsK8U!aBrR?;n+N**$`YWA?NHi*!0 z0$HKaP=*@mw?pMZI2u+VE87tbk!#rWs|+FVjEcZjg9cS(eQub6!-h~?i_&31R4|&z zFDP1r|3rn_N-K-L$;C#a7CPf>y3x3wgYq~nG;y({4*H|G5egr+@bL$u23r#nnc75& zDJV?S+DclKs6~azo82>M-%r$WkYXA$keRe}g(-)^XQ^R$I@g6nGax2qHkwk#j5ZLt z!jw*X&09)=JAW=Q&cN%bbD_H}Le~7dVvlGO+&^5|V}!e4Vjp-K{9bxtzdL@#r?IY?ff z1WjHz%9k%h*D@n!t%xA92u{llXj>l1G*;D$1K68u0zY>n)1GEV3RVKeIxO%-02UVKJY=)~{t~DG7mUs~8uG9kHe)kTnQjD5Ckl+s}hf zsSoQ-RI0%6x)_w+lHue!#z;X*q?eVhpzyM6E}F_RY18^T4mMX1Uf*=YwDVH@vM1Ui zlS!|Nq#G-qaA2;|vf!SoRCfG*s{6%A_EM8M<>TkA?C3GBSN@3@Z{9XK_vPChuwWab zQ`28;`+*PhcYGA?OdzWOemmpw(T+;`=*}Vv#@(atIb>yCm(9CH6rSucu`##qDPlp> zJ8fK?qCIeEe;l55I3je1*y2iJlU?Ua(F}P+MP*4*`TF&1s|$+CHx%m%(o3peD=*He zd?Tx}ym(_#b>8%e7T8S&;Q8@Vsso62Dg>sm=)5U?AxRCzRECVkB3_ z+R6qs_)G08mhgP8K5shIJ6zdHdHek*q@n-KH1q|QG$L@QE`_8b=jw>d#l3P$hrs$* zs0d`%EAei z8M}x)(Bw{c9y9W2hm&qx%7COZessdAT|7j$y5P-IQVg|DBdZg*Eor#Y>`bp}X{N|k z&crXDmSbqp9qn`_7PYwG*_lz}{}`Uzn+%UFIwxlgpWB4CxnaA&*Pvv z_bPi?o#z59X#Tl0DBFrGs0cUOye*n{+5*XideFQt0vt%`!Ix%J5p>}tF-6i%Xb+8zRJyAA8}mTh6HIh~-3zaa60skq!|CJ8XwI`l(>%q$??fy6lBr zU)qdG8siZG+3Sd%{&Ird?T+mPL_9{KzG+(jLdpsiKWoIYlAiaG$ms!0#g6!P?>tiKx@#L#0 zJ8WzxAR0F;xXRE|aMix-v7LZu)bPC)PHcRxdE(49`&7mw_NAtG2HM4BN*Y5(OHA(+ z;)6~mb_=o9J@kU^x+89nyP}Zmb1-nt4HaMV>Fw7;xHx-9NV-6c#g`STiEqfnR|aQq z&6vV)@;ks9-s*~kQ!C=fbBvqv#5nfRCP0bfvPDUNr|b?Orf^Ew>vM0cT2> zPo~nR-`cF?E^IQR`DcH$#jU_j=7ZPmh4g^{o33Uc(k>MFEU>XW*w4bUyRPI@QfQ$| zh}ywMMkd}DeDj8dm^)B+xDzW4TJMjNRq{xNf^WB3EdTrM7=;W~J%qYdBUU16N8&7$ z-0Suteo3cVN$W{QaF6x1tnHSglqbTAo?v{~Gt(|(3pq@}))^AO^}$SAfjJMBTI4bP zqX&y7Vb#N9gtZNaOz5u3b71YR>A2bD>Nma@Cs`xwmKXfG2l2lVhSETs9}>bT&mAR? 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zDWx1xt^!JW2WWgq%?Ehm5DuEFNv>A20A^Hk+SO{9XEj9}#_?t~EkCSI z0QlyxS_Uxxh`Lu{KMY!mn~eteY4lb{ktUx%h)r|jn|NBin%;O*T>udN4&K|C`W7A+ zXVdz(uxn@27jMCY*%bLU-UZ60$KO_GDD1aI?Ia}$MBR!;hI(W<3R7p(#iMwHkj>PT~YLkNTWM);5nG zKZz-uNB2*vqXjd5a-y@LF6ExW;O5csQ|cms{-@Q)0Ny?ggU+K4XOLFTqlIVSQ1j^6 z8Fh?kiZrc?6I@$<(a z0?|xIG#7|g46zbJF}D_oP=?@tQ7%j%B6UPNf#|3sItfH)9nodvBZaKrXolf`*DXe{ z#4`k2GUo0Ak*Fhj3Pc|r(N`dnbVRa14A2n+1!9Pf7%C7W018DnBLyZ+XBi_9;~0Yf zb-D2Zk)b0d3B*)}n9Ni)3q&SEuqA2E5{MZ(Vx~aM(Gj^L3%TL*bj&=#QlKLi2*g4i zu}C16>WF0mQKBPO2*fHKQ6>;;bi`VLSkLS){t{k=z&ycN_#edEAP^gM#3q5*q9dLb zi05>~^8&F|N4z8u+ZlqbY4Z+&*rg+0DHNF9I%bbR?9~x(2*d#$aZn%*>xd%)@wSdQ zDiFtY#Jd7;!ir_2Z8uWN8A;NUv$KMfsjUN{mLj|U72)*A`s3x!bKq5 z3mJw5E3=2dcjR45F>QNNP$Sx5n}{moQ@bT5E(Xv=OgAx0yC9ksK BasicFifo2_write - Retirement_Retirement --> BasicFifo2_write - TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write - TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write + Retirement_Retirement2 --> BasicFifo2_write + TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write + TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write FIFO5_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write RegisterFile_perf --> HwExpHistogram2__add ReorderBuffer_perf --> HwExpHistogram4__add - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request - WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMasterAdapter_request_read + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Serializer_Serializer + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> BasicFifo_write + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMaster_request + WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller + Serializer_Serializer1 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller + BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller + WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller + Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Forwarder2_write ICache_ICache <--> HwCounter4__incr ArgumentsToResultsZipper_peek_arg --> ICache_MemRead BasicFifo3_peek --> ICache_MemRead @@ -756,16 +756,16 @@ FIFO11_read --> RegAllocation_RegAllocation BasicFifo2_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO12_write - FIFO13_read --> RSSelection_RSSelection FIFO13_read --> RSSelection_RSSelection2 + FIFO13_read --> RSSelection_RSSelection FIFO13_read --> RSSelection_RSSelection1 - RSFuncBlock_select --> RSSelection_RSSelection - RS_select --> RSSelection_RSSelection - RSSelection_RSSelection --> FIFO14_write + RSFuncBlock_select --> RSSelection_RSSelection2 + RS_select --> RSSelection_RSSelection2 RSSelection_RSSelection2 --> FIFO14_write + RSSelection_RSSelection --> FIFO14_write RSSelection_RSSelection1 --> FIFO14_write - RSFuncBlock1_select --> RSSelection_RSSelection2 - FifoRS_select --> RSSelection_RSSelection2 + RSFuncBlock1_select --> RSSelection_RSSelection + FifoRS_select --> RSSelection_RSSelection RSSelection_RSSelection1 <--> CSRUnit_select FIFO14_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion @@ -788,7 +788,7 @@ Collector3_method --> ConnectTrans13_ConnectTrans Forwarder8_read --> ConnectTrans13_ConnectTrans ConnectTrans13_ConnectTrans --> FetchUnit_resume - Retirement_Retirement4 --> FetchUnit_resume + Retirement_Retirement --> FetchUnit_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -802,7 +802,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add - RS_RS2 --> WakeupSelect_WakeupSelect + RS_RS4 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -826,10 +826,10 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter1__incr WakeupSelect_WakeupSelect --> FIFO3_write - RS_RS --> WakeupSelect1_WakeupSelect + RS_RS1 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO4_write - RS_RS3 --> WakeupSelect2_WakeupSelect + RS_RS --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> TaggedCounter2__incr WakeupSelect2_WakeupSelect <--> HwCounter7__incr @@ -838,15 +838,15 @@ WakeupSelect3_WakeupSelect --> BasicFifo5_write ConnectTrans9_ConnectTrans --> BasicFifo5_write ConnectTrans4_ConnectTrans --> BasicFifo5_write - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo5_write - TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> BasicFifo5_write TransactionManager_ConnectTrans_accept_cond1 --> BasicFifo5_write + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo5_write + TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> BasicFifo5_write WakeupSelect2_WakeupSelect --> FIFO6_write WakeupSelect2_WakeupSelect --> FIFO5_write - RS_RS1 --> WakeupSelect3_WakeupSelect + RS_RS3 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO7_write - RS_RS4 --> WakeupSelect4_WakeupSelect + RS_RS2 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans5_ConnectTrans --> Forwarder5_write ConnectTrans6_ConnectTrans --> Forwarder5_write @@ -866,19 +866,19 @@ ConnectTrans9_ConnectTrans --> BasicFifo6_write FifoRS_perf --> HwExpHistogram8__add Forwarder6_read --> LSUDummy_LSUDummy1 - Forwarder6_read --> TransactionManager_issue_cond1_LSUDummy Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 - Forwarder6_read --> TransactionManager_issue_cond0_LSUDummy + Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 + Forwarder6_read --> TransactionManager_issue_cond1_LSUDummy LSUDummy_LSUDummy1 --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write - TransactionManager_issue_cond1_LSUDummy --> FIFO8_write TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write - TransactionManager_issue_cond0_LSUDummy --> FIFO8_write + TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write + TransactionManager_issue_cond1_LSUDummy --> FIFO8_write LSUDummy_LSUDummy1 --> FIFO10_write WakeupSelect5_WakeupSelect --> FIFO10_write - TransactionManager_issue_cond1_LSUDummy --> FIFO10_write TransactionManager_LSUDummy_issue_cond2 --> FIFO10_write - TransactionManager_issue_cond0_LSUDummy --> FIFO10_write + TransactionManager_LSUDummy_issue_cond0 --> FIFO10_write + TransactionManager_issue_cond1_LSUDummy --> FIFO10_write FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop @@ -923,55 +923,55 @@ Collector2_method --> ConnectTrans3_ConnectTrans Forwarder7_read --> ConnectTrans3_ConnectTrans CSRUnit_get_result --> ConnectTrans4_ConnectTrans - MethodTryProduct_MethodTryProduct2 --> LSUDummy_precommit - MethodTryProduct_MethodTryProduct --> CSRUnit_precommit + MethodTryProduct_MethodTryProduct1 --> LSUDummy_precommit + MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit ConnectTrans11_ConnectTrans --> Forwarder8_write ConnectTrans12_ConnectTrans --> Forwarder8_write BasicFifo6_read --> ConnectTrans11_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans12_ConnectTrans + ReorderBuffer_peek --> Retirement_Retirement4 + ReorderBuffer_peek --> Retirement_Retirement3 ReorderBuffer_peek --> Retirement_Retirement2 - ReorderBuffer_peek --> Retirement_Retirement1 - ReorderBuffer_peek --> Retirement_Retirement - ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement - ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement2 --> MethodTryProduct_method - ExceptionCauseRegister_get --> Retirement_Retirement1 - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement <--> ReorderBuffer_retire - TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire - TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire - Retirement_Retirement <--> FIFOLatencyMeasurer1__stop - TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer1__stop - TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer1__stop - FIFO2_read --> Retirement_Retirement - FIFO2_read --> TransactionManager_Retirement_cond1_Retirement - FIFO2_read --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement --> HwExpHistogram3__add - TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram3__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram3__add - CoreInstructionCounter_decrement --> Retirement_Retirement - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement - RRAT_peek --> Retirement_Retirement - RRAT_peek --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement --> RegisterFile_free - TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free - TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free - Retirement_Retirement --> TaggedLatencyMeasurer__stop - TransactionManager_Retirement_cond1_Retirement --> TaggedLatencyMeasurer__stop - TransactionManager_Retirement_cond0_Retirement --> TaggedLatencyMeasurer__stop - AsyncMemoryBank_read --> Retirement_Retirement - AsyncMemoryBank_read --> TransactionManager_Retirement_cond1_Retirement - AsyncMemoryBank_read --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement --> HwExpHistogram1__add - TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add - Retirement_Retirement --> FRAT_rename - TransactionManager_Retirement_cond1_Retirement --> FRAT_rename + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement4 --> MethodTryProduct_method + ExceptionCauseRegister_get --> Retirement_Retirement3 + ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 + ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement2 <--> ReorderBuffer_retire + TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire + TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire + Retirement_Retirement2 <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop + FIFO2_read --> Retirement_Retirement2 + FIFO2_read --> TransactionManager_Retirement_Retirement_cond1 + FIFO2_read --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement2 --> HwExpHistogram3__add + TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add + CoreInstructionCounter_decrement --> Retirement_Retirement2 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 + RRAT_peek --> Retirement_Retirement2 + RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement2 --> RegisterFile_free + TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free + TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free + Retirement_Retirement2 --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop + AsyncMemoryBank_read --> Retirement_Retirement2 + AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1 + AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement2 --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add + Retirement_Retirement2 --> FRAT_rename TransactionManager_ROBAllocation_Renaming --> FRAT_rename - CSRRegister1_read --> Retirement_Retirement4 - Retirement_Retirement4 <--> ExceptionCauseRegister_clear + TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename + CSRRegister1_read --> Retirement_Retirement + Retirement_Retirement <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -983,78 +983,17 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt - TransactionManager_MethodTryProduct_precommit_cond1 <--> MethodTryProduct_MethodTryProduct1 - TransactionManager_MethodTryProduct_precommit_cond2 <--> MethodTryProduct_MethodTryProduct1 - TransactionManager_MethodTryProduct_precommit_cond0 <--> MethodTryProduct_MethodTryProduct1 - TransactionManager_MethodTryProduct_precommit_cond1 --> PrivilegedFuncUnit_precommit + TransactionManager_MethodTryProduct_precommit_cond2 <--> MethodTryProduct_MethodTryProduct + TransactionManager_precommit_cond0_MethodTryProduct <--> MethodTryProduct_MethodTryProduct + TransactionManager_precommit_cond1_MethodTryProduct <--> MethodTryProduct_MethodTryProduct TransactionManager_MethodTryProduct_precommit_cond2 --> PrivilegedFuncUnit_precommit - TransactionManager_MethodTryProduct_precommit_cond0 --> PrivilegedFuncUnit_precommit - TransactionManager_MethodTryProduct_precommit_cond1 --> TaggedCounter3__incr + TransactionManager_precommit_cond0_MethodTryProduct --> PrivilegedFuncUnit_precommit + TransactionManager_precommit_cond1_MethodTryProduct --> PrivilegedFuncUnit_precommit TransactionManager_MethodTryProduct_precommit_cond2 --> TaggedCounter3__incr - TransactionManager_MethodTryProduct_precommit_cond0 --> TaggedCounter3__incr - TransactionManager_MethodTryProduct_precommit_cond1 <--> PrivilegedFuncUnit_precommit_cond1 - TransactionManager_MethodTryProduct_precommit_cond1 <--> InterruptController_mret - TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 - TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read - TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer - TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write - TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write - TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request - TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request - TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy - TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy - TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy - TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue - TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue - TransactionManager_issue_cond1_LSUDummy --> FIFO9_write - TransactionManager_LSUDummy_issue_cond2 --> FIFO9_write - TransactionManager_issue_cond0_LSUDummy --> FIFO9_write + TransactionManager_precommit_cond0_MethodTryProduct --> TaggedCounter3__incr + TransactionManager_precommit_cond1_MethodTryProduct --> TaggedCounter3__incr TransactionManager_MethodTryProduct_precommit_cond2 <--> PrivilegedFuncUnit_precommit_cond2 TransactionManager_MethodTryProduct_precommit_cond2 <--> ICache_flush - TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3 - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement3 - TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write - TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry - TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry - TransactionManager_MethodTryProduct_precommit_cond0 <--> PrivilegedFuncUnit_precommit_cond0 - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 - TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - FIFO9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - FIFO9_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans - TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write - TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> Forwarder7_write - TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write - LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - Serializer1_Serializer2 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - Forwarder1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_cond0_Retirement --> RRAT_commit - TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment - CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write - CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write - TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation Connect_read --> TransactionManager_ROBAllocation_Renaming TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put @@ -1064,12 +1003,73 @@ TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming FIFO12_read --> TransactionManager_ROBAllocation_Renaming TransactionManager_ROBAllocation_Renaming --> Connect_write - TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - Serializer1_Serializer1 --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 - TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write - TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3 + TransactionManager_precommit_cond0_MethodTryProduct <--> PrivilegedFuncUnit_precommit_cond0 + TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans + TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans + TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write + TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> Forwarder7_write + LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 + LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1 FIFO8_read --> TransactionManager_ConnectTrans_accept_cond1 FIFO10_read --> TransactionManager_ConnectTrans_accept_cond1 + TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy + TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy + TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy + TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue + TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond2 --> FIFO9_write + TransactionManager_LSUDummy_issue_cond0 --> FIFO9_write + TransactionManager_issue_cond1_LSUDummy --> FIFO9_write + TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1 + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement1 + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write + TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 + TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond0 + LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + FIFO9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + FIFO9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + Serializer1_Serializer --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 + TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write + TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 + TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write + TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write + TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request + TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit + TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment + CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write + CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr + TransactionManager_precommit_cond1_MethodTryProduct <--> PrivilegedFuncUnit_precommit_cond1 + TransactionManager_precommit_cond1_MethodTryProduct <--> InterruptController_mret + TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 + TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read + TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3 + TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + Serializer1_Serializer2 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 diff --git a/api.html b/api.html index 2e43cb783..ff16140c2 100644 --- a/api.html +++ b/api.html @@ -259,7 +259,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 18:05 2024-04-14. + Last updated on 12:31 2024-04-15.

diff --git a/assumptions.html b/assumptions.html index dc9019150..4b65ca310 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 18:05 2024-04-14. + Last updated on 12:31 2024-04-15.

diff --git a/auto_graph.html b/auto_graph.html index aa750f29f..5eeab28f4 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -86,8 +86,8 @@ Core_DiscardBranchVerify["DiscardBranchVerify"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_request["request"] + WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_result["result"] subgraph Forwarder["result Forwarder"] Forwarder_write["write"] @@ -96,16 +96,16 @@ end subgraph WishboneMaster1["wb_master_data WishboneMaster"] WishboneMaster1_WishboneMaster["WishboneMaster"] - WishboneMaster1_request["request"] WishboneMaster1_result["result"] + WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] Forwarder1_read["read"] Forwarder1_write["write"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_get_read_response["get_read_response"] WishboneMasterAdapter_request_read["request_read"] + WishboneMasterAdapter_get_read_response["get_read_response"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] @@ -116,8 +116,8 @@ end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] - WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_get_read_response["get_read_response"] + WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_read["request_read"] WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] @@ -136,8 +136,8 @@ CoreInstructionCounter_increment["increment"] end subgraph FIFO["fifo_fetch FIFO"] - FIFO_read["read"] FIFO_write["write"] + FIFO_read["read"] end subgraph MethodMap["core_counter_increment_discard_map MethodMap"] MethodMap_method["method"] @@ -150,22 +150,22 @@ BasicFifo2_write["write"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_read["read"] Forwarder2_write["write"] + Forwarder2_read["read"] end end subgraph ICache["icache ICache"] - ICache_ICache["ICache"] + ICache_issue_req["issue_req"] + ICache_flush["flush"] ICache_MemRead["MemRead"] ICache_accept_res["accept_res"] + ICache_ICache["ICache"] ICache_ICache1["ICache"] - ICache_flush["flush"] - ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -182,8 +182,8 @@ HwCounter4__incr["_incr"] end subgraph FIFOLatencyMeasurer["req_latency FIFOLatencyMeasurer"] - FIFOLatencyMeasurer__stop["_stop"] FIFOLatencyMeasurer__start["_start"] + FIFOLatencyMeasurer__stop["_stop"] subgraph HwExpHistogram["histogram HwExpHistogram"] HwExpHistogram__add["_add"] end @@ -194,9 +194,9 @@ end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] ArgumentsToResultsZipper_peek_arg["peek_arg"] - ArgumentsToResultsZipper_read["read"] ArgumentsToResultsZipper_write_args["write_args"] ArgumentsToResultsZipper_write_results["write_results"] + ArgumentsToResultsZipper_read["read"] subgraph BasicFifo3["fifo BasicFifo"] BasicFifo3_read["read"] BasicFifo3_peek["peek"] @@ -212,15 +212,15 @@ FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_peek["peek"] RRAT_commit["commit"] + RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] RegisterFile_perf["perf"] + RegisterFile_read2["read2"] RegisterFile_free["free"] RegisterFile_read1["read1"] RegisterFile_write["write"] - RegisterFile_read2["read2"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer__start["_start"] TaggedLatencyMeasurer__stop["_stop"] @@ -228,8 +228,8 @@ HwExpHistogram1__add["_add"] end subgraph AsyncMemoryBank["slots AsyncMemoryBank"] - AsyncMemoryBank_write["write"] AsyncMemoryBank_read["read"] + AsyncMemoryBank_write["write"] end end subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] @@ -237,12 +237,12 @@ end end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_perf["perf"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_put["put"] ReorderBuffer_peek["peek"] ReorderBuffer_retire["retire"] ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_perf["perf"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] FIFOLatencyMeasurer1__start["_start"] FIFOLatencyMeasurer1__stop["_stop"] @@ -250,8 +250,8 @@ HwExpHistogram3__add["_add"] end subgraph FIFO2["fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end end subgraph HwExpHistogram4["perf_rob_size HwExpHistogram"] @@ -259,11 +259,11 @@ end end subgraph FetchUnit["fetch FetchUnit"] - FetchUnit_Fetch_Stage1["Fetch_Stage1"] FetchUnit_resume["resume"] FetchUnit_stall_exception["stall_exception"] - FetchUnit_Fetch_Stage2["Fetch_Stage2"] FetchUnit_Fetch_Stage0["Fetch_Stage0"] + FetchUnit_Fetch_Stage2["Fetch_Stage2"] + FetchUnit_Fetch_Stage1["Fetch_Stage1"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] end @@ -287,13 +287,13 @@ Semaphore_release["release"] end subgraph Pipe["s1_s2_pipe Pipe"] - Pipe_write["write"] Pipe_read["read"] + Pipe_write["write"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_clear["clear"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_clear["clear"] ExceptionCauseRegister_report["report"] subgraph BasicFifo5["fu_report_fifo BasicFifo"] BasicFifo5_read["read"] @@ -326,21 +326,21 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_select["select"] - RSFuncBlock_get_result["get_result"] RSFuncBlock_insert["insert"] RSFuncBlock_update["update"] + RSFuncBlock_select["select"] + RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] - RS_perf["perf"] + RS_insert["insert"] RS_RS["RS"] + RS_update["update"] RS_RS1["RS"] - RS_insert["insert"] + RS_perf["perf"] + RS_select["select"] RS_RS2["RS"] - RS_update["update"] RS_RS3["RS"] - RS_select["select"] - RS_take["take"] RS_RS4["RS"] + RS_take["take"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer1__stop["_stop"] TaggedLatencyMeasurer1__start["_start"] @@ -357,8 +357,8 @@ end end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph TaggedCounter1["perf_instr TaggedCounter"] TaggedCounter1__incr["_incr"] end @@ -371,8 +371,8 @@ WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO4["fifo FIFO"] FIFO4_write["write"] FIFO4_read["read"] @@ -382,11 +382,11 @@ WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO5["fifo_branch_resolved FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end subgraph TaggedCounter2["perf_instr TaggedCounter"] TaggedCounter2__incr["_incr"] @@ -398,19 +398,19 @@ HwCounter7__incr["_incr"] end subgraph FIFO6["fifo_res FIFO"] - FIFO6_read["read"] FIFO6_write["write"] + FIFO6_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] + ExceptionFuncUnit_issue["issue"] subgraph FIFO7["fifo FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -418,14 +418,14 @@ end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] PrivilegedFuncUnit_issue["issue"] - PrivilegedFuncUnit_precommit_cond2["precommit_cond2"] - PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_precommit_cond0["precommit_cond0"] + PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_precommit_cond2["precommit_cond2"] PrivilegedFuncUnit_precommit["precommit"] PrivilegedFuncUnit_precommit_cond1["precommit_cond1"] subgraph BasicFifo6["fetch_resume_fifo BasicFifo"] - BasicFifo6_read["read"] BasicFifo6_write["write"] + BasicFifo6_read["read"] end subgraph TaggedCounter3["perf_instr TaggedCounter"] TaggedCounter3__incr["_incr"] @@ -437,8 +437,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_read["read"] Forwarder5_write["write"] + Forwarder5_read["read"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans5["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -462,18 +462,18 @@ subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] RSFuncBlock1_select["select"] RSFuncBlock1_insert["insert"] - RSFuncBlock1_get_result["get_result"] RSFuncBlock1_update["update"] + RSFuncBlock1_get_result["get_result"] subgraph FifoRS["rs FifoRS"] FifoRS_update["update"] FifoRS_select["select"] - FifoRS_FifoRS["FifoRS"] + FifoRS_insert["insert"] FifoRS_take["take"] FifoRS_perf["perf"] - FifoRS_insert["insert"] + FifoRS_FifoRS["FifoRS"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer2__start["_start"] TaggedLatencyMeasurer2__stop["_stop"] + TaggedLatencyMeasurer2__start["_start"] subgraph HwExpHistogram7["histogram HwExpHistogram"] HwExpHistogram7__add["_add"] end @@ -487,33 +487,33 @@ end end subgraph LSUDummy["func_unit_0 LSUDummy"] - LSUDummy_LSUDummy["LSUDummy"] - LSUDummy_issue["issue"] LSUDummy_accept["accept"] - LSUDummy_accept_cond1["accept_cond1"] - LSUDummy_precommit["precommit"] LSUDummy_accept_cond0["accept_cond0"] + LSUDummy_accept_cond1["accept_cond1"] + LSUDummy_LSUDummy["LSUDummy"] LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_issue["issue"] + LSUDummy_precommit["precommit"] subgraph LSURequester["requester LSURequester"] LSURequester_accept["accept"] + LSURequester_issue_cond0["issue_cond0"] LSURequester_issue["issue"] LSURequester_issue_cond1["issue_cond1"] - LSURequester_issue_cond0["issue_cond0"] LSURequester_accept_cond1["accept_cond1"] - LSURequester_accept_cond0["accept_cond0"] LSURequester_issue_cond2["issue_cond2"] + LSURequester_accept_cond0["accept_cond0"] end subgraph Forwarder6["requests Forwarder"] - Forwarder6_read["read"] Forwarder6_write["write"] + Forwarder6_read["read"] end subgraph FIFO8["results_noop FIFO"] FIFO8_read["read"] FIFO8_write["write"] end subgraph FIFO9["issued FIFO"] - FIFO9_write["write"] FIFO9_read["read"] + FIFO9_write["write"] end subgraph FIFO10["issued_noop FIFO"] FIFO10_read["read"] @@ -538,18 +538,18 @@ end subgraph CSRUnit["rs_block_2 CSRUnit"] CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_get_result["get_result"] CSRUnit_insert["insert"] - CSRUnit_select["select"] CSRUnit_update["update"] - CSRUnit_fetch_resume["fetch_resume"] CSRUnit_precommit["precommit"] - CSRUnit_get_result["get_result"] + CSRUnit_select["select"] + CSRUnit_fetch_resume["fetch_resume"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] MethodTryProduct_MethodTryProduct1["MethodTryProduct"] - MethodTryProduct_method["method"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] + MethodTryProduct_method["method"] end subgraph Collector3["FetchResumeKey_unifier Collector"] Collector3_method["method"] @@ -571,16 +571,16 @@ ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"] end subgraph InterruptController["interrupt_controller InterruptController"] - InterruptController_report_interrupt["report_interrupt"] - InterruptController_entry["entry"] InterruptController_mret["mret"] + InterruptController_entry["entry"] + InterruptController_report_interrupt["report_interrupt"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] - CSRRegister__internal_fu_read["_internal_fu_read"] CSRRegister__internal_fu_write["_internal_fu_write"] + CSRRegister__internal_fu_read["_internal_fu_read"] CSRRegister_write["write"] subgraph MethodMap1["fu_write_map MethodMap"] MethodMap1_method["method"] @@ -593,9 +593,9 @@ end end subgraph CSRRegister1["mtvec CSRRegister"] + CSRRegister1_read["read"] CSRRegister1__internal_fu_read["_internal_fu_read"] CSRRegister1__internal_fu_write["_internal_fu_write"] - CSRRegister1_read["read"] subgraph MethodMap3["fu_write_map MethodMap"] MethodMap3_method["method"] end @@ -609,8 +609,8 @@ subgraph CSRRegister2["mepc CSRRegister"] CSRRegister2__internal_fu_read["_internal_fu_read"] CSRRegister2_read["read"] - CSRRegister2__internal_fu_write["_internal_fu_write"] CSRRegister2_write["write"] + CSRRegister2__internal_fu_write["_internal_fu_write"] subgraph MethodMap5["fu_write_map MethodMap"] MethodMap5_method["method"] end @@ -662,8 +662,8 @@ end end subgraph FIFO11["fifo_decode FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -680,8 +680,8 @@ RegAllocation_RegAllocation["RegAllocation"] end subgraph Connect["rename_out_buf Connect"] - Connect_read["read"] Connect_write["write"] + Connect_read["read"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] @@ -713,25 +713,25 @@ Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] Retirement_Retirement1["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement4["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] CSRRegister7__internal_fu_read["_internal_fu_read"] - CSRRegister7_read["read"] CSRRegister7_write["write"] + CSRRegister7_read["read"] subgraph MethodMap16["fu_read_map MethodMap"] MethodMap16_method["method"] end end subgraph CSRRegister8["register_high CSRRegister"] + CSRRegister8__internal_fu_read["_internal_fu_read"] CSRRegister8_read["read"] CSRRegister8_write["write"] - CSRRegister8__internal_fu_read["_internal_fu_read"] subgraph MethodMap18["fu_read_map MethodMap"] MethodMap18_method["method"] end @@ -754,39 +754,39 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_MethodTryProduct_precommit_cond0["MethodTryProduct_precommit_cond0"] - TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_ConnectTrans_accept_cond1["ConnectTrans_accept_cond1"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_precommit_cond0_MethodTryProduct["precommit_cond0_MethodTryProduct"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] + TransactionManager_accept_cond0_ConnectTrans_accept_cond1["accept_cond0_ConnectTrans_accept_cond1"] + TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"] + TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_precommit_cond1_MethodTryProduct["precommit_cond1_MethodTryProduct"] TransactionManager_MethodTryProduct_precommit_cond2["MethodTryProduct_precommit_cond2"] - TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] - TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_MethodTryProduct_precommit_cond1["MethodTryProduct_precommit_cond1"] - TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_ConnectTrans_accept_cond1["ConnectTrans_accept_cond1"] - TransactionManager_accept_cond0_accept_cond1_ConnectTrans["accept_cond0_accept_cond1_ConnectTrans"] + TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] end end Core_InitFreeRFFifo --> BasicFifo2_write -Retirement_Retirement --> BasicFifo2_write -TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write -TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write +Retirement_Retirement2 --> BasicFifo2_write +TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write +TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write FIFO5_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write RegisterFile_perf --> HwExpHistogram2__add ReorderBuffer_perf --> HwExpHistogram4__add -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request -WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMasterAdapter_request_read +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Serializer_Serializer +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> BasicFifo_write +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMaster_request +WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller +Serializer_Serializer1 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller +BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller +WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller +Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Forwarder2_write ICache_ICache <--> HwCounter4__incr ArgumentsToResultsZipper_peek_arg --> ICache_MemRead BasicFifo3_peek --> ICache_MemRead @@ -835,16 +835,16 @@ FIFO11_read --> RegAllocation_RegAllocation BasicFifo2_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO12_write -FIFO13_read --> RSSelection_RSSelection FIFO13_read --> RSSelection_RSSelection2 +FIFO13_read --> RSSelection_RSSelection FIFO13_read --> RSSelection_RSSelection1 -RSFuncBlock_select --> RSSelection_RSSelection -RS_select --> RSSelection_RSSelection -RSSelection_RSSelection --> FIFO14_write +RSFuncBlock_select --> RSSelection_RSSelection2 +RS_select --> RSSelection_RSSelection2 RSSelection_RSSelection2 --> FIFO14_write +RSSelection_RSSelection --> FIFO14_write RSSelection_RSSelection1 --> FIFO14_write -RSFuncBlock1_select --> RSSelection_RSSelection2 -FifoRS_select --> RSSelection_RSSelection2 +RSFuncBlock1_select --> RSSelection_RSSelection +FifoRS_select --> RSSelection_RSSelection RSSelection_RSSelection1 <--> CSRUnit_select FIFO14_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion @@ -867,7 +867,7 @@ Collector3_method --> ConnectTrans13_ConnectTrans Forwarder8_read --> ConnectTrans13_ConnectTrans ConnectTrans13_ConnectTrans --> FetchUnit_resume -Retirement_Retirement4 --> FetchUnit_resume +Retirement_Retirement --> FetchUnit_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -881,7 +881,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add -RS_RS2 --> WakeupSelect_WakeupSelect +RS_RS4 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -905,10 +905,10 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter1__incr WakeupSelect_WakeupSelect --> FIFO3_write -RS_RS --> WakeupSelect1_WakeupSelect +RS_RS1 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO4_write -RS_RS3 --> WakeupSelect2_WakeupSelect +RS_RS --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> TaggedCounter2__incr WakeupSelect2_WakeupSelect <--> HwCounter7__incr @@ -917,15 +917,15 @@ WakeupSelect3_WakeupSelect --> BasicFifo5_write ConnectTrans9_ConnectTrans --> BasicFifo5_write ConnectTrans4_ConnectTrans --> BasicFifo5_write -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo5_write -TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> BasicFifo5_write TransactionManager_ConnectTrans_accept_cond1 --> BasicFifo5_write +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo5_write +TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> BasicFifo5_write WakeupSelect2_WakeupSelect --> FIFO6_write WakeupSelect2_WakeupSelect --> FIFO5_write -RS_RS1 --> WakeupSelect3_WakeupSelect +RS_RS3 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO7_write -RS_RS4 --> WakeupSelect4_WakeupSelect +RS_RS2 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans5_ConnectTrans --> Forwarder5_write ConnectTrans6_ConnectTrans --> Forwarder5_write @@ -945,19 +945,19 @@ ConnectTrans9_ConnectTrans --> BasicFifo6_write FifoRS_perf --> HwExpHistogram8__add Forwarder6_read --> LSUDummy_LSUDummy1 -Forwarder6_read --> TransactionManager_issue_cond1_LSUDummy Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 -Forwarder6_read --> TransactionManager_issue_cond0_LSUDummy +Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 +Forwarder6_read --> TransactionManager_issue_cond1_LSUDummy LSUDummy_LSUDummy1 --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write -TransactionManager_issue_cond1_LSUDummy --> FIFO8_write TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write -TransactionManager_issue_cond0_LSUDummy --> FIFO8_write +TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write +TransactionManager_issue_cond1_LSUDummy --> FIFO8_write LSUDummy_LSUDummy1 --> FIFO10_write WakeupSelect5_WakeupSelect --> FIFO10_write -TransactionManager_issue_cond1_LSUDummy --> FIFO10_write TransactionManager_LSUDummy_issue_cond2 --> FIFO10_write -TransactionManager_issue_cond0_LSUDummy --> FIFO10_write +TransactionManager_LSUDummy_issue_cond0 --> FIFO10_write +TransactionManager_issue_cond1_LSUDummy --> FIFO10_write FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop @@ -1002,55 +1002,55 @@ Collector2_method --> ConnectTrans3_ConnectTrans Forwarder7_read --> ConnectTrans3_ConnectTrans CSRUnit_get_result --> ConnectTrans4_ConnectTrans -MethodTryProduct_MethodTryProduct2 --> LSUDummy_precommit -MethodTryProduct_MethodTryProduct --> CSRUnit_precommit +MethodTryProduct_MethodTryProduct1 --> LSUDummy_precommit +MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit ConnectTrans11_ConnectTrans --> Forwarder8_write ConnectTrans12_ConnectTrans --> Forwarder8_write BasicFifo6_read --> ConnectTrans11_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans12_ConnectTrans +ReorderBuffer_peek --> Retirement_Retirement4 +ReorderBuffer_peek --> Retirement_Retirement3 ReorderBuffer_peek --> Retirement_Retirement2 -ReorderBuffer_peek --> Retirement_Retirement1 -ReorderBuffer_peek --> Retirement_Retirement -ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement -ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement2 --> MethodTryProduct_method -ExceptionCauseRegister_get --> Retirement_Retirement1 -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement <--> ReorderBuffer_retire -TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire -TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire -Retirement_Retirement <--> FIFOLatencyMeasurer1__stop -TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer1__stop -TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer1__stop -FIFO2_read --> Retirement_Retirement -FIFO2_read --> TransactionManager_Retirement_cond1_Retirement -FIFO2_read --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement --> HwExpHistogram3__add -TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram3__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram3__add -CoreInstructionCounter_decrement --> Retirement_Retirement -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement -RRAT_peek --> Retirement_Retirement -RRAT_peek --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement --> RegisterFile_free -TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free -TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free -Retirement_Retirement --> TaggedLatencyMeasurer__stop -TransactionManager_Retirement_cond1_Retirement --> TaggedLatencyMeasurer__stop -TransactionManager_Retirement_cond0_Retirement --> TaggedLatencyMeasurer__stop -AsyncMemoryBank_read --> Retirement_Retirement -AsyncMemoryBank_read --> TransactionManager_Retirement_cond1_Retirement -AsyncMemoryBank_read --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement --> HwExpHistogram1__add -TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add -Retirement_Retirement --> FRAT_rename -TransactionManager_Retirement_cond1_Retirement --> FRAT_rename +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement4 --> MethodTryProduct_method +ExceptionCauseRegister_get --> Retirement_Retirement3 +ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 +ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement2 <--> ReorderBuffer_retire +TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire +TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire +Retirement_Retirement2 <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop +FIFO2_read --> Retirement_Retirement2 +FIFO2_read --> TransactionManager_Retirement_Retirement_cond1 +FIFO2_read --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement2 --> HwExpHistogram3__add +TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add +CoreInstructionCounter_decrement --> Retirement_Retirement2 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 +RRAT_peek --> Retirement_Retirement2 +RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement2 --> RegisterFile_free +TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free +TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free +Retirement_Retirement2 --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop +AsyncMemoryBank_read --> Retirement_Retirement2 +AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1 +AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement2 --> HwExpHistogram1__add +TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add +Retirement_Retirement2 --> FRAT_rename TransactionManager_ROBAllocation_Renaming --> FRAT_rename -CSRRegister1_read --> Retirement_Retirement4 -Retirement_Retirement4 <--> ExceptionCauseRegister_clear +TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename +CSRRegister1_read --> Retirement_Retirement +Retirement_Retirement <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -1062,78 +1062,17 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt -TransactionManager_MethodTryProduct_precommit_cond1 <--> MethodTryProduct_MethodTryProduct1 -TransactionManager_MethodTryProduct_precommit_cond2 <--> MethodTryProduct_MethodTryProduct1 -TransactionManager_MethodTryProduct_precommit_cond0 <--> MethodTryProduct_MethodTryProduct1 -TransactionManager_MethodTryProduct_precommit_cond1 --> PrivilegedFuncUnit_precommit +TransactionManager_MethodTryProduct_precommit_cond2 <--> MethodTryProduct_MethodTryProduct +TransactionManager_precommit_cond0_MethodTryProduct <--> MethodTryProduct_MethodTryProduct +TransactionManager_precommit_cond1_MethodTryProduct <--> MethodTryProduct_MethodTryProduct TransactionManager_MethodTryProduct_precommit_cond2 --> PrivilegedFuncUnit_precommit -TransactionManager_MethodTryProduct_precommit_cond0 --> PrivilegedFuncUnit_precommit -TransactionManager_MethodTryProduct_precommit_cond1 --> TaggedCounter3__incr +TransactionManager_precommit_cond0_MethodTryProduct --> PrivilegedFuncUnit_precommit +TransactionManager_precommit_cond1_MethodTryProduct --> PrivilegedFuncUnit_precommit TransactionManager_MethodTryProduct_precommit_cond2 --> TaggedCounter3__incr -TransactionManager_MethodTryProduct_precommit_cond0 --> TaggedCounter3__incr -TransactionManager_MethodTryProduct_precommit_cond1 <--> PrivilegedFuncUnit_precommit_cond1 -TransactionManager_MethodTryProduct_precommit_cond1 <--> InterruptController_mret -TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 -TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read -TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer -TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write -TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write -TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request -TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request -TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy -TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy -TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy -TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue -TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue -TransactionManager_issue_cond1_LSUDummy --> FIFO9_write -TransactionManager_LSUDummy_issue_cond2 --> FIFO9_write -TransactionManager_issue_cond0_LSUDummy --> FIFO9_write +TransactionManager_precommit_cond0_MethodTryProduct --> TaggedCounter3__incr +TransactionManager_precommit_cond1_MethodTryProduct --> TaggedCounter3__incr TransactionManager_MethodTryProduct_precommit_cond2 <--> PrivilegedFuncUnit_precommit_cond2 TransactionManager_MethodTryProduct_precommit_cond2 <--> ICache_flush -TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3 -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement3 -TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write -TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry -TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry -TransactionManager_MethodTryProduct_precommit_cond0 <--> PrivilegedFuncUnit_precommit_cond0 -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 -TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond0 -LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -LSURequester_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -FIFO9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -FIFO9_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans -TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans -TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write -TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> Forwarder7_write -TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write -LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -Serializer1_Serializer2 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -Forwarder1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_cond0_Retirement --> RRAT_commit -TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment -CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write -CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write -TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation Connect_read --> TransactionManager_ROBAllocation_Renaming TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put @@ -1143,15 +1082,76 @@ TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming FIFO12_read --> TransactionManager_ROBAllocation_Renaming TransactionManager_ROBAllocation_Renaming --> Connect_write -TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -Serializer1_Serializer1 --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 -TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write -TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3 +TransactionManager_precommit_cond0_MethodTryProduct <--> PrivilegedFuncUnit_precommit_cond0 +TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans +TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans +TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write +TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> Forwarder7_write +LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 +LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1 FIFO8_read --> TransactionManager_ConnectTrans_accept_cond1 FIFO10_read --> TransactionManager_ConnectTrans_accept_cond1 +TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy +TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy +TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy +TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue +TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond2 --> FIFO9_write +TransactionManager_LSUDummy_issue_cond0 --> FIFO9_write +TransactionManager_issue_cond1_LSUDummy --> FIFO9_write +TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1 +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement1 +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write +TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 +TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond0 +LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +FIFO9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +FIFO9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +Serializer1_Serializer --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 +TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write +TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 +TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write +TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write +TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request +TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit +TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment +CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write +CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr +TransactionManager_precommit_cond1_MethodTryProduct <--> PrivilegedFuncUnit_precommit_cond1 +TransactionManager_precommit_cond1_MethodTryProduct <--> InterruptController_mret +TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 +TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read +TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3 +TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +Serializer1_Serializer2 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 @@ -1162,7 +1162,7 @@

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diff --git a/components/icache.html b/components/icache.html index cc2cd4c77..e0745e173 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

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diff --git a/coreblocks.backend.html b/coreblocks.backend.html index 077817996..edbac404d 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -165,7 +165,7 @@

Submodules

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diff --git a/coreblocks.cache.html b/coreblocks.cache.html index 120257135..230a9b2d9 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -241,7 +241,7 @@

Submodules

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diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index e25e405a1..4e0ca3fe4 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -157,7 +157,7 @@

Submodules

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diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index 672c210f4..90efa58a7 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -1758,7 +1758,7 @@

Submodules

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diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index eec166ebf..967de928b 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -181,7 +181,7 @@

Submodules

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diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 915e58ea5..2bede66a6 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -125,7 +125,7 @@

Subpackages

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diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index c92df9f57..36036b5f1 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -879,7 +879,7 @@

Submodules

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diff --git a/coreblocks.func_blocks.fu.lsu.html b/coreblocks.func_blocks.fu.lsu.html index 7839cc817..7497d91bc 100644 --- a/coreblocks.func_blocks.fu.lsu.html +++ b/coreblocks.func_blocks.fu.lsu.html @@ -231,7 +231,7 @@

Submodules

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diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index 2253958dc..722ba940e 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -238,7 +238,7 @@

Submodules

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diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index 60adb08be..0a4d95861 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -148,7 +148,7 @@

Subpackages

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diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index 81941ec53..f3a3e9657 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -169,7 +169,7 @@

Submodules

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diff --git a/coreblocks.html b/coreblocks.html index 53ded9865..bc4830a18 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -248,7 +248,7 @@

Submodules

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diff --git a/coreblocks.params.html b/coreblocks.params.html index 94c5a72b4..86d33bb73 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -1171,7 +1171,7 @@

Submodules

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diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index fa9d2b0e3..fc6d02066 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -746,7 +746,7 @@

Submodules

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diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html index d9879917b..d07ed2e1b 100644 --- a/coreblocks.priv.csr.html +++ b/coreblocks.priv.csr.html @@ -303,7 +303,7 @@

Submodules

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diff --git a/coreblocks.priv.html b/coreblocks.priv.html index e4f9ba856..61d502504 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -123,7 +123,7 @@

Subpackages

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diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index cf4c452c5..58a84dfb1 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -171,7 +171,7 @@

Submodules

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diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 8db756d82..4414a9ced 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

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diff --git a/current-graph.html b/current-graph.html index 1f4521728..ea27cf8f5 100644 --- a/current-graph.html +++ b/current-graph.html @@ -92,8 +92,8 @@

Full transaction-method graph

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diff --git a/development-environment.html b/development-environment.html index f5b121f6d..5557538fc 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

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diff --git a/genindex.html b/genindex.html index 9be8c8738..22fdc82d2 100644 --- a/genindex.html +++ b/genindex.html @@ -3827,7 +3827,7 @@

Z

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diff --git a/home.html b/home.html index a2d314711..8c942ed0e 100644 --- a/home.html +++ b/home.html @@ -129,7 +129,7 @@

Documentation

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diff --git a/index.html b/index.html index 57e631eca..4e684fe63 100644 --- a/index.html +++ b/index.html @@ -229,7 +229,7 @@

Coreblocks

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diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html index b5c3890f7..6e87ce86d 100644 --- a/miscellany/exceptions-summary.html +++ b/miscellany/exceptions-summary.html @@ -271,7 +271,7 @@

Summary

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diff --git a/modules-coreblocks.html b/modules-coreblocks.html index 91f5e3b5a..4d90816fb 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -168,7 +168,7 @@

coreblocks

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diff --git a/modules-transactron.html b/modules-transactron.html index 1a9fadd4f..9cabacd19 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -161,7 +161,7 @@

transactron

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diff --git a/problem-checklist.html b/problem-checklist.html index 14ec91eec..3bacedc55 100644 --- a/problem-checklist.html +++ b/problem-checklist.html @@ -105,7 +105,7 @@

Problem checklist

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Python Module Index

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More detailed description of each block

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Read and clean row

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External interface signals

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Regression tests manual execution

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Transaction and method nesting

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Submodules

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Submodules

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Submodules

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Submodules

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Submodules

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Submodules

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