diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree
index fb57eb1fa..9cbcae6ba 100644
Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ
diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree
index 765db014d..8a59d8032 100644
Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ
diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree
index 76836f6e7..d70e03791 100644
Binary files a/.doctrees/current-graph.doctree and b/.doctrees/current-graph.doctree differ
diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle
index 3cf46b417..a92c23376 100644
Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ
diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt
index 2da8adfb4..dfabe3c43 100644
--- a/_sources/auto_graph.rst.txt
+++ b/_sources/auto_graph.rst.txt
@@ -7,8 +7,8 @@
                    Core_DiscardBranchVerify["DiscardBranchVerify"]
                    Core_InitFreeRFFifo["InitFreeRFFifo"]
                    subgraph WishboneMaster["wb_master_instr WishboneMaster"]
-                       WishboneMaster_WishboneMaster["WishboneMaster"]
                        WishboneMaster_request["request"]
+                       WishboneMaster_WishboneMaster["WishboneMaster"]
                        WishboneMaster_result["result"]
                        subgraph Forwarder["result Forwarder"]
                            Forwarder_write["write"]
@@ -17,16 +17,16 @@
                    end
                    subgraph WishboneMaster1["wb_master_data WishboneMaster"]
                        WishboneMaster1_WishboneMaster["WishboneMaster"]
-                       WishboneMaster1_request["request"]
                        WishboneMaster1_result["result"]
+                       WishboneMaster1_request["request"]
                        subgraph Forwarder1["result Forwarder"]
                            Forwarder1_read["read"]
                            Forwarder1_write["write"]
                        end
                    end
                    subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"]
-                       WishboneMasterAdapter_get_read_response["get_read_response"]
                        WishboneMasterAdapter_request_read["request_read"]
+                       WishboneMasterAdapter_get_read_response["get_read_response"]
                        subgraph Serializer["bus_serializer Serializer"]
                            Serializer_Serializer["Serializer"]
                            Serializer_Serializer1["Serializer"]
@@ -37,8 +37,8 @@
                        end
                    end
                    subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"]
-                       WishboneMasterAdapter1_get_write_response["get_write_response"]
                        WishboneMasterAdapter1_get_read_response["get_read_response"]
+                       WishboneMasterAdapter1_get_write_response["get_write_response"]
                        WishboneMasterAdapter1_request_read["request_read"]
                        WishboneMasterAdapter1_request_write["request_write"]
                        subgraph Serializer1["bus_serializer Serializer"]
@@ -57,8 +57,8 @@
                        CoreInstructionCounter_increment["increment"]
                    end
                    subgraph FIFO["fifo_fetch FIFO"]
-                       FIFO_read["read"]
                        FIFO_write["write"]
+                       FIFO_read["read"]
                    end
                    subgraph MethodMap["core_counter_increment_discard_map MethodMap"]
                        MethodMap_method["method"]
@@ -71,22 +71,22 @@
                        BasicFifo2_write["write"]
                    end
                    subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"]
-                       SimpleCommonBusCacheRefiller_accept_refill["accept_refill"]
                        SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"]
-                       SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"]
                        SimpleCommonBusCacheRefiller_start_refill["start_refill"]
+                       SimpleCommonBusCacheRefiller_accept_refill["accept_refill"]
+                       SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"]
                        subgraph Forwarder2["resp_fwd Forwarder"]
-                           Forwarder2_read["read"]
                            Forwarder2_write["write"]
+                           Forwarder2_read["read"]
                        end
                    end
                    subgraph ICache["icache ICache"]
-                       ICache_ICache["ICache"]
+                       ICache_issue_req["issue_req"]
+                       ICache_flush["flush"]
                        ICache_MemRead["MemRead"]
                        ICache_accept_res["accept_res"]
+                       ICache_ICache["ICache"]
                        ICache_ICache1["ICache"]
-                       ICache_flush["flush"]
-                       ICache_issue_req["issue_req"]
                        subgraph HwCounter["perf_loads HwCounter"]
                            HwCounter__incr["_incr"]
                        end
@@ -103,8 +103,8 @@
                            HwCounter4__incr["_incr"]
                        end
                        subgraph FIFOLatencyMeasurer["req_latency FIFOLatencyMeasurer"]
-                           FIFOLatencyMeasurer__stop["_stop"]
                            FIFOLatencyMeasurer__start["_start"]
+                           FIFOLatencyMeasurer__stop["_stop"]
                            subgraph HwExpHistogram["histogram HwExpHistogram"]
                                HwExpHistogram__add["_add"]
                            end
@@ -115,9 +115,9 @@
                        end
                        subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"]
                            ArgumentsToResultsZipper_peek_arg["peek_arg"]
-                           ArgumentsToResultsZipper_read["read"]
                            ArgumentsToResultsZipper_write_args["write_args"]
                            ArgumentsToResultsZipper_write_results["write_results"]
+                           ArgumentsToResultsZipper_read["read"]
                            subgraph BasicFifo3["fifo BasicFifo"]
                                BasicFifo3_read["read"]
                                BasicFifo3_peek["peek"]
@@ -133,15 +133,15 @@
                        FRAT_rename["rename"]
                    end
                    subgraph RRAT["RRAT RRAT"]
-                       RRAT_peek["peek"]
                        RRAT_commit["commit"]
+                       RRAT_peek["peek"]
                    end
                    subgraph RegisterFile["RF RegisterFile"]
                        RegisterFile_perf["perf"]
+                       RegisterFile_read2["read2"]
                        RegisterFile_free["free"]
                        RegisterFile_read1["read1"]
                        RegisterFile_write["write"]
-                       RegisterFile_read2["read2"]
                        subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"]
                            TaggedLatencyMeasurer__start["_start"]
                            TaggedLatencyMeasurer__stop["_stop"]
@@ -149,8 +149,8 @@
                                HwExpHistogram1__add["_add"]
                            end
                            subgraph AsyncMemoryBank["slots AsyncMemoryBank"]
-                               AsyncMemoryBank_write["write"]
                                AsyncMemoryBank_read["read"]
+                               AsyncMemoryBank_write["write"]
                            end
                        end
                        subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"]
@@ -158,12 +158,12 @@
                        end
                    end
                    subgraph ReorderBuffer["ROB ReorderBuffer"]
-                       ReorderBuffer_perf["perf"]
                        ReorderBuffer_mark_done["mark_done"]
                        ReorderBuffer_put["put"]
                        ReorderBuffer_peek["peek"]
                        ReorderBuffer_retire["retire"]
                        ReorderBuffer_get_indices["get_indices"]
+                       ReorderBuffer_perf["perf"]
                        subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"]
                            FIFOLatencyMeasurer1__start["_start"]
                            FIFOLatencyMeasurer1__stop["_stop"]
@@ -171,8 +171,8 @@
                                HwExpHistogram3__add["_add"]
                            end
                            subgraph FIFO2["fifo FIFO"]
-                               FIFO2_read["read"]
                                FIFO2_write["write"]
+                               FIFO2_read["read"]
                            end
                        end
                        subgraph HwExpHistogram4["perf_rob_size HwExpHistogram"]
@@ -180,11 +180,11 @@
                        end
                    end
                    subgraph FetchUnit["fetch FetchUnit"]
-                       FetchUnit_Fetch_Stage1["Fetch_Stage1"]
                        FetchUnit_resume["resume"]
                        FetchUnit_stall_exception["stall_exception"]
-                       FetchUnit_Fetch_Stage2["Fetch_Stage2"]
                        FetchUnit_Fetch_Stage0["Fetch_Stage0"]
+                       FetchUnit_Fetch_Stage2["Fetch_Stage2"]
+                       FetchUnit_Fetch_Stage1["Fetch_Stage1"]
                        subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"]
                            TaggedCounter__incr["_incr"]
                        end
@@ -208,13 +208,13 @@
                            Semaphore_release["release"]
                        end
                        subgraph Pipe["s1_s2_pipe Pipe"]
-                           Pipe_write["write"]
                            Pipe_read["read"]
+                           Pipe_write["write"]
                        end
                    end
                    subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"]
-                       ExceptionCauseRegister_clear["clear"]
                        ExceptionCauseRegister_get["get"]
+                       ExceptionCauseRegister_clear["clear"]
                        ExceptionCauseRegister_report["report"]
                        subgraph BasicFifo5["fu_report_fifo BasicFifo"]
                            BasicFifo5_read["read"]
@@ -247,21 +247,21 @@
                            MethodProduct1_method["method"]
                        end
                        subgraph RSFuncBlock["rs_block_0 RSFuncBlock"]
-                           RSFuncBlock_select["select"]
-                           RSFuncBlock_get_result["get_result"]
                            RSFuncBlock_insert["insert"]
                            RSFuncBlock_update["update"]
+                           RSFuncBlock_select["select"]
+                           RSFuncBlock_get_result["get_result"]
                            subgraph RS["rs RS"]
-                               RS_perf["perf"]
+                               RS_insert["insert"]
                                RS_RS["RS"]
+                               RS_update["update"]
                                RS_RS1["RS"]
-                               RS_insert["insert"]
+                               RS_perf["perf"]
+                               RS_select["select"]
                                RS_RS2["RS"]
-                               RS_update["update"]
                                RS_RS3["RS"]
-                               RS_select["select"]
-                               RS_take["take"]
                                RS_RS4["RS"]
+                               RS_take["take"]
                                subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"]
                                    TaggedLatencyMeasurer1__stop["_stop"]
                                    TaggedLatencyMeasurer1__start["_start"]
@@ -278,8 +278,8 @@
                                end
                            end
                            subgraph AluFuncUnit["func_unit_0 AluFuncUnit"]
-                               AluFuncUnit_accept["accept"]
                                AluFuncUnit_issue["issue"]
+                               AluFuncUnit_accept["accept"]
                                subgraph TaggedCounter1["perf_instr TaggedCounter"]
                                    TaggedCounter1__incr["_incr"]
                                end
@@ -292,8 +292,8 @@
                                WakeupSelect_WakeupSelect["WakeupSelect"]
                            end
                            subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"]
-                               ShiftFuncUnit_accept["accept"]
                                ShiftFuncUnit_issue["issue"]
+                               ShiftFuncUnit_accept["accept"]
                                subgraph FIFO4["fifo FIFO"]
                                    FIFO4_write["write"]
                                    FIFO4_read["read"]
@@ -303,11 +303,11 @@
                                WakeupSelect1_WakeupSelect["WakeupSelect"]
                            end
                            subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"]
-                               JumpBranchFuncUnit_accept["accept"]
                                JumpBranchFuncUnit_issue["issue"]
+                               JumpBranchFuncUnit_accept["accept"]
                                subgraph FIFO5["fifo_branch_resolved FIFO"]
-                                   FIFO5_read["read"]
                                    FIFO5_write["write"]
+                                   FIFO5_read["read"]
                                end
                                subgraph TaggedCounter2["perf_instr TaggedCounter"]
                                    TaggedCounter2__incr["_incr"]
@@ -319,19 +319,19 @@
                                    HwCounter7__incr["_incr"]
                                end
                                subgraph FIFO6["fifo_res FIFO"]
-                                   FIFO6_read["read"]
                                    FIFO6_write["write"]
+                                   FIFO6_read["read"]
                                end
                            end
                            subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"]
                                WakeupSelect2_WakeupSelect["WakeupSelect"]
                            end
                            subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"]
-                               ExceptionFuncUnit_issue["issue"]
                                ExceptionFuncUnit_accept["accept"]
+                               ExceptionFuncUnit_issue["issue"]
                                subgraph FIFO7["fifo FIFO"]
-                                   FIFO7_read["read"]
                                    FIFO7_write["write"]
+                                   FIFO7_read["read"]
                                end
                            end
                            subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"]
@@ -339,14 +339,14 @@
                            end
                            subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"]
                                PrivilegedFuncUnit_issue["issue"]
-                               PrivilegedFuncUnit_precommit_cond2["precommit_cond2"]
-                               PrivilegedFuncUnit_accept["accept"]
                                PrivilegedFuncUnit_precommit_cond0["precommit_cond0"]
+                               PrivilegedFuncUnit_accept["accept"]
+                               PrivilegedFuncUnit_precommit_cond2["precommit_cond2"]
                                PrivilegedFuncUnit_precommit["precommit"]
                                PrivilegedFuncUnit_precommit_cond1["precommit_cond1"]
                                subgraph BasicFifo6["fetch_resume_fifo BasicFifo"]
-                                   BasicFifo6_read["read"]
                                    BasicFifo6_write["write"]
+                                   BasicFifo6_read["read"]
                                end
                                subgraph TaggedCounter3["perf_instr TaggedCounter"]
                                    TaggedCounter3__incr["_incr"]
@@ -358,8 +358,8 @@
                            subgraph Collector1["collector Collector"]
                                Collector1_method["method"]
                                subgraph Forwarder5["forwarder Forwarder"]
-                                   Forwarder5_read["read"]
                                    Forwarder5_write["write"]
+                                   Forwarder5_read["read"]
                                end
                                subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"]
                                    subgraph ConnectTrans5["ManyToOneConnectTrans_input_0 ConnectTrans"]
@@ -383,18 +383,18 @@
                        subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"]
                            RSFuncBlock1_select["select"]
                            RSFuncBlock1_insert["insert"]
-                           RSFuncBlock1_get_result["get_result"]
                            RSFuncBlock1_update["update"]
+                           RSFuncBlock1_get_result["get_result"]
                            subgraph FifoRS["rs FifoRS"]
                                FifoRS_update["update"]
                                FifoRS_select["select"]
-                               FifoRS_FifoRS["FifoRS"]
+                               FifoRS_insert["insert"]
                                FifoRS_take["take"]
                                FifoRS_perf["perf"]
-                               FifoRS_insert["insert"]
+                               FifoRS_FifoRS["FifoRS"]
                                subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"]
-                                   TaggedLatencyMeasurer2__start["_start"]
                                    TaggedLatencyMeasurer2__stop["_stop"]
+                                   TaggedLatencyMeasurer2__start["_start"]
                                    subgraph HwExpHistogram7["histogram HwExpHistogram"]
                                        HwExpHistogram7__add["_add"]
                                    end
@@ -408,33 +408,33 @@
                                end
                            end
                            subgraph LSUDummy["func_unit_0 LSUDummy"]
-                               LSUDummy_LSUDummy["LSUDummy"]
-                               LSUDummy_issue["issue"]
                                LSUDummy_accept["accept"]
-                               LSUDummy_accept_cond1["accept_cond1"]
-                               LSUDummy_precommit["precommit"]
                                LSUDummy_accept_cond0["accept_cond0"]
+                               LSUDummy_accept_cond1["accept_cond1"]
+                               LSUDummy_LSUDummy["LSUDummy"]
                                LSUDummy_LSUDummy1["LSUDummy"]
+                               LSUDummy_issue["issue"]
+                               LSUDummy_precommit["precommit"]
                                subgraph LSURequester["requester LSURequester"]
                                    LSURequester_accept["accept"]
+                                   LSURequester_issue_cond0["issue_cond0"]
                                    LSURequester_issue["issue"]
                                    LSURequester_issue_cond1["issue_cond1"]
-                                   LSURequester_issue_cond0["issue_cond0"]
                                    LSURequester_accept_cond1["accept_cond1"]
-                                   LSURequester_accept_cond0["accept_cond0"]
                                    LSURequester_issue_cond2["issue_cond2"]
+                                   LSURequester_accept_cond0["accept_cond0"]
                                end
                                subgraph Forwarder6["requests Forwarder"]
-                                   Forwarder6_read["read"]
                                    Forwarder6_write["write"]
+                                   Forwarder6_read["read"]
                                end
                                subgraph FIFO8["results_noop FIFO"]
                                    FIFO8_read["read"]
                                    FIFO8_write["write"]
                                end
                                subgraph FIFO9["issued FIFO"]
-                                   FIFO9_write["write"]
                                    FIFO9_read["read"]
+                                   FIFO9_write["write"]
                                end
                                subgraph FIFO10["issued_noop FIFO"]
                                    FIFO10_read["read"]
@@ -459,18 +459,18 @@
                        end
                        subgraph CSRUnit["rs_block_2 CSRUnit"]
                            CSRUnit_CSRUnit["CSRUnit"]
+                           CSRUnit_get_result["get_result"]
                            CSRUnit_insert["insert"]
-                           CSRUnit_select["select"]
                            CSRUnit_update["update"]
-                           CSRUnit_fetch_resume["fetch_resume"]
                            CSRUnit_precommit["precommit"]
-                           CSRUnit_get_result["get_result"]
+                           CSRUnit_select["select"]
+                           CSRUnit_fetch_resume["fetch_resume"]
                        end
                        subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"]
                            MethodTryProduct_MethodTryProduct["MethodTryProduct"]
                            MethodTryProduct_MethodTryProduct1["MethodTryProduct"]
-                           MethodTryProduct_method["method"]
                            MethodTryProduct_MethodTryProduct2["MethodTryProduct"]
+                           MethodTryProduct_method["method"]
                        end
                        subgraph Collector3["FetchResumeKey_unifier Collector"]
                            Collector3_method["method"]
@@ -492,16 +492,16 @@
                        ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"]
                    end
                    subgraph InterruptController["interrupt_controller InterruptController"]
-                       InterruptController_report_interrupt["report_interrupt"]
-                       InterruptController_entry["entry"]
                        InterruptController_mret["mret"]
+                       InterruptController_entry["entry"]
+                       InterruptController_report_interrupt["report_interrupt"]
                    end
                    subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"]
                        GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"]
                        subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"]
                            subgraph CSRRegister["mcause CSRRegister"]
-                               CSRRegister__internal_fu_read["_internal_fu_read"]
                                CSRRegister__internal_fu_write["_internal_fu_write"]
+                               CSRRegister__internal_fu_read["_internal_fu_read"]
                                CSRRegister_write["write"]
                                subgraph MethodMap1["fu_write_map MethodMap"]
                                    MethodMap1_method["method"]
@@ -514,9 +514,9 @@
                                end
                            end
                            subgraph CSRRegister1["mtvec CSRRegister"]
+                               CSRRegister1_read["read"]
                                CSRRegister1__internal_fu_read["_internal_fu_read"]
                                CSRRegister1__internal_fu_write["_internal_fu_write"]
-                               CSRRegister1_read["read"]
                                subgraph MethodMap3["fu_write_map MethodMap"]
                                    MethodMap3_method["method"]
                                end
@@ -530,8 +530,8 @@
                            subgraph CSRRegister2["mepc CSRRegister"]
                                CSRRegister2__internal_fu_read["_internal_fu_read"]
                                CSRRegister2_read["read"]
-                               CSRRegister2__internal_fu_write["_internal_fu_write"]
                                CSRRegister2_write["write"]
+                               CSRRegister2__internal_fu_write["_internal_fu_write"]
                                subgraph MethodMap5["fu_write_map MethodMap"]
                                    MethodMap5_method["method"]
                                end
@@ -583,8 +583,8 @@
                        end
                    end
                    subgraph FIFO11["fifo_decode FIFO"]
-                       FIFO11_write["write"]
                        FIFO11_read["read"]
+                       FIFO11_write["write"]
                    end
                    subgraph DecodeStage["decode DecodeStage"]
                        DecodeStage_DecodeStage["DecodeStage"]
@@ -601,8 +601,8 @@
                            RegAllocation_RegAllocation["RegAllocation"]
                        end
                        subgraph Connect["rename_out_buf Connect"]
-                           Connect_read["read"]
                            Connect_write["write"]
+                           Connect_read["read"]
                        end
                        subgraph Renaming["renaming Renaming"]
                            Renaming_Renaming["Renaming"]
@@ -634,25 +634,25 @@
                        Retirement_core_state["core_state"]
                        Retirement_Retirement["Retirement"]
                        Retirement_Retirement1["Retirement"]
+                       Retirement_Retirement_cond1["Retirement_cond1"]
+                       Retirement_Retirement_cond0["Retirement_cond0"]
                        Retirement_Retirement2["Retirement"]
                        Retirement_Retirement3["Retirement"]
-                       Retirement_Retirement_cond0["Retirement_cond0"]
-                       Retirement_Retirement_cond1["Retirement_cond1"]
                        Retirement_Retirement4["Retirement"]
                        subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"]
                            DoubleCounterCSR2_increment["increment"]
                            subgraph CSRRegister7["register_low CSRRegister"]
                                CSRRegister7__internal_fu_read["_internal_fu_read"]
-                               CSRRegister7_read["read"]
                                CSRRegister7_write["write"]
+                               CSRRegister7_read["read"]
                                subgraph MethodMap16["fu_read_map MethodMap"]
                                    MethodMap16_method["method"]
                                end
                            end
                            subgraph CSRRegister8["register_high CSRRegister"]
+                               CSRRegister8__internal_fu_read["_internal_fu_read"]
                                CSRRegister8_read["read"]
                                CSRRegister8_write["write"]
-                               CSRRegister8__internal_fu_read["_internal_fu_read"]
                                subgraph MethodMap18["fu_read_map MethodMap"]
                                    MethodMap18_method["method"]
                                end
@@ -675,39 +675,39 @@
                end
            end
            subgraph TransactionManager["transactionManager TransactionManager"]
-               TransactionManager_MethodTryProduct_precommit_cond0["MethodTryProduct_precommit_cond0"]
-               TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"]
-               TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"]
+               TransactionManager_ConnectTrans_accept_cond1["ConnectTrans_accept_cond1"]
+               TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"]
+               TransactionManager_precommit_cond0_MethodTryProduct["precommit_cond0_MethodTryProduct"]
+               TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"]
+               TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"]
                TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"]
+               TransactionManager_accept_cond0_ConnectTrans_accept_cond1["accept_cond0_ConnectTrans_accept_cond1"]
+               TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"]
+               TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"]
+               TransactionManager_precommit_cond1_MethodTryProduct["precommit_cond1_MethodTryProduct"]
                TransactionManager_MethodTryProduct_precommit_cond2["MethodTryProduct_precommit_cond2"]
-               TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"]
-               TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"]
-               TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"]
-               TransactionManager_MethodTryProduct_precommit_cond1["MethodTryProduct_precommit_cond1"]
-               TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"]
-               TransactionManager_ConnectTrans_accept_cond1["ConnectTrans_accept_cond1"]
-               TransactionManager_accept_cond0_accept_cond1_ConnectTrans["accept_cond0_accept_cond1_ConnectTrans"]
+               TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"]
            end
        end
    Core_InitFreeRFFifo --> BasicFifo2_write
-   Retirement_Retirement --> BasicFifo2_write
-   TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write
-   TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write
+   Retirement_Retirement2 --> BasicFifo2_write
+   TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write
+   TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write
    FIFO5_read --> Core_DiscardBranchVerify
    WishboneMaster_WishboneMaster --> Forwarder_write
    WishboneMaster1_WishboneMaster --> Forwarder1_write
    RegisterFile_perf --> HwExpHistogram2__add
    ReorderBuffer_perf --> HwExpHistogram4__add
-   SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read
-   SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1
-   SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write
-   SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request
-   WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-   Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-   BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-   WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-   Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-   SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write
+   SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMasterAdapter_request_read
+   SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Serializer_Serializer
+   SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> BasicFifo_write
+   SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMaster_request
+   WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+   Serializer_Serializer1 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+   BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+   WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+   Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+   SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Forwarder2_write
    ICache_ICache <--> HwCounter4__incr
    ArgumentsToResultsZipper_peek_arg --> ICache_MemRead
    BasicFifo3_peek --> ICache_MemRead
@@ -756,16 +756,16 @@
    FIFO11_read --> RegAllocation_RegAllocation
    BasicFifo2_read --> RegAllocation_RegAllocation
    RegAllocation_RegAllocation --> FIFO12_write
-   FIFO13_read --> RSSelection_RSSelection
    FIFO13_read --> RSSelection_RSSelection2
+   FIFO13_read --> RSSelection_RSSelection
    FIFO13_read --> RSSelection_RSSelection1
-   RSFuncBlock_select --> RSSelection_RSSelection
-   RS_select --> RSSelection_RSSelection
-   RSSelection_RSSelection --> FIFO14_write
+   RSFuncBlock_select --> RSSelection_RSSelection2
+   RS_select --> RSSelection_RSSelection2
    RSSelection_RSSelection2 --> FIFO14_write
+   RSSelection_RSSelection --> FIFO14_write
    RSSelection_RSSelection1 --> FIFO14_write
-   RSFuncBlock1_select --> RSSelection_RSSelection2
-   FifoRS_select --> RSSelection_RSSelection2
+   RSFuncBlock1_select --> RSSelection_RSSelection
+   FifoRS_select --> RSSelection_RSSelection
    RSSelection_RSSelection1 <--> CSRUnit_select
    FIFO14_read --> RSInsertion_RSInsertion
    RegisterFile_read1 --> RSInsertion_RSInsertion
@@ -788,7 +788,7 @@
    Collector3_method --> ConnectTrans13_ConnectTrans
    Forwarder8_read --> ConnectTrans13_ConnectTrans
    ConnectTrans13_ConnectTrans --> FetchUnit_resume
-   Retirement_Retirement4 --> FetchUnit_resume
+   Retirement_Retirement --> FetchUnit_resume
    Collector_method --> ResultAnnouncement_ResultAnnouncement
    Forwarder4_read --> ResultAnnouncement_ResultAnnouncement
    ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done
@@ -802,7 +802,7 @@
    ResultAnnouncement_ResultAnnouncement --> FifoRS_update
    ResultAnnouncement_ResultAnnouncement --> CSRUnit_update
    RS_perf --> HwExpHistogram6__add
-   RS_RS2 --> WakeupSelect_WakeupSelect
+   RS_RS4 --> WakeupSelect_WakeupSelect
    RS_take --> WakeupSelect_WakeupSelect
    RS_take --> WakeupSelect1_WakeupSelect
    RS_take --> WakeupSelect2_WakeupSelect
@@ -826,10 +826,10 @@
    WakeupSelect_WakeupSelect --> AluFuncUnit_issue
    WakeupSelect_WakeupSelect --> TaggedCounter1__incr
    WakeupSelect_WakeupSelect --> FIFO3_write
-   RS_RS --> WakeupSelect1_WakeupSelect
+   RS_RS1 --> WakeupSelect1_WakeupSelect
    WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue
    WakeupSelect1_WakeupSelect --> FIFO4_write
-   RS_RS3 --> WakeupSelect2_WakeupSelect
+   RS_RS --> WakeupSelect2_WakeupSelect
    WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue
    WakeupSelect2_WakeupSelect --> TaggedCounter2__incr
    WakeupSelect2_WakeupSelect <--> HwCounter7__incr
@@ -838,15 +838,15 @@
    WakeupSelect3_WakeupSelect --> BasicFifo5_write
    ConnectTrans9_ConnectTrans --> BasicFifo5_write
    ConnectTrans4_ConnectTrans --> BasicFifo5_write
-   TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo5_write
-   TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> BasicFifo5_write
    TransactionManager_ConnectTrans_accept_cond1 --> BasicFifo5_write
+   TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo5_write
+   TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> BasicFifo5_write
    WakeupSelect2_WakeupSelect --> FIFO6_write
    WakeupSelect2_WakeupSelect --> FIFO5_write
-   RS_RS1 --> WakeupSelect3_WakeupSelect
+   RS_RS3 --> WakeupSelect3_WakeupSelect
    WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue
    WakeupSelect3_WakeupSelect --> FIFO7_write
-   RS_RS4 --> WakeupSelect4_WakeupSelect
+   RS_RS2 --> WakeupSelect4_WakeupSelect
    WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue
    ConnectTrans5_ConnectTrans --> Forwarder5_write
    ConnectTrans6_ConnectTrans --> Forwarder5_write
@@ -866,19 +866,19 @@
    ConnectTrans9_ConnectTrans --> BasicFifo6_write
    FifoRS_perf --> HwExpHistogram8__add
    Forwarder6_read --> LSUDummy_LSUDummy1
-   Forwarder6_read --> TransactionManager_issue_cond1_LSUDummy
    Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2
-   Forwarder6_read --> TransactionManager_issue_cond0_LSUDummy
+   Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0
+   Forwarder6_read --> TransactionManager_issue_cond1_LSUDummy
    LSUDummy_LSUDummy1 --> FIFO8_write
    WakeupSelect5_WakeupSelect --> FIFO8_write
-   TransactionManager_issue_cond1_LSUDummy --> FIFO8_write
    TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write
-   TransactionManager_issue_cond0_LSUDummy --> FIFO8_write
+   TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write
+   TransactionManager_issue_cond1_LSUDummy --> FIFO8_write
    LSUDummy_LSUDummy1 --> FIFO10_write
    WakeupSelect5_WakeupSelect --> FIFO10_write
-   TransactionManager_issue_cond1_LSUDummy --> FIFO10_write
    TransactionManager_LSUDummy_issue_cond2 --> FIFO10_write
-   TransactionManager_issue_cond0_LSUDummy --> FIFO10_write
+   TransactionManager_LSUDummy_issue_cond0 --> FIFO10_write
+   TransactionManager_issue_cond1_LSUDummy --> FIFO10_write
    FifoRS_FifoRS --> WakeupSelect5_WakeupSelect
    FifoRS_take --> WakeupSelect5_WakeupSelect
    WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop
@@ -923,55 +923,55 @@
    Collector2_method --> ConnectTrans3_ConnectTrans
    Forwarder7_read --> ConnectTrans3_ConnectTrans
    CSRUnit_get_result --> ConnectTrans4_ConnectTrans
-   MethodTryProduct_MethodTryProduct2 --> LSUDummy_precommit
-   MethodTryProduct_MethodTryProduct --> CSRUnit_precommit
+   MethodTryProduct_MethodTryProduct1 --> LSUDummy_precommit
+   MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit
    ConnectTrans11_ConnectTrans --> Forwarder8_write
    ConnectTrans12_ConnectTrans --> Forwarder8_write
    BasicFifo6_read --> ConnectTrans11_ConnectTrans
    CSRUnit_fetch_resume --> ConnectTrans12_ConnectTrans
+   ReorderBuffer_peek --> Retirement_Retirement4
+   ReorderBuffer_peek --> Retirement_Retirement3
    ReorderBuffer_peek --> Retirement_Retirement2
-   ReorderBuffer_peek --> Retirement_Retirement1
-   ReorderBuffer_peek --> Retirement_Retirement
-   ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement
-   ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement
-   Retirement_Retirement2 --> MethodTryProduct_method
-   ExceptionCauseRegister_get --> Retirement_Retirement1
-   ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement
-   ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement
-   Retirement_Retirement <--> ReorderBuffer_retire
-   TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire
-   TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire
-   Retirement_Retirement <--> FIFOLatencyMeasurer1__stop
-   TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer1__stop
-   TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer1__stop
-   FIFO2_read --> Retirement_Retirement
-   FIFO2_read --> TransactionManager_Retirement_cond1_Retirement
-   FIFO2_read --> TransactionManager_Retirement_cond0_Retirement
-   Retirement_Retirement --> HwExpHistogram3__add
-   TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram3__add
-   TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram3__add
-   CoreInstructionCounter_decrement --> Retirement_Retirement
-   CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement
-   CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement
-   RRAT_peek --> Retirement_Retirement
-   RRAT_peek --> TransactionManager_Retirement_cond1_Retirement
-   Retirement_Retirement --> RegisterFile_free
-   TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free
-   TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free
-   Retirement_Retirement --> TaggedLatencyMeasurer__stop
-   TransactionManager_Retirement_cond1_Retirement --> TaggedLatencyMeasurer__stop
-   TransactionManager_Retirement_cond0_Retirement --> TaggedLatencyMeasurer__stop
-   AsyncMemoryBank_read --> Retirement_Retirement
-   AsyncMemoryBank_read --> TransactionManager_Retirement_cond1_Retirement
-   AsyncMemoryBank_read --> TransactionManager_Retirement_cond0_Retirement
-   Retirement_Retirement --> HwExpHistogram1__add
-   TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add
-   TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add
-   Retirement_Retirement --> FRAT_rename
-   TransactionManager_Retirement_cond1_Retirement --> FRAT_rename
+   ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1
+   ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0
+   Retirement_Retirement4 --> MethodTryProduct_method
+   ExceptionCauseRegister_get --> Retirement_Retirement3
+   ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1
+   ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0
+   Retirement_Retirement2 <--> ReorderBuffer_retire
+   TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire
+   TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire
+   Retirement_Retirement2 <--> FIFOLatencyMeasurer1__stop
+   TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop
+   TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop
+   FIFO2_read --> Retirement_Retirement2
+   FIFO2_read --> TransactionManager_Retirement_Retirement_cond1
+   FIFO2_read --> TransactionManager_Retirement_Retirement_cond0
+   Retirement_Retirement2 --> HwExpHistogram3__add
+   TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add
+   TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add
+   CoreInstructionCounter_decrement --> Retirement_Retirement2
+   CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1
+   CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0
+   RRAT_peek --> Retirement_Retirement2
+   RRAT_peek --> TransactionManager_Retirement_Retirement_cond1
+   Retirement_Retirement2 --> RegisterFile_free
+   TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free
+   TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free
+   Retirement_Retirement2 --> TaggedLatencyMeasurer__stop
+   TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop
+   TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop
+   AsyncMemoryBank_read --> Retirement_Retirement2
+   AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1
+   AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0
+   Retirement_Retirement2 --> HwExpHistogram1__add
+   TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add
+   TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add
+   Retirement_Retirement2 --> FRAT_rename
    TransactionManager_ROBAllocation_Renaming --> FRAT_rename
-   CSRRegister1_read --> Retirement_Retirement4
-   Retirement_Retirement4 <--> ExceptionCauseRegister_clear
+   TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename
+   CSRRegister1_read --> Retirement_Retirement
+   Retirement_Retirement <--> ExceptionCauseRegister_clear
    GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment
    CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters
    GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write
@@ -983,78 +983,17 @@
    CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters
    GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write
    AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt
-   TransactionManager_MethodTryProduct_precommit_cond1 <--> MethodTryProduct_MethodTryProduct1
-   TransactionManager_MethodTryProduct_precommit_cond2 <--> MethodTryProduct_MethodTryProduct1
-   TransactionManager_MethodTryProduct_precommit_cond0 <--> MethodTryProduct_MethodTryProduct1
-   TransactionManager_MethodTryProduct_precommit_cond1 --> PrivilegedFuncUnit_precommit
+   TransactionManager_MethodTryProduct_precommit_cond2 <--> MethodTryProduct_MethodTryProduct
+   TransactionManager_precommit_cond0_MethodTryProduct <--> MethodTryProduct_MethodTryProduct
+   TransactionManager_precommit_cond1_MethodTryProduct <--> MethodTryProduct_MethodTryProduct
    TransactionManager_MethodTryProduct_precommit_cond2 --> PrivilegedFuncUnit_precommit
-   TransactionManager_MethodTryProduct_precommit_cond0 --> PrivilegedFuncUnit_precommit
-   TransactionManager_MethodTryProduct_precommit_cond1 --> TaggedCounter3__incr
+   TransactionManager_precommit_cond0_MethodTryProduct --> PrivilegedFuncUnit_precommit
+   TransactionManager_precommit_cond1_MethodTryProduct --> PrivilegedFuncUnit_precommit
    TransactionManager_MethodTryProduct_precommit_cond2 --> TaggedCounter3__incr
-   TransactionManager_MethodTryProduct_precommit_cond0 --> TaggedCounter3__incr
-   TransactionManager_MethodTryProduct_precommit_cond1 <--> PrivilegedFuncUnit_precommit_cond1
-   TransactionManager_MethodTryProduct_precommit_cond1 <--> InterruptController_mret
-   TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1
-   TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read
-   TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer
-   TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write
-   TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write
-   TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request
-   TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request
-   TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy
-   TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy
-   TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy
-   TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue
-   TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue
-   TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue
-   TransactionManager_issue_cond1_LSUDummy --> FIFO9_write
-   TransactionManager_LSUDummy_issue_cond2 --> FIFO9_write
-   TransactionManager_issue_cond0_LSUDummy --> FIFO9_write
+   TransactionManager_precommit_cond0_MethodTryProduct --> TaggedCounter3__incr
+   TransactionManager_precommit_cond1_MethodTryProduct --> TaggedCounter3__incr
    TransactionManager_MethodTryProduct_precommit_cond2 <--> PrivilegedFuncUnit_precommit_cond2
    TransactionManager_MethodTryProduct_precommit_cond2 <--> ICache_flush
-   TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2
-   TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1
-   TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3
-   TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement3
-   TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write
-   TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write
-   TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write
-   TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write
-   TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry
-   TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry
-   TransactionManager_MethodTryProduct_precommit_cond0 <--> PrivilegedFuncUnit_precommit_cond0
-   TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0
-   TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond0
-   LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-   LSURequester_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-   FIFO9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-   FIFO9_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-   TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans
-   TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans
-   TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans
-   TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write
-   TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> Forwarder7_write
-   TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write
-   LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-   LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-   LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1
-   TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0
-   WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-   Serializer1_Serializer2 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-   BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-   BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-   WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-   WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-   Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-   Forwarder1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-   TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0
-   TransactionManager_Retirement_cond0_Retirement --> RRAT_commit
-   TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment
-   CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement
-   TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write
-   CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement
-   TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write
-   TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr
    TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation
    Connect_read --> TransactionManager_ROBAllocation_Renaming
    TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put
@@ -1064,12 +1003,73 @@
    TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming
    FIFO12_read --> TransactionManager_ROBAllocation_Renaming
    TransactionManager_ROBAllocation_Renaming --> Connect_write
-   TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSURequester_accept_cond1
-   WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-   Serializer1_Serializer1 --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-   TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0
-   TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write
-   TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3
+   TransactionManager_precommit_cond0_MethodTryProduct <--> PrivilegedFuncUnit_precommit_cond0
+   TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans
+   TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans
+   TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans
+   TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write
+   TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write
+   TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> Forwarder7_write
+   LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1
+   LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+   LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1
    TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1
    FIFO8_read --> TransactionManager_ConnectTrans_accept_cond1
    FIFO10_read --> TransactionManager_ConnectTrans_accept_cond1
+   TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy
+   TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy
+   TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy
+   TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue
+   TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue
+   TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue
+   TransactionManager_LSUDummy_issue_cond2 --> FIFO9_write
+   TransactionManager_LSUDummy_issue_cond0 --> FIFO9_write
+   TransactionManager_issue_cond1_LSUDummy --> FIFO9_write
+   TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2
+   TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1
+   TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement1
+   TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write
+   TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write
+   TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write
+   TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write
+   TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry
+   TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry
+   TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1
+   TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0
+   TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond0
+   LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+   LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+   FIFO9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+   FIFO9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+   TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0
+   WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+   Serializer1_Serializer --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+   BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+   BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+   WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+   WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+   Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+   Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+   TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0
+   TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write
+   TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1
+   TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write
+   TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write
+   TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request
+   TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request
+   TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0
+   TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit
+   TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment
+   CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0
+   TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write
+   CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0
+   TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write
+   TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr
+   TransactionManager_precommit_cond1_MethodTryProduct <--> PrivilegedFuncUnit_precommit_cond1
+   TransactionManager_precommit_cond1_MethodTryProduct <--> InterruptController_mret
+   TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1
+   TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read
+   TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3
+   TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSURequester_accept_cond1
+   WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+   Serializer1_Serializer2 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1
diff --git a/api.html b/api.html
index 2e43cb783..ff16140c2 100644
--- a/api.html
+++ b/api.html
@@ -259,7 +259,7 @@ <h2>transactron<a class="headerlink" href="#transactron" title="Permalink to thi
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/assumptions.html b/assumptions.html
index dc9019150..4b65ca310 100644
--- a/assumptions.html
+++ b/assumptions.html
@@ -104,7 +104,7 @@ <h1>List of assumptions made during development<a class="headerlink" href="#list
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/auto_graph.html b/auto_graph.html
index aa750f29f..5eeab28f4 100644
--- a/auto_graph.html
+++ b/auto_graph.html
@@ -86,8 +86,8 @@
                 Core_DiscardBranchVerify[&quot;DiscardBranchVerify&quot;]
                 Core_InitFreeRFFifo[&quot;InitFreeRFFifo&quot;]
                 subgraph WishboneMaster[&quot;wb_master_instr WishboneMaster&quot;]
-                    WishboneMaster_WishboneMaster[&quot;WishboneMaster&quot;]
                     WishboneMaster_request[&quot;request&quot;]
+                    WishboneMaster_WishboneMaster[&quot;WishboneMaster&quot;]
                     WishboneMaster_result[&quot;result&quot;]
                     subgraph Forwarder[&quot;result Forwarder&quot;]
                         Forwarder_write[&quot;write&quot;]
@@ -96,16 +96,16 @@
                 end
                 subgraph WishboneMaster1[&quot;wb_master_data WishboneMaster&quot;]
                     WishboneMaster1_WishboneMaster[&quot;WishboneMaster&quot;]
-                    WishboneMaster1_request[&quot;request&quot;]
                     WishboneMaster1_result[&quot;result&quot;]
+                    WishboneMaster1_request[&quot;request&quot;]
                     subgraph Forwarder1[&quot;result Forwarder&quot;]
                         Forwarder1_read[&quot;read&quot;]
                         Forwarder1_write[&quot;write&quot;]
                     end
                 end
                 subgraph WishboneMasterAdapter[&quot;bus_master_instr_adapter WishboneMasterAdapter&quot;]
-                    WishboneMasterAdapter_get_read_response[&quot;get_read_response&quot;]
                     WishboneMasterAdapter_request_read[&quot;request_read&quot;]
+                    WishboneMasterAdapter_get_read_response[&quot;get_read_response&quot;]
                     subgraph Serializer[&quot;bus_serializer Serializer&quot;]
                         Serializer_Serializer[&quot;Serializer&quot;]
                         Serializer_Serializer1[&quot;Serializer&quot;]
@@ -116,8 +116,8 @@
                     end
                 end
                 subgraph WishboneMasterAdapter1[&quot;bus_master_data_adapter WishboneMasterAdapter&quot;]
-                    WishboneMasterAdapter1_get_write_response[&quot;get_write_response&quot;]
                     WishboneMasterAdapter1_get_read_response[&quot;get_read_response&quot;]
+                    WishboneMasterAdapter1_get_write_response[&quot;get_write_response&quot;]
                     WishboneMasterAdapter1_request_read[&quot;request_read&quot;]
                     WishboneMasterAdapter1_request_write[&quot;request_write&quot;]
                     subgraph Serializer1[&quot;bus_serializer Serializer&quot;]
@@ -136,8 +136,8 @@
                     CoreInstructionCounter_increment[&quot;increment&quot;]
                 end
                 subgraph FIFO[&quot;fifo_fetch FIFO&quot;]
-                    FIFO_read[&quot;read&quot;]
                     FIFO_write[&quot;write&quot;]
+                    FIFO_read[&quot;read&quot;]
                 end
                 subgraph MethodMap[&quot;core_counter_increment_discard_map MethodMap&quot;]
                     MethodMap_method[&quot;method&quot;]
@@ -150,22 +150,22 @@
                     BasicFifo2_write[&quot;write&quot;]
                 end
                 subgraph SimpleCommonBusCacheRefiller[&quot;icache_refiller SimpleCommonBusCacheRefiller&quot;]
-                    SimpleCommonBusCacheRefiller_accept_refill[&quot;accept_refill&quot;]
                     SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller[&quot;SimpleCommonBusCacheRefiller&quot;]
-                    SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1[&quot;SimpleCommonBusCacheRefiller&quot;]
                     SimpleCommonBusCacheRefiller_start_refill[&quot;start_refill&quot;]
+                    SimpleCommonBusCacheRefiller_accept_refill[&quot;accept_refill&quot;]
+                    SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1[&quot;SimpleCommonBusCacheRefiller&quot;]
                     subgraph Forwarder2[&quot;resp_fwd Forwarder&quot;]
-                        Forwarder2_read[&quot;read&quot;]
                         Forwarder2_write[&quot;write&quot;]
+                        Forwarder2_read[&quot;read&quot;]
                     end
                 end
                 subgraph ICache[&quot;icache ICache&quot;]
-                    ICache_ICache[&quot;ICache&quot;]
+                    ICache_issue_req[&quot;issue_req&quot;]
+                    ICache_flush[&quot;flush&quot;]
                     ICache_MemRead[&quot;MemRead&quot;]
                     ICache_accept_res[&quot;accept_res&quot;]
+                    ICache_ICache[&quot;ICache&quot;]
                     ICache_ICache1[&quot;ICache&quot;]
-                    ICache_flush[&quot;flush&quot;]
-                    ICache_issue_req[&quot;issue_req&quot;]
                     subgraph HwCounter[&quot;perf_loads HwCounter&quot;]
                         HwCounter__incr[&quot;_incr&quot;]
                     end
@@ -182,8 +182,8 @@
                         HwCounter4__incr[&quot;_incr&quot;]
                     end
                     subgraph FIFOLatencyMeasurer[&quot;req_latency FIFOLatencyMeasurer&quot;]
-                        FIFOLatencyMeasurer__stop[&quot;_stop&quot;]
                         FIFOLatencyMeasurer__start[&quot;_start&quot;]
+                        FIFOLatencyMeasurer__stop[&quot;_stop&quot;]
                         subgraph HwExpHistogram[&quot;histogram HwExpHistogram&quot;]
                             HwExpHistogram__add[&quot;_add&quot;]
                         end
@@ -194,9 +194,9 @@
                     end
                     subgraph ArgumentsToResultsZipper[&quot;req_zipper ArgumentsToResultsZipper&quot;]
                         ArgumentsToResultsZipper_peek_arg[&quot;peek_arg&quot;]
-                        ArgumentsToResultsZipper_read[&quot;read&quot;]
                         ArgumentsToResultsZipper_write_args[&quot;write_args&quot;]
                         ArgumentsToResultsZipper_write_results[&quot;write_results&quot;]
+                        ArgumentsToResultsZipper_read[&quot;read&quot;]
                         subgraph BasicFifo3[&quot;fifo BasicFifo&quot;]
                             BasicFifo3_read[&quot;read&quot;]
                             BasicFifo3_peek[&quot;peek&quot;]
@@ -212,15 +212,15 @@
                     FRAT_rename[&quot;rename&quot;]
                 end
                 subgraph RRAT[&quot;RRAT RRAT&quot;]
-                    RRAT_peek[&quot;peek&quot;]
                     RRAT_commit[&quot;commit&quot;]
+                    RRAT_peek[&quot;peek&quot;]
                 end
                 subgraph RegisterFile[&quot;RF RegisterFile&quot;]
                     RegisterFile_perf[&quot;perf&quot;]
+                    RegisterFile_read2[&quot;read2&quot;]
                     RegisterFile_free[&quot;free&quot;]
                     RegisterFile_read1[&quot;read1&quot;]
                     RegisterFile_write[&quot;write&quot;]
-                    RegisterFile_read2[&quot;read2&quot;]
                     subgraph TaggedLatencyMeasurer[&quot;perf_rf_valid_time TaggedLatencyMeasurer&quot;]
                         TaggedLatencyMeasurer__start[&quot;_start&quot;]
                         TaggedLatencyMeasurer__stop[&quot;_stop&quot;]
@@ -228,8 +228,8 @@
                             HwExpHistogram1__add[&quot;_add&quot;]
                         end
                         subgraph AsyncMemoryBank[&quot;slots AsyncMemoryBank&quot;]
-                            AsyncMemoryBank_write[&quot;write&quot;]
                             AsyncMemoryBank_read[&quot;read&quot;]
+                            AsyncMemoryBank_write[&quot;write&quot;]
                         end
                     end
                     subgraph HwExpHistogram2[&quot;perf_num_valid HwExpHistogram&quot;]
@@ -237,12 +237,12 @@
                     end
                 end
                 subgraph ReorderBuffer[&quot;ROB ReorderBuffer&quot;]
-                    ReorderBuffer_perf[&quot;perf&quot;]
                     ReorderBuffer_mark_done[&quot;mark_done&quot;]
                     ReorderBuffer_put[&quot;put&quot;]
                     ReorderBuffer_peek[&quot;peek&quot;]
                     ReorderBuffer_retire[&quot;retire&quot;]
                     ReorderBuffer_get_indices[&quot;get_indices&quot;]
+                    ReorderBuffer_perf[&quot;perf&quot;]
                     subgraph FIFOLatencyMeasurer1[&quot;perf_rob_wait_time FIFOLatencyMeasurer&quot;]
                         FIFOLatencyMeasurer1__start[&quot;_start&quot;]
                         FIFOLatencyMeasurer1__stop[&quot;_stop&quot;]
@@ -250,8 +250,8 @@
                             HwExpHistogram3__add[&quot;_add&quot;]
                         end
                         subgraph FIFO2[&quot;fifo FIFO&quot;]
-                            FIFO2_read[&quot;read&quot;]
                             FIFO2_write[&quot;write&quot;]
+                            FIFO2_read[&quot;read&quot;]
                         end
                     end
                     subgraph HwExpHistogram4[&quot;perf_rob_size HwExpHistogram&quot;]
@@ -259,11 +259,11 @@
                     end
                 end
                 subgraph FetchUnit[&quot;fetch FetchUnit&quot;]
-                    FetchUnit_Fetch_Stage1[&quot;Fetch_Stage1&quot;]
                     FetchUnit_resume[&quot;resume&quot;]
                     FetchUnit_stall_exception[&quot;stall_exception&quot;]
-                    FetchUnit_Fetch_Stage2[&quot;Fetch_Stage2&quot;]
                     FetchUnit_Fetch_Stage0[&quot;Fetch_Stage0&quot;]
+                    FetchUnit_Fetch_Stage2[&quot;Fetch_Stage2&quot;]
+                    FetchUnit_Fetch_Stage1[&quot;Fetch_Stage1&quot;]
                     subgraph TaggedCounter[&quot;perf_fetch_utilization TaggedCounter&quot;]
                         TaggedCounter__incr[&quot;_incr&quot;]
                     end
@@ -287,13 +287,13 @@
                         Semaphore_release[&quot;release&quot;]
                     end
                     subgraph Pipe[&quot;s1_s2_pipe Pipe&quot;]
-                        Pipe_write[&quot;write&quot;]
                         Pipe_read[&quot;read&quot;]
+                        Pipe_write[&quot;write&quot;]
                     end
                 end
                 subgraph ExceptionCauseRegister[&quot;exception_cause_register ExceptionCauseRegister&quot;]
-                    ExceptionCauseRegister_clear[&quot;clear&quot;]
                     ExceptionCauseRegister_get[&quot;get&quot;]
+                    ExceptionCauseRegister_clear[&quot;clear&quot;]
                     ExceptionCauseRegister_report[&quot;report&quot;]
                     subgraph BasicFifo5[&quot;fu_report_fifo BasicFifo&quot;]
                         BasicFifo5_read[&quot;read&quot;]
@@ -326,21 +326,21 @@
                         MethodProduct1_method[&quot;method&quot;]
                     end
                     subgraph RSFuncBlock[&quot;rs_block_0 RSFuncBlock&quot;]
-                        RSFuncBlock_select[&quot;select&quot;]
-                        RSFuncBlock_get_result[&quot;get_result&quot;]
                         RSFuncBlock_insert[&quot;insert&quot;]
                         RSFuncBlock_update[&quot;update&quot;]
+                        RSFuncBlock_select[&quot;select&quot;]
+                        RSFuncBlock_get_result[&quot;get_result&quot;]
                         subgraph RS[&quot;rs RS&quot;]
-                            RS_perf[&quot;perf&quot;]
+                            RS_insert[&quot;insert&quot;]
                             RS_RS[&quot;RS&quot;]
+                            RS_update[&quot;update&quot;]
                             RS_RS1[&quot;RS&quot;]
-                            RS_insert[&quot;insert&quot;]
+                            RS_perf[&quot;perf&quot;]
+                            RS_select[&quot;select&quot;]
                             RS_RS2[&quot;RS&quot;]
-                            RS_update[&quot;update&quot;]
                             RS_RS3[&quot;RS&quot;]
-                            RS_select[&quot;select&quot;]
-                            RS_take[&quot;take&quot;]
                             RS_RS4[&quot;RS&quot;]
+                            RS_take[&quot;take&quot;]
                             subgraph TaggedLatencyMeasurer1[&quot;perf_rs_wait_time TaggedLatencyMeasurer&quot;]
                                 TaggedLatencyMeasurer1__stop[&quot;_stop&quot;]
                                 TaggedLatencyMeasurer1__start[&quot;_start&quot;]
@@ -357,8 +357,8 @@
                             end
                         end
                         subgraph AluFuncUnit[&quot;func_unit_0 AluFuncUnit&quot;]
-                            AluFuncUnit_accept[&quot;accept&quot;]
                             AluFuncUnit_issue[&quot;issue&quot;]
+                            AluFuncUnit_accept[&quot;accept&quot;]
                             subgraph TaggedCounter1[&quot;perf_instr TaggedCounter&quot;]
                                 TaggedCounter1__incr[&quot;_incr&quot;]
                             end
@@ -371,8 +371,8 @@
                             WakeupSelect_WakeupSelect[&quot;WakeupSelect&quot;]
                         end
                         subgraph ShiftFuncUnit[&quot;func_unit_1 ShiftFuncUnit&quot;]
-                            ShiftFuncUnit_accept[&quot;accept&quot;]
                             ShiftFuncUnit_issue[&quot;issue&quot;]
+                            ShiftFuncUnit_accept[&quot;accept&quot;]
                             subgraph FIFO4[&quot;fifo FIFO&quot;]
                                 FIFO4_write[&quot;write&quot;]
                                 FIFO4_read[&quot;read&quot;]
@@ -382,11 +382,11 @@
                             WakeupSelect1_WakeupSelect[&quot;WakeupSelect&quot;]
                         end
                         subgraph JumpBranchFuncUnit[&quot;func_unit_2 JumpBranchFuncUnit&quot;]
-                            JumpBranchFuncUnit_accept[&quot;accept&quot;]
                             JumpBranchFuncUnit_issue[&quot;issue&quot;]
+                            JumpBranchFuncUnit_accept[&quot;accept&quot;]
                             subgraph FIFO5[&quot;fifo_branch_resolved FIFO&quot;]
-                                FIFO5_read[&quot;read&quot;]
                                 FIFO5_write[&quot;write&quot;]
+                                FIFO5_read[&quot;read&quot;]
                             end
                             subgraph TaggedCounter2[&quot;perf_instr TaggedCounter&quot;]
                                 TaggedCounter2__incr[&quot;_incr&quot;]
@@ -398,19 +398,19 @@
                                 HwCounter7__incr[&quot;_incr&quot;]
                             end
                             subgraph FIFO6[&quot;fifo_res FIFO&quot;]
-                                FIFO6_read[&quot;read&quot;]
                                 FIFO6_write[&quot;write&quot;]
+                                FIFO6_read[&quot;read&quot;]
                             end
                         end
                         subgraph WakeupSelect2[&quot;wakeup_select_2 WakeupSelect&quot;]
                             WakeupSelect2_WakeupSelect[&quot;WakeupSelect&quot;]
                         end
                         subgraph ExceptionFuncUnit[&quot;func_unit_3 ExceptionFuncUnit&quot;]
-                            ExceptionFuncUnit_issue[&quot;issue&quot;]
                             ExceptionFuncUnit_accept[&quot;accept&quot;]
+                            ExceptionFuncUnit_issue[&quot;issue&quot;]
                             subgraph FIFO7[&quot;fifo FIFO&quot;]
-                                FIFO7_read[&quot;read&quot;]
                                 FIFO7_write[&quot;write&quot;]
+                                FIFO7_read[&quot;read&quot;]
                             end
                         end
                         subgraph WakeupSelect3[&quot;wakeup_select_3 WakeupSelect&quot;]
@@ -418,14 +418,14 @@
                         end
                         subgraph PrivilegedFuncUnit[&quot;func_unit_4 PrivilegedFuncUnit&quot;]
                             PrivilegedFuncUnit_issue[&quot;issue&quot;]
-                            PrivilegedFuncUnit_precommit_cond2[&quot;precommit_cond2&quot;]
-                            PrivilegedFuncUnit_accept[&quot;accept&quot;]
                             PrivilegedFuncUnit_precommit_cond0[&quot;precommit_cond0&quot;]
+                            PrivilegedFuncUnit_accept[&quot;accept&quot;]
+                            PrivilegedFuncUnit_precommit_cond2[&quot;precommit_cond2&quot;]
                             PrivilegedFuncUnit_precommit[&quot;precommit&quot;]
                             PrivilegedFuncUnit_precommit_cond1[&quot;precommit_cond1&quot;]
                             subgraph BasicFifo6[&quot;fetch_resume_fifo BasicFifo&quot;]
-                                BasicFifo6_read[&quot;read&quot;]
                                 BasicFifo6_write[&quot;write&quot;]
+                                BasicFifo6_read[&quot;read&quot;]
                             end
                             subgraph TaggedCounter3[&quot;perf_instr TaggedCounter&quot;]
                                 TaggedCounter3__incr[&quot;_incr&quot;]
@@ -437,8 +437,8 @@
                         subgraph Collector1[&quot;collector Collector&quot;]
                             Collector1_method[&quot;method&quot;]
                             subgraph Forwarder5[&quot;forwarder Forwarder&quot;]
-                                Forwarder5_read[&quot;read&quot;]
                                 Forwarder5_write[&quot;write&quot;]
+                                Forwarder5_read[&quot;read&quot;]
                             end
                             subgraph ManyToOneConnectTrans1[&quot;connect ManyToOneConnectTrans&quot;]
                                 subgraph ConnectTrans5[&quot;ManyToOneConnectTrans_input_0 ConnectTrans&quot;]
@@ -462,18 +462,18 @@
                     subgraph RSFuncBlock1[&quot;rs_block_1 RSFuncBlock&quot;]
                         RSFuncBlock1_select[&quot;select&quot;]
                         RSFuncBlock1_insert[&quot;insert&quot;]
-                        RSFuncBlock1_get_result[&quot;get_result&quot;]
                         RSFuncBlock1_update[&quot;update&quot;]
+                        RSFuncBlock1_get_result[&quot;get_result&quot;]
                         subgraph FifoRS[&quot;rs FifoRS&quot;]
                             FifoRS_update[&quot;update&quot;]
                             FifoRS_select[&quot;select&quot;]
-                            FifoRS_FifoRS[&quot;FifoRS&quot;]
+                            FifoRS_insert[&quot;insert&quot;]
                             FifoRS_take[&quot;take&quot;]
                             FifoRS_perf[&quot;perf&quot;]
-                            FifoRS_insert[&quot;insert&quot;]
+                            FifoRS_FifoRS[&quot;FifoRS&quot;]
                             subgraph TaggedLatencyMeasurer2[&quot;perf_rs_wait_time TaggedLatencyMeasurer&quot;]
-                                TaggedLatencyMeasurer2__start[&quot;_start&quot;]
                                 TaggedLatencyMeasurer2__stop[&quot;_stop&quot;]
+                                TaggedLatencyMeasurer2__start[&quot;_start&quot;]
                                 subgraph HwExpHistogram7[&quot;histogram HwExpHistogram&quot;]
                                     HwExpHistogram7__add[&quot;_add&quot;]
                                 end
@@ -487,33 +487,33 @@
                             end
                         end
                         subgraph LSUDummy[&quot;func_unit_0 LSUDummy&quot;]
-                            LSUDummy_LSUDummy[&quot;LSUDummy&quot;]
-                            LSUDummy_issue[&quot;issue&quot;]
                             LSUDummy_accept[&quot;accept&quot;]
-                            LSUDummy_accept_cond1[&quot;accept_cond1&quot;]
-                            LSUDummy_precommit[&quot;precommit&quot;]
                             LSUDummy_accept_cond0[&quot;accept_cond0&quot;]
+                            LSUDummy_accept_cond1[&quot;accept_cond1&quot;]
+                            LSUDummy_LSUDummy[&quot;LSUDummy&quot;]
                             LSUDummy_LSUDummy1[&quot;LSUDummy&quot;]
+                            LSUDummy_issue[&quot;issue&quot;]
+                            LSUDummy_precommit[&quot;precommit&quot;]
                             subgraph LSURequester[&quot;requester LSURequester&quot;]
                                 LSURequester_accept[&quot;accept&quot;]
+                                LSURequester_issue_cond0[&quot;issue_cond0&quot;]
                                 LSURequester_issue[&quot;issue&quot;]
                                 LSURequester_issue_cond1[&quot;issue_cond1&quot;]
-                                LSURequester_issue_cond0[&quot;issue_cond0&quot;]
                                 LSURequester_accept_cond1[&quot;accept_cond1&quot;]
-                                LSURequester_accept_cond0[&quot;accept_cond0&quot;]
                                 LSURequester_issue_cond2[&quot;issue_cond2&quot;]
+                                LSURequester_accept_cond0[&quot;accept_cond0&quot;]
                             end
                             subgraph Forwarder6[&quot;requests Forwarder&quot;]
-                                Forwarder6_read[&quot;read&quot;]
                                 Forwarder6_write[&quot;write&quot;]
+                                Forwarder6_read[&quot;read&quot;]
                             end
                             subgraph FIFO8[&quot;results_noop FIFO&quot;]
                                 FIFO8_read[&quot;read&quot;]
                                 FIFO8_write[&quot;write&quot;]
                             end
                             subgraph FIFO9[&quot;issued FIFO&quot;]
-                                FIFO9_write[&quot;write&quot;]
                                 FIFO9_read[&quot;read&quot;]
+                                FIFO9_write[&quot;write&quot;]
                             end
                             subgraph FIFO10[&quot;issued_noop FIFO&quot;]
                                 FIFO10_read[&quot;read&quot;]
@@ -538,18 +538,18 @@
                     end
                     subgraph CSRUnit[&quot;rs_block_2 CSRUnit&quot;]
                         CSRUnit_CSRUnit[&quot;CSRUnit&quot;]
+                        CSRUnit_get_result[&quot;get_result&quot;]
                         CSRUnit_insert[&quot;insert&quot;]
-                        CSRUnit_select[&quot;select&quot;]
                         CSRUnit_update[&quot;update&quot;]
-                        CSRUnit_fetch_resume[&quot;fetch_resume&quot;]
                         CSRUnit_precommit[&quot;precommit&quot;]
-                        CSRUnit_get_result[&quot;get_result&quot;]
+                        CSRUnit_select[&quot;select&quot;]
+                        CSRUnit_fetch_resume[&quot;fetch_resume&quot;]
                     end
                     subgraph MethodTryProduct[&quot;InstructionPrecommitKey_unifier MethodTryProduct&quot;]
                         MethodTryProduct_MethodTryProduct[&quot;MethodTryProduct&quot;]
                         MethodTryProduct_MethodTryProduct1[&quot;MethodTryProduct&quot;]
-                        MethodTryProduct_method[&quot;method&quot;]
                         MethodTryProduct_MethodTryProduct2[&quot;MethodTryProduct&quot;]
+                        MethodTryProduct_method[&quot;method&quot;]
                     end
                     subgraph Collector3[&quot;FetchResumeKey_unifier Collector&quot;]
                         Collector3_method[&quot;method&quot;]
@@ -571,16 +571,16 @@
                     ResultAnnouncement_ResultAnnouncement[&quot;ResultAnnouncement&quot;]
                 end
                 subgraph InterruptController[&quot;interrupt_controller InterruptController&quot;]
-                    InterruptController_report_interrupt[&quot;report_interrupt&quot;]
-                    InterruptController_entry[&quot;entry&quot;]
                     InterruptController_mret[&quot;mret&quot;]
+                    InterruptController_entry[&quot;entry&quot;]
+                    InterruptController_report_interrupt[&quot;report_interrupt&quot;]
                 end
                 subgraph GenericCSRRegisters[&quot;csr_generic GenericCSRRegisters&quot;]
                     GenericCSRRegisters_GenericCSRRegisters[&quot;GenericCSRRegisters&quot;]
                     subgraph MachineModeCSRRegisters[&quot;m_mode MachineModeCSRRegisters&quot;]
                         subgraph CSRRegister[&quot;mcause CSRRegister&quot;]
-                            CSRRegister__internal_fu_read[&quot;_internal_fu_read&quot;]
                             CSRRegister__internal_fu_write[&quot;_internal_fu_write&quot;]
+                            CSRRegister__internal_fu_read[&quot;_internal_fu_read&quot;]
                             CSRRegister_write[&quot;write&quot;]
                             subgraph MethodMap1[&quot;fu_write_map MethodMap&quot;]
                                 MethodMap1_method[&quot;method&quot;]
@@ -593,9 +593,9 @@
                             end
                         end
                         subgraph CSRRegister1[&quot;mtvec CSRRegister&quot;]
+                            CSRRegister1_read[&quot;read&quot;]
                             CSRRegister1__internal_fu_read[&quot;_internal_fu_read&quot;]
                             CSRRegister1__internal_fu_write[&quot;_internal_fu_write&quot;]
-                            CSRRegister1_read[&quot;read&quot;]
                             subgraph MethodMap3[&quot;fu_write_map MethodMap&quot;]
                                 MethodMap3_method[&quot;method&quot;]
                             end
@@ -609,8 +609,8 @@
                         subgraph CSRRegister2[&quot;mepc CSRRegister&quot;]
                             CSRRegister2__internal_fu_read[&quot;_internal_fu_read&quot;]
                             CSRRegister2_read[&quot;read&quot;]
-                            CSRRegister2__internal_fu_write[&quot;_internal_fu_write&quot;]
                             CSRRegister2_write[&quot;write&quot;]
+                            CSRRegister2__internal_fu_write[&quot;_internal_fu_write&quot;]
                             subgraph MethodMap5[&quot;fu_write_map MethodMap&quot;]
                                 MethodMap5_method[&quot;method&quot;]
                             end
@@ -662,8 +662,8 @@
                     end
                 end
                 subgraph FIFO11[&quot;fifo_decode FIFO&quot;]
-                    FIFO11_write[&quot;write&quot;]
                     FIFO11_read[&quot;read&quot;]
+                    FIFO11_write[&quot;write&quot;]
                 end
                 subgraph DecodeStage[&quot;decode DecodeStage&quot;]
                     DecodeStage_DecodeStage[&quot;DecodeStage&quot;]
@@ -680,8 +680,8 @@
                         RegAllocation_RegAllocation[&quot;RegAllocation&quot;]
                     end
                     subgraph Connect[&quot;rename_out_buf Connect&quot;]
-                        Connect_read[&quot;read&quot;]
                         Connect_write[&quot;write&quot;]
+                        Connect_read[&quot;read&quot;]
                     end
                     subgraph Renaming[&quot;renaming Renaming&quot;]
                         Renaming_Renaming[&quot;Renaming&quot;]
@@ -713,25 +713,25 @@
                     Retirement_core_state[&quot;core_state&quot;]
                     Retirement_Retirement[&quot;Retirement&quot;]
                     Retirement_Retirement1[&quot;Retirement&quot;]
+                    Retirement_Retirement_cond1[&quot;Retirement_cond1&quot;]
+                    Retirement_Retirement_cond0[&quot;Retirement_cond0&quot;]
                     Retirement_Retirement2[&quot;Retirement&quot;]
                     Retirement_Retirement3[&quot;Retirement&quot;]
-                    Retirement_Retirement_cond0[&quot;Retirement_cond0&quot;]
-                    Retirement_Retirement_cond1[&quot;Retirement_cond1&quot;]
                     Retirement_Retirement4[&quot;Retirement&quot;]
                     subgraph DoubleCounterCSR2[&quot;instret_csr DoubleCounterCSR&quot;]
                         DoubleCounterCSR2_increment[&quot;increment&quot;]
                         subgraph CSRRegister7[&quot;register_low CSRRegister&quot;]
                             CSRRegister7__internal_fu_read[&quot;_internal_fu_read&quot;]
-                            CSRRegister7_read[&quot;read&quot;]
                             CSRRegister7_write[&quot;write&quot;]
+                            CSRRegister7_read[&quot;read&quot;]
                             subgraph MethodMap16[&quot;fu_read_map MethodMap&quot;]
                                 MethodMap16_method[&quot;method&quot;]
                             end
                         end
                         subgraph CSRRegister8[&quot;register_high CSRRegister&quot;]
+                            CSRRegister8__internal_fu_read[&quot;_internal_fu_read&quot;]
                             CSRRegister8_read[&quot;read&quot;]
                             CSRRegister8_write[&quot;write&quot;]
-                            CSRRegister8__internal_fu_read[&quot;_internal_fu_read&quot;]
                             subgraph MethodMap18[&quot;fu_read_map MethodMap&quot;]
                                 MethodMap18_method[&quot;method&quot;]
                             end
@@ -754,39 +754,39 @@
             end
         end
         subgraph TransactionManager[&quot;transactionManager TransactionManager&quot;]
-            TransactionManager_MethodTryProduct_precommit_cond0[&quot;MethodTryProduct_precommit_cond0&quot;]
-            TransactionManager_accept_cond0_ConnectTrans_accept_cond0[&quot;accept_cond0_ConnectTrans_accept_cond0&quot;]
-            TransactionManager_Retirement_cond0_Retirement[&quot;Retirement_cond0_Retirement&quot;]
+            TransactionManager_ConnectTrans_accept_cond1[&quot;ConnectTrans_accept_cond1&quot;]
+            TransactionManager_Retirement_Retirement_cond0[&quot;Retirement_Retirement_cond0&quot;]
+            TransactionManager_precommit_cond0_MethodTryProduct[&quot;precommit_cond0_MethodTryProduct&quot;]
+            TransactionManager_LSUDummy_issue_cond2[&quot;LSUDummy_issue_cond2&quot;]
+            TransactionManager_issue_cond1_LSUDummy[&quot;issue_cond1_LSUDummy&quot;]
             TransactionManager_ROBAllocation_Renaming[&quot;ROBAllocation_Renaming&quot;]
+            TransactionManager_accept_cond0_ConnectTrans_accept_cond1[&quot;accept_cond0_ConnectTrans_accept_cond1&quot;]
+            TransactionManager_accept_cond0_ConnectTrans_accept_cond0[&quot;accept_cond0_ConnectTrans_accept_cond0&quot;]
+            TransactionManager_Retirement_Retirement_cond1[&quot;Retirement_Retirement_cond1&quot;]
+            TransactionManager_precommit_cond1_MethodTryProduct[&quot;precommit_cond1_MethodTryProduct&quot;]
             TransactionManager_MethodTryProduct_precommit_cond2[&quot;MethodTryProduct_precommit_cond2&quot;]
-            TransactionManager_issue_cond1_LSUDummy[&quot;issue_cond1_LSUDummy&quot;]
-            TransactionManager_issue_cond0_LSUDummy[&quot;issue_cond0_LSUDummy&quot;]
-            TransactionManager_LSUDummy_issue_cond2[&quot;LSUDummy_issue_cond2&quot;]
-            TransactionManager_MethodTryProduct_precommit_cond1[&quot;MethodTryProduct_precommit_cond1&quot;]
-            TransactionManager_Retirement_cond1_Retirement[&quot;Retirement_cond1_Retirement&quot;]
-            TransactionManager_ConnectTrans_accept_cond1[&quot;ConnectTrans_accept_cond1&quot;]
-            TransactionManager_accept_cond0_accept_cond1_ConnectTrans[&quot;accept_cond0_accept_cond1_ConnectTrans&quot;]
+            TransactionManager_LSUDummy_issue_cond0[&quot;LSUDummy_issue_cond0&quot;]
         end
     end
 Core_InitFreeRFFifo --&gt; BasicFifo2_write
-Retirement_Retirement --&gt; BasicFifo2_write
-TransactionManager_Retirement_cond1_Retirement --&gt; BasicFifo2_write
-TransactionManager_Retirement_cond0_Retirement --&gt; BasicFifo2_write
+Retirement_Retirement2 --&gt; BasicFifo2_write
+TransactionManager_Retirement_Retirement_cond1 --&gt; BasicFifo2_write
+TransactionManager_Retirement_Retirement_cond0 --&gt; BasicFifo2_write
 FIFO5_read --&gt; Core_DiscardBranchVerify
 WishboneMaster_WishboneMaster --&gt; Forwarder_write
 WishboneMaster1_WishboneMaster --&gt; Forwarder1_write
 RegisterFile_perf --&gt; HwExpHistogram2__add
 ReorderBuffer_perf --&gt; HwExpHistogram4__add
-SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; WishboneMasterAdapter_request_read
-SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; Serializer_Serializer1
-SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; BasicFifo_write
-SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; WishboneMaster_request
-WishboneMasterAdapter_get_read_response --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-Serializer_Serializer --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-BasicFifo_read --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-WishboneMaster_result --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-Forwarder_read --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --&gt; Forwarder2_write
+SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --&gt; WishboneMasterAdapter_request_read
+SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --&gt; Serializer_Serializer
+SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --&gt; BasicFifo_write
+SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --&gt; WishboneMaster_request
+WishboneMasterAdapter_get_read_response --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+Serializer_Serializer1 --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+BasicFifo_read --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+WishboneMaster_result --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+Forwarder_read --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; Forwarder2_write
 ICache_ICache &lt;--&gt; HwCounter4__incr
 ArgumentsToResultsZipper_peek_arg --&gt; ICache_MemRead
 BasicFifo3_peek --&gt; ICache_MemRead
@@ -835,16 +835,16 @@
 FIFO11_read --&gt; RegAllocation_RegAllocation
 BasicFifo2_read --&gt; RegAllocation_RegAllocation
 RegAllocation_RegAllocation --&gt; FIFO12_write
-FIFO13_read --&gt; RSSelection_RSSelection
 FIFO13_read --&gt; RSSelection_RSSelection2
+FIFO13_read --&gt; RSSelection_RSSelection
 FIFO13_read --&gt; RSSelection_RSSelection1
-RSFuncBlock_select --&gt; RSSelection_RSSelection
-RS_select --&gt; RSSelection_RSSelection
-RSSelection_RSSelection --&gt; FIFO14_write
+RSFuncBlock_select --&gt; RSSelection_RSSelection2
+RS_select --&gt; RSSelection_RSSelection2
 RSSelection_RSSelection2 --&gt; FIFO14_write
+RSSelection_RSSelection --&gt; FIFO14_write
 RSSelection_RSSelection1 --&gt; FIFO14_write
-RSFuncBlock1_select --&gt; RSSelection_RSSelection2
-FifoRS_select --&gt; RSSelection_RSSelection2
+RSFuncBlock1_select --&gt; RSSelection_RSSelection
+FifoRS_select --&gt; RSSelection_RSSelection
 RSSelection_RSSelection1 &lt;--&gt; CSRUnit_select
 FIFO14_read --&gt; RSInsertion_RSInsertion
 RegisterFile_read1 --&gt; RSInsertion_RSInsertion
@@ -867,7 +867,7 @@
 Collector3_method --&gt; ConnectTrans13_ConnectTrans
 Forwarder8_read --&gt; ConnectTrans13_ConnectTrans
 ConnectTrans13_ConnectTrans --&gt; FetchUnit_resume
-Retirement_Retirement4 --&gt; FetchUnit_resume
+Retirement_Retirement --&gt; FetchUnit_resume
 Collector_method --&gt; ResultAnnouncement_ResultAnnouncement
 Forwarder4_read --&gt; ResultAnnouncement_ResultAnnouncement
 ResultAnnouncement_ResultAnnouncement --&gt; ReorderBuffer_mark_done
@@ -881,7 +881,7 @@
 ResultAnnouncement_ResultAnnouncement --&gt; FifoRS_update
 ResultAnnouncement_ResultAnnouncement --&gt; CSRUnit_update
 RS_perf --&gt; HwExpHistogram6__add
-RS_RS2 --&gt; WakeupSelect_WakeupSelect
+RS_RS4 --&gt; WakeupSelect_WakeupSelect
 RS_take --&gt; WakeupSelect_WakeupSelect
 RS_take --&gt; WakeupSelect1_WakeupSelect
 RS_take --&gt; WakeupSelect2_WakeupSelect
@@ -905,10 +905,10 @@
 WakeupSelect_WakeupSelect --&gt; AluFuncUnit_issue
 WakeupSelect_WakeupSelect --&gt; TaggedCounter1__incr
 WakeupSelect_WakeupSelect --&gt; FIFO3_write
-RS_RS --&gt; WakeupSelect1_WakeupSelect
+RS_RS1 --&gt; WakeupSelect1_WakeupSelect
 WakeupSelect1_WakeupSelect --&gt; ShiftFuncUnit_issue
 WakeupSelect1_WakeupSelect --&gt; FIFO4_write
-RS_RS3 --&gt; WakeupSelect2_WakeupSelect
+RS_RS --&gt; WakeupSelect2_WakeupSelect
 WakeupSelect2_WakeupSelect --&gt; JumpBranchFuncUnit_issue
 WakeupSelect2_WakeupSelect --&gt; TaggedCounter2__incr
 WakeupSelect2_WakeupSelect &lt;--&gt; HwCounter7__incr
@@ -917,15 +917,15 @@
 WakeupSelect3_WakeupSelect --&gt; BasicFifo5_write
 ConnectTrans9_ConnectTrans --&gt; BasicFifo5_write
 ConnectTrans4_ConnectTrans --&gt; BasicFifo5_write
-TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --&gt; BasicFifo5_write
-TransactionManager_accept_cond0_accept_cond1_ConnectTrans --&gt; BasicFifo5_write
 TransactionManager_ConnectTrans_accept_cond1 --&gt; BasicFifo5_write
+TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --&gt; BasicFifo5_write
+TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --&gt; BasicFifo5_write
 WakeupSelect2_WakeupSelect --&gt; FIFO6_write
 WakeupSelect2_WakeupSelect --&gt; FIFO5_write
-RS_RS1 --&gt; WakeupSelect3_WakeupSelect
+RS_RS3 --&gt; WakeupSelect3_WakeupSelect
 WakeupSelect3_WakeupSelect --&gt; ExceptionFuncUnit_issue
 WakeupSelect3_WakeupSelect --&gt; FIFO7_write
-RS_RS4 --&gt; WakeupSelect4_WakeupSelect
+RS_RS2 --&gt; WakeupSelect4_WakeupSelect
 WakeupSelect4_WakeupSelect --&gt; PrivilegedFuncUnit_issue
 ConnectTrans5_ConnectTrans --&gt; Forwarder5_write
 ConnectTrans6_ConnectTrans --&gt; Forwarder5_write
@@ -945,19 +945,19 @@
 ConnectTrans9_ConnectTrans --&gt; BasicFifo6_write
 FifoRS_perf --&gt; HwExpHistogram8__add
 Forwarder6_read --&gt; LSUDummy_LSUDummy1
-Forwarder6_read --&gt; TransactionManager_issue_cond1_LSUDummy
 Forwarder6_read --&gt; TransactionManager_LSUDummy_issue_cond2
-Forwarder6_read --&gt; TransactionManager_issue_cond0_LSUDummy
+Forwarder6_read --&gt; TransactionManager_LSUDummy_issue_cond0
+Forwarder6_read --&gt; TransactionManager_issue_cond1_LSUDummy
 LSUDummy_LSUDummy1 --&gt; FIFO8_write
 WakeupSelect5_WakeupSelect --&gt; FIFO8_write
-TransactionManager_issue_cond1_LSUDummy --&gt; FIFO8_write
 TransactionManager_LSUDummy_issue_cond2 --&gt; FIFO8_write
-TransactionManager_issue_cond0_LSUDummy --&gt; FIFO8_write
+TransactionManager_LSUDummy_issue_cond0 --&gt; FIFO8_write
+TransactionManager_issue_cond1_LSUDummy --&gt; FIFO8_write
 LSUDummy_LSUDummy1 --&gt; FIFO10_write
 WakeupSelect5_WakeupSelect --&gt; FIFO10_write
-TransactionManager_issue_cond1_LSUDummy --&gt; FIFO10_write
 TransactionManager_LSUDummy_issue_cond2 --&gt; FIFO10_write
-TransactionManager_issue_cond0_LSUDummy --&gt; FIFO10_write
+TransactionManager_LSUDummy_issue_cond0 --&gt; FIFO10_write
+TransactionManager_issue_cond1_LSUDummy --&gt; FIFO10_write
 FifoRS_FifoRS --&gt; WakeupSelect5_WakeupSelect
 FifoRS_take --&gt; WakeupSelect5_WakeupSelect
 WakeupSelect5_WakeupSelect --&gt; TaggedLatencyMeasurer2__stop
@@ -1002,55 +1002,55 @@
 Collector2_method --&gt; ConnectTrans3_ConnectTrans
 Forwarder7_read --&gt; ConnectTrans3_ConnectTrans
 CSRUnit_get_result --&gt; ConnectTrans4_ConnectTrans
-MethodTryProduct_MethodTryProduct2 --&gt; LSUDummy_precommit
-MethodTryProduct_MethodTryProduct --&gt; CSRUnit_precommit
+MethodTryProduct_MethodTryProduct1 --&gt; LSUDummy_precommit
+MethodTryProduct_MethodTryProduct2 --&gt; CSRUnit_precommit
 ConnectTrans11_ConnectTrans --&gt; Forwarder8_write
 ConnectTrans12_ConnectTrans --&gt; Forwarder8_write
 BasicFifo6_read --&gt; ConnectTrans11_ConnectTrans
 CSRUnit_fetch_resume --&gt; ConnectTrans12_ConnectTrans
+ReorderBuffer_peek --&gt; Retirement_Retirement4
+ReorderBuffer_peek --&gt; Retirement_Retirement3
 ReorderBuffer_peek --&gt; Retirement_Retirement2
-ReorderBuffer_peek --&gt; Retirement_Retirement1
-ReorderBuffer_peek --&gt; Retirement_Retirement
-ReorderBuffer_peek --&gt; TransactionManager_Retirement_cond1_Retirement
-ReorderBuffer_peek --&gt; TransactionManager_Retirement_cond0_Retirement
-Retirement_Retirement2 --&gt; MethodTryProduct_method
-ExceptionCauseRegister_get --&gt; Retirement_Retirement1
-ExceptionCauseRegister_get --&gt; TransactionManager_Retirement_cond1_Retirement
-ExceptionCauseRegister_get --&gt; TransactionManager_Retirement_cond0_Retirement
-Retirement_Retirement &lt;--&gt; ReorderBuffer_retire
-TransactionManager_Retirement_cond1_Retirement &lt;--&gt; ReorderBuffer_retire
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; ReorderBuffer_retire
-Retirement_Retirement &lt;--&gt; FIFOLatencyMeasurer1__stop
-TransactionManager_Retirement_cond1_Retirement &lt;--&gt; FIFOLatencyMeasurer1__stop
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; FIFOLatencyMeasurer1__stop
-FIFO2_read --&gt; Retirement_Retirement
-FIFO2_read --&gt; TransactionManager_Retirement_cond1_Retirement
-FIFO2_read --&gt; TransactionManager_Retirement_cond0_Retirement
-Retirement_Retirement --&gt; HwExpHistogram3__add
-TransactionManager_Retirement_cond1_Retirement --&gt; HwExpHistogram3__add
-TransactionManager_Retirement_cond0_Retirement --&gt; HwExpHistogram3__add
-CoreInstructionCounter_decrement --&gt; Retirement_Retirement
-CoreInstructionCounter_decrement --&gt; TransactionManager_Retirement_cond1_Retirement
-CoreInstructionCounter_decrement --&gt; TransactionManager_Retirement_cond0_Retirement
-RRAT_peek --&gt; Retirement_Retirement
-RRAT_peek --&gt; TransactionManager_Retirement_cond1_Retirement
-Retirement_Retirement --&gt; RegisterFile_free
-TransactionManager_Retirement_cond1_Retirement --&gt; RegisterFile_free
-TransactionManager_Retirement_cond0_Retirement --&gt; RegisterFile_free
-Retirement_Retirement --&gt; TaggedLatencyMeasurer__stop
-TransactionManager_Retirement_cond1_Retirement --&gt; TaggedLatencyMeasurer__stop
-TransactionManager_Retirement_cond0_Retirement --&gt; TaggedLatencyMeasurer__stop
-AsyncMemoryBank_read --&gt; Retirement_Retirement
-AsyncMemoryBank_read --&gt; TransactionManager_Retirement_cond1_Retirement
-AsyncMemoryBank_read --&gt; TransactionManager_Retirement_cond0_Retirement
-Retirement_Retirement --&gt; HwExpHistogram1__add
-TransactionManager_Retirement_cond1_Retirement --&gt; HwExpHistogram1__add
-TransactionManager_Retirement_cond0_Retirement --&gt; HwExpHistogram1__add
-Retirement_Retirement --&gt; FRAT_rename
-TransactionManager_Retirement_cond1_Retirement --&gt; FRAT_rename
+ReorderBuffer_peek --&gt; TransactionManager_Retirement_Retirement_cond1
+ReorderBuffer_peek --&gt; TransactionManager_Retirement_Retirement_cond0
+Retirement_Retirement4 --&gt; MethodTryProduct_method
+ExceptionCauseRegister_get --&gt; Retirement_Retirement3
+ExceptionCauseRegister_get --&gt; TransactionManager_Retirement_Retirement_cond1
+ExceptionCauseRegister_get --&gt; TransactionManager_Retirement_Retirement_cond0
+Retirement_Retirement2 &lt;--&gt; ReorderBuffer_retire
+TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; ReorderBuffer_retire
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; ReorderBuffer_retire
+Retirement_Retirement2 &lt;--&gt; FIFOLatencyMeasurer1__stop
+TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; FIFOLatencyMeasurer1__stop
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; FIFOLatencyMeasurer1__stop
+FIFO2_read --&gt; Retirement_Retirement2
+FIFO2_read --&gt; TransactionManager_Retirement_Retirement_cond1
+FIFO2_read --&gt; TransactionManager_Retirement_Retirement_cond0
+Retirement_Retirement2 --&gt; HwExpHistogram3__add
+TransactionManager_Retirement_Retirement_cond1 --&gt; HwExpHistogram3__add
+TransactionManager_Retirement_Retirement_cond0 --&gt; HwExpHistogram3__add
+CoreInstructionCounter_decrement --&gt; Retirement_Retirement2
+CoreInstructionCounter_decrement --&gt; TransactionManager_Retirement_Retirement_cond1
+CoreInstructionCounter_decrement --&gt; TransactionManager_Retirement_Retirement_cond0
+RRAT_peek --&gt; Retirement_Retirement2
+RRAT_peek --&gt; TransactionManager_Retirement_Retirement_cond1
+Retirement_Retirement2 --&gt; RegisterFile_free
+TransactionManager_Retirement_Retirement_cond1 --&gt; RegisterFile_free
+TransactionManager_Retirement_Retirement_cond0 --&gt; RegisterFile_free
+Retirement_Retirement2 --&gt; TaggedLatencyMeasurer__stop
+TransactionManager_Retirement_Retirement_cond1 --&gt; TaggedLatencyMeasurer__stop
+TransactionManager_Retirement_Retirement_cond0 --&gt; TaggedLatencyMeasurer__stop
+AsyncMemoryBank_read --&gt; Retirement_Retirement2
+AsyncMemoryBank_read --&gt; TransactionManager_Retirement_Retirement_cond1
+AsyncMemoryBank_read --&gt; TransactionManager_Retirement_Retirement_cond0
+Retirement_Retirement2 --&gt; HwExpHistogram1__add
+TransactionManager_Retirement_Retirement_cond1 --&gt; HwExpHistogram1__add
+TransactionManager_Retirement_Retirement_cond0 --&gt; HwExpHistogram1__add
+Retirement_Retirement2 --&gt; FRAT_rename
 TransactionManager_ROBAllocation_Renaming --&gt; FRAT_rename
-CSRRegister1_read --&gt; Retirement_Retirement4
-Retirement_Retirement4 &lt;--&gt; ExceptionCauseRegister_clear
+TransactionManager_Retirement_Retirement_cond1 --&gt; FRAT_rename
+CSRRegister1_read --&gt; Retirement_Retirement
+Retirement_Retirement &lt;--&gt; ExceptionCauseRegister_clear
 GenericCSRRegisters_GenericCSRRegisters &lt;--&gt; DoubleCounterCSR_increment
 CSRRegister3_read --&gt; GenericCSRRegisters_GenericCSRRegisters
 GenericCSRRegisters_GenericCSRRegisters --&gt; CSRRegister3_write
@@ -1062,78 +1062,17 @@
 CSRRegister6_read --&gt; GenericCSRRegisters_GenericCSRRegisters
 GenericCSRRegisters_GenericCSRRegisters --&gt; CSRRegister6_write
 AdapterTrans1_AdapterTrans_report_interrupt &lt;--&gt; InterruptController_report_interrupt
-TransactionManager_MethodTryProduct_precommit_cond1 &lt;--&gt; MethodTryProduct_MethodTryProduct1
-TransactionManager_MethodTryProduct_precommit_cond2 &lt;--&gt; MethodTryProduct_MethodTryProduct1
-TransactionManager_MethodTryProduct_precommit_cond0 &lt;--&gt; MethodTryProduct_MethodTryProduct1
-TransactionManager_MethodTryProduct_precommit_cond1 --&gt; PrivilegedFuncUnit_precommit
+TransactionManager_MethodTryProduct_precommit_cond2 &lt;--&gt; MethodTryProduct_MethodTryProduct
+TransactionManager_precommit_cond0_MethodTryProduct &lt;--&gt; MethodTryProduct_MethodTryProduct
+TransactionManager_precommit_cond1_MethodTryProduct &lt;--&gt; MethodTryProduct_MethodTryProduct
 TransactionManager_MethodTryProduct_precommit_cond2 --&gt; PrivilegedFuncUnit_precommit
-TransactionManager_MethodTryProduct_precommit_cond0 --&gt; PrivilegedFuncUnit_precommit
-TransactionManager_MethodTryProduct_precommit_cond1 --&gt; TaggedCounter3__incr
+TransactionManager_precommit_cond0_MethodTryProduct --&gt; PrivilegedFuncUnit_precommit
+TransactionManager_precommit_cond1_MethodTryProduct --&gt; PrivilegedFuncUnit_precommit
 TransactionManager_MethodTryProduct_precommit_cond2 --&gt; TaggedCounter3__incr
-TransactionManager_MethodTryProduct_precommit_cond0 --&gt; TaggedCounter3__incr
-TransactionManager_MethodTryProduct_precommit_cond1 &lt;--&gt; PrivilegedFuncUnit_precommit_cond1
-TransactionManager_MethodTryProduct_precommit_cond1 &lt;--&gt; InterruptController_mret
-TransactionManager_issue_cond1_LSUDummy &lt;--&gt; LSURequester_issue_cond1
-TransactionManager_issue_cond1_LSUDummy --&gt; WishboneMasterAdapter1_request_read
-TransactionManager_issue_cond1_LSUDummy --&gt; Serializer1_Serializer
-TransactionManager_issue_cond1_LSUDummy --&gt; BasicFifo1_write
-TransactionManager_issue_cond0_LSUDummy --&gt; BasicFifo1_write
-TransactionManager_issue_cond1_LSUDummy --&gt; WishboneMaster1_request
-TransactionManager_issue_cond0_LSUDummy --&gt; WishboneMaster1_request
-TransactionManager_issue_cond1_LSUDummy &lt;--&gt; LSUDummy_LSUDummy
-TransactionManager_LSUDummy_issue_cond2 &lt;--&gt; LSUDummy_LSUDummy
-TransactionManager_issue_cond0_LSUDummy &lt;--&gt; LSUDummy_LSUDummy
-TransactionManager_issue_cond1_LSUDummy --&gt; LSURequester_issue
-TransactionManager_LSUDummy_issue_cond2 --&gt; LSURequester_issue
-TransactionManager_issue_cond0_LSUDummy --&gt; LSURequester_issue
-TransactionManager_issue_cond1_LSUDummy --&gt; FIFO9_write
-TransactionManager_LSUDummy_issue_cond2 --&gt; FIFO9_write
-TransactionManager_issue_cond0_LSUDummy --&gt; FIFO9_write
+TransactionManager_precommit_cond0_MethodTryProduct --&gt; TaggedCounter3__incr
+TransactionManager_precommit_cond1_MethodTryProduct --&gt; TaggedCounter3__incr
 TransactionManager_MethodTryProduct_precommit_cond2 &lt;--&gt; PrivilegedFuncUnit_precommit_cond2
 TransactionManager_MethodTryProduct_precommit_cond2 &lt;--&gt; ICache_flush
-TransactionManager_LSUDummy_issue_cond2 &lt;--&gt; LSURequester_issue_cond2
-TransactionManager_Retirement_cond1_Retirement &lt;--&gt; Retirement_Retirement_cond1
-TransactionManager_Retirement_cond1_Retirement &lt;--&gt; Retirement_Retirement3
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; Retirement_Retirement3
-TransactionManager_Retirement_cond1_Retirement --&gt; CSRRegister_write
-TransactionManager_Retirement_cond0_Retirement --&gt; CSRRegister_write
-TransactionManager_Retirement_cond1_Retirement --&gt; CSRRegister2_write
-TransactionManager_Retirement_cond0_Retirement --&gt; CSRRegister2_write
-TransactionManager_Retirement_cond1_Retirement &lt;--&gt; InterruptController_entry
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; InterruptController_entry
-TransactionManager_MethodTryProduct_precommit_cond0 &lt;--&gt; PrivilegedFuncUnit_precommit_cond0
-TransactionManager_accept_cond0_ConnectTrans_accept_cond0 &lt;--&gt; LSUDummy_accept_cond0
-TransactionManager_accept_cond0_accept_cond1_ConnectTrans &lt;--&gt; LSUDummy_accept_cond0
-LSURequester_accept --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-LSURequester_accept --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-FIFO9_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-FIFO9_read --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-TransactionManager_accept_cond0_ConnectTrans_accept_cond0 &lt;--&gt; ConnectTrans10_ConnectTrans
-TransactionManager_accept_cond0_accept_cond1_ConnectTrans &lt;--&gt; ConnectTrans10_ConnectTrans
-TransactionManager_ConnectTrans_accept_cond1 &lt;--&gt; ConnectTrans10_ConnectTrans
-TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --&gt; Forwarder7_write
-TransactionManager_accept_cond0_accept_cond1_ConnectTrans --&gt; Forwarder7_write
-TransactionManager_ConnectTrans_accept_cond1 --&gt; Forwarder7_write
-LSUDummy_accept --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-LSUDummy_accept --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-LSUDummy_accept --&gt; TransactionManager_ConnectTrans_accept_cond1
-TransactionManager_accept_cond0_ConnectTrans_accept_cond0 &lt;--&gt; LSURequester_accept_cond0
-WishboneMasterAdapter1_get_write_response --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-Serializer1_Serializer2 --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-BasicFifo1_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-BasicFifo1_read --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-WishboneMaster1_result --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-WishboneMaster1_result --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-Forwarder1_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-Forwarder1_read --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; Retirement_Retirement_cond0
-TransactionManager_Retirement_cond0_Retirement --&gt; RRAT_commit
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; DoubleCounterCSR2_increment
-CSRRegister7_read --&gt; TransactionManager_Retirement_cond0_Retirement
-TransactionManager_Retirement_cond0_Retirement --&gt; CSRRegister7_write
-CSRRegister8_read --&gt; TransactionManager_Retirement_cond0_Retirement
-TransactionManager_Retirement_cond0_Retirement --&gt; CSRRegister8_write
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; HwCounter9__incr
 TransactionManager_ROBAllocation_Renaming &lt;--&gt; ROBAllocation_ROBAllocation
 Connect_read --&gt; TransactionManager_ROBAllocation_Renaming
 TransactionManager_ROBAllocation_Renaming --&gt; ReorderBuffer_put
@@ -1143,15 +1082,76 @@
 TransactionManager_ROBAllocation_Renaming &lt;--&gt; Renaming_Renaming
 FIFO12_read --&gt; TransactionManager_ROBAllocation_Renaming
 TransactionManager_ROBAllocation_Renaming --&gt; Connect_write
-TransactionManager_accept_cond0_accept_cond1_ConnectTrans &lt;--&gt; LSURequester_accept_cond1
-WishboneMasterAdapter1_get_read_response --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-Serializer1_Serializer1 --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-TransactionManager_issue_cond0_LSUDummy &lt;--&gt; LSURequester_issue_cond0
-TransactionManager_issue_cond0_LSUDummy --&gt; WishboneMasterAdapter1_request_write
-TransactionManager_issue_cond0_LSUDummy --&gt; Serializer1_Serializer3
+TransactionManager_precommit_cond0_MethodTryProduct &lt;--&gt; PrivilegedFuncUnit_precommit_cond0
+TransactionManager_ConnectTrans_accept_cond1 &lt;--&gt; ConnectTrans10_ConnectTrans
+TransactionManager_accept_cond0_ConnectTrans_accept_cond0 &lt;--&gt; ConnectTrans10_ConnectTrans
+TransactionManager_accept_cond0_ConnectTrans_accept_cond1 &lt;--&gt; ConnectTrans10_ConnectTrans
+TransactionManager_ConnectTrans_accept_cond1 --&gt; Forwarder7_write
+TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --&gt; Forwarder7_write
+TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --&gt; Forwarder7_write
+LSUDummy_accept --&gt; TransactionManager_ConnectTrans_accept_cond1
+LSUDummy_accept --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+LSUDummy_accept --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
 TransactionManager_ConnectTrans_accept_cond1 &lt;--&gt; LSUDummy_accept_cond1
 FIFO8_read --&gt; TransactionManager_ConnectTrans_accept_cond1
 FIFO10_read --&gt; TransactionManager_ConnectTrans_accept_cond1
+TransactionManager_LSUDummy_issue_cond2 &lt;--&gt; LSUDummy_LSUDummy
+TransactionManager_LSUDummy_issue_cond0 &lt;--&gt; LSUDummy_LSUDummy
+TransactionManager_issue_cond1_LSUDummy &lt;--&gt; LSUDummy_LSUDummy
+TransactionManager_LSUDummy_issue_cond2 --&gt; LSURequester_issue
+TransactionManager_LSUDummy_issue_cond0 --&gt; LSURequester_issue
+TransactionManager_issue_cond1_LSUDummy --&gt; LSURequester_issue
+TransactionManager_LSUDummy_issue_cond2 --&gt; FIFO9_write
+TransactionManager_LSUDummy_issue_cond0 --&gt; FIFO9_write
+TransactionManager_issue_cond1_LSUDummy --&gt; FIFO9_write
+TransactionManager_LSUDummy_issue_cond2 &lt;--&gt; LSURequester_issue_cond2
+TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; Retirement_Retirement1
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; Retirement_Retirement1
+TransactionManager_Retirement_Retirement_cond1 --&gt; CSRRegister_write
+TransactionManager_Retirement_Retirement_cond0 --&gt; CSRRegister_write
+TransactionManager_Retirement_Retirement_cond1 --&gt; CSRRegister2_write
+TransactionManager_Retirement_Retirement_cond0 --&gt; CSRRegister2_write
+TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; InterruptController_entry
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; InterruptController_entry
+TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; Retirement_Retirement_cond1
+TransactionManager_accept_cond0_ConnectTrans_accept_cond0 &lt;--&gt; LSUDummy_accept_cond0
+TransactionManager_accept_cond0_ConnectTrans_accept_cond1 &lt;--&gt; LSUDummy_accept_cond0
+LSURequester_accept --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+LSURequester_accept --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+FIFO9_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+FIFO9_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+TransactionManager_accept_cond0_ConnectTrans_accept_cond0 &lt;--&gt; LSURequester_accept_cond0
+WishboneMasterAdapter1_get_write_response --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+Serializer1_Serializer --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+BasicFifo1_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+BasicFifo1_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+WishboneMaster1_result --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+WishboneMaster1_result --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+Forwarder1_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+Forwarder1_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+TransactionManager_LSUDummy_issue_cond0 &lt;--&gt; LSURequester_issue_cond0
+TransactionManager_LSUDummy_issue_cond0 --&gt; WishboneMasterAdapter1_request_write
+TransactionManager_LSUDummy_issue_cond0 --&gt; Serializer1_Serializer1
+TransactionManager_LSUDummy_issue_cond0 --&gt; BasicFifo1_write
+TransactionManager_issue_cond1_LSUDummy --&gt; BasicFifo1_write
+TransactionManager_LSUDummy_issue_cond0 --&gt; WishboneMaster1_request
+TransactionManager_issue_cond1_LSUDummy --&gt; WishboneMaster1_request
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; Retirement_Retirement_cond0
+TransactionManager_Retirement_Retirement_cond0 --&gt; RRAT_commit
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; DoubleCounterCSR2_increment
+CSRRegister7_read --&gt; TransactionManager_Retirement_Retirement_cond0
+TransactionManager_Retirement_Retirement_cond0 --&gt; CSRRegister7_write
+CSRRegister8_read --&gt; TransactionManager_Retirement_Retirement_cond0
+TransactionManager_Retirement_Retirement_cond0 --&gt; CSRRegister8_write
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; HwCounter9__incr
+TransactionManager_precommit_cond1_MethodTryProduct &lt;--&gt; PrivilegedFuncUnit_precommit_cond1
+TransactionManager_precommit_cond1_MethodTryProduct &lt;--&gt; InterruptController_mret
+TransactionManager_issue_cond1_LSUDummy &lt;--&gt; LSURequester_issue_cond1
+TransactionManager_issue_cond1_LSUDummy --&gt; WishboneMasterAdapter1_request_read
+TransactionManager_issue_cond1_LSUDummy --&gt; Serializer1_Serializer3
+TransactionManager_accept_cond0_ConnectTrans_accept_cond1 &lt;--&gt; LSURequester_accept_cond1
+WishboneMasterAdapter1_get_read_response --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+Serializer1_Serializer2 --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
         </div>
 
            </div>
@@ -1162,7 +1162,7 @@
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/components/icache.html b/components/icache.html
index cc2cd4c77..e0745e173 100644
--- a/components/icache.html
+++ b/components/icache.html
@@ -131,7 +131,7 @@ <h2>Address mapping example<a class="headerlink" href="#address-mapping-example"
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.backend.html b/coreblocks.backend.html
index 077817996..edbac404d 100644
--- a/coreblocks.backend.html
+++ b/coreblocks.backend.html
@@ -165,7 +165,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.cache.html b/coreblocks.cache.html
index 120257135..230a9b2d9 100644
--- a/coreblocks.cache.html
+++ b/coreblocks.cache.html
@@ -241,7 +241,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html
index e25e405a1..4e0ca3fe4 100644
--- a/coreblocks.core_structs.html
+++ b/coreblocks.core_structs.html
@@ -157,7 +157,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html
index 672c210f4..90efa58a7 100644
--- a/coreblocks.frontend.decoder.html
+++ b/coreblocks.frontend.decoder.html
@@ -1758,7 +1758,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html
index eec166ebf..967de928b 100644
--- a/coreblocks.frontend.fetch.html
+++ b/coreblocks.frontend.fetch.html
@@ -181,7 +181,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html
index 915e58ea5..2bede66a6 100644
--- a/coreblocks.frontend.html
+++ b/coreblocks.frontend.html
@@ -125,7 +125,7 @@ <h2>Subpackages<a class="headerlink" href="#subpackages" title="Permalink to thi
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html
index c92df9f57..36036b5f1 100644
--- a/coreblocks.func_blocks.fu.html
+++ b/coreblocks.func_blocks.fu.html
@@ -879,7 +879,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.func_blocks.fu.lsu.html b/coreblocks.func_blocks.fu.lsu.html
index 7839cc817..7497d91bc 100644
--- a/coreblocks.func_blocks.fu.lsu.html
+++ b/coreblocks.func_blocks.fu.lsu.html
@@ -231,7 +231,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html
index 2253958dc..722ba940e 100644
--- a/coreblocks.func_blocks.fu.unsigned_multiplication.html
+++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html
@@ -238,7 +238,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html
index 60adb08be..0a4d95861 100644
--- a/coreblocks.func_blocks.html
+++ b/coreblocks.func_blocks.html
@@ -148,7 +148,7 @@ <h2>Subpackages<a class="headerlink" href="#subpackages" title="Permalink to thi
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html
index 81941ec53..f3a3e9657 100644
--- a/coreblocks.func_blocks.interface.html
+++ b/coreblocks.func_blocks.interface.html
@@ -169,7 +169,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.html b/coreblocks.html
index 53ded9865..bc4830a18 100644
--- a/coreblocks.html
+++ b/coreblocks.html
@@ -248,7 +248,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.params.html b/coreblocks.params.html
index 94c5a72b4..86d33bb73 100644
--- a/coreblocks.params.html
+++ b/coreblocks.params.html
@@ -1171,7 +1171,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html
index fa9d2b0e3..fc6d02066 100644
--- a/coreblocks.peripherals.html
+++ b/coreblocks.peripherals.html
@@ -746,7 +746,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html
index d9879917b..d07ed2e1b 100644
--- a/coreblocks.priv.csr.html
+++ b/coreblocks.priv.csr.html
@@ -303,7 +303,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.priv.html b/coreblocks.priv.html
index e4f9ba856..61d502504 100644
--- a/coreblocks.priv.html
+++ b/coreblocks.priv.html
@@ -123,7 +123,7 @@ <h2>Subpackages<a class="headerlink" href="#subpackages" title="Permalink to thi
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html
index cf4c452c5..58a84dfb1 100644
--- a/coreblocks.priv.traps.html
+++ b/coreblocks.priv.traps.html
@@ -171,7 +171,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html
index 8db756d82..4414a9ced 100644
--- a/coreblocks.scheduler.html
+++ b/coreblocks.scheduler.html
@@ -191,7 +191,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/current-graph.html b/current-graph.html
index 1f4521728..ea27cf8f5 100644
--- a/current-graph.html
+++ b/current-graph.html
@@ -92,8 +92,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                 Core_DiscardBranchVerify[&quot;DiscardBranchVerify&quot;]
                 Core_InitFreeRFFifo[&quot;InitFreeRFFifo&quot;]
                 subgraph WishboneMaster[&quot;wb_master_instr WishboneMaster&quot;]
-                    WishboneMaster_WishboneMaster[&quot;WishboneMaster&quot;]
                     WishboneMaster_request[&quot;request&quot;]
+                    WishboneMaster_WishboneMaster[&quot;WishboneMaster&quot;]
                     WishboneMaster_result[&quot;result&quot;]
                     subgraph Forwarder[&quot;result Forwarder&quot;]
                         Forwarder_write[&quot;write&quot;]
@@ -102,16 +102,16 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                 end
                 subgraph WishboneMaster1[&quot;wb_master_data WishboneMaster&quot;]
                     WishboneMaster1_WishboneMaster[&quot;WishboneMaster&quot;]
-                    WishboneMaster1_request[&quot;request&quot;]
                     WishboneMaster1_result[&quot;result&quot;]
+                    WishboneMaster1_request[&quot;request&quot;]
                     subgraph Forwarder1[&quot;result Forwarder&quot;]
                         Forwarder1_read[&quot;read&quot;]
                         Forwarder1_write[&quot;write&quot;]
                     end
                 end
                 subgraph WishboneMasterAdapter[&quot;bus_master_instr_adapter WishboneMasterAdapter&quot;]
-                    WishboneMasterAdapter_get_read_response[&quot;get_read_response&quot;]
                     WishboneMasterAdapter_request_read[&quot;request_read&quot;]
+                    WishboneMasterAdapter_get_read_response[&quot;get_read_response&quot;]
                     subgraph Serializer[&quot;bus_serializer Serializer&quot;]
                         Serializer_Serializer[&quot;Serializer&quot;]
                         Serializer_Serializer1[&quot;Serializer&quot;]
@@ -122,8 +122,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     end
                 end
                 subgraph WishboneMasterAdapter1[&quot;bus_master_data_adapter WishboneMasterAdapter&quot;]
-                    WishboneMasterAdapter1_get_write_response[&quot;get_write_response&quot;]
                     WishboneMasterAdapter1_get_read_response[&quot;get_read_response&quot;]
+                    WishboneMasterAdapter1_get_write_response[&quot;get_write_response&quot;]
                     WishboneMasterAdapter1_request_read[&quot;request_read&quot;]
                     WishboneMasterAdapter1_request_write[&quot;request_write&quot;]
                     subgraph Serializer1[&quot;bus_serializer Serializer&quot;]
@@ -142,8 +142,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     CoreInstructionCounter_increment[&quot;increment&quot;]
                 end
                 subgraph FIFO[&quot;fifo_fetch FIFO&quot;]
-                    FIFO_read[&quot;read&quot;]
                     FIFO_write[&quot;write&quot;]
+                    FIFO_read[&quot;read&quot;]
                 end
                 subgraph MethodMap[&quot;core_counter_increment_discard_map MethodMap&quot;]
                     MethodMap_method[&quot;method&quot;]
@@ -156,22 +156,22 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     BasicFifo2_write[&quot;write&quot;]
                 end
                 subgraph SimpleCommonBusCacheRefiller[&quot;icache_refiller SimpleCommonBusCacheRefiller&quot;]
-                    SimpleCommonBusCacheRefiller_accept_refill[&quot;accept_refill&quot;]
                     SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller[&quot;SimpleCommonBusCacheRefiller&quot;]
-                    SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1[&quot;SimpleCommonBusCacheRefiller&quot;]
                     SimpleCommonBusCacheRefiller_start_refill[&quot;start_refill&quot;]
+                    SimpleCommonBusCacheRefiller_accept_refill[&quot;accept_refill&quot;]
+                    SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1[&quot;SimpleCommonBusCacheRefiller&quot;]
                     subgraph Forwarder2[&quot;resp_fwd Forwarder&quot;]
-                        Forwarder2_read[&quot;read&quot;]
                         Forwarder2_write[&quot;write&quot;]
+                        Forwarder2_read[&quot;read&quot;]
                     end
                 end
                 subgraph ICache[&quot;icache ICache&quot;]
-                    ICache_ICache[&quot;ICache&quot;]
+                    ICache_issue_req[&quot;issue_req&quot;]
+                    ICache_flush[&quot;flush&quot;]
                     ICache_MemRead[&quot;MemRead&quot;]
                     ICache_accept_res[&quot;accept_res&quot;]
+                    ICache_ICache[&quot;ICache&quot;]
                     ICache_ICache1[&quot;ICache&quot;]
-                    ICache_flush[&quot;flush&quot;]
-                    ICache_issue_req[&quot;issue_req&quot;]
                     subgraph HwCounter[&quot;perf_loads HwCounter&quot;]
                         HwCounter__incr[&quot;_incr&quot;]
                     end
@@ -188,8 +188,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         HwCounter4__incr[&quot;_incr&quot;]
                     end
                     subgraph FIFOLatencyMeasurer[&quot;req_latency FIFOLatencyMeasurer&quot;]
-                        FIFOLatencyMeasurer__stop[&quot;_stop&quot;]
                         FIFOLatencyMeasurer__start[&quot;_start&quot;]
+                        FIFOLatencyMeasurer__stop[&quot;_stop&quot;]
                         subgraph HwExpHistogram[&quot;histogram HwExpHistogram&quot;]
                             HwExpHistogram__add[&quot;_add&quot;]
                         end
@@ -200,9 +200,9 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     end
                     subgraph ArgumentsToResultsZipper[&quot;req_zipper ArgumentsToResultsZipper&quot;]
                         ArgumentsToResultsZipper_peek_arg[&quot;peek_arg&quot;]
-                        ArgumentsToResultsZipper_read[&quot;read&quot;]
                         ArgumentsToResultsZipper_write_args[&quot;write_args&quot;]
                         ArgumentsToResultsZipper_write_results[&quot;write_results&quot;]
+                        ArgumentsToResultsZipper_read[&quot;read&quot;]
                         subgraph BasicFifo3[&quot;fifo BasicFifo&quot;]
                             BasicFifo3_read[&quot;read&quot;]
                             BasicFifo3_peek[&quot;peek&quot;]
@@ -218,15 +218,15 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     FRAT_rename[&quot;rename&quot;]
                 end
                 subgraph RRAT[&quot;RRAT RRAT&quot;]
-                    RRAT_peek[&quot;peek&quot;]
                     RRAT_commit[&quot;commit&quot;]
+                    RRAT_peek[&quot;peek&quot;]
                 end
                 subgraph RegisterFile[&quot;RF RegisterFile&quot;]
                     RegisterFile_perf[&quot;perf&quot;]
+                    RegisterFile_read2[&quot;read2&quot;]
                     RegisterFile_free[&quot;free&quot;]
                     RegisterFile_read1[&quot;read1&quot;]
                     RegisterFile_write[&quot;write&quot;]
-                    RegisterFile_read2[&quot;read2&quot;]
                     subgraph TaggedLatencyMeasurer[&quot;perf_rf_valid_time TaggedLatencyMeasurer&quot;]
                         TaggedLatencyMeasurer__start[&quot;_start&quot;]
                         TaggedLatencyMeasurer__stop[&quot;_stop&quot;]
@@ -234,8 +234,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                             HwExpHistogram1__add[&quot;_add&quot;]
                         end
                         subgraph AsyncMemoryBank[&quot;slots AsyncMemoryBank&quot;]
-                            AsyncMemoryBank_write[&quot;write&quot;]
                             AsyncMemoryBank_read[&quot;read&quot;]
+                            AsyncMemoryBank_write[&quot;write&quot;]
                         end
                     end
                     subgraph HwExpHistogram2[&quot;perf_num_valid HwExpHistogram&quot;]
@@ -243,12 +243,12 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     end
                 end
                 subgraph ReorderBuffer[&quot;ROB ReorderBuffer&quot;]
-                    ReorderBuffer_perf[&quot;perf&quot;]
                     ReorderBuffer_mark_done[&quot;mark_done&quot;]
                     ReorderBuffer_put[&quot;put&quot;]
                     ReorderBuffer_peek[&quot;peek&quot;]
                     ReorderBuffer_retire[&quot;retire&quot;]
                     ReorderBuffer_get_indices[&quot;get_indices&quot;]
+                    ReorderBuffer_perf[&quot;perf&quot;]
                     subgraph FIFOLatencyMeasurer1[&quot;perf_rob_wait_time FIFOLatencyMeasurer&quot;]
                         FIFOLatencyMeasurer1__start[&quot;_start&quot;]
                         FIFOLatencyMeasurer1__stop[&quot;_stop&quot;]
@@ -256,8 +256,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                             HwExpHistogram3__add[&quot;_add&quot;]
                         end
                         subgraph FIFO2[&quot;fifo FIFO&quot;]
-                            FIFO2_read[&quot;read&quot;]
                             FIFO2_write[&quot;write&quot;]
+                            FIFO2_read[&quot;read&quot;]
                         end
                     end
                     subgraph HwExpHistogram4[&quot;perf_rob_size HwExpHistogram&quot;]
@@ -265,11 +265,11 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     end
                 end
                 subgraph FetchUnit[&quot;fetch FetchUnit&quot;]
-                    FetchUnit_Fetch_Stage1[&quot;Fetch_Stage1&quot;]
                     FetchUnit_resume[&quot;resume&quot;]
                     FetchUnit_stall_exception[&quot;stall_exception&quot;]
-                    FetchUnit_Fetch_Stage2[&quot;Fetch_Stage2&quot;]
                     FetchUnit_Fetch_Stage0[&quot;Fetch_Stage0&quot;]
+                    FetchUnit_Fetch_Stage2[&quot;Fetch_Stage2&quot;]
+                    FetchUnit_Fetch_Stage1[&quot;Fetch_Stage1&quot;]
                     subgraph TaggedCounter[&quot;perf_fetch_utilization TaggedCounter&quot;]
                         TaggedCounter__incr[&quot;_incr&quot;]
                     end
@@ -293,13 +293,13 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         Semaphore_release[&quot;release&quot;]
                     end
                     subgraph Pipe[&quot;s1_s2_pipe Pipe&quot;]
-                        Pipe_write[&quot;write&quot;]
                         Pipe_read[&quot;read&quot;]
+                        Pipe_write[&quot;write&quot;]
                     end
                 end
                 subgraph ExceptionCauseRegister[&quot;exception_cause_register ExceptionCauseRegister&quot;]
-                    ExceptionCauseRegister_clear[&quot;clear&quot;]
                     ExceptionCauseRegister_get[&quot;get&quot;]
+                    ExceptionCauseRegister_clear[&quot;clear&quot;]
                     ExceptionCauseRegister_report[&quot;report&quot;]
                     subgraph BasicFifo5[&quot;fu_report_fifo BasicFifo&quot;]
                         BasicFifo5_read[&quot;read&quot;]
@@ -332,21 +332,21 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         MethodProduct1_method[&quot;method&quot;]
                     end
                     subgraph RSFuncBlock[&quot;rs_block_0 RSFuncBlock&quot;]
-                        RSFuncBlock_select[&quot;select&quot;]
-                        RSFuncBlock_get_result[&quot;get_result&quot;]
                         RSFuncBlock_insert[&quot;insert&quot;]
                         RSFuncBlock_update[&quot;update&quot;]
+                        RSFuncBlock_select[&quot;select&quot;]
+                        RSFuncBlock_get_result[&quot;get_result&quot;]
                         subgraph RS[&quot;rs RS&quot;]
-                            RS_perf[&quot;perf&quot;]
+                            RS_insert[&quot;insert&quot;]
                             RS_RS[&quot;RS&quot;]
+                            RS_update[&quot;update&quot;]
                             RS_RS1[&quot;RS&quot;]
-                            RS_insert[&quot;insert&quot;]
+                            RS_perf[&quot;perf&quot;]
+                            RS_select[&quot;select&quot;]
                             RS_RS2[&quot;RS&quot;]
-                            RS_update[&quot;update&quot;]
                             RS_RS3[&quot;RS&quot;]
-                            RS_select[&quot;select&quot;]
-                            RS_take[&quot;take&quot;]
                             RS_RS4[&quot;RS&quot;]
+                            RS_take[&quot;take&quot;]
                             subgraph TaggedLatencyMeasurer1[&quot;perf_rs_wait_time TaggedLatencyMeasurer&quot;]
                                 TaggedLatencyMeasurer1__stop[&quot;_stop&quot;]
                                 TaggedLatencyMeasurer1__start[&quot;_start&quot;]
@@ -363,8 +363,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                             end
                         end
                         subgraph AluFuncUnit[&quot;func_unit_0 AluFuncUnit&quot;]
-                            AluFuncUnit_accept[&quot;accept&quot;]
                             AluFuncUnit_issue[&quot;issue&quot;]
+                            AluFuncUnit_accept[&quot;accept&quot;]
                             subgraph TaggedCounter1[&quot;perf_instr TaggedCounter&quot;]
                                 TaggedCounter1__incr[&quot;_incr&quot;]
                             end
@@ -377,8 +377,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                             WakeupSelect_WakeupSelect[&quot;WakeupSelect&quot;]
                         end
                         subgraph ShiftFuncUnit[&quot;func_unit_1 ShiftFuncUnit&quot;]
-                            ShiftFuncUnit_accept[&quot;accept&quot;]
                             ShiftFuncUnit_issue[&quot;issue&quot;]
+                            ShiftFuncUnit_accept[&quot;accept&quot;]
                             subgraph FIFO4[&quot;fifo FIFO&quot;]
                                 FIFO4_write[&quot;write&quot;]
                                 FIFO4_read[&quot;read&quot;]
@@ -388,11 +388,11 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                             WakeupSelect1_WakeupSelect[&quot;WakeupSelect&quot;]
                         end
                         subgraph JumpBranchFuncUnit[&quot;func_unit_2 JumpBranchFuncUnit&quot;]
-                            JumpBranchFuncUnit_accept[&quot;accept&quot;]
                             JumpBranchFuncUnit_issue[&quot;issue&quot;]
+                            JumpBranchFuncUnit_accept[&quot;accept&quot;]
                             subgraph FIFO5[&quot;fifo_branch_resolved FIFO&quot;]
-                                FIFO5_read[&quot;read&quot;]
                                 FIFO5_write[&quot;write&quot;]
+                                FIFO5_read[&quot;read&quot;]
                             end
                             subgraph TaggedCounter2[&quot;perf_instr TaggedCounter&quot;]
                                 TaggedCounter2__incr[&quot;_incr&quot;]
@@ -404,19 +404,19 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                                 HwCounter7__incr[&quot;_incr&quot;]
                             end
                             subgraph FIFO6[&quot;fifo_res FIFO&quot;]
-                                FIFO6_read[&quot;read&quot;]
                                 FIFO6_write[&quot;write&quot;]
+                                FIFO6_read[&quot;read&quot;]
                             end
                         end
                         subgraph WakeupSelect2[&quot;wakeup_select_2 WakeupSelect&quot;]
                             WakeupSelect2_WakeupSelect[&quot;WakeupSelect&quot;]
                         end
                         subgraph ExceptionFuncUnit[&quot;func_unit_3 ExceptionFuncUnit&quot;]
-                            ExceptionFuncUnit_issue[&quot;issue&quot;]
                             ExceptionFuncUnit_accept[&quot;accept&quot;]
+                            ExceptionFuncUnit_issue[&quot;issue&quot;]
                             subgraph FIFO7[&quot;fifo FIFO&quot;]
-                                FIFO7_read[&quot;read&quot;]
                                 FIFO7_write[&quot;write&quot;]
+                                FIFO7_read[&quot;read&quot;]
                             end
                         end
                         subgraph WakeupSelect3[&quot;wakeup_select_3 WakeupSelect&quot;]
@@ -424,14 +424,14 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         end
                         subgraph PrivilegedFuncUnit[&quot;func_unit_4 PrivilegedFuncUnit&quot;]
                             PrivilegedFuncUnit_issue[&quot;issue&quot;]
-                            PrivilegedFuncUnit_precommit_cond2[&quot;precommit_cond2&quot;]
-                            PrivilegedFuncUnit_accept[&quot;accept&quot;]
                             PrivilegedFuncUnit_precommit_cond0[&quot;precommit_cond0&quot;]
+                            PrivilegedFuncUnit_accept[&quot;accept&quot;]
+                            PrivilegedFuncUnit_precommit_cond2[&quot;precommit_cond2&quot;]
                             PrivilegedFuncUnit_precommit[&quot;precommit&quot;]
                             PrivilegedFuncUnit_precommit_cond1[&quot;precommit_cond1&quot;]
                             subgraph BasicFifo6[&quot;fetch_resume_fifo BasicFifo&quot;]
-                                BasicFifo6_read[&quot;read&quot;]
                                 BasicFifo6_write[&quot;write&quot;]
+                                BasicFifo6_read[&quot;read&quot;]
                             end
                             subgraph TaggedCounter3[&quot;perf_instr TaggedCounter&quot;]
                                 TaggedCounter3__incr[&quot;_incr&quot;]
@@ -443,8 +443,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         subgraph Collector1[&quot;collector Collector&quot;]
                             Collector1_method[&quot;method&quot;]
                             subgraph Forwarder5[&quot;forwarder Forwarder&quot;]
-                                Forwarder5_read[&quot;read&quot;]
                                 Forwarder5_write[&quot;write&quot;]
+                                Forwarder5_read[&quot;read&quot;]
                             end
                             subgraph ManyToOneConnectTrans1[&quot;connect ManyToOneConnectTrans&quot;]
                                 subgraph ConnectTrans5[&quot;ManyToOneConnectTrans_input_0 ConnectTrans&quot;]
@@ -468,18 +468,18 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     subgraph RSFuncBlock1[&quot;rs_block_1 RSFuncBlock&quot;]
                         RSFuncBlock1_select[&quot;select&quot;]
                         RSFuncBlock1_insert[&quot;insert&quot;]
-                        RSFuncBlock1_get_result[&quot;get_result&quot;]
                         RSFuncBlock1_update[&quot;update&quot;]
+                        RSFuncBlock1_get_result[&quot;get_result&quot;]
                         subgraph FifoRS[&quot;rs FifoRS&quot;]
                             FifoRS_update[&quot;update&quot;]
                             FifoRS_select[&quot;select&quot;]
-                            FifoRS_FifoRS[&quot;FifoRS&quot;]
+                            FifoRS_insert[&quot;insert&quot;]
                             FifoRS_take[&quot;take&quot;]
                             FifoRS_perf[&quot;perf&quot;]
-                            FifoRS_insert[&quot;insert&quot;]
+                            FifoRS_FifoRS[&quot;FifoRS&quot;]
                             subgraph TaggedLatencyMeasurer2[&quot;perf_rs_wait_time TaggedLatencyMeasurer&quot;]
-                                TaggedLatencyMeasurer2__start[&quot;_start&quot;]
                                 TaggedLatencyMeasurer2__stop[&quot;_stop&quot;]
+                                TaggedLatencyMeasurer2__start[&quot;_start&quot;]
                                 subgraph HwExpHistogram7[&quot;histogram HwExpHistogram&quot;]
                                     HwExpHistogram7__add[&quot;_add&quot;]
                                 end
@@ -493,33 +493,33 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                             end
                         end
                         subgraph LSUDummy[&quot;func_unit_0 LSUDummy&quot;]
-                            LSUDummy_LSUDummy[&quot;LSUDummy&quot;]
-                            LSUDummy_issue[&quot;issue&quot;]
                             LSUDummy_accept[&quot;accept&quot;]
-                            LSUDummy_accept_cond1[&quot;accept_cond1&quot;]
-                            LSUDummy_precommit[&quot;precommit&quot;]
                             LSUDummy_accept_cond0[&quot;accept_cond0&quot;]
+                            LSUDummy_accept_cond1[&quot;accept_cond1&quot;]
+                            LSUDummy_LSUDummy[&quot;LSUDummy&quot;]
                             LSUDummy_LSUDummy1[&quot;LSUDummy&quot;]
+                            LSUDummy_issue[&quot;issue&quot;]
+                            LSUDummy_precommit[&quot;precommit&quot;]
                             subgraph LSURequester[&quot;requester LSURequester&quot;]
                                 LSURequester_accept[&quot;accept&quot;]
+                                LSURequester_issue_cond0[&quot;issue_cond0&quot;]
                                 LSURequester_issue[&quot;issue&quot;]
                                 LSURequester_issue_cond1[&quot;issue_cond1&quot;]
-                                LSURequester_issue_cond0[&quot;issue_cond0&quot;]
                                 LSURequester_accept_cond1[&quot;accept_cond1&quot;]
-                                LSURequester_accept_cond0[&quot;accept_cond0&quot;]
                                 LSURequester_issue_cond2[&quot;issue_cond2&quot;]
+                                LSURequester_accept_cond0[&quot;accept_cond0&quot;]
                             end
                             subgraph Forwarder6[&quot;requests Forwarder&quot;]
-                                Forwarder6_read[&quot;read&quot;]
                                 Forwarder6_write[&quot;write&quot;]
+                                Forwarder6_read[&quot;read&quot;]
                             end
                             subgraph FIFO8[&quot;results_noop FIFO&quot;]
                                 FIFO8_read[&quot;read&quot;]
                                 FIFO8_write[&quot;write&quot;]
                             end
                             subgraph FIFO9[&quot;issued FIFO&quot;]
-                                FIFO9_write[&quot;write&quot;]
                                 FIFO9_read[&quot;read&quot;]
+                                FIFO9_write[&quot;write&quot;]
                             end
                             subgraph FIFO10[&quot;issued_noop FIFO&quot;]
                                 FIFO10_read[&quot;read&quot;]
@@ -544,18 +544,18 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     end
                     subgraph CSRUnit[&quot;rs_block_2 CSRUnit&quot;]
                         CSRUnit_CSRUnit[&quot;CSRUnit&quot;]
+                        CSRUnit_get_result[&quot;get_result&quot;]
                         CSRUnit_insert[&quot;insert&quot;]
-                        CSRUnit_select[&quot;select&quot;]
                         CSRUnit_update[&quot;update&quot;]
-                        CSRUnit_fetch_resume[&quot;fetch_resume&quot;]
                         CSRUnit_precommit[&quot;precommit&quot;]
-                        CSRUnit_get_result[&quot;get_result&quot;]
+                        CSRUnit_select[&quot;select&quot;]
+                        CSRUnit_fetch_resume[&quot;fetch_resume&quot;]
                     end
                     subgraph MethodTryProduct[&quot;InstructionPrecommitKey_unifier MethodTryProduct&quot;]
                         MethodTryProduct_MethodTryProduct[&quot;MethodTryProduct&quot;]
                         MethodTryProduct_MethodTryProduct1[&quot;MethodTryProduct&quot;]
-                        MethodTryProduct_method[&quot;method&quot;]
                         MethodTryProduct_MethodTryProduct2[&quot;MethodTryProduct&quot;]
+                        MethodTryProduct_method[&quot;method&quot;]
                     end
                     subgraph Collector3[&quot;FetchResumeKey_unifier Collector&quot;]
                         Collector3_method[&quot;method&quot;]
@@ -577,16 +577,16 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     ResultAnnouncement_ResultAnnouncement[&quot;ResultAnnouncement&quot;]
                 end
                 subgraph InterruptController[&quot;interrupt_controller InterruptController&quot;]
-                    InterruptController_report_interrupt[&quot;report_interrupt&quot;]
-                    InterruptController_entry[&quot;entry&quot;]
                     InterruptController_mret[&quot;mret&quot;]
+                    InterruptController_entry[&quot;entry&quot;]
+                    InterruptController_report_interrupt[&quot;report_interrupt&quot;]
                 end
                 subgraph GenericCSRRegisters[&quot;csr_generic GenericCSRRegisters&quot;]
                     GenericCSRRegisters_GenericCSRRegisters[&quot;GenericCSRRegisters&quot;]
                     subgraph MachineModeCSRRegisters[&quot;m_mode MachineModeCSRRegisters&quot;]
                         subgraph CSRRegister[&quot;mcause CSRRegister&quot;]
-                            CSRRegister__internal_fu_read[&quot;_internal_fu_read&quot;]
                             CSRRegister__internal_fu_write[&quot;_internal_fu_write&quot;]
+                            CSRRegister__internal_fu_read[&quot;_internal_fu_read&quot;]
                             CSRRegister_write[&quot;write&quot;]
                             subgraph MethodMap1[&quot;fu_write_map MethodMap&quot;]
                                 MethodMap1_method[&quot;method&quot;]
@@ -599,9 +599,9 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                             end
                         end
                         subgraph CSRRegister1[&quot;mtvec CSRRegister&quot;]
+                            CSRRegister1_read[&quot;read&quot;]
                             CSRRegister1__internal_fu_read[&quot;_internal_fu_read&quot;]
                             CSRRegister1__internal_fu_write[&quot;_internal_fu_write&quot;]
-                            CSRRegister1_read[&quot;read&quot;]
                             subgraph MethodMap3[&quot;fu_write_map MethodMap&quot;]
                                 MethodMap3_method[&quot;method&quot;]
                             end
@@ -615,8 +615,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         subgraph CSRRegister2[&quot;mepc CSRRegister&quot;]
                             CSRRegister2__internal_fu_read[&quot;_internal_fu_read&quot;]
                             CSRRegister2_read[&quot;read&quot;]
-                            CSRRegister2__internal_fu_write[&quot;_internal_fu_write&quot;]
                             CSRRegister2_write[&quot;write&quot;]
+                            CSRRegister2__internal_fu_write[&quot;_internal_fu_write&quot;]
                             subgraph MethodMap5[&quot;fu_write_map MethodMap&quot;]
                                 MethodMap5_method[&quot;method&quot;]
                             end
@@ -668,8 +668,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     end
                 end
                 subgraph FIFO11[&quot;fifo_decode FIFO&quot;]
-                    FIFO11_write[&quot;write&quot;]
                     FIFO11_read[&quot;read&quot;]
+                    FIFO11_write[&quot;write&quot;]
                 end
                 subgraph DecodeStage[&quot;decode DecodeStage&quot;]
                     DecodeStage_DecodeStage[&quot;DecodeStage&quot;]
@@ -686,8 +686,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         RegAllocation_RegAllocation[&quot;RegAllocation&quot;]
                     end
                     subgraph Connect[&quot;rename_out_buf Connect&quot;]
-                        Connect_read[&quot;read&quot;]
                         Connect_write[&quot;write&quot;]
+                        Connect_read[&quot;read&quot;]
                     end
                     subgraph Renaming[&quot;renaming Renaming&quot;]
                         Renaming_Renaming[&quot;Renaming&quot;]
@@ -719,25 +719,25 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     Retirement_core_state[&quot;core_state&quot;]
                     Retirement_Retirement[&quot;Retirement&quot;]
                     Retirement_Retirement1[&quot;Retirement&quot;]
+                    Retirement_Retirement_cond1[&quot;Retirement_cond1&quot;]
+                    Retirement_Retirement_cond0[&quot;Retirement_cond0&quot;]
                     Retirement_Retirement2[&quot;Retirement&quot;]
                     Retirement_Retirement3[&quot;Retirement&quot;]
-                    Retirement_Retirement_cond0[&quot;Retirement_cond0&quot;]
-                    Retirement_Retirement_cond1[&quot;Retirement_cond1&quot;]
                     Retirement_Retirement4[&quot;Retirement&quot;]
                     subgraph DoubleCounterCSR2[&quot;instret_csr DoubleCounterCSR&quot;]
                         DoubleCounterCSR2_increment[&quot;increment&quot;]
                         subgraph CSRRegister7[&quot;register_low CSRRegister&quot;]
                             CSRRegister7__internal_fu_read[&quot;_internal_fu_read&quot;]
-                            CSRRegister7_read[&quot;read&quot;]
                             CSRRegister7_write[&quot;write&quot;]
+                            CSRRegister7_read[&quot;read&quot;]
                             subgraph MethodMap16[&quot;fu_read_map MethodMap&quot;]
                                 MethodMap16_method[&quot;method&quot;]
                             end
                         end
                         subgraph CSRRegister8[&quot;register_high CSRRegister&quot;]
+                            CSRRegister8__internal_fu_read[&quot;_internal_fu_read&quot;]
                             CSRRegister8_read[&quot;read&quot;]
                             CSRRegister8_write[&quot;write&quot;]
-                            CSRRegister8__internal_fu_read[&quot;_internal_fu_read&quot;]
                             subgraph MethodMap18[&quot;fu_read_map MethodMap&quot;]
                                 MethodMap18_method[&quot;method&quot;]
                             end
@@ -760,39 +760,39 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
             end
         end
         subgraph TransactionManager[&quot;transactionManager TransactionManager&quot;]
-            TransactionManager_MethodTryProduct_precommit_cond0[&quot;MethodTryProduct_precommit_cond0&quot;]
-            TransactionManager_accept_cond0_ConnectTrans_accept_cond0[&quot;accept_cond0_ConnectTrans_accept_cond0&quot;]
-            TransactionManager_Retirement_cond0_Retirement[&quot;Retirement_cond0_Retirement&quot;]
+            TransactionManager_ConnectTrans_accept_cond1[&quot;ConnectTrans_accept_cond1&quot;]
+            TransactionManager_Retirement_Retirement_cond0[&quot;Retirement_Retirement_cond0&quot;]
+            TransactionManager_precommit_cond0_MethodTryProduct[&quot;precommit_cond0_MethodTryProduct&quot;]
+            TransactionManager_LSUDummy_issue_cond2[&quot;LSUDummy_issue_cond2&quot;]
+            TransactionManager_issue_cond1_LSUDummy[&quot;issue_cond1_LSUDummy&quot;]
             TransactionManager_ROBAllocation_Renaming[&quot;ROBAllocation_Renaming&quot;]
+            TransactionManager_accept_cond0_ConnectTrans_accept_cond1[&quot;accept_cond0_ConnectTrans_accept_cond1&quot;]
+            TransactionManager_accept_cond0_ConnectTrans_accept_cond0[&quot;accept_cond0_ConnectTrans_accept_cond0&quot;]
+            TransactionManager_Retirement_Retirement_cond1[&quot;Retirement_Retirement_cond1&quot;]
+            TransactionManager_precommit_cond1_MethodTryProduct[&quot;precommit_cond1_MethodTryProduct&quot;]
             TransactionManager_MethodTryProduct_precommit_cond2[&quot;MethodTryProduct_precommit_cond2&quot;]
-            TransactionManager_issue_cond1_LSUDummy[&quot;issue_cond1_LSUDummy&quot;]
-            TransactionManager_issue_cond0_LSUDummy[&quot;issue_cond0_LSUDummy&quot;]
-            TransactionManager_LSUDummy_issue_cond2[&quot;LSUDummy_issue_cond2&quot;]
-            TransactionManager_MethodTryProduct_precommit_cond1[&quot;MethodTryProduct_precommit_cond1&quot;]
-            TransactionManager_Retirement_cond1_Retirement[&quot;Retirement_cond1_Retirement&quot;]
-            TransactionManager_ConnectTrans_accept_cond1[&quot;ConnectTrans_accept_cond1&quot;]
-            TransactionManager_accept_cond0_accept_cond1_ConnectTrans[&quot;accept_cond0_accept_cond1_ConnectTrans&quot;]
+            TransactionManager_LSUDummy_issue_cond0[&quot;LSUDummy_issue_cond0&quot;]
         end
     end
 Core_InitFreeRFFifo --&gt; BasicFifo2_write
-Retirement_Retirement --&gt; BasicFifo2_write
-TransactionManager_Retirement_cond1_Retirement --&gt; BasicFifo2_write
-TransactionManager_Retirement_cond0_Retirement --&gt; BasicFifo2_write
+Retirement_Retirement2 --&gt; BasicFifo2_write
+TransactionManager_Retirement_Retirement_cond1 --&gt; BasicFifo2_write
+TransactionManager_Retirement_Retirement_cond0 --&gt; BasicFifo2_write
 FIFO5_read --&gt; Core_DiscardBranchVerify
 WishboneMaster_WishboneMaster --&gt; Forwarder_write
 WishboneMaster1_WishboneMaster --&gt; Forwarder1_write
 RegisterFile_perf --&gt; HwExpHistogram2__add
 ReorderBuffer_perf --&gt; HwExpHistogram4__add
-SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; WishboneMasterAdapter_request_read
-SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; Serializer_Serializer1
-SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; BasicFifo_write
-SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; WishboneMaster_request
-WishboneMasterAdapter_get_read_response --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-Serializer_Serializer --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-BasicFifo_read --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-WishboneMaster_result --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-Forwarder_read --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1
-SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --&gt; Forwarder2_write
+SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --&gt; WishboneMasterAdapter_request_read
+SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --&gt; Serializer_Serializer
+SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --&gt; BasicFifo_write
+SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --&gt; WishboneMaster_request
+WishboneMasterAdapter_get_read_response --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+Serializer_Serializer1 --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+BasicFifo_read --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+WishboneMaster_result --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+Forwarder_read --&gt; SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
+SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; Forwarder2_write
 ICache_ICache &lt;--&gt; HwCounter4__incr
 ArgumentsToResultsZipper_peek_arg --&gt; ICache_MemRead
 BasicFifo3_peek --&gt; ICache_MemRead
@@ -841,16 +841,16 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 FIFO11_read --&gt; RegAllocation_RegAllocation
 BasicFifo2_read --&gt; RegAllocation_RegAllocation
 RegAllocation_RegAllocation --&gt; FIFO12_write
-FIFO13_read --&gt; RSSelection_RSSelection
 FIFO13_read --&gt; RSSelection_RSSelection2
+FIFO13_read --&gt; RSSelection_RSSelection
 FIFO13_read --&gt; RSSelection_RSSelection1
-RSFuncBlock_select --&gt; RSSelection_RSSelection
-RS_select --&gt; RSSelection_RSSelection
-RSSelection_RSSelection --&gt; FIFO14_write
+RSFuncBlock_select --&gt; RSSelection_RSSelection2
+RS_select --&gt; RSSelection_RSSelection2
 RSSelection_RSSelection2 --&gt; FIFO14_write
+RSSelection_RSSelection --&gt; FIFO14_write
 RSSelection_RSSelection1 --&gt; FIFO14_write
-RSFuncBlock1_select --&gt; RSSelection_RSSelection2
-FifoRS_select --&gt; RSSelection_RSSelection2
+RSFuncBlock1_select --&gt; RSSelection_RSSelection
+FifoRS_select --&gt; RSSelection_RSSelection
 RSSelection_RSSelection1 &lt;--&gt; CSRUnit_select
 FIFO14_read --&gt; RSInsertion_RSInsertion
 RegisterFile_read1 --&gt; RSInsertion_RSInsertion
@@ -873,7 +873,7 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 Collector3_method --&gt; ConnectTrans13_ConnectTrans
 Forwarder8_read --&gt; ConnectTrans13_ConnectTrans
 ConnectTrans13_ConnectTrans --&gt; FetchUnit_resume
-Retirement_Retirement4 --&gt; FetchUnit_resume
+Retirement_Retirement --&gt; FetchUnit_resume
 Collector_method --&gt; ResultAnnouncement_ResultAnnouncement
 Forwarder4_read --&gt; ResultAnnouncement_ResultAnnouncement
 ResultAnnouncement_ResultAnnouncement --&gt; ReorderBuffer_mark_done
@@ -887,7 +887,7 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 ResultAnnouncement_ResultAnnouncement --&gt; FifoRS_update
 ResultAnnouncement_ResultAnnouncement --&gt; CSRUnit_update
 RS_perf --&gt; HwExpHistogram6__add
-RS_RS2 --&gt; WakeupSelect_WakeupSelect
+RS_RS4 --&gt; WakeupSelect_WakeupSelect
 RS_take --&gt; WakeupSelect_WakeupSelect
 RS_take --&gt; WakeupSelect1_WakeupSelect
 RS_take --&gt; WakeupSelect2_WakeupSelect
@@ -911,10 +911,10 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 WakeupSelect_WakeupSelect --&gt; AluFuncUnit_issue
 WakeupSelect_WakeupSelect --&gt; TaggedCounter1__incr
 WakeupSelect_WakeupSelect --&gt; FIFO3_write
-RS_RS --&gt; WakeupSelect1_WakeupSelect
+RS_RS1 --&gt; WakeupSelect1_WakeupSelect
 WakeupSelect1_WakeupSelect --&gt; ShiftFuncUnit_issue
 WakeupSelect1_WakeupSelect --&gt; FIFO4_write
-RS_RS3 --&gt; WakeupSelect2_WakeupSelect
+RS_RS --&gt; WakeupSelect2_WakeupSelect
 WakeupSelect2_WakeupSelect --&gt; JumpBranchFuncUnit_issue
 WakeupSelect2_WakeupSelect --&gt; TaggedCounter2__incr
 WakeupSelect2_WakeupSelect &lt;--&gt; HwCounter7__incr
@@ -923,15 +923,15 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 WakeupSelect3_WakeupSelect --&gt; BasicFifo5_write
 ConnectTrans9_ConnectTrans --&gt; BasicFifo5_write
 ConnectTrans4_ConnectTrans --&gt; BasicFifo5_write
-TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --&gt; BasicFifo5_write
-TransactionManager_accept_cond0_accept_cond1_ConnectTrans --&gt; BasicFifo5_write
 TransactionManager_ConnectTrans_accept_cond1 --&gt; BasicFifo5_write
+TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --&gt; BasicFifo5_write
+TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --&gt; BasicFifo5_write
 WakeupSelect2_WakeupSelect --&gt; FIFO6_write
 WakeupSelect2_WakeupSelect --&gt; FIFO5_write
-RS_RS1 --&gt; WakeupSelect3_WakeupSelect
+RS_RS3 --&gt; WakeupSelect3_WakeupSelect
 WakeupSelect3_WakeupSelect --&gt; ExceptionFuncUnit_issue
 WakeupSelect3_WakeupSelect --&gt; FIFO7_write
-RS_RS4 --&gt; WakeupSelect4_WakeupSelect
+RS_RS2 --&gt; WakeupSelect4_WakeupSelect
 WakeupSelect4_WakeupSelect --&gt; PrivilegedFuncUnit_issue
 ConnectTrans5_ConnectTrans --&gt; Forwarder5_write
 ConnectTrans6_ConnectTrans --&gt; Forwarder5_write
@@ -951,19 +951,19 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 ConnectTrans9_ConnectTrans --&gt; BasicFifo6_write
 FifoRS_perf --&gt; HwExpHistogram8__add
 Forwarder6_read --&gt; LSUDummy_LSUDummy1
-Forwarder6_read --&gt; TransactionManager_issue_cond1_LSUDummy
 Forwarder6_read --&gt; TransactionManager_LSUDummy_issue_cond2
-Forwarder6_read --&gt; TransactionManager_issue_cond0_LSUDummy
+Forwarder6_read --&gt; TransactionManager_LSUDummy_issue_cond0
+Forwarder6_read --&gt; TransactionManager_issue_cond1_LSUDummy
 LSUDummy_LSUDummy1 --&gt; FIFO8_write
 WakeupSelect5_WakeupSelect --&gt; FIFO8_write
-TransactionManager_issue_cond1_LSUDummy --&gt; FIFO8_write
 TransactionManager_LSUDummy_issue_cond2 --&gt; FIFO8_write
-TransactionManager_issue_cond0_LSUDummy --&gt; FIFO8_write
+TransactionManager_LSUDummy_issue_cond0 --&gt; FIFO8_write
+TransactionManager_issue_cond1_LSUDummy --&gt; FIFO8_write
 LSUDummy_LSUDummy1 --&gt; FIFO10_write
 WakeupSelect5_WakeupSelect --&gt; FIFO10_write
-TransactionManager_issue_cond1_LSUDummy --&gt; FIFO10_write
 TransactionManager_LSUDummy_issue_cond2 --&gt; FIFO10_write
-TransactionManager_issue_cond0_LSUDummy --&gt; FIFO10_write
+TransactionManager_LSUDummy_issue_cond0 --&gt; FIFO10_write
+TransactionManager_issue_cond1_LSUDummy --&gt; FIFO10_write
 FifoRS_FifoRS --&gt; WakeupSelect5_WakeupSelect
 FifoRS_take --&gt; WakeupSelect5_WakeupSelect
 WakeupSelect5_WakeupSelect --&gt; TaggedLatencyMeasurer2__stop
@@ -1008,55 +1008,55 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 Collector2_method --&gt; ConnectTrans3_ConnectTrans
 Forwarder7_read --&gt; ConnectTrans3_ConnectTrans
 CSRUnit_get_result --&gt; ConnectTrans4_ConnectTrans
-MethodTryProduct_MethodTryProduct2 --&gt; LSUDummy_precommit
-MethodTryProduct_MethodTryProduct --&gt; CSRUnit_precommit
+MethodTryProduct_MethodTryProduct1 --&gt; LSUDummy_precommit
+MethodTryProduct_MethodTryProduct2 --&gt; CSRUnit_precommit
 ConnectTrans11_ConnectTrans --&gt; Forwarder8_write
 ConnectTrans12_ConnectTrans --&gt; Forwarder8_write
 BasicFifo6_read --&gt; ConnectTrans11_ConnectTrans
 CSRUnit_fetch_resume --&gt; ConnectTrans12_ConnectTrans
+ReorderBuffer_peek --&gt; Retirement_Retirement4
+ReorderBuffer_peek --&gt; Retirement_Retirement3
 ReorderBuffer_peek --&gt; Retirement_Retirement2
-ReorderBuffer_peek --&gt; Retirement_Retirement1
-ReorderBuffer_peek --&gt; Retirement_Retirement
-ReorderBuffer_peek --&gt; TransactionManager_Retirement_cond1_Retirement
-ReorderBuffer_peek --&gt; TransactionManager_Retirement_cond0_Retirement
-Retirement_Retirement2 --&gt; MethodTryProduct_method
-ExceptionCauseRegister_get --&gt; Retirement_Retirement1
-ExceptionCauseRegister_get --&gt; TransactionManager_Retirement_cond1_Retirement
-ExceptionCauseRegister_get --&gt; TransactionManager_Retirement_cond0_Retirement
-Retirement_Retirement &lt;--&gt; ReorderBuffer_retire
-TransactionManager_Retirement_cond1_Retirement &lt;--&gt; ReorderBuffer_retire
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; ReorderBuffer_retire
-Retirement_Retirement &lt;--&gt; FIFOLatencyMeasurer1__stop
-TransactionManager_Retirement_cond1_Retirement &lt;--&gt; FIFOLatencyMeasurer1__stop
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; FIFOLatencyMeasurer1__stop
-FIFO2_read --&gt; Retirement_Retirement
-FIFO2_read --&gt; TransactionManager_Retirement_cond1_Retirement
-FIFO2_read --&gt; TransactionManager_Retirement_cond0_Retirement
-Retirement_Retirement --&gt; HwExpHistogram3__add
-TransactionManager_Retirement_cond1_Retirement --&gt; HwExpHistogram3__add
-TransactionManager_Retirement_cond0_Retirement --&gt; HwExpHistogram3__add
-CoreInstructionCounter_decrement --&gt; Retirement_Retirement
-CoreInstructionCounter_decrement --&gt; TransactionManager_Retirement_cond1_Retirement
-CoreInstructionCounter_decrement --&gt; TransactionManager_Retirement_cond0_Retirement
-RRAT_peek --&gt; Retirement_Retirement
-RRAT_peek --&gt; TransactionManager_Retirement_cond1_Retirement
-Retirement_Retirement --&gt; RegisterFile_free
-TransactionManager_Retirement_cond1_Retirement --&gt; RegisterFile_free
-TransactionManager_Retirement_cond0_Retirement --&gt; RegisterFile_free
-Retirement_Retirement --&gt; TaggedLatencyMeasurer__stop
-TransactionManager_Retirement_cond1_Retirement --&gt; TaggedLatencyMeasurer__stop
-TransactionManager_Retirement_cond0_Retirement --&gt; TaggedLatencyMeasurer__stop
-AsyncMemoryBank_read --&gt; Retirement_Retirement
-AsyncMemoryBank_read --&gt; TransactionManager_Retirement_cond1_Retirement
-AsyncMemoryBank_read --&gt; TransactionManager_Retirement_cond0_Retirement
-Retirement_Retirement --&gt; HwExpHistogram1__add
-TransactionManager_Retirement_cond1_Retirement --&gt; HwExpHistogram1__add
-TransactionManager_Retirement_cond0_Retirement --&gt; HwExpHistogram1__add
-Retirement_Retirement --&gt; FRAT_rename
-TransactionManager_Retirement_cond1_Retirement --&gt; FRAT_rename
+ReorderBuffer_peek --&gt; TransactionManager_Retirement_Retirement_cond1
+ReorderBuffer_peek --&gt; TransactionManager_Retirement_Retirement_cond0
+Retirement_Retirement4 --&gt; MethodTryProduct_method
+ExceptionCauseRegister_get --&gt; Retirement_Retirement3
+ExceptionCauseRegister_get --&gt; TransactionManager_Retirement_Retirement_cond1
+ExceptionCauseRegister_get --&gt; TransactionManager_Retirement_Retirement_cond0
+Retirement_Retirement2 &lt;--&gt; ReorderBuffer_retire
+TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; ReorderBuffer_retire
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; ReorderBuffer_retire
+Retirement_Retirement2 &lt;--&gt; FIFOLatencyMeasurer1__stop
+TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; FIFOLatencyMeasurer1__stop
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; FIFOLatencyMeasurer1__stop
+FIFO2_read --&gt; Retirement_Retirement2
+FIFO2_read --&gt; TransactionManager_Retirement_Retirement_cond1
+FIFO2_read --&gt; TransactionManager_Retirement_Retirement_cond0
+Retirement_Retirement2 --&gt; HwExpHistogram3__add
+TransactionManager_Retirement_Retirement_cond1 --&gt; HwExpHistogram3__add
+TransactionManager_Retirement_Retirement_cond0 --&gt; HwExpHistogram3__add
+CoreInstructionCounter_decrement --&gt; Retirement_Retirement2
+CoreInstructionCounter_decrement --&gt; TransactionManager_Retirement_Retirement_cond1
+CoreInstructionCounter_decrement --&gt; TransactionManager_Retirement_Retirement_cond0
+RRAT_peek --&gt; Retirement_Retirement2
+RRAT_peek --&gt; TransactionManager_Retirement_Retirement_cond1
+Retirement_Retirement2 --&gt; RegisterFile_free
+TransactionManager_Retirement_Retirement_cond1 --&gt; RegisterFile_free
+TransactionManager_Retirement_Retirement_cond0 --&gt; RegisterFile_free
+Retirement_Retirement2 --&gt; TaggedLatencyMeasurer__stop
+TransactionManager_Retirement_Retirement_cond1 --&gt; TaggedLatencyMeasurer__stop
+TransactionManager_Retirement_Retirement_cond0 --&gt; TaggedLatencyMeasurer__stop
+AsyncMemoryBank_read --&gt; Retirement_Retirement2
+AsyncMemoryBank_read --&gt; TransactionManager_Retirement_Retirement_cond1
+AsyncMemoryBank_read --&gt; TransactionManager_Retirement_Retirement_cond0
+Retirement_Retirement2 --&gt; HwExpHistogram1__add
+TransactionManager_Retirement_Retirement_cond1 --&gt; HwExpHistogram1__add
+TransactionManager_Retirement_Retirement_cond0 --&gt; HwExpHistogram1__add
+Retirement_Retirement2 --&gt; FRAT_rename
 TransactionManager_ROBAllocation_Renaming --&gt; FRAT_rename
-CSRRegister1_read --&gt; Retirement_Retirement4
-Retirement_Retirement4 &lt;--&gt; ExceptionCauseRegister_clear
+TransactionManager_Retirement_Retirement_cond1 --&gt; FRAT_rename
+CSRRegister1_read --&gt; Retirement_Retirement
+Retirement_Retirement &lt;--&gt; ExceptionCauseRegister_clear
 GenericCSRRegisters_GenericCSRRegisters &lt;--&gt; DoubleCounterCSR_increment
 CSRRegister3_read --&gt; GenericCSRRegisters_GenericCSRRegisters
 GenericCSRRegisters_GenericCSRRegisters --&gt; CSRRegister3_write
@@ -1068,78 +1068,17 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 CSRRegister6_read --&gt; GenericCSRRegisters_GenericCSRRegisters
 GenericCSRRegisters_GenericCSRRegisters --&gt; CSRRegister6_write
 AdapterTrans1_AdapterTrans_report_interrupt &lt;--&gt; InterruptController_report_interrupt
-TransactionManager_MethodTryProduct_precommit_cond1 &lt;--&gt; MethodTryProduct_MethodTryProduct1
-TransactionManager_MethodTryProduct_precommit_cond2 &lt;--&gt; MethodTryProduct_MethodTryProduct1
-TransactionManager_MethodTryProduct_precommit_cond0 &lt;--&gt; MethodTryProduct_MethodTryProduct1
-TransactionManager_MethodTryProduct_precommit_cond1 --&gt; PrivilegedFuncUnit_precommit
+TransactionManager_MethodTryProduct_precommit_cond2 &lt;--&gt; MethodTryProduct_MethodTryProduct
+TransactionManager_precommit_cond0_MethodTryProduct &lt;--&gt; MethodTryProduct_MethodTryProduct
+TransactionManager_precommit_cond1_MethodTryProduct &lt;--&gt; MethodTryProduct_MethodTryProduct
 TransactionManager_MethodTryProduct_precommit_cond2 --&gt; PrivilegedFuncUnit_precommit
-TransactionManager_MethodTryProduct_precommit_cond0 --&gt; PrivilegedFuncUnit_precommit
-TransactionManager_MethodTryProduct_precommit_cond1 --&gt; TaggedCounter3__incr
+TransactionManager_precommit_cond0_MethodTryProduct --&gt; PrivilegedFuncUnit_precommit
+TransactionManager_precommit_cond1_MethodTryProduct --&gt; PrivilegedFuncUnit_precommit
 TransactionManager_MethodTryProduct_precommit_cond2 --&gt; TaggedCounter3__incr
-TransactionManager_MethodTryProduct_precommit_cond0 --&gt; TaggedCounter3__incr
-TransactionManager_MethodTryProduct_precommit_cond1 &lt;--&gt; PrivilegedFuncUnit_precommit_cond1
-TransactionManager_MethodTryProduct_precommit_cond1 &lt;--&gt; InterruptController_mret
-TransactionManager_issue_cond1_LSUDummy &lt;--&gt; LSURequester_issue_cond1
-TransactionManager_issue_cond1_LSUDummy --&gt; WishboneMasterAdapter1_request_read
-TransactionManager_issue_cond1_LSUDummy --&gt; Serializer1_Serializer
-TransactionManager_issue_cond1_LSUDummy --&gt; BasicFifo1_write
-TransactionManager_issue_cond0_LSUDummy --&gt; BasicFifo1_write
-TransactionManager_issue_cond1_LSUDummy --&gt; WishboneMaster1_request
-TransactionManager_issue_cond0_LSUDummy --&gt; WishboneMaster1_request
-TransactionManager_issue_cond1_LSUDummy &lt;--&gt; LSUDummy_LSUDummy
-TransactionManager_LSUDummy_issue_cond2 &lt;--&gt; LSUDummy_LSUDummy
-TransactionManager_issue_cond0_LSUDummy &lt;--&gt; LSUDummy_LSUDummy
-TransactionManager_issue_cond1_LSUDummy --&gt; LSURequester_issue
-TransactionManager_LSUDummy_issue_cond2 --&gt; LSURequester_issue
-TransactionManager_issue_cond0_LSUDummy --&gt; LSURequester_issue
-TransactionManager_issue_cond1_LSUDummy --&gt; FIFO9_write
-TransactionManager_LSUDummy_issue_cond2 --&gt; FIFO9_write
-TransactionManager_issue_cond0_LSUDummy --&gt; FIFO9_write
+TransactionManager_precommit_cond0_MethodTryProduct --&gt; TaggedCounter3__incr
+TransactionManager_precommit_cond1_MethodTryProduct --&gt; TaggedCounter3__incr
 TransactionManager_MethodTryProduct_precommit_cond2 &lt;--&gt; PrivilegedFuncUnit_precommit_cond2
 TransactionManager_MethodTryProduct_precommit_cond2 &lt;--&gt; ICache_flush
-TransactionManager_LSUDummy_issue_cond2 &lt;--&gt; LSURequester_issue_cond2
-TransactionManager_Retirement_cond1_Retirement &lt;--&gt; Retirement_Retirement_cond1
-TransactionManager_Retirement_cond1_Retirement &lt;--&gt; Retirement_Retirement3
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; Retirement_Retirement3
-TransactionManager_Retirement_cond1_Retirement --&gt; CSRRegister_write
-TransactionManager_Retirement_cond0_Retirement --&gt; CSRRegister_write
-TransactionManager_Retirement_cond1_Retirement --&gt; CSRRegister2_write
-TransactionManager_Retirement_cond0_Retirement --&gt; CSRRegister2_write
-TransactionManager_Retirement_cond1_Retirement &lt;--&gt; InterruptController_entry
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; InterruptController_entry
-TransactionManager_MethodTryProduct_precommit_cond0 &lt;--&gt; PrivilegedFuncUnit_precommit_cond0
-TransactionManager_accept_cond0_ConnectTrans_accept_cond0 &lt;--&gt; LSUDummy_accept_cond0
-TransactionManager_accept_cond0_accept_cond1_ConnectTrans &lt;--&gt; LSUDummy_accept_cond0
-LSURequester_accept --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-LSURequester_accept --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-FIFO9_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-FIFO9_read --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-TransactionManager_accept_cond0_ConnectTrans_accept_cond0 &lt;--&gt; ConnectTrans10_ConnectTrans
-TransactionManager_accept_cond0_accept_cond1_ConnectTrans &lt;--&gt; ConnectTrans10_ConnectTrans
-TransactionManager_ConnectTrans_accept_cond1 &lt;--&gt; ConnectTrans10_ConnectTrans
-TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --&gt; Forwarder7_write
-TransactionManager_accept_cond0_accept_cond1_ConnectTrans --&gt; Forwarder7_write
-TransactionManager_ConnectTrans_accept_cond1 --&gt; Forwarder7_write
-LSUDummy_accept --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-LSUDummy_accept --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-LSUDummy_accept --&gt; TransactionManager_ConnectTrans_accept_cond1
-TransactionManager_accept_cond0_ConnectTrans_accept_cond0 &lt;--&gt; LSURequester_accept_cond0
-WishboneMasterAdapter1_get_write_response --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-Serializer1_Serializer2 --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-BasicFifo1_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-BasicFifo1_read --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-WishboneMaster1_result --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-WishboneMaster1_result --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-Forwarder1_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
-Forwarder1_read --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; Retirement_Retirement_cond0
-TransactionManager_Retirement_cond0_Retirement --&gt; RRAT_commit
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; DoubleCounterCSR2_increment
-CSRRegister7_read --&gt; TransactionManager_Retirement_cond0_Retirement
-TransactionManager_Retirement_cond0_Retirement --&gt; CSRRegister7_write
-CSRRegister8_read --&gt; TransactionManager_Retirement_cond0_Retirement
-TransactionManager_Retirement_cond0_Retirement --&gt; CSRRegister8_write
-TransactionManager_Retirement_cond0_Retirement &lt;--&gt; HwCounter9__incr
 TransactionManager_ROBAllocation_Renaming &lt;--&gt; ROBAllocation_ROBAllocation
 Connect_read --&gt; TransactionManager_ROBAllocation_Renaming
 TransactionManager_ROBAllocation_Renaming --&gt; ReorderBuffer_put
@@ -1149,15 +1088,76 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 TransactionManager_ROBAllocation_Renaming &lt;--&gt; Renaming_Renaming
 FIFO12_read --&gt; TransactionManager_ROBAllocation_Renaming
 TransactionManager_ROBAllocation_Renaming --&gt; Connect_write
-TransactionManager_accept_cond0_accept_cond1_ConnectTrans &lt;--&gt; LSURequester_accept_cond1
-WishboneMasterAdapter1_get_read_response --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-Serializer1_Serializer1 --&gt; TransactionManager_accept_cond0_accept_cond1_ConnectTrans
-TransactionManager_issue_cond0_LSUDummy &lt;--&gt; LSURequester_issue_cond0
-TransactionManager_issue_cond0_LSUDummy --&gt; WishboneMasterAdapter1_request_write
-TransactionManager_issue_cond0_LSUDummy --&gt; Serializer1_Serializer3
+TransactionManager_precommit_cond0_MethodTryProduct &lt;--&gt; PrivilegedFuncUnit_precommit_cond0
+TransactionManager_ConnectTrans_accept_cond1 &lt;--&gt; ConnectTrans10_ConnectTrans
+TransactionManager_accept_cond0_ConnectTrans_accept_cond0 &lt;--&gt; ConnectTrans10_ConnectTrans
+TransactionManager_accept_cond0_ConnectTrans_accept_cond1 &lt;--&gt; ConnectTrans10_ConnectTrans
+TransactionManager_ConnectTrans_accept_cond1 --&gt; Forwarder7_write
+TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --&gt; Forwarder7_write
+TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --&gt; Forwarder7_write
+LSUDummy_accept --&gt; TransactionManager_ConnectTrans_accept_cond1
+LSUDummy_accept --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+LSUDummy_accept --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
 TransactionManager_ConnectTrans_accept_cond1 &lt;--&gt; LSUDummy_accept_cond1
 FIFO8_read --&gt; TransactionManager_ConnectTrans_accept_cond1
 FIFO10_read --&gt; TransactionManager_ConnectTrans_accept_cond1
+TransactionManager_LSUDummy_issue_cond2 &lt;--&gt; LSUDummy_LSUDummy
+TransactionManager_LSUDummy_issue_cond0 &lt;--&gt; LSUDummy_LSUDummy
+TransactionManager_issue_cond1_LSUDummy &lt;--&gt; LSUDummy_LSUDummy
+TransactionManager_LSUDummy_issue_cond2 --&gt; LSURequester_issue
+TransactionManager_LSUDummy_issue_cond0 --&gt; LSURequester_issue
+TransactionManager_issue_cond1_LSUDummy --&gt; LSURequester_issue
+TransactionManager_LSUDummy_issue_cond2 --&gt; FIFO9_write
+TransactionManager_LSUDummy_issue_cond0 --&gt; FIFO9_write
+TransactionManager_issue_cond1_LSUDummy --&gt; FIFO9_write
+TransactionManager_LSUDummy_issue_cond2 &lt;--&gt; LSURequester_issue_cond2
+TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; Retirement_Retirement1
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; Retirement_Retirement1
+TransactionManager_Retirement_Retirement_cond1 --&gt; CSRRegister_write
+TransactionManager_Retirement_Retirement_cond0 --&gt; CSRRegister_write
+TransactionManager_Retirement_Retirement_cond1 --&gt; CSRRegister2_write
+TransactionManager_Retirement_Retirement_cond0 --&gt; CSRRegister2_write
+TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; InterruptController_entry
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; InterruptController_entry
+TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; Retirement_Retirement_cond1
+TransactionManager_accept_cond0_ConnectTrans_accept_cond0 &lt;--&gt; LSUDummy_accept_cond0
+TransactionManager_accept_cond0_ConnectTrans_accept_cond1 &lt;--&gt; LSUDummy_accept_cond0
+LSURequester_accept --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+LSURequester_accept --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+FIFO9_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+FIFO9_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+TransactionManager_accept_cond0_ConnectTrans_accept_cond0 &lt;--&gt; LSURequester_accept_cond0
+WishboneMasterAdapter1_get_write_response --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+Serializer1_Serializer --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+BasicFifo1_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+BasicFifo1_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+WishboneMaster1_result --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+WishboneMaster1_result --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+Forwarder1_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond0
+Forwarder1_read --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+TransactionManager_LSUDummy_issue_cond0 &lt;--&gt; LSURequester_issue_cond0
+TransactionManager_LSUDummy_issue_cond0 --&gt; WishboneMasterAdapter1_request_write
+TransactionManager_LSUDummy_issue_cond0 --&gt; Serializer1_Serializer1
+TransactionManager_LSUDummy_issue_cond0 --&gt; BasicFifo1_write
+TransactionManager_issue_cond1_LSUDummy --&gt; BasicFifo1_write
+TransactionManager_LSUDummy_issue_cond0 --&gt; WishboneMaster1_request
+TransactionManager_issue_cond1_LSUDummy --&gt; WishboneMaster1_request
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; Retirement_Retirement_cond0
+TransactionManager_Retirement_Retirement_cond0 --&gt; RRAT_commit
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; DoubleCounterCSR2_increment
+CSRRegister7_read --&gt; TransactionManager_Retirement_Retirement_cond0
+TransactionManager_Retirement_Retirement_cond0 --&gt; CSRRegister7_write
+CSRRegister8_read --&gt; TransactionManager_Retirement_Retirement_cond0
+TransactionManager_Retirement_Retirement_cond0 --&gt; CSRRegister8_write
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; HwCounter9__incr
+TransactionManager_precommit_cond1_MethodTryProduct &lt;--&gt; PrivilegedFuncUnit_precommit_cond1
+TransactionManager_precommit_cond1_MethodTryProduct &lt;--&gt; InterruptController_mret
+TransactionManager_issue_cond1_LSUDummy &lt;--&gt; LSURequester_issue_cond1
+TransactionManager_issue_cond1_LSUDummy --&gt; WishboneMasterAdapter1_request_read
+TransactionManager_issue_cond1_LSUDummy --&gt; Serializer1_Serializer3
+TransactionManager_accept_cond0_ConnectTrans_accept_cond1 &lt;--&gt; LSURequester_accept_cond1
+WishboneMasterAdapter1_get_read_response --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
+Serializer1_Serializer2 --&gt; TransactionManager_accept_cond0_ConnectTrans_accept_cond1
         </div></div>
 </div>
 </div>
@@ -1174,7 +1174,7 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/development-environment.html b/development-environment.html
index f5b121f6d..5557538fc 100644
--- a/development-environment.html
+++ b/development-environment.html
@@ -209,7 +209,7 @@ <h3>tprof.py<a class="headerlink" href="#tprof-py" title="Permalink to this head
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/genindex.html b/genindex.html
index 9be8c8738..22fdc82d2 100644
--- a/genindex.html
+++ b/genindex.html
@@ -3827,7 +3827,7 @@ <h2 id="Z">Z</h2>
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/home.html b/home.html
index a2d314711..8c942ed0e 100644
--- a/home.html
+++ b/home.html
@@ -129,7 +129,7 @@ <h2>Documentation<a class="headerlink" href="#documentation" title="Permalink to
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/index.html b/index.html
index 57e631eca..4e684fe63 100644
--- a/index.html
+++ b/index.html
@@ -229,7 +229,7 @@ <h1>Coreblocks<a class="headerlink" href="#coreblocks" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html
index b5c3890f7..6e87ce86d 100644
--- a/miscellany/exceptions-summary.html
+++ b/miscellany/exceptions-summary.html
@@ -271,7 +271,7 @@ <h2>Summary<a class="headerlink" href="#summary" title="Permalink to this headin
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/modules-coreblocks.html b/modules-coreblocks.html
index 91f5e3b5a..4d90816fb 100644
--- a/modules-coreblocks.html
+++ b/modules-coreblocks.html
@@ -168,7 +168,7 @@ <h1>coreblocks<a class="headerlink" href="#coreblocks" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/modules-transactron.html b/modules-transactron.html
index 1a9fadd4f..9cabacd19 100644
--- a/modules-transactron.html
+++ b/modules-transactron.html
@@ -161,7 +161,7 @@ <h1>transactron<a class="headerlink" href="#transactron" title="Permalink to thi
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/problem-checklist.html b/problem-checklist.html
index 14ec91eec..3bacedc55 100644
--- a/problem-checklist.html
+++ b/problem-checklist.html
@@ -105,7 +105,7 @@ <h1>Problem checklist<a class="headerlink" href="#problem-checklist" title="Perm
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/py-modindex.html b/py-modindex.html
index 9235e99c4..3a65da6bc 100644
--- a/py-modindex.html
+++ b/py-modindex.html
@@ -668,7 +668,7 @@ <h1>Python Module Index</h1>
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/scheduler/overview.html b/scheduler/overview.html
index 2460f0485..ee2068215 100644
--- a/scheduler/overview.html
+++ b/scheduler/overview.html
@@ -146,7 +146,7 @@ <h2>More detailed description of each block<a class="headerlink" href="#more-det
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/search.html b/search.html
index 84724adb6..cd69f5506 100644
--- a/search.html
+++ b/search.html
@@ -101,7 +101,7 @@
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/shared-structs/implementation/rs-impl.html b/shared-structs/implementation/rs-impl.html
index 2ccf4a61b..347f76aef 100644
--- a/shared-structs/implementation/rs-impl.html
+++ b/shared-structs/implementation/rs-impl.html
@@ -252,7 +252,7 @@ <h3>Read and clean row<a class="headerlink" href="#read-and-clean-row" title="Pe
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/shared-structs/rs.html b/shared-structs/rs.html
index efa09a823..fb99fb20c 100644
--- a/shared-structs/rs.html
+++ b/shared-structs/rs.html
@@ -222,7 +222,7 @@ <h2>External interface signals<a class="headerlink" href="#external-interface-si
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/synthesis/synthesis.html b/synthesis/synthesis.html
index 9fefa3813..c6c79f1d7 100644
--- a/synthesis/synthesis.html
+++ b/synthesis/synthesis.html
@@ -266,7 +266,7 @@ <h3>Regression tests manual execution<a class="headerlink" href="#regression-tes
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/transactions.html b/transactions.html
index efe7096f5..f3253feab 100644
--- a/transactions.html
+++ b/transactions.html
@@ -409,7 +409,7 @@ <h3>Transaction and method nesting<a class="headerlink" href="#transaction-and-m
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/transactron.core.html b/transactron.core.html
index 17f7db806..956e95735 100644
--- a/transactron.core.html
+++ b/transactron.core.html
@@ -860,7 +860,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/transactron.html b/transactron.html
index a308ce570..36061942a 100644
--- a/transactron.html
+++ b/transactron.html
@@ -751,7 +751,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/transactron.lib.html b/transactron.lib.html
index 3567abcf1..1b9b0005e 100644
--- a/transactron.lib.html
+++ b/transactron.lib.html
@@ -2166,7 +2166,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/transactron.testing.html b/transactron.testing.html
index 41219909d..707a549f7 100644
--- a/transactron.testing.html
+++ b/transactron.testing.html
@@ -425,7 +425,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/transactron.utils.amaranth_ext.html b/transactron.utils.amaranth_ext.html
index 4cc224292..98b8e2ebd 100644
--- a/transactron.utils.amaranth_ext.html
+++ b/transactron.utils.amaranth_ext.html
@@ -293,7 +293,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>
 
diff --git a/transactron.utils.html b/transactron.utils.html
index 8d2a34a23..216273eda 100644
--- a/transactron.utils.html
+++ b/transactron.utils.html
@@ -792,7 +792,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 18:05 2024-04-14.
+      <span class="lastupdated">Last updated on 12:31 2024-04-15.
       </span></p>
   </div>