From cd3043bf31339e1459ce7ab42b1c0d8d4b5c13e0 Mon Sep 17 00:00:00 2001 From: tilk Date: Tue, 5 Mar 2024 11:12:31 +0000 Subject: [PATCH] A step towards amaranth `v0.5.0` (#577) --- .doctrees/api.doctree | Bin 21036 -> 21036 bytes .doctrees/auto_graph.doctree | Bin 44469 -> 44467 bytes .doctrees/coreblocks.cache.doctree | Bin 56706 -> 56728 bytes .doctrees/coreblocks.doctree | Bin 11232 -> 11236 bytes .doctrees/coreblocks.frontend.doctree | Bin 121524 -> 121611 bytes .doctrees/coreblocks.fu.doctree | Bin 280284 -> 280343 bytes ...eblocks.fu.unsigned_multiplication.doctree | Bin 47433 -> 47441 bytes .doctrees/coreblocks.lsu.doctree | Bin 47580 -> 47588 bytes .doctrees/coreblocks.params.doctree | Bin 788908 -> 789257 bytes .doctrees/coreblocks.peripherals.doctree | Bin 170794 -> 170832 bytes .doctrees/coreblocks.scheduler.doctree | Bin 42169 -> 42177 bytes .doctrees/coreblocks.stages.doctree | Bin 77941 -> 77957 bytes .doctrees/coreblocks.structs_common.doctree | Bin 155695 -> 155756 bytes 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index 29177e46c..497fc261f 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -7,12 +7,12 @@ Core_DiscardBranchVerify["DiscardBranchVerify"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_request["request"] - WishboneMaster_result["result"] WishboneMaster_WishboneMaster["WishboneMaster"] + WishboneMaster_result["result"] + WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] - Forwarder_read["read"] Forwarder_write["write"] + Forwarder_read["read"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] @@ -20,13 +20,13 @@ WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] subgraph Forwarder1["result Forwarder"] - Forwarder1_write["write"] Forwarder1_read["read"] + Forwarder1_write["write"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] @@ -37,10 +37,10 @@ end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] - WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_read["request_read"] WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_write["request_write"] + WishboneMasterAdapter1_get_write_response["get_write_response"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] @@ -53,8 +53,8 @@ end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph FIFO["fifo_fetch FIFO"] FIFO_write["write"] @@ -67,12 +67,12 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["address_fwd Forwarder"] Forwarder2_read["read"] @@ -80,11 +80,11 @@ end end subgraph ICache["icache ICache"] + ICache_issue_req["issue_req"] ICache_ICache["ICache"] - ICache_accept_res["accept_res"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] - ICache_issue_req["issue_req"] + ICache_accept_res["accept_res"] ICache_ICache3["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] @@ -108,8 +108,8 @@ HwExpHistogram__add["_add"] end subgraph FIFO1["fifo FIFO"] - FIFO1_write["write"] FIFO1_read["read"] + FIFO1_write["write"] end end subgraph FIFO2["req_fifo FIFO"] @@ -117,8 +117,8 @@ FIFO2_write["write"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end subgraph FRAT["FRAT FRAT"] @@ -129,17 +129,17 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_write["write"] - RegisterFile_read2["read2"] RegisterFile_read1["read1"] + RegisterFile_read2["read2"] RegisterFile_free["free"] + RegisterFile_write["write"] end subgraph ReorderBuffer["ROB ReorderBuffer"] ReorderBuffer_retire["retire"] ReorderBuffer_peek["peek"] - ReorderBuffer_get_indices["get_indices"] ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_get_indices["get_indices"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] LatencyMeasurer1__stop["_stop"] LatencyMeasurer1__start["_start"] @@ -147,25 +147,25 @@ HwExpHistogram1__add["_add"] end subgraph FIFO3["fifo FIFO"] - FIFO3_read["read"] FIFO3_write["write"] + FIFO3_read["read"] end end end subgraph Fetch["fetch Fetch"] - Fetch_stall_exception["stall_exception"] + Fetch_resume["resume"] Fetch_Fetch["Fetch"] + Fetch_stall_exception["stall_exception"] Fetch_Fetch1["Fetch"] - Fetch_resume["resume"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] - BasicFifo3_write["write"] BasicFifo3_read["read"] + BasicFifo3_write["write"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] - ExceptionCauseRegister_clear["clear"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_clear["clear"] + ExceptionCauseRegister_report["report"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] BasicFifo4_read["read"] BasicFifo4_write["write"] @@ -178,8 +178,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_write["write"] Forwarder4_read["read"] + Forwarder4_write["write"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -197,20 +197,20 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_insert["insert"] + RSFuncBlock_select["select"] RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] - RSFuncBlock_select["select"] + RSFuncBlock_insert["insert"] subgraph RS["rs RS"] - RS_update["update"] - RS_insert["insert"] RS_RS["RS"] + RS_take["take"] RS_RS1["RS"] RS_RS2["RS"] - RS_select["select"] + RS_update["update"] RS_RS3["RS"] - RS_take["take"] + RS_insert["insert"] RS_RS4["RS"] + RS_select["select"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] AluFuncUnit_issue["issue"] @@ -224,22 +224,22 @@ WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_issue["issue"] ShiftFuncUnit_accept["accept"] + ShiftFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO6["fifo_branch_resolved FIFO"] - FIFO6_write["write"] FIFO6_read["read"] + FIFO6_write["write"] end subgraph HwCounter5["perf_jumps HwCounter"] HwCounter5__incr["_incr"] @@ -251,16 +251,16 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_write["write"] FIFO7_read["read"] + FIFO7_write["write"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] + ExceptionFuncUnit_accept["accept"] subgraph FIFO8["fifo FIFO"] FIFO8_write["write"] FIFO8_read["read"] @@ -307,42 +307,42 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_LSUDummy["LSUDummy"] - LSUDummy_precommit["precommit"] - LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_get_result["get_result"] - LSUDummy_select["select"] - LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_insert["insert"] + LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_select["select"] + LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_update["update"] + LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_precommit["precommit"] subgraph Forwarder6["forwarder Forwarder"] - Forwarder6_write["write"] Forwarder6_read["read"] + Forwarder6_write["write"] end subgraph LSURequester["requester LSURequester"] - LSURequester_accept["accept"] + LSURequester_issue_cond1["issue_cond1"] LSURequester_issue["issue"] - LSURequester_issue_cond2["issue_cond2"] LSURequester_accept_cond0["accept_cond0"] LSURequester_issue_cond0["issue_cond0"] - LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond2["issue_cond2"] LSURequester_accept_cond1["accept_cond1"] + LSURequester_accept["accept"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_select["select"] CSRUnit_update["update"] - CSRUnit_CSRUnit["CSRUnit"] CSRUnit_precommit["precommit"] CSRUnit_get_result["get_result"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_insert["insert"] CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_select["select"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] - MethodTryProduct_method["method"] MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] + MethodTryProduct_method["method"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] @@ -364,9 +364,9 @@ ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"] end subgraph InterruptController["interrupt_controller InterruptController"] - InterruptController_report_interrupt["report_interrupt"] - InterruptController_mret["mret"] InterruptController_entry["entry"] + InterruptController_mret["mret"] + InterruptController_report_interrupt["report_interrupt"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] @@ -377,40 +377,40 @@ CSRRegister__fu_read["_fu_read"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_write["_fu_write"] CSRRegister1_read["read"] CSRRegister1__fu_read["_fu_read"] + CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2__fu_write["_fu_write"] - CSRRegister2_write["write"] CSRRegister2_read["read"] CSRRegister2__fu_read["_fu_read"] + CSRRegister2_write["write"] + CSRRegister2__fu_write["_fu_write"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] CSRRegister3_read["read"] - CSRRegister3__fu_read["_fu_read"] CSRRegister3_write["write"] + CSRRegister3__fu_read["_fu_read"] end subgraph CSRRegister4["register_high CSRRegister"] - CSRRegister4_write["write"] CSRRegister4__fu_read["_fu_read"] CSRRegister4_read["read"] + CSRRegister4_write["write"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_write["write"] CSRRegister5__fu_read["_fu_read"] CSRRegister5_read["read"] + CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_write["write"] CSRRegister6_read["read"] + CSRRegister6_write["write"] CSRRegister6__fu_read["_fu_read"] end end @@ -441,15 +441,15 @@ Renaming_Renaming["Renaming"] end subgraph FIFO12["reg_alloc_out_buf FIFO"] - FIFO12_write["write"] FIFO12_read["read"] + FIFO12_write["write"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO13["rs_select_out_buf FIFO"] - FIFO13_read["read"] FIFO13_write["write"] + FIFO13_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -469,25 +469,25 @@ ConnectTrans11_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] + Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] Retirement_Retirement1["Retirement"] Retirement_Retirement2["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] - Retirement_core_state["core_state"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement3["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement4["Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] - CSRRegister7__fu_read["_fu_read"] - CSRRegister7_write["write"] CSRRegister7_read["read"] + CSRRegister7_write["write"] + CSRRegister7__fu_read["_fu_read"] end subgraph CSRRegister8["register_high CSRRegister"] + CSRRegister8_write["write"] CSRRegister8__fu_read["_fu_read"] CSRRegister8_read["read"] - CSRRegister8_write["write"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -512,61 +512,61 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] - TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] - TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] - TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] - TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] + TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] end end Core_InitFreeRFFifo --> BasicFifo2_write - Retirement_Retirement3 --> BasicFifo2_write - TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write + Retirement_Retirement --> BasicFifo2_write + TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write Forwarder2_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request ICache_ICache2 <--> HwCounter4__incr - ICache_ICache1 <--> HwCounter3__incr - ICache_ICache1 <--> HwCounter2__incr - ICache_ICache1 <--> HwCounter1__incr - ICache_ICache1 --> Forwarder3_write - ICache_ICache3 --> SimpleCommonBusCacheRefiller_start_refill + ICache_ICache <--> HwCounter3__incr + ICache_ICache <--> HwCounter2__incr + ICache_ICache <--> HwCounter1__incr + ICache_ICache --> Forwarder3_write + ICache_ICache1 --> SimpleCommonBusCacheRefiller_start_refill + ICache_ICache1 --> Forwarder2_write ICache_ICache3 --> Forwarder2_write - ICache_ICache --> Forwarder2_write - SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache - WishboneMasterAdapter_get_read_response --> ICache_ICache - Serializer_Serializer --> ICache_ICache - BasicFifo_read --> ICache_ICache - WishboneMaster_result --> ICache_ICache - Forwarder_read --> ICache_ICache - Fetch_Fetch1 --> ICache_issue_req - Fetch_Fetch1 <--> HwCounter__incr - Fetch_Fetch1 <--> LatencyMeasurer__start - Fetch_Fetch1 --> FIFO1_write - Fetch_Fetch1 --> FIFO2_write - Fetch_Fetch1 --> BasicFifo3_write - BasicFifo3_read --> Fetch_Fetch - ICache_accept_res --> Fetch_Fetch - FIFO2_read --> Fetch_Fetch - Fetch_Fetch <--> LatencyMeasurer__stop - FIFO1_read --> Fetch_Fetch - Fetch_Fetch --> HwExpHistogram__add - Forwarder3_read --> Fetch_Fetch - Fetch_Fetch --> MethodProduct_method + SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3 + WishboneMasterAdapter_get_read_response --> ICache_ICache3 + Serializer_Serializer1 --> ICache_ICache3 + BasicFifo_read --> ICache_ICache3 + WishboneMaster_result --> ICache_ICache3 + Forwarder_read --> ICache_ICache3 + Fetch_Fetch --> ICache_issue_req + Fetch_Fetch <--> HwCounter__incr + Fetch_Fetch <--> LatencyMeasurer__start + Fetch_Fetch --> FIFO1_write + Fetch_Fetch --> FIFO2_write + Fetch_Fetch --> BasicFifo3_write + BasicFifo3_read --> Fetch_Fetch1 + ICache_accept_res --> Fetch_Fetch1 + FIFO2_read --> Fetch_Fetch1 + Fetch_Fetch1 <--> LatencyMeasurer__stop + FIFO1_read --> Fetch_Fetch1 + Fetch_Fetch1 --> HwExpHistogram__add + Forwarder3_read --> Fetch_Fetch1 + Fetch_Fetch1 --> MethodProduct_method AdapterTrans_AdapterTrans_method --> MethodProduct_method - Fetch_Fetch --> FIFO_write + Fetch_Fetch1 --> FIFO_write AdapterTrans_AdapterTrans_method --> FIFO_write - Fetch_Fetch --> MethodMap_method + Fetch_Fetch1 --> MethodMap_method AdapterTrans_AdapterTrans_method --> MethodMap_method - Fetch_Fetch <--> CoreInstructionCounter_increment + Fetch_Fetch1 <--> CoreInstructionCounter_increment AdapterTrans_AdapterTrans_method <--> CoreInstructionCounter_increment FIFO_read --> DecodeStage_DecodeStage DecodeStage_DecodeStage <--> HwCounter8__incr @@ -576,7 +576,7 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename - Retirement_Retirement3 --> FRAT_rename + Retirement_Retirement --> FRAT_rename TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation @@ -584,17 +584,17 @@ ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write - FIFO12_read --> RSSelection_RSSelection2 - RSSelection_RSSelection2 --> Forwarder8_write - Forwarder8_read --> RSSelection_RSSelection1 + FIFO12_read --> RSSelection_RSSelection1 + RSSelection_RSSelection1 --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection + Forwarder8_read --> RSSelection_RSSelection2 Forwarder8_read --> RSSelection_RSSelection3 - RSFuncBlock_select --> RSSelection_RSSelection1 - RS_select --> RSSelection_RSSelection1 - RSSelection_RSSelection1 --> FIFO13_write + RSFuncBlock_select --> RSSelection_RSSelection + RS_select --> RSSelection_RSSelection RSSelection_RSSelection --> FIFO13_write + RSSelection_RSSelection2 --> FIFO13_write RSSelection_RSSelection3 --> FIFO13_write - RSSelection_RSSelection <--> LSUDummy_select + RSSelection_RSSelection2 <--> LSUDummy_select RSSelection_RSSelection3 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion @@ -611,7 +611,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume - Retirement_Retirement --> Fetch_resume + Retirement_Retirement4 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -633,7 +633,7 @@ RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write - RS_RS4 --> WakeupSelect2_WakeupSelect + RS_RS1 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -648,7 +648,7 @@ RS_RS2 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write - RS_RS1 --> WakeupSelect4_WakeupSelect + RS_RS4 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -666,12 +666,12 @@ PrivilegedFuncUnit_accept --> ConnectTrans8_ConnectTrans CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write - LSUDummy_LSUDummy --> Forwarder6_write - TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write - TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write - TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write + LSUDummy_LSUDummy1 --> Forwarder6_write TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write - TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write + TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write + TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write + TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write + TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -695,43 +695,43 @@ CSRUnit_get_result --> ConnectTrans3_ConnectTrans MethodTryProduct_MethodTryProduct1 --> PrivilegedFuncUnit_precommit MethodTryProduct_MethodTryProduct1 <--> InterruptController_mret - MethodTryProduct_MethodTryProduct2 --> LSUDummy_precommit - MethodTryProduct_MethodTryProduct --> CSRUnit_precommit + MethodTryProduct_MethodTryProduct --> LSUDummy_precommit + MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans ReorderBuffer_peek --> Retirement_Retirement1 - ReorderBuffer_peek --> Retirement_Retirement4 - ReorderBuffer_peek --> Retirement_Retirement3 - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 + ReorderBuffer_peek --> Retirement_Retirement2 + ReorderBuffer_peek --> Retirement_Retirement + ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement Retirement_Retirement1 --> MethodTryProduct_method - ExceptionCauseRegister_get --> Retirement_Retirement4 - ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 + ExceptionCauseRegister_get --> Retirement_Retirement2 + ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement3 <--> ReorderBuffer_retire - TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire + Retirement_Retirement <--> ReorderBuffer_retire + TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire - Retirement_Retirement3 <--> LatencyMeasurer1__stop - TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop + Retirement_Retirement <--> LatencyMeasurer1__stop + TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop - FIFO3_read --> Retirement_Retirement3 - FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 + FIFO3_read --> Retirement_Retirement + FIFO3_read --> TransactionManager_Retirement_cond0_Retirement FIFO3_read --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement3 --> HwExpHistogram1__add - TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add + Retirement_Retirement --> HwExpHistogram1__add + TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add - CoreInstructionCounter_decrement --> Retirement_Retirement3 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 + CoreInstructionCounter_decrement --> Retirement_Retirement + CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement - RRAT_peek --> Retirement_Retirement3 + RRAT_peek --> Retirement_Retirement RRAT_peek --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement3 --> RegisterFile_free - TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free + Retirement_Retirement --> RegisterFile_free + TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free - CSRRegister1_read --> Retirement_Retirement - Retirement_Retirement <--> ExceptionCauseRegister_clear + CSRRegister1_read --> Retirement_Retirement4 + Retirement_Retirement4 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -743,53 +743,53 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans2_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt - TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy1 - TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy1 - LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_cond0_Retirement --> RRAT_commit + TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment + CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write + CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write + TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr + TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement3 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3 + TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write + TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write + TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write + TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write + TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry + TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry + TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy2 + TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2 LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 - TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 - Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond0 - BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 + LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 + Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond1 BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 - WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 + BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 - Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 + WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 - TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy2 - TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy2 - TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy2 + Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 + TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy + TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy + TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy + TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue - TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue - TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 - TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer2 + TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 + TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read + TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer2 + TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write - TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write + TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request - TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request - TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 - TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2 - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement2 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write - TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry - TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry - TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit - TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment - CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write - CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write - TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr - TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 - Serializer1_Serializer1 --> TransactionManager_LSUDummy_accept_cond1 - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 - TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 - TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read - TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3 + TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 + TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write + TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 + TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 + TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 + Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond0 diff --git a/api.html b/api.html index b4f5cab57..1632f131e 100644 --- a/api.html +++ b/api.html @@ -281,7 +281,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/assumptions.html b/assumptions.html index 820b0c878..e90fe2e23 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/auto_graph.html b/auto_graph.html index d6f5d5e69..94f37c369 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -86,12 +86,12 @@ Core_DiscardBranchVerify["DiscardBranchVerify"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_request["request"] - WishboneMaster_result["result"] WishboneMaster_WishboneMaster["WishboneMaster"] + WishboneMaster_result["result"] + WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] - Forwarder_read["read"] Forwarder_write["write"] + Forwarder_read["read"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] @@ -99,13 +99,13 @@ WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] subgraph Forwarder1["result Forwarder"] - Forwarder1_write["write"] Forwarder1_read["read"] + Forwarder1_write["write"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] @@ -116,10 +116,10 @@ end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] - WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_read["request_read"] WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_write["request_write"] + WishboneMasterAdapter1_get_write_response["get_write_response"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] @@ -132,8 +132,8 @@ end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph FIFO["fifo_fetch FIFO"] FIFO_write["write"] @@ -146,12 +146,12 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["address_fwd Forwarder"] Forwarder2_read["read"] @@ -159,11 +159,11 @@ end end subgraph ICache["icache ICache"] + ICache_issue_req["issue_req"] ICache_ICache["ICache"] - ICache_accept_res["accept_res"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] - ICache_issue_req["issue_req"] + ICache_accept_res["accept_res"] ICache_ICache3["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] @@ -187,8 +187,8 @@ HwExpHistogram__add["_add"] end subgraph FIFO1["fifo FIFO"] - FIFO1_write["write"] FIFO1_read["read"] + FIFO1_write["write"] end end subgraph FIFO2["req_fifo FIFO"] @@ -196,8 +196,8 @@ FIFO2_write["write"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end subgraph FRAT["FRAT FRAT"] @@ -208,17 +208,17 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_write["write"] - RegisterFile_read2["read2"] RegisterFile_read1["read1"] + RegisterFile_read2["read2"] RegisterFile_free["free"] + RegisterFile_write["write"] end subgraph ReorderBuffer["ROB ReorderBuffer"] ReorderBuffer_retire["retire"] ReorderBuffer_peek["peek"] - ReorderBuffer_get_indices["get_indices"] ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_get_indices["get_indices"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] LatencyMeasurer1__stop["_stop"] LatencyMeasurer1__start["_start"] @@ -226,25 +226,25 @@ HwExpHistogram1__add["_add"] end subgraph FIFO3["fifo FIFO"] - FIFO3_read["read"] FIFO3_write["write"] + FIFO3_read["read"] end end end subgraph Fetch["fetch Fetch"] - Fetch_stall_exception["stall_exception"] + Fetch_resume["resume"] Fetch_Fetch["Fetch"] + Fetch_stall_exception["stall_exception"] Fetch_Fetch1["Fetch"] - Fetch_resume["resume"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] - BasicFifo3_write["write"] BasicFifo3_read["read"] + BasicFifo3_write["write"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] - ExceptionCauseRegister_clear["clear"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_clear["clear"] + ExceptionCauseRegister_report["report"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] BasicFifo4_read["read"] BasicFifo4_write["write"] @@ -257,8 +257,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_write["write"] Forwarder4_read["read"] + Forwarder4_write["write"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -276,20 +276,20 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_insert["insert"] + RSFuncBlock_select["select"] RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] - RSFuncBlock_select["select"] + RSFuncBlock_insert["insert"] subgraph RS["rs RS"] - RS_update["update"] - RS_insert["insert"] RS_RS["RS"] + RS_take["take"] RS_RS1["RS"] RS_RS2["RS"] - RS_select["select"] + RS_update["update"] RS_RS3["RS"] - RS_take["take"] + RS_insert["insert"] RS_RS4["RS"] + RS_select["select"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] AluFuncUnit_issue["issue"] @@ -303,22 +303,22 @@ WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_issue["issue"] ShiftFuncUnit_accept["accept"] + ShiftFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO6["fifo_branch_resolved FIFO"] - FIFO6_write["write"] FIFO6_read["read"] + FIFO6_write["write"] end subgraph HwCounter5["perf_jumps HwCounter"] HwCounter5__incr["_incr"] @@ -330,16 +330,16 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_write["write"] FIFO7_read["read"] + FIFO7_write["write"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] + ExceptionFuncUnit_accept["accept"] subgraph FIFO8["fifo FIFO"] FIFO8_write["write"] FIFO8_read["read"] @@ -386,42 +386,42 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_LSUDummy["LSUDummy"] - LSUDummy_precommit["precommit"] - LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_get_result["get_result"] - LSUDummy_select["select"] - LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_insert["insert"] + LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_select["select"] + LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_update["update"] + LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_precommit["precommit"] subgraph Forwarder6["forwarder Forwarder"] - Forwarder6_write["write"] Forwarder6_read["read"] + Forwarder6_write["write"] end subgraph LSURequester["requester LSURequester"] - LSURequester_accept["accept"] + LSURequester_issue_cond1["issue_cond1"] LSURequester_issue["issue"] - LSURequester_issue_cond2["issue_cond2"] LSURequester_accept_cond0["accept_cond0"] LSURequester_issue_cond0["issue_cond0"] - LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond2["issue_cond2"] LSURequester_accept_cond1["accept_cond1"] + LSURequester_accept["accept"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_select["select"] CSRUnit_update["update"] - CSRUnit_CSRUnit["CSRUnit"] CSRUnit_precommit["precommit"] CSRUnit_get_result["get_result"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_insert["insert"] CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_select["select"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] - MethodTryProduct_method["method"] MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] + MethodTryProduct_method["method"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] @@ -443,9 +443,9 @@ ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"] end subgraph InterruptController["interrupt_controller InterruptController"] - InterruptController_report_interrupt["report_interrupt"] - InterruptController_mret["mret"] InterruptController_entry["entry"] + InterruptController_mret["mret"] + InterruptController_report_interrupt["report_interrupt"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] @@ -456,40 +456,40 @@ CSRRegister__fu_read["_fu_read"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_write["_fu_write"] CSRRegister1_read["read"] CSRRegister1__fu_read["_fu_read"] + CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2__fu_write["_fu_write"] - CSRRegister2_write["write"] CSRRegister2_read["read"] CSRRegister2__fu_read["_fu_read"] + CSRRegister2_write["write"] + CSRRegister2__fu_write["_fu_write"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] CSRRegister3_read["read"] - CSRRegister3__fu_read["_fu_read"] CSRRegister3_write["write"] + CSRRegister3__fu_read["_fu_read"] end subgraph CSRRegister4["register_high CSRRegister"] - CSRRegister4_write["write"] CSRRegister4__fu_read["_fu_read"] CSRRegister4_read["read"] + CSRRegister4_write["write"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_write["write"] CSRRegister5__fu_read["_fu_read"] CSRRegister5_read["read"] + CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_write["write"] CSRRegister6_read["read"] + CSRRegister6_write["write"] CSRRegister6__fu_read["_fu_read"] end end @@ -520,15 +520,15 @@ Renaming_Renaming["Renaming"] end subgraph FIFO12["reg_alloc_out_buf FIFO"] - FIFO12_write["write"] FIFO12_read["read"] + FIFO12_write["write"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO13["rs_select_out_buf FIFO"] - FIFO13_read["read"] FIFO13_write["write"] + FIFO13_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -548,25 +548,25 @@ ConnectTrans11_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] + Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] Retirement_Retirement1["Retirement"] Retirement_Retirement2["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] - Retirement_core_state["core_state"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement3["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement4["Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] - CSRRegister7__fu_read["_fu_read"] - CSRRegister7_write["write"] CSRRegister7_read["read"] + CSRRegister7_write["write"] + CSRRegister7__fu_read["_fu_read"] end subgraph CSRRegister8["register_high CSRRegister"] + CSRRegister8_write["write"] CSRRegister8__fu_read["_fu_read"] CSRRegister8_read["read"] - CSRRegister8_write["write"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -591,61 +591,61 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] - TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] - TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] - TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] - TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] + TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] end end Core_InitFreeRFFifo --> BasicFifo2_write -Retirement_Retirement3 --> BasicFifo2_write -TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write +Retirement_Retirement --> BasicFifo2_write +TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write Forwarder2_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request ICache_ICache2 <--> HwCounter4__incr -ICache_ICache1 <--> HwCounter3__incr -ICache_ICache1 <--> HwCounter2__incr -ICache_ICache1 <--> HwCounter1__incr -ICache_ICache1 --> Forwarder3_write -ICache_ICache3 --> SimpleCommonBusCacheRefiller_start_refill +ICache_ICache <--> HwCounter3__incr +ICache_ICache <--> HwCounter2__incr +ICache_ICache <--> HwCounter1__incr +ICache_ICache --> Forwarder3_write +ICache_ICache1 --> SimpleCommonBusCacheRefiller_start_refill +ICache_ICache1 --> Forwarder2_write ICache_ICache3 --> Forwarder2_write -ICache_ICache --> Forwarder2_write -SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache -WishboneMasterAdapter_get_read_response --> ICache_ICache -Serializer_Serializer --> ICache_ICache -BasicFifo_read --> ICache_ICache -WishboneMaster_result --> ICache_ICache -Forwarder_read --> ICache_ICache -Fetch_Fetch1 --> ICache_issue_req -Fetch_Fetch1 <--> HwCounter__incr -Fetch_Fetch1 <--> LatencyMeasurer__start -Fetch_Fetch1 --> FIFO1_write -Fetch_Fetch1 --> FIFO2_write -Fetch_Fetch1 --> BasicFifo3_write -BasicFifo3_read --> Fetch_Fetch -ICache_accept_res --> Fetch_Fetch -FIFO2_read --> Fetch_Fetch -Fetch_Fetch <--> LatencyMeasurer__stop -FIFO1_read --> Fetch_Fetch -Fetch_Fetch --> HwExpHistogram__add -Forwarder3_read --> Fetch_Fetch -Fetch_Fetch --> MethodProduct_method +SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3 +WishboneMasterAdapter_get_read_response --> ICache_ICache3 +Serializer_Serializer1 --> ICache_ICache3 +BasicFifo_read --> ICache_ICache3 +WishboneMaster_result --> ICache_ICache3 +Forwarder_read --> ICache_ICache3 +Fetch_Fetch --> ICache_issue_req +Fetch_Fetch <--> HwCounter__incr +Fetch_Fetch <--> LatencyMeasurer__start +Fetch_Fetch --> FIFO1_write +Fetch_Fetch --> FIFO2_write +Fetch_Fetch --> BasicFifo3_write +BasicFifo3_read --> Fetch_Fetch1 +ICache_accept_res --> Fetch_Fetch1 +FIFO2_read --> Fetch_Fetch1 +Fetch_Fetch1 <--> LatencyMeasurer__stop +FIFO1_read --> Fetch_Fetch1 +Fetch_Fetch1 --> HwExpHistogram__add +Forwarder3_read --> Fetch_Fetch1 +Fetch_Fetch1 --> MethodProduct_method AdapterTrans_AdapterTrans_method --> MethodProduct_method -Fetch_Fetch --> FIFO_write +Fetch_Fetch1 --> FIFO_write AdapterTrans_AdapterTrans_method --> FIFO_write -Fetch_Fetch --> MethodMap_method +Fetch_Fetch1 --> MethodMap_method AdapterTrans_AdapterTrans_method --> MethodMap_method -Fetch_Fetch <--> CoreInstructionCounter_increment +Fetch_Fetch1 <--> CoreInstructionCounter_increment AdapterTrans_AdapterTrans_method <--> CoreInstructionCounter_increment FIFO_read --> DecodeStage_DecodeStage DecodeStage_DecodeStage <--> HwCounter8__incr @@ -655,7 +655,7 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename -Retirement_Retirement3 --> FRAT_rename +Retirement_Retirement --> FRAT_rename TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation @@ -663,17 +663,17 @@ ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write -FIFO12_read --> RSSelection_RSSelection2 -RSSelection_RSSelection2 --> Forwarder8_write -Forwarder8_read --> RSSelection_RSSelection1 +FIFO12_read --> RSSelection_RSSelection1 +RSSelection_RSSelection1 --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection +Forwarder8_read --> RSSelection_RSSelection2 Forwarder8_read --> RSSelection_RSSelection3 -RSFuncBlock_select --> RSSelection_RSSelection1 -RS_select --> RSSelection_RSSelection1 -RSSelection_RSSelection1 --> FIFO13_write +RSFuncBlock_select --> RSSelection_RSSelection +RS_select --> RSSelection_RSSelection RSSelection_RSSelection --> FIFO13_write +RSSelection_RSSelection2 --> FIFO13_write RSSelection_RSSelection3 --> FIFO13_write -RSSelection_RSSelection <--> LSUDummy_select +RSSelection_RSSelection2 <--> LSUDummy_select RSSelection_RSSelection3 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion @@ -690,7 +690,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume -Retirement_Retirement --> Fetch_resume +Retirement_Retirement4 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -712,7 +712,7 @@ RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write -RS_RS4 --> WakeupSelect2_WakeupSelect +RS_RS1 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -727,7 +727,7 @@ RS_RS2 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write -RS_RS1 --> WakeupSelect4_WakeupSelect +RS_RS4 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -745,12 +745,12 @@ PrivilegedFuncUnit_accept --> ConnectTrans8_ConnectTrans CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write -LSUDummy_LSUDummy --> Forwarder6_write -TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write -TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write -TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write +LSUDummy_LSUDummy1 --> Forwarder6_write TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write -TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write +TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write +TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write +TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write +TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -774,43 +774,43 @@ CSRUnit_get_result --> ConnectTrans3_ConnectTrans MethodTryProduct_MethodTryProduct1 --> PrivilegedFuncUnit_precommit MethodTryProduct_MethodTryProduct1 <--> InterruptController_mret -MethodTryProduct_MethodTryProduct2 --> LSUDummy_precommit -MethodTryProduct_MethodTryProduct --> CSRUnit_precommit +MethodTryProduct_MethodTryProduct --> LSUDummy_precommit +MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans ReorderBuffer_peek --> Retirement_Retirement1 -ReorderBuffer_peek --> Retirement_Retirement4 -ReorderBuffer_peek --> Retirement_Retirement3 -ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 +ReorderBuffer_peek --> Retirement_Retirement2 +ReorderBuffer_peek --> Retirement_Retirement +ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement Retirement_Retirement1 --> MethodTryProduct_method -ExceptionCauseRegister_get --> Retirement_Retirement4 -ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 +ExceptionCauseRegister_get --> Retirement_Retirement2 +ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement3 <--> ReorderBuffer_retire -TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire +Retirement_Retirement <--> ReorderBuffer_retire +TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire -Retirement_Retirement3 <--> LatencyMeasurer1__stop -TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop +Retirement_Retirement <--> LatencyMeasurer1__stop +TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop -FIFO3_read --> Retirement_Retirement3 -FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 +FIFO3_read --> Retirement_Retirement +FIFO3_read --> TransactionManager_Retirement_cond0_Retirement FIFO3_read --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement3 --> HwExpHistogram1__add -TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add +Retirement_Retirement --> HwExpHistogram1__add +TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add -CoreInstructionCounter_decrement --> Retirement_Retirement3 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 +CoreInstructionCounter_decrement --> Retirement_Retirement +CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement -RRAT_peek --> Retirement_Retirement3 +RRAT_peek --> Retirement_Retirement RRAT_peek --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement3 --> RegisterFile_free -TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free +Retirement_Retirement --> RegisterFile_free +TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free -CSRRegister1_read --> Retirement_Retirement -Retirement_Retirement <--> ExceptionCauseRegister_clear +CSRRegister1_read --> Retirement_Retirement4 +Retirement_Retirement4 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -822,56 +822,56 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans2_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt -TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy1 -TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy1 -LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 +TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_cond0_Retirement --> RRAT_commit +TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment +CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write +CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write +TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr +TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement3 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3 +TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write +TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write +TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write +TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write +TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry +TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry +TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy2 +TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2 LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 -TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 -Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond0 -BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 +LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 +TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 +Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond1 BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 -WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 +BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 -Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 +WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 -TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy2 -TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy2 -TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy2 +Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 +TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy +TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy +TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy +TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue -TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue -TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 -TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write -TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer2 +TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 +TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read +TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer2 +TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write -TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write +TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request -TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request -TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 -TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2 -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement2 -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write -TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry -TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry -TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit -TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment -CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write -CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write -TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr -TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 -Serializer1_Serializer1 --> TransactionManager_LSUDummy_accept_cond1 -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 -TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 -TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read -TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3 +TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 +TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write +TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 +TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 +TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 +Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond0 @@ -882,7 +882,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/components/icache.html b/components/icache.html index 2c50789ee..f2b0d3a15 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index fc16564af..acf3c8004 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -124,7 +124,7 @@

Submodules
-deserialize_addr(raw_addr: Value) → dict[str, amaranth.hdl.ast.Value]
+deserialize_addr(raw_addr: Value) → dict[str, amaranth.hdl._ast.Value]
@@ -241,7 +241,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 705937a20..3fb57cebd 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -340,7 +340,7 @@

Submodules
-instr_mux(sel: Value, inputs: list[amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | tuple[amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable]]) → tuple[amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable]
+instr_mux(sel: Value, inputs: list[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]) → tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]

@@ -368,7 +368,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/coreblocks.fu.html b/coreblocks.fu.html index 6a354b540..5371f33e1 100644 --- a/coreblocks.fu.html +++ b/coreblocks.fu.html @@ -236,7 +236,7 @@

Submodules
-coreblocks.fu.div_unit.get_input(arg: Record) → tuple[amaranth.hdl.ast.Value, amaranth.hdl.ast.Value]
+coreblocks.fu.div_unit.get_input(arg: Record) → tuple[amaranth.hdl._ast.Value, amaranth.hdl._ast.Value]
@@ -965,7 +965,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/coreblocks.fu.unsigned_multiplication.html b/coreblocks.fu.unsigned_multiplication.html index 0ffaef62b..265990af8 100644 --- a/coreblocks.fu.unsigned_multiplication.html +++ b/coreblocks.fu.unsigned_multiplication.html @@ -237,7 +237,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/coreblocks.html b/coreblocks.html index b4caa05d4..67963c8c9 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -234,7 +234,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/coreblocks.lsu.html b/coreblocks.lsu.html index cbb68601a..c8710f148 100644 --- a/coreblocks.lsu.html +++ b/coreblocks.lsu.html @@ -236,7 +236,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/coreblocks.params.html b/coreblocks.params.html index b196673c9..09be8e8ba 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -314,7 +314,7 @@

SubmodulesRISCVInstr

-__init__(opcode: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, imm: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, funct3: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, rs1: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, rs2: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable)
+__init__(opcode: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -341,7 +341,7 @@

SubmodulesRISCVInstr

-__init__(opcode: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, rd: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, funct3: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, rs1: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, imm: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable)
+__init__(opcode: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -373,7 +373,7 @@

SubmodulesRISCVInstr

-__init__(opcode: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, rd: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, imm: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable)
+__init__(opcode: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -389,7 +389,7 @@

SubmodulesRISCVInstr

-__init__(opcode: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, rd: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, funct3: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, rs1: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, rs2: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, funct7: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable)
+__init__(opcode: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct7: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -405,7 +405,7 @@

SubmodulesRISCVInstr

-__init__(opcode: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, imm: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, funct3: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, rs1: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, rs2: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable)
+__init__(opcode: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -421,7 +421,7 @@

SubmodulesRISCVInstr

-__init__(opcode: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, rd: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable, imm: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable)
+__init__(opcode: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -2701,7 +2701,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index ea1b480dc..60ca692af 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -598,7 +598,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index d2a84c70e..fa33b8076 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/coreblocks.stages.html b/coreblocks.stages.html index e3a4fc8dd..a61ced1a2 100644 --- a/coreblocks.stages.html +++ b/coreblocks.stages.html @@ -263,7 +263,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/coreblocks.structs_common.html b/coreblocks.structs_common.html index a21cc5e10..6fab03ea7 100644 --- a/coreblocks.structs_common.html +++ b/coreblocks.structs_common.html @@ -522,7 +522,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/coreblocks.utils.html b/coreblocks.utils.html index a61b73560..393cb7a0a 100644 --- a/coreblocks.utils.html +++ b/coreblocks.utils.html @@ -149,7 +149,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/current-graph.html b/current-graph.html index ec91adc1b..160968cf3 100644 --- a/current-graph.html +++ b/current-graph.html @@ -92,12 +92,12 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/development-environment.html b/development-environment.html index 373472b3d..397322f8c 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/genindex.html b/genindex.html index 48a0f19b5..ee77323d7 100644 --- a/genindex.html +++ b/genindex.html @@ -3754,7 +3754,7 @@

Z

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/home.html b/home.html index 84f730a38..57feccdc4 100644 --- a/home.html +++ b/home.html @@ -129,7 +129,7 @@

Documentation

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/index.html b/index.html index 912db2708..fd5264b16 100644 --- a/index.html +++ b/index.html @@ -229,7 +229,7 @@

Coreblocks

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html index 37ebe736b..a11b9c72c 100644 --- a/miscellany/exceptions-summary.html +++ b/miscellany/exceptions-summary.html @@ -271,7 +271,7 @@

Summary

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/modules-coreblocks.html b/modules-coreblocks.html index 89d460b88..cf26944d7 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -203,7 +203,7 @@

coreblocks

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/modules-transactron.html b/modules-transactron.html index 46abd356f..b8a31464d 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -148,7 +148,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/problem-checklist.html b/problem-checklist.html index 81379f282..59d0fa908 100644 --- a/problem-checklist.html +++ b/problem-checklist.html @@ -105,7 +105,7 @@

Problem checklist

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/py-modindex.html b/py-modindex.html index 0dd36f78a..25a79562d 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -613,7 +613,7 @@

Python Module Index

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/scheduler/overview.html b/scheduler/overview.html index d0ab2223d..1415569ec 100644 --- a/scheduler/overview.html +++ b/scheduler/overview.html @@ -146,7 +146,7 @@

More detailed description of each block

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/search.html b/search.html index 8a2757781..23940dc65 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/searchindex.js b/searchindex.js index 29570c4f8..52dfa8d13 100644 --- a/searchindex.js +++ b/searchindex.js @@ -1 +1 @@ -Search.setIndex({"docnames": ["api", "assumptions", "auto_graph", "components/icache", "coreblocks", "coreblocks.cache", "coreblocks.frontend", "coreblocks.fu", "coreblocks.fu.unsigned_multiplication", "coreblocks.lsu", "coreblocks.params", "coreblocks.peripherals", "coreblocks.scheduler", "coreblocks.stages", "coreblocks.structs_common", "coreblocks.utils", "current-graph", "development-environment", "home", "index", "miscellany/exceptions-summary", "modules-coreblocks", "modules-transactron", "problem-checklist", "scheduler/overview", "shared-structs/implementation/rs-impl", "shared-structs/rs", "synthesis/synthesis", "transactions", "transactron", "transactron.lib", "transactron.testing", "transactron.utils", "transactron.utils.amaranth_ext"], "filenames": ["api.md", "assumptions.md", "auto_graph.rst", "components/icache.md", "coreblocks.rst", "coreblocks.cache.rst", "coreblocks.frontend.rst", "coreblocks.fu.rst", "coreblocks.fu.unsigned_multiplication.rst", "coreblocks.lsu.rst", "coreblocks.params.rst", "coreblocks.peripherals.rst", "coreblocks.scheduler.rst", "coreblocks.stages.rst", "coreblocks.structs_common.rst", "coreblocks.utils.rst", "current-graph.md", "development-environment.md", "home.md", "index.md", "miscellany/exceptions-summary.md", "modules-coreblocks.rst", "modules-transactron.rst", "problem-checklist.md", "scheduler/overview.md", "shared-structs/implementation/rs-impl.md", "shared-structs/rs.md", "synthesis/synthesis.md", "transactions.md", "transactron.rst", "transactron.lib.rst", "transactron.testing.rst", "transactron.utils.rst", "transactron.utils.amaranth_ext.rst"], "titles": ["API", "List of assumptions made during development", "<no title>", "Instruction Cache", "coreblocks package", "coreblocks.cache package", "coreblocks.frontend package", "coreblocks.fu package", "coreblocks.fu.unsigned_multiplication package", "coreblocks.lsu package", "coreblocks.params package", "coreblocks.peripherals package", "coreblocks.scheduler package", "coreblocks.stages package", "coreblocks.structs_common package", "coreblocks.utils package", "Full transaction-method graph", "Development environment", "Introduction", "Coreblocks", "Summary of papers about interrupts", "coreblocks", "transactron", "Problem checklist", "Scheduler overview", "Proposition of Reservation Station implementation", "Reservation Station", "Core verification", "Documentation for Coreblocks transaction framework", "transactron package", "transactron.lib package", "transactron.testing package", "transactron.utils package", "transactron.utils.amaranth_ext package"], "terms": {"packag": [0, 17, 19, 21, 22], "subpackag": [0, 21, 22], "cach": [0, 4, 6, 10, 19, 21, 32], "submodul": [0, 21, 22, 27], "icach": [0, 4, 6, 21, 30], "modul": [0, 17, 21, 22, 27, 28], "ifac": [0, 4, 21, 30], "refil": [0, 3, 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"arbitrarili": 3, "long": [3, 26, 27, 30], "ensur": [3, 27], "ani": [3, 6, 11, 12, 20, 23, 30, 31, 32, 33], "refetch": 3, "howev": [3, 30], "guarante": [3, 20], "have": [3, 9, 11, 13, 14, 17, 20, 23, 27, 28, 29, 30, 31, 32, 33], "alreadi": [3, 13, 20, 30, 32], "been": 3, "still": [3, 20, 26, 29], "wait": [3, 11, 13, 14, 17, 20, 25, 26, 29, 31], "accept": [3, 5, 7, 8, 14, 15, 27, 29, 30, 32], "inform": [3, 9, 12, 17, 29, 30, 32], "regard": 3, "error": [3, 5, 10, 11, 29, 30, 32], "mean": [3, 12, 17, 26, 29, 30], "dure": [3, 9, 19, 24, 30, 31], "line": [3, 5, 10, 17, 19], "subsequ": 3, "access": [3, 10, 11, 14, 20, 28, 30, 31, 32], "trigger": [3, 14], "which": [3, 5, 6, 7, 9, 10, 11, 12, 13, 17, 18, 20, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33], "most": [3, 20, 28, 29, 30], "like": [3, 6, 11, 20, 28, 29, 30], "For": [3, 10, 17, 25, 26, 28, 30, 32, 33], "32": [3, 7, 8, 10, 11, 20, 28, 30], "128": [3, 10], "set": [3, 5, 6, 7, 9, 10, 12, 13, 14, 19, 25, 27, 29, 30, 32, 33], "size": [3, 10, 11, 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6, 7, 9, 10, 12, 13, 14, 19, 20, 24, 25, 27], "replac": [5, 8, 10, 25], "polici": 5, "pseudo": 5, "random": [5, 31], "scheme": 5, "everi": [5, 7, 11, 17, 27, 29, 30], "time": [5, 11, 14, 20, 29, 30], "trash": 5, "we": [5, 9, 13, 20, 24, 25, 26, 27, 28, 31], "select": [5, 6, 7, 9, 11, 12, 13, 14, 15, 17], "next": [5, 6, 9, 12, 13, 14, 20, 29, 33], "wai": [5, 7, 11, 17, 20, 27, 28, 29, 30, 32], "keep": [5, 29], "global": [5, 14, 20], "counter": [5, 10, 14, 17, 30], "abstract": [5, 8, 10, 27, 30, 32], "awai": 5, "need": [5, 11, 17, 20, 25, 28, 29], "two": [5, 10, 14, 20, 23, 27, 28, 29, 30, 31, 32], "refiller_start": 5, "call": [5, 7, 12, 14, 17, 23, 25, 28, 29, 30, 31, 32], "whenev": 5, "refiller_accept": 5, "readi": [5, 9, 10, 11, 12, 13, 14, 19, 25, 29, 30], "word": [5, 10], "written": [5, 14, 26, 27, 30], "last": [5, 10, 12, 14, 29, 30], "when": [5, 11, 14, 17, 20, 23, 25, 26, 28, 29, 30, 31, 32, 33], "either": [5, 11, 28, 29, 30, 32, 33], "transfer": [5, 11, 29, 30], "over": [5, 14, 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30, 31, 32, 33], "ast": [5, 6, 7, 10, 29, 30, 31, 32, 33], "serialize_addr": 5, "addr": [5, 9, 10, 11, 30], "record": [5, 7, 9, 11, 23, 28, 29, 30, 31, 32, 33], "icachebypass": 5, "bus_mast": 5, "busmasterinterfac": [5, 9, 10, 11], "haselabor": [5, 11, 15, 29, 30, 31, 33], "interfac": [5, 6, 8, 9, 11, 12, 13, 14, 19, 27, 28, 29, 30], "whole": [5, 18, 20, 30], "given": [5, 7, 9, 10, 17, 25, 28, 29, 30, 31, 32, 33], "simplecommonbuscacherefil": 5, "decodestag": 6, "decod": [6, 7, 10, 12, 29, 32], "transact": [6, 10, 11, 14, 17, 19, 25, 29, 30, 33], "instanti": [6, 29], "instrdecod": 6, "make": [6, 7, 17, 18, 20, 23, 27, 28, 31], "actual": [6, 17, 19, 28], "combinatori": [6, 28], "manner": [6, 11], "get_raw": 6, "push_decod": 6, "raw": 6, "previou": [6, 11, 20, 30], "step": [6, 12, 17, 20, 27, 28], "e": [6, 10, 17, 20, 23, 28, 30, 32, 33], "g": [6, 10, 17, 20, 23, 28, 30, 32, 33], "fetchlayout": [6, 10], "send": [6, 10, 11, 12, 13], "It": [6, 7, 8, 9, 11, 12, 13, 17, 20, 24, 25, 27, 28, 29, 30, 31, 32, 33], "describ": [6, 10, 12, 13, 20, 27, 29, 30, 31], "decodelayout": [6, 10, 12], "pc": [6, 10, 14, 19], "insid": [6, 27, 28, 29, 30], "increment": [6, 14], "ilen_byt": 6, "cont": [6, 31], "unalignedfetch": 6, "work": [6, 12, 20, 23, 27, 28, 29], "unalign": 6, "perform": [6, 7, 8, 10, 12, 14, 17, 27, 28, 29, 30, 32, 33], "elementari": 6, "compon": [6, 10, 18, 29, 30], "opcod": [6, 10, 25, 26], "funct3": [6, 7, 10], "etc": [6, 10, 28], "connect": [6, 11, 13, 14, 20, 28, 29, 30], "via": [6, 28, 29], "its": [6, 12, 13, 14, 20, 27, 28, 29, 30, 32, 33], "attribut": [6, 7, 8, 9, 10, 11, 13, 14, 29, 30, 32, 33], "signal": [6, 7, 9, 10, 11, 19, 23, 29, 30, 31, 32, 33], "ilen": [6, 10], "out": [6, 7, 8, 11, 13, 18, 19, 29, 30, 33], "identifi": [6, 10, 25, 30, 32], "funct3_v": 6, "1": [6, 7, 8, 10, 12, 14, 20, 25, 26, 27, 28, 29, 30, 31, 32, 33], "funct7": [6, 7, 10], "seven": 6, "funct7_v": 6, "funct12": [6, 10], "twelv": 6, "funct12_v": 6, "rd": [6, 10], "reg_cnt_log": 6, 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10, 12, 17, 19, 29, 30], "constructor": [6, 28, 29, 32], "encod": [6, 20, 29, 32, 33], "object": [6, 7, 9, 10, 11, 27, 28, 29, 30, 31, 32], "repres": [6, 14, 29, 30], "singl": [6, 7, 8, 10, 12, 13, 14, 28, 29, 30, 32], "option": [6, 7, 10, 14, 17, 28, 29, 30, 31, 32, 33], "exist": [6, 28, 32], "instr_type_overrid": 6, "instrtyp": [6, 10], "specifi": [6, 10, 11, 14, 26, 30, 31, 32], "determin": [6, 20, 27, 30, 32], "instrust": 6, "almost": 6, "correct": [6, 9, 20, 25, 26, 27], "rd_zero": 6, "bool": [6, 7, 9, 10, 11, 14, 29, 30, 31, 32, 33], "field": [6, 9, 10, 14, 17, 25, 26, 28, 29, 30, 31, 32], "constant": 6, "zero": [6, 10, 14, 25, 30, 33], "other": [6, 14, 17, 19, 28, 29, 30, 33], "accordingli": 6, "default": [6, 11, 17, 28, 29, 30, 32, 33], "fals": [6, 7, 9, 10, 17, 28, 29, 30, 32, 33], "rs1_zero": 6, "instrdecompress": 6, "decompr_reg": 6, "rvc_reg": 6, "instr_mux": 6, "sel": 6, "list": [6, 7, 10, 11, 14, 17, 19, 23, 27, 29, 30, 31, 32, 33], "int": [6, 7, 8, 9, 10, 11, 13, 14, 29, 30, 31, 32, 33], "enum": [6, 7, 10, 29, 30, 31, 32], "valuecast": [6, 10, 29, 30, 31, 32], "tupl": [6, 7, 10, 12, 13, 14, 29, 30, 32], "is_instr_compress": 6, "alucompon": [7, 10], "functionalcomponentparam": [7, 10, 13], "zba_en": 7, "zbb_enabl": 7, "get_modul": [7, 9, 10, 13, 14], "funcunit": [7, 10, 13, 15], "get_optyp": [7, 9, 10, 13, 14], "alufuncunit": 7, "alu_fn": 7, "alufn": 7, "divcompon": 7, "ipc": [7, 27], "3": [7, 10, 14, 17, 29, 32], "div_fn": 7, "divfn": 7, "decodermanag": 7, "fn": 7, "intflag": [7, 10, 29], "div": [7, 10], "divu": [7, 10], "2": [7, 8, 10, 11, 14, 27, 29, 30, 32], "rem": [7, 10], "remu": [7, 10], "8": [7, 8, 10, 11, 29, 30], "__new__": [7, 10, 14, 29], "get_instruct": 7, "valid": [7, 10, 11, 12, 25, 30, 32, 33], "implement": [7, 9, 11, 18, 19, 20, 24, 30, 32, 33], "format": [7, 17, 27, 28, 29, 30, 32], "divunit": 7, "get_input": 7, "arg": [7, 11, 28, 29, 30, 31, 32, 33], "exceptionfuncunit": 7, "unit_fn": 7, "exceptionunitfn": 7, "exceptionunitcompon": [7, 10], "respons": [7, 11, 12, 17, 29, 30, 31], "decode_fn": 7, "exec_fn": [7, 10], "op": [7, 10], "check_optyp": 7, "manag": [7, 17, 19, 29, 30, 32], "enumer": 7, "get_decod": 7, "auto": 7, "pass": [7, 13, 14, 17, 19, 27, 29, 30, 31, 32], "contructor": 7, "get_funct": 7, "get_op_typ": 7, "jumpbranchfuncunit": 7, "jb_fn": 7, "jumpbranchfn": 7, "jumpcompon": [7, 10], "mulcompon": 7, "mul_unit_typ": 7, "multyp": 7, "dsp_width": [7, 8], "mul_fn": 7, "mulfn": 7, "hot": [7, 20, 33], "wire": [7, 32], "5": [7, 10, 24, 30, 31], "differ": [7, 11, 13, 17, 18, 20, 23, 27, 29, 30, 32], "mul": [7, 10], "mulh": [7, 10], "mulhsu": [7, 10], "mulhu": [7, 10], "intenum": [7, 10, 14], "recursive_mul": 7, "fastest": 7, "multipli": [7, 8], "onli": [7, 11, 14, 20, 27, 28, 29, 30, 31, 32], "costli": [7, 20], "term": 7, "resourc": [7, 14, 20, 27, 28], "sequence_mul": 7, "dsp": [7, 8], "balanc": 7, "between": [7, 17, 20, 28, 29, 30, 32, 33], "cost": [7, 19, 28], "shift_mul": 7, "cheapest": 7, "russian": [7, 8], "peasant": [7, 8], "algorithm": [7, 8], "mulunit": 7, "unsign": [7, 8], "integ": [7, 10, 32], "standard": [7, 14, 20, 27, 33], "funcunitlayout": [7, 10, 12, 13], "comput": [7, 8, 9, 14, 20, 30, 32], "mul_typ": 7, "privilegedfn": 7, "mret": [7, 10], "classmethod": [7, 29, 30, 32], "privilegedfuncunit": 7, "gp": [7, 10, 14], "privilegedunitcompon": [7, 10], "shiftfuncunit": 7, "shift_unit_fn": 7, "shiftunitfn": 7, "shiftunitcompon": [7, 10], "clmultipli": 7, "carri": [7, 10, 27], "less": [7, 10], "product": [7, 30], "i1": [7, 8], "n": [7, 8, 10], "factor": 7, "i2": [7, 8], "reset": [7, 14, 19, 29], "new": [7, 9, 11, 14, 19, 20, 29, 30, 32, 33], "busi": 7, "while": [7, 29, 31], "progress": 7, "bit_width": 7, "recursion_depth": 7, "width": [7, 8, 10, 11, 14, 30, 32, 33], "depth": [7, 11, 27, 30], "recurs": [7, 8, 27, 28, 29, 32], "parallel": 7, "assum": [7, 13, 20, 30, 32], "power": [7, 32], "iterative_modul": 7, "recursive_modul": 7, "zbccompon": 7, "zbc_fn": 7, "zbcfn": 7, "clmul": [7, 10], "clmulh": [7, 10], "clmulr": [7, 10], "zbcunit": 7, "execut": [7, 10, 11, 12, 13, 17, 19, 24, 26, 28, 29, 30, 31], "zbsfunction": 7, "in1": 7, "in2": 7, "zbscompon": 7, "bclr": [7, 10], "bext": [7, 10], "binv": [7, 10], "bset": [7, 10], "zbsunit": 7, "zbs_fn": 7, "dspmulunit": 8, "clock": [8, 24, 27, 28, 29, 30], "design": [8, 20, 28, 29], "synthesi": [8, 19], "tool": [8, 17, 27, 29], "o": [8, 20, 28, 29], "same": [8, 9, 17, 28, 29, 30, 32], "number": [8, 10, 11, 13, 17, 20, 27, 29, 30, 31, 32, 33], "mulbaseunsign": 8, "unsignedmulunitlayout": [8, 10], "recursiveunsignedmul": 8, "see": [8, 23, 27, 28, 30], "fast": 8, "within": [8, 17], "sequentialunsignedmul": 8, "sequenti": [8, 11], "classic": [8, 20], "shiftunsignedmul": 8, "cheap": 8, "multi": 8, "lsublockcompon": [9, 10], "blockcomponentparam": [9, 10, 13, 14], "funcblock": [9, 10, 12, 13, 14, 15], "get_rs_entry_count": [9, 10, 13, 14], "lsudummi": 9, "veri": [9, 20, 28], "serial": [9, 13, 30], "all": [9, 10, 11, 14, 17, 19, 20, 23, 28, 29, 30, 32, 33], "store": [9, 10, 13, 14, 20, 25, 26, 29, 30, 32], "load": [9, 10, 20, 30, 32], "isn": [9, 27, 29], "compliant": [9, 27], "riscv": [9, 27], "spec": 9, "doesn": [9, 20, 23, 28, 30], "check": [9, 17, 20, 23, 25, 26, 27, 29, 32], "rang": [9, 29, 30, 31, 32, 33], "reserv": [9, 10, 14, 19, 20], "place": [9, 11, 14, 20, 25, 27, 28, 29, 30], "intruct": 9, "insert": [9, 12, 13, 14, 15, 19, 20, 24, 25], "put": [9, 14, 25, 27, 30], "receiv": [9, 11, 14, 28, 29, 30], "calcul": [9, 30], "end": [9, 10, 13, 20, 30, 32], "further": [9, 17, 30], "get_result": [9, 13, 14, 15, 30], "To": [9, 17, 20, 27, 30, 32], "precommit": [9, 13, 17], "processor": [9, 18, 19, 24], "master": [9, 11, 27], "pmacheck": 9, "physic": [9, 10, 12, 20], "memori": [9, 10, 11, 20, 30], "checker": 9, "mai": [9, 17, 30, 31, 32], "part": [9, 14, 20, 24, 28, 29, 30], "combin": [9, 13, 19, 23, 29, 30, 32], "circuit": [9, 27, 28, 29, 30, 32], "pmaregion": [9, 10], "contigu": [9, 10], "region": [9, 20], "includ": [9, 27, 28, 29, 30, 32, 33], "both": [9, 25, 28, 29, 30, 32], "begin": [9, 20], "mmio": 9, "true": [9, 10, 11, 28, 29, 30, 31, 32, 33], "indic": [9, 20, 26, 29], "coreconfigur": 10, "func_units_config": 10, "collect": [10, 13, 14, 18, 27, 29, 30, 31, 32, 33], "station": [10, 19], "exampl": [10, 14, 17, 19, 25, 28, 29, 30, 33], "rsblockcompon": [10, 13], "rs_entri": [10, 13, 14], "compress": 10, "enabl": [10, 30, 31, 32], "embed": 10, "reduc": [10, 20, 29], "debug": [10, 17, 32], "hardwar": [10, 19, 24, 28, 30, 32], "disabl": [10, 30, 31], "them": [10, 17, 20, 27, 28, 29, 30, 32], "synthes": [10, 27, 30], "phys_regs_bit": 10, "file": [10, 17, 20, 27, 32], "rob_entries_bit": 10, "reorder": [10, 20, 30], "buffer": [10, 11, 20, 25, 30], "start_pc": 10, "initi": [10, 11, 19, 30, 31], "program": [10, 20, 27, 28], "icache_en": 10, "bypass": 10, "directli": [10, 28, 29], "icache_wai": 10, "icache_sets_bit": 10, "log": [10, 20], "icache_block_size_bit": 10, "allow_partial_extens": 10, "allow": [10, 18, 20, 27, 28, 29, 30, 33], "partial": [10, 29, 30, 32], "_implied_extens": 10, "extenst": 10, "flag": 10, "intern": [10, 19, 28, 29, 30], "definit": [10, 19, 29], "per": [10, 27], "segment": 10, "abc": [10, 29, 30, 31, 32, 33], "func_unit": [10, 13], "csrblockcompon": [10, 14], "6": [10, 20], "7": 10, "factori": [10, 29, 30, 32], "kwarg": [10, 11, 29, 30, 31, 32, 33], "optypes_support": 10, "iter": [10, 13, 14, 29, 30, 31, 32, 33], "dependentcach": [10, 32], "cfg": 10, "addr_width": [10, 11], "length": [10, 20, 29, 32], "word_width": 10, "machin": [10, 14], "num_of_wai": 10, "num_of_sets_bit": 10, "block_size_bit": 10, "btypeinstr": 10, "riscvinstr": 10, "pack": 10, "ebreakinstr": 10, "itypeinstr": 10, "illegalinstr": 10, "jtypeinstr": 10, "rtypeinstr": 10, "stypeinstr": 10, "utypeinstr": 10, "exceptioncaus": 10, "breakpoint": 10, "environment_call_from_m": 10, "environment_call_from_": 10, "9": 10, "environment_call_from_u": 10, "illegal_instruct": 10, "instruction_access_fault": 10, "instruction_address_misalign": 10, "instruction_page_fault": 10, "load_access_fault": 10, "load_address_misalign": 10, "load_page_fault": 10, "store_access_fault": 10, "store_address_misalign": 10, "store_page_fault": 10, "avail": [10, 11, 12, 14, 17, 18, 27, 30], "atom": [10, 25, 28], "b": 10, "512": 10, "manipul": 10, "256": 10, "d": [10, 28, 29, 32], "doubl": [10, 14, 20], "precis": [10, 20, 27], "float": [10, 29, 30, 31, 32], "point": [10, 20, 23, 27], "64": [10, 11], "f": [10, 12, 17, 27, 31], "98366": 10, "contain": [10, 17, 27, 28, 29, 30, 32], "basic": [10, 19, 27, 30], "full": [10, 17, 19, 20, 27, 30], "j": 10, "1024": 10, "dynam": [10, 20, 33], "languag": [10, 28], "l": [10, 17], "decim": 10, "m": [10, 11, 14, 17, 20, 27, 28, 29, 30, 33], "divis": 10, "16384": 10, "user": [10, 14, 20, 27, 30], "level": [10, 11, 18, 20, 27, 28], "interrupt": [10, 19], "p": [10, 17], "4096": 10, "simd": 10, "q": 10, "quad": 10, "2048": 10, "8192": 10, "vector": [10, 12, 19, 20], "xintmachinemod": 10, "8589934592": 10, "categor": 10, "privilieg": 10, "xintsupervisor": 10, "17179869184": 10, "supervisor": [10, 14], "zam": 10, "2097152": 10, "misalign": 10, "zba": 10, "268435456": 10, "extend": [10, 23, 29], "zbb": 10, "536870912": 10, "1073741824": 10, "2147483648": 10, "zdinx": 10, "33554432": 10, "zfh": 10, "4194304": 10, "half": 10, "zfhmin": 10, "8388608": 10, "minim": 10, "zfinx": 10, "16777216": 10, "zhinx": 10, "67108864": 10, "zicntr": 10, "524288": 10, "timer": [10, 14], "zicsr": 10, "32768": 10, "statu": [10, 14, 31], "zifencei": 10, "65536": 10, "zihintntl": 10, "262144": 10, "non": [10, 25, 29, 30], "tempor": 10, "local": [10, 14, 17], "hint": [10, 29], "zihintpaus": 10, "131072": 10, "paus": 10, "energi": 10, "zihpm": 10, "1048576": 10, "zmmul": 10, "134217728": 10, "ztso": 10, "4294967296": 10, "total": 10, "tso": 10, "dev_i": 10, "dev_o": 10, "mem_r": 10, "mem_w": 10, "clz": 10, "1536": 10, "cpop": 10, "1538": 10, "ctz": 10, "1537": 10, "ebreak": 10, "ecal": 10, "770": 10, "orcb": 10, "647": 10, "rev8_32": 10, "1688": 10, "rev8_64": 10, "1720": 10, "sextb": 10, "1540": 10, "sexth": 10, "1541": 10, "sret": 10, "258": 10, "wfi": 10, "261": 10, "zexth": 10, "add": [10, 28, 29, 30, 32], "AND": 10, "andn": 10, "beq": 10, "bge": 10, "bgeu": 10, "blt": 10, "bltu": 10, "bne": 10, "csrrc": 10, "csrrci": 10, "csrr": 10, "csrrsi": 10, "csrrw": 10, "csrrwi": 10, "divuw": 10, "divw": 10, "fencei": 10, "h": [10, 20], "hu": 10, "jalr": 10, "max": [10, 27], "maxu": 10, "min": [10, 30], "minu": 10, "mulw": 10, "OR": 10, "orn": 10, "remuw": 10, "remw": 10, "rev8": 10, "rol": 10, "ror": 10, "sh1add": 10, "sh2add": 10, "sh3add": 10, "sll": 10, "slt": 10, "sltu": 10, "sr": 10, "sub": 10, "w": [10, 20], "xnor": 10, "xor": 10, "36": 10, "52": 10, "20": 10, "48": 10, "muldiv": 10, "sa": 10, "sfencevma": 10, "sl": 10, "gather": 10, "numer": 10, "val": [10, 32], "correspond": [10, 25, 29, 33], "val_log": 10, "relev": [10, 29], "nativ": 10, "reg_cnt": 10, "maximum": [10, 27, 30], "bitwis": 10, "isa_str": 10, "string": 10, "pleas": [10, 17, 23, 28], "refer": [10, 29, 32], "gcc": 10, "": [10, 11, 20, 28, 29, 30, 32, 33], "arch": [10, 17, 27], "detail": [10, 14, 19], "u": [10, 20, 27, 30, 32], "auipc": 10, "branch": [10, 20, 27, 30], "24": 10, "jal": 10, "27": 10, "25": 10, "load_fp": 10, "lui": 10, "misc_mem": 10, "op32": 10, "op_imm": 10, "op_imm_32": 10, "store_fp": 10, "system": [10, 27, 28, 32], "28": [10, 20], "a0": 10, "a1": 10, "a2": 10, "a3": 10, "a4": 10, "a5": 10, "a6": 10, "a7": 10, "17": 10, "fp": [10, 29], "ra": 10, "s0": 10, "s1": 10, "s10": 10, "26": 10, "s11": 10, "s2": 10, "18": 10, "s3": 10, "19": 10, "s4": 10, "s5": 10, "21": 10, "s6": 10, "22": 10, "s7": 10, "23": 10, "s8": 10, "s9": 10, "sp": 10, "t0": 10, "t1": [10, 28], "t2": [10, 28], "t3": 10, "t4": 10, "29": 10, "t5": 10, "30": [10, 20], "t6": 10, "tp": [10, 32], "x1": 10, "x10": 10, "x11": 10, "x12": 10, "x13": 10, "x14": 10, "x15": 10, "x16": 10, "x17": 10, "x18": 10, "x19": 10, "x2": 10, "x20": 10, "x21": 10, "x22": 10, "x23": 10, "x24": 10, "x25": 10, "x26": 10, "x27": 10, "x28": 10, "x29": 10, "x3": 10, "x30": 10, "x31": 10, "x4": 10, "x5": 10, "x6": 10, "x7": 10, "x8": 10, "x9": 10, "asyncinterruptinsertsignalkei": 10, "simplekei": [10, 29, 30, 32], "branchverifykei": 10, "commonbusdatakei": 10, "exceptionreportkei": 10, "fetchresumekei": 10, "unifierkei": [10, 13, 30], "unifi": [10, 30], "alia": 10, "collector": [10, 30], "genericcsrregisterskei": 10, "genericcsrregist": [10, 14], "instructionprecommitkei": 10, "methodtryproduct": [10, 30], "mretkei": 10, "csrlayout": 10, "commonlayoutfield": 10, "commonli": 10, "layoutlistfield": 10, "caus": [10, 20, 30, 32], "piec": 10, "rais": [10, 20, 29, 30, 31, 32], "exec_fn_layout": 10, "op_typ": 10, "reg_id": 10, "id": [10, 12, 25, 26, 29], "reg_val": 10, "some": [10, 14, 20, 23, 28, 29, 30, 32], "regs_l": 10, "logic": [10, 20, 26, 27, 28], "manual": [10, 19, 28], "thei": [10, 11, 14, 17, 20, 24, 27, 28, 29, 30], "regs_p": 10, "rl_dst": 10, "destin": 10, "operand": [10, 20, 25, 26], "rl_s1": 10, "rl_s2": 10, "rob_id": 10, "entri": [10, 12, 13, 20, 24, 25, 26, 30, 32], "rp_dst": 10, "rp_s1": 10, "rp_s2": 10, "s1_val": 10, "s2_val": 10, "side_fx": 10, "side": [10, 11, 14, 20, 25, 26], "effect": [10, 14, 20, 25, 26, 29, 30], "fetcher": 10, "access_fault": 10, "fail": [10, 20, 32], "produc": [10, 17], "jumpbranchlayout": 10, "verify_branch": 10, "predictor": 10, "about": [10, 17, 19, 29, 30, 32], "lsulayout": 10, "pmalayout": 10, "ratlayout": [10, 12], "tabl": [10, 19], "old_rp_dst": 10, "previous": [10, 11], "rrat": [10, 14], "rflayout": [10, 12], "roblayout": [10, 12], "done": [10, 20, 27, 28, 29, 30, 31], "yet": [10, 29], "latest": [10, 27, 30], "rob_data": 10, "earliest": [10, 14], "rsinterfacelayout": 10, "rs_entries_bit": 10, "data_layout": [10, 12, 30, 32], "shapelik": [10, 29, 30, 32], "layoutlist": [10, 29, 30, 32], "rslayout": [10, 12], "ready_list": 10, "bitmask": 10, "run": [10, 17, 27, 28, 29, 30, 31, 33], "retirementlayout": 10, "current": [10, 12, 14, 20, 29], "schedulerlayout": 10, "regs_l_rob_in": 10, "befor": [10, 11, 14, 17, 23, 24, 28, 30], "alloc": [10, 12, 24, 25, 26], "regs_p_alloc_out": 10, "rs_entry_id": 10, "rs_select": 10, "confus": 10, "address_gener": 10, "arithmet": 10, "bit_manipul": 10, "bit_rot": 10, "compar": [10, 19], "csr_imm": [10, 14], "csr_reg": [10, 14], "div_rem": 10, "34": 10, "33": 10, "single_bit_manipul": 10, "unary_bit_manipulation_1": 10, "unary_bit_manipulation_2": 10, "unary_bit_manipulation_3": 10, "unary_bit_manipulation_4": 10, "unary_bit_manipulation_5": 10, "unknown": [10, 17, 29, 30, 32], "optypes_required_by_extens": 10, "resolve_impl": 10, "ignore_unsupport": 10, "axilitemast": 11, "axi": 11, "lite": 11, "axil_param": 11, "axiliteparamet": 11, "ra_request": 11, "channel": 11, "being": [11, 17, 30, 32, 33], "ra_request_layout": 11, "argument": [11, 12, 17, 19, 26, 27, 29, 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"arbitrarili": 3, "long": [3, 26, 27, 30], "ensur": [3, 27], "ani": [3, 6, 11, 12, 20, 23, 30, 31, 32, 33], "refetch": 3, "howev": [3, 30], "guarante": [3, 20], "have": [3, 9, 11, 13, 14, 17, 20, 23, 27, 28, 29, 30, 31, 32, 33], "alreadi": [3, 13, 20, 30, 32], "been": 3, "still": [3, 20, 26, 29], "wait": [3, 11, 13, 14, 17, 20, 25, 26, 29, 31], "accept": [3, 5, 7, 8, 14, 15, 27, 29, 30, 32], "inform": [3, 9, 12, 17, 29, 30, 32], "regard": 3, "error": [3, 5, 10, 11, 29, 30, 32], "mean": [3, 12, 17, 26, 29, 30], "dure": [3, 9, 19, 24, 30, 31], "line": [3, 5, 10, 17, 19], "subsequ": 3, "access": [3, 10, 11, 14, 20, 28, 30, 31, 32], "trigger": [3, 14], "which": [3, 5, 6, 7, 9, 10, 11, 12, 13, 17, 18, 20, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33], "most": [3, 20, 28, 29, 30], "like": [3, 6, 11, 20, 28, 29, 30], "For": [3, 10, 17, 25, 26, 28, 30, 32, 33], "32": [3, 7, 8, 10, 11, 20, 28, 30], "128": [3, 10], "set": [3, 5, 6, 7, 9, 10, 12, 13, 14, 19, 25, 27, 29, 30, 32, 33], "size": [3, 10, 11, 20, 28, 30, 32], "equal": [3, 14], "31": [3, 10], "15": [3, 10], "14": [3, 10], "13": [3, 10], "12": [3, 10], "11": [3, 10, 17, 27], "10": [3, 10, 20], "09": 3, "08": 3, "07": 3, "06": [3, 31], "05": 3, "04": 3, "03": 3, "02": 3, "01": 3, "00": 3, "tag": [3, 11, 20, 25, 26], "index": [3, 10, 29, 33], "offset": 3, "unsigned_multipl": [4, 7], "common": [4, 7, 11, 30, 32], "fast_recurs": [4, 7], "sequenc": [4, 7, 12, 30], "shift": [4, 7, 10], "class": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 28, 29, 30, 31, 32, 33], "base": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 20, 29, 30, 31, 32, 33], "elaborat": [4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 28, 29, 30, 31, 32], "__init__": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 28, 29, 30, 31, 32, 33], "gen_param": [4, 6, 7, 8, 9, 10, 12, 13, 14], "wb_instr_bu": 4, "wishbonebu": [4, 11], "wb_data_bu": 4, "cacheinterfac": [5, 6], "A": [5, 10, 11, 27, 28, 29, 30, 32], "simpl": [5, 6, 9, 12, 13, 29, 30, 32, 33], "associ": [5, 10, 30], "instruct": [5, 6, 7, 9, 10, 12, 13, 14, 19, 20, 24, 25, 27], "replac": [5, 8, 10, 25], "polici": 5, "pseudo": 5, "random": [5, 31], "scheme": 5, "everi": [5, 7, 11, 17, 27, 29, 30], "time": [5, 11, 14, 20, 29, 30], "trash": 5, "we": [5, 9, 13, 20, 24, 25, 26, 27, 28, 31], "select": [5, 6, 7, 9, 11, 12, 13, 14, 15, 17], "next": [5, 6, 9, 12, 13, 14, 20, 29, 33], "wai": [5, 7, 11, 17, 20, 27, 28, 29, 30, 32], "keep": [5, 29], "global": [5, 14, 20], "counter": [5, 10, 14, 17, 30], "abstract": [5, 8, 10, 27, 30, 32], "awai": 5, "need": [5, 11, 17, 20, 25, 28, 29], "two": [5, 10, 14, 20, 23, 27, 28, 29, 30, 31, 32], "refiller_start": 5, "call": [5, 7, 12, 14, 17, 23, 25, 28, 29, 30, 31, 32], "whenev": 5, "refiller_accept": 5, "readi": [5, 9, 10, 11, 12, 13, 14, 19, 25, 29, 30], "word": [5, 10], "written": [5, 14, 26, 27, 30], "last": [5, 10, 12, 14, 29, 30], "when": [5, 11, 14, 17, 20, 23, 25, 26, 28, 29, 30, 31, 32, 33], "either": [5, 11, 28, 29, 30, 32, 33], "transfer": [5, 11, 29, 30], "over": [5, 14, 29, 30], "shouldn": [5, 27], "t": [5, 6, 9, 10, 17, 20, 23, 25, 27, 28, 29, 30, 31, 32], "until": [5, 20, 30], "start": [5, 7, 9, 10, 11, 20, 29, 30], "icachelayout": [5, 10], "icacheparamet": [5, 10], "cacherefillerinterfac": 5, "none": [5, 6, 7, 9, 10, 13, 14, 29, 30, 31, 32, 33], "paramet": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 28, 29, 30, 31, 32, 33], "instanc": [5, 6, 7, 9, 12, 13, 27, 29, 30, 31, 32], "us": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 19, 20, 23, 27, 28, 29, 30, 31, 32, 33], "creat": [5, 8, 17, 27, 28, 29, 30, 31, 32, 33], "gener": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 18, 20, 23, 27, 29, 30, 31, 32], "input": [5, 6, 7, 11, 13, 14, 20, 25, 26, 28, 29, 30, 33], "start_refil": 5, "accept_refil": 5, "deserialize_addr": 5, "raw_addr": 5, "valu": [5, 6, 7, 9, 10, 11, 12, 13, 14, 19, 23, 25, 26, 29, 30, 31, 32, 33], "dict": [5, 11, 28, 29, 30, 31, 32, 33], "str": [5, 10, 29, 30, 31, 32, 33], "amaranth": [5, 6, 7, 10, 11, 23, 27, 28, 29, 30, 31, 32, 33], "hdl": [5, 6, 7, 10, 29, 30, 31, 32, 33], "_ast": [5, 6, 7, 10, 29, 30, 31, 32, 33], "serialize_addr": 5, "addr": [5, 9, 10, 11, 30], "record": [5, 7, 9, 11, 23, 28, 29, 30, 31, 32, 33], "icachebypass": 5, "bus_mast": 5, "busmasterinterfac": [5, 9, 10, 11], "haselabor": [5, 11, 15, 29, 30, 31, 33], "interfac": [5, 6, 8, 9, 11, 12, 13, 14, 19, 27, 28, 29, 30], "whole": [5, 18, 20, 30], "given": [5, 7, 9, 10, 17, 25, 28, 29, 30, 31, 32, 33], "simplecommonbuscacherefil": 5, "decodestag": 6, "decod": [6, 7, 10, 12, 29, 32], "transact": [6, 10, 11, 14, 17, 19, 25, 29, 30, 33], "instanti": [6, 29], "instrdecod": 6, "make": [6, 7, 17, 18, 20, 23, 27, 28, 31], "actual": [6, 17, 19, 28], "combinatori": [6, 28], "manner": [6, 11], "get_raw": 6, "push_decod": 6, "raw": 6, "previou": [6, 11, 20, 30], "step": [6, 12, 17, 20, 27, 28], "e": [6, 10, 17, 20, 23, 28, 30, 32, 33], "g": [6, 10, 17, 20, 23, 28, 30, 32, 33], "fetchlayout": [6, 10], "send": [6, 10, 11, 12, 13], "It": [6, 7, 8, 9, 11, 12, 13, 17, 20, 24, 25, 27, 28, 29, 30, 31, 32, 33], "describ": [6, 10, 12, 13, 20, 27, 29, 30, 31], "decodelayout": [6, 10, 12], "pc": [6, 10, 14, 19], "insid": [6, 27, 28, 29, 30], "increment": [6, 14], "ilen_byt": 6, "cont": [6, 31], "unalignedfetch": 6, "work": [6, 12, 20, 23, 27, 28, 29], "unalign": 6, "perform": [6, 7, 8, 10, 12, 14, 17, 27, 28, 29, 30, 32, 33], "elementari": 6, "compon": [6, 10, 18, 29, 30], "opcod": [6, 10, 25, 26], "funct3": [6, 7, 10], "etc": [6, 10, 28], "connect": [6, 11, 13, 14, 20, 28, 29, 30], "via": [6, 28, 29], "its": [6, 12, 13, 14, 20, 27, 28, 29, 30, 32, 33], "attribut": [6, 7, 8, 9, 10, 11, 13, 14, 29, 30, 32, 33], "signal": [6, 7, 9, 10, 11, 19, 23, 29, 30, 31, 32, 33], "ilen": [6, 10], "out": [6, 7, 8, 11, 13, 18, 19, 29, 30, 33], "identifi": [6, 10, 25, 30, 32], "funct3_v": 6, "1": [6, 7, 8, 10, 12, 14, 20, 25, 26, 27, 28, 29, 30, 31, 32, 33], "funct7": [6, 7, 10], "seven": 6, "funct7_v": 6, "funct12": [6, 10], "twelv": 6, "funct12_v": 6, "rd": [6, 10], "reg_cnt_log": 6, "address": [6, 9, 10, 11, 14, 19, 20], "regist": [6, 10, 12, 14, 20, 24, 30, 32], "rd_v": 6, "rs1": [6, 10], "hold": [6, 11, 14, 30], "first": [6, 7, 10, 12, 20, 25, 26, 27, 28, 30, 31, 32], "rs1_v": 6, "take": [6, 11, 13, 24, 25, 28, 29, 30, 31, 32], "form": [6, 10, 14, 20, 27, 30], "rs2": [6, 10], "second": [6, 7, 10, 12, 25, 26, 27, 30], "rs2_v": 6, "imm": [6, 10], "xlen": [6, 7, 10, 14, 32], "immedi": [6, 10, 11], "provid": [6, 7, 10, 12, 14, 27, 28, 30, 31, 32], "were": [6, 20, 28], "succ": 6, "fencetarget": [6, 10], "successor": 6, "fenc": [6, 10], "pred": 6, "predecessor": 6, "fm": 6, "fencefm": [6, 10], "mode": [6, 10, 17, 20], "csr_alen": [6, 10], "control": [6, 10, 11, 14, 27, 29, 30, 33], "sourc": [6, 10, 12, 17, 25, 29, 30, 32], "type": [6, 7, 10, 17, 29, 30, 31, 32], "defin": [6, 9, 14, 28, 29, 30, 32, 33], "kind": [6, 7, 12, 30, 32], "illeg": 6, "wa": [6, 10, 14, 17, 20, 28, 29, 30, 32], "success": [6, 11, 31], "do": [6, 10, 20, 23, 28, 29], "fit": 6, "support": [6, 9, 10, 12, 17, 19, 29, 30], "constructor": [6, 28, 29, 32], "encod": [6, 20, 29, 32, 33], "object": [6, 7, 9, 10, 11, 27, 28, 29, 30, 31, 32], "repres": [6, 14, 29, 30], "singl": [6, 7, 8, 10, 12, 13, 14, 28, 29, 30, 32], "option": [6, 7, 10, 14, 17, 28, 29, 30, 31, 32, 33], "exist": [6, 28, 32], "instr_type_overrid": 6, "instrtyp": [6, 10], "specifi": [6, 10, 11, 14, 26, 30, 31, 32], "determin": [6, 20, 27, 30, 32], "instrust": 6, "almost": 6, "correct": [6, 9, 20, 25, 26, 27], "rd_zero": 6, "bool": [6, 7, 9, 10, 11, 14, 29, 30, 31, 32, 33], "field": [6, 9, 10, 14, 17, 25, 26, 28, 29, 30, 31, 32], "constant": 6, "zero": [6, 10, 14, 25, 30, 33], "other": [6, 14, 17, 19, 28, 29, 30, 33], "accordingli": 6, "default": [6, 11, 17, 28, 29, 30, 32, 33], "fals": [6, 7, 9, 10, 17, 28, 29, 30, 32, 33], "rs1_zero": 6, "instrdecompress": 6, "decompr_reg": 6, "rvc_reg": 6, "instr_mux": 6, "sel": 6, "list": [6, 7, 10, 11, 14, 17, 19, 23, 27, 29, 30, 31, 32, 33], "int": [6, 7, 8, 9, 10, 11, 13, 14, 29, 30, 31, 32, 33], "enum": [6, 7, 10, 29, 30, 31, 32], "valuecast": [6, 10, 29, 30, 31, 32], "tupl": [6, 7, 10, 12, 13, 14, 29, 30, 32], "is_instr_compress": 6, "alucompon": [7, 10], "functionalcomponentparam": [7, 10, 13], "zba_en": 7, "zbb_enabl": 7, "get_modul": [7, 9, 10, 13, 14], "funcunit": [7, 10, 13, 15], "get_optyp": [7, 9, 10, 13, 14], "alufuncunit": 7, "alu_fn": 7, "alufn": 7, "divcompon": 7, "ipc": [7, 27], "3": [7, 10, 14, 17, 29, 32], "div_fn": 7, "divfn": 7, "decodermanag": 7, "fn": 7, "intflag": [7, 10, 29], "div": [7, 10], "divu": [7, 10], "2": [7, 8, 10, 11, 14, 27, 29, 30, 32], "rem": [7, 10], "remu": [7, 10], "8": [7, 8, 10, 11, 29, 30], "__new__": [7, 10, 14, 29], "get_instruct": 7, "valid": [7, 10, 11, 12, 25, 30, 32, 33], "implement": [7, 9, 11, 18, 19, 20, 24, 30, 32, 33], "format": [7, 17, 27, 28, 29, 30, 32], "divunit": 7, "get_input": 7, "arg": [7, 11, 28, 29, 30, 31, 32, 33], "exceptionfuncunit": 7, "unit_fn": 7, "exceptionunitfn": 7, "exceptionunitcompon": [7, 10], "respons": [7, 11, 12, 17, 29, 30, 31], "decode_fn": 7, "exec_fn": [7, 10], "op": [7, 10], "check_optyp": 7, "manag": [7, 17, 19, 29, 30, 32], "enumer": 7, "get_decod": 7, "auto": 7, "pass": [7, 13, 14, 17, 19, 27, 29, 30, 31, 32], "contructor": 7, "get_funct": 7, "get_op_typ": 7, "jumpbranchfuncunit": 7, "jb_fn": 7, "jumpbranchfn": 7, "jumpcompon": [7, 10], "mulcompon": 7, "mul_unit_typ": 7, "multyp": 7, "dsp_width": [7, 8], "mul_fn": 7, "mulfn": 7, "hot": [7, 20, 33], "wire": [7, 32], "5": [7, 10, 24, 30, 31], "differ": [7, 11, 13, 17, 18, 20, 23, 27, 29, 30, 32], "mul": [7, 10], "mulh": [7, 10], "mulhsu": [7, 10], "mulhu": [7, 10], "intenum": [7, 10, 14], "recursive_mul": 7, "fastest": 7, "multipli": [7, 8], "onli": [7, 11, 14, 20, 27, 28, 29, 30, 31, 32], "costli": [7, 20], "term": 7, "resourc": [7, 14, 20, 27, 28], "sequence_mul": 7, "dsp": [7, 8], "balanc": 7, "between": [7, 17, 20, 28, 29, 30, 32, 33], "cost": [7, 19, 28], "shift_mul": 7, "cheapest": 7, "russian": [7, 8], "peasant": [7, 8], "algorithm": [7, 8], "mulunit": 7, "unsign": [7, 8], "integ": [7, 10, 32], "standard": [7, 14, 20, 27, 33], "funcunitlayout": [7, 10, 12, 13], "comput": [7, 8, 9, 14, 20, 30, 32], "mul_typ": 7, "privilegedfn": 7, "mret": [7, 10], "classmethod": [7, 29, 30, 32], "privilegedfuncunit": 7, "gp": [7, 10, 14], "privilegedunitcompon": [7, 10], "shiftfuncunit": 7, "shift_unit_fn": 7, "shiftunitfn": 7, "shiftunitcompon": [7, 10], "clmultipli": 7, "carri": [7, 10, 27], "less": [7, 10], "product": [7, 30], "i1": [7, 8], "n": [7, 8, 10], "factor": 7, "i2": [7, 8], "reset": [7, 14, 19, 29], "new": [7, 9, 11, 14, 19, 20, 29, 30, 32, 33], "busi": 7, "while": [7, 29, 31], "progress": 7, "bit_width": 7, "recursion_depth": 7, "width": [7, 8, 10, 11, 14, 30, 32, 33], "depth": [7, 11, 27, 30], "recurs": [7, 8, 27, 28, 29, 32], "parallel": 7, "assum": [7, 13, 20, 30, 32], "power": [7, 32], "iterative_modul": 7, "recursive_modul": 7, "zbccompon": 7, "zbc_fn": 7, "zbcfn": 7, "clmul": [7, 10], "clmulh": [7, 10], "clmulr": [7, 10], "zbcunit": 7, "execut": [7, 10, 11, 12, 13, 17, 19, 24, 26, 28, 29, 30, 31], "zbsfunction": 7, "in1": 7, "in2": 7, "zbscompon": 7, "bclr": [7, 10], "bext": [7, 10], "binv": [7, 10], "bset": [7, 10], "zbsunit": 7, "zbs_fn": 7, "dspmulunit": 8, "clock": [8, 24, 27, 28, 29, 30], "design": [8, 20, 28, 29], "synthesi": [8, 19], "tool": [8, 17, 27, 29], "o": [8, 20, 28, 29], "same": [8, 9, 17, 28, 29, 30, 32], "number": [8, 10, 11, 13, 17, 20, 27, 29, 30, 31, 32, 33], "mulbaseunsign": 8, "unsignedmulunitlayout": [8, 10], "recursiveunsignedmul": 8, "see": [8, 23, 27, 28, 30], "fast": 8, "within": [8, 17], "sequentialunsignedmul": 8, "sequenti": [8, 11], "classic": [8, 20], "shiftunsignedmul": 8, "cheap": 8, "multi": 8, "lsublockcompon": [9, 10], "blockcomponentparam": [9, 10, 13, 14], "funcblock": [9, 10, 12, 13, 14, 15], "get_rs_entry_count": [9, 10, 13, 14], "lsudummi": 9, "veri": [9, 20, 28], "serial": [9, 13, 30], "all": [9, 10, 11, 14, 17, 19, 20, 23, 28, 29, 30, 32, 33], "store": [9, 10, 13, 14, 20, 25, 26, 29, 30, 32], "load": [9, 10, 20, 30, 32], "isn": [9, 27, 29], "compliant": [9, 27], "riscv": [9, 27], "spec": 9, "doesn": [9, 20, 23, 28, 30], "check": [9, 17, 20, 23, 25, 26, 27, 29, 32], "rang": [9, 29, 30, 31, 32, 33], "reserv": [9, 10, 14, 19, 20], "place": [9, 11, 14, 20, 25, 27, 28, 29, 30], "intruct": 9, "insert": [9, 12, 13, 14, 15, 19, 20, 24, 25], "put": [9, 14, 25, 27, 30], "receiv": [9, 11, 14, 28, 29, 30], "calcul": [9, 30], "end": [9, 10, 13, 20, 30, 32], "further": [9, 17, 30], "get_result": [9, 13, 14, 15, 30], "To": [9, 17, 20, 27, 30, 32], "precommit": [9, 13, 17], "processor": [9, 18, 19, 24], "master": [9, 11, 27], "pmacheck": 9, "physic": [9, 10, 12, 20], "memori": [9, 10, 11, 20, 30], "checker": 9, "mai": [9, 17, 30, 31, 32], "part": [9, 14, 20, 24, 28, 29, 30], "combin": [9, 13, 19, 23, 29, 30, 32], "circuit": [9, 27, 28, 29, 30, 32], "pmaregion": [9, 10], "contigu": [9, 10], "region": [9, 20], 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27, "manual": 27, "reproduct": 27, "depend": [27, 30, 32], "benchmark": 27, "regress": 27, "test": [27, 31], "framework": 28, "basic": 28, "usag": 28, "argument": 28, "pass": 28, "convent": 28, "definit": 28, "return": 28, "valu": 28, "The": 28, "librari": 28, "advanc": 28, "concept": 28, "special": 28, "combin": 28, "domain": 28, "conflict": 28, "nest": 28, "profil": [29, 31], "trace": 29, "lib": 30, "adapt": 30, "button": 30, "connector": 30, "fifo": 30, "metric": 30, "reqr": 30, "simultan": 30, "storag": 30, "transform": 30, "assert": [31, 32], "function": [31, 33], "gtkw_extens": 31, "infrastructur": 31, "sugar": 31, "testbenchio": 31, "assign": 32, "data_repr": 32, "debug_sign": 32, "depcach": 32, "gen": 32, "transactron_help": 32, "amaranth_ext": 33, "elaborat": 33}, "envversion": {"sphinx.domains.c": 2, "sphinx.domains.changeset": 1, "sphinx.domains.citation": 1, "sphinx.domains.cpp": 6, "sphinx.domains.index": 1, "sphinx.domains.javascript": 2, "sphinx.domains.math": 2, "sphinx.domains.python": 3, "sphinx.domains.rst": 2, "sphinx.domains.std": 2, "sphinx.ext.todo": 2, "sphinx": 56}}) \ No newline at end of file diff --git a/shared-structs/implementation/rs-impl.html b/shared-structs/implementation/rs-impl.html index 5cf8c0196..b47cec00e 100644 --- a/shared-structs/implementation/rs-impl.html +++ b/shared-structs/implementation/rs-impl.html @@ -252,7 +252,7 @@

Read and clean row

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/shared-structs/rs.html b/shared-structs/rs.html index 7842f3a8a..a60e0de58 100644 --- a/shared-structs/rs.html +++ b/shared-structs/rs.html @@ -222,7 +222,7 @@

External interface signals

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/synthesis/synthesis.html b/synthesis/synthesis.html index 0ff9a7e96..efb7a5c69 100644 --- a/synthesis/synthesis.html +++ b/synthesis/synthesis.html @@ -266,7 +266,7 @@

Regression tests manual execution

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/transactions.html b/transactions.html index 15ca3f924..02599b875 100644 --- a/transactions.html +++ b/transactions.html @@ -409,7 +409,7 @@

Transaction and method nesting

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/transactron.html b/transactron.html index 156f84a66..6203bff52 100644 --- a/transactron.html +++ b/transactron.html @@ -187,7 +187,7 @@

Submodules
-__init__(*, name: Optional[str] = None, i: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl.ast.Shape | amaranth.hdl.ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]] = (), o: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl.ast.Shape | amaranth.hdl.ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]] = (), nonexclusive: bool = False, single_caller: bool = False, src_loc: int | tuple[str, int] = 0)
+__init__(*, name: Optional[str] = None, i: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]] = (), o: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]] = (), nonexclusive: bool = False, single_caller: bool = False, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -217,7 +217,7 @@

Submodules
-body(m: ~transactron.core.TModule, *, ready: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1), out: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 0'd0), validate_arguments: ~typing.Optional[~collections.abc.Callable[[...], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable]] = None) → Iterator[View[StructLayout]]
+body(m: ~transactron.core.TModule, *, ready: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable = (const 1'd1), out: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable = (const 0'd0), validate_arguments: ~typing.Optional[~collections.abc.Callable[[...], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]] = None) → Iterator[View[StructLayout]]

Define method body

The body context manager can be used to define the actions performed by a Method when it’s run. Each assignment added to @@ -267,7 +267,7 @@

Submodules
-debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -373,7 +373,7 @@

Submodules
-AvoidedIf(cond: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable)
+AvoidedIf(cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

@@ -403,7 +403,7 @@

Submodules
-If(cond: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable)
+If(cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

@@ -413,7 +413,7 @@

Submodules
-Switch(test: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable)
+Switch(test: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

@@ -495,7 +495,7 @@

Submodules
-body(m: ~transactron.core.TModule, *, request: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1)) → Iterator[Transaction]
+body(m: ~transactron.core.TModule, *, request: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable = (const 1'd1)) → Iterator[Transaction]

Defines the Transaction body.

This context manager allows to conveniently define the actions performed by a Transaction when it’s granted. Each assignment @@ -519,7 +519,7 @@

Submodules
-debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -534,7 +534,7 @@

Submodules
-__init__(cc_scheduler: ~collections.abc.Callable[[~transactron.core.MethodMap, dict[transactron.core.Transaction, set[transactron.core.Transaction]], set[transactron.core.Transaction], dict[transactron.core.Transaction, int]], ~amaranth.hdl.dsl.Module] = <function eager_deterministic_cc_scheduler>)
+__init__(cc_scheduler: ~collections.abc.Callable[[~transactron.core.MethodMap, dict[transactron.core.Transaction, set[transactron.core.Transaction]], set[transactron.core.Transaction], dict[transactron.core.Transaction, int]], ~amaranth.hdl._dsl.Module] = <function eager_deterministic_cc_scheduler>)

@@ -544,7 +544,7 @@

Submodules
-debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -608,7 +608,7 @@

Submodules
-transactron.core.def_method(m: ~transactron.core.TModule, method: ~transactron.core.Method, ready: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1), validate_arguments: ~typing.Optional[~collections.abc.Callable[[...], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable]] = None)
+transactron.core.def_method(m: ~transactron.core.TModule, method: ~transactron.core.Method, ready: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable = (const 1'd1), validate_arguments: ~typing.Optional[~collections.abc.Callable[[...], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]] = None)

Define a method.

This decorator allows to define transactional methods in an elegant way using Python’s def syntax. Internally, def_method @@ -1021,7 +1021,7 @@

Submodules
-subfragments: list[tuple[amaranth.hdl.ir.Elaboratable, str]]
+subfragments: list[tuple[amaranth.hdl._ir.Elaboratable, str]]

@@ -1096,7 +1096,7 @@

Submodules
-__init__(*, name: Optional[str] = None, i: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl.ast.Shape | amaranth.hdl.ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]] = (), o: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl.ast.Shape | amaranth.hdl.ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]] = (), nonexclusive: bool = False, single_caller: bool = False, src_loc: int | tuple[str, int] = 0)
+__init__(*, name: Optional[str] = None, i: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]] = (), o: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]] = (), nonexclusive: bool = False, single_caller: bool = False, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -1126,7 +1126,7 @@

Submodules
-body(m: ~transactron.core.TModule, *, ready: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1), out: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 0'd0), validate_arguments: ~typing.Optional[~collections.abc.Callable[[...], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable]] = None) → Iterator[View[StructLayout]]
+body(m: ~transactron.core.TModule, *, ready: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable = (const 1'd1), out: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable = (const 0'd0), validate_arguments: ~typing.Optional[~collections.abc.Callable[[...], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]] = None) → Iterator[View[StructLayout]]

Define method body

The body context manager can be used to define the actions performed by a Method when it’s run. Each assignment added to @@ -1176,7 +1176,7 @@

Submodules
-debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -1258,7 +1258,7 @@

Submodules
-AvoidedIf(cond: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable)
+AvoidedIf(cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

@@ -1288,7 +1288,7 @@

Submodules
-If(cond: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable)
+If(cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

@@ -1298,7 +1298,7 @@

Submodules
-Switch(test: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable)
+Switch(test: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

@@ -1380,7 +1380,7 @@

Submodules
-body(m: ~transactron.core.TModule, *, request: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1)) → Iterator[Transaction]
+body(m: ~transactron.core.TModule, *, request: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable = (const 1'd1)) → Iterator[Transaction]

Defines the Transaction body.

This context manager allows to conveniently define the actions performed by a Transaction when it’s granted. Each assignment @@ -1404,7 +1404,7 @@

Submodules
-debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -1419,7 +1419,7 @@

Submodules
-__init__(cc_scheduler: ~collections.abc.Callable[[~transactron.core.MethodMap, dict[transactron.core.Transaction, set[transactron.core.Transaction]], set[transactron.core.Transaction], dict[transactron.core.Transaction, int]], ~amaranth.hdl.dsl.Module] = <function eager_deterministic_cc_scheduler>)
+__init__(cc_scheduler: ~collections.abc.Callable[[~transactron.core.MethodMap, dict[transactron.core.Transaction, set[transactron.core.Transaction]], set[transactron.core.Transaction], dict[transactron.core.Transaction, int]], ~amaranth.hdl._dsl.Module] = <function eager_deterministic_cc_scheduler>)

@@ -1429,7 +1429,7 @@

Submodules
-debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -1482,7 +1482,7 @@

Submodules
-transactron.def_method(m: ~transactron.core.TModule, method: ~transactron.core.Method, ready: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1), validate_arguments: ~typing.Optional[~collections.abc.Callable[[...], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable]] = None)
+transactron.def_method(m: ~transactron.core.TModule, method: ~transactron.core.Method, ready: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable = (const 1'd1), validate_arguments: ~typing.Optional[~collections.abc.Callable[[...], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]] = None)

Define a method.

This decorator allows to define transactional methods in an elegant way using Python’s def syntax. Internally, def_method @@ -1550,7 +1550,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/transactron.lib.html b/transactron.lib.html index e1a01353b..c7b8f304c 100644 --- a/transactron.lib.html +++ b/transactron.lib.html @@ -147,7 +147,7 @@

Submodules
-debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -696,7 +696,7 @@

Submodules
-debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

Returns tree-like SignalBundle composed of all metric registers.

@@ -751,7 +751,7 @@

Submodules
-incr(m: ~transactron.core.TModule, *, cond: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable = (const 1'd1))
+incr(m: ~transactron.core.TModule, *, cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable = (const 1'd1))

Increases the value of the counter by 1.

Should be called in the body of either a transaction or a method.

@@ -1380,7 +1380,7 @@

Submodules
-__init__(method1: Method, method2: Method, *, i_fun: Optional[Callable[[TModule, View[StructLayout]], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]] = None, o_fun: Optional[Callable[[TModule, View[StructLayout]], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]] = None, src_loc: int | tuple[str, int] = 0)
+__init__(method1: Method, method2: Method, *, i_fun: Optional[Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]] = None, o_fun: Optional[Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]] = None, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -1426,7 +1426,7 @@

Submodules
-__init__(target: Method, condition: Callable[[TModule, View[StructLayout]], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable], default: Optional[Union[Value, int, Enum, ValueCastable, Mapping[str, RecordDict]]] = None, *, use_condition: bool = False, src_loc: int | tuple[str, int] = 0)
+__init__(target: Method, condition: Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable], default: Optional[Union[Value, int, Enum, ValueCastable, Mapping[str, RecordDict]]] = None, *, use_condition: bool = False, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -1471,7 +1471,7 @@

Submodules
-__init__(target: Method, *, i_transform: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.TModule, 'View[StructLayout]'], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, o_transform: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.TModule, 'View[StructLayout]'], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, src_loc: int | tuple[str, int] = 0)
+__init__(target: Method, *, i_transform: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.TModule, 'View[StructLayout]'], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, o_transform: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.TModule, 'View[StructLayout]'], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -1501,7 +1501,7 @@

SubmodulesElaboratable, Unifier

-__init__(targets: list[transactron.core.Method], combiner: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.TModule, list['View[StructLayout]']], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, *, src_loc: int | tuple[str, int] = 0)
+__init__(targets: list[transactron.core.Method], combiner: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.TModule, list['View[StructLayout]']], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, *, src_loc: int | tuple[str, int] = 0)

Method product.

Takes arbitrary, non-zero number of target methods, and constructs a method which calls all of the target methods using the same @@ -1540,7 +1540,7 @@

SubmodulesElaboratable, Unifier

-__init__(targets: list[transactron.core.Method], combiner: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.TModule, list[tuple[amaranth.hdl.ast.Value, 'View[StructLayout]']]], amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, *, src_loc: int | tuple[str, int] = 0)
+__init__(targets: list[transactron.core.Method], combiner: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.TModule, list[tuple[amaranth.hdl._ast.Value, 'View[StructLayout]']]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, *, src_loc: int | tuple[str, int] = 0)

Method product with optional calling.

Takes arbitrary, non-zero number of target methods, and constructs a method which tries to call all of the target methods using the same @@ -1643,7 +1643,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/transactron.testing.html b/transactron.testing.html index 82bec45ad..02b05f850 100644 --- a/transactron.testing.html +++ b/transactron.testing.html @@ -306,7 +306,7 @@

Submodules
-call_init(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}, /, **kwdata: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, Union[amaranth.hdl.ast.Value, int, enum.Enum, amaranth.hdl.ast.ValueCastable, RecordValueDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
+call_init(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}, /, **kwdata: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, Union[amaranth.hdl._ast.Value, int, enum.Enum, amaranth.hdl._ast.ValueCastable, RecordValueDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]

@@ -321,7 +321,7 @@

Submodules
-debug_signals() → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -399,7 +399,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/transactron.utils.amaranth_ext.html b/transactron.utils.amaranth_ext.html index a48179257..708388943 100644 --- a/transactron.utils.amaranth_ext.html +++ b/transactron.utils.amaranth_ext.html @@ -261,7 +261,7 @@

Submodules
-transactron.utils.amaranth_ext.functions.flatten_signals(signals: amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]) → Iterable[Signal]
+transactron.utils.amaranth_ext.functions.flatten_signals(signals: amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]) → Iterable[Signal]

Flattens input data, which can be either a signal, a record, a list (or a dict) of SignalBundle items.

@@ -293,7 +293,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.

diff --git a/transactron.utils.html b/transactron.utils.html index d1dafddca..20655f8ff 100644 --- a/transactron.utils.html +++ b/transactron.utils.html @@ -133,7 +133,7 @@

Submodules
-transactron.utils.assertion.assert_bits(dependencies: DependencyManager) → list[tuple[amaranth.hdl.ast.Value, tuple[str, int]]]
+transactron.utils.assertion.assert_bits(dependencies: DependencyManager) → list[tuple[amaranth.hdl._ast.Value, tuple[str, int]]]

Gets assertion bits.

This function returns all the assertion signals created by assertion, together with their source locations.

@@ -196,7 +196,7 @@

Submodules
-transactron.utils.assign.assign(lhs: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, AssignArg]], rhs: amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, amaranth.hdl.ast.Value | int | enum.Enum | amaranth.hdl.ast.ValueCastable | collections.abc.Mapping[str, AssignArg]], *, fields: transactron.utils.assign.AssignType | collections.abc.Iterable[str] | collections.abc.Mapping[str, transactron.utils.assign.AssignType | collections.abc.Iterable[str] | collections.abc.Mapping[str, AssignFields]] = AssignType.RHS, lhs_strict=False, rhs_strict=False) → Iterable[Assign]
+transactron.utils.assign.assign(lhs: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg], rhs: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg], *, fields: transactron.utils.assign.AssignType | collections.abc.Iterable[str] | collections.abc.Mapping[str, AssignFields] = AssignType.RHS, lhs_strict=False, rhs_strict=False) → Iterable[Assign]

Safe structured assignment.

This function recursively generates assignment statements for field-containing structures. This includes: Amaranth Records, @@ -312,7 +312,7 @@

Submodules
-transactron.utils.data_repr.data_layout(val: amaranth.hdl.ast.Shape | amaranth.hdl.ast.ShapeCastable | int | range | type[enum.Enum]) → amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]
+transactron.utils.data_repr.data_layout(val: amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum]) → amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]

@@ -396,7 +396,7 @@

Submodules

transactron.utils.debug_signals module

-transactron.utils.debug_signals.auto_debug_signals(thing) → amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl.ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+transactron.utils.debug_signals.auto_debug_signals(thing) → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

Automatic debug signal generation.

Exposes class attributes with debug signals (Amaranth Signals, Records, Arrays and Elaboratables, Methods, classes @@ -712,7 +712,7 @@

Submodules
-transactron.utils.gen.generate_verilog(top_module: Elaboratable, ports: list[amaranth.hdl.ast.Signal], top_name: str = 'top') → tuple[str, transactron.utils.gen.GenerationInfo]
+transactron.utils.gen.generate_verilog(top_module: Elaboratable, ports: list[amaranth.hdl._ast.Signal], top_name: str = 'top') → tuple[str, transactron.utils.gen.GenerationInfo]

@@ -725,12 +725,12 @@

Submodules
-transactron.utils.transactron_helpers.from_method_layout(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl.ast.Shape | amaranth.hdl.ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]]) → StructLayout
+transactron.utils.transactron_helpers.from_method_layout(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]]) → StructLayout

-transactron.utils.transactron_helpers.get_caller_class_name(default: Optional[str] = None) → tuple[Optional[amaranth.hdl.ir.Elaboratable], str]
+transactron.utils.transactron_helpers.get_caller_class_name(default: Optional[str] = None) → tuple[Optional[amaranth.hdl._ir.Elaboratable], str]
@@ -771,7 +771,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:11 2024-03-04. + Last updated on 11:12 2024-03-05.