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index 000000000..c47d24a36
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index 000000000..41b943d00
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index 2f4451c36..bbf2b3b48 100644
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diff --git a/.doctrees/coreblocks.priv.traps.doctree b/.doctrees/coreblocks.priv.traps.doctree
new file mode 100644
index 000000000..f518930e4
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diff --git a/.doctrees/coreblocks.scheduler.doctree b/.doctrees/coreblocks.scheduler.doctree
index 0384e2f10..f0d13ac1e 100644
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diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree
index 46b056d65..b0e6cb0c2 100644
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diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle
index 42aa22c92..12ed0f57b 100644
Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ
diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt
index 344edc761..23126380c 100644
--- a/_sources/auto_graph.rst.txt
+++ b/_sources/auto_graph.rst.txt
@@ -4,12 +4,12 @@
subgraph TransactionModule["TransactionModule"]
subgraph CoreTestElaboratable["elaboratable CoreTestElaboratable"]
subgraph Core["core Core"]
- Core_InitFreeRFFifo["InitFreeRFFifo"]
Core_DiscardBranchVerify["DiscardBranchVerify"]
+ Core_InitFreeRFFifo["InitFreeRFFifo"]
subgraph WishboneMaster["wb_master_instr WishboneMaster"]
WishboneMaster_WishboneMaster["WishboneMaster"]
- WishboneMaster_request["request"]
WishboneMaster_result["result"]
+ WishboneMaster_request["request"]
subgraph Forwarder["result Forwarder"]
Forwarder_write["write"]
Forwarder_read["read"]
@@ -17,30 +17,30 @@
end
subgraph WishboneMaster1["wb_master_data WishboneMaster"]
WishboneMaster1_WishboneMaster["WishboneMaster"]
- WishboneMaster1_result["result"]
WishboneMaster1_request["request"]
+ WishboneMaster1_result["result"]
subgraph Forwarder1["result Forwarder"]
- Forwarder1_write["write"]
Forwarder1_read["read"]
+ Forwarder1_write["write"]
end
end
subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"]
- WishboneMasterAdapter_request_read["request_read"]
WishboneMasterAdapter_get_read_response["get_read_response"]
+ WishboneMasterAdapter_request_read["request_read"]
subgraph Serializer["bus_serializer Serializer"]
Serializer_Serializer["Serializer"]
Serializer_Serializer1["Serializer"]
subgraph BasicFifo["pending_requests BasicFifo"]
- BasicFifo_read["read"]
BasicFifo_write["write"]
+ BasicFifo_read["read"]
end
end
end
subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"]
- WishboneMasterAdapter1_request_write["request_write"]
WishboneMasterAdapter1_request_read["request_read"]
- WishboneMasterAdapter1_get_read_response["get_read_response"]
+ WishboneMasterAdapter1_request_write["request_write"]
WishboneMasterAdapter1_get_write_response["get_write_response"]
+ WishboneMasterAdapter1_get_read_response["get_read_response"]
subgraph Serializer1["bus_serializer Serializer"]
Serializer1_Serializer["Serializer"]
Serializer1_Serializer1["Serializer"]
@@ -75,15 +75,15 @@
SimpleCommonBusCacheRefiller_accept_refill["accept_refill"]
SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"]
subgraph Forwarder2["address_fwd Forwarder"]
- Forwarder2_write["write"]
Forwarder2_read["read"]
+ Forwarder2_write["write"]
end
end
subgraph ICache["icache ICache"]
- ICache_accept_res["accept_res"]
ICache_ICache["ICache"]
- ICache_ICache1["ICache"]
+ ICache_accept_res["accept_res"]
ICache_issue_req["issue_req"]
+ ICache_ICache1["ICache"]
ICache_ICache2["ICache"]
ICache_ICache3["ICache"]
subgraph HwCounter["perf_loads HwCounter"]
@@ -102,23 +102,23 @@
HwCounter4__incr["_incr"]
end
subgraph LatencyMeasurer["req_latency LatencyMeasurer"]
- LatencyMeasurer__start["_start"]
LatencyMeasurer__stop["_stop"]
+ LatencyMeasurer__start["_start"]
subgraph HwExpHistogram["histogram HwExpHistogram"]
HwExpHistogram__add["_add"]
end
subgraph FIFO1["fifo FIFO"]
- FIFO1_read["read"]
FIFO1_write["write"]
+ FIFO1_read["read"]
end
end
subgraph FIFO2["req_fifo FIFO"]
- FIFO2_write["write"]
FIFO2_read["read"]
+ FIFO2_write["write"]
end
subgraph Forwarder3["res_fwd Forwarder"]
- Forwarder3_read["read"]
Forwarder3_write["write"]
+ Forwarder3_read["read"]
end
end
subgraph FRAT["FRAT FRAT"]
@@ -129,17 +129,17 @@
RRAT_peek["peek"]
end
subgraph RegisterFile["RF RegisterFile"]
- RegisterFile_read2["read2"]
RegisterFile_read1["read1"]
RegisterFile_write["write"]
RegisterFile_free["free"]
+ RegisterFile_read2["read2"]
end
subgraph ReorderBuffer["ROB ReorderBuffer"]
+ ReorderBuffer_mark_done["mark_done"]
ReorderBuffer_peek["peek"]
ReorderBuffer_retire["retire"]
ReorderBuffer_get_indices["get_indices"]
ReorderBuffer_put["put"]
- ReorderBuffer_mark_done["mark_done"]
subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"]
LatencyMeasurer1__stop["_stop"]
LatencyMeasurer1__start["_start"]
@@ -147,15 +147,15 @@
HwExpHistogram1__add["_add"]
end
subgraph FIFO3["fifo FIFO"]
- FIFO3_write["write"]
FIFO3_read["read"]
+ FIFO3_write["write"]
end
end
end
subgraph Fetch["fetch Fetch"]
Fetch_Fetch["Fetch"]
- Fetch_resume["resume"]
Fetch_stall_exception["stall_exception"]
+ Fetch_resume["resume"]
Fetch_Fetch1["Fetch"]
subgraph BasicFifo3["fetch_target_queue BasicFifo"]
BasicFifo3_read["read"]
@@ -167,8 +167,8 @@
ExceptionCauseRegister_get["get"]
ExceptionCauseRegister_clear["clear"]
subgraph BasicFifo4["fu_report_fifo BasicFifo"]
- BasicFifo4_read["read"]
BasicFifo4_write["write"]
+ BasicFifo4_read["read"]
end
subgraph ConnectTrans["report_connector ConnectTrans"]
ConnectTrans_ConnectTrans["ConnectTrans"]
@@ -197,24 +197,24 @@
MethodProduct1_method["method"]
end
subgraph RSFuncBlock["rs_block_0 RSFuncBlock"]
- RSFuncBlock_update["update"]
+ RSFuncBlock_get_result["get_result"]
RSFuncBlock_select["select"]
RSFuncBlock_insert["insert"]
- RSFuncBlock_get_result["get_result"]
+ RSFuncBlock_update["update"]
subgraph RS["rs RS"]
RS_RS["RS"]
- RS_update["update"]
- RS_insert["insert"]
- RS_select["select"]
+ RS_take["take"]
RS_RS1["RS"]
RS_RS2["RS"]
+ RS_insert["insert"]
RS_RS3["RS"]
+ RS_update["update"]
RS_RS4["RS"]
- RS_take["take"]
+ RS_select["select"]
end
subgraph AluFuncUnit["func_unit_0 AluFuncUnit"]
- AluFuncUnit_issue["issue"]
AluFuncUnit_accept["accept"]
+ AluFuncUnit_issue["issue"]
subgraph FIFO4["fifo FIFO"]
FIFO4_write["write"]
FIFO4_read["read"]
@@ -224,8 +224,8 @@
WakeupSelect_WakeupSelect["WakeupSelect"]
end
subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"]
- ShiftFuncUnit_issue["issue"]
ShiftFuncUnit_accept["accept"]
+ ShiftFuncUnit_issue["issue"]
subgraph FIFO5["fifo FIFO"]
FIFO5_read["read"]
FIFO5_write["write"]
@@ -235,11 +235,11 @@
WakeupSelect1_WakeupSelect["WakeupSelect"]
end
subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"]
- JumpBranchFuncUnit_issue["issue"]
JumpBranchFuncUnit_accept["accept"]
+ JumpBranchFuncUnit_issue["issue"]
subgraph FIFO6["fifo_branch_resolved FIFO"]
- FIFO6_write["write"]
FIFO6_read["read"]
+ FIFO6_write["write"]
end
subgraph HwCounter5["perf_jumps HwCounter"]
HwCounter5__incr["_incr"]
@@ -262,8 +262,8 @@
ExceptionFuncUnit_accept["accept"]
ExceptionFuncUnit_issue["issue"]
subgraph FIFO8["fifo FIFO"]
- FIFO8_read["read"]
FIFO8_write["write"]
+ FIFO8_read["read"]
end
end
subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"]
@@ -271,11 +271,11 @@
end
subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"]
PrivilegedFuncUnit_accept["accept"]
- PrivilegedFuncUnit_precommit["precommit"]
PrivilegedFuncUnit_issue["issue"]
+ PrivilegedFuncUnit_precommit["precommit"]
subgraph BasicFifo5["fetch_resume_fifo BasicFifo"]
- BasicFifo5_read["read"]
BasicFifo5_write["write"]
+ BasicFifo5_read["read"]
end
end
subgraph WakeupSelect4["wakeup_select_4 WakeupSelect"]
@@ -284,8 +284,8 @@
subgraph Collector1["collector Collector"]
Collector1_method["method"]
subgraph Forwarder5["forwarder Forwarder"]
- Forwarder5_read["read"]
Forwarder5_write["write"]
+ Forwarder5_read["read"]
end
subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"]
subgraph ConnectTrans4["ManyToOneConnectTrans_input_0 ConnectTrans"]
@@ -307,10 +307,10 @@
end
end
subgraph LSUDummy["rs_block_1 LSUDummy"]
- LSUDummy_LSUDummy["LSUDummy"]
- LSUDummy_get_result["get_result"]
LSUDummy_select["select"]
LSUDummy_precommit["precommit"]
+ LSUDummy_get_result["get_result"]
+ LSUDummy_LSUDummy["LSUDummy"]
LSUDummy_LSUDummy1["LSUDummy"]
LSUDummy_LSUDummy2["LSUDummy"]
LSUDummy_insert["insert"]
@@ -321,28 +321,28 @@
end
subgraph LSURequester["requester LSURequester"]
LSURequester_accept_cond0["accept_cond0"]
- LSURequester_issue_cond1["issue_cond1"]
+ LSURequester_issue["issue"]
+ LSURequester_issue_cond0["issue_cond0"]
LSURequester_accept["accept"]
LSURequester_issue_cond2["issue_cond2"]
- LSURequester_issue_cond0["issue_cond0"]
- LSURequester_issue["issue"]
+ LSURequester_issue_cond1["issue_cond1"]
LSURequester_accept_cond1["accept_cond1"]
end
end
subgraph CSRUnit["rs_block_2 CSRUnit"]
CSRUnit_select["select"]
- CSRUnit_CSRUnit["CSRUnit"]
+ CSRUnit_update["update"]
CSRUnit_precommit["precommit"]
CSRUnit_get_result["get_result"]
+ CSRUnit_CSRUnit["CSRUnit"]
CSRUnit_insert["insert"]
CSRUnit_fetch_resume["fetch_resume"]
- CSRUnit_update["update"]
end
subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"]
MethodTryProduct_MethodTryProduct["MethodTryProduct"]
- MethodTryProduct_method["method"]
MethodTryProduct_MethodTryProduct1["MethodTryProduct"]
MethodTryProduct_MethodTryProduct2["MethodTryProduct"]
+ MethodTryProduct_method["method"]
end
subgraph Collector2["FetchResumeKey_unifier Collector"]
Collector2_method["method"]
@@ -365,52 +365,52 @@
end
subgraph InterruptController["interrupt_controller InterruptController"]
InterruptController_entry["entry"]
- InterruptController_report_interrupt["report_interrupt"]
InterruptController_mret["mret"]
+ InterruptController_report_interrupt["report_interrupt"]
end
subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"]
GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"]
subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"]
subgraph CSRRegister["mcause CSRRegister"]
- CSRRegister__fu_write["_fu_write"]
CSRRegister__fu_read["_fu_read"]
+ CSRRegister__fu_write["_fu_write"]
CSRRegister_write["write"]
end
subgraph CSRRegister1["mtvec CSRRegister"]
CSRRegister1__fu_write["_fu_write"]
- CSRRegister1__fu_read["_fu_read"]
CSRRegister1_read["read"]
+ CSRRegister1__fu_read["_fu_read"]
end
subgraph CSRRegister2["mepc CSRRegister"]
- CSRRegister2_read["read"]
CSRRegister2_write["write"]
- CSRRegister2__fu_write["_fu_write"]
CSRRegister2__fu_read["_fu_read"]
+ CSRRegister2_read["read"]
+ CSRRegister2__fu_write["_fu_write"]
end
end
subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"]
DoubleCounterCSR_increment["increment"]
subgraph CSRRegister3["register_low CSRRegister"]
- CSRRegister3_read["read"]
CSRRegister3_write["write"]
CSRRegister3__fu_read["_fu_read"]
+ CSRRegister3_read["read"]
end
subgraph CSRRegister4["register_high CSRRegister"]
- CSRRegister4_write["write"]
CSRRegister4_read["read"]
CSRRegister4__fu_read["_fu_read"]
+ CSRRegister4_write["write"]
end
end
subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"]
DoubleCounterCSR1_increment["increment"]
subgraph CSRRegister5["register_low CSRRegister"]
- CSRRegister5__fu_read["_fu_read"]
CSRRegister5_read["read"]
CSRRegister5_write["write"]
+ CSRRegister5__fu_read["_fu_read"]
end
subgraph CSRRegister6["register_high CSRRegister"]
- CSRRegister6__fu_read["_fu_read"]
CSRRegister6_read["read"]
+ CSRRegister6__fu_read["_fu_read"]
CSRRegister6_write["write"]
end
end
@@ -434,22 +434,22 @@
RegAllocation_RegAllocation["RegAllocation"]
end
subgraph FIFO11["rename_out_buf FIFO"]
- FIFO11_read["read"]
FIFO11_write["write"]
+ FIFO11_read["read"]
end
subgraph Renaming["renaming Renaming"]
Renaming_Renaming["Renaming"]
end
subgraph FIFO12["reg_alloc_out_buf FIFO"]
- FIFO12_write["write"]
FIFO12_read["read"]
+ FIFO12_write["write"]
end
subgraph ROBAllocation["rob_alloc ROBAllocation"]
ROBAllocation_ROBAllocation["ROBAllocation"]
end
subgraph FIFO13["rs_select_out_buf FIFO"]
- FIFO13_read["read"]
FIFO13_write["write"]
+ FIFO13_read["read"]
end
subgraph RSSelection["rs_selector RSSelection"]
RSSelection_RSSelection["RSSelection"]
@@ -469,25 +469,25 @@
ConnectTrans11_ConnectTrans["ConnectTrans"]
end
subgraph Retirement["retirement Retirement"]
+ Retirement_core_state["core_state"]
Retirement_Retirement["Retirement"]
Retirement_Retirement1["Retirement"]
Retirement_Retirement2["Retirement"]
- Retirement_Retirement3["Retirement"]
+ Retirement_Retirement_cond0["Retirement_cond0"]
Retirement_Retirement_cond1["Retirement_cond1"]
+ Retirement_Retirement3["Retirement"]
Retirement_Retirement4["Retirement"]
- Retirement_Retirement_cond0["Retirement_cond0"]
- Retirement_core_state["core_state"]
subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"]
DoubleCounterCSR2_increment["increment"]
subgraph CSRRegister7["register_low CSRRegister"]
- CSRRegister7_read["read"]
CSRRegister7__fu_read["_fu_read"]
CSRRegister7_write["write"]
+ CSRRegister7_read["read"]
end
subgraph CSRRegister8["register_high CSRRegister"]
+ CSRRegister8_read["read"]
CSRRegister8_write["write"]
CSRRegister8__fu_read["_fu_read"]
- CSRRegister8_read["read"]
end
end
subgraph HwCounter9["perf_instr_ret HwCounter"]
@@ -509,59 +509,59 @@
subgraph TransactionManager["transactionManager TransactionManager"]
TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"]
TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"]
+ TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"]
TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"]
- TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"]
- TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"]
+ TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"]
+ TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"]
TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"]
- TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"]
end
end
Core_InitFreeRFFifo --> BasicFifo2_write
Retirement_Retirement1 --> BasicFifo2_write
- TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write
- TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write
+ TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write
+ TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write
FIFO6_read --> Core_DiscardBranchVerify
WishboneMaster_WishboneMaster --> Forwarder_write
WishboneMaster1_WishboneMaster --> Forwarder1_write
Forwarder2_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller
SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read
- SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer
+ SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1
SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write
SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request
- ICache_ICache3 <--> HwCounter4__incr
- ICache_ICache <--> HwCounter3__incr
- ICache_ICache <--> HwCounter2__incr
- ICache_ICache <--> HwCounter1__incr
- ICache_ICache --> Forwarder3_write
+ ICache_ICache <--> HwCounter4__incr
+ ICache_ICache2 <--> HwCounter3__incr
+ ICache_ICache2 <--> HwCounter2__incr
+ ICache_ICache2 <--> HwCounter1__incr
+ ICache_ICache2 --> Forwarder3_write
ICache_ICache1 --> SimpleCommonBusCacheRefiller_start_refill
ICache_ICache1 --> Forwarder2_write
- ICache_ICache2 --> Forwarder2_write
- SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache2
- WishboneMasterAdapter_get_read_response --> ICache_ICache2
- Serializer_Serializer1 --> ICache_ICache2
- BasicFifo_read --> ICache_ICache2
- WishboneMaster_result --> ICache_ICache2
- Forwarder_read --> ICache_ICache2
- Fetch_Fetch1 --> ICache_issue_req
- Fetch_Fetch1 <--> HwCounter__incr
- Fetch_Fetch1 <--> LatencyMeasurer__start
- Fetch_Fetch1 --> FIFO1_write
- Fetch_Fetch1 --> FIFO2_write
- Fetch_Fetch1 --> BasicFifo3_write
- BasicFifo3_read --> Fetch_Fetch
- ICache_accept_res --> Fetch_Fetch
- FIFO2_read --> Fetch_Fetch
- Fetch_Fetch <--> LatencyMeasurer__stop
- FIFO1_read --> Fetch_Fetch
- Fetch_Fetch --> HwExpHistogram__add
- Forwarder3_read --> Fetch_Fetch
- Fetch_Fetch --> MethodProduct_method
+ ICache_ICache3 --> Forwarder2_write
+ SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3
+ WishboneMasterAdapter_get_read_response --> ICache_ICache3
+ Serializer_Serializer --> ICache_ICache3
+ BasicFifo_read --> ICache_ICache3
+ WishboneMaster_result --> ICache_ICache3
+ Forwarder_read --> ICache_ICache3
+ Fetch_Fetch --> ICache_issue_req
+ Fetch_Fetch <--> HwCounter__incr
+ Fetch_Fetch <--> LatencyMeasurer__start
+ Fetch_Fetch --> FIFO1_write
+ Fetch_Fetch --> FIFO2_write
+ Fetch_Fetch --> BasicFifo3_write
+ BasicFifo3_read --> Fetch_Fetch1
+ ICache_accept_res --> Fetch_Fetch1
+ FIFO2_read --> Fetch_Fetch1
+ Fetch_Fetch1 <--> LatencyMeasurer__stop
+ FIFO1_read --> Fetch_Fetch1
+ Fetch_Fetch1 --> HwExpHistogram__add
+ Forwarder3_read --> Fetch_Fetch1
+ Fetch_Fetch1 --> MethodProduct_method
AdapterTrans_AdapterTrans_method --> MethodProduct_method
- Fetch_Fetch --> FIFO_write
+ Fetch_Fetch1 --> FIFO_write
AdapterTrans_AdapterTrans_method --> FIFO_write
- Fetch_Fetch --> MethodMap_method
+ Fetch_Fetch1 --> MethodMap_method
AdapterTrans_AdapterTrans_method --> MethodMap_method
- Fetch_Fetch <--> CoreInstructionCounter_increment
+ Fetch_Fetch1 <--> CoreInstructionCounter_increment
AdapterTrans_AdapterTrans_method <--> CoreInstructionCounter_increment
FIFO_read --> DecodeStage_DecodeStage
DecodeStage_DecodeStage <--> HwCounter8__incr
@@ -572,24 +572,24 @@
FIFO10_read --> Renaming_Renaming
Renaming_Renaming --> FRAT_rename
Retirement_Retirement1 --> FRAT_rename
- TransactionManager_Retirement_cond1_Retirement --> FRAT_rename
+ TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename
Renaming_Renaming --> FIFO11_write
FIFO11_read --> ROBAllocation_ROBAllocation
ROBAllocation_ROBAllocation --> ReorderBuffer_put
ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start
ROBAllocation_ROBAllocation --> FIFO3_write
ROBAllocation_ROBAllocation --> FIFO12_write
- FIFO12_read --> RSSelection_RSSelection
- RSSelection_RSSelection --> Forwarder8_write
- Forwarder8_read --> RSSelection_RSSelection2
+ FIFO12_read --> RSSelection_RSSelection2
+ RSSelection_RSSelection2 --> Forwarder8_write
Forwarder8_read --> RSSelection_RSSelection1
+ Forwarder8_read --> RSSelection_RSSelection
Forwarder8_read --> RSSelection_RSSelection3
- RSFuncBlock_select --> RSSelection_RSSelection2
- RS_select --> RSSelection_RSSelection2
- RSSelection_RSSelection2 --> FIFO13_write
+ RSFuncBlock_select --> RSSelection_RSSelection1
+ RS_select --> RSSelection_RSSelection1
RSSelection_RSSelection1 --> FIFO13_write
+ RSSelection_RSSelection --> FIFO13_write
RSSelection_RSSelection3 --> FIFO13_write
- RSSelection_RSSelection1 <--> LSUDummy_select
+ RSSelection_RSSelection <--> LSUDummy_select
RSSelection_RSSelection3 <--> CSRUnit_select
FIFO13_read --> RSInsertion_RSInsertion
RegisterFile_read1 --> RSInsertion_RSInsertion
@@ -606,7 +606,7 @@
Collector2_method --> ConnectTrans11_ConnectTrans
Forwarder7_read --> ConnectTrans11_ConnectTrans
ConnectTrans11_ConnectTrans --> Fetch_resume
- Retirement_Retirement2 --> Fetch_resume
+ Retirement_Retirement3 --> Fetch_resume
Collector_method --> ResultAnnouncement_ResultAnnouncement
Forwarder4_read --> ResultAnnouncement_ResultAnnouncement
ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done
@@ -616,7 +616,7 @@
ResultAnnouncement_ResultAnnouncement --> RS_update
ResultAnnouncement_ResultAnnouncement --> LSUDummy_update
ResultAnnouncement_ResultAnnouncement --> CSRUnit_update
- RS_RS2 --> WakeupSelect_WakeupSelect
+ RS_RS --> WakeupSelect_WakeupSelect
RS_take --> WakeupSelect_WakeupSelect
RS_take --> WakeupSelect1_WakeupSelect
RS_take --> WakeupSelect2_WakeupSelect
@@ -624,10 +624,10 @@
RS_take --> WakeupSelect4_WakeupSelect
WakeupSelect_WakeupSelect --> AluFuncUnit_issue
WakeupSelect_WakeupSelect --> FIFO4_write
- RS_RS --> WakeupSelect1_WakeupSelect
+ RS_RS4 --> WakeupSelect1_WakeupSelect
WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue
WakeupSelect1_WakeupSelect --> FIFO5_write
- RS_RS4 --> WakeupSelect2_WakeupSelect
+ RS_RS3 --> WakeupSelect2_WakeupSelect
WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue
WakeupSelect2_WakeupSelect <--> HwCounter5__incr
WakeupSelect2_WakeupSelect <--> HwCounter6__incr
@@ -639,7 +639,7 @@
ConnectTrans3_ConnectTrans --> BasicFifo4_write
WakeupSelect2_WakeupSelect --> FIFO7_write
WakeupSelect2_WakeupSelect --> FIFO6_write
- RS_RS3 --> WakeupSelect3_WakeupSelect
+ RS_RS2 --> WakeupSelect3_WakeupSelect
WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue
WakeupSelect3_WakeupSelect --> FIFO8_write
RS_RS1 --> WakeupSelect4_WakeupSelect
@@ -660,12 +660,12 @@
PrivilegedFuncUnit_accept --> ConnectTrans8_ConnectTrans
CSRRegister2_read --> ConnectTrans8_ConnectTrans
ConnectTrans8_ConnectTrans --> BasicFifo5_write
- LSUDummy_LSUDummy2 --> Forwarder6_write
+ LSUDummy_LSUDummy1 --> Forwarder6_write
TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write
TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write
- TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write
TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write
- TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write
+ TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write
+ TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write
CSRRegister__fu_read --> CSRUnit_CSRUnit
CSRUnit_CSRUnit --> CSRRegister__fu_write
CSRRegister1__fu_read --> CSRUnit_CSRUnit
@@ -695,37 +695,37 @@
ConnectTrans10_ConnectTrans --> Forwarder7_write
BasicFifo5_read --> ConnectTrans9_ConnectTrans
CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans
- ReorderBuffer_peek --> Retirement_Retirement4
- ReorderBuffer_peek --> Retirement_Retirement3
+ ReorderBuffer_peek --> Retirement_Retirement2
+ ReorderBuffer_peek --> Retirement_Retirement
ReorderBuffer_peek --> Retirement_Retirement1
- ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement
- ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0
- Retirement_Retirement4 --> MethodTryProduct_method
- ExceptionCauseRegister_get --> Retirement_Retirement3
- ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement
- ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0
+ ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement
+ ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1
+ Retirement_Retirement2 --> MethodTryProduct_method
+ ExceptionCauseRegister_get --> Retirement_Retirement
+ ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement
+ ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1
Retirement_Retirement1 <--> ReorderBuffer_retire
- TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire
- TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire
+ TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire
+ TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire
Retirement_Retirement1 <--> LatencyMeasurer1__stop
- TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop
- TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop
+ TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop
+ TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop
FIFO3_read --> Retirement_Retirement1
- FIFO3_read --> TransactionManager_Retirement_cond1_Retirement
- FIFO3_read --> TransactionManager_Retirement_Retirement_cond0
+ FIFO3_read --> TransactionManager_Retirement_cond0_Retirement
+ FIFO3_read --> TransactionManager_Retirement_Retirement_cond1
Retirement_Retirement1 --> HwExpHistogram1__add
- TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add
- TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add
+ TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add
+ TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add
CoreInstructionCounter_decrement --> Retirement_Retirement1
- CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement
- CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0
+ CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement
+ CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1
RRAT_peek --> Retirement_Retirement1
- RRAT_peek --> TransactionManager_Retirement_cond1_Retirement
+ RRAT_peek --> TransactionManager_Retirement_Retirement_cond1
Retirement_Retirement1 --> RegisterFile_free
- TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free
- TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free
- CSRRegister1_read --> Retirement_Retirement2
- Retirement_Retirement2 <--> ExceptionCauseRegister_clear
+ TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free
+ TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free
+ CSRRegister1_read --> Retirement_Retirement3
+ Retirement_Retirement3 <--> ExceptionCauseRegister_clear
GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment
CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters
GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write
@@ -737,13 +737,29 @@
CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters
GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write
AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt
- TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy
- TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy
+ TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0
+ TransactionManager_Retirement_cond0_Retirement --> RRAT_commit
+ TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment
+ CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement
+ TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write
+ CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement
+ TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write
+ TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr
+ TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement4
+ TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement4
+ TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write
+ TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write
+ TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write
+ TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write
+ TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry
+ TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry
+ TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2
+ TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy2
LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0
LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1
TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0
WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0
- Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond0
+ Serializer1_Serializer2 --> TransactionManager_LSUDummy_accept_cond0
BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0
BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1
WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0
@@ -752,38 +768,22 @@
Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1
TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1
WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1
- Serializer1_Serializer2 --> TransactionManager_LSUDummy_accept_cond1
+ Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond1
+ TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2
+ TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy
+ TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy
+ TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy
+ TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue
+ TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue
+ TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue
TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1
TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read
- TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer1
+ TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3
TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write
- TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write
+ TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write
TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request
- TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request
- TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1
- TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1
- TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1
- TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue
- TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue
- TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue
- TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2
- TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0
- TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write
- TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3
- TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1
- TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement
- TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement
- TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write
- TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write
- TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write
- TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write
- TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry
- TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry
- TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0
- TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit
- TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment
- CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0
- TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write
- CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0
- TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write
- TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr
+ TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request
+ TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0
+ TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write
+ TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1
+ TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1
diff --git a/_sources/coreblocks.backend.rst.txt b/_sources/coreblocks.backend.rst.txt
new file mode 100644
index 000000000..324d524d8
--- /dev/null
+++ b/_sources/coreblocks.backend.rst.txt
@@ -0,0 +1,29 @@
+coreblocks.backend package
+==========================
+
+Submodules
+----------
+
+coreblocks.backend.annoucement module
+-------------------------------------
+
+.. automodule:: coreblocks.backend.annoucement
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.backend.retirement module
+------------------------------------
+
+.. automodule:: coreblocks.backend.retirement
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+Module contents
+---------------
+
+.. automodule:: coreblocks.backend
+ :members:
+ :undoc-members:
+ :show-inheritance:
diff --git a/_sources/coreblocks.core_structs.rst.txt b/_sources/coreblocks.core_structs.rst.txt
new file mode 100644
index 000000000..932cd8e37
--- /dev/null
+++ b/_sources/coreblocks.core_structs.rst.txt
@@ -0,0 +1,37 @@
+coreblocks.core\_structs package
+================================
+
+Submodules
+----------
+
+coreblocks.core\_structs.rat module
+-----------------------------------
+
+.. automodule:: coreblocks.core_structs.rat
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.core\_structs.rf module
+----------------------------------
+
+.. automodule:: coreblocks.core_structs.rf
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.core\_structs.rob module
+-----------------------------------
+
+.. automodule:: coreblocks.core_structs.rob
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+Module contents
+---------------
+
+.. automodule:: coreblocks.core_structs
+ :members:
+ :undoc-members:
+ :show-inheritance:
diff --git a/_sources/coreblocks.frontend.decoder.rst.txt b/_sources/coreblocks.frontend.decoder.rst.txt
new file mode 100644
index 000000000..468b2ce6b
--- /dev/null
+++ b/_sources/coreblocks.frontend.decoder.rst.txt
@@ -0,0 +1,61 @@
+coreblocks.frontend.decoder package
+===================================
+
+Submodules
+----------
+
+coreblocks.frontend.decoder.decode\_stage module
+------------------------------------------------
+
+.. automodule:: coreblocks.frontend.decoder.decode_stage
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.frontend.decoder.instr\_decoder module
+-------------------------------------------------
+
+.. automodule:: coreblocks.frontend.decoder.instr_decoder
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.frontend.decoder.instr\_description module
+-----------------------------------------------------
+
+.. automodule:: coreblocks.frontend.decoder.instr_description
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.frontend.decoder.isa module
+--------------------------------------
+
+.. automodule:: coreblocks.frontend.decoder.isa
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.frontend.decoder.optypes module
+------------------------------------------
+
+.. automodule:: coreblocks.frontend.decoder.optypes
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.frontend.decoder.rvc module
+--------------------------------------
+
+.. automodule:: coreblocks.frontend.decoder.rvc
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+Module contents
+---------------
+
+.. automodule:: coreblocks.frontend.decoder
+ :members:
+ :undoc-members:
+ :show-inheritance:
diff --git a/_sources/coreblocks.frontend.fetch.rst.txt b/_sources/coreblocks.frontend.fetch.rst.txt
new file mode 100644
index 000000000..eb9654663
--- /dev/null
+++ b/_sources/coreblocks.frontend.fetch.rst.txt
@@ -0,0 +1,21 @@
+coreblocks.frontend.fetch package
+=================================
+
+Submodules
+----------
+
+coreblocks.frontend.fetch.fetch module
+--------------------------------------
+
+.. automodule:: coreblocks.frontend.fetch.fetch
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+Module contents
+---------------
+
+.. automodule:: coreblocks.frontend.fetch
+ :members:
+ :undoc-members:
+ :show-inheritance:
diff --git a/_sources/coreblocks.frontend.rst.txt b/_sources/coreblocks.frontend.rst.txt
index ce30b1993..1704adb13 100644
--- a/_sources/coreblocks.frontend.rst.txt
+++ b/_sources/coreblocks.frontend.rst.txt
@@ -1,48 +1,14 @@
coreblocks.frontend package
===========================
-Submodules
-----------
+Subpackages
+-----------
-coreblocks.frontend.decode\_stage module
-----------------------------------------
+.. toctree::
+ :maxdepth: 4
-.. automodule:: coreblocks.frontend.decode_stage
- :members:
- :undoc-members:
- :show-inheritance:
-
-coreblocks.frontend.fetch module
---------------------------------
-
-.. automodule:: coreblocks.frontend.fetch
- :members:
- :undoc-members:
- :show-inheritance:
-
-coreblocks.frontend.instr\_decoder module
------------------------------------------
-
-.. automodule:: coreblocks.frontend.instr_decoder
- :members:
- :undoc-members:
- :show-inheritance:
-
-coreblocks.frontend.instr\_description module
----------------------------------------------
-
-.. automodule:: coreblocks.frontend.instr_description
- :members:
- :undoc-members:
- :show-inheritance:
-
-coreblocks.frontend.rvc module
-------------------------------
-
-.. automodule:: coreblocks.frontend.rvc
- :members:
- :undoc-members:
- :show-inheritance:
+ coreblocks.frontend.decoder
+ coreblocks.frontend.fetch
Module contents
---------------
diff --git a/_sources/coreblocks.func_blocks.fu.rst.txt b/_sources/coreblocks.func_blocks.fu.rst.txt
new file mode 100644
index 000000000..8860dad84
--- /dev/null
+++ b/_sources/coreblocks.func_blocks.fu.rst.txt
@@ -0,0 +1,93 @@
+coreblocks.func\_blocks.fu package
+==================================
+
+Subpackages
+-----------
+
+.. toctree::
+ :maxdepth: 4
+
+ coreblocks.func_blocks.fu.unsigned_multiplication
+
+Submodules
+----------
+
+coreblocks.func\_blocks.fu.alu module
+-------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.alu
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.fu.div\_unit module
+-------------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.div_unit
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.fu.exception module
+-------------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.exception
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.fu.jumpbranch module
+--------------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.jumpbranch
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.fu.mul\_unit module
+-------------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.mul_unit
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.fu.priv module
+--------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.priv
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.fu.shift\_unit module
+---------------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.shift_unit
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.fu.zbc module
+-------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.zbc
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.fu.zbs module
+-------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.zbs
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+Module contents
+---------------
+
+.. automodule:: coreblocks.func_blocks.fu
+ :members:
+ :undoc-members:
+ :show-inheritance:
diff --git a/_sources/coreblocks.func_blocks.fu.unsigned_multiplication.rst.txt b/_sources/coreblocks.func_blocks.fu.unsigned_multiplication.rst.txt
new file mode 100644
index 000000000..750dd4b40
--- /dev/null
+++ b/_sources/coreblocks.func_blocks.fu.unsigned_multiplication.rst.txt
@@ -0,0 +1,45 @@
+coreblocks.func\_blocks.fu.unsigned\_multiplication package
+===========================================================
+
+Submodules
+----------
+
+coreblocks.func\_blocks.fu.unsigned\_multiplication.common module
+-----------------------------------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.unsigned_multiplication.common
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.fu.unsigned\_multiplication.fast\_recursive module
+--------------------------------------------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.unsigned_multiplication.fast_recursive
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.fu.unsigned\_multiplication.sequence module
+-------------------------------------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.unsigned_multiplication.sequence
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.fu.unsigned\_multiplication.shift module
+----------------------------------------------------------------
+
+.. automodule:: coreblocks.func_blocks.fu.unsigned_multiplication.shift
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+Module contents
+---------------
+
+.. automodule:: coreblocks.func_blocks.fu.unsigned_multiplication
+ :members:
+ :undoc-members:
+ :show-inheritance:
diff --git a/_sources/coreblocks.func_blocks.interface.rst.txt b/_sources/coreblocks.func_blocks.interface.rst.txt
new file mode 100644
index 000000000..14eebc46c
--- /dev/null
+++ b/_sources/coreblocks.func_blocks.interface.rst.txt
@@ -0,0 +1,29 @@
+coreblocks.func\_blocks.interface package
+=========================================
+
+Submodules
+----------
+
+coreblocks.func\_blocks.interface.func\_blocks\_unifier module
+--------------------------------------------------------------
+
+.. automodule:: coreblocks.func_blocks.interface.func_blocks_unifier
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.interface.func\_protocols module
+--------------------------------------------------------
+
+.. automodule:: coreblocks.func_blocks.interface.func_protocols
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+Module contents
+---------------
+
+.. automodule:: coreblocks.func_blocks.interface
+ :members:
+ :undoc-members:
+ :show-inheritance:
diff --git a/_sources/coreblocks.func_blocks.lsu.rst.txt b/_sources/coreblocks.func_blocks.lsu.rst.txt
new file mode 100644
index 000000000..3fbe614c7
--- /dev/null
+++ b/_sources/coreblocks.func_blocks.lsu.rst.txt
@@ -0,0 +1,29 @@
+coreblocks.func\_blocks.lsu package
+===================================
+
+Submodules
+----------
+
+coreblocks.func\_blocks.lsu.dummyLsu module
+-------------------------------------------
+
+.. automodule:: coreblocks.func_blocks.lsu.dummyLsu
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.func\_blocks.lsu.pma module
+--------------------------------------
+
+.. automodule:: coreblocks.func_blocks.lsu.pma
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+Module contents
+---------------
+
+.. automodule:: coreblocks.func_blocks.lsu
+ :members:
+ :undoc-members:
+ :show-inheritance:
diff --git a/_sources/coreblocks.func_blocks.rst.txt b/_sources/coreblocks.func_blocks.rst.txt
new file mode 100644
index 000000000..df834c794
--- /dev/null
+++ b/_sources/coreblocks.func_blocks.rst.txt
@@ -0,0 +1,20 @@
+coreblocks.func\_blocks package
+===============================
+
+Subpackages
+-----------
+
+.. toctree::
+ :maxdepth: 4
+
+ coreblocks.func_blocks.fu
+ coreblocks.func_blocks.interface
+ coreblocks.func_blocks.lsu
+
+Module contents
+---------------
+
+.. automodule:: coreblocks.func_blocks
+ :members:
+ :undoc-members:
+ :show-inheritance:
diff --git a/_sources/coreblocks.params.rst.txt b/_sources/coreblocks.params.rst.txt
index 95d079110..ebae7db5a 100644
--- a/_sources/coreblocks.params.rst.txt
+++ b/_sources/coreblocks.params.rst.txt
@@ -44,34 +44,10 @@ coreblocks.params.instr module
:undoc-members:
:show-inheritance:
-coreblocks.params.isa module
-----------------------------
+coreblocks.params.isa\_params module
+------------------------------------
-.. automodule:: coreblocks.params.isa
- :members:
- :undoc-members:
- :show-inheritance:
-
-coreblocks.params.keys module
------------------------------
-
-.. automodule:: coreblocks.params.keys
- :members:
- :undoc-members:
- :show-inheritance:
-
-coreblocks.params.layouts module
---------------------------------
-
-.. automodule:: coreblocks.params.layouts
- :members:
- :undoc-members:
- :show-inheritance:
-
-coreblocks.params.optypes module
---------------------------------
-
-.. automodule:: coreblocks.params.optypes
+.. automodule:: coreblocks.params.isa_params
:members:
:undoc-members:
:show-inheritance:
diff --git a/_sources/coreblocks.priv.csr.rst.txt b/_sources/coreblocks.priv.csr.rst.txt
new file mode 100644
index 000000000..0e8427bb5
--- /dev/null
+++ b/_sources/coreblocks.priv.csr.rst.txt
@@ -0,0 +1,29 @@
+coreblocks.priv.csr package
+===========================
+
+Submodules
+----------
+
+coreblocks.priv.csr.csr\_instances module
+-----------------------------------------
+
+.. automodule:: coreblocks.priv.csr.csr_instances
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.priv.csr.csr\_register module
+----------------------------------------
+
+.. automodule:: coreblocks.priv.csr.csr_register
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+Module contents
+---------------
+
+.. automodule:: coreblocks.priv.csr
+ :members:
+ :undoc-members:
+ :show-inheritance:
diff --git a/_sources/coreblocks.priv.rst.txt b/_sources/coreblocks.priv.rst.txt
new file mode 100644
index 000000000..d5a09f3b7
--- /dev/null
+++ b/_sources/coreblocks.priv.rst.txt
@@ -0,0 +1,19 @@
+coreblocks.priv package
+=======================
+
+Subpackages
+-----------
+
+.. toctree::
+ :maxdepth: 4
+
+ coreblocks.priv.csr
+ coreblocks.priv.traps
+
+Module contents
+---------------
+
+.. automodule:: coreblocks.priv
+ :members:
+ :undoc-members:
+ :show-inheritance:
diff --git a/_sources/coreblocks.priv.traps.rst.txt b/_sources/coreblocks.priv.traps.rst.txt
new file mode 100644
index 000000000..a46153975
--- /dev/null
+++ b/_sources/coreblocks.priv.traps.rst.txt
@@ -0,0 +1,37 @@
+coreblocks.priv.traps package
+=============================
+
+Submodules
+----------
+
+coreblocks.priv.traps.exception module
+--------------------------------------
+
+.. automodule:: coreblocks.priv.traps.exception
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.priv.traps.instr\_counter module
+-------------------------------------------
+
+.. automodule:: coreblocks.priv.traps.instr_counter
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+coreblocks.priv.traps.interrupt\_controller module
+--------------------------------------------------
+
+.. automodule:: coreblocks.priv.traps.interrupt_controller
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+Module contents
+---------------
+
+.. automodule:: coreblocks.priv.traps
+ :members:
+ :undoc-members:
+ :show-inheritance:
diff --git a/_sources/coreblocks.rst.txt b/_sources/coreblocks.rst.txt
index 8af6cf8fc..ba81bdde0 100644
--- a/_sources/coreblocks.rst.txt
+++ b/_sources/coreblocks.rst.txt
@@ -7,16 +7,15 @@ Subpackages
.. toctree::
:maxdepth: 4
+ coreblocks.backend
coreblocks.cache
+ coreblocks.core_structs
coreblocks.frontend
- coreblocks.fu
- coreblocks.lsu
+ coreblocks.func_blocks
coreblocks.params
coreblocks.peripherals
+ coreblocks.priv
coreblocks.scheduler
- coreblocks.stages
- coreblocks.structs_common
- coreblocks.utils
Submodules
----------
diff --git a/api.html b/api.html
index 492e3cddb..2a1f6c1ba 100644
--- a/api.html
+++ b/api.html
@@ -98,6 +98,13 @@
coreblocks.stages package
-
-coreblocks.structs_common package
-
-coreblocks.utils package
-
Submodules
@@ -294,7 +259,7 @@ transactron
|
- - __new__() (coreblocks.fu.div_unit.DivFn.Fn method)
+
- __new__() (coreblocks.frontend.decoder.isa.ExceptionCause method)
- - (coreblocks.fu.mul_unit.MulFn.Fn method)
+
- (coreblocks.frontend.decoder.isa.FenceFm method)
- - (coreblocks.fu.mul_unit.MulType method)
+
- (coreblocks.frontend.decoder.isa.FenceTarget method)
- - (coreblocks.fu.priv.PrivilegedFn.Fn method)
+
- (coreblocks.frontend.decoder.isa.Funct12 method)
- - (coreblocks.fu.zbc.ZbcFn.Fn method)
+
- (coreblocks.frontend.decoder.isa.Funct3 method)
- - (coreblocks.fu.zbs.ZbsFunction.Fn method)
+
- (coreblocks.frontend.decoder.isa.Funct7 method)
- - (coreblocks.params.isa.ExceptionCause method)
+
- (coreblocks.frontend.decoder.isa.Opcode method)
- - (coreblocks.params.isa.Extension method)
+
- (coreblocks.frontend.decoder.isa.Registers method)
- - (coreblocks.params.isa.FenceFm method)
+
- (coreblocks.frontend.decoder.optypes.OpType method)
- - (coreblocks.params.isa.FenceTarget method)
+
- (coreblocks.func_blocks.fu.div_unit.DivFn.Fn method)
- - (coreblocks.params.isa.Funct12 method)
+
- (coreblocks.func_blocks.fu.mul_unit.MulFn.Fn method)
- - (coreblocks.params.isa.Funct3 method)
+
- (coreblocks.func_blocks.fu.mul_unit.MulType method)
- - (coreblocks.params.isa.Funct7 method)
+
- (coreblocks.func_blocks.fu.priv.PrivilegedFn.Fn method)
- - (coreblocks.params.isa.Opcode method)
+
- (coreblocks.func_blocks.fu.zbc.ZbcFn.Fn method)
- - (coreblocks.params.isa.Registers method)
+
- (coreblocks.func_blocks.fu.zbs.ZbsFunction.Fn method)
- - (coreblocks.params.optypes.OpType method)
+
- (coreblocks.params.isa_params.Extension method)
- - (coreblocks.structs_common.csr.PrivilegeLevel method)
+
- (coreblocks.priv.csr.csr_instances.CSRAddress method)
- - (coreblocks.structs_common.csr_generic.CSRAddress method)
+
- (coreblocks.priv.csr.csr_register.PrivilegeLevel method)
- (transactron.graph.Direction method)
@@ -515,31 +457,29 @@ _
A
|
- - ADDRESS_GENERATION (coreblocks.params.optypes.OpType attribute)
-
- adr (coreblocks.peripherals.wishbone.WishboneInterface attribute)
- align_down_to_power_of_two() (in module transactron.utils.data_repr)
@@ -593,29 +531,29 @@
A
- allow_partial_extensions (coreblocks.params.configurations.CoreConfiguration attribute)
- - ALUComponent (class in coreblocks.fu.alu)
+
- ALUComponent (class in coreblocks.func_blocks.fu.alu)
- - AluFuncUnit (class in coreblocks.fu.alu)
+
- AluFuncUnit (class in coreblocks.func_blocks.fu.alu)
- analyze_methods() (transactron.profiler.Profile method)
- analyze_transactions() (transactron.profiler.Profile method)
- - AND (coreblocks.params.isa.Funct3 attribute)
+
- AND (coreblocks.frontend.decoder.isa.Funct3 attribute)
- - ANDN (coreblocks.params.isa.Funct3 attribute)
+
- ANDN (coreblocks.frontend.decoder.isa.Funct3 attribute)
- ArgumentsToResultsZipper (class in transactron.lib.reqres)
- - ARITHMETIC (coreblocks.params.optypes.OpType attribute)
+
- ARITHMETIC (coreblocks.frontend.decoder.optypes.OpType attribute)
- assertion() (transactron.lib.logging.HardwareLogger method)
@@ -623,12 +561,10 @@ A
- AssignType (class in transactron.utils.assign)
- - AsyncInterruptInsertSignalKey (class in coreblocks.params.keys)
-
- - AUIPC (coreblocks.params.isa.Opcode attribute)
+
- AUIPC (coreblocks.frontend.decoder.isa.Opcode attribute)
- auto_debug_signals() (in module transactron.utils.debug_signals)
@@ -655,61 +591,61 @@
A
B
|
- - BRANCH (coreblocks.params.isa.Opcode attribute)
+
- BRANCH (coreblocks.frontend.decoder.isa.Opcode attribute)
- - BranchVerifyKey (class in coreblocks.params.keys)
+
- BREAKPOINT (coreblocks.frontend.decoder.isa.ExceptionCause attribute)
- - BREAKPOINT (coreblocks.params.isa.ExceptionCause attribute)
-
- - BSET (coreblocks.fu.zbs.ZbsFunction.Fn attribute)
+
- BSET (coreblocks.frontend.decoder.isa.Funct3 attribute)
- BTypeInstr (class in coreblocks.params.instr)
- - BU (coreblocks.params.isa.Funct3 attribute)
+
- BU (coreblocks.frontend.decoder.isa.Funct3 attribute)
- bus (coreblocks.peripherals.wishbone.WishboneMemorySlave attribute)
@@ -749,7 +683,7 @@ B
C
- COMMON (transactron.utils.assign.AssignType attribute)
- - CommonBusDataKey (class in coreblocks.params.keys)
-
- - CommonLayoutFields (class in coreblocks.params.layouts)
-
- - COMPARE (coreblocks.params.optypes.OpType attribute)
+
- COMPARE (coreblocks.frontend.decoder.optypes.OpType attribute)
- compressed (coreblocks.params.configurations.CoreConfiguration attribute)
@@ -858,6 +786,27 @@ C
+ -
+ coreblocks.backend
+
+
+ -
+ coreblocks.backend.annoucement
+
+
+ -
+ coreblocks.backend.retirement
+
+
-
@@ -896,471 +845,456 @@
C
-
- coreblocks.frontend
+ coreblocks.core_structs
-
- coreblocks.frontend.decode_stage
+ coreblocks.core_structs.rat
-
- coreblocks.frontend.fetch
+ coreblocks.core_structs.rf
-
- coreblocks.frontend.instr_decoder
+ coreblocks.core_structs.rob
-
- coreblocks.frontend.instr_description
-
-
- -
- coreblocks.frontend.rvc
+ coreblocks.frontend
-
- coreblocks.fu
+ coreblocks.frontend.decoder
-
- coreblocks.fu.alu
+ coreblocks.frontend.decoder.decode_stage
-
- coreblocks.fu.div_unit
+ coreblocks.frontend.decoder.instr_decoder
-
- coreblocks.fu.exception
+ coreblocks.frontend.decoder.instr_description
-
- coreblocks.fu.fu_decoder
+ coreblocks.frontend.decoder.isa
-
- coreblocks.fu.jumpbranch
+ coreblocks.frontend.decoder.optypes
-
- coreblocks.fu.mul_unit
+ coreblocks.frontend.decoder.rvc
-
- coreblocks.fu.priv
+ coreblocks.frontend.fetch
-
- coreblocks.fu.shift_unit
+ coreblocks.frontend.fetch.fetch
-
- coreblocks.fu.unsigned_multiplication
+ coreblocks.func_blocks
-
- coreblocks.fu.unsigned_multiplication.common
+ coreblocks.func_blocks.fu
-
- coreblocks.fu.unsigned_multiplication.fast_recursive
+ coreblocks.func_blocks.fu.alu
-
- coreblocks.fu.unsigned_multiplication.sequence
+ coreblocks.func_blocks.fu.div_unit
-
- coreblocks.fu.unsigned_multiplication.shift
+ coreblocks.func_blocks.fu.exception
-
- coreblocks.fu.zbc
+ coreblocks.func_blocks.fu.jumpbranch
-
- coreblocks.fu.zbs
+ coreblocks.func_blocks.fu.mul_unit
+ |
+
-
- coreblocks.lsu
+ coreblocks.func_blocks.fu.priv
-
- coreblocks.lsu.dummyLsu
+ coreblocks.func_blocks.fu.shift_unit
- |
-
- - CTZ (coreblocks.params.isa.Funct12 attribute)
+
- CTZ (coreblocks.frontend.decoder.isa.Funct12 attribute)
- cyc (coreblocks.peripherals.wishbone.WishboneInterface attribute)
- - CYCLE (coreblocks.structs_common.csr_generic.CSRAddress attribute)
+
- CYCLE (coreblocks.priv.csr.csr_instances.CSRAddress attribute)
- - CYCLEH (coreblocks.structs_common.csr_generic.CSRAddress attribute)
+
- CYCLEH (coreblocks.priv.csr.csr_instances.CSRAddress attribute)
- cycles (transactron.profiler.Profile attribute)
@@ -1390,17 +1324,15 @@ C
D
- defined (transactron.core.transaction_base.TransactionBase attribute)
- |
- |
+
- deserialize_addr() (coreblocks.cache.icache.ICache method)
- - DEV_I (coreblocks.params.isa.FenceTarget attribute)
+
- DEV_I (coreblocks.frontend.decoder.isa.FenceTarget attribute)
- - DEV_O (coreblocks.params.isa.FenceTarget attribute)
+
- DEV_O (coreblocks.frontend.decoder.isa.FenceTarget attribute)
- Direction (class in transactron.graph)
- disable() (transactron.testing.testbenchio.TestbenchIO method)
- - DIV (coreblocks.fu.div_unit.DivFn.Fn attribute)
+
- DIV (coreblocks.frontend.decoder.isa.Funct3 attribute)
- - div_fn (coreblocks.fu.div_unit.DivComponent attribute)
+
- div_fn (coreblocks.func_blocks.fu.div_unit.DivComponent attribute)
- - DIV_REM (coreblocks.params.optypes.OpType attribute)
+
- DIV_REM (coreblocks.frontend.decoder.optypes.OpType attribute)
- - DivComponent (class in coreblocks.fu.div_unit)
+
- DivComponent (class in coreblocks.func_blocks.fu.div_unit)
- - DivFn (class in coreblocks.fu.div_unit)
+
- DivFn (class in coreblocks.func_blocks.fu.div_unit)
- - DivFn.Fn (class in coreblocks.fu.div_unit)
+
- DivFn.Fn (class in coreblocks.func_blocks.fu.div_unit)
- - DIVU (coreblocks.fu.div_unit.DivFn.Fn attribute)
+
- DIVU (coreblocks.frontend.decoder.isa.Funct3 attribute)
- - DivUnit (class in coreblocks.fu.div_unit)
+
- DivUnit (class in coreblocks.func_blocks.fu.div_unit)
- - DIVUW (coreblocks.params.isa.Funct3 attribute)
+
- DIVUW (coreblocks.frontend.decoder.isa.Funct3 attribute)
- - DIVW (coreblocks.params.isa.Funct3 attribute)
-
- - done (coreblocks.params.layouts.ROBLayouts attribute)
+
- DIVW (coreblocks.frontend.decoder.isa.Funct3 attribute)
- done() (transactron.testing.testbenchio.TestbenchIO method)
- - DoubleCounterCSR (class in coreblocks.structs_common.csr_generic)
+
- DoubleCounterCSR (class in coreblocks.priv.csr.csr_instances)
- - dsp_width (coreblocks.fu.mul_unit.MulComponent attribute)
+
- dsp_width (coreblocks.func_blocks.fu.mul_unit.MulComponent attribute)
- - DSPMulUnit (class in coreblocks.fu.unsigned_multiplication.common)
+
- DSPMulUnit (class in coreblocks.func_blocks.fu.unsigned_multiplication.common)
- dump() (transactron.graph.OwnershipGraph method)
@@ -1556,22 +1480,22 @@ D
E
@@ -1652,29 +1558,25 @@ E
F
@@ -1784,7 +1670,7 @@ F
G
- get_caller_class_name() (in module transactron.utils.transactron_helpers)
-
- - get_decoder() (coreblocks.fu.fu_decoder.DecoderManager method)
- get_dependency() (transactron.lib.dependencies.DependencyManager method)
@@ -1822,96 +1704,82 @@
G
- (transactron.utils.dependencies.DependencyManager method)
- - get_extra_method() (coreblocks.stages.func_blocks_unifier.FuncBlocksUnifier method)
-
- - get_function() (coreblocks.fu.fu_decoder.DecoderManager method)
+
- get_extra_method() (coreblocks.func_blocks.interface.func_blocks_unifier.FuncBlocksUnifier method)
- get_hier_name() (transactron.graph.OwnershipGraph method)
- - get_input() (in module coreblocks.fu.div_unit)
+
- get_input() (in module coreblocks.func_blocks.fu.div_unit)
- - get_instructions() (coreblocks.fu.div_unit.DivFn method)
+
- get_instructions() (coreblocks.func_blocks.fu.div_unit.DivFn method)
- get_log_records() (in module transactron.lib.logging)
- get_metrics() (transactron.lib.metrics.HardwareMetricsManager method)
- - get_module() (coreblocks.fu.alu.ALUComponent method)
+
- get_module() (coreblocks.func_blocks.fu.alu.ALUComponent method)
|
- get_name() (transactron.graph.OwnershipGraph method)
- - get_op_types() (coreblocks.fu.fu_decoder.DecoderManager method)
-
- - get_optypes() (coreblocks.fu.alu.ALUComponent method)
+
- get_optypes() (coreblocks.func_blocks.fu.alu.ALUComponent method)
- get_outputs() (in module transactron.testing.functions)
@@ -1924,16 +1792,12 @@
G
- get_register_value() (transactron.lib.metrics.HardwareMetricsManager method)
- - get_result (coreblocks.utils.protocols.FuncBlock attribute)
+
- get_result (coreblocks.func_blocks.interface.func_protocols.FuncBlock attribute)
- - get_rs_entry_count() (coreblocks.lsu.dummyLsu.LSUBlockComponent method)
+
- get_rs_entry_count() (coreblocks.func_blocks.lsu.dummyLsu.LSUBlockComponent method)
- get_src_loc() (in module transactron.utils.transactron_helpers)
@@ -1942,7 +1806,7 @@
G
- get_write_response (coreblocks.peripherals.bus_adapter.BusMasterInterface attribute)
- - GP (coreblocks.params.isa.Registers attribute)
+
- GP (coreblocks.frontend.decoder.isa.Registers attribute)
- grant (transactron.profiler.TransactionSamples attribute)
@@ -1954,13 +1818,13 @@ G
H
|
@@ -1978,10 +1842,10 @@ H
I
- - I (coreblocks.params.isa.Extension attribute)
+
- I (coreblocks.frontend.decoder.isa.InstrType attribute)
- ICache (class in coreblocks.cache.icache)
@@ -1995,8 +1859,6 @@
I
- icache_ways (coreblocks.params.configurations.CoreConfiguration attribute)
- ICacheBypass (class in coreblocks.cache.icache)
-
- - ICacheLayouts (class in coreblocks.params.layouts)
- ICacheParameters (class in coreblocks.params.icache_params)
@@ -2004,11 +1866,9 @@ I
- If() (transactron.core.tmodule.TModule method)
- - ILLEGAL_INSTRUCTION (coreblocks.params.isa.ExceptionCause attribute)
+
- ILLEGAL_INSTRUCTION (coreblocks.frontend.decoder.isa.ExceptionCause attribute)
- IllegalInstr (class in coreblocks.params.instr)
-
- - imm (coreblocks.params.layouts.CommonLayoutFields attribute)
- IN (transactron.graph.Direction attribute)
@@ -2020,7 +1880,7 @@ I
- INOUT (transactron.graph.Direction attribute)
- - insert (coreblocks.utils.protocols.FuncBlock attribute)
+
- insert (coreblocks.func_blocks.interface.func_protocols.FuncBlock attribute)
- insert_edge() (transactron.graph.OwnershipGraph method)
@@ -2028,47 +1888,43 @@ I
- insert_node() (transactron.graph.OwnershipGraph method)
- - instr (coreblocks.params.layouts.CommonLayoutFields attribute)
-
- - instr_mux() (coreblocks.frontend.rvc.InstrDecompress method)
-
- - instr_type_override (coreblocks.frontend.instr_description.Encoding attribute)
+
- instr_mux() (coreblocks.frontend.decoder.rvc.InstrDecompress method)
- - InstrDecoder (class in coreblocks.frontend.instr_decoder)
+
- instr_type_override (coreblocks.frontend.decoder.instr_description.Encoding attribute)
- - InstrDecompress (class in coreblocks.frontend.rvc)
+
- InstrDecoder (class in coreblocks.frontend.decoder.instr_decoder)
- - INSTRET (coreblocks.structs_common.csr_generic.CSRAddress attribute)
+
- InstrDecompress (class in coreblocks.frontend.decoder.rvc)
- - INSTRETH (coreblocks.structs_common.csr_generic.CSRAddress attribute)
+
- INSTRET (coreblocks.priv.csr.csr_instances.CSRAddress attribute)
- - InstrType (class in coreblocks.params.isa)
+
- INSTRETH (coreblocks.priv.csr.csr_instances.CSRAddress attribute)
- - INSTRUCTION_ACCESS_FAULT (coreblocks.params.isa.ExceptionCause attribute)
+
- InstrType (class in coreblocks.frontend.decoder.isa)
- - INSTRUCTION_ADDRESS_MISALIGNED (coreblocks.params.isa.ExceptionCause attribute)
+
- INSTRUCTION_ACCESS_FAULT (coreblocks.frontend.decoder.isa.ExceptionCause attribute)
- - INSTRUCTION_PAGE_FAULT (coreblocks.params.isa.ExceptionCause attribute)
+
- INSTRUCTION_ADDRESS_MISALIGNED (coreblocks.frontend.decoder.isa.ExceptionCause attribute)
- - InstructionPrecommitKey (class in coreblocks.params.keys)
+
- INSTRUCTION_PAGE_FAULT (coreblocks.frontend.decoder.isa.ExceptionCause attribute)
- int_to_signed() (in module transactron.utils.data_repr)
- - InterruptController (class in coreblocks.structs_common.interrupt_controller)
+
- InterruptController (class in coreblocks.priv.traps.interrupt_controller)
- - ipc (coreblocks.fu.div_unit.DivComponent attribute)
+
- ipc (coreblocks.func_blocks.fu.div_unit.DivComponent attribute)
- - is_instr_compressed() (in module coreblocks.frontend.rvc)
+
- is_instr_compressed() (in module coreblocks.frontend.decoder.rvc)
- is_transaction (transactron.profiler.ProfileInfo attribute)
- - ISA (class in coreblocks.params.isa)
+
- ISA (class in coreblocks.params.isa_params)
- - issue (coreblocks.utils.protocols.FuncUnit attribute)
+
- issue (coreblocks.func_blocks.interface.func_protocols.FuncUnit attribute)
- issue_req (coreblocks.cache.iface.CacheInterface attribute)
- - iterative_module() (coreblocks.fu.zbc.ClMultiplier method)
+
- iterative_module() (coreblocks.func_blocks.fu.zbc.ClMultiplier method)
- ITypeInstr (class in coreblocks.params.instr)
@@ -2078,35 +1934,33 @@ I
J
@@ -2114,7 +1968,7 @@ J
L
@@ -2194,11 +2046,11 @@ L
M
@@ -2599,7 +2453,7 @@ M
N
- - N (coreblocks.params.isa.Extension attribute)
+
- N (coreblocks.params.isa_params.Extension attribute)
- name (transactron.core.transaction_base.TransactionBase attribute)
@@ -2619,7 +2473,7 @@
N
- next (transactron.core.tmodule.TModule property)
- - NONE (coreblocks.params.isa.FenceFm attribute)
+
- NONE (coreblocks.frontend.decoder.isa.FenceFm attribute)
- (transactron.graph.Direction attribute)
@@ -2633,54 +2487,50 @@
N
O
|
- - optypes_supported() (in module coreblocks.params.fu_params)
-
- - OR (coreblocks.params.isa.Funct3 attribute)
+
- OR (coreblocks.frontend.decoder.isa.Funct3 attribute)
- - ORCB (coreblocks.params.isa.Funct12 attribute)
+
- ORCB (coreblocks.frontend.decoder.isa.Funct12 attribute)
- - ORN (coreblocks.params.isa.Funct3 attribute)
+
- ORN (coreblocks.frontend.decoder.isa.Funct3 attribute)
- OUT (transactron.graph.Direction attribute)
@@ -2699,7 +2549,7 @@
O
P
|
- |
+
- prepare() (transactron.tracing.TracingFragment method)
- print_info() (transactron.core.manager.TransactionManager method)
- Priority (class in transactron.core.transaction_base)
- - PRIV (coreblocks.params.isa.Funct3 attribute)
+
- PRIV (coreblocks.frontend.decoder.isa.Funct3 attribute)
- - PrivilegedFn (class in coreblocks.fu.priv)
+
- PrivilegedFn (class in coreblocks.func_blocks.fu.priv)
- - PrivilegedFn.Fn (class in coreblocks.fu.priv)
+
- PrivilegedFn.Fn (class in coreblocks.func_blocks.fu.priv)
- - PrivilegedFuncUnit (class in coreblocks.fu.priv)
+
- PrivilegedFuncUnit (class in coreblocks.func_blocks.fu.priv)
- - PrivilegedUnitComponent (class in coreblocks.fu.priv)
+
- PrivilegedUnitComponent (class in coreblocks.func_blocks.fu.priv)
- - PrivilegeLevel (class in coreblocks.structs_common.csr)
+
- PrivilegeLevel (class in coreblocks.priv.csr.csr_register)
- Profile (class in transactron.profiler)
@@ -2783,7 +2631,7 @@ P
Q
@@ -2791,39 +2639,31 @@ Q
R
@@ -2983,37 +2773,33 @@ R
S
@@ -3247,21 +3025,21 @@ S
T
@@ -3680,45 +3458,37 @@ T
U
|
- - unifier (coreblocks.params.keys.FetchResumeKey attribute)
-
-
- UnifierKey (class in transactron.lib.dependencies)
- - UNKNOWN (coreblocks.params.optypes.OpType attribute)
-
- - UnsignedMulUnitLayouts (class in coreblocks.params.layouts)
+
- UNKNOWN (coreblocks.frontend.decoder.optypes.OpType attribute)
- - update (coreblocks.utils.protocols.FuncBlock attribute)
+
- update (coreblocks.func_blocks.interface.func_protocols.FuncBlock attribute)
- use() (transactron.lib.transformers.Transformer method)
- - USER (coreblocks.structs_common.csr.PrivilegeLevel attribute)
+
- USER (coreblocks.priv.csr.csr_register.PrivilegeLevel attribute)
- UTypeInstr (class in coreblocks.params.instr)
@@ -3728,14 +3498,10 @@ U
V
|
|
@@ -3744,7 +3510,7 @@ V
W
- - W (coreblocks.params.isa.Funct3 attribute)
+
- W (coreblocks.frontend.decoder.isa.Funct3 attribute)
- wait_until_done() (transactron.testing.testbenchio.TestbenchIO method)
@@ -3758,10 +3524,10 @@ W
- we (coreblocks.peripherals.wishbone.WishboneInterface attribute)
- - WFI (coreblocks.params.isa.Funct12 attribute)
+
- WFI (coreblocks.frontend.decoder.isa.Funct12 attribute)
- width (transactron.lib.metrics.MetricRegisterModel attribute)
@@ -3800,88 +3566,88 @@
W
X
|
|
@@ -3890,73 +3656,73 @@ X
Z
@@ -3971,7 +3737,7 @@ Z
© Copyright Kuźnia Rdzeni, 2024.
- Last updated on 13:17 2024-03-17.
+ Last updated on 14:58 2024-03-21.
diff --git a/home.html b/home.html
index 37c6098b6..5d846c2a2 100644
--- a/home.html
+++ b/home.html
@@ -129,7 +129,7 @@ Documentation
+
+ |
+
+ coreblocks.backend |
+ |
+
+ |
+
+ coreblocks.backend.annoucement |
+ |
+
+ |
+
+ coreblocks.backend.retirement |
+ |
|
@@ -126,297 +141,292 @@ Python Module Index
|
|
- coreblocks.frontend |
- |
-
- |
-
- coreblocks.frontend.decode_stage |
+ coreblocks.core_structs |
|
|
- coreblocks.frontend.fetch |
+ coreblocks.core_structs.rat |
|
|
- coreblocks.frontend.instr_decoder |
+ coreblocks.core_structs.rf |
|
|
- coreblocks.frontend.instr_description |
+ coreblocks.core_structs.rob |
|
|
- coreblocks.frontend.rvc |
+ coreblocks.frontend |
|
|
- coreblocks.fu |
+ coreblocks.frontend.decoder |
|
|
- coreblocks.fu.alu |
+ coreblocks.frontend.decoder.decode_stage |
|
|
- coreblocks.fu.div_unit |
+ coreblocks.frontend.decoder.instr_decoder |
|
|
- coreblocks.fu.exception |
+ coreblocks.frontend.decoder.instr_description |
|
|
- coreblocks.fu.fu_decoder |
+ coreblocks.frontend.decoder.isa |
|
|
- coreblocks.fu.jumpbranch |
+ coreblocks.frontend.decoder.optypes |
|
|
- coreblocks.fu.mul_unit |
+ coreblocks.frontend.decoder.rvc |
|
|
- coreblocks.fu.priv |
+ coreblocks.frontend.fetch |
|
|
- coreblocks.fu.shift_unit |
+ coreblocks.frontend.fetch.fetch |
|
|
- coreblocks.fu.unsigned_multiplication |
+ coreblocks.func_blocks |
|
|
- coreblocks.fu.unsigned_multiplication.common |
+ coreblocks.func_blocks.fu |
|
|
- coreblocks.fu.unsigned_multiplication.fast_recursive |
+ coreblocks.func_blocks.fu.alu |
|
|
- coreblocks.fu.unsigned_multiplication.sequence |
+ coreblocks.func_blocks.fu.div_unit |
|
|
- coreblocks.fu.unsigned_multiplication.shift |
+ coreblocks.func_blocks.fu.exception |
|
|
- coreblocks.fu.zbc |
+ coreblocks.func_blocks.fu.jumpbranch |
|
|
- coreblocks.fu.zbs |
+ coreblocks.func_blocks.fu.mul_unit |
|
|
- coreblocks.lsu |
+ coreblocks.func_blocks.fu.priv |
|
|
- coreblocks.lsu.dummyLsu |
+ coreblocks.func_blocks.fu.shift_unit |
|
|
- coreblocks.lsu.pma |
+ coreblocks.func_blocks.fu.unsigned_multiplication |
|
|
- coreblocks.params |
+ coreblocks.func_blocks.fu.unsigned_multiplication.common |
|
|
- coreblocks.params.configurations |
+ coreblocks.func_blocks.fu.unsigned_multiplication.fast_recursive |
|
|
- coreblocks.params.fu_params |
+ coreblocks.func_blocks.fu.unsigned_multiplication.sequence |
|
|
- coreblocks.params.genparams |
+ coreblocks.func_blocks.fu.unsigned_multiplication.shift |
|
|
- coreblocks.params.icache_params |
+ coreblocks.func_blocks.fu.zbc |
|
|
- coreblocks.params.instr |
+ coreblocks.func_blocks.fu.zbs |
|
|
- coreblocks.params.isa |
+ coreblocks.func_blocks.interface |
|
|
- coreblocks.params.keys |
+ coreblocks.func_blocks.interface.func_blocks_unifier |
|
|
- coreblocks.params.layouts |
+ coreblocks.func_blocks.interface.func_protocols |
|
|
- coreblocks.params.optypes |
+ coreblocks.func_blocks.lsu |
|
|
- coreblocks.peripherals |
+ coreblocks.func_blocks.lsu.dummyLsu |
|
|
- coreblocks.peripherals.axi_lite |
+ coreblocks.func_blocks.lsu.pma |
|
|
- coreblocks.peripherals.bus_adapter |
+ coreblocks.params |
|
|
- coreblocks.peripherals.wishbone |
+ coreblocks.params.configurations |
|
|
- coreblocks.scheduler |
+ coreblocks.params.fu_params |
|
|
- coreblocks.scheduler.scheduler |
+ coreblocks.params.genparams |
|
|
- coreblocks.scheduler.wakeup_select |
+ coreblocks.params.icache_params |
|
|
- coreblocks.stages |
+ coreblocks.params.instr |
|
|
- coreblocks.stages.backend |
+ coreblocks.params.isa_params |
|
|
- coreblocks.stages.func_blocks_unifier |
+ coreblocks.peripherals |
|
|
- coreblocks.stages.retirement |
+ coreblocks.peripherals.axi_lite |
|
|
- coreblocks.stages.rs_func_block |
+ coreblocks.peripherals.bus_adapter |
|
|
- coreblocks.structs_common |
+ coreblocks.peripherals.wishbone |
|
|
- coreblocks.structs_common.csr |
+ coreblocks.priv |
|
|
- coreblocks.structs_common.csr_generic |
+ coreblocks.priv.csr |
|
|
- coreblocks.structs_common.exception |
+ coreblocks.priv.csr.csr_instances |
|
|
- coreblocks.structs_common.instr_counter |
+ coreblocks.priv.csr.csr_register |
|
|
- coreblocks.structs_common.interrupt_controller |
+ coreblocks.priv.traps |
|
|
- coreblocks.structs_common.rat |
+ coreblocks.priv.traps.exception |
|
|
- coreblocks.structs_common.rf |
+ coreblocks.priv.traps.instr_counter |
|
|
- coreblocks.structs_common.rob |
+ coreblocks.priv.traps.interrupt_controller |
|
|
- coreblocks.structs_common.rs |
+ coreblocks.scheduler |
|
|
- coreblocks.utils |
+ coreblocks.scheduler.scheduler |
|
|
- coreblocks.utils.protocols |
+ coreblocks.scheduler.wakeup_select |
|
| | |
|
@@ -658,7 +668,7 @@ Python Module Index
© Copyright Kuźnia Rdzeni, 2024.
- Last updated on 13:17 2024-03-17.
+ Last updated on 14:58 2024-03-21.
diff --git a/scheduler/overview.html b/scheduler/overview.html
index 30cb9329d..f7a06ff02 100644
--- a/scheduler/overview.html
+++ b/scheduler/overview.html
@@ -146,7 +146,7 @@ More detailed description of each block |
|
|
|
|
|
| |
|
|
|
|
|
|
|