From baf8db4b5904dde6903899c8ad090bdb5673196f Mon Sep 17 00:00:00 2001 From: tilk Date: Wed, 6 Mar 2024 17:29:27 +0000 Subject: [PATCH] Fix the pysim regression. (#604) --- .doctrees/api.doctree | Bin 21036 -> 21036 bytes .doctrees/auto_graph.doctree | Bin 44182 -> 44189 bytes .doctrees/current-graph.doctree | Bin 45403 -> 45410 bytes .doctrees/environment.pickle | Bin 440258 -> 440258 bytes _sources/auto_graph.rst.txt | 316 ++++++++++---------- api.html | 2 +- assumptions.html | 2 +- auto_graph.html | 318 ++++++++++----------- components/icache.html | 2 +- coreblocks.cache.html | 2 +- coreblocks.frontend.html | 2 +- coreblocks.fu.html | 2 +- coreblocks.fu.unsigned_multiplication.html | 2 +- coreblocks.html | 2 +- coreblocks.lsu.html | 2 +- coreblocks.params.html | 2 +- coreblocks.peripherals.html | 2 +- coreblocks.scheduler.html | 2 +- coreblocks.stages.html | 2 +- coreblocks.structs_common.html | 2 +- coreblocks.utils.html | 2 +- current-graph.html | 318 ++++++++++----------- development-environment.html | 2 +- genindex.html | 2 +- home.html | 2 +- index.html | 2 +- miscellany/exceptions-summary.html | 2 +- modules-coreblocks.html | 2 +- modules-transactron.html | 2 +- problem-checklist.html | 2 +- py-modindex.html | 2 +- scheduler/overview.html | 2 +- search.html | 2 +- shared-structs/implementation/rs-impl.html | 2 +- shared-structs/rs.html | 2 +- synthesis/synthesis.html | 2 +- transactions.html | 2 +- transactron.html | 2 +- transactron.lib.html | 2 +- transactron.testing.html | 2 +- transactron.utils.amaranth_ext.html | 2 +- transactron.utils.html | 2 +- 42 files changed, 511 insertions(+), 511 deletions(-) diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index b1e0d66d9b2e4950abaee14a9c784e0d14872692..d2f818cfcd684506d62478fbd8f77421df029ffb 100644 GIT binary patch delta 459 zcmYjN%SyvQ6m7t6Y}MM7uQ7!NN|E;_S=O2hnb|=}<-I-UpxNifOUUG6>S+;h%w;0y=O>w81rdmD#EpK;udn12awhchZL4UAeu zQn2$bM@eYZvfzjU@&#cO^oO^npPHNctGT_qHoaJ)8A6bA=g_w;|P@St8wKRLC-@L8knd<~`6ob7Z02wC}mqxA3 zscuIaRfKCQLJS0I(@8&j`}))?7xF1A2-L-(51OUh)zmrytC62MuyH5pOn9cUga){8 zJDbDpyJ>Iaer;<4!x?wg& zXdm4`s=_pjSr(O?Y)j^4Cfiu%l7VJ1F&hr!E?J^3OVrG{%)RFWyFc>d>w9~?_j}&U z>AN@hV>ftNulz{BFT27ejZY49Fl~>(3~$8%@4;r?8qlioQ<@U-VM}nWDFZ2bC91CCT93F#XGJL8^r(6-JQE74hy$Hmqg7`vd zlQ6%i{2V^gq@!0R!)SpDJ2V2O8Y+n-o7_6AlE6_=@&`=;=Gvvw9Qfr0T zB!k?T21k+cX{9|zH-0CVl;^C`Cgl;$@%0?8Cpho{ot<ixyj}5|>;8dw;(xn`%sw0;nzw7jtum6_6KEb*x)TeCxJ}j-of@xLw+YOJz!Y zT$+QbvQ9iG6VP3z$3$7iT!%!*vRDrPcvj#|j~k^P1+J9aQChYDK2Id91sSlH$KjoF zH+sv}s32MDA-c_la6Uhcii$!+RxBa90*Wh?=&7(u-A7H48jmW@BW(E!eEC8N+7IZ& zs^vxwBSiTrOK+thUamYHhL5XKSOZe3qOrLukFBC%Rg@@OwS&W_)wA7cZqVS>Y6oVj zeVC}pW)~#is+w2G=RjI*38rdgFx1&XvF~b2X)!i1x+QCM=&QSi!PWU#x4HlmtAD^x zYpfyci8b~)+-j)^|Wo2|8D(qoNRddt`>O>8^o!GZ^H0(qqL?#@cC=N|;D^b}> zgy|cSic_`DK7PG*IntX2=3BqX4bvtf(p(sDs>H{ee&f-*UyVpQ!L|a74r$;Urlea7 znLl|%jhkCjaj|V7F0>@m(cxxGBqq0*a3QGU8y8|cn25_;7A{)3dTse@+qZXZe97x= z_3hZ`?Pz~_apS^gx}^)0KN>Y{sd%z=1?R%mZL!$6jk3}UAw8%QuWoDLxy2AVM9zun zj-~Wl?2CoNr$xLk4ioLk^!;nm?K4mkzt7FP)X*=8#ck$z=u4Fx1AGi}IweF|XDa6s zy`68%$hh;GU3yQn?Yzp-8&kV-VB0-}ySo?RtKC_M?^;CIimv-Smn#`uJY zM=Q!EP|P}iqR$22sYsaiTbO@(MAG%*hx@+|L(c&Z{G$n&K9GU#0}7}P=5kK)xr0iM z+A`K}grmO+Px@!OIM$y}Gty(cB}VRK#QuE2h~`6iRBH1fGd?*qiwo(qSSrguP{`)M zWKc(TA|4FHP-MI_1}TFXEE>`YF{>+aanM4jTZ1_a!DJ}wd4B=(GD&yN`xB5HU;`@& zk41YRTMBb(gsh-GfHZ|mT~}AO250*-=i*cl=L#H-LqAvrAvLHA9A3ufs-=<@x#p$P zFm9QR;;zH@dFXa(*z=APiLf0{k=7R>otEzMi9F_GlI#~prS{E9vi+mQ%x02o>2BJ| zgn7m~Gn~)HIWufT*HPO%sNF}G5K4p3jz-OcxOFrNttYEupSe70jH%-=e#kh_<)Wd? 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zvPF=P4!B0r;a1cufF~G60*@rZ)xPxDI%m=@S-kN{2KHz`Hu&JpuSo z2b>XrPjtXp0l1(8S_I&89q@$!e60h%5rB(K|3b7&0&-O+xh4SL>wrHCz)w2hX94(4 z2iy>V+YG?}@KUQh-a7*l0Wb=HlMbkI77#Zb;w}JQI>1{1{B(f70JPBoZ3Upc4hRx} zP#q8^03CHeCjsbM#UT7oLq!NkcOB3}0HSq3i~#h~0lftvK?fuXK(Y=<5r8xukS+lI zH9(bVfPf5U5Vo9|h6q5W4#*OK937A=0C_rKlmLv;0b>OqUk6MOfC3#*C;(McbjVZz zDb@iq1Ynj9C=q}%9Z)U+6*^#^04&r2iv(ba4p=GxT<_?v7yjUufUM#qH0C+AH(!+T z*sCuw(YbE%WEs%BAJ}Z;Hj@=(}u-rRI4x$?*RG D{S~b& diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index af9ff5633..488d9d5c4 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -7,12 +7,12 @@ Core_InitFreeRFFifo["InitFreeRFFifo"] Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_request["request"] - WishboneMaster_result["result"] WishboneMaster_WishboneMaster["WishboneMaster"] + WishboneMaster_result["result"] + WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] - Forwarder_write["write"] Forwarder_read["read"] + Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] @@ -25,8 +25,8 @@ end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] @@ -37,24 +37,24 @@ end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] - WishboneMasterAdapter1_request_write["request_write"] + WishboneMasterAdapter1_request_read["request_read"] WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_get_read_response["get_read_response"] - WishboneMasterAdapter1_request_read["request_read"] + WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_write["write"] BasicFifo1_read["read"] + BasicFifo1_write["write"] end end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph FIFO["fifo_fetch FIFO"] FIFO_read["read"] @@ -71,20 +71,20 @@ BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] subgraph Forwarder2["address_fwd Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end end subgraph ICache["icache ICache"] ICache_ICache["ICache"] + ICache_accept_res["accept_res"] ICache_ICache1["ICache"] - ICache_issue_req["issue_req"] ICache_ICache2["ICache"] - ICache_accept_res["accept_res"] + ICache_issue_req["issue_req"] ICache_ICache3["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] @@ -113,12 +113,12 @@ end end subgraph FIFO2["req_fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end subgraph FRAT["FRAT FRAT"] @@ -129,17 +129,17 @@ RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_write["write"] - RegisterFile_read1["read1"] RegisterFile_read2["read2"] + RegisterFile_read1["read1"] + RegisterFile_write["write"] RegisterFile_free["free"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_peek["peek"] - ReorderBuffer_retire["retire"] - ReorderBuffer_put["put"] ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_retire["retire"] + ReorderBuffer_peek["peek"] + ReorderBuffer_put["put"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] LatencyMeasurer1__stop["_stop"] LatencyMeasurer1__start["_start"] @@ -147,8 +147,8 @@ HwExpHistogram1__add["_add"] end subgraph FIFO3["fifo FIFO"] - FIFO3_read["read"] FIFO3_write["write"] + FIFO3_read["read"] end end end @@ -163,8 +163,8 @@ end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_get["get"] ExceptionCauseRegister_report["report"] + ExceptionCauseRegister_get["get"] ExceptionCauseRegister_clear["clear"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] BasicFifo4_write["write"] @@ -178,8 +178,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_write["write"] Forwarder4_read["read"] + Forwarder4_write["write"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -199,18 +199,18 @@ subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] RSFuncBlock_insert["insert"] RSFuncBlock_update["update"] - RSFuncBlock_select["select"] RSFuncBlock_get_result["get_result"] + RSFuncBlock_select["select"] subgraph RS["rs RS"] - RS_select["select"] RS_RS["RS"] - RS_take["take"] - RS_insert["insert"] RS_RS1["RS"] RS_RS2["RS"] + RS_update["update"] RS_RS3["RS"] + RS_select["select"] + RS_insert["insert"] RS_RS4["RS"] - RS_update["update"] + RS_take["take"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] AluFuncUnit_accept["accept"] @@ -251,8 +251,8 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_write["write"] FIFO7_read["read"] + FIFO7_write["write"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -284,8 +284,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_read["read"] Forwarder5_write["write"] + Forwarder5_read["read"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans4["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -308,47 +308,47 @@ end subgraph LSUDummy["rs_block_1 LSUDummy"] LSUDummy_select["select"] - LSUDummy_LSUDummy["LSUDummy"] LSUDummy_update["update"] LSUDummy_precommit["precommit"] + LSUDummy_LSUDummy["LSUDummy"] LSUDummy_get_result["get_result"] LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_insert["insert"] + LSUDummy_LSUDummy2["LSUDummy"] subgraph Forwarder6["forwarder Forwarder"] Forwarder6_write["write"] Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_accept["accept"] + LSURequester_accept_cond1["accept_cond1"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_accept_cond0["accept_cond0"] LSURequester_issue["issue"] - LSURequester_accept_cond1["accept_cond1"] - LSURequester_issue_cond0["issue_cond0"] LSURequester_issue_cond2["issue_cond2"] - LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept["accept"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] CSRUnit_select["select"] CSRUnit_fetch_resume["fetch_resume"] CSRUnit_update["update"] - CSRUnit_precommit["precommit"] CSRUnit_get_result["get_result"] - CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_precommit["precommit"] CSRUnit_insert["insert"] + CSRUnit_CSRUnit["CSRUnit"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] - MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_method["method"] + MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_write["write"] Forwarder7_read["read"] + Forwarder7_write["write"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans9["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -365,53 +365,53 @@ end subgraph InterruptController["interrupt_controller InterruptController"] InterruptController_mret["mret"] - InterruptController_report_interrupt["report_interrupt"] InterruptController_entry["entry"] + InterruptController_report_interrupt["report_interrupt"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] CSRRegister_write["write"] - CSRRegister__fu_write["_fu_write"] CSRRegister__fu_read["_fu_read"] + CSRRegister__fu_write["_fu_write"] end subgraph CSRRegister1["mtvec CSRRegister"] + CSRRegister1__fu_read["_fu_read"] CSRRegister1_read["read"] CSRRegister1__fu_write["_fu_write"] - CSRRegister1__fu_read["_fu_read"] end subgraph CSRRegister2["mepc CSRRegister"] + CSRRegister2__fu_write["_fu_write"] + CSRRegister2__fu_read["_fu_read"] CSRRegister2_write["write"] CSRRegister2_read["read"] - CSRRegister2__fu_read["_fu_read"] - CSRRegister2__fu_write["_fu_write"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] - CSRRegister3_write["write"] CSRRegister3_read["read"] + CSRRegister3_write["write"] CSRRegister3__fu_read["_fu_read"] end subgraph CSRRegister4["register_high CSRRegister"] CSRRegister4_read["read"] - CSRRegister4__fu_read["_fu_read"] CSRRegister4_write["write"] + CSRRegister4__fu_read["_fu_read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_read["read"] CSRRegister5__fu_read["_fu_read"] CSRRegister5_write["write"] + CSRRegister5_read["read"] end subgraph CSRRegister6["register_high CSRRegister"] + CSRRegister6__fu_read["_fu_read"] CSRRegister6_write["write"] CSRRegister6_read["read"] - CSRRegister6__fu_read["_fu_read"] end end end @@ -434,15 +434,15 @@ RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO11["rename_out_buf FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] end subgraph FIFO12["reg_alloc_out_buf FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -471,23 +471,23 @@ subgraph Retirement["retirement Retirement"] Retirement_Retirement["Retirement"] Retirement_Retirement1["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement2["Retirement"] - Retirement_core_state["core_state"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement3["Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] + Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_core_state["core_state"] Retirement_Retirement4["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] - CSRRegister7_read["read"] CSRRegister7__fu_read["_fu_read"] CSRRegister7_write["write"] + CSRRegister7_read["read"] end subgraph CSRRegister8["register_high CSRRegister"] - CSRRegister8__fu_read["_fu_read"] - CSRRegister8_write["write"] CSRRegister8_read["read"] + CSRRegister8_write["write"] + CSRRegister8__fu_read["_fu_read"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -507,19 +507,19 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] - TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] + TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] end end Core_InitFreeRFFifo --> BasicFifo2_write - Retirement_Retirement --> BasicFifo2_write - TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write - TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write + Retirement_Retirement3 --> BasicFifo2_write + TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write + TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write @@ -528,20 +528,20 @@ SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request - ICache_ICache2 <--> HwCounter4__incr + ICache_ICache1 <--> HwCounter4__incr ICache_ICache <--> HwCounter3__incr ICache_ICache <--> HwCounter2__incr ICache_ICache <--> HwCounter1__incr ICache_ICache --> Forwarder3_write - ICache_ICache3 --> SimpleCommonBusCacheRefiller_start_refill + ICache_ICache2 --> SimpleCommonBusCacheRefiller_start_refill + ICache_ICache2 --> Forwarder2_write ICache_ICache3 --> Forwarder2_write - ICache_ICache1 --> Forwarder2_write - SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 - WishboneMasterAdapter_get_read_response --> ICache_ICache1 - Serializer_Serializer1 --> ICache_ICache1 - BasicFifo_read --> ICache_ICache1 - WishboneMaster_result --> ICache_ICache1 - Forwarder_read --> ICache_ICache1 + SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3 + WishboneMasterAdapter_get_read_response --> ICache_ICache3 + Serializer_Serializer1 --> ICache_ICache3 + BasicFifo_read --> ICache_ICache3 + WishboneMaster_result --> ICache_ICache3 + Forwarder_read --> ICache_ICache3 Fetch_Fetch --> ICache_issue_req Fetch_Fetch <--> HwCounter__incr Fetch_Fetch <--> LatencyMeasurer__start @@ -571,8 +571,8 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename - Retirement_Retirement --> FRAT_rename - TransactionManager_Retirement_cond1_Retirement --> FRAT_rename + Retirement_Retirement3 --> FRAT_rename + TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put @@ -582,15 +582,15 @@ FIFO12_read --> RSSelection_RSSelection RSSelection_RSSelection --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection2 - Forwarder8_read --> RSSelection_RSSelection3 Forwarder8_read --> RSSelection_RSSelection1 + Forwarder8_read --> RSSelection_RSSelection3 RSFuncBlock_select --> RSSelection_RSSelection2 RS_select --> RSSelection_RSSelection2 RSSelection_RSSelection2 --> FIFO13_write - RSSelection_RSSelection3 --> FIFO13_write RSSelection_RSSelection1 --> FIFO13_write - RSSelection_RSSelection3 <--> LSUDummy_select - RSSelection_RSSelection1 <--> CSRUnit_select + RSSelection_RSSelection3 --> FIFO13_write + RSSelection_RSSelection1 <--> LSUDummy_select + RSSelection_RSSelection3 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -606,7 +606,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume - Retirement_Retirement2 --> Fetch_resume + Retirement_Retirement4 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -616,7 +616,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update - RS_RS1 --> WakeupSelect_WakeupSelect + RS_RS4 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -624,10 +624,10 @@ RS_take --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO4_write - RS_RS4 --> WakeupSelect1_WakeupSelect + RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write - RS_RS3 --> WakeupSelect2_WakeupSelect + RS_RS2 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -639,10 +639,10 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write - RS_RS2 --> WakeupSelect3_WakeupSelect + RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write - RS_RS --> WakeupSelect4_WakeupSelect + RS_RS1 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -661,11 +661,11 @@ CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write LSUDummy_LSUDummy2 --> Forwarder6_write - TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write - TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write + TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write - TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write + TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write + TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -687,45 +687,45 @@ LSUDummy_get_result --> ConnectTrans2_ConnectTrans Forwarder6_read --> ConnectTrans2_ConnectTrans CSRUnit_get_result --> ConnectTrans3_ConnectTrans - MethodTryProduct_MethodTryProduct1 --> PrivilegedFuncUnit_precommit - MethodTryProduct_MethodTryProduct1 <--> InterruptController_mret - MethodTryProduct_MethodTryProduct2 --> LSUDummy_precommit - MethodTryProduct_MethodTryProduct --> CSRUnit_precommit + MethodTryProduct_MethodTryProduct --> PrivilegedFuncUnit_precommit + MethodTryProduct_MethodTryProduct <--> InterruptController_mret + MethodTryProduct_MethodTryProduct1 --> LSUDummy_precommit + MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans + ReorderBuffer_peek --> Retirement_Retirement2 ReorderBuffer_peek --> Retirement_Retirement1 ReorderBuffer_peek --> Retirement_Retirement3 - ReorderBuffer_peek --> Retirement_Retirement - ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement - ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement1 --> MethodTryProduct_method - ExceptionCauseRegister_get --> Retirement_Retirement3 - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement <--> ReorderBuffer_retire - TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire - TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire - Retirement_Retirement <--> LatencyMeasurer1__stop - TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop - TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop - FIFO3_read --> Retirement_Retirement - FIFO3_read --> TransactionManager_Retirement_cond0_Retirement - FIFO3_read --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement --> HwExpHistogram1__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add - TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add - CoreInstructionCounter_decrement --> Retirement_Retirement - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement - RRAT_peek --> Retirement_Retirement - RRAT_peek --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement --> RegisterFile_free - TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free - TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free - CSRRegister1_read --> Retirement_Retirement2 - Retirement_Retirement2 <--> ExceptionCauseRegister_clear + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement2 --> MethodTryProduct_method + ExceptionCauseRegister_get --> Retirement_Retirement1 + ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 + ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement3 <--> ReorderBuffer_retire + TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire + TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire + Retirement_Retirement3 <--> LatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop + FIFO3_read --> Retirement_Retirement3 + FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 + FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement3 --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add + CoreInstructionCounter_decrement --> Retirement_Retirement3 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 + RRAT_peek --> Retirement_Retirement3 + RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement3 --> RegisterFile_free + TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free + TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free + CSRRegister1_read --> Retirement_Retirement4 + Retirement_Retirement4 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -737,42 +737,28 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt - TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy - Serializer1_Serializer3 --> TransactionManager_accept_cond0_LSUDummy + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write + TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 + TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy + TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy + LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 + LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy + TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 + Serializer1_Serializer2 --> TransactionManager_LSUDummy_accept_cond1 + BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy - BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy + WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy - WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy + Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy - Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy - TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy - TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy - LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy - LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy - TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 - TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 - TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 - TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 - TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue - TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue - TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_cond0_Retirement --> RRAT_commit - TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment - CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write - CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write - TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement4 - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement4 - TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write - TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry - TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer @@ -780,10 +766,24 @@ TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 - TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy - Serializer1_Serializer1 --> TransactionManager_accept_cond1_LSUDummy + TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue + TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy + Serializer1_Serializer1 --> TransactionManager_accept_cond0_LSUDummy TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write - TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer2 + TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3 + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit + TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment + CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write + CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr + TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 diff --git a/api.html b/api.html index 5e0aea3a8..f827f651a 100644 --- a/api.html +++ b/api.html @@ -281,7 +281,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:20 2024-03-06. + Last updated on 17:29 2024-03-06.

diff --git a/assumptions.html b/assumptions.html index da86a8395..e9ee259bd 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:20 2024-03-06. + Last updated on 17:29 2024-03-06.

diff --git a/auto_graph.html b/auto_graph.html index 85b38caaf..656aa3540 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -86,12 +86,12 @@ Core_InitFreeRFFifo["InitFreeRFFifo"] Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_request["request"] - WishboneMaster_result["result"] WishboneMaster_WishboneMaster["WishboneMaster"] + WishboneMaster_result["result"] + WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] - Forwarder_write["write"] Forwarder_read["read"] + Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] @@ -104,8 +104,8 @@ end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] @@ -116,24 +116,24 @@ end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] - WishboneMasterAdapter1_request_write["request_write"] + WishboneMasterAdapter1_request_read["request_read"] WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_get_read_response["get_read_response"] - WishboneMasterAdapter1_request_read["request_read"] + WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_write["write"] BasicFifo1_read["read"] + BasicFifo1_write["write"] end end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph FIFO["fifo_fetch FIFO"] FIFO_read["read"] @@ -150,20 +150,20 @@ BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] subgraph Forwarder2["address_fwd Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end end subgraph ICache["icache ICache"] ICache_ICache["ICache"] + ICache_accept_res["accept_res"] ICache_ICache1["ICache"] - ICache_issue_req["issue_req"] ICache_ICache2["ICache"] - ICache_accept_res["accept_res"] + ICache_issue_req["issue_req"] ICache_ICache3["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] @@ -192,12 +192,12 @@ end end subgraph FIFO2["req_fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end subgraph FRAT["FRAT FRAT"] @@ -208,17 +208,17 @@ RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_write["write"] - RegisterFile_read1["read1"] RegisterFile_read2["read2"] + RegisterFile_read1["read1"] + RegisterFile_write["write"] RegisterFile_free["free"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_peek["peek"] - ReorderBuffer_retire["retire"] - ReorderBuffer_put["put"] ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_retire["retire"] + ReorderBuffer_peek["peek"] + ReorderBuffer_put["put"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] LatencyMeasurer1__stop["_stop"] LatencyMeasurer1__start["_start"] @@ -226,8 +226,8 @@ HwExpHistogram1__add["_add"] end subgraph FIFO3["fifo FIFO"] - FIFO3_read["read"] FIFO3_write["write"] + FIFO3_read["read"] end end end @@ -242,8 +242,8 @@ end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_get["get"] ExceptionCauseRegister_report["report"] + ExceptionCauseRegister_get["get"] ExceptionCauseRegister_clear["clear"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] BasicFifo4_write["write"] @@ -257,8 +257,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_write["write"] Forwarder4_read["read"] + Forwarder4_write["write"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -278,18 +278,18 @@ subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] RSFuncBlock_insert["insert"] RSFuncBlock_update["update"] - RSFuncBlock_select["select"] RSFuncBlock_get_result["get_result"] + RSFuncBlock_select["select"] subgraph RS["rs RS"] - RS_select["select"] RS_RS["RS"] - RS_take["take"] - RS_insert["insert"] RS_RS1["RS"] RS_RS2["RS"] + RS_update["update"] RS_RS3["RS"] + RS_select["select"] + RS_insert["insert"] RS_RS4["RS"] - RS_update["update"] + RS_take["take"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] AluFuncUnit_accept["accept"] @@ -330,8 +330,8 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_write["write"] FIFO7_read["read"] + FIFO7_write["write"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -363,8 +363,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_read["read"] Forwarder5_write["write"] + Forwarder5_read["read"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans4["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -387,47 +387,47 @@ end subgraph LSUDummy["rs_block_1 LSUDummy"] LSUDummy_select["select"] - LSUDummy_LSUDummy["LSUDummy"] LSUDummy_update["update"] LSUDummy_precommit["precommit"] + LSUDummy_LSUDummy["LSUDummy"] LSUDummy_get_result["get_result"] LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_insert["insert"] + LSUDummy_LSUDummy2["LSUDummy"] subgraph Forwarder6["forwarder Forwarder"] Forwarder6_write["write"] Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_accept["accept"] + LSURequester_accept_cond1["accept_cond1"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_accept_cond0["accept_cond0"] LSURequester_issue["issue"] - LSURequester_accept_cond1["accept_cond1"] - LSURequester_issue_cond0["issue_cond0"] LSURequester_issue_cond2["issue_cond2"] - LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept["accept"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] CSRUnit_select["select"] CSRUnit_fetch_resume["fetch_resume"] CSRUnit_update["update"] - CSRUnit_precommit["precommit"] CSRUnit_get_result["get_result"] - CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_precommit["precommit"] CSRUnit_insert["insert"] + CSRUnit_CSRUnit["CSRUnit"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] - MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_method["method"] + MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_write["write"] Forwarder7_read["read"] + Forwarder7_write["write"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans9["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -444,53 +444,53 @@ end subgraph InterruptController["interrupt_controller InterruptController"] InterruptController_mret["mret"] - InterruptController_report_interrupt["report_interrupt"] InterruptController_entry["entry"] + InterruptController_report_interrupt["report_interrupt"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] CSRRegister_write["write"] - CSRRegister__fu_write["_fu_write"] CSRRegister__fu_read["_fu_read"] + CSRRegister__fu_write["_fu_write"] end subgraph CSRRegister1["mtvec CSRRegister"] + CSRRegister1__fu_read["_fu_read"] CSRRegister1_read["read"] CSRRegister1__fu_write["_fu_write"] - CSRRegister1__fu_read["_fu_read"] end subgraph CSRRegister2["mepc CSRRegister"] + CSRRegister2__fu_write["_fu_write"] + CSRRegister2__fu_read["_fu_read"] CSRRegister2_write["write"] CSRRegister2_read["read"] - CSRRegister2__fu_read["_fu_read"] - CSRRegister2__fu_write["_fu_write"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] - CSRRegister3_write["write"] CSRRegister3_read["read"] + CSRRegister3_write["write"] CSRRegister3__fu_read["_fu_read"] end subgraph CSRRegister4["register_high CSRRegister"] CSRRegister4_read["read"] - CSRRegister4__fu_read["_fu_read"] CSRRegister4_write["write"] + CSRRegister4__fu_read["_fu_read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_read["read"] CSRRegister5__fu_read["_fu_read"] CSRRegister5_write["write"] + CSRRegister5_read["read"] end subgraph CSRRegister6["register_high CSRRegister"] + CSRRegister6__fu_read["_fu_read"] CSRRegister6_write["write"] CSRRegister6_read["read"] - CSRRegister6__fu_read["_fu_read"] end end end @@ -513,15 +513,15 @@ RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO11["rename_out_buf FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] end subgraph FIFO12["reg_alloc_out_buf FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -550,23 +550,23 @@ subgraph Retirement["retirement Retirement"] Retirement_Retirement["Retirement"] Retirement_Retirement1["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement2["Retirement"] - Retirement_core_state["core_state"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement3["Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] + Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_core_state["core_state"] Retirement_Retirement4["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] - CSRRegister7_read["read"] CSRRegister7__fu_read["_fu_read"] CSRRegister7_write["write"] + CSRRegister7_read["read"] end subgraph CSRRegister8["register_high CSRRegister"] - CSRRegister8__fu_read["_fu_read"] - CSRRegister8_write["write"] CSRRegister8_read["read"] + CSRRegister8_write["write"] + CSRRegister8__fu_read["_fu_read"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -586,19 +586,19 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] - TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] + TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] end end Core_InitFreeRFFifo --> BasicFifo2_write -Retirement_Retirement --> BasicFifo2_write -TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write -TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write +Retirement_Retirement3 --> BasicFifo2_write +TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write +TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write @@ -607,20 +607,20 @@ SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request -ICache_ICache2 <--> HwCounter4__incr +ICache_ICache1 <--> HwCounter4__incr ICache_ICache <--> HwCounter3__incr ICache_ICache <--> HwCounter2__incr ICache_ICache <--> HwCounter1__incr ICache_ICache --> Forwarder3_write -ICache_ICache3 --> SimpleCommonBusCacheRefiller_start_refill +ICache_ICache2 --> SimpleCommonBusCacheRefiller_start_refill +ICache_ICache2 --> Forwarder2_write ICache_ICache3 --> Forwarder2_write -ICache_ICache1 --> Forwarder2_write -SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 -WishboneMasterAdapter_get_read_response --> ICache_ICache1 -Serializer_Serializer1 --> ICache_ICache1 -BasicFifo_read --> ICache_ICache1 -WishboneMaster_result --> ICache_ICache1 -Forwarder_read --> ICache_ICache1 +SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3 +WishboneMasterAdapter_get_read_response --> ICache_ICache3 +Serializer_Serializer1 --> ICache_ICache3 +BasicFifo_read --> ICache_ICache3 +WishboneMaster_result --> ICache_ICache3 +Forwarder_read --> ICache_ICache3 Fetch_Fetch --> ICache_issue_req Fetch_Fetch <--> HwCounter__incr Fetch_Fetch <--> LatencyMeasurer__start @@ -650,8 +650,8 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename -Retirement_Retirement --> FRAT_rename -TransactionManager_Retirement_cond1_Retirement --> FRAT_rename +Retirement_Retirement3 --> FRAT_rename +TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put @@ -661,15 +661,15 @@ FIFO12_read --> RSSelection_RSSelection RSSelection_RSSelection --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection2 -Forwarder8_read --> RSSelection_RSSelection3 Forwarder8_read --> RSSelection_RSSelection1 +Forwarder8_read --> RSSelection_RSSelection3 RSFuncBlock_select --> RSSelection_RSSelection2 RS_select --> RSSelection_RSSelection2 RSSelection_RSSelection2 --> FIFO13_write -RSSelection_RSSelection3 --> FIFO13_write RSSelection_RSSelection1 --> FIFO13_write -RSSelection_RSSelection3 <--> LSUDummy_select -RSSelection_RSSelection1 <--> CSRUnit_select +RSSelection_RSSelection3 --> FIFO13_write +RSSelection_RSSelection1 <--> LSUDummy_select +RSSelection_RSSelection3 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -685,7 +685,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume -Retirement_Retirement2 --> Fetch_resume +Retirement_Retirement4 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -695,7 +695,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update -RS_RS1 --> WakeupSelect_WakeupSelect +RS_RS4 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -703,10 +703,10 @@ RS_take --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO4_write -RS_RS4 --> WakeupSelect1_WakeupSelect +RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write -RS_RS3 --> WakeupSelect2_WakeupSelect +RS_RS2 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -718,10 +718,10 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write -RS_RS2 --> WakeupSelect3_WakeupSelect +RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write -RS_RS --> WakeupSelect4_WakeupSelect +RS_RS1 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -740,11 +740,11 @@ CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write LSUDummy_LSUDummy2 --> Forwarder6_write -TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write -TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write +TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write -TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write +TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write +TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -766,45 +766,45 @@ LSUDummy_get_result --> ConnectTrans2_ConnectTrans Forwarder6_read --> ConnectTrans2_ConnectTrans CSRUnit_get_result --> ConnectTrans3_ConnectTrans -MethodTryProduct_MethodTryProduct1 --> PrivilegedFuncUnit_precommit -MethodTryProduct_MethodTryProduct1 <--> InterruptController_mret -MethodTryProduct_MethodTryProduct2 --> LSUDummy_precommit -MethodTryProduct_MethodTryProduct --> CSRUnit_precommit +MethodTryProduct_MethodTryProduct --> PrivilegedFuncUnit_precommit +MethodTryProduct_MethodTryProduct <--> InterruptController_mret +MethodTryProduct_MethodTryProduct1 --> LSUDummy_precommit +MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans +ReorderBuffer_peek --> Retirement_Retirement2 ReorderBuffer_peek --> Retirement_Retirement1 ReorderBuffer_peek --> Retirement_Retirement3 -ReorderBuffer_peek --> Retirement_Retirement -ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement -ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement1 --> MethodTryProduct_method -ExceptionCauseRegister_get --> Retirement_Retirement3 -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement <--> ReorderBuffer_retire -TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire -TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire -Retirement_Retirement <--> LatencyMeasurer1__stop -TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop -TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop -FIFO3_read --> Retirement_Retirement -FIFO3_read --> TransactionManager_Retirement_cond0_Retirement -FIFO3_read --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement --> HwExpHistogram1__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add -TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add -CoreInstructionCounter_decrement --> Retirement_Retirement -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement -RRAT_peek --> Retirement_Retirement -RRAT_peek --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement --> RegisterFile_free -TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free -TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free -CSRRegister1_read --> Retirement_Retirement2 -Retirement_Retirement2 <--> ExceptionCauseRegister_clear +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement2 --> MethodTryProduct_method +ExceptionCauseRegister_get --> Retirement_Retirement1 +ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 +ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement3 <--> ReorderBuffer_retire +TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire +TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire +Retirement_Retirement3 <--> LatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop +FIFO3_read --> Retirement_Retirement3 +FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 +FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement3 --> HwExpHistogram1__add +TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add +CoreInstructionCounter_decrement --> Retirement_Retirement3 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 +RRAT_peek --> Retirement_Retirement3 +RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement3 --> RegisterFile_free +TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free +TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free +CSRRegister1_read --> Retirement_Retirement4 +Retirement_Retirement4 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -816,42 +816,28 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt -TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy -Serializer1_Serializer3 --> TransactionManager_accept_cond0_LSUDummy +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write +TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 +TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy +TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy +LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 +LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy +TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 +Serializer1_Serializer2 --> TransactionManager_LSUDummy_accept_cond1 +BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy -BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy +WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy -WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy +Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy -Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy -TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy -TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy -LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy -LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy -TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 -TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 -TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 -TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 -TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue -TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue -TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_cond0_Retirement --> RRAT_commit -TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment -CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write -CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write -TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement4 -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement4 -TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write -TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry -TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer @@ -859,13 +845,27 @@ TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 -TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy -Serializer1_Serializer1 --> TransactionManager_accept_cond1_LSUDummy +TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue +TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy +Serializer1_Serializer1 --> TransactionManager_accept_cond0_LSUDummy TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write -TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer2 +TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3 +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit +TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment +CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write +CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr +TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 @@ -876,7 +876,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:20 2024-03-06. + Last updated on 17:29 2024-03-06.

diff --git a/components/icache.html b/components/icache.html index a6802e473..64df95208 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:20 2024-03-06. + Last updated on 17:29 2024-03-06.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index 841491e14..70794a726 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -241,7 +241,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:20 2024-03-06. + Last updated on 17:29 2024-03-06.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 134189ddb..dcdb92304 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -368,7 +368,7 @@

Submodules

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