diff --git a/.doctrees/Current_graph.doctree b/.doctrees/Current_graph.doctree index c16c8125f..05d93c8d0 100644 Binary files a/.doctrees/Current_graph.doctree and b/.doctrees/Current_graph.doctree differ diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index 4a1bf2615..42611b4bc 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index be71f3acf..8f62837d7 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/coreblocks.fu.doctree b/.doctrees/coreblocks.fu.doctree index e2a9b4002..75be64dea 100644 Binary files a/.doctrees/coreblocks.fu.doctree and b/.doctrees/coreblocks.fu.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index f90d487db..1348fdfbe 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/Assumptions.html b/Assumptions.html index 5a2044731..dedde64f8 100644 --- a/Assumptions.html +++ b/Assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/Current_graph.html b/Current_graph.html index 723773610..696d30cfd 100644 --- a/Current_graph.html +++ b/Current_graph.html @@ -105,16 +105,16 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/Development_environment.html b/Development_environment.html index c2652bc32..234aed7b7 100644 --- a/Development_environment.html +++ b/Development_environment.html @@ -178,7 +178,7 @@

build_docs.sh

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/Home.html b/Home.html index 6cb22ffe7..07cfc2e48 100644 --- a/Home.html +++ b/Home.html @@ -129,7 +129,7 @@

Documentation

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/Problem-checklist.html b/Problem-checklist.html index 3c459f8cb..adb9970f4 100644 --- a/Problem-checklist.html +++ b/Problem-checklist.html @@ -105,7 +105,7 @@

Problem checklist

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/Transactions.html b/Transactions.html index d539ccbd6..244224ae3 100644 --- a/Transactions.html +++ b/Transactions.html @@ -409,7 +409,7 @@

Transaction and method nesting

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index a75639e9a..036294770 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -22,16 +22,16 @@ BasicFifo_read["read"] end subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"] + SimpleWBCacheRefiller_start_refill["start_refill"] SimpleWBCacheRefiller_accept_refill["accept_refill"] SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] - SimpleWBCacheRefiller_start_refill["start_refill"] end subgraph ICache["icache ICache"] + ICache_issue_req["issue_req"] ICache_ICache["ICache"] + ICache_accept_res["accept_res"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] - ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] subgraph FIFO1["req_fifo FIFO"] FIFO1_write["write"] FIFO1_read["read"] @@ -59,19 +59,19 @@ subgraph RegisterFile["RF RegisterFile"] RegisterFile_write["write"] RegisterFile_read1["read1"] - RegisterFile_read2["read2"] RegisterFile_free["free"] + RegisterFile_read2["read2"] end subgraph ReorderBuffer["ROB ReorderBuffer"] + ReorderBuffer_put["put"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_peek["peek"] ReorderBuffer_retire["retire"] - ReorderBuffer_put["put"] - ReorderBuffer_get_indices["get_indices"] end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_report["report"] end subgraph FuncBlocksUnifier["func_blocks_unifier FuncBlocksUnifier"] subgraph Collector["result_collector Collector"] @@ -93,14 +93,14 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_insert["insert"] - RSFuncBlock_select["select"] RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] + RSFuncBlock_select["select"] + RSFuncBlock_insert["insert"] subgraph RS["rs RS"] RS_RS["RS"] - RS_RS1["RS"] RS_update["update"] + RS_RS1["RS"] RS_RS2["RS"] RS_RS3["RS"] RS_take["take"] @@ -108,19 +108,19 @@ RS_select["select"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph FIFO2["fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO3["fifo FIFO"] FIFO3_read["read"] FIFO3_write["write"] @@ -134,12 +134,12 @@ JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] subgraph FIFO4["fifo_res FIFO"] - FIFO4_read["read"] FIFO4_write["write"] + FIFO4_read["read"] end subgraph FIFO5["fifo_branch FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -203,15 +203,15 @@ CSRRegister_read["read"] end subgraph CSRRegister1["register_high CSRRegister"] - CSRRegister1_write["write"] CSRRegister1_read["read"] + CSRRegister1_write["write"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister2["register_low CSRRegister"] - CSRRegister2_read["read"] CSRRegister2_write["write"] + CSRRegister2_read["read"] end subgraph CSRRegister3["register_high CSRRegister"] CSRRegister3_read["read"] @@ -223,23 +223,23 @@ end end subgraph FIFO7["fifo_decode FIFO"] - FIFO7_write["write"] FIFO7_read["read"] + FIFO7_write["write"] end subgraph Decode["decode Decode"] Decode_Decode["Decode"] end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO8["alloc_rename_buf FIFO"] - FIFO8_write["write"] FIFO8_read["read"] + FIFO8_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO9["rename_out_buf FIFO"] - FIFO9_write["write"] FIFO9_read["read"] + FIFO9_write["write"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] @@ -281,8 +281,8 @@ CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_read["read"] CSRRegister6_write["write"] + CSRRegister6_read["read"] end end end @@ -300,12 +300,12 @@ end end Core_InitFreeRFFifo --> BasicFifo_write - Retirement_Retirement1 --> BasicFifo_write + Retirement_Retirement --> BasicFifo_write SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request - ICache_ICache --> Forwarder_write + ICache_ICache2 --> Forwarder_write ICache_ICache1 --> SimpleWBCacheRefiller_start_refill - SimpleWBCacheRefiller_accept_refill --> ICache_ICache2 - WishboneMaster_result --> ICache_ICache2 + SimpleWBCacheRefiller_accept_refill --> ICache_ICache + WishboneMaster_result --> ICache_ICache Fetch_Fetch --> ICache_issue_req Fetch_Fetch --> FIFO1_write Fetch_Fetch --> BasicFifo1_write @@ -326,15 +326,15 @@ FIFO9_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation --> FIFO10_write - FIFO10_read --> RSSelection_RSSelection1 - RSSelection_RSSelection1 --> Forwarder3_write + FIFO10_read --> RSSelection_RSSelection2 + RSSelection_RSSelection2 --> Forwarder3_write Forwarder3_read --> RSSelection_RSSelection - Forwarder3_read --> RSSelection_RSSelection2 + Forwarder3_read --> RSSelection_RSSelection1 RSFuncBlock_select --> RSSelection_RSSelection RS_select --> RSSelection_RSSelection RSSelection_RSSelection --> FIFO11_write - RSSelection_RSSelection2 --> FIFO11_write - RSSelection_RSSelection2 <--> LSUDummy_select + RSSelection_RSSelection1 --> FIFO11_write + RSSelection_RSSelection1 <--> LSUDummy_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -360,19 +360,19 @@ RS_take --> WakeupSelect3_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO2_write - RS_RS1 --> WakeupSelect1_WakeupSelect + RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write - RS_RS3 --> WakeupSelect2_WakeupSelect + RS_RS1 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> ExceptionCauseRegister_report WakeupSelect3_WakeupSelect --> ExceptionCauseRegister_report - LSUDummyInternals_LSUDummyInternals1 --> ExceptionCauseRegister_report LSUDummyInternals_LSUDummyInternals --> ExceptionCauseRegister_report + LSUDummyInternals_LSUDummyInternals1 --> ExceptionCauseRegister_report ReorderBuffer_get_indices --> WakeupSelect2_WakeupSelect ReorderBuffer_get_indices --> WakeupSelect3_WakeupSelect - ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals1 ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals + ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals1 WakeupSelect2_WakeupSelect --> FIFO4_write WakeupSelect2_WakeupSelect --> FIFO5_write RS_RS --> WakeupSelect3_WakeupSelect @@ -391,25 +391,25 @@ ExceptionFuncUnit_accept --> ConnectTrans5_ConnectTrans FIFO6_read --> ConnectTrans5_ConnectTrans LSUDummyInternals_LSUDummyInternals2 --> WishboneMaster1_request - WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals + WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals1 ConnectTrans_ConnectTrans --> Forwarder1_write ConnectTrans1_ConnectTrans --> Forwarder1_write RSFuncBlock_get_result --> ConnectTrans_ConnectTrans Collector1_method --> ConnectTrans_ConnectTrans Forwarder2_read --> ConnectTrans_ConnectTrans LSUDummy_get_result --> ConnectTrans1_ConnectTrans - ReorderBuffer_peek --> Retirement_Retirement - Retirement_Retirement --> LSUDummy_precommit - ReorderBuffer_retire --> Retirement_Retirement1 - ExceptionCauseRegister_get --> Retirement_Retirement1 - Retirement_Retirement1 --> CSRRegister4_write - Retirement_Retirement1 --> RRAT_commit - Retirement_Retirement1 --> RegisterFile_free - Retirement_Retirement1 <--> DoubleCounterCSR2_increment - CSRRegister5_read --> Retirement_Retirement1 - Retirement_Retirement1 --> CSRRegister5_write - CSRRegister6_read --> Retirement_Retirement1 - Retirement_Retirement1 --> CSRRegister6_write + ReorderBuffer_peek --> Retirement_Retirement1 + Retirement_Retirement1 --> LSUDummy_precommit + ReorderBuffer_retire --> Retirement_Retirement + ExceptionCauseRegister_get --> Retirement_Retirement + Retirement_Retirement --> CSRRegister4_write + Retirement_Retirement --> RRAT_commit + Retirement_Retirement --> RegisterFile_free + Retirement_Retirement <--> DoubleCounterCSR2_increment + CSRRegister5_read --> Retirement_Retirement + Retirement_Retirement --> CSRRegister5_write + CSRRegister6_read --> Retirement_Retirement + Retirement_Retirement --> CSRRegister6_write GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister_write diff --git a/api.html b/api.html index 1b2e4ec93..956d83903 100644 --- a/api.html +++ b/api.html @@ -235,7 +235,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/auto_graph.html b/auto_graph.html index 205606384..94d964204 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -101,16 +101,16 @@ BasicFifo_read["read"] end subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"] + SimpleWBCacheRefiller_start_refill["start_refill"] SimpleWBCacheRefiller_accept_refill["accept_refill"] SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] - SimpleWBCacheRefiller_start_refill["start_refill"] end subgraph ICache["icache ICache"] + ICache_issue_req["issue_req"] ICache_ICache["ICache"] + ICache_accept_res["accept_res"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] - ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] subgraph FIFO1["req_fifo FIFO"] FIFO1_write["write"] FIFO1_read["read"] @@ -138,19 +138,19 @@ subgraph RegisterFile["RF RegisterFile"] RegisterFile_write["write"] RegisterFile_read1["read1"] - RegisterFile_read2["read2"] RegisterFile_free["free"] + RegisterFile_read2["read2"] end subgraph ReorderBuffer["ROB ReorderBuffer"] + ReorderBuffer_put["put"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_peek["peek"] ReorderBuffer_retire["retire"] - ReorderBuffer_put["put"] - ReorderBuffer_get_indices["get_indices"] end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_report["report"] end subgraph FuncBlocksUnifier["func_blocks_unifier FuncBlocksUnifier"] subgraph Collector["result_collector Collector"] @@ -172,14 +172,14 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_insert["insert"] - RSFuncBlock_select["select"] RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] + RSFuncBlock_select["select"] + RSFuncBlock_insert["insert"] subgraph RS["rs RS"] RS_RS["RS"] - RS_RS1["RS"] RS_update["update"] + RS_RS1["RS"] RS_RS2["RS"] RS_RS3["RS"] RS_take["take"] @@ -187,19 +187,19 @@ RS_select["select"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph FIFO2["fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO3["fifo FIFO"] FIFO3_read["read"] FIFO3_write["write"] @@ -213,12 +213,12 @@ JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] subgraph FIFO4["fifo_res FIFO"] - FIFO4_read["read"] FIFO4_write["write"] + FIFO4_read["read"] end subgraph FIFO5["fifo_branch FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -282,15 +282,15 @@ CSRRegister_read["read"] end subgraph CSRRegister1["register_high CSRRegister"] - CSRRegister1_write["write"] CSRRegister1_read["read"] + CSRRegister1_write["write"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister2["register_low CSRRegister"] - CSRRegister2_read["read"] CSRRegister2_write["write"] + CSRRegister2_read["read"] end subgraph CSRRegister3["register_high CSRRegister"] CSRRegister3_read["read"] @@ -302,23 +302,23 @@ end end subgraph FIFO7["fifo_decode FIFO"] - FIFO7_write["write"] FIFO7_read["read"] + FIFO7_write["write"] end subgraph Decode["decode Decode"] Decode_Decode["Decode"] end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO8["alloc_rename_buf FIFO"] - FIFO8_write["write"] FIFO8_read["read"] + FIFO8_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO9["rename_out_buf FIFO"] - FIFO9_write["write"] FIFO9_read["read"] + FIFO9_write["write"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] @@ -360,8 +360,8 @@ CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_read["read"] CSRRegister6_write["write"] + CSRRegister6_read["read"] end end end @@ -379,12 +379,12 @@ end end Core_InitFreeRFFifo --> BasicFifo_write -Retirement_Retirement1 --> BasicFifo_write +Retirement_Retirement --> BasicFifo_write SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request -ICache_ICache --> Forwarder_write +ICache_ICache2 --> Forwarder_write ICache_ICache1 --> SimpleWBCacheRefiller_start_refill -SimpleWBCacheRefiller_accept_refill --> ICache_ICache2 -WishboneMaster_result --> ICache_ICache2 +SimpleWBCacheRefiller_accept_refill --> ICache_ICache +WishboneMaster_result --> ICache_ICache Fetch_Fetch --> ICache_issue_req Fetch_Fetch --> FIFO1_write Fetch_Fetch --> BasicFifo1_write @@ -405,15 +405,15 @@ FIFO9_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation --> FIFO10_write -FIFO10_read --> RSSelection_RSSelection1 -RSSelection_RSSelection1 --> Forwarder3_write +FIFO10_read --> RSSelection_RSSelection2 +RSSelection_RSSelection2 --> Forwarder3_write Forwarder3_read --> RSSelection_RSSelection -Forwarder3_read --> RSSelection_RSSelection2 +Forwarder3_read --> RSSelection_RSSelection1 RSFuncBlock_select --> RSSelection_RSSelection RS_select --> RSSelection_RSSelection RSSelection_RSSelection --> FIFO11_write -RSSelection_RSSelection2 --> FIFO11_write -RSSelection_RSSelection2 <--> LSUDummy_select +RSSelection_RSSelection1 --> FIFO11_write +RSSelection_RSSelection1 <--> LSUDummy_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -439,19 +439,19 @@ RS_take --> WakeupSelect3_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO2_write -RS_RS1 --> WakeupSelect1_WakeupSelect +RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write -RS_RS3 --> WakeupSelect2_WakeupSelect +RS_RS1 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> ExceptionCauseRegister_report WakeupSelect3_WakeupSelect --> ExceptionCauseRegister_report -LSUDummyInternals_LSUDummyInternals1 --> ExceptionCauseRegister_report LSUDummyInternals_LSUDummyInternals --> ExceptionCauseRegister_report +LSUDummyInternals_LSUDummyInternals1 --> ExceptionCauseRegister_report ReorderBuffer_get_indices --> WakeupSelect2_WakeupSelect ReorderBuffer_get_indices --> WakeupSelect3_WakeupSelect -ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals1 ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals +ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals1 WakeupSelect2_WakeupSelect --> FIFO4_write WakeupSelect2_WakeupSelect --> FIFO5_write RS_RS --> WakeupSelect3_WakeupSelect @@ -470,25 +470,25 @@ ExceptionFuncUnit_accept --> ConnectTrans5_ConnectTrans FIFO6_read --> ConnectTrans5_ConnectTrans LSUDummyInternals_LSUDummyInternals2 --> WishboneMaster1_request -WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals +WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals1 ConnectTrans_ConnectTrans --> Forwarder1_write ConnectTrans1_ConnectTrans --> Forwarder1_write RSFuncBlock_get_result --> ConnectTrans_ConnectTrans Collector1_method --> ConnectTrans_ConnectTrans Forwarder2_read --> ConnectTrans_ConnectTrans LSUDummy_get_result --> ConnectTrans1_ConnectTrans -ReorderBuffer_peek --> Retirement_Retirement -Retirement_Retirement --> LSUDummy_precommit -ReorderBuffer_retire --> Retirement_Retirement1 -ExceptionCauseRegister_get --> Retirement_Retirement1 -Retirement_Retirement1 --> CSRRegister4_write -Retirement_Retirement1 --> RRAT_commit -Retirement_Retirement1 --> RegisterFile_free -Retirement_Retirement1 <--> DoubleCounterCSR2_increment -CSRRegister5_read --> Retirement_Retirement1 -Retirement_Retirement1 --> CSRRegister5_write -CSRRegister6_read --> Retirement_Retirement1 -Retirement_Retirement1 --> CSRRegister6_write +ReorderBuffer_peek --> Retirement_Retirement1 +Retirement_Retirement1 --> LSUDummy_precommit +ReorderBuffer_retire --> Retirement_Retirement +ExceptionCauseRegister_get --> Retirement_Retirement +Retirement_Retirement --> CSRRegister4_write +Retirement_Retirement --> RRAT_commit +Retirement_Retirement --> RegisterFile_free +Retirement_Retirement <--> DoubleCounterCSR2_increment +CSRRegister5_read --> Retirement_Retirement +Retirement_Retirement --> CSRRegister5_write +CSRRegister6_read --> Retirement_Retirement +Retirement_Retirement --> CSRRegister6_write GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister_write @@ -509,7 +509,7 @@

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/components/icache.html b/components/icache.html index ec868c72f..0eae81dc6 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index dd03d89ce..e1972c057 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -399,7 +399,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/coreblocks.fu.html b/coreblocks.fu.html index bc4946181..0f2c7f968 100644 --- a/coreblocks.fu.html +++ b/coreblocks.fu.html @@ -209,7 +209,17 @@

Submodules
get_instructions() → Sequence[tuple]
-
+

Method providing list of valid instruction.

+
+
Returns
+
+
returnSequence[tuple]

List of implemented instructions, each following format: +(IntFlag, OpType, Funct3 (optional), Funct7 (optional))

+
+
+
+
+
@@ -295,37 +305,71 @@

Submodules
Fn: Type[IntFlag]
-

Method providing list of valid instruction.

+

Enumeration of instructions implemented in given functional unit.

+
+ +
+
+get_decoder(gen_params: GenParams) → Decoder
+

Method returning auto generated instruction decoder.

-
Returns
+
Parameters
-
returnSequence[tuple]

List of implemented instructions, each following format: -(IntFlag, OpType, Funct3 (optional), Funct7 (optional))

+
gen_params: GenParams

Generation parameters passed to a decoder contructor.

+
+
+
+
Returns
+
+
returnset[OpType]

List of OpTypes.

-
-
-get_decoder(gen_params: GenParams) → Decoder
-
-
get_function() → Value
-
+

Method returning Signal Object for decoder, called function in FU blocks

+
+
Returns
+
+
returnValue

Signal object.

+
+
+
+
+
get_instructions() → Sequence[tuple]
-
+

Method providing list of valid instruction.

+
+
Returns
+
+
returnSequence[tuple]

List of implemented instructions, each following format: +(IntFlag, OpType, Funct3 (optional), Funct7 (optional))

+
+
+
+
+
get_op_types() → set[coreblocks.params.optypes.OpType]
-
+

Method returning op types from listed instructions.

+
+
Returns
+
+
returnset[OpType]

List of OpTypes.

+
+
+
+
+
@@ -442,7 +486,17 @@

Submodules
get_instructions() → Sequence[tuple]
-
+

Method providing list of valid instruction.

+
+
Returns
+
+
returnSequence[tuple]

List of implemented instructions, each following format: +(IntFlag, OpType, Funct3 (optional), Funct7 (optional))

+
+
+
+
+
@@ -657,7 +711,17 @@

Submodules
classmethod get_instructions() → Sequence[tuple]
-
+

Method providing list of valid instruction.

+
+
Returns
+
+
returnSequence[tuple]

List of implemented instructions, each following format: +(IntFlag, OpType, Funct3 (optional), Funct7 (optional))

+
+
+
+
+
@@ -700,16 +764,23 @@

Submodules
__init__(gen_params: ~coreblocks.params.genparams.GenParams, function=<coreblocks.fu.zbs.ZbsFunction object>)
-
+
+
Parameters
+
+
gen_paramsGenParams

Core generation parameters.

+
+
functionZbsFunction

Decoder manager to decode instruction.

+
+
+
+
+
@@ -773,7 +844,17 @@

Submodules
get_instructions() → Sequence[tuple]
-
+

Method providing list of valid instruction.

+
+
Returns
+
+
returnSequence[tuple]

List of implemented instructions, each following format: +(IntFlag, OpType, Funct3 (optional), Funct7 (optional))

+
+
+
+
+
@@ -817,7 +898,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/coreblocks.fu.unsigned_multiplication.html b/coreblocks.fu.unsigned_multiplication.html index 8f7ce8708..316062944 100644 --- a/coreblocks.fu.unsigned_multiplication.html +++ b/coreblocks.fu.unsigned_multiplication.html @@ -237,7 +237,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/coreblocks.html b/coreblocks.html index 824bb16ed..e7ad40961 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -218,7 +218,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/coreblocks.params.html b/coreblocks.params.html index 6e7c8637d..7d901abe2 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -2404,7 +2404,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index 89e4d6a7a..e0ad24e3e 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -348,7 +348,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index d540a21ba..4bba256bb 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/coreblocks.stages.html b/coreblocks.stages.html index 539a9a26a..5f9779210 100644 --- a/coreblocks.stages.html +++ b/coreblocks.stages.html @@ -266,7 +266,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/coreblocks.structs_common.html b/coreblocks.structs_common.html index d2c8c04c1..7d6b9f564 100644 --- a/coreblocks.structs_common.html +++ b/coreblocks.structs_common.html @@ -454,7 +454,7 @@

Submodules

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diff --git a/coreblocks.utils.html b/coreblocks.utils.html index d71f1fd28..2ae781e8c 100644 --- a/coreblocks.utils.html +++ b/coreblocks.utils.html @@ -478,7 +478,7 @@

Submodules

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diff --git a/genindex.html b/genindex.html index e9a662495..29bfee28a 100644 --- a/genindex.html +++ b/genindex.html @@ -2776,7 +2776,7 @@

Z

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diff --git a/index.html b/index.html index 0b3ead185..8b11085f4 100644 --- a/index.html +++ b/index.html @@ -221,7 +221,7 @@

Coreblocks

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/miscellany/exceptionsSummary.html b/miscellany/exceptionsSummary.html index fbc78bf78..c28168774 100644 --- a/miscellany/exceptionsSummary.html +++ b/miscellany/exceptionsSummary.html @@ -271,7 +271,7 @@

Summary

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/modules-coreblocks.html b/modules-coreblocks.html index f1c7d1824..83a5a7872 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -187,7 +187,7 @@

coreblocks

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/modules-transactron.html b/modules-transactron.html index 7aad88c22..8d0802ffd 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -118,7 +118,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/py-modindex.html b/py-modindex.html index 69dc1ea20..4c05770c9 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -453,7 +453,7 @@

Python Module Index

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/scheduler/Overview.html b/scheduler/Overview.html index 050be183a..0ba2808ec 100644 --- a/scheduler/Overview.html +++ b/scheduler/Overview.html @@ -146,7 +146,7 @@

More detailed description of each block

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

diff --git a/search.html b/search.html index 8fa387869..c15c7b4d2 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.

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Read and clean row

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External interface signals

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Benchmarks

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diff --git a/transactron.html b/transactron.html index 046789da3..75d7582b8 100644 --- a/transactron.html +++ b/transactron.html @@ -1297,7 +1297,7 @@

Submodules

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diff --git a/transactron.lib.html b/transactron.lib.html index b7dd1ff67..3cb89388b 100644 --- a/transactron.lib.html +++ b/transactron.lib.html @@ -895,7 +895,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 16:15 2023-11-02. + Last updated on 20:30 2023-11-05.