diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index a57107503..da29cf1a2 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index 711b36203..2a16c5f4b 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/coreblocks.cache.doctree b/.doctrees/coreblocks.cache.doctree index 2d501f1ea..e517a79ad 100644 Binary files a/.doctrees/coreblocks.cache.doctree and b/.doctrees/coreblocks.cache.doctree differ diff --git a/.doctrees/coreblocks.params.doctree b/.doctrees/coreblocks.params.doctree index 47500e28a..27fb7cf9c 100644 Binary files a/.doctrees/coreblocks.params.doctree and b/.doctrees/coreblocks.params.doctree differ diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree index 8688866a0..3a5f64e1d 100644 Binary files a/.doctrees/current-graph.doctree and b/.doctrees/current-graph.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index 01b62b1e1..9938f9fd5 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 39cd85ef8..348488966 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -7,12 +7,12 @@ Core_DiscardBranchVerify["DiscardBranchVerify"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_WishboneMaster["WishboneMaster"] - WishboneMaster_request["request"] WishboneMaster_result["result"] + WishboneMaster_request["request"] + WishboneMaster_WishboneMaster["WishboneMaster"] subgraph Forwarder["result Forwarder"] - Forwarder_read["read"] Forwarder_write["write"] + Forwarder_read["read"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] @@ -25,40 +25,40 @@ end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] + WishboneMasterAdapter1_request_read["request_read"] WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_get_write_response["get_write_response"] - WishboneMasterAdapter1_request_read["request_read"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_write["write"] BasicFifo1_read["read"] + BasicFifo1_write["write"] end end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph FIFO["fifo_fetch FIFO"] - FIFO_read["read"] FIFO_write["write"] + FIFO_read["read"] end subgraph MethodMap["core_counter_increment_discard_map MethodMap"] MethodMap_method["method"] @@ -67,14 +67,15 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] - subgraph Forwarder2["address_fwd Forwarder"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] + subgraph Forwarder2["resp_fwd Forwarder"] Forwarder2_read["read"] Forwarder2_write["write"] end @@ -82,10 +83,10 @@ subgraph ICache["icache ICache"] ICache_ICache["ICache"] ICache_ICache1["ICache"] - ICache_ICache2["ICache"] ICache_accept_res["accept_res"] - ICache_ICache3["ICache"] ICache_issue_req["issue_req"] + ICache_ICache2["ICache"] + ICache_ICache3["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -102,8 +103,8 @@ HwCounter4__incr["_incr"] end subgraph LatencyMeasurer["req_latency LatencyMeasurer"] - LatencyMeasurer__start["_start"] LatencyMeasurer__stop["_stop"] + LatencyMeasurer__start["_start"] subgraph HwExpHistogram["histogram HwExpHistogram"] HwExpHistogram__add["_add"] end @@ -117,16 +118,16 @@ FIFO2_read["read"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_peek["peek"] RRAT_commit["commit"] + RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] RegisterFile_read1["read1"] @@ -135,14 +136,14 @@ RegisterFile_free["free"] end subgraph ReorderBuffer["ROB ReorderBuffer"] + ReorderBuffer_put["put"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_peek["peek"] ReorderBuffer_retire["retire"] - ReorderBuffer_put["put"] - ReorderBuffer_get_indices["get_indices"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] - LatencyMeasurer1__start["_start"] LatencyMeasurer1__stop["_stop"] + LatencyMeasurer1__start["_start"] subgraph HwExpHistogram1["histogram HwExpHistogram"] HwExpHistogram1__add["_add"] end @@ -154,8 +155,8 @@ end subgraph Fetch["fetch Fetch"] Fetch_Fetch["Fetch"] - Fetch_Fetch1["Fetch"] Fetch_resume["resume"] + Fetch_Fetch1["Fetch"] Fetch_stall_exception["stall_exception"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] BasicFifo3_read["read"] @@ -163,12 +164,12 @@ end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] + ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] ExceptionCauseRegister_clear["clear"] - ExceptionCauseRegister_report["report"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] - BasicFifo4_read["read"] BasicFifo4_write["write"] + BasicFifo4_read["read"] end subgraph ConnectTrans["report_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -178,8 +179,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_read["read"] Forwarder4_write["write"] + Forwarder4_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -197,27 +198,27 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_insert["insert"] RSFuncBlock_select["select"] RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] + RSFuncBlock_insert["insert"] subgraph RS["rs RS"] - RS_update["update"] RS_RS["RS"] + RS_update["update"] + RS_take["take"] RS_RS1["RS"] - RS_select["select"] RS_RS2["RS"] + RS_select["select"] RS_RS3["RS"] - RS_take["take"] - RS_insert["insert"] RS_RS4["RS"] + RS_insert["insert"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] subgraph FIFO4["fifo FIFO"] - FIFO4_read["read"] FIFO4_write["write"] + FIFO4_read["read"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] @@ -251,28 +252,28 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_write["write"] FIFO7_read["read"] + FIFO7_write["write"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] + ExceptionFuncUnit_issue["issue"] subgraph FIFO8["fifo FIFO"] - FIFO8_write["write"] FIFO8_read["read"] + FIFO8_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] + PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_precommit["precommit"] - PrivilegedFuncUnit_issue["issue"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] BasicFifo5_write["write"] BasicFifo5_read["read"] @@ -307,36 +308,36 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_select["select"] - LSUDummy_update["update"] LSUDummy_LSUDummy["LSUDummy"] LSUDummy_precommit["precommit"] LSUDummy_get_result["get_result"] LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_insert["insert"] + LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_select["select"] + LSUDummy_update["update"] subgraph Forwarder6["forwarder Forwarder"] - Forwarder6_read["read"] Forwarder6_write["write"] + Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_issue["issue"] - LSURequester_accept_cond0["accept_cond0"] - LSURequester_issue_cond1["issue_cond1"] - LSURequester_accept["accept"] - LSURequester_issue_cond2["issue_cond2"] LSURequester_accept_cond1["accept_cond1"] LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue_cond2["issue_cond2"] + LSURequester_issue["issue"] + LSURequester_accept["accept"] + LSURequester_issue_cond1["issue_cond1"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_insert["insert"] - CSRUnit_CSRUnit["CSRUnit"] - CSRUnit_fetch_resume["fetch_resume"] CSRUnit_select["select"] CSRUnit_update["update"] CSRUnit_precommit["precommit"] CSRUnit_get_result["get_result"] + CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_insert["insert"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] @@ -347,8 +348,8 @@ subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_write["write"] Forwarder7_read["read"] + Forwarder7_write["write"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans9["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -364,9 +365,9 @@ ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"] end subgraph InterruptController["interrupt_controller InterruptController"] - InterruptController_mret["mret"] InterruptController_report_interrupt["report_interrupt"] InterruptController_entry["entry"] + InterruptController_mret["mret"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] @@ -377,23 +378,23 @@ CSRRegister_write["write"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_write["_fu_write"] CSRRegister1__fu_read["_fu_read"] + CSRRegister1__fu_write["_fu_write"] CSRRegister1_read["read"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2_write["write"] - CSRRegister2__fu_write["_fu_write"] - CSRRegister2__fu_read["_fu_read"] CSRRegister2_read["read"] + CSRRegister2__fu_read["_fu_read"] + CSRRegister2__fu_write["_fu_write"] + CSRRegister2_write["write"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] - CSRRegister3__fu_read["_fu_read"] CSRRegister3_read["read"] CSRRegister3_write["write"] + CSRRegister3__fu_read["_fu_read"] end subgraph CSRRegister4["register_high CSRRegister"] CSRRegister4__fu_read["_fu_read"] @@ -427,22 +428,22 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO10["alloc_rename_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO11["rename_out_buf FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] end subgraph FIFO12["reg_alloc_out_buf FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -469,20 +470,20 @@ ConnectTrans11_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] - Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] Retirement_Retirement1["Retirement"] + Retirement_core_state["core_state"] + Retirement_Retirement_cond0["Retirement_cond0"] + Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement4["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] - CSRRegister7__fu_read["_fu_read"] CSRRegister7_read["read"] CSRRegister7_write["write"] + CSRRegister7__fu_read["_fu_read"] end subgraph CSRRegister8["register_high CSRRegister"] CSRRegister8_read["read"] @@ -507,61 +508,60 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] - TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] - TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] + TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] + TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] + TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] end end Core_InitFreeRFFifo --> BasicFifo2_write Retirement_Retirement --> BasicFifo2_write - TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write + TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write - Forwarder2_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request + WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write ICache_ICache2 <--> HwCounter4__incr ICache_ICache1 <--> HwCounter3__incr ICache_ICache1 <--> HwCounter2__incr ICache_ICache1 <--> HwCounter1__incr ICache_ICache1 --> Forwarder3_write - ICache_ICache --> SimpleCommonBusCacheRefiller_start_refill - ICache_ICache --> Forwarder2_write - ICache_ICache3 --> Forwarder2_write - SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3 - WishboneMasterAdapter_get_read_response --> ICache_ICache3 - Serializer_Serializer1 --> ICache_ICache3 - BasicFifo_read --> ICache_ICache3 - WishboneMaster_result --> ICache_ICache3 - Forwarder_read --> ICache_ICache3 - Fetch_Fetch1 --> ICache_issue_req - Fetch_Fetch1 <--> HwCounter__incr - Fetch_Fetch1 <--> LatencyMeasurer__start - Fetch_Fetch1 --> FIFO1_write - Fetch_Fetch1 --> FIFO2_write - Fetch_Fetch1 --> BasicFifo3_write - BasicFifo3_read --> Fetch_Fetch - ICache_accept_res --> Fetch_Fetch - FIFO2_read --> Fetch_Fetch - Fetch_Fetch <--> LatencyMeasurer__stop - FIFO1_read --> Fetch_Fetch - Fetch_Fetch --> HwExpHistogram__add - Forwarder3_read --> Fetch_Fetch - Fetch_Fetch --> MethodProduct_method + ICache_ICache3 --> SimpleCommonBusCacheRefiller_start_refill + SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache + Forwarder2_read --> ICache_ICache + Fetch_Fetch --> ICache_issue_req + Fetch_Fetch <--> HwCounter__incr + Fetch_Fetch <--> LatencyMeasurer__start + Fetch_Fetch --> FIFO1_write + Fetch_Fetch --> FIFO2_write + Fetch_Fetch --> BasicFifo3_write + BasicFifo3_read --> Fetch_Fetch1 + ICache_accept_res --> Fetch_Fetch1 + FIFO2_read --> Fetch_Fetch1 + Fetch_Fetch1 <--> LatencyMeasurer__stop + FIFO1_read --> Fetch_Fetch1 + Fetch_Fetch1 --> HwExpHistogram__add + Forwarder3_read --> Fetch_Fetch1 + Fetch_Fetch1 --> MethodProduct_method AdapterTrans_AdapterTrans_method --> MethodProduct_method - Fetch_Fetch --> FIFO_write + Fetch_Fetch1 --> FIFO_write AdapterTrans_AdapterTrans_method --> FIFO_write - Fetch_Fetch --> MethodMap_method + Fetch_Fetch1 --> MethodMap_method AdapterTrans_AdapterTrans_method --> MethodMap_method - Fetch_Fetch <--> CoreInstructionCounter_increment + Fetch_Fetch1 <--> CoreInstructionCounter_increment AdapterTrans_AdapterTrans_method <--> CoreInstructionCounter_increment FIFO_read --> DecodeStage_DecodeStage DecodeStage_DecodeStage <--> HwCounter8__incr @@ -579,17 +579,17 @@ ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write - FIFO12_read --> RSSelection_RSSelection1 - RSSelection_RSSelection1 --> Forwarder8_write + FIFO12_read --> RSSelection_RSSelection2 + RSSelection_RSSelection2 --> Forwarder8_write + Forwarder8_read --> RSSelection_RSSelection1 Forwarder8_read --> RSSelection_RSSelection3 - Forwarder8_read --> RSSelection_RSSelection2 Forwarder8_read --> RSSelection_RSSelection - RSFuncBlock_select --> RSSelection_RSSelection3 - RS_select --> RSSelection_RSSelection3 + RSFuncBlock_select --> RSSelection_RSSelection1 + RS_select --> RSSelection_RSSelection1 + RSSelection_RSSelection1 --> FIFO13_write RSSelection_RSSelection3 --> FIFO13_write - RSSelection_RSSelection2 --> FIFO13_write RSSelection_RSSelection --> FIFO13_write - RSSelection_RSSelection2 <--> LSUDummy_select + RSSelection_RSSelection3 <--> LSUDummy_select RSSelection_RSSelection <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion @@ -606,7 +606,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume - Retirement_Retirement4 --> Fetch_resume + Retirement_Retirement3 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -616,7 +616,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update - RS_RS2 --> WakeupSelect_WakeupSelect + RS_RS3 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -627,7 +627,7 @@ RS_RS4 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write - RS_RS3 --> WakeupSelect2_WakeupSelect + RS_RS2 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -639,10 +639,10 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write - RS_RS --> WakeupSelect3_WakeupSelect + RS_RS1 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write - RS_RS1 --> WakeupSelect4_WakeupSelect + RS_RS --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -661,11 +661,11 @@ CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write LSUDummy_LSUDummy --> Forwarder6_write + TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write - TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write - TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write - TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write - TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write + TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write + TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write + TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -695,37 +695,37 @@ ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans - ReorderBuffer_peek --> Retirement_Retirement2 - ReorderBuffer_peek --> Retirement_Retirement3 + ReorderBuffer_peek --> Retirement_Retirement4 + ReorderBuffer_peek --> Retirement_Retirement1 ReorderBuffer_peek --> Retirement_Retirement - ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement2 --> MethodTryProduct_method - ExceptionCauseRegister_get --> Retirement_Retirement3 - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement4 --> MethodTryProduct_method + ExceptionCauseRegister_get --> Retirement_Retirement1 + ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 Retirement_Retirement <--> ReorderBuffer_retire - TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire + TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire Retirement_Retirement <--> LatencyMeasurer1__stop - TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop FIFO3_read --> Retirement_Retirement - FIFO3_read --> TransactionManager_Retirement_cond0_Retirement + FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 Retirement_Retirement --> HwExpHistogram1__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add CoreInstructionCounter_decrement --> Retirement_Retirement - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 RRAT_peek --> Retirement_Retirement RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 Retirement_Retirement --> RegisterFile_free - TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free + TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free - CSRRegister1_read --> Retirement_Retirement4 - Retirement_Retirement4 <--> ExceptionCauseRegister_clear + CSRRegister1_read --> Retirement_Retirement3 + Retirement_Retirement3 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -737,53 +737,53 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt + TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy + Serializer1_Serializer2 --> TransactionManager_accept_cond1_LSUDummy + BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy + BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy + WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy + WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy + Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy + Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy + TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy2 + TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy2 + LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy + LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write - TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer + TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer1 TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write + TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request - TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request + TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 - TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy1 - TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_cond0_Retirement --> RRAT_commit - TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment - CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write - CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write - TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement1 - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1 - TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write + TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 + TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 + TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read + TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2 + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement2 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write - TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit + TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment + CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write + CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr + TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy + Serializer1_Serializer3 --> TransactionManager_accept_cond0_LSUDummy TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 - TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 - TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read - TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer3 - TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2 - TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy2 - LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 - LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 - TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 - Serializer1_Serializer1 --> TransactionManager_LSUDummy_accept_cond0 - BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 - BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 - WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 - WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 - Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 - Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 - TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 - TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 - Serializer1_Serializer2 --> TransactionManager_LSUDummy_accept_cond1 diff --git a/api.html b/api.html index 1ec2633bd..8ab3aed4b 100644 --- a/api.html +++ b/api.html @@ -259,7 +259,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/assumptions.html b/assumptions.html index 5d9fa255d..46da0f858 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/auto_graph.html b/auto_graph.html index 8052d5f8d..bd241f8d2 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -86,12 +86,12 @@ Core_DiscardBranchVerify["DiscardBranchVerify"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_WishboneMaster["WishboneMaster"] - WishboneMaster_request["request"] WishboneMaster_result["result"] + WishboneMaster_request["request"] + WishboneMaster_WishboneMaster["WishboneMaster"] subgraph Forwarder["result Forwarder"] - Forwarder_read["read"] Forwarder_write["write"] + Forwarder_read["read"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] @@ -104,40 +104,40 @@ end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] + WishboneMasterAdapter1_request_read["request_read"] WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_get_write_response["get_write_response"] - WishboneMasterAdapter1_request_read["request_read"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_write["write"] BasicFifo1_read["read"] + BasicFifo1_write["write"] end end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph FIFO["fifo_fetch FIFO"] - FIFO_read["read"] FIFO_write["write"] + FIFO_read["read"] end subgraph MethodMap["core_counter_increment_discard_map MethodMap"] MethodMap_method["method"] @@ -146,14 +146,15 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] - subgraph Forwarder2["address_fwd Forwarder"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] + subgraph Forwarder2["resp_fwd Forwarder"] Forwarder2_read["read"] Forwarder2_write["write"] end @@ -161,10 +162,10 @@ subgraph ICache["icache ICache"] ICache_ICache["ICache"] ICache_ICache1["ICache"] - ICache_ICache2["ICache"] ICache_accept_res["accept_res"] - ICache_ICache3["ICache"] ICache_issue_req["issue_req"] + ICache_ICache2["ICache"] + ICache_ICache3["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -181,8 +182,8 @@ HwCounter4__incr["_incr"] end subgraph LatencyMeasurer["req_latency LatencyMeasurer"] - LatencyMeasurer__start["_start"] LatencyMeasurer__stop["_stop"] + LatencyMeasurer__start["_start"] subgraph HwExpHistogram["histogram HwExpHistogram"] HwExpHistogram__add["_add"] end @@ -196,16 +197,16 @@ FIFO2_read["read"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_peek["peek"] RRAT_commit["commit"] + RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] RegisterFile_read1["read1"] @@ -214,14 +215,14 @@ RegisterFile_free["free"] end subgraph ReorderBuffer["ROB ReorderBuffer"] + ReorderBuffer_put["put"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_peek["peek"] ReorderBuffer_retire["retire"] - ReorderBuffer_put["put"] - ReorderBuffer_get_indices["get_indices"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] - LatencyMeasurer1__start["_start"] LatencyMeasurer1__stop["_stop"] + LatencyMeasurer1__start["_start"] subgraph HwExpHistogram1["histogram HwExpHistogram"] HwExpHistogram1__add["_add"] end @@ -233,8 +234,8 @@ end subgraph Fetch["fetch Fetch"] Fetch_Fetch["Fetch"] - Fetch_Fetch1["Fetch"] Fetch_resume["resume"] + Fetch_Fetch1["Fetch"] Fetch_stall_exception["stall_exception"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] BasicFifo3_read["read"] @@ -242,12 +243,12 @@ end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] + ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] ExceptionCauseRegister_clear["clear"] - ExceptionCauseRegister_report["report"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] - BasicFifo4_read["read"] BasicFifo4_write["write"] + BasicFifo4_read["read"] end subgraph ConnectTrans["report_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -257,8 +258,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_read["read"] Forwarder4_write["write"] + Forwarder4_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -276,27 +277,27 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_insert["insert"] RSFuncBlock_select["select"] RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] + RSFuncBlock_insert["insert"] subgraph RS["rs RS"] - RS_update["update"] RS_RS["RS"] + RS_update["update"] + RS_take["take"] RS_RS1["RS"] - RS_select["select"] RS_RS2["RS"] + RS_select["select"] RS_RS3["RS"] - RS_take["take"] - RS_insert["insert"] RS_RS4["RS"] + RS_insert["insert"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] subgraph FIFO4["fifo FIFO"] - FIFO4_read["read"] FIFO4_write["write"] + FIFO4_read["read"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] @@ -330,28 +331,28 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_write["write"] FIFO7_read["read"] + FIFO7_write["write"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] + ExceptionFuncUnit_issue["issue"] subgraph FIFO8["fifo FIFO"] - FIFO8_write["write"] FIFO8_read["read"] + FIFO8_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] + PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_precommit["precommit"] - PrivilegedFuncUnit_issue["issue"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] BasicFifo5_write["write"] BasicFifo5_read["read"] @@ -386,36 +387,36 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_select["select"] - LSUDummy_update["update"] LSUDummy_LSUDummy["LSUDummy"] LSUDummy_precommit["precommit"] LSUDummy_get_result["get_result"] LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_insert["insert"] + LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_select["select"] + LSUDummy_update["update"] subgraph Forwarder6["forwarder Forwarder"] - Forwarder6_read["read"] Forwarder6_write["write"] + Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_issue["issue"] - LSURequester_accept_cond0["accept_cond0"] - LSURequester_issue_cond1["issue_cond1"] - LSURequester_accept["accept"] - LSURequester_issue_cond2["issue_cond2"] LSURequester_accept_cond1["accept_cond1"] LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue_cond2["issue_cond2"] + LSURequester_issue["issue"] + LSURequester_accept["accept"] + LSURequester_issue_cond1["issue_cond1"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_insert["insert"] - CSRUnit_CSRUnit["CSRUnit"] - CSRUnit_fetch_resume["fetch_resume"] CSRUnit_select["select"] CSRUnit_update["update"] CSRUnit_precommit["precommit"] CSRUnit_get_result["get_result"] + CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_insert["insert"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] @@ -426,8 +427,8 @@ subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_write["write"] Forwarder7_read["read"] + Forwarder7_write["write"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans9["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -443,9 +444,9 @@ ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"] end subgraph InterruptController["interrupt_controller InterruptController"] - InterruptController_mret["mret"] InterruptController_report_interrupt["report_interrupt"] InterruptController_entry["entry"] + InterruptController_mret["mret"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] @@ -456,23 +457,23 @@ CSRRegister_write["write"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_write["_fu_write"] CSRRegister1__fu_read["_fu_read"] + CSRRegister1__fu_write["_fu_write"] CSRRegister1_read["read"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2_write["write"] - CSRRegister2__fu_write["_fu_write"] - CSRRegister2__fu_read["_fu_read"] CSRRegister2_read["read"] + CSRRegister2__fu_read["_fu_read"] + CSRRegister2__fu_write["_fu_write"] + CSRRegister2_write["write"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] - CSRRegister3__fu_read["_fu_read"] CSRRegister3_read["read"] CSRRegister3_write["write"] + CSRRegister3__fu_read["_fu_read"] end subgraph CSRRegister4["register_high CSRRegister"] CSRRegister4__fu_read["_fu_read"] @@ -506,22 +507,22 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO10["alloc_rename_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO11["rename_out_buf FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] end subgraph FIFO12["reg_alloc_out_buf FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -548,20 +549,20 @@ ConnectTrans11_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] - Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] Retirement_Retirement1["Retirement"] + Retirement_core_state["core_state"] + Retirement_Retirement_cond0["Retirement_cond0"] + Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement4["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] - CSRRegister7__fu_read["_fu_read"] CSRRegister7_read["read"] CSRRegister7_write["write"] + CSRRegister7__fu_read["_fu_read"] end subgraph CSRRegister8["register_high CSRRegister"] CSRRegister8_read["read"] @@ -586,61 +587,60 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] - TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] - TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] + TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] + TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] + TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] end end Core_InitFreeRFFifo --> BasicFifo2_write Retirement_Retirement --> BasicFifo2_write -TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write +TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write -Forwarder2_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request +WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write ICache_ICache2 <--> HwCounter4__incr ICache_ICache1 <--> HwCounter3__incr ICache_ICache1 <--> HwCounter2__incr ICache_ICache1 <--> HwCounter1__incr ICache_ICache1 --> Forwarder3_write -ICache_ICache --> SimpleCommonBusCacheRefiller_start_refill -ICache_ICache --> Forwarder2_write -ICache_ICache3 --> Forwarder2_write -SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3 -WishboneMasterAdapter_get_read_response --> ICache_ICache3 -Serializer_Serializer1 --> ICache_ICache3 -BasicFifo_read --> ICache_ICache3 -WishboneMaster_result --> ICache_ICache3 -Forwarder_read --> ICache_ICache3 -Fetch_Fetch1 --> ICache_issue_req -Fetch_Fetch1 <--> HwCounter__incr -Fetch_Fetch1 <--> LatencyMeasurer__start -Fetch_Fetch1 --> FIFO1_write -Fetch_Fetch1 --> FIFO2_write -Fetch_Fetch1 --> BasicFifo3_write -BasicFifo3_read --> Fetch_Fetch -ICache_accept_res --> Fetch_Fetch -FIFO2_read --> Fetch_Fetch -Fetch_Fetch <--> LatencyMeasurer__stop -FIFO1_read --> Fetch_Fetch -Fetch_Fetch --> HwExpHistogram__add -Forwarder3_read --> Fetch_Fetch -Fetch_Fetch --> MethodProduct_method +ICache_ICache3 --> SimpleCommonBusCacheRefiller_start_refill +SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache +Forwarder2_read --> ICache_ICache +Fetch_Fetch --> ICache_issue_req +Fetch_Fetch <--> HwCounter__incr +Fetch_Fetch <--> LatencyMeasurer__start +Fetch_Fetch --> FIFO1_write +Fetch_Fetch --> FIFO2_write +Fetch_Fetch --> BasicFifo3_write +BasicFifo3_read --> Fetch_Fetch1 +ICache_accept_res --> Fetch_Fetch1 +FIFO2_read --> Fetch_Fetch1 +Fetch_Fetch1 <--> LatencyMeasurer__stop +FIFO1_read --> Fetch_Fetch1 +Fetch_Fetch1 --> HwExpHistogram__add +Forwarder3_read --> Fetch_Fetch1 +Fetch_Fetch1 --> MethodProduct_method AdapterTrans_AdapterTrans_method --> MethodProduct_method -Fetch_Fetch --> FIFO_write +Fetch_Fetch1 --> FIFO_write AdapterTrans_AdapterTrans_method --> FIFO_write -Fetch_Fetch --> MethodMap_method +Fetch_Fetch1 --> MethodMap_method AdapterTrans_AdapterTrans_method --> MethodMap_method -Fetch_Fetch <--> CoreInstructionCounter_increment +Fetch_Fetch1 <--> CoreInstructionCounter_increment AdapterTrans_AdapterTrans_method <--> CoreInstructionCounter_increment FIFO_read --> DecodeStage_DecodeStage DecodeStage_DecodeStage <--> HwCounter8__incr @@ -658,17 +658,17 @@ ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write -FIFO12_read --> RSSelection_RSSelection1 -RSSelection_RSSelection1 --> Forwarder8_write +FIFO12_read --> RSSelection_RSSelection2 +RSSelection_RSSelection2 --> Forwarder8_write +Forwarder8_read --> RSSelection_RSSelection1 Forwarder8_read --> RSSelection_RSSelection3 -Forwarder8_read --> RSSelection_RSSelection2 Forwarder8_read --> RSSelection_RSSelection -RSFuncBlock_select --> RSSelection_RSSelection3 -RS_select --> RSSelection_RSSelection3 +RSFuncBlock_select --> RSSelection_RSSelection1 +RS_select --> RSSelection_RSSelection1 +RSSelection_RSSelection1 --> FIFO13_write RSSelection_RSSelection3 --> FIFO13_write -RSSelection_RSSelection2 --> FIFO13_write RSSelection_RSSelection --> FIFO13_write -RSSelection_RSSelection2 <--> LSUDummy_select +RSSelection_RSSelection3 <--> LSUDummy_select RSSelection_RSSelection <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion @@ -685,7 +685,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume -Retirement_Retirement4 --> Fetch_resume +Retirement_Retirement3 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -695,7 +695,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update -RS_RS2 --> WakeupSelect_WakeupSelect +RS_RS3 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -706,7 +706,7 @@ RS_RS4 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write -RS_RS3 --> WakeupSelect2_WakeupSelect +RS_RS2 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -718,10 +718,10 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write -RS_RS --> WakeupSelect3_WakeupSelect +RS_RS1 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write -RS_RS1 --> WakeupSelect4_WakeupSelect +RS_RS --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -740,11 +740,11 @@ CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write LSUDummy_LSUDummy --> Forwarder6_write +TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write -TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write -TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write -TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write -TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write +TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write +TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write +TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -774,37 +774,37 @@ ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans -ReorderBuffer_peek --> Retirement_Retirement2 -ReorderBuffer_peek --> Retirement_Retirement3 +ReorderBuffer_peek --> Retirement_Retirement4 +ReorderBuffer_peek --> Retirement_Retirement1 ReorderBuffer_peek --> Retirement_Retirement -ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement2 --> MethodTryProduct_method -ExceptionCauseRegister_get --> Retirement_Retirement3 -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement +Retirement_Retirement4 --> MethodTryProduct_method +ExceptionCauseRegister_get --> Retirement_Retirement1 +ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 Retirement_Retirement <--> ReorderBuffer_retire -TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire +TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire Retirement_Retirement <--> LatencyMeasurer1__stop -TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop FIFO3_read --> Retirement_Retirement -FIFO3_read --> TransactionManager_Retirement_cond0_Retirement +FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 Retirement_Retirement --> HwExpHistogram1__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add CoreInstructionCounter_decrement --> Retirement_Retirement -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 RRAT_peek --> Retirement_Retirement RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 Retirement_Retirement --> RegisterFile_free -TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free +TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free -CSRRegister1_read --> Retirement_Retirement4 -Retirement_Retirement4 <--> ExceptionCauseRegister_clear +CSRRegister1_read --> Retirement_Retirement3 +Retirement_Retirement3 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -816,56 +816,56 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt +TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy +Serializer1_Serializer2 --> TransactionManager_accept_cond1_LSUDummy +BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy +BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy +WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy +WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy +Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy +Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy +TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy2 +TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy2 +LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy +LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write -TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer +TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer1 TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write -TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write +TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request -TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request +TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 -TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy1 -TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_cond0_Retirement --> RRAT_commit -TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment -CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write -CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write -TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement1 -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1 -TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write +TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 +TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 +TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read +TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2 +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement2 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write -TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit +TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment +CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write +CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr +TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy +Serializer1_Serializer3 --> TransactionManager_accept_cond0_LSUDummy TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 -TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 -TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read -TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer3 -TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2 -TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy2 -LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 -LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 -TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 -Serializer1_Serializer1 --> TransactionManager_LSUDummy_accept_cond0 -BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 -BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 -WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 -WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 -Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 -Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 -TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 -TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 -Serializer1_Serializer2 --> TransactionManager_LSUDummy_accept_cond1 @@ -876,7 +876,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/components/icache.html b/components/icache.html index ac317507a..4a49c5544 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.backend.html b/coreblocks.backend.html index 06f0df0e7..97783cc64 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -165,7 +165,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index 0ac546a51..b830418b3 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -98,10 +98,10 @@

Submodules
__init__(layouts: ICacheLayouts, params: ICacheParameters, refiller: CacheRefillerInterface) → None
@@ -192,7 +192,7 @@

Submodules
start_refillMethod

A method that is used to start a refill for a given cache line.

-
accept_refillMethod

A method that is used to accept one word from the requested cache line.

+
accept_refillMethod

A method that is used to accept one fetch block from the requested cache line.

@@ -241,7 +241,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index 0d9a38f8d..ec3cae5c2 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -157,7 +157,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index e7dfe04c2..0bf181124 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -1721,7 +1721,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index 9a495fcb5..15d16af82 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -161,7 +161,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 95cd0b698..cc3d008ad 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -125,7 +125,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index d9d9c50f6..269d7481f 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -867,7 +867,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index 257d81169..49ae16f3b 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -238,7 +238,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index 51741f02d..30f4c48f1 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -148,7 +148,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index b48dee4c0..f3cabe485 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -169,7 +169,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.func_blocks.lsu.html b/coreblocks.func_blocks.lsu.html index 1b052dee5..3fe2759f1 100644 --- a/coreblocks.func_blocks.lsu.html +++ b/coreblocks.func_blocks.lsu.html @@ -248,7 +248,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.html b/coreblocks.html index b42f87fc2..db9ee097d 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -255,7 +255,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.params.html b/coreblocks.params.html index 157f79dbe..693db6b54 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -120,7 +120,9 @@

Submodules
-__init__(*, xlen: int = 32, func_units_config: ~collections.abc.Collection[~coreblocks.params.fu_params.BlockComponentParams] = (RSBlockComponent(func_units=[<coreblocks.func_blocks.fu.alu.ALUComponent object>, <coreblocks.func_blocks.fu.shift_unit.ShiftUnitComponent object>, <coreblocks.func_blocks.fu.jumpbranch.JumpComponent object>, <coreblocks.func_blocks.fu.exception.ExceptionUnitComponent object>, <coreblocks.func_blocks.fu.priv.PrivilegedUnitComponent object>], rs_entries=4), <coreblocks.func_blocks.lsu.dummyLsu.LSUBlockComponent object>, <coreblocks.func_blocks.csr.csr.CSRBlockComponent object>), compressed: bool = False, embedded: bool = False, debug_signals: bool = True, phys_regs_bits: int = 6, rob_entries_bits: int = 7, start_pc: int = 0, icache_enable: bool = True, icache_ways: int = 2, icache_sets_bits: int = 7, icache_block_size_bits: int = 5, allow_partial_extensions: bool = False, _implied_extensions: ~coreblocks.params.isa_params.Extension = Extension.None, pma: list[coreblocks.func_blocks.lsu.pma.PMARegion] = <factory>) → None
+__init__(*, xlen: int = 32, func_units_config: ~collections.abc.Collection[~coreblocks.params.fu_params.BlockComponentParams] = (RSBlockComponent(func_units=[<coreblocks.func_blocks.fu.alu.ALUComponent object>, <coreblocks.func_blocks.fu.shift_unit.ShiftUnitComponent object>, <coreblocks.func_blocks.fu.jumpbranch.JumpComponent object>, <coreblocks.func_blocks.fu.exception.ExceptionUnitComponent object>, <coreblocks.func_blocks.fu.priv.PrivilegedUnitComponent object>], rs_entries=4), <coreblocks.func_blocks.lsu.dummyLsu.LSUBlockComponent object>, <coreblocks.func_blocks.csr.csr.CSRBlockComponent object>), compressed: bool = False, embedded: bool = False, debug_signals: bool = True, phys_regs_bits: int = 6, rob_entries_bits: int = 7, start_pc: int = 0, icache_enable: bool = True, icache_ways: int = 2, icache_sets_bits: int = 7, icache_line_bytes_log: int = 5, fetch_block_bytes_log: int = 2, allow_partial_extensions: bool = False, _implied_extensions: ~coreblocks.params.isa_params.Extension = Extension.None, pma: list[coreblocks.func_blocks.lsu.pma.PMARegion] = <factory>) → None
@@ -157,13 +159,13 @@

Submodules -
-func_units_config: Collection[BlockComponentParams] = (RSBlockComponent(func_units=[<coreblocks.func_blocks.fu.alu.ALUComponent object>, <coreblocks.func_blocks.fu.shift_unit.ShiftUnitComponent object>, <coreblocks.func_blocks.fu.jumpbranch.JumpComponent object>, <coreblocks.func_blocks.fu.exception.ExceptionUnitComponent object>, <coreblocks.func_blocks.fu.priv.PrivilegedUnitComponent object>], rs_entries=4), <coreblocks.func_blocks.lsu.dummyLsu.LSUBlockComponent object>, <coreblocks.func_blocks.csr.csr.CSRBlockComponent object>)
+
+fetch_block_bytes_log: int = 2

-
-icache_block_size_bits: int = 5
+
+func_units_config: Collection[BlockComponentParams] = (RSBlockComponent(func_units=[<coreblocks.func_blocks.fu.alu.ALUComponent object>, <coreblocks.func_blocks.fu.shift_unit.ShiftUnitComponent object>, <coreblocks.func_blocks.fu.jumpbranch.JumpComponent object>, <coreblocks.func_blocks.fu.exception.ExceptionUnitComponent object>, <coreblocks.func_blocks.fu.priv.PrivilegedUnitComponent object>], rs_entries=4), <coreblocks.func_blocks.lsu.dummyLsu.LSUBlockComponent object>, <coreblocks.func_blocks.csr.csr.CSRBlockComponent object>)
@@ -171,6 +173,11 @@

Submodulesicache_enable: bool = True

+
+
+icache_line_bytes_log: int = 5
+
+
icache_sets_bits: int = 7
@@ -291,7 +298,7 @@

Submodulesint

Log of the number of cache sets.

-
block_size_bitsint

Log of the size of a single cache block in bytes.

+
line_bytes_logint

Log of the size of a single cache line in bytes.

enablebool

Enable the instruction cache. If disabled, requestes are bypassed to the bus.

@@ -300,7 +307,7 @@

Submodules
-__init__(*, addr_width, word_width, num_of_ways, num_of_sets_bits, block_size_bits, enable=True)
+__init__(*, addr_width, word_width, fetch_block_bytes_log, num_of_ways, num_of_sets_bits, line_bytes_log, enable=True)

@@ -754,7 +761,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index 4fcfee8e8..728532bee 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -746,7 +746,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html index 01a657398..af2333f5b 100644 --- a/coreblocks.priv.csr.html +++ b/coreblocks.priv.csr.html @@ -327,7 +327,7 @@

Submodules

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diff --git a/coreblocks.priv.html b/coreblocks.priv.html index 7a8cd4f99..6b8207fad 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -123,7 +123,7 @@

Subpackages

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diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index 06f5871d9..5faa0d2e3 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -171,7 +171,7 @@

Submodules

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diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 78d55ae6f..84a18b3cc 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

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diff --git a/current-graph.html b/current-graph.html index ba6956829..bc0e1328f 100644 --- a/current-graph.html +++ b/current-graph.html @@ -92,12 +92,12 @@

Full transaction-method graph

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diff --git a/development-environment.html b/development-environment.html index c40b811d6..32e3ec008 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

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diff --git a/genindex.html b/genindex.html index 9fce309da..abcead821 100644 --- a/genindex.html +++ b/genindex.html @@ -1593,6 +1593,8 @@

F

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  • Fetch (class in coreblocks.frontend.fetch.fetch) +
    • +
  • fetch_block_bytes_log (coreblocks.params.configurations.CoreConfiguration attribute)
  • fields (transactron.lib.logging.LogRecord attribute)
    • @@ -1865,10 +1867,10 @@

    I

  • ICache (class in coreblocks.cache.icache) -
    • -
  • icache_block_size_bits (coreblocks.params.configurations.CoreConfiguration attribute)
  • icache_enable (coreblocks.params.configurations.CoreConfiguration attribute) +
    • +
  • icache_line_bytes_log (coreblocks.params.configurations.CoreConfiguration attribute)
  • icache_sets_bits (coreblocks.params.configurations.CoreConfiguration attribute)
    • @@ -3755,7 +3757,7 @@

    Z

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    diff --git a/home.html b/home.html index 4acda82f8..787f9c3fc 100644 --- a/home.html +++ b/home.html @@ -129,7 +129,7 @@

    Documentation

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    diff --git a/index.html b/index.html index 4fb282ef5..9ce77deed 100644 --- a/index.html +++ b/index.html @@ -229,7 +229,7 @@

    Coreblocks

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    diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html index f53ea3e05..cba86e40f 100644 --- a/miscellany/exceptions-summary.html +++ b/miscellany/exceptions-summary.html @@ -271,7 +271,7 @@

    Summary

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    diff --git a/modules-coreblocks.html b/modules-coreblocks.html index ff5d7ab16..4435944c8 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -168,7 +168,7 @@

    coreblocks

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    diff --git a/modules-transactron.html b/modules-transactron.html index 2faebcaf1..e5332c1c5 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -161,7 +161,7 @@

    transactron

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    diff --git a/objects.inv b/objects.inv index 2424575e4..b4da70600 100644 Binary files a/objects.inv and b/objects.inv differ diff --git a/problem-checklist.html b/problem-checklist.html index 38456e29c..293601f11 100644 --- a/problem-checklist.html +++ b/problem-checklist.html @@ -105,7 +105,7 @@

    Problem checklist

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    diff --git a/py-modindex.html b/py-modindex.html index eb9813b16..a5ea369db 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -668,7 +668,7 @@

    Python Module Index

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    diff --git a/scheduler/overview.html b/scheduler/overview.html index a448d98aa..6d978c3ff 100644 --- a/scheduler/overview.html +++ b/scheduler/overview.html @@ -146,7 +146,7 @@

    More detailed description of each block

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    diff --git a/search.html b/search.html index 055ef4c33..85936d231 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 15:57 2024-03-27. + Last updated on 10:11 2024-03-31.

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19, 20, 21, 34, 36, 37, 38, 39, 40], "instanc": [5, 6, 9, 10, 15, 21, 33, 35, 36, 37, 38, 39], "us": [5, 6, 9, 10, 12, 13, 15, 16, 17, 19, 20, 21, 25, 26, 29, 33, 34, 36, 37, 38, 39, 40], "gener": [5, 6, 9, 10, 12, 13, 15, 16, 17, 19, 21, 23, 24, 26, 29, 33, 35, 36, 37, 38, 39], "next": [5, 6, 9, 10, 15, 21, 26, 36, 40], "readi": [5, 6, 15, 17, 19, 21, 25, 31, 35, 36, 37], "assum": [5, 12, 26, 37, 39], "differ": [5, 12, 17, 23, 24, 26, 29, 33, 36, 37, 39], "end": [5, 15, 26, 36, 37], "without": [5, 21, 26, 36, 37, 39], "pass": [5, 23, 25, 33, 36, 37, 38, 39], "finish": [5, 17, 20, 37], "rob_peek": 5, "rob_retir": 5, "r_rat_commit": 5, "r_rat_peek": 5, "free_rf_put": 5, "rf_free": 5, "precommit": [5, 15, 23], "exception_cause_get": 5, "exception_cause_clear": 5, "frat_renam": 5, "fetch_continu": 5, "instr_decr": 5, "trap_entri": 5, "cacheinterfac": [6, 10], "A": [6, 16, 17, 33, 34, 35, 36, 37, 39], "associ": [6, 16, 37], "replac": [6, 13, 16, 31], "polici": 6, "pseudo": 6, "random": [6, 38], "scheme": 6, "everi": [6, 12, 17, 23, 33, 36, 37], "time": [6, 17, 19, 26, 36, 37], "trash": 6, "select": [6, 9, 12, 14, 15, 17, 21, 23], "wai": [6, 12, 17, 23, 26, 33, 34, 36, 37, 39], "keep": [6, 36], "global": [6, 19, 26], "counter": [6, 16, 19, 20, 23, 37], "abstract": [6, 13, 16, 33, 37, 39], "awai": 6, "need": [6, 17, 23, 26, 31, 34, 36], "two": [6, 19, 26, 29, 33, 34, 36, 37, 38, 39], "refiller_start": 6, "call": [6, 19, 20, 21, 23, 29, 31, 34, 35, 36, 37, 38, 39], "whenev": [6, 37], "refiller_accept": 6, "word": [6, 16], "written": [6, 19, 32, 33, 37], "last": [6, 20, 21, 36, 37], "when": [6, 17, 20, 23, 26, 29, 31, 32, 34, 36, 37, 38, 39, 40], "either": [6, 17, 34, 36, 37, 38, 39, 40], "transfer": [6, 17, 36, 37], "over": [6, 19, 36, 37], "shouldn": [6, 33], "t": [6, 9, 15, 16, 23, 26, 29, 31, 33, 34, 36, 37, 38, 39], "until": [6, 26, 37], "start": [6, 12, 15, 17, 26, 36, 37], "layout": [6, 9, 10, 17, 21, 23, 29, 34, 36, 37, 39], "icachelayout": 6, "icacheparamet": [6, 16], "cacherefillerinterfac": 6, "none": [6, 7, 9, 10, 12, 15, 16, 19, 35, 36, 37, 38, 39, 40], "creat": [6, 13, 17, 23, 33, 34, 36, 37, 38, 39, 40], "input": [6, 9, 12, 17, 26, 31, 32, 34, 36, 37, 40], "start_refil": 6, "accept_refil": 6, "deserialize_addr": 6, "raw_addr": 6, "dict": [6, 17, 34, 35, 36, 37, 38, 39, 40], "str": [6, 16, 17, 35, 36, 37, 38, 39, 40], "amaranth": [6, 9, 12, 16, 17, 29, 33, 34, 35, 36, 37, 38, 39, 40], "hdl": [6, 9, 12, 16, 35, 36, 37, 38, 39, 40], "_ast": [6, 9, 12, 16, 36, 37, 38, 39, 40], "serialize_addr": 6, "addr": [6, 15, 17, 37], "view": [6, 12, 15, 36, 37, 38, 39, 40], "icachebypass": 6, "bus_mast": 6, "busmasterinterfac": [6, 15, 17], "haselabor": [6, 14, 17, 35, 36, 37, 38, 40], "protocol": [6, 14, 17, 35, 36, 37], "whole": [6, 24, 26, 37], "given": [6, 15, 23, 31, 34, 35, 36, 37, 38, 39, 40], "simplecommonbuscacherefil": 6, "frat": 7, "rrat": 7, "registerfil": 7, "reorderbuff": [7, 20], "decodestag": 9, "instanti": [9, 36], "instrdecod": 9, "make": [9, 12, 23, 24, 26, 29, 33, 34, 35, 38], "actual": [9, 23, 25, 34], "combinatori": [9, 34], "manner": [9, 17], "get_raw": 9, "push_decod": 9, "raw": 9, "previou": [9, 17, 26, 37], "step": [9, 10, 21, 23, 26, 33, 34], "e": [9, 16, 23, 26, 29, 34, 37, 39, 40], "g": [9, 16, 23, 26, 29, 34, 37, 39, 40], "fetchlayout": [9, 10], "describ": [9, 10, 21, 26, 33, 35, 36, 37, 38], "decodelayout": [9, 21], "perform": [9, 12, 13, 16, 21, 23, 33, 34, 36, 37, 39, 40], "elementari": 9, "compon": [9, 16, 17, 24, 36, 37], "opcod": [9, 16, 31, 32], "funct3": [9, 12, 16], "etc": [9, 16, 34], "via": [9, 34, 36], "attribut": [9, 12, 13, 15, 16, 17, 19, 20, 35, 36, 37, 39, 40], "signal": [9, 12, 15, 16, 17, 25, 29, 35, 36, 37, 38, 39, 40], "ilen": [9, 16], "out": [9, 12, 13, 17, 24, 25, 35, 36, 37, 40], "identifi": [9, 16, 31, 37], "funct3_v": 9, "1": [9, 12, 13, 16, 19, 21, 26, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40], "funct7": [9, 12, 16], "seven": 9, "funct7_v": 9, "funct12": 9, "twelv": 9, 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"constructor": [9, 34, 36, 39], "encod": [9, 16, 26, 35, 39, 40], "object": [9, 12, 15, 16, 17, 33, 34, 35, 37, 38, 39], "repres": [9, 19, 36, 37], "singl": [9, 12, 13, 16, 20, 21, 34, 36, 37, 39], "option": [9, 12, 16, 17, 19, 23, 34, 35, 36, 37, 38, 39, 40], "exist": [9, 34], "instr_type_overrid": 9, "instrtyp": 9, "specifi": [9, 16, 17, 19, 32, 37, 38, 39], "determin": [9, 26, 33, 37, 39], "instrust": 9, "almost": 9, "correct": [9, 15, 26, 31, 32, 33], "rd_zero": 9, "bool": [9, 15, 16, 19, 35, 36, 37, 38, 39, 40], "field": [9, 15, 16, 19, 23, 31, 32, 34, 35, 36, 37, 38, 39], "constant": 9, "zero": [9, 20, 31, 37, 40], "other": [9, 19, 23, 25, 34, 35, 36, 37, 40], "accordingli": 9, "default": [9, 17, 23, 34, 35, 36, 37, 39, 40], "fals": [9, 12, 15, 16, 23, 34, 35, 36, 37, 39, 40], "rs1_zero": 9, "exceptioncaus": 9, "intenum": [9, 12, 19], "breakpoint": 9, "3": [9, 12, 19, 23, 35, 36, 39], "environment_call_from_m": 9, "environment_call_from_": 9, "9": 9, "environment_call_from_u": 9, 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16, "4194304": 16, "half": 16, "zfhmin": 16, "8388608": 16, "minim": 16, "zfinx": 16, "16777216": 16, "zhinx": 16, "67108864": 16, "zicntr": 16, "524288": 16, "timer": [16, 19], "zicsr": 16, "32768": 16, "statu": [16, 19, 38], "zifencei": 16, "65536": 16, "zihintntl": 16, "262144": 16, "non": [16, 31, 36, 37, 38], "tempor": 16, "local": [16, 20, 23], "hint": [16, 36], "zihintpaus": 16, "131072": 16, "paus": 16, "energi": 16, "zihpm": 16, "1048576": 16, "zmmul": 16, "134217728": 16, "ztso": 16, "4294967296": 16, "total": 16, "gather": 16, "numer": 16, "val": [16, 39], "correspond": [16, 31, 36, 40], "val_log": 16, "relev": [16, 35], "nativ": 16, "reg_cnt": 16, "maximum": [16, 33, 37], "bitwis": 16, "isa_str": 16, "string": [16, 37, 38], "pleas": [16, 23, 29, 34], "refer": [16, 35, 39], "gcc": 16, "arch": [16, 23, 33], "detail": [16, 20, 25, 37], "axiliteinterfac": 17, "abstractinterfac": 17, "abstractsignatur": 17, "read_address": 17, "axilitereadaddressinterfac": 17, "read_data": 17, "axilitereaddatainterfac": 17, "write_address": 17, "axilitewriteaddressinterfac": 17, "write_data": 17, "axilitewritedatainterfac": 17, "write_respons": 17, "axilitewriteresponseinterfac": 17, "axilitemast": 17, "axi": 17, "lite": 17, "axil_param": 17, "axiliteparamet": 17, "ra_request": 17, "channel": 17, "being": [17, 23, 37, 39, 40], "ra_request_layout": 17, "argument": [17, 21, 23, 25, 32, 33, 36, 37, 38, 39, 40], "rd_respons": 17, "availab": 17, "state": [17, 25, 26, 34, 36, 37, 38], "rd_response_layout": 17, "wa_request": 17, "wa_request_layout": 17, "wd_request": 17, "wd_request_layout": 17, "wr_respons": 17, "wr_response_layout": 17, "axil_mast": 17, "result_handl": 17, "start_request_transact": 17, "is_address_channel": 17, "state_machine_request": 17, "request_sign": 17, "data_width": 17, "must": [17, 36, 37, 39], "axilitesignatur": 17, "signatur": 17, "patamet": 17, "axilitemasteradapt": 17, "where": [17, 21, 23, 26, 31, 32, 34, 36, 37, 38, 39], "expect": 17, "busparametersinterfac": 17, "method_layout": 17, "commonbusmastermethodlayout": 17, "request_read": 17, "underli": 17, "request_read_layout": 17, "request_writ": 17, "request_write_layout": 17, "get_read_respons": 17, "action": [17, 19, 36, 37, 39], "read_response_layout": 17, "get_write_respons": 17, "write_response_layout": 17, "prefer": [17, 34], "gain": 17, "simplifi": 17, "interchang": 17, "buse": 17, "previous": 17, "wishbonemasteradapt": 17, "wishbonemast": 17, "pipelinedwishbonemast": 17, "wb_param": 17, "wishboneparamet": 17, "max_req": 17, "limit": [17, 34, 37], "pend": 17, "wb": 17, "request_layout": 17, "result_layout": 17, "requests_finish": 17, "generate_method_layout": 17, "wishbonearbit": 17, "arbit": 17, "slave": 17, "assert": [17, 37, 40], "cyc": 17, "grant": [17, 34, 35, 36, 37, 40], "round": [17, 36, 39, 40], "robin": [17, 36, 40], "num_slav": 17, "devic": 17, "slave_wb": 17, "intefac": 17, "num_mast": 17, "ack": 17, "adr": 17, "dat_r": 17, "dat_w": 17, "err": 17, "lock": [17, 23, 26, 34, 35, 37], "rst": 17, "rty": 17, "stall": [17, 26], "stb": 17, "name": [17, 23, 34, 35, 36, 37, 38, 39, 40], "wb_master": 17, "becom": 17, "wishbonemastermethodlayout": 17, "wishbonememoryslav": 17, "underneath": 17, "keyword": [17, 34, 36, 37, 38, 39], "thei": [17, 19, 23, 26, 30, 33, 34, 36, 37], "re": [17, 26, 29, 34, 36], "infer": [17, 36], "wishbonemux": 17, "muxer": 17, "multiplex": [17, 34], "ssel_tga": 17, "corespond": 17, "tga": 17, "note": [17, 19, 37], "stare": 17, "clear": [17, 31, 32, 37], "delai": [17, 34], "deassert": [17, 40], "master_wb": 17, "singal": 17, "granular": [17, 37], "smallest": 17, "port": [17, 36, 37, 39, 40], "capabl": 17, "wishbonesignatur": 17, "path": [17, 36, 37], "src_loc_at": [17, 37], "csraddress": 19, "3072": 19, "cycleh": 19, "3200": 19, "instret": 19, "3074": 19, "instreth": 19, "3202": 19, "mcaus": 19, "834": 19, "mepc": 19, "833": 19, "mtvec": 19, "773": 19, "3073": 19, "timeh": 19, "3201": 19, "doublecountercsr": 19, "group": [19, 37], "csrregist": 19, "At": 19, "overflow": [19, 37], "low_addr": 19, "high_addr": 19, "lower": [19, 39], "higher": 19, "synthetis": 19, "genericcsrregist": 19, "machinemodecsrregist": 19, "csrlistkei": 19, "listkei": [19, 37, 39], "dependencymanag": [19, 36, 37, 38, 39], "behaviour": [19, 33], "automat": [19, 23, 33, 39], "csrunit": 19, "bodi": [19, 34, 36, 37], "csr_val": 19, "els": [19, 26, 34, 36], "side": [19, 26, 31, 32], "effect": [19, 26, 31, 32, 36, 37], "_fu_read": 19, "_fu_writ": 19, "current": [19, 20, 21, 26, 36], "ignor": 19, "prioriti": [19, 20, 34, 36, 37], "csr_number": 19, "ro_bit": 19, "mask": [19, 37], "those": [19, 26, 36], "some": [19, 26, 29, 34, 36, 37], "upper": [19, 37], "0b11": 19, "discard": 19, "privilegelevel": 19, "csr_access_privileg": 19, "csr_addr": 19, "exceptioncauseregist": 20, "earliest": 20, "report": [20, 37], "rob_get_indic": 20, "fetch_stall_except": 20, "should_update_priorii": 20, "current_caus": 20, "new_caus": 20, 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"column": 23, "question": [23, 34], "togeth": [23, 34, 36], "differenti": 23, "ident": [23, 37], "declar": [23, 34, 37, 38], "disambigu": 23, "show": 23, "caller": [23, 34, 35, 36, 37], "condit": [23, 34, 35, 36, 37], "could": [23, 34, 37], "forc": 23, "conflict": [23, 25, 35, 36], "produc": 23, "tree": [23, 35, 37], "root": [23, 35], "invert": 23, "children": 23, "how": [23, 26, 31, 33, 36, 37], "mani": [23, 26, 33, 34, 35, 36, 37, 39], "sort": [23, 37], "filter": [23, 37], "regular": 23, "express": [23, 34, 37], "loc": 23, "coreblock": [24, 29, 33], "go": [24, 26, 29, 36], "microarchitectur": 24, "focu": 24, "flexibl": [24, 30], "easili": [24, 37], "experi": 24, "doc": 24, "descript": [24, 25, 33, 37, 39], "overview": [24, 25, 26], "high": [24, 37, 40], "found": [24, 33], "version": [24, 33], "page": [24, 26, 33], "api": [24, 25], "kuznia": [24, 33], "rdzeni": [24, 33], "github": [24, 33], "io": [24, 33], "introduct": 25, "assumpt": [25, 26], "made": [25, 26, 34], "develop": [25, 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"1993": 26, "2001": 26, "much": [26, 37], "research": 26, "cpu": 26, "consid": [26, 34, 36, 37], "solv": 26, "instead": [26, 29, 34, 35, 36, 37, 38, 40], "try": [26, 29, 34], "due": [26, 36, 37], "characterist": 26, "easi": [26, 29, 34, 37], "our": [26, 30, 33], "decid": [26, 30, 34], "what": 26, "peopl": 26, "probabl": [26, 38], "lot": 26, "worth": 26, "walker": 26, "cragon": 26, "concurr": [26, 36], "ieee": 26, "vol": 26, "june": 26, "1995": 26, "moudgil": 26, "vassiliadi": 26, "micro": 26, "pp": 26, "58": 26, "67": 26, "februari": 26, "1996": 26, "These": [26, 33, 34], "survei": 26, "topic": 26, "cdc": 26, "6600": 26, "done": [26, 33, 34, 36, 37, 38], "jump": 26, "handler": [26, 38], "ibm360": 26, "stop": [26, 37], "crai": 26, "similar": [26, 33, 34, 37, 40], "here": [26, 31], "bigger": [26, 37], "torng": 26, "martin": 26, "dai": 26, "probe": 26, "idea": [26, 34], "author": 26, "window": 26, "iw": 26, "dispatch": [26, 30, 31, 32], "didn": 26, "context": [26, 35, 36, 37, 39], "copi": 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