diff --git a/test/regression/memory.py b/test/regression/memory.py
index 97d9c41bb..68bda0616 100644
--- a/test/regression/memory.py
+++ b/test/regression/memory.py
@@ -137,7 +137,7 @@ def write(self, req: WriteRequest) -> WriteReply:
             return WriteReply(status=ReplyStatus.ERROR)
 
 
-def load_segments_from_elf(file_path: str) -> list[RandomAccessMemory]:
+def load_segments_from_elf(file_path: str, *, disable_write_protection: bool = False) -> list[RandomAccessMemory]:
     segments: list[RandomAccessMemory] = []
 
     with open(file_path, "rb") as f:
@@ -162,7 +162,7 @@ def align_down(n: int) -> int:
             flags = SegmentFlags(0)
             if flags_raw & P_FLAGS.PF_R:
                 flags |= SegmentFlags.READ
-            if flags_raw & P_FLAGS.PF_W:
+            if flags_raw & P_FLAGS.PF_W or disable_write_protection:
                 flags |= SegmentFlags.WRITE
             if flags_raw & P_FLAGS.PF_X:
                 flags |= SegmentFlags.EXECUTABLE
diff --git a/test/regression/test.py b/test/regression/test.py
index fa023f90f..cbe8067cd 100644
--- a/test/regression/test.py
+++ b/test/regression/test.py
@@ -7,6 +7,9 @@
 test_dir = Path(__file__).parent.parent
 riscv_tests_dir = test_dir.joinpath("external/riscv-tests")
 
+# disable write protection for specific tests with writes to .text section
+exclude_write_protection = ["rv32uc-rvc"]
+
 
 class MMIO(MemorySegment):
     def __init__(self, on_finish: Callable[[], None]):
@@ -31,7 +34,10 @@ async def run_test(sim_backend: SimulationBackend, test_name: str):
     mmio = MMIO(lambda: sim_backend.stop())
 
     mem_segments: list[MemorySegment] = []
-    mem_segments += load_segments_from_elf(str(riscv_tests_dir.joinpath("test-" + test_name)))
+    mem_segments += load_segments_from_elf(
+        str(riscv_tests_dir.joinpath("test-" + test_name)),
+        disable_write_protection=test_name in exclude_write_protection,
+    )
     mem_segments.append(mmio)
 
     mem_model = CoreMemoryModel(mem_segments)