diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index 8af9dd2f9..0051faba9 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index d7d384c88..490eb827e 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree index c8040cee0..e434f889d 100644 Binary files a/.doctrees/current-graph.doctree and b/.doctrees/current-graph.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index 716eeece0..ceeea8506 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/.doctrees/transactron.lib.doctree b/.doctrees/transactron.lib.doctree index 54b8fd273..e5d0d4a70 100644 Binary files a/.doctrees/transactron.lib.doctree and b/.doctrees/transactron.lib.doctree differ diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index e332048e1..8d0d93c08 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -6,26 +6,26 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_WishboneMaster["WishboneMaster"] - WishboneMaster_result["result"] WishboneMaster_request["request"] + WishboneMaster_result["result"] + WishboneMaster_WishboneMaster["WishboneMaster"] subgraph Forwarder["result Forwarder"] Forwarder_read["read"] Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] + WishboneMaster1_request["request"] WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] - WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] Forwarder1_write["write"] Forwarder1_read["read"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_get_read_response["get_read_response"] WishboneMasterAdapter_request_read["request_read"] + WishboneMasterAdapter_get_read_response["get_read_response"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] @@ -37,8 +37,8 @@ end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_request_write["request_write"] - WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_read["request_read"] + WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_get_read_response["get_read_response"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] @@ -52,32 +52,32 @@ end end subgraph CoreFrontend["frontend CoreFrontend"] - CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] CoreFrontend_target_pred_req["target_pred_req"] - CoreFrontend_stall["stall"] CoreFrontend_target_pred_resp["target_pred_resp"] + CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] + CoreFrontend_stall["stall"] subgraph BasicFifo2["instr_buffer BasicFifo"] - BasicFifo2_write["write"] - BasicFifo2_clear["clear"] BasicFifo2_read["read"] + BasicFifo2_clear["clear"] + BasicFifo2_write["write"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end end subgraph ICache["icache ICache"] - ICache_issue_req["issue_req"] - ICache_MemRead["MemRead"] ICache_ICache["ICache"] + ICache_MemRead["MemRead"] + ICache_ICache1["ICache"] ICache_accept_res["accept_res"] ICache_flush["flush"] - ICache_ICache1["ICache"] + ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -100,34 +100,34 @@ HwExpHistogram__add["_add"] end subgraph FIFO["fifo FIFO"] - FIFO_read["read"] FIFO_write["write"] + FIFO_read["read"] end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] ArgumentsToResultsZipper_peek_arg["peek_arg"] - ArgumentsToResultsZipper_read["read"] - ArgumentsToResultsZipper_write_args["write_args"] ArgumentsToResultsZipper_write_results["write_results"] + ArgumentsToResultsZipper_write_args["write_args"] + ArgumentsToResultsZipper_read["read"] subgraph BasicFifo3["fifo BasicFifo"] BasicFifo3_read["read"] - BasicFifo3_write["write"] BasicFifo3_peek["peek"] + BasicFifo3_write["write"] end subgraph Forwarder3["forwarder Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end end subgraph FetchUnit["fetch FetchUnit"] - FetchUnit_Fetch_Stage2["Fetch_Stage2"] + FetchUnit_resume_from_exception["resume_from_exception"] FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] + FetchUnit_resume_from_unsafe["resume_from_unsafe"] FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] - FetchUnit_stall_exception["stall_exception"] FetchUnit_Fetch_Stage1["Fetch_Stage1"] - FetchUnit_resume_from_exception["resume_from_exception"] - FetchUnit_resume_from_unsafe["resume_from_unsafe"] + FetchUnit_stall_exception["stall_exception"] + FetchUnit_Fetch_Stage2["Fetch_Stage2"] FetchUnit_Fetch_Stage0["Fetch_Stage0"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] @@ -136,9 +136,9 @@ HwCounter5__incr["_incr"] end subgraph Serializer["serializer Serializer"] + Serializer_clean["clean"] Serializer_write["write"] Serializer_read["read"] - Serializer_clean["clean"] end subgraph ConnectTrans["serializer_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -148,12 +148,12 @@ BasicFifo4_write["write"] end subgraph Semaphore["req_counter Semaphore"] - Semaphore_acquire["acquire"] Semaphore_release["release"] + Semaphore_acquire["acquire"] end subgraph Pipe["s1_s2_pipe Pipe"] - Pipe_write["write"] Pipe_read["read"] + Pipe_write["write"] end subgraph Predecoder["predecoder_0 Predecoder"] Predecoder_predecode["predecode"] @@ -172,9 +172,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] - Pipe1_read["read"] Pipe1_write["write"] Pipe1_clean["clean"] + Pipe1_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -184,8 +184,8 @@ end end subgraph BasicFifo5["free_rf_fifo BasicFifo"] - BasicFifo5_write["write"] BasicFifo5_read["read"] + BasicFifo5_write["write"] end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] @@ -195,11 +195,11 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_perf["perf"] RegisterFile_write["write"] + RegisterFile_read2["read2"] RegisterFile_free["free"] RegisterFile_read1["read1"] - RegisterFile_read2["read2"] + RegisterFile_perf["perf"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer__start["_start"] TaggedLatencyMeasurer__stop["_stop"] @@ -207,8 +207,8 @@ HwExpHistogram1__add["_add"] end subgraph AsyncMemoryBank["slots AsyncMemoryBank"] - AsyncMemoryBank_read["read"] - AsyncMemoryBank_write["write"] + AsyncMemoryBank_AsyncMemoryBank["AsyncMemoryBank"] + AsyncMemoryBank_AsyncMemoryBank1["AsyncMemoryBank"] end end subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] @@ -216,12 +216,12 @@ end end subgraph ReorderBuffer["ROB ReorderBuffer"] + ReorderBuffer_put["put"] ReorderBuffer_peek["peek"] - ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_retire["retire"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_perf["perf"] - ReorderBuffer_put["put"] + ReorderBuffer_retire["retire"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] FIFOLatencyMeasurer1__start["_start"] FIFOLatencyMeasurer1__stop["_stop"] @@ -238,12 +238,12 @@ end end subgraph ExceptionInformationRegister["exception_information_register ExceptionInformationRegister"] - ExceptionInformationRegister_clear["clear"] ExceptionInformationRegister_report["report"] + ExceptionInformationRegister_clear["clear"] ExceptionInformationRegister_get["get"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] - BasicFifo6_write["write"] BasicFifo6_read["read"] + BasicFifo6_write["write"] end subgraph ConnectTrans1["report_connector ConnectTrans"] ConnectTrans1_ConnectTrans["ConnectTrans"] @@ -273,29 +273,29 @@ end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] RSFuncBlock_update["update"] - RSFuncBlock_insert["insert"] - RSFuncBlock_get_result["get_result"] RSFuncBlock_select["select"] + RSFuncBlock_get_result["get_result"] + RSFuncBlock_insert["insert"] subgraph RS["rs RS"] + RS_perf["perf"] RS_RS["RS"] RS_RS1["RS"] - RS_insert["insert"] - RS_RS2["RS"] RS_update["update"] + RS_RS2["RS"] RS_select["select"] + RS_insert["insert"] + RS_take["take"] RS_RS3["RS"] RS_RS4["RS"] - RS_perf["perf"] - RS_take["take"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__start["_start"] TaggedLatencyMeasurer1__stop["_stop"] + TaggedLatencyMeasurer1__start["_start"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_write["write"] - AsyncMemoryBank1_read["read"] + AsyncMemoryBank1_AsyncMemoryBank["AsyncMemoryBank"] + AsyncMemoryBank1_AsyncMemoryBank1["AsyncMemoryBank"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -309,16 +309,16 @@ TaggedCounter4__incr["_incr"] end subgraph FIFO2["fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO3["fifo FIFO"] FIFO3_read["read"] FIFO3_write["write"] @@ -328,8 +328,8 @@ WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO4["fifo_branch_resolved FIFO"] FIFO4_write["write"] FIFO4_read["read"] @@ -355,8 +355,8 @@ ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -364,12 +364,12 @@ end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] - PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] + PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] PrivilegedFuncUnit_issue["issue"] - PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] + PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] BasicFifo8_read["read"] BasicFifo8_write["write"] @@ -407,26 +407,26 @@ end end subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] - RSFuncBlock1_get_result["get_result"] - RSFuncBlock1_select["select"] RSFuncBlock1_insert["insert"] RSFuncBlock1_update["update"] + RSFuncBlock1_get_result["get_result"] + RSFuncBlock1_select["select"] subgraph FifoRS["rs FifoRS"] - FifoRS_select["select"] - FifoRS_FifoRS["FifoRS"] - FifoRS_update["update"] - FifoRS_insert["insert"] FifoRS_take["take"] + FifoRS_update["update"] + FifoRS_FifoRS["FifoRS"] + FifoRS_select["select"] FifoRS_perf["perf"] + FifoRS_insert["insert"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer2__start["_start"] TaggedLatencyMeasurer2__stop["_stop"] + TaggedLatencyMeasurer2__start["_start"] subgraph HwExpHistogram7["histogram HwExpHistogram"] HwExpHistogram7__add["_add"] end subgraph AsyncMemoryBank2["slots AsyncMemoryBank"] - AsyncMemoryBank2_read["read"] - AsyncMemoryBank2_write["write"] + AsyncMemoryBank2_AsyncMemoryBank["AsyncMemoryBank"] + AsyncMemoryBank2_AsyncMemoryBank1["AsyncMemoryBank"] end end subgraph HwExpHistogram8["perf_num_full HwExpHistogram"] @@ -434,24 +434,24 @@ end end subgraph LSUDummy["func_unit_0 LSUDummy"] - LSUDummy_accept_cond0["accept_cond0"] + LSUDummy_accept["accept"] LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_accept_cond0["accept_cond0"] LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_issue["issue"] - LSUDummy_accept["accept"] LSUDummy_accept_cond1["accept_cond1"] + LSUDummy_issue["issue"] LSUDummy_LSUDummy2["LSUDummy"] subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond0["issue_cond0"] - LSURequester_accept_cond0["accept_cond0"] - LSURequester_accept_cond1["accept_cond1"] LSURequester_issue["issue"] - LSURequester_issue_cond2["issue_cond2"] + LSURequester_accept_cond0["accept_cond0"] LSURequester_accept["accept"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_accept_cond1["accept_cond1"] + LSURequester_issue_cond0["issue_cond0"] + LSURequester_issue_cond2["issue_cond2"] subgraph BasicFifo9["args_fifo BasicFifo"] - BasicFifo9_read["read"] BasicFifo9_write["write"] + BasicFifo9_read["read"] end end subgraph Forwarder6["requests Forwarder"] @@ -463,8 +463,8 @@ FIFO6_write["write"] end subgraph FIFO7["issued FIFO"] - FIFO7_write["write"] FIFO7_read["read"] + FIFO7_write["write"] end subgraph FIFO8["issued_noop FIFO"] FIFO8_read["read"] @@ -477,8 +477,8 @@ subgraph Collector2["collector Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_read["read"] Forwarder7_write["write"] + Forwarder7_read["read"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans10["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -488,10 +488,10 @@ end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_CSRUnit["CSRUnit"] CSRUnit_update["update"] CSRUnit_get_result["get_result"] CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_CSRUnit1["CSRUnit"] CSRUnit_insert["insert"] CSRUnit_select["select"] @@ -547,17 +547,17 @@ end end subgraph AliasedCSR["mstatus AliasedCSR"] - AliasedCSR__fu_write["_fu_write"] AliasedCSR__fu_read["_fu_read"] + AliasedCSR__fu_write["_fu_write"] end subgraph AliasedCSR1["mstatush AliasedCSR"] - AliasedCSR1__fu_read["_fu_read"] AliasedCSR1__fu_write["_fu_write"] + AliasedCSR1__fu_read["_fu_read"] end subgraph CSRRegister6["mcause CSRRegister"] - CSRRegister6__internal_fu_read["_internal_fu_read"] CSRRegister6_write["write"] CSRRegister6__internal_fu_write["_internal_fu_write"] + CSRRegister6__internal_fu_read["_internal_fu_read"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -569,9 +569,9 @@ end end subgraph CSRRegister7["mtvec CSRRegister"] + CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7_read["read"] CSRRegister7__internal_fu_read["_internal_fu_read"] - CSRRegister7__internal_fu_write["_internal_fu_write"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] end @@ -583,9 +583,9 @@ end end subgraph CSRRegister8["mepc CSRRegister"] - CSRRegister8_read["read"] CSRRegister8_write["write"] CSRRegister8__internal_fu_read["_internal_fu_read"] + CSRRegister8_read["read"] CSRRegister8__internal_fu_write["_internal_fu_write"] subgraph MethodMap16["fu_write_map MethodMap"] MethodMap16_method["method"] @@ -598,9 +598,9 @@ end end subgraph CSRRegister9["mtval CSRRegister"] - CSRRegister9__internal_fu_write["_internal_fu_write"] - CSRRegister9_write["write"] CSRRegister9__internal_fu_read["_internal_fu_read"] + CSRRegister9_write["write"] + CSRRegister9__internal_fu_write["_internal_fu_write"] subgraph MethodMap18["fu_write_map MethodMap"] MethodMap18_method["method"] end @@ -612,8 +612,8 @@ end end subgraph CSRRegister10["priv_mode CSRRegister"] - CSRRegister10_read["read"] CSRRegister10_write["write"] + CSRRegister10_read["read"] end subgraph CSRRegister11["mstatus_mie CSRRegister"] CSRRegister11__internal_fu_read["_internal_fu_read"] @@ -632,8 +632,8 @@ end subgraph CSRRegister12["mstatus_mpie CSRRegister"] CSRRegister12__internal_fu_write["_internal_fu_write"] - CSRRegister12__internal_fu_read["_internal_fu_read"] CSRRegister12_read["read"] + CSRRegister12__internal_fu_read["_internal_fu_read"] CSRRegister12_write["write"] subgraph MethodMap24["fu_write_map MethodMap"] MethodMap24_method["method"] @@ -646,10 +646,10 @@ end end subgraph CSRRegister13["mstatus_mpp CSRRegister"] + CSRRegister13__internal_fu_write["_internal_fu_write"] CSRRegister13_read["read"] CSRRegister13_write["write"] CSRRegister13__internal_fu_read["_internal_fu_read"] - CSRRegister13__internal_fu_write["_internal_fu_write"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -661,9 +661,9 @@ end end subgraph CSRRegister14["mstatus_mprv CSRRegister"] + CSRRegister14_write["write"] CSRRegister14__internal_fu_read["_internal_fu_read"] CSRRegister14__internal_fu_write["_internal_fu_write"] - CSRRegister14_write["write"] subgraph MethodMap28["fu_write_map MethodMap"] MethodMap28_method["method"] end @@ -692,17 +692,17 @@ subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister16["register_low CSRRegister"] - CSRRegister16_write["write"] CSRRegister16_read["read"] CSRRegister16__internal_fu_read["_internal_fu_read"] + CSRRegister16_write["write"] subgraph MethodMap33["fu_read_map MethodMap"] MethodMap33_method["method"] end end subgraph CSRRegister17["register_high CSRRegister"] - CSRRegister17_write["write"] - CSRRegister17__internal_fu_read["_internal_fu_read"] CSRRegister17_read["read"] + CSRRegister17__internal_fu_read["_internal_fu_read"] + CSRRegister17_write["write"] subgraph MethodMap35["fu_read_map MethodMap"] MethodMap35_method["method"] end @@ -711,8 +711,8 @@ subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister18["register_low CSRRegister"] - CSRRegister18_write["write"] CSRRegister18_read["read"] + CSRRegister18_write["write"] CSRRegister18__internal_fu_read["_internal_fu_read"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] @@ -720,8 +720,8 @@ end subgraph CSRRegister19["register_high CSRRegister"] CSRRegister19_write["write"] - CSRRegister19_read["read"] CSRRegister19__internal_fu_read["_internal_fu_read"] + CSRRegister19_read["read"] subgraph MethodMap39["fu_read_map MethodMap"] MethodMap39_method["method"] end @@ -729,16 +729,16 @@ end end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] - InternalInterruptController_interrupt_cause["interrupt_cause"] InternalInterruptController_InternalInterruptController["InternalInterruptController"] - InternalInterruptController_mret["mret"] - InternalInterruptController_entry["entry"] InternalInterruptController_InternalInterruptController1["InternalInterruptController"] + InternalInterruptController_interrupt_cause["interrupt_cause"] + InternalInterruptController_entry["entry"] + InternalInterruptController_mret["mret"] InternalInterruptController_InternalInterruptController2["InternalInterruptController"] subgraph CSRRegister20["mie CSRRegister"] + CSRRegister20__internal_fu_write["_internal_fu_write"] CSRRegister20__internal_fu_read["_internal_fu_read"] CSRRegister20_read["read"] - CSRRegister20__internal_fu_write["_internal_fu_write"] subgraph MethodMap40["fu_write_map MethodMap"] MethodMap40_method["method"] end @@ -750,11 +750,11 @@ end end subgraph CSRRegister21["mip CSRRegister"] - CSRRegister21__internal_fu_write["_internal_fu_write"] CSRRegister21_write["write"] CSRRegister21_read["read"] CSRRegister21__internal_fu_read["_internal_fu_read"] CSRRegister21_read_comb["read_comb"] + CSRRegister21__internal_fu_write["_internal_fu_write"] subgraph MethodMap42["fu_write_map MethodMap"] MethodMap42_method["method"] end @@ -767,16 +767,16 @@ end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph MethodProduct1["get_instr MethodProduct"] MethodProduct1_method["method"] end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO9["alloc_rename_buf FIFO"] - FIFO9_write["write"] FIFO9_read["read"] + FIFO9_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -789,8 +789,8 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -812,8 +812,8 @@ subgraph Collector3["FetchResumeKey_unifier Collector"] Collector3_method["method"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_write["write"] Forwarder8_read["read"] + Forwarder8_write["write"] end subgraph ManyToOneConnectTrans3["connect ManyToOneConnectTrans"] subgraph ConnectTrans11["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -829,28 +829,28 @@ ConnectTrans13_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_precommit["precommit"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement["Retirement"] Retirement_Retirement1["Retirement"] - Retirement_Retirement2["Retirement"] Retirement_Retirement_cond1["Retirement_cond1"] - Retirement_core_state["core_state"] + Retirement_Retirement_cond0["Retirement_cond0"] + Retirement_precommit["precommit"] + Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] + Retirement_core_state["core_state"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister22["register_low CSRRegister"] - CSRRegister22__internal_fu_read["_internal_fu_read"] CSRRegister22_write["write"] CSRRegister22_read["read"] + CSRRegister22__internal_fu_read["_internal_fu_read"] subgraph MethodMap45["fu_read_map MethodMap"] MethodMap45_method["method"] end end subgraph CSRRegister23["register_high CSRRegister"] - CSRRegister23__internal_fu_read["_internal_fu_read"] - CSRRegister23_write["write"] CSRRegister23_read["read"] + CSRRegister23_write["write"] + CSRRegister23__internal_fu_read["_internal_fu_read"] subgraph MethodMap47["fu_read_map MethodMap"] MethodMap47_method["method"] end @@ -860,55 +860,55 @@ HwCounter9__incr["_incr"] end subgraph FIFOLatencyMeasurer2["perf_trap_latency FIFOLatencyMeasurer"] - FIFOLatencyMeasurer2__stop["_stop"] FIFOLatencyMeasurer2__start["_start"] + FIFOLatencyMeasurer2__stop["_stop"] subgraph HwExpHistogram9["histogram HwExpHistogram"] HwExpHistogram9__add["_add"] end subgraph FIFO12["fifo FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end end end end end subgraph TransactionManager["transaction_manager TransactionManager"] - TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] - TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_accept_cond0_accept_cond0_ConnectTrans["accept_cond0_accept_cond0_ConnectTrans"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] - TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit["PrivilegedFuncUnit_cond0_PrivilegedFuncUnit"] + TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] - TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_PrivilegedFuncUnit_cond0"] + TransactionManager_accept_cond1_ConnectTrans_accept_cond0["accept_cond1_ConnectTrans_accept_cond0"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0["Fetch_Stage2_Fetch_Stage2_cond0"] - TransactionManager_accept_cond0_accept_cond1_ConnectTrans["accept_cond0_accept_cond1_ConnectTrans"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1["Fetch_Stage2_Fetch_Stage2_cond1"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] + TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] end end Core_InitFreeRFFifo --> BasicFifo5_write - Retirement_Retirement1 --> BasicFifo5_write + Retirement_Retirement --> BasicFifo5_write + TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write - TransactionManager_Retirement_cond1_Retirement --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Serializer_Serializer1 - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> BasicFifo_write - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMaster_request - WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Forwarder2_write - ICache_ICache1 <--> HwCounter4__incr + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request + WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write + ICache_ICache <--> HwCounter4__incr ArgumentsToResultsZipper_peek_arg --> ICache_MemRead BasicFifo3_peek --> ICache_MemRead ICache_MemRead <--> HwCounter1__incr @@ -916,9 +916,9 @@ ICache_MemRead --> Forwarder3_write ICache_MemRead <--> HwCounter2__incr ICache_MemRead --> SimpleCommonBusCacheRefiller_start_refill - SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache - Forwarder2_read --> ICache_ICache - ICache_ICache <--> HwCounter3__incr + SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 + Forwarder2_read --> ICache_ICache1 + ICache_ICache1 <--> HwCounter3__incr FetchUnit_Fetch_Stage0 <--> Semaphore_acquire FetchUnit_Fetch_Stage0 --> ICache_issue_req FetchUnit_Fetch_Stage0 <--> HwCounter__incr @@ -953,43 +953,43 @@ GenericCSRRegisters_GenericCSRRegisters --> CSRRegister18_write CSRRegister19_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister19_write + CSRRegister11_read --> InternalInterruptController_InternalInterruptController CSRRegister11_read --> InternalInterruptController_InternalInterruptController1 - CSRRegister11_read --> InternalInterruptController_InternalInterruptController2 + CSRRegister10_read --> InternalInterruptController_InternalInterruptController CSRRegister10_read --> InternalInterruptController_InternalInterruptController1 - CSRRegister10_read --> InternalInterruptController_InternalInterruptController2 CSRRegister10_read --> WakeupSelect3_WakeupSelect - CSRRegister10_read --> CSRUnit_CSRUnit - CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + CSRRegister10_read --> CSRUnit_CSRUnit1 CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit - CSRRegister20_read --> InternalInterruptController_InternalInterruptController1 - CSRRegister21_read --> InternalInterruptController_InternalInterruptController1 - CSRRegister21_read_comb --> InternalInterruptController_InternalInterruptController - InternalInterruptController_InternalInterruptController --> CSRRegister21_write - InternalInterruptController_InternalInterruptController2 --> CSRRegister11_write - InternalInterruptController_InternalInterruptController2 --> CSRRegister12_write - InternalInterruptController_InternalInterruptController2 --> CSRRegister13_write - InternalInterruptController_InternalInterruptController2 --> CSRRegister10_write - CSRRegister12_read --> InternalInterruptController_InternalInterruptController2 - CSRRegister13_read --> InternalInterruptController_InternalInterruptController2 - InternalInterruptController_InternalInterruptController2 --> CSRRegister14_write + CSRRegister20_read --> InternalInterruptController_InternalInterruptController + CSRRegister21_read --> InternalInterruptController_InternalInterruptController + CSRRegister21_read_comb --> InternalInterruptController_InternalInterruptController2 + InternalInterruptController_InternalInterruptController2 --> CSRRegister21_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister11_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister12_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister13_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister10_write + CSRRegister12_read --> InternalInterruptController_InternalInterruptController1 + CSRRegister13_read --> InternalInterruptController_InternalInterruptController1 + InternalInterruptController_InternalInterruptController1 --> CSRRegister14_write MethodProduct1_method --> RegAllocation_RegAllocation Pipe1_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation <--> CoreInstructionCounter_increment BasicFifo5_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO9_write - FIFO10_read --> RSSelection_RSSelection FIFO10_read --> RSSelection_RSSelection1 FIFO10_read --> RSSelection_RSSelection2 - RSFuncBlock_select --> RSSelection_RSSelection - RS_select --> RSSelection_RSSelection - RSSelection_RSSelection --> FIFO11_write + FIFO10_read --> RSSelection_RSSelection + RSFuncBlock_select --> RSSelection_RSSelection1 + RS_select --> RSSelection_RSSelection1 RSSelection_RSSelection1 --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write - RSFuncBlock1_select --> RSSelection_RSSelection1 - FifoRS_select --> RSSelection_RSSelection1 - RSSelection_RSSelection2 <--> CSRUnit_select + RSSelection_RSSelection --> FIFO11_write + RSFuncBlock1_select --> RSSelection_RSSelection2 + FifoRS_select --> RSSelection_RSSelection2 + RSSelection_RSSelection <--> CSRUnit_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -997,11 +997,11 @@ RSInsertion_RSInsertion --> RSFuncBlock_insert RSInsertion_RSInsertion --> RS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer1__start - RSInsertion_RSInsertion --> AsyncMemoryBank1_write + RSInsertion_RSInsertion --> AsyncMemoryBank1_AsyncMemoryBank RSInsertion_RSInsertion --> RSFuncBlock1_insert RSInsertion_RSInsertion --> FifoRS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer2__start - RSInsertion_RSInsertion --> AsyncMemoryBank2_write + RSInsertion_RSInsertion --> AsyncMemoryBank2_AsyncMemoryBank RSInsertion_RSInsertion --> CSRUnit_insert BasicFifo6_read --> ConnectTrans1_ConnectTrans ConnectTrans1_ConnectTrans --> ExceptionInformationRegister_report @@ -1023,7 +1023,7 @@ ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done ResultAnnouncement_ResultAnnouncement --> RegisterFile_write ResultAnnouncement_ResultAnnouncement --> TaggedLatencyMeasurer__start - ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_write + ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_AsyncMemoryBank1 ResultAnnouncement_ResultAnnouncement --> MethodProduct_method ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update @@ -1031,7 +1031,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add - RS_RS1 --> WakeupSelect_WakeupSelect + RS_RS2 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -1042,11 +1042,11 @@ WakeupSelect2_WakeupSelect --> TaggedLatencyMeasurer1__stop WakeupSelect3_WakeupSelect --> TaggedLatencyMeasurer1__stop WakeupSelect4_WakeupSelect --> TaggedLatencyMeasurer1__stop - AsyncMemoryBank1_read --> WakeupSelect_WakeupSelect - AsyncMemoryBank1_read --> WakeupSelect1_WakeupSelect - AsyncMemoryBank1_read --> WakeupSelect2_WakeupSelect - AsyncMemoryBank1_read --> WakeupSelect3_WakeupSelect - AsyncMemoryBank1_read --> WakeupSelect4_WakeupSelect + AsyncMemoryBank1_AsyncMemoryBank1 --> WakeupSelect_WakeupSelect + AsyncMemoryBank1_AsyncMemoryBank1 --> WakeupSelect1_WakeupSelect + AsyncMemoryBank1_AsyncMemoryBank1 --> WakeupSelect2_WakeupSelect + AsyncMemoryBank1_AsyncMemoryBank1 --> WakeupSelect3_WakeupSelect + AsyncMemoryBank1_AsyncMemoryBank1 --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> HwExpHistogram5__add WakeupSelect1_WakeupSelect --> HwExpHistogram5__add WakeupSelect2_WakeupSelect --> HwExpHistogram5__add @@ -1055,22 +1055,22 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter4__incr WakeupSelect_WakeupSelect --> FIFO2_write - RS_RS3 --> WakeupSelect1_WakeupSelect + RS_RS --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write - RS_RS2 --> WakeupSelect2_WakeupSelect + RS_RS3 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write WakeupSelect2_WakeupSelect --> TaggedCounter5__incr - RS_RS --> WakeupSelect3_WakeupSelect + RS_RS1 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> BasicFifo6_write ConnectTrans7_ConnectTrans --> BasicFifo6_write ConnectTrans9_ConnectTrans --> BasicFifo6_write ConnectTrans4_ConnectTrans --> BasicFifo6_write - TransactionManager_accept_cond0_accept_cond0_ConnectTrans --> BasicFifo6_write - TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> BasicFifo6_write + TransactionManager_accept_cond1_ConnectTrans_accept_cond0 --> BasicFifo6_write + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write TransactionManager_accept_cond1_ConnectTrans --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write RS_RS4 --> WakeupSelect4_WakeupSelect @@ -1096,129 +1096,129 @@ CSRRegister8_read --> ConnectTrans9_ConnectTrans ConnectTrans9_ConnectTrans --> BasicFifo8_write FifoRS_perf --> HwExpHistogram8__add - Forwarder6_read --> LSUDummy_LSUDummy + Forwarder6_read --> LSUDummy_LSUDummy1 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 - Forwarder6_read --> TransactionManager_LSUDummy_issue_cond1 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 - LSUDummy_LSUDummy --> FIFO6_write + Forwarder6_read --> TransactionManager_LSUDummy_issue_cond1 + LSUDummy_LSUDummy1 --> FIFO6_write WakeupSelect5_WakeupSelect --> FIFO6_write TransactionManager_LSUDummy_issue_cond0 --> FIFO6_write - TransactionManager_LSUDummy_issue_cond1 --> FIFO6_write TransactionManager_LSUDummy_issue_cond2 --> FIFO6_write - LSUDummy_LSUDummy --> FIFO8_write + TransactionManager_LSUDummy_issue_cond1 --> FIFO6_write + LSUDummy_LSUDummy1 --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write - TransactionManager_LSUDummy_issue_cond1 --> FIFO8_write TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write - Retirement_precommit --> LSUDummy_LSUDummy2 - Retirement_precommit --> CSRUnit_CSRUnit1 - Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + TransactionManager_LSUDummy_issue_cond1 --> FIFO8_write + Retirement_precommit --> LSUDummy_LSUDummy + Retirement_precommit --> CSRUnit_CSRUnit Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit - ReorderBuffer_peek --> LSUDummy_LSUDummy2 - ReorderBuffer_peek --> CSRUnit_CSRUnit1 - ReorderBuffer_peek --> Retirement_Retirement + ReorderBuffer_peek --> LSUDummy_LSUDummy + ReorderBuffer_peek --> CSRUnit_CSRUnit ReorderBuffer_peek --> Retirement_Retirement1 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + ReorderBuffer_peek --> Retirement_Retirement ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 - ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop - AsyncMemoryBank2_read --> WakeupSelect5_WakeupSelect + AsyncMemoryBank2_AsyncMemoryBank1 --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> HwExpHistogram7__add WakeupSelect5_WakeupSelect --> LSUDummy_issue WakeupSelect5_WakeupSelect --> Forwarder6_write - MethodMap1_method --> CSRUnit_CSRUnit - CSRRegister__internal_fu_read --> CSRUnit_CSRUnit - MethodMap3_method --> CSRUnit_CSRUnit - CSRRegister1__internal_fu_read --> CSRUnit_CSRUnit - MethodMap5_method --> CSRUnit_CSRUnit - CSRRegister2__internal_fu_read --> CSRUnit_CSRUnit - MethodMap7_method --> CSRUnit_CSRUnit - CSRRegister3__internal_fu_read --> CSRUnit_CSRUnit - MethodMap9_method --> CSRUnit_CSRUnit - CSRRegister4__internal_fu_read --> CSRUnit_CSRUnit - CSRUnit_CSRUnit --> MethodFilter4_method - CSRUnit_CSRUnit --> MethodMap8_method - CSRUnit_CSRUnit --> CSRRegister4__internal_fu_write - MethodMap11_method --> CSRUnit_CSRUnit - CSRRegister5__internal_fu_read --> CSRUnit_CSRUnit - AliasedCSR__fu_read --> CSRUnit_CSRUnit - MethodMap23_method --> CSRUnit_CSRUnit - CSRRegister11__internal_fu_read --> CSRUnit_CSRUnit - MethodMap25_method --> CSRUnit_CSRUnit - CSRRegister12__internal_fu_read --> CSRUnit_CSRUnit - MethodMap27_method --> CSRUnit_CSRUnit - CSRRegister13__internal_fu_read --> CSRUnit_CSRUnit - MethodMap29_method --> CSRUnit_CSRUnit - CSRRegister14__internal_fu_read --> CSRUnit_CSRUnit - MethodMap31_method --> CSRUnit_CSRUnit - CSRRegister15__internal_fu_read --> CSRUnit_CSRUnit - CSRUnit_CSRUnit --> AliasedCSR__fu_write - CSRUnit_CSRUnit --> MethodFilter11_method - CSRUnit_CSRUnit --> MethodMap22_method - CSRUnit_CSRUnit --> CSRRegister11__internal_fu_write - CSRUnit_CSRUnit --> MethodFilter12_method - CSRUnit_CSRUnit --> MethodMap24_method - CSRUnit_CSRUnit --> CSRRegister12__internal_fu_write - CSRUnit_CSRUnit --> MethodFilter13_method - CSRUnit_CSRUnit --> MethodMap26_method - CSRUnit_CSRUnit --> CSRRegister13__internal_fu_write - CSRUnit_CSRUnit --> MethodFilter14_method - CSRUnit_CSRUnit --> MethodMap28_method - CSRUnit_CSRUnit --> CSRRegister14__internal_fu_write - CSRUnit_CSRUnit --> MethodFilter15_method - CSRUnit_CSRUnit --> MethodMap30_method - CSRUnit_CSRUnit --> CSRRegister15__internal_fu_write - AliasedCSR1__fu_read --> CSRUnit_CSRUnit - CSRUnit_CSRUnit --> AliasedCSR1__fu_write - MethodMap13_method --> CSRUnit_CSRUnit - CSRRegister6__internal_fu_read --> CSRUnit_CSRUnit - CSRUnit_CSRUnit --> MethodFilter6_method - CSRUnit_CSRUnit --> MethodMap12_method - CSRUnit_CSRUnit --> CSRRegister6__internal_fu_write - MethodMap15_method --> CSRUnit_CSRUnit - CSRRegister7__internal_fu_read --> CSRUnit_CSRUnit - CSRUnit_CSRUnit --> MethodFilter7_method - CSRUnit_CSRUnit --> MethodMap14_method - CSRUnit_CSRUnit --> CSRRegister7__internal_fu_write - MethodMap17_method --> CSRUnit_CSRUnit - CSRRegister8__internal_fu_read --> CSRUnit_CSRUnit - CSRUnit_CSRUnit --> MethodFilter8_method - CSRUnit_CSRUnit --> MethodMap16_method - CSRUnit_CSRUnit --> CSRRegister8__internal_fu_write - MethodMap19_method --> CSRUnit_CSRUnit - CSRRegister9__internal_fu_read --> CSRUnit_CSRUnit - CSRUnit_CSRUnit --> MethodFilter9_method - CSRUnit_CSRUnit --> MethodMap18_method - CSRUnit_CSRUnit --> CSRRegister9__internal_fu_write - MethodMap33_method --> CSRUnit_CSRUnit - CSRRegister16__internal_fu_read --> CSRUnit_CSRUnit - MethodMap35_method --> CSRUnit_CSRUnit - CSRRegister17__internal_fu_read --> CSRUnit_CSRUnit - MethodMap37_method --> CSRUnit_CSRUnit - CSRRegister18__internal_fu_read --> CSRUnit_CSRUnit - MethodMap39_method --> CSRUnit_CSRUnit - CSRRegister19__internal_fu_read --> CSRUnit_CSRUnit - MethodMap41_method --> CSRUnit_CSRUnit - CSRRegister20__internal_fu_read --> CSRUnit_CSRUnit - CSRUnit_CSRUnit --> MethodFilter20_method - CSRUnit_CSRUnit --> MethodMap40_method - CSRUnit_CSRUnit --> CSRRegister20__internal_fu_write - MethodMap43_method --> CSRUnit_CSRUnit - CSRRegister21__internal_fu_read --> CSRUnit_CSRUnit - CSRUnit_CSRUnit --> MethodFilter21_method - CSRUnit_CSRUnit --> MethodMap42_method - CSRUnit_CSRUnit --> CSRRegister21__internal_fu_write - MethodMap45_method --> CSRUnit_CSRUnit - CSRRegister22__internal_fu_read --> CSRUnit_CSRUnit - MethodMap47_method --> CSRUnit_CSRUnit - CSRRegister23__internal_fu_read --> CSRUnit_CSRUnit + MethodMap1_method --> CSRUnit_CSRUnit1 + CSRRegister__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap3_method --> CSRUnit_CSRUnit1 + CSRRegister1__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap5_method --> CSRUnit_CSRUnit1 + CSRRegister2__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap7_method --> CSRUnit_CSRUnit1 + CSRRegister3__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap9_method --> CSRUnit_CSRUnit1 + CSRRegister4__internal_fu_read --> CSRUnit_CSRUnit1 + CSRUnit_CSRUnit1 --> MethodFilter4_method + CSRUnit_CSRUnit1 --> MethodMap8_method + CSRUnit_CSRUnit1 --> CSRRegister4__internal_fu_write + MethodMap11_method --> CSRUnit_CSRUnit1 + CSRRegister5__internal_fu_read --> CSRUnit_CSRUnit1 + AliasedCSR__fu_read --> CSRUnit_CSRUnit1 + MethodMap23_method --> CSRUnit_CSRUnit1 + CSRRegister11__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap25_method --> CSRUnit_CSRUnit1 + CSRRegister12__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap27_method --> CSRUnit_CSRUnit1 + CSRRegister13__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap29_method --> CSRUnit_CSRUnit1 + CSRRegister14__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap31_method --> CSRUnit_CSRUnit1 + CSRRegister15__internal_fu_read --> CSRUnit_CSRUnit1 + CSRUnit_CSRUnit1 --> AliasedCSR__fu_write + CSRUnit_CSRUnit1 --> MethodFilter11_method + CSRUnit_CSRUnit1 --> MethodMap22_method + CSRUnit_CSRUnit1 --> CSRRegister11__internal_fu_write + CSRUnit_CSRUnit1 --> MethodFilter12_method + CSRUnit_CSRUnit1 --> MethodMap24_method + CSRUnit_CSRUnit1 --> CSRRegister12__internal_fu_write + CSRUnit_CSRUnit1 --> MethodFilter13_method + CSRUnit_CSRUnit1 --> MethodMap26_method + CSRUnit_CSRUnit1 --> CSRRegister13__internal_fu_write + CSRUnit_CSRUnit1 --> MethodFilter14_method + CSRUnit_CSRUnit1 --> MethodMap28_method + CSRUnit_CSRUnit1 --> CSRRegister14__internal_fu_write + CSRUnit_CSRUnit1 --> MethodFilter15_method + CSRUnit_CSRUnit1 --> MethodMap30_method + CSRUnit_CSRUnit1 --> CSRRegister15__internal_fu_write + AliasedCSR1__fu_read --> CSRUnit_CSRUnit1 + CSRUnit_CSRUnit1 --> AliasedCSR1__fu_write + MethodMap13_method --> CSRUnit_CSRUnit1 + CSRRegister6__internal_fu_read --> CSRUnit_CSRUnit1 + CSRUnit_CSRUnit1 --> MethodFilter6_method + CSRUnit_CSRUnit1 --> MethodMap12_method + CSRUnit_CSRUnit1 --> CSRRegister6__internal_fu_write + MethodMap15_method --> CSRUnit_CSRUnit1 + CSRRegister7__internal_fu_read --> CSRUnit_CSRUnit1 + CSRUnit_CSRUnit1 --> MethodFilter7_method + CSRUnit_CSRUnit1 --> MethodMap14_method + CSRUnit_CSRUnit1 --> CSRRegister7__internal_fu_write + MethodMap17_method --> CSRUnit_CSRUnit1 + CSRRegister8__internal_fu_read --> CSRUnit_CSRUnit1 + CSRUnit_CSRUnit1 --> MethodFilter8_method + CSRUnit_CSRUnit1 --> MethodMap16_method + CSRUnit_CSRUnit1 --> CSRRegister8__internal_fu_write + MethodMap19_method --> CSRUnit_CSRUnit1 + CSRRegister9__internal_fu_read --> CSRUnit_CSRUnit1 + CSRUnit_CSRUnit1 --> MethodFilter9_method + CSRUnit_CSRUnit1 --> MethodMap18_method + CSRUnit_CSRUnit1 --> CSRRegister9__internal_fu_write + MethodMap33_method --> CSRUnit_CSRUnit1 + CSRRegister16__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap35_method --> CSRUnit_CSRUnit1 + CSRRegister17__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap37_method --> CSRUnit_CSRUnit1 + CSRRegister18__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap39_method --> CSRUnit_CSRUnit1 + CSRRegister19__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap41_method --> CSRUnit_CSRUnit1 + CSRRegister20__internal_fu_read --> CSRUnit_CSRUnit1 + CSRUnit_CSRUnit1 --> MethodFilter20_method + CSRUnit_CSRUnit1 --> MethodMap40_method + CSRUnit_CSRUnit1 --> CSRRegister20__internal_fu_write + MethodMap43_method --> CSRUnit_CSRUnit1 + CSRRegister21__internal_fu_read --> CSRUnit_CSRUnit1 + CSRUnit_CSRUnit1 --> MethodFilter21_method + CSRUnit_CSRUnit1 --> MethodMap42_method + CSRUnit_CSRUnit1 --> CSRRegister21__internal_fu_write + MethodMap45_method --> CSRUnit_CSRUnit1 + CSRRegister22__internal_fu_read --> CSRUnit_CSRUnit1 + MethodMap47_method --> CSRUnit_CSRUnit1 + CSRRegister23__internal_fu_read --> CSRUnit_CSRUnit1 ConnectTrans2_ConnectTrans --> Forwarder4_write ConnectTrans3_ConnectTrans --> Forwarder4_write ConnectTrans4_ConnectTrans --> Forwarder4_write @@ -1229,160 +1229,152 @@ Collector2_method --> ConnectTrans3_ConnectTrans Forwarder7_read --> ConnectTrans3_ConnectTrans CSRUnit_get_result --> ConnectTrans4_ConnectTrans - ExceptionInformationRegister_get --> Retirement_Retirement + ExceptionInformationRegister_get --> Retirement_Retirement1 + ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond1 ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond0 - ExceptionInformationRegister_get --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement1 <--> ReorderBuffer_retire + Retirement_Retirement <--> ReorderBuffer_retire + TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire - TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire - Retirement_Retirement1 <--> FIFOLatencyMeasurer1__stop + Retirement_Retirement <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop - TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer1__stop - FIFO1_read --> Retirement_Retirement1 + FIFO1_read --> Retirement_Retirement + FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 - FIFO1_read --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement1 --> HwExpHistogram3__add + Retirement_Retirement --> HwExpHistogram3__add + TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add - TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram3__add - CoreInstructionCounter_decrement --> Retirement_Retirement1 + CoreInstructionCounter_decrement --> Retirement_Retirement + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement - RRAT_peek --> Retirement_Retirement1 - RRAT_peek --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement1 --> RegisterFile_free + RRAT_peek --> Retirement_Retirement + RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement --> RegisterFile_free + TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free - TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free - Retirement_Retirement1 --> TaggedLatencyMeasurer__stop + Retirement_Retirement --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop - TransactionManager_Retirement_cond1_Retirement --> TaggedLatencyMeasurer__stop - AsyncMemoryBank_read --> Retirement_Retirement1 - AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0 - AsyncMemoryBank_read --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement1 --> HwExpHistogram1__add + AsyncMemoryBank_AsyncMemoryBank --> Retirement_Retirement + AsyncMemoryBank_AsyncMemoryBank --> TransactionManager_Retirement_Retirement_cond1 + AsyncMemoryBank_AsyncMemoryBank --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add - TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add - Retirement_Retirement1 --> FRAT_rename + Retirement_Retirement --> FRAT_rename + TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename TransactionManager_ROBAllocation_Renaming --> FRAT_rename - TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Retirement_Retirement3 <--> FIFOLatencyMeasurer2__stop FIFO12_read --> Retirement_Retirement3 Retirement_Retirement3 --> HwExpHistogram9__add CSRRegister7_read --> Retirement_Retirement3 Retirement_Retirement3 --> FetchUnit_resume_from_exception Retirement_Retirement3 <--> ExceptionInformationRegister_clear - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit --> TaggedCounter6__incr - CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush - TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation - Connect_read --> TransactionManager_ROBAllocation_Renaming - TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put - TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start - TransactionManager_ROBAllocation_Renaming --> FIFO1_write - TransactionManager_ROBAllocation_Renaming --> FIFO10_write - TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming - FIFO9_read --> TransactionManager_ROBAllocation_Renaming - TransactionManager_ROBAllocation_Renaming --> Connect_write - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy1 - TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy1 - TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy1 + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2 + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> Semaphore_release + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> Semaphore_release + Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 + Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Predecoder_predecode + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> Predecoder_predecode + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> PredictionChecker_check + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> PredictionChecker_check + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter1__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter1__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter2__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter2__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter3__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write + TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy2 + TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy2 + TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy2 TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond0 --> BasicFifo9_write - TransactionManager_LSUDummy_issue_cond1 --> BasicFifo9_write TransactionManager_LSUDummy_issue_cond2 --> BasicFifo9_write + TransactionManager_LSUDummy_issue_cond1 --> BasicFifo9_write TransactionManager_LSUDummy_issue_cond0 --> FIFO7_write - TransactionManager_LSUDummy_issue_cond1 --> FIFO7_write TransactionManager_LSUDummy_issue_cond2 --> FIFO7_write + TransactionManager_LSUDummy_issue_cond1 --> FIFO7_write TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer3 + TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - TransactionManager_accept_cond0_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 - TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans - LSURequester_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - BasicFifo9_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans - BasicFifo9_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - FIFO7_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans - FIFO7_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - TransactionManager_accept_cond0_accept_cond0_ConnectTrans <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans - Serializer1_Serializer --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans - BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans - BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans - WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - Forwarder1_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans - Forwarder1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - TransactionManager_accept_cond0_accept_cond0_ConnectTrans <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr + CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 + Serializer1_Serializer2 --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 + BasicFifo1_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 + BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + WishboneMaster1_result --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 + WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + Forwarder1_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 + Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond0_accept_cond0_ConnectTrans --> Forwarder7_write - TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> Forwarder7_write + TransactionManager_accept_cond1_ConnectTrans_accept_cond0 --> Forwarder7_write + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write - LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans - LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans + LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 + LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2 - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> Semaphore_release - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> Semaphore_release - Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 - Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> Predecoder_predecode - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Predecoder_predecode - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> PredictionChecker_check - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> PredictionChecker_check - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter1__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter1__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter2__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter2__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter3__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2_cond1 - TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - Serializer1_Serializer1 --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 - FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans - FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write + TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 + LSURequester_accept --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 + LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + BasicFifo9_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 + BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + FIFO7_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 + FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement2 TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2 - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement2 + TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start - TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer2__start + TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write TransactionManager_Retirement_Retirement_cond0 --> FIFO12_write - TransactionManager_Retirement_cond1_Retirement --> FIFO12_write + InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 - InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond1_Retirement + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister6_write + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister9_write TransactionManager_Retirement_Retirement_cond0 --> CSRRegister9_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister9_write + TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry - TransactionManager_Retirement_cond1_Retirement <--> InternalInterruptController_entry + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + Serializer1_Serializer3 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret + TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2_cond1 TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment @@ -1393,8 +1385,16 @@ TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read - TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer2 - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 - TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 - TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> InternalInterruptController_mret + TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer1 + TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation + Connect_read --> TransactionManager_ROBAllocation_Renaming + TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put + TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start + TransactionManager_ROBAllocation_Renaming --> FIFO1_write + TransactionManager_ROBAllocation_Renaming --> FIFO10_write + TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming + FIFO9_read --> TransactionManager_ROBAllocation_Renaming + TransactionManager_ROBAllocation_Renaming --> Connect_write + TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 + FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans + FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans diff --git a/api.html b/api.html index be84b1e13..8d34b75ba 100644 --- a/api.html +++ b/api.html @@ -271,7 +271,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/assumptions.html b/assumptions.html index 5f0973fed..8ecce89d2 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/auto_graph.html b/auto_graph.html index e054a5181..0b06c100a 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -85,26 +85,26 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_WishboneMaster["WishboneMaster"] - WishboneMaster_result["result"] WishboneMaster_request["request"] + WishboneMaster_result["result"] + WishboneMaster_WishboneMaster["WishboneMaster"] subgraph Forwarder["result Forwarder"] Forwarder_read["read"] Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] + WishboneMaster1_request["request"] WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] - WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] Forwarder1_write["write"] Forwarder1_read["read"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_get_read_response["get_read_response"] WishboneMasterAdapter_request_read["request_read"] + WishboneMasterAdapter_get_read_response["get_read_response"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] @@ -116,8 +116,8 @@ end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_request_write["request_write"] - WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_read["request_read"] + WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_get_read_response["get_read_response"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] @@ -131,32 +131,32 @@ end end subgraph CoreFrontend["frontend CoreFrontend"] - CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] CoreFrontend_target_pred_req["target_pred_req"] - CoreFrontend_stall["stall"] CoreFrontend_target_pred_resp["target_pred_resp"] + CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] + CoreFrontend_stall["stall"] subgraph BasicFifo2["instr_buffer BasicFifo"] - BasicFifo2_write["write"] - BasicFifo2_clear["clear"] BasicFifo2_read["read"] + BasicFifo2_clear["clear"] + BasicFifo2_write["write"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end end subgraph ICache["icache ICache"] - ICache_issue_req["issue_req"] - ICache_MemRead["MemRead"] ICache_ICache["ICache"] + ICache_MemRead["MemRead"] + ICache_ICache1["ICache"] ICache_accept_res["accept_res"] ICache_flush["flush"] - ICache_ICache1["ICache"] + ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -179,34 +179,34 @@ HwExpHistogram__add["_add"] end subgraph FIFO["fifo FIFO"] - FIFO_read["read"] FIFO_write["write"] + FIFO_read["read"] end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] ArgumentsToResultsZipper_peek_arg["peek_arg"] - ArgumentsToResultsZipper_read["read"] - ArgumentsToResultsZipper_write_args["write_args"] ArgumentsToResultsZipper_write_results["write_results"] + ArgumentsToResultsZipper_write_args["write_args"] + ArgumentsToResultsZipper_read["read"] subgraph BasicFifo3["fifo BasicFifo"] BasicFifo3_read["read"] - BasicFifo3_write["write"] BasicFifo3_peek["peek"] + BasicFifo3_write["write"] end subgraph Forwarder3["forwarder Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end end subgraph FetchUnit["fetch FetchUnit"] - FetchUnit_Fetch_Stage2["Fetch_Stage2"] + FetchUnit_resume_from_exception["resume_from_exception"] FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] + FetchUnit_resume_from_unsafe["resume_from_unsafe"] FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] - FetchUnit_stall_exception["stall_exception"] FetchUnit_Fetch_Stage1["Fetch_Stage1"] - FetchUnit_resume_from_exception["resume_from_exception"] - FetchUnit_resume_from_unsafe["resume_from_unsafe"] + FetchUnit_stall_exception["stall_exception"] + FetchUnit_Fetch_Stage2["Fetch_Stage2"] FetchUnit_Fetch_Stage0["Fetch_Stage0"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] @@ -215,9 +215,9 @@ HwCounter5__incr["_incr"] end subgraph Serializer["serializer Serializer"] + Serializer_clean["clean"] Serializer_write["write"] Serializer_read["read"] - Serializer_clean["clean"] end subgraph ConnectTrans["serializer_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -227,12 +227,12 @@ BasicFifo4_write["write"] end subgraph Semaphore["req_counter Semaphore"] - Semaphore_acquire["acquire"] Semaphore_release["release"] + Semaphore_acquire["acquire"] end subgraph Pipe["s1_s2_pipe Pipe"] - Pipe_write["write"] Pipe_read["read"] + Pipe_write["write"] end subgraph Predecoder["predecoder_0 Predecoder"] Predecoder_predecode["predecode"] @@ -251,9 +251,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] - Pipe1_read["read"] Pipe1_write["write"] Pipe1_clean["clean"] + Pipe1_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -263,8 +263,8 @@ end end subgraph BasicFifo5["free_rf_fifo BasicFifo"] - BasicFifo5_write["write"] BasicFifo5_read["read"] + BasicFifo5_write["write"] end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] @@ -274,11 +274,11 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_perf["perf"] RegisterFile_write["write"] + RegisterFile_read2["read2"] RegisterFile_free["free"] RegisterFile_read1["read1"] - RegisterFile_read2["read2"] + RegisterFile_perf["perf"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer__start["_start"] TaggedLatencyMeasurer__stop["_stop"] @@ -286,8 +286,8 @@ HwExpHistogram1__add["_add"] end subgraph AsyncMemoryBank["slots AsyncMemoryBank"] - AsyncMemoryBank_read["read"] - AsyncMemoryBank_write["write"] + AsyncMemoryBank_AsyncMemoryBank["AsyncMemoryBank"] + AsyncMemoryBank_AsyncMemoryBank1["AsyncMemoryBank"] end end subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] @@ -295,12 +295,12 @@ end end subgraph ReorderBuffer["ROB ReorderBuffer"] + ReorderBuffer_put["put"] ReorderBuffer_peek["peek"] - ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_retire["retire"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_perf["perf"] - ReorderBuffer_put["put"] + ReorderBuffer_retire["retire"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] FIFOLatencyMeasurer1__start["_start"] FIFOLatencyMeasurer1__stop["_stop"] @@ -317,12 +317,12 @@ end end subgraph ExceptionInformationRegister["exception_information_register ExceptionInformationRegister"] - ExceptionInformationRegister_clear["clear"] ExceptionInformationRegister_report["report"] + ExceptionInformationRegister_clear["clear"] ExceptionInformationRegister_get["get"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] - BasicFifo6_write["write"] BasicFifo6_read["read"] + BasicFifo6_write["write"] end subgraph ConnectTrans1["report_connector ConnectTrans"] ConnectTrans1_ConnectTrans["ConnectTrans"] @@ -352,29 +352,29 @@ end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] RSFuncBlock_update["update"] - RSFuncBlock_insert["insert"] - RSFuncBlock_get_result["get_result"] RSFuncBlock_select["select"] + RSFuncBlock_get_result["get_result"] + RSFuncBlock_insert["insert"] subgraph RS["rs RS"] + RS_perf["perf"] RS_RS["RS"] RS_RS1["RS"] - RS_insert["insert"] - RS_RS2["RS"] RS_update["update"] + RS_RS2["RS"] RS_select["select"] + RS_insert["insert"] + RS_take["take"] RS_RS3["RS"] RS_RS4["RS"] - RS_perf["perf"] - RS_take["take"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__start["_start"] TaggedLatencyMeasurer1__stop["_stop"] + TaggedLatencyMeasurer1__start["_start"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_write["write"] - AsyncMemoryBank1_read["read"] + AsyncMemoryBank1_AsyncMemoryBank["AsyncMemoryBank"] + AsyncMemoryBank1_AsyncMemoryBank1["AsyncMemoryBank"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -388,16 +388,16 @@ TaggedCounter4__incr["_incr"] end subgraph FIFO2["fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO3["fifo FIFO"] FIFO3_read["read"] FIFO3_write["write"] @@ -407,8 +407,8 @@ WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO4["fifo_branch_resolved FIFO"] FIFO4_write["write"] FIFO4_read["read"] @@ -434,8 +434,8 @@ ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -443,12 +443,12 @@ end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] - PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] + PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] PrivilegedFuncUnit_issue["issue"] - PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] + PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] BasicFifo8_read["read"] BasicFifo8_write["write"] @@ -486,26 +486,26 @@ end end subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] - RSFuncBlock1_get_result["get_result"] - RSFuncBlock1_select["select"] RSFuncBlock1_insert["insert"] RSFuncBlock1_update["update"] + RSFuncBlock1_get_result["get_result"] + RSFuncBlock1_select["select"] subgraph FifoRS["rs FifoRS"] - FifoRS_select["select"] - FifoRS_FifoRS["FifoRS"] - FifoRS_update["update"] - FifoRS_insert["insert"] FifoRS_take["take"] + FifoRS_update["update"] + FifoRS_FifoRS["FifoRS"] + FifoRS_select["select"] FifoRS_perf["perf"] + FifoRS_insert["insert"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer2__start["_start"] TaggedLatencyMeasurer2__stop["_stop"] + TaggedLatencyMeasurer2__start["_start"] subgraph HwExpHistogram7["histogram HwExpHistogram"] HwExpHistogram7__add["_add"] end subgraph AsyncMemoryBank2["slots AsyncMemoryBank"] - AsyncMemoryBank2_read["read"] - AsyncMemoryBank2_write["write"] + AsyncMemoryBank2_AsyncMemoryBank["AsyncMemoryBank"] + AsyncMemoryBank2_AsyncMemoryBank1["AsyncMemoryBank"] end end subgraph HwExpHistogram8["perf_num_full HwExpHistogram"] @@ -513,24 +513,24 @@ end end subgraph LSUDummy["func_unit_0 LSUDummy"] - LSUDummy_accept_cond0["accept_cond0"] + LSUDummy_accept["accept"] LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_accept_cond0["accept_cond0"] LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_issue["issue"] - LSUDummy_accept["accept"] LSUDummy_accept_cond1["accept_cond1"] + LSUDummy_issue["issue"] LSUDummy_LSUDummy2["LSUDummy"] subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond0["issue_cond0"] - LSURequester_accept_cond0["accept_cond0"] - LSURequester_accept_cond1["accept_cond1"] LSURequester_issue["issue"] - LSURequester_issue_cond2["issue_cond2"] + LSURequester_accept_cond0["accept_cond0"] LSURequester_accept["accept"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_accept_cond1["accept_cond1"] + LSURequester_issue_cond0["issue_cond0"] + LSURequester_issue_cond2["issue_cond2"] subgraph BasicFifo9["args_fifo BasicFifo"] - BasicFifo9_read["read"] BasicFifo9_write["write"] + BasicFifo9_read["read"] end end subgraph Forwarder6["requests Forwarder"] @@ -542,8 +542,8 @@ FIFO6_write["write"] end subgraph FIFO7["issued FIFO"] - FIFO7_write["write"] FIFO7_read["read"] + FIFO7_write["write"] end subgraph FIFO8["issued_noop FIFO"] FIFO8_read["read"] @@ -556,8 +556,8 @@ subgraph Collector2["collector Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_read["read"] Forwarder7_write["write"] + Forwarder7_read["read"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans10["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -567,10 +567,10 @@ end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_CSRUnit["CSRUnit"] CSRUnit_update["update"] CSRUnit_get_result["get_result"] CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_CSRUnit1["CSRUnit"] CSRUnit_insert["insert"] CSRUnit_select["select"] @@ -626,17 +626,17 @@ end end subgraph AliasedCSR["mstatus AliasedCSR"] - AliasedCSR__fu_write["_fu_write"] AliasedCSR__fu_read["_fu_read"] + AliasedCSR__fu_write["_fu_write"] end subgraph AliasedCSR1["mstatush AliasedCSR"] - AliasedCSR1__fu_read["_fu_read"] AliasedCSR1__fu_write["_fu_write"] + AliasedCSR1__fu_read["_fu_read"] end subgraph CSRRegister6["mcause CSRRegister"] - CSRRegister6__internal_fu_read["_internal_fu_read"] CSRRegister6_write["write"] CSRRegister6__internal_fu_write["_internal_fu_write"] + CSRRegister6__internal_fu_read["_internal_fu_read"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -648,9 +648,9 @@ end end subgraph CSRRegister7["mtvec CSRRegister"] + CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7_read["read"] CSRRegister7__internal_fu_read["_internal_fu_read"] - CSRRegister7__internal_fu_write["_internal_fu_write"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] end @@ -662,9 +662,9 @@ end end subgraph CSRRegister8["mepc CSRRegister"] - CSRRegister8_read["read"] CSRRegister8_write["write"] CSRRegister8__internal_fu_read["_internal_fu_read"] + CSRRegister8_read["read"] CSRRegister8__internal_fu_write["_internal_fu_write"] subgraph MethodMap16["fu_write_map MethodMap"] MethodMap16_method["method"] @@ -677,9 +677,9 @@ end end subgraph CSRRegister9["mtval CSRRegister"] - CSRRegister9__internal_fu_write["_internal_fu_write"] - CSRRegister9_write["write"] CSRRegister9__internal_fu_read["_internal_fu_read"] + CSRRegister9_write["write"] + CSRRegister9__internal_fu_write["_internal_fu_write"] subgraph MethodMap18["fu_write_map MethodMap"] MethodMap18_method["method"] end @@ -691,8 +691,8 @@ end end subgraph CSRRegister10["priv_mode CSRRegister"] - CSRRegister10_read["read"] CSRRegister10_write["write"] + CSRRegister10_read["read"] end subgraph CSRRegister11["mstatus_mie CSRRegister"] CSRRegister11__internal_fu_read["_internal_fu_read"] @@ -711,8 +711,8 @@ end subgraph CSRRegister12["mstatus_mpie CSRRegister"] CSRRegister12__internal_fu_write["_internal_fu_write"] - CSRRegister12__internal_fu_read["_internal_fu_read"] CSRRegister12_read["read"] + CSRRegister12__internal_fu_read["_internal_fu_read"] CSRRegister12_write["write"] subgraph MethodMap24["fu_write_map MethodMap"] MethodMap24_method["method"] @@ -725,10 +725,10 @@ end end subgraph CSRRegister13["mstatus_mpp CSRRegister"] + CSRRegister13__internal_fu_write["_internal_fu_write"] CSRRegister13_read["read"] CSRRegister13_write["write"] CSRRegister13__internal_fu_read["_internal_fu_read"] - CSRRegister13__internal_fu_write["_internal_fu_write"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -740,9 +740,9 @@ end end subgraph CSRRegister14["mstatus_mprv CSRRegister"] + CSRRegister14_write["write"] CSRRegister14__internal_fu_read["_internal_fu_read"] CSRRegister14__internal_fu_write["_internal_fu_write"] - CSRRegister14_write["write"] subgraph MethodMap28["fu_write_map MethodMap"] MethodMap28_method["method"] end @@ -771,17 +771,17 @@ subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister16["register_low CSRRegister"] - CSRRegister16_write["write"] CSRRegister16_read["read"] CSRRegister16__internal_fu_read["_internal_fu_read"] + CSRRegister16_write["write"] subgraph MethodMap33["fu_read_map MethodMap"] MethodMap33_method["method"] end end subgraph CSRRegister17["register_high CSRRegister"] - CSRRegister17_write["write"] - CSRRegister17__internal_fu_read["_internal_fu_read"] CSRRegister17_read["read"] + CSRRegister17__internal_fu_read["_internal_fu_read"] + CSRRegister17_write["write"] subgraph MethodMap35["fu_read_map MethodMap"] MethodMap35_method["method"] end @@ -790,8 +790,8 @@ subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister18["register_low CSRRegister"] - CSRRegister18_write["write"] CSRRegister18_read["read"] + CSRRegister18_write["write"] CSRRegister18__internal_fu_read["_internal_fu_read"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] @@ -799,8 +799,8 @@ end subgraph CSRRegister19["register_high CSRRegister"] CSRRegister19_write["write"] - CSRRegister19_read["read"] CSRRegister19__internal_fu_read["_internal_fu_read"] + CSRRegister19_read["read"] subgraph MethodMap39["fu_read_map MethodMap"] MethodMap39_method["method"] end @@ -808,16 +808,16 @@ end end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] - InternalInterruptController_interrupt_cause["interrupt_cause"] InternalInterruptController_InternalInterruptController["InternalInterruptController"] - InternalInterruptController_mret["mret"] - InternalInterruptController_entry["entry"] InternalInterruptController_InternalInterruptController1["InternalInterruptController"] + InternalInterruptController_interrupt_cause["interrupt_cause"] + InternalInterruptController_entry["entry"] + InternalInterruptController_mret["mret"] InternalInterruptController_InternalInterruptController2["InternalInterruptController"] subgraph CSRRegister20["mie CSRRegister"] + CSRRegister20__internal_fu_write["_internal_fu_write"] CSRRegister20__internal_fu_read["_internal_fu_read"] CSRRegister20_read["read"] - CSRRegister20__internal_fu_write["_internal_fu_write"] subgraph MethodMap40["fu_write_map MethodMap"] MethodMap40_method["method"] end @@ -829,11 +829,11 @@ end end subgraph CSRRegister21["mip CSRRegister"] - CSRRegister21__internal_fu_write["_internal_fu_write"] CSRRegister21_write["write"] CSRRegister21_read["read"] CSRRegister21__internal_fu_read["_internal_fu_read"] CSRRegister21_read_comb["read_comb"] + CSRRegister21__internal_fu_write["_internal_fu_write"] subgraph MethodMap42["fu_write_map MethodMap"] MethodMap42_method["method"] end @@ -846,16 +846,16 @@ end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph MethodProduct1["get_instr MethodProduct"] MethodProduct1_method["method"] end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO9["alloc_rename_buf FIFO"] - FIFO9_write["write"] FIFO9_read["read"] + FIFO9_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -868,8 +868,8 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -891,8 +891,8 @@ subgraph Collector3["FetchResumeKey_unifier Collector"] Collector3_method["method"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_write["write"] Forwarder8_read["read"] + Forwarder8_write["write"] end subgraph ManyToOneConnectTrans3["connect ManyToOneConnectTrans"] subgraph ConnectTrans11["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -908,28 +908,28 @@ ConnectTrans13_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_precommit["precommit"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement["Retirement"] Retirement_Retirement1["Retirement"] - Retirement_Retirement2["Retirement"] Retirement_Retirement_cond1["Retirement_cond1"] - Retirement_core_state["core_state"] + Retirement_Retirement_cond0["Retirement_cond0"] + Retirement_precommit["precommit"] + Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] + Retirement_core_state["core_state"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister22["register_low CSRRegister"] - CSRRegister22__internal_fu_read["_internal_fu_read"] CSRRegister22_write["write"] CSRRegister22_read["read"] + CSRRegister22__internal_fu_read["_internal_fu_read"] subgraph MethodMap45["fu_read_map MethodMap"] MethodMap45_method["method"] end end subgraph CSRRegister23["register_high CSRRegister"] - CSRRegister23__internal_fu_read["_internal_fu_read"] - CSRRegister23_write["write"] CSRRegister23_read["read"] + CSRRegister23_write["write"] + CSRRegister23__internal_fu_read["_internal_fu_read"] subgraph MethodMap47["fu_read_map MethodMap"] MethodMap47_method["method"] end @@ -939,55 +939,55 @@ HwCounter9__incr["_incr"] end subgraph FIFOLatencyMeasurer2["perf_trap_latency FIFOLatencyMeasurer"] - FIFOLatencyMeasurer2__stop["_stop"] FIFOLatencyMeasurer2__start["_start"] + FIFOLatencyMeasurer2__stop["_stop"] subgraph HwExpHistogram9["histogram HwExpHistogram"] HwExpHistogram9__add["_add"] end subgraph FIFO12["fifo FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end end end end end subgraph TransactionManager["transaction_manager TransactionManager"] - TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] - TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_accept_cond0_accept_cond0_ConnectTrans["accept_cond0_accept_cond0_ConnectTrans"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] - TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit["PrivilegedFuncUnit_cond0_PrivilegedFuncUnit"] + TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] - TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_PrivilegedFuncUnit_cond0"] + TransactionManager_accept_cond1_ConnectTrans_accept_cond0["accept_cond1_ConnectTrans_accept_cond0"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0["Fetch_Stage2_Fetch_Stage2_cond0"] - TransactionManager_accept_cond0_accept_cond1_ConnectTrans["accept_cond0_accept_cond1_ConnectTrans"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1["Fetch_Stage2_Fetch_Stage2_cond1"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] + TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] end end Core_InitFreeRFFifo --> BasicFifo5_write -Retirement_Retirement1 --> BasicFifo5_write +Retirement_Retirement --> BasicFifo5_write +TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write -TransactionManager_Retirement_cond1_Retirement --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMasterAdapter_request_read -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Serializer_Serializer1 -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> BasicFifo_write -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMaster_request -WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Forwarder2_write -ICache_ICache1 <--> HwCounter4__incr +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request +WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write +ICache_ICache <--> HwCounter4__incr ArgumentsToResultsZipper_peek_arg --> ICache_MemRead BasicFifo3_peek --> ICache_MemRead ICache_MemRead <--> HwCounter1__incr @@ -995,9 +995,9 @@ ICache_MemRead --> Forwarder3_write ICache_MemRead <--> HwCounter2__incr ICache_MemRead --> SimpleCommonBusCacheRefiller_start_refill -SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache -Forwarder2_read --> ICache_ICache -ICache_ICache <--> HwCounter3__incr +SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 +Forwarder2_read --> ICache_ICache1 +ICache_ICache1 <--> HwCounter3__incr FetchUnit_Fetch_Stage0 <--> Semaphore_acquire FetchUnit_Fetch_Stage0 --> ICache_issue_req FetchUnit_Fetch_Stage0 <--> HwCounter__incr @@ -1032,43 +1032,43 @@ GenericCSRRegisters_GenericCSRRegisters --> CSRRegister18_write CSRRegister19_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister19_write +CSRRegister11_read --> InternalInterruptController_InternalInterruptController CSRRegister11_read --> InternalInterruptController_InternalInterruptController1 -CSRRegister11_read --> InternalInterruptController_InternalInterruptController2 +CSRRegister10_read --> InternalInterruptController_InternalInterruptController CSRRegister10_read --> InternalInterruptController_InternalInterruptController1 -CSRRegister10_read --> InternalInterruptController_InternalInterruptController2 CSRRegister10_read --> WakeupSelect3_WakeupSelect -CSRRegister10_read --> CSRUnit_CSRUnit -CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 +CSRRegister10_read --> CSRUnit_CSRUnit1 CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit -CSRRegister20_read --> InternalInterruptController_InternalInterruptController1 -CSRRegister21_read --> InternalInterruptController_InternalInterruptController1 -CSRRegister21_read_comb --> InternalInterruptController_InternalInterruptController -InternalInterruptController_InternalInterruptController --> CSRRegister21_write -InternalInterruptController_InternalInterruptController2 --> CSRRegister11_write -InternalInterruptController_InternalInterruptController2 --> CSRRegister12_write -InternalInterruptController_InternalInterruptController2 --> CSRRegister13_write -InternalInterruptController_InternalInterruptController2 --> CSRRegister10_write -CSRRegister12_read --> InternalInterruptController_InternalInterruptController2 -CSRRegister13_read --> InternalInterruptController_InternalInterruptController2 -InternalInterruptController_InternalInterruptController2 --> CSRRegister14_write +CSRRegister20_read --> InternalInterruptController_InternalInterruptController +CSRRegister21_read --> InternalInterruptController_InternalInterruptController +CSRRegister21_read_comb --> InternalInterruptController_InternalInterruptController2 +InternalInterruptController_InternalInterruptController2 --> CSRRegister21_write +InternalInterruptController_InternalInterruptController1 --> CSRRegister11_write +InternalInterruptController_InternalInterruptController1 --> CSRRegister12_write +InternalInterruptController_InternalInterruptController1 --> CSRRegister13_write +InternalInterruptController_InternalInterruptController1 --> CSRRegister10_write +CSRRegister12_read --> InternalInterruptController_InternalInterruptController1 +CSRRegister13_read --> InternalInterruptController_InternalInterruptController1 +InternalInterruptController_InternalInterruptController1 --> CSRRegister14_write MethodProduct1_method --> RegAllocation_RegAllocation Pipe1_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation <--> CoreInstructionCounter_increment BasicFifo5_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO9_write -FIFO10_read --> RSSelection_RSSelection FIFO10_read --> RSSelection_RSSelection1 FIFO10_read --> RSSelection_RSSelection2 -RSFuncBlock_select --> RSSelection_RSSelection -RS_select --> RSSelection_RSSelection -RSSelection_RSSelection --> FIFO11_write +FIFO10_read --> RSSelection_RSSelection +RSFuncBlock_select --> RSSelection_RSSelection1 +RS_select --> RSSelection_RSSelection1 RSSelection_RSSelection1 --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write -RSFuncBlock1_select --> RSSelection_RSSelection1 -FifoRS_select --> RSSelection_RSSelection1 -RSSelection_RSSelection2 <--> CSRUnit_select +RSSelection_RSSelection --> FIFO11_write +RSFuncBlock1_select --> RSSelection_RSSelection2 +FifoRS_select --> RSSelection_RSSelection2 +RSSelection_RSSelection <--> CSRUnit_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -1076,11 +1076,11 @@ RSInsertion_RSInsertion --> RSFuncBlock_insert RSInsertion_RSInsertion --> RS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer1__start -RSInsertion_RSInsertion --> AsyncMemoryBank1_write +RSInsertion_RSInsertion --> AsyncMemoryBank1_AsyncMemoryBank RSInsertion_RSInsertion --> RSFuncBlock1_insert RSInsertion_RSInsertion --> FifoRS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer2__start -RSInsertion_RSInsertion --> AsyncMemoryBank2_write +RSInsertion_RSInsertion --> AsyncMemoryBank2_AsyncMemoryBank RSInsertion_RSInsertion --> CSRUnit_insert BasicFifo6_read --> ConnectTrans1_ConnectTrans ConnectTrans1_ConnectTrans --> ExceptionInformationRegister_report @@ -1102,7 +1102,7 @@ ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done ResultAnnouncement_ResultAnnouncement --> RegisterFile_write ResultAnnouncement_ResultAnnouncement --> TaggedLatencyMeasurer__start -ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_write +ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_AsyncMemoryBank1 ResultAnnouncement_ResultAnnouncement --> MethodProduct_method ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update @@ -1110,7 +1110,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add -RS_RS1 --> WakeupSelect_WakeupSelect +RS_RS2 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -1121,11 +1121,11 @@ WakeupSelect2_WakeupSelect --> TaggedLatencyMeasurer1__stop WakeupSelect3_WakeupSelect --> TaggedLatencyMeasurer1__stop WakeupSelect4_WakeupSelect --> TaggedLatencyMeasurer1__stop -AsyncMemoryBank1_read --> WakeupSelect_WakeupSelect -AsyncMemoryBank1_read --> WakeupSelect1_WakeupSelect -AsyncMemoryBank1_read --> WakeupSelect2_WakeupSelect -AsyncMemoryBank1_read --> WakeupSelect3_WakeupSelect -AsyncMemoryBank1_read --> WakeupSelect4_WakeupSelect +AsyncMemoryBank1_AsyncMemoryBank1 --> WakeupSelect_WakeupSelect +AsyncMemoryBank1_AsyncMemoryBank1 --> WakeupSelect1_WakeupSelect +AsyncMemoryBank1_AsyncMemoryBank1 --> WakeupSelect2_WakeupSelect +AsyncMemoryBank1_AsyncMemoryBank1 --> WakeupSelect3_WakeupSelect +AsyncMemoryBank1_AsyncMemoryBank1 --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> HwExpHistogram5__add WakeupSelect1_WakeupSelect --> HwExpHistogram5__add WakeupSelect2_WakeupSelect --> HwExpHistogram5__add @@ -1134,22 +1134,22 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter4__incr WakeupSelect_WakeupSelect --> FIFO2_write -RS_RS3 --> WakeupSelect1_WakeupSelect +RS_RS --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write -RS_RS2 --> WakeupSelect2_WakeupSelect +RS_RS3 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write WakeupSelect2_WakeupSelect --> TaggedCounter5__incr -RS_RS --> WakeupSelect3_WakeupSelect +RS_RS1 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> BasicFifo6_write ConnectTrans7_ConnectTrans --> BasicFifo6_write ConnectTrans9_ConnectTrans --> BasicFifo6_write ConnectTrans4_ConnectTrans --> BasicFifo6_write -TransactionManager_accept_cond0_accept_cond0_ConnectTrans --> BasicFifo6_write -TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> BasicFifo6_write +TransactionManager_accept_cond1_ConnectTrans_accept_cond0 --> BasicFifo6_write +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write TransactionManager_accept_cond1_ConnectTrans --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write RS_RS4 --> WakeupSelect4_WakeupSelect @@ -1175,129 +1175,129 @@ CSRRegister8_read --> ConnectTrans9_ConnectTrans ConnectTrans9_ConnectTrans --> BasicFifo8_write FifoRS_perf --> HwExpHistogram8__add -Forwarder6_read --> LSUDummy_LSUDummy +Forwarder6_read --> LSUDummy_LSUDummy1 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 -Forwarder6_read --> TransactionManager_LSUDummy_issue_cond1 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 -LSUDummy_LSUDummy --> FIFO6_write +Forwarder6_read --> TransactionManager_LSUDummy_issue_cond1 +LSUDummy_LSUDummy1 --> FIFO6_write WakeupSelect5_WakeupSelect --> FIFO6_write TransactionManager_LSUDummy_issue_cond0 --> FIFO6_write -TransactionManager_LSUDummy_issue_cond1 --> FIFO6_write TransactionManager_LSUDummy_issue_cond2 --> FIFO6_write -LSUDummy_LSUDummy --> FIFO8_write +TransactionManager_LSUDummy_issue_cond1 --> FIFO6_write +LSUDummy_LSUDummy1 --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write -TransactionManager_LSUDummy_issue_cond1 --> FIFO8_write TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write -Retirement_precommit --> LSUDummy_LSUDummy2 -Retirement_precommit --> CSRUnit_CSRUnit1 -Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 +TransactionManager_LSUDummy_issue_cond1 --> FIFO8_write +Retirement_precommit --> LSUDummy_LSUDummy +Retirement_precommit --> CSRUnit_CSRUnit Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit -ReorderBuffer_peek --> LSUDummy_LSUDummy2 -ReorderBuffer_peek --> CSRUnit_CSRUnit1 -ReorderBuffer_peek --> Retirement_Retirement +ReorderBuffer_peek --> LSUDummy_LSUDummy +ReorderBuffer_peek --> CSRUnit_CSRUnit ReorderBuffer_peek --> Retirement_Retirement1 -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 +ReorderBuffer_peek --> Retirement_Retirement ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 -ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop -AsyncMemoryBank2_read --> WakeupSelect5_WakeupSelect +AsyncMemoryBank2_AsyncMemoryBank1 --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> HwExpHistogram7__add WakeupSelect5_WakeupSelect --> LSUDummy_issue WakeupSelect5_WakeupSelect --> Forwarder6_write -MethodMap1_method --> CSRUnit_CSRUnit -CSRRegister__internal_fu_read --> CSRUnit_CSRUnit -MethodMap3_method --> CSRUnit_CSRUnit -CSRRegister1__internal_fu_read --> CSRUnit_CSRUnit -MethodMap5_method --> CSRUnit_CSRUnit -CSRRegister2__internal_fu_read --> CSRUnit_CSRUnit -MethodMap7_method --> CSRUnit_CSRUnit -CSRRegister3__internal_fu_read --> CSRUnit_CSRUnit -MethodMap9_method --> CSRUnit_CSRUnit -CSRRegister4__internal_fu_read --> CSRUnit_CSRUnit -CSRUnit_CSRUnit --> MethodFilter4_method -CSRUnit_CSRUnit --> MethodMap8_method -CSRUnit_CSRUnit --> CSRRegister4__internal_fu_write -MethodMap11_method --> CSRUnit_CSRUnit -CSRRegister5__internal_fu_read --> CSRUnit_CSRUnit -AliasedCSR__fu_read --> CSRUnit_CSRUnit -MethodMap23_method --> CSRUnit_CSRUnit -CSRRegister11__internal_fu_read --> CSRUnit_CSRUnit -MethodMap25_method --> CSRUnit_CSRUnit -CSRRegister12__internal_fu_read --> CSRUnit_CSRUnit -MethodMap27_method --> CSRUnit_CSRUnit -CSRRegister13__internal_fu_read --> CSRUnit_CSRUnit -MethodMap29_method --> CSRUnit_CSRUnit -CSRRegister14__internal_fu_read --> CSRUnit_CSRUnit -MethodMap31_method --> CSRUnit_CSRUnit -CSRRegister15__internal_fu_read --> CSRUnit_CSRUnit -CSRUnit_CSRUnit --> AliasedCSR__fu_write -CSRUnit_CSRUnit --> MethodFilter11_method -CSRUnit_CSRUnit --> MethodMap22_method -CSRUnit_CSRUnit --> CSRRegister11__internal_fu_write -CSRUnit_CSRUnit --> MethodFilter12_method -CSRUnit_CSRUnit --> MethodMap24_method -CSRUnit_CSRUnit --> CSRRegister12__internal_fu_write -CSRUnit_CSRUnit --> MethodFilter13_method -CSRUnit_CSRUnit --> MethodMap26_method -CSRUnit_CSRUnit --> CSRRegister13__internal_fu_write -CSRUnit_CSRUnit --> MethodFilter14_method -CSRUnit_CSRUnit --> MethodMap28_method -CSRUnit_CSRUnit --> CSRRegister14__internal_fu_write -CSRUnit_CSRUnit --> MethodFilter15_method -CSRUnit_CSRUnit --> MethodMap30_method -CSRUnit_CSRUnit --> CSRRegister15__internal_fu_write -AliasedCSR1__fu_read --> CSRUnit_CSRUnit -CSRUnit_CSRUnit --> AliasedCSR1__fu_write -MethodMap13_method --> CSRUnit_CSRUnit -CSRRegister6__internal_fu_read --> CSRUnit_CSRUnit -CSRUnit_CSRUnit --> MethodFilter6_method -CSRUnit_CSRUnit --> MethodMap12_method -CSRUnit_CSRUnit --> CSRRegister6__internal_fu_write -MethodMap15_method --> CSRUnit_CSRUnit -CSRRegister7__internal_fu_read --> CSRUnit_CSRUnit -CSRUnit_CSRUnit --> MethodFilter7_method -CSRUnit_CSRUnit --> MethodMap14_method -CSRUnit_CSRUnit --> CSRRegister7__internal_fu_write -MethodMap17_method --> CSRUnit_CSRUnit -CSRRegister8__internal_fu_read --> CSRUnit_CSRUnit -CSRUnit_CSRUnit --> MethodFilter8_method -CSRUnit_CSRUnit --> MethodMap16_method -CSRUnit_CSRUnit --> CSRRegister8__internal_fu_write -MethodMap19_method --> CSRUnit_CSRUnit -CSRRegister9__internal_fu_read --> CSRUnit_CSRUnit -CSRUnit_CSRUnit --> MethodFilter9_method -CSRUnit_CSRUnit --> MethodMap18_method -CSRUnit_CSRUnit --> CSRRegister9__internal_fu_write -MethodMap33_method --> CSRUnit_CSRUnit -CSRRegister16__internal_fu_read --> CSRUnit_CSRUnit -MethodMap35_method --> CSRUnit_CSRUnit -CSRRegister17__internal_fu_read --> CSRUnit_CSRUnit -MethodMap37_method --> CSRUnit_CSRUnit -CSRRegister18__internal_fu_read --> CSRUnit_CSRUnit -MethodMap39_method --> CSRUnit_CSRUnit -CSRRegister19__internal_fu_read --> CSRUnit_CSRUnit -MethodMap41_method --> CSRUnit_CSRUnit -CSRRegister20__internal_fu_read --> CSRUnit_CSRUnit -CSRUnit_CSRUnit --> MethodFilter20_method -CSRUnit_CSRUnit --> MethodMap40_method -CSRUnit_CSRUnit --> CSRRegister20__internal_fu_write -MethodMap43_method --> CSRUnit_CSRUnit -CSRRegister21__internal_fu_read --> CSRUnit_CSRUnit -CSRUnit_CSRUnit --> MethodFilter21_method -CSRUnit_CSRUnit --> MethodMap42_method -CSRUnit_CSRUnit --> CSRRegister21__internal_fu_write -MethodMap45_method --> CSRUnit_CSRUnit -CSRRegister22__internal_fu_read --> CSRUnit_CSRUnit -MethodMap47_method --> CSRUnit_CSRUnit -CSRRegister23__internal_fu_read --> CSRUnit_CSRUnit +MethodMap1_method --> CSRUnit_CSRUnit1 +CSRRegister__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap3_method --> CSRUnit_CSRUnit1 +CSRRegister1__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap5_method --> CSRUnit_CSRUnit1 +CSRRegister2__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap7_method --> CSRUnit_CSRUnit1 +CSRRegister3__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap9_method --> CSRUnit_CSRUnit1 +CSRRegister4__internal_fu_read --> CSRUnit_CSRUnit1 +CSRUnit_CSRUnit1 --> MethodFilter4_method +CSRUnit_CSRUnit1 --> MethodMap8_method +CSRUnit_CSRUnit1 --> CSRRegister4__internal_fu_write +MethodMap11_method --> CSRUnit_CSRUnit1 +CSRRegister5__internal_fu_read --> CSRUnit_CSRUnit1 +AliasedCSR__fu_read --> CSRUnit_CSRUnit1 +MethodMap23_method --> CSRUnit_CSRUnit1 +CSRRegister11__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap25_method --> CSRUnit_CSRUnit1 +CSRRegister12__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap27_method --> CSRUnit_CSRUnit1 +CSRRegister13__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap29_method --> CSRUnit_CSRUnit1 +CSRRegister14__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap31_method --> CSRUnit_CSRUnit1 +CSRRegister15__internal_fu_read --> CSRUnit_CSRUnit1 +CSRUnit_CSRUnit1 --> AliasedCSR__fu_write +CSRUnit_CSRUnit1 --> MethodFilter11_method +CSRUnit_CSRUnit1 --> MethodMap22_method +CSRUnit_CSRUnit1 --> CSRRegister11__internal_fu_write +CSRUnit_CSRUnit1 --> MethodFilter12_method +CSRUnit_CSRUnit1 --> MethodMap24_method +CSRUnit_CSRUnit1 --> CSRRegister12__internal_fu_write +CSRUnit_CSRUnit1 --> MethodFilter13_method +CSRUnit_CSRUnit1 --> MethodMap26_method +CSRUnit_CSRUnit1 --> CSRRegister13__internal_fu_write +CSRUnit_CSRUnit1 --> MethodFilter14_method +CSRUnit_CSRUnit1 --> MethodMap28_method +CSRUnit_CSRUnit1 --> CSRRegister14__internal_fu_write +CSRUnit_CSRUnit1 --> MethodFilter15_method +CSRUnit_CSRUnit1 --> MethodMap30_method +CSRUnit_CSRUnit1 --> CSRRegister15__internal_fu_write +AliasedCSR1__fu_read --> CSRUnit_CSRUnit1 +CSRUnit_CSRUnit1 --> AliasedCSR1__fu_write +MethodMap13_method --> CSRUnit_CSRUnit1 +CSRRegister6__internal_fu_read --> CSRUnit_CSRUnit1 +CSRUnit_CSRUnit1 --> MethodFilter6_method +CSRUnit_CSRUnit1 --> MethodMap12_method +CSRUnit_CSRUnit1 --> CSRRegister6__internal_fu_write +MethodMap15_method --> CSRUnit_CSRUnit1 +CSRRegister7__internal_fu_read --> CSRUnit_CSRUnit1 +CSRUnit_CSRUnit1 --> MethodFilter7_method +CSRUnit_CSRUnit1 --> MethodMap14_method +CSRUnit_CSRUnit1 --> CSRRegister7__internal_fu_write +MethodMap17_method --> CSRUnit_CSRUnit1 +CSRRegister8__internal_fu_read --> CSRUnit_CSRUnit1 +CSRUnit_CSRUnit1 --> MethodFilter8_method +CSRUnit_CSRUnit1 --> MethodMap16_method +CSRUnit_CSRUnit1 --> CSRRegister8__internal_fu_write +MethodMap19_method --> CSRUnit_CSRUnit1 +CSRRegister9__internal_fu_read --> CSRUnit_CSRUnit1 +CSRUnit_CSRUnit1 --> MethodFilter9_method +CSRUnit_CSRUnit1 --> MethodMap18_method +CSRUnit_CSRUnit1 --> CSRRegister9__internal_fu_write +MethodMap33_method --> CSRUnit_CSRUnit1 +CSRRegister16__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap35_method --> CSRUnit_CSRUnit1 +CSRRegister17__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap37_method --> CSRUnit_CSRUnit1 +CSRRegister18__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap39_method --> CSRUnit_CSRUnit1 +CSRRegister19__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap41_method --> CSRUnit_CSRUnit1 +CSRRegister20__internal_fu_read --> CSRUnit_CSRUnit1 +CSRUnit_CSRUnit1 --> MethodFilter20_method +CSRUnit_CSRUnit1 --> MethodMap40_method +CSRUnit_CSRUnit1 --> CSRRegister20__internal_fu_write +MethodMap43_method --> CSRUnit_CSRUnit1 +CSRRegister21__internal_fu_read --> CSRUnit_CSRUnit1 +CSRUnit_CSRUnit1 --> MethodFilter21_method +CSRUnit_CSRUnit1 --> MethodMap42_method +CSRUnit_CSRUnit1 --> CSRRegister21__internal_fu_write +MethodMap45_method --> CSRUnit_CSRUnit1 +CSRRegister22__internal_fu_read --> CSRUnit_CSRUnit1 +MethodMap47_method --> CSRUnit_CSRUnit1 +CSRRegister23__internal_fu_read --> CSRUnit_CSRUnit1 ConnectTrans2_ConnectTrans --> Forwarder4_write ConnectTrans3_ConnectTrans --> Forwarder4_write ConnectTrans4_ConnectTrans --> Forwarder4_write @@ -1308,160 +1308,152 @@ Collector2_method --> ConnectTrans3_ConnectTrans Forwarder7_read --> ConnectTrans3_ConnectTrans CSRUnit_get_result --> ConnectTrans4_ConnectTrans -ExceptionInformationRegister_get --> Retirement_Retirement +ExceptionInformationRegister_get --> Retirement_Retirement1 +ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond1 ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond0 -ExceptionInformationRegister_get --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement1 <--> ReorderBuffer_retire +Retirement_Retirement <--> ReorderBuffer_retire +TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire -TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire -Retirement_Retirement1 <--> FIFOLatencyMeasurer1__stop +Retirement_Retirement <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop -TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer1__stop -FIFO1_read --> Retirement_Retirement1 +FIFO1_read --> Retirement_Retirement +FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 -FIFO1_read --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement1 --> HwExpHistogram3__add +Retirement_Retirement --> HwExpHistogram3__add +TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add -TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram3__add -CoreInstructionCounter_decrement --> Retirement_Retirement1 +CoreInstructionCounter_decrement --> Retirement_Retirement +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement -RRAT_peek --> Retirement_Retirement1 -RRAT_peek --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement1 --> RegisterFile_free +RRAT_peek --> Retirement_Retirement +RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement --> RegisterFile_free +TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free -TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free -Retirement_Retirement1 --> TaggedLatencyMeasurer__stop +Retirement_Retirement --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop -TransactionManager_Retirement_cond1_Retirement --> TaggedLatencyMeasurer__stop -AsyncMemoryBank_read --> Retirement_Retirement1 -AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0 -AsyncMemoryBank_read --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement1 --> HwExpHistogram1__add +AsyncMemoryBank_AsyncMemoryBank --> Retirement_Retirement +AsyncMemoryBank_AsyncMemoryBank --> TransactionManager_Retirement_Retirement_cond1 +AsyncMemoryBank_AsyncMemoryBank --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement --> HwExpHistogram1__add +TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add -TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add -Retirement_Retirement1 --> FRAT_rename +Retirement_Retirement --> FRAT_rename +TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename TransactionManager_ROBAllocation_Renaming --> FRAT_rename -TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Retirement_Retirement3 <--> FIFOLatencyMeasurer2__stop FIFO12_read --> Retirement_Retirement3 Retirement_Retirement3 --> HwExpHistogram9__add CSRRegister7_read --> Retirement_Retirement3 Retirement_Retirement3 --> FetchUnit_resume_from_exception Retirement_Retirement3 <--> ExceptionInformationRegister_clear -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit --> TaggedCounter6__incr -CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 -CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush -TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation -Connect_read --> TransactionManager_ROBAllocation_Renaming -TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put -TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start -TransactionManager_ROBAllocation_Renaming --> FIFO1_write -TransactionManager_ROBAllocation_Renaming --> FIFO10_write -TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming -FIFO9_read --> TransactionManager_ROBAllocation_Renaming -TransactionManager_ROBAllocation_Renaming --> Connect_write -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy1 -TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy1 -TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy1 +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2 +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> Semaphore_release +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> Semaphore_release +Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 +Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Predecoder_predecode +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> Predecoder_predecode +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> PredictionChecker_check +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> PredictionChecker_check +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter1__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter1__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter2__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter2__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter3__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write +TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy2 +TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy2 +TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy2 TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond0 --> BasicFifo9_write -TransactionManager_LSUDummy_issue_cond1 --> BasicFifo9_write TransactionManager_LSUDummy_issue_cond2 --> BasicFifo9_write +TransactionManager_LSUDummy_issue_cond1 --> BasicFifo9_write TransactionManager_LSUDummy_issue_cond0 --> FIFO7_write -TransactionManager_LSUDummy_issue_cond1 --> FIFO7_write TransactionManager_LSUDummy_issue_cond2 --> FIFO7_write +TransactionManager_LSUDummy_issue_cond1 --> FIFO7_write TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write -TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer3 +TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -TransactionManager_accept_cond0_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 -TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond0 -LSURequester_accept --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans -LSURequester_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -BasicFifo9_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans -BasicFifo9_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -FIFO7_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans -FIFO7_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -TransactionManager_accept_cond0_accept_cond0_ConnectTrans <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans -Serializer1_Serializer --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans -BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans -BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans -WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -Forwarder1_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans -Forwarder1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -TransactionManager_accept_cond0_accept_cond0_ConnectTrans <--> ConnectTrans10_ConnectTrans -TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr +CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 +CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 +Serializer1_Serializer2 --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 +BasicFifo1_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 +BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +WishboneMaster1_result --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 +WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +Forwarder1_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 +Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans -TransactionManager_accept_cond0_accept_cond0_ConnectTrans --> Forwarder7_write -TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> Forwarder7_write +TransactionManager_accept_cond1_ConnectTrans_accept_cond0 --> Forwarder7_write +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write -LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans -LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans +LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 +LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2 -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> Semaphore_release -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> Semaphore_release -Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 -Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> Predecoder_predecode -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Predecoder_predecode -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> PredictionChecker_check -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> PredictionChecker_check -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter1__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter1__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter2__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter2__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter3__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2_cond1 -TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -Serializer1_Serializer1 --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 -FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans -FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write +TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 +LSURequester_accept --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 +LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +BasicFifo9_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 +BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +FIFO7_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 +FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement2 TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2 -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement2 +TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start -TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer2__start +TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write TransactionManager_Retirement_Retirement_cond0 --> FIFO12_write -TransactionManager_Retirement_cond1_Retirement --> FIFO12_write +InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 -InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond1_Retirement +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister6_write +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister9_write TransactionManager_Retirement_Retirement_cond0 --> CSRRegister9_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister9_write +TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry -TransactionManager_Retirement_cond1_Retirement <--> InternalInterruptController_entry +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +Serializer1_Serializer3 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret +TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2_cond1 TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment @@ -1472,11 +1464,19 @@ TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read -TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer2 -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 -TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 -TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> InternalInterruptController_mret +TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer1 +TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation +Connect_read --> TransactionManager_ROBAllocation_Renaming +TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put +TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start +TransactionManager_ROBAllocation_Renaming --> FIFO1_write +TransactionManager_ROBAllocation_Renaming --> FIFO10_write +TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming +FIFO9_read --> TransactionManager_ROBAllocation_Renaming +TransactionManager_ROBAllocation_Renaming --> Connect_write +TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 +FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans +FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans @@ -1487,7 +1487,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/components/icache.html b/components/icache.html index 57dbfc35e..357f17b9e 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.arch.html b/coreblocks.arch.html index 2a4542806..82a5a3f3a 100644 --- a/coreblocks.arch.html +++ b/coreblocks.arch.html @@ -92,7 +92,7 @@

Submodules
class coreblocks.arch.csr_address.CSRAddress
-

Bases: IntEnum

+

Bases: IntEnum

COREBLOCKS_TEST_CSR = 2047
@@ -2342,7 +2342,7 @@

Submodules
class coreblocks.arch.isa_consts.ExceptionCause
-

Bases: IntEnum

+

Bases: IntEnum

BREAKPOINT = 3
@@ -2423,7 +2423,7 @@

Submodules
class coreblocks.arch.isa_consts.FenceFm
-

Bases: IntEnum

+

Bases: IntEnum

NONE = 0
@@ -2444,7 +2444,7 @@

Submodules
class coreblocks.arch.isa_consts.FenceTarget
-

Bases: IntFlag

+

Bases: IntFlag

DEV_I = 8
@@ -2475,7 +2475,7 @@

Submodules
class coreblocks.arch.isa_consts.Funct12
-

Bases: IntEnum

+

Bases: IntEnum

CLZ = 1536
@@ -2556,7 +2556,7 @@

Submodules
class coreblocks.arch.isa_consts.Funct3
-

Bases: IntEnum

+

Bases: IntEnum

ADD = 0
@@ -2922,7 +2922,7 @@

Submodules
class coreblocks.arch.isa_consts.Funct7
-

Bases: IntEnum

+

Bases: IntEnum

ADD = 0
@@ -3175,7 +3175,7 @@

Submodules
class coreblocks.arch.isa_consts.Opcode
-

Bases: IntEnum

+

Bases: IntEnum

AUIPC = 5
@@ -3266,7 +3266,7 @@

Submodules
class coreblocks.arch.isa_consts.PrivilegeLevel
-

Bases: IntEnum

+

Bases: IntEnum

MACHINE = 3
@@ -3292,7 +3292,7 @@

Submodules
class coreblocks.arch.isa_consts.Registers
-

Bases: IntEnum

+

Bases: IntEnum

A0 = 10
@@ -3628,7 +3628,7 @@

Submodules
class coreblocks.arch.isa_consts.XlenEncoding
-

Bases: IntEnum

+

Bases: IntEnum

W128 = 3
@@ -3702,22 +3702,22 @@

Submodules
-static is_branch(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
+static is_branch(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value

-static is_jal(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
+static is_jal(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
-static is_jalr(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
+static is_jalr(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
-static valid(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
+static valid(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value

@@ -3923,7 +3923,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.backend.html b/coreblocks.backend.html index 461322b46..3d64a20be 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -165,7 +165,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index dd3a43902..9be514b55 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -124,12 +124,12 @@

Submodules
-deserialize_addr(raw_addr: Value) → dict[str, amaranth.hdl._ast.Value]
+deserialize_addr(raw_addr: Value) → dict[str, amaranth.hdl._ast.Value]

-serialize_addr(addr: View) → Value
+serialize_addr(addr: View) → Value

@@ -241,7 +241,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index 0a39d01d5..c87624e5a 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -157,7 +157,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index 169ea8d48..c9f58b7a9 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -280,19 +280,19 @@

Submodules
-decompr_reg(rvc_reg: Value) → Value
+decompr_reg(rvc_reg: Value) → Value

-instr_mux(sel: Value, inputs: list[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]) → tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]
+instr_mux(sel: Value, inputs: list[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]) → tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]

-coreblocks.frontend.decoder.rvc.is_instr_compressed(instr: Value) → Value
+coreblocks.frontend.decoder.rvc.is_instr_compressed(instr: Value) → Value
@@ -313,7 +313,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index a4173a3c9..56a7c7447 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -187,7 +187,7 @@

Submodules
-__init__(width: int, elem_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]) → None
+__init__(width: int, elem_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]) → None

@@ -210,7 +210,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index b5c897c62..7cce13bb0 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -151,19 +151,19 @@

Submodules
-fb_addr(pc: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
+fb_addr(pc: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value

Returns the fetch block address of a given PC.

-fb_instr_idx(pc: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
+fb_instr_idx(pc: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value

Returns the index of an instruction in a fetch block for a given instruction PC.

-pc_from_fb(fb_addr: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, fb_instr_idx: int | amaranth.hdl._ast.Value) → Value
+pc_from_fb(fb_addr: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, fb_instr_idx: int | amaranth.hdl._ast.Value) → Value

For a given fetch block address and an instruction index, returns the instruction’s PC.

@@ -187,7 +187,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index ffdac250a..5d0ded568 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -246,7 +246,7 @@

Submodules
-coreblocks.func_blocks.fu.div_unit.get_input(arg: View) → tuple[amaranth.hdl._ast.Value, amaranth.hdl._ast.Value]
+coreblocks.func_blocks.fu.div_unit.get_input(arg: View) → tuple[amaranth.hdl._ast.Value, amaranth.hdl._ast.Value]

@@ -886,7 +886,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.func_blocks.fu.lsu.html b/coreblocks.func_blocks.fu.lsu.html index 02302ade8..31f588d0c 100644 --- a/coreblocks.func_blocks.fu.lsu.html +++ b/coreblocks.func_blocks.fu.lsu.html @@ -175,22 +175,22 @@

Submodules
-check_align(m: TModule, funct3: Value, addr: Value)
+check_align(m: TModule, funct3: Value, addr: Value)

-postprocess_load_data(m: ModuleLike, funct3: Value, raw_data: Value, addr: Value)
+postprocess_load_data(m: ModuleLike, funct3: Value, raw_data: Value, addr: Value)
-prepare_bytes_mask(m: ModuleLike, funct3: Value, addr: Value) → Signal
+prepare_bytes_mask(m: ModuleLike, funct3: Value, addr: Value) → Signal
-prepare_data_to_save(m: ModuleLike, funct3: Value, raw_data: Value, addr: Value)
+prepare_data_to_save(m: ModuleLike, funct3: Value, raw_data: Value, addr: Value)
@@ -224,7 +224,7 @@

Submodules
class coreblocks.func_blocks.fu.lsu.pma.PMALayout
-

Bases: StructLayout

+

Bases: StructLayout

__init__()
@@ -290,7 +290,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index 23eda010b..9284ba574 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -260,7 +260,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index b1338c28b..c88fe58fa 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -150,7 +150,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index 70abca79a..24e987b3a 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -164,7 +164,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.html b/coreblocks.html index d58c70df8..428341a1e 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -232,7 +232,7 @@

Submodules
class coreblocks.core.Core
-

Bases: Component

+

Bases: Component

__init__(*, gen_params: GenParams)
@@ -268,7 +268,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.params.html b/coreblocks.params.html index 5b4993466..e24bc8f59 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -208,7 +208,7 @@

SubmodulesInstructionFunct3Type

-__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -308,7 +308,7 @@

SubmodulesInstructionFunct3Type

-__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -413,7 +413,7 @@

SubmodulesRISCVInstr

-__init__(opcode: Opcode, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -473,7 +473,7 @@

Submodules
class coreblocks.params.instr.RISCVInstr
-

Bases: ABC, ValueCastable

+

Bases: ABC, ValueCastable

__init__(opcode: Opcode)
@@ -482,7 +482,7 @@

Submodules
as_value()
-

Convert self to a value-like object.

+

Convert self to a value-like object.

This method is called by the Amaranth language to convert self to a concrete Value. It will usually return a Value object, but it may also return another value-like object to delegate its functionality.

@@ -556,7 +556,7 @@

Submodules
Returns
-
A shape-like object.
+
A shape-like object.
Raises
@@ -579,7 +579,7 @@

SubmodulesInstructionFunct3Type, InstructionFunct7Type

-__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct7: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct7: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -668,7 +668,7 @@

SubmodulesInstructionFunct3Type

-__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -757,7 +757,7 @@

SubmodulesRISCVInstr

-__init__(opcode: Opcode, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -832,7 +832,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index eac6c3d85..94305f429 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -123,7 +123,7 @@

Submodules
class coreblocks.peripherals.axi_lite.AXILiteMaster
-

Bases: Component

+

Bases: Component

AXI-Lite master interface.

Parameters
@@ -209,7 +209,7 @@

Submodules
class coreblocks.peripherals.axi_lite.AXILiteSignature
-

Bases: Signature

+

Bases: Signature

AXI-Lite bus signature

Parameters
@@ -375,7 +375,7 @@

Submodules
class coreblocks.peripherals.wishbone.PipelinedWishboneMaster
-

Bases: Component

+

Bases: Component

Pipelined Wishbone bus master interface.

Parameters
@@ -423,7 +423,7 @@

Submodules
class coreblocks.peripherals.wishbone.WishboneArbiter
-

Bases: Component

+

Bases: Component

Wishbone Arbiter.

Connects multiple masters to one slave. Bus is requested by asserting CYC signal and is granted to masters in a round robin manner.

@@ -536,7 +536,7 @@

Submodules
class coreblocks.peripherals.wishbone.WishboneMaster
-

Bases: Component

+

Bases: Component

Wishbone bus master interface.

Parameters
@@ -605,7 +605,7 @@

Submodules
class coreblocks.peripherals.wishbone.WishboneMemorySlave
-

Bases: Component

+

Bases: Component

Wishbone slave with memory Wishbone slave interface with addressable memory underneath.

@@ -641,7 +641,7 @@

Submodules
class coreblocks.peripherals.wishbone.WishboneMuxer
-

Bases: Component

+

Bases: Component

Wishbone Muxer.

Connects one master to multiple slaves.

@@ -714,7 +714,7 @@

Submodules
class coreblocks.peripherals.wishbone.WishboneSignature
-

Bases: Signature

+

Bases: Signature

__init__(wb_params: WishboneParameters)
@@ -746,7 +746,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html index 3b32ec7d3..726c4496f 100644 --- a/coreblocks.priv.csr.html +++ b/coreblocks.priv.csr.html @@ -255,7 +255,7 @@

Submodules
-__init__(csr_number: Optional[int], gen_params: GenParams, *, width: Optional[int] = None, ro_bits: int = 0, init: int | amaranth.lib.enum.Enum = 0, fu_write_priority: bool = True, fu_write_filtermap: Optional[Callable[[TModule, Value], tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]] = None, fu_read_map: Optional[Callable[[TModule, Value], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]] = None, src_loc: int | tuple[str, int] = 0)
+__init__(csr_number: Optional[int], gen_params: GenParams, *, width: Optional[int] = None, ro_bits: int = 0, init: int | amaranth.lib.enum.Enum = 0, fu_write_priority: bool = True, fu_write_filtermap: Optional[Callable[[TModule, Value], tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]] = None, fu_read_map: Optional[Callable[[TModule, Value], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]] = None, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -311,7 +311,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.priv.html b/coreblocks.priv.html index 231fa4de1..3aa772aee 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -124,7 +124,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index ee9d1172b..acd0f9b6e 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -109,7 +109,7 @@

Submodules
-coreblocks.priv.traps.exception.should_update_prioriy(m: TModule, current_cause: Value, new_cause: Value) → Value
+coreblocks.priv.traps.exception.should_update_prioriy(m: TModule, current_cause: Value, new_cause: Value) → Value

@@ -145,7 +145,7 @@

Submodules
class coreblocks.priv.traps.interrupt_controller.InternalInterruptController
-

Bases: Component

+

Bases: Component

Core Internal Interrupt Controller Compatible with RISC-V privileged specification. Operates on CSR registers xIE, xIP, and parts of xSTATUS. @@ -205,7 +205,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 2e19a2d51..7f22a7878 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/current-graph.html b/current-graph.html index cbaa2115a..4b609c98d 100644 --- a/current-graph.html +++ b/current-graph.html @@ -91,26 +91,26 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/development-environment.html b/development-environment.html index 7a9b9d06e..6cdd9b72a 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/genindex.html b/genindex.html index 55093656b..9b54ea98e 100644 --- a/genindex.html +++ b/genindex.html @@ -4803,7 +4803,7 @@

Z

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/home.html b/home.html index 52eb74b40..cd66abcb5 100644 --- a/home.html +++ b/home.html @@ -129,7 +129,7 @@

Documentation

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/index.html b/index.html index 783cdf72a..f2dafc2fd 100644 --- a/index.html +++ b/index.html @@ -229,7 +229,7 @@

Coreblocks

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html index 168ba0577..e8dab6a9e 100644 --- a/miscellany/exceptions-summary.html +++ b/miscellany/exceptions-summary.html @@ -271,7 +271,7 @@

Summary

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/modules-coreblocks.html b/modules-coreblocks.html index 5edb24830..84dc942f3 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -179,7 +179,7 @@

coreblocks

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/modules-transactron.html b/modules-transactron.html index 49ca8710a..a3e900f5d 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -162,7 +162,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/problem-checklist.html b/problem-checklist.html index fdf87ec4d..1c43fb622 100644 --- a/problem-checklist.html +++ b/problem-checklist.html @@ -105,7 +105,7 @@

Problem checklist

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/py-modindex.html b/py-modindex.html index 1476a848d..6b3d97007 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -708,7 +708,7 @@

Python Module Index

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/scheduler/overview.html b/scheduler/overview.html index cf06d5f8a..4d8640f87 100644 --- a/scheduler/overview.html +++ b/scheduler/overview.html @@ -146,7 +146,7 @@

More detailed description of each block

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/search.html b/search.html index ff77b6640..a70baea60 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/searchindex.js b/searchindex.js index 5b295d06b..a3ea01237 100644 --- a/searchindex.js +++ b/searchindex.js @@ -1 +1 @@ -Search.setIndex({"docnames": ["api", "assumptions", "auto_graph", "components/icache", "coreblocks", "coreblocks.arch", "coreblocks.backend", "coreblocks.cache", "coreblocks.core_structs", "coreblocks.frontend", "coreblocks.frontend.decoder", "coreblocks.frontend.fetch", "coreblocks.func_blocks", "coreblocks.func_blocks.fu", "coreblocks.func_blocks.fu.lsu", "coreblocks.func_blocks.fu.unsigned_multiplication", "coreblocks.func_blocks.interface", "coreblocks.params", "coreblocks.peripherals", "coreblocks.priv", "coreblocks.priv.csr", "coreblocks.priv.traps", "coreblocks.scheduler", "current-graph", "development-environment", "home", "index", "miscellany/exceptions-summary", "modules-coreblocks", "modules-transactron", "problem-checklist", "scheduler/overview", "shared-structs/implementation/rs-impl", "shared-structs/rs", "synthesis/synthesis", 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20, 26, 27, 38], "form": [5, 10, 20, 27, 34, 37, 38], "bitwis": 5, "isa_str": 5, "str": [5, 7, 11, 18, 20, 36, 37, 38, 39, 40, 41], "paramet": [5, 6, 7, 10, 11, 13, 14, 15, 17, 18, 20, 21, 22, 35, 37, 38, 39, 40, 41], "string": [5, 38, 39], "identifi": [5, 10, 11, 32, 38], "pleas": [5, 24, 30, 35], "refer": [5, 36, 40], "gcc": 5, "": [5, 9, 11, 18, 27, 35, 36, 37, 38, 40, 41], "option": [5, 10, 13, 17, 18, 20, 24, 35, 36, 37, 38, 39, 40, 41], "detail": [5, 21, 26, 38], "exceptioncaus": 5, "breakpoint": 5, "environment_call_from_m": 5, "environment_call_from_": 5, "environment_call_from_u": 5, "illegal_instruct": 5, "instruction_access_fault": 5, "instruction_address_misalign": 5, "instruction_page_fault": 5, "load_access_fault": 5, "load_address_misalign": 5, "load_page_fault": 5, "store_access_fault": 5, "store_address_misalign": 5, "store_page_fault": 5, "fencefm": [5, 10], "none": [5, 7, 8, 10, 11, 13, 14, 17, 20, 36, 37, 38, 39, 40, 41], "tso": 5, "fencetarget": [5, 10], "dev_i": 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37], "two": [5, 7, 20, 27, 30, 34, 35, 37, 38, 39, 40], "third": [5, 37, 38], "about": [5, 11, 17, 24, 26, 36, 38, 40], "becaus": [5, 27, 35, 36, 37, 38], "tweak": 5, "helper": 5, "prefer": [5, 18, 35], "us": [5, 6, 7, 10, 11, 13, 14, 15, 17, 18, 20, 21, 22, 26, 27, 30, 34, 35, 37, 38, 39, 40, 41], "cfi": [5, 11], "static": [5, 17, 36, 37, 40, 41], "is_branch": 5, "amaranth": [5, 7, 9, 10, 11, 13, 17, 18, 20, 30, 34, 35, 36, 37, 38, 39, 40, 41], "hdl": [5, 7, 9, 10, 13, 17, 20, 36, 37, 38, 39, 40, 41], "_ast": [5, 7, 9, 10, 13, 17, 20, 37, 38, 39, 40, 41], "valuecast": [5, 9, 10, 17, 20, 37, 38, 39, 40, 41], "is_jal": 5, "is_jalr": 5, "valid": [5, 13, 18, 22, 32, 38, 40, 41], "do": [5, 10, 27, 30, 35, 37, 38, 41], "confus": 5, "address_gener": 5, "arithmet": 5, "bit_manipul": 5, "bit_rot": 5, "compar": [5, 26, 38], "csr_imm": 5, "csr_reg": 5, "div_rem": 5, "caus": [5, 17, 21, 27, 38, 40], "befor": [5, 14, 18, 21, 24, 30, 31, 35, 37, 38], "execut": [5, 6, 13, 18, 22, 24, 26, 31, 33, 35, 36, 37, 38], "logic": [5, 14, 27, 33, 34, 35], "33": 5, "single_bit_manipul": 5, "unary_bit_manipulation_1": 5, "unary_bit_manipulation_2": 5, "unary_bit_manipulation_3": 5, "unary_bit_manipulation_4": 5, "unary_bit_manipulation_5": 5, "unknown": [5, 24, 36, 38, 40], "resultannounc": 6, "elaborat": [6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 18, 20, 21, 22, 35, 36, 37, 38, 39, 40], "simpl": [6, 7, 10, 14, 20, 22, 37, 38, 40, 41], "It": [6, 10, 11, 13, 14, 15, 17, 18, 20, 22, 24, 27, 31, 32, 34, 35, 36, 37, 38, 39, 40, 41], "take": [6, 10, 18, 31, 32, 35, 37, 38, 39, 40], "its": [6, 10, 17, 20, 22, 27, 34, 35, 37, 38, 40, 41], "mark": [6, 26, 27, 36], "complet": [6, 18, 20, 27], "also": [6, 11, 17, 24, 34, 35, 38, 39], "sent": [6, 18, 39], "get_result": [6, 16, 38], "serial": [6, 11, 14, 38], "so": [6, 17, 18, 27, 34, 35, 36, 37, 38, 41], "we": [6, 7, 18, 27, 31, 32, 33, 34, 35, 38, 39], "more": [6, 20, 24, 26, 27, 38, 40, 41], "than": [6, 27, 38, 40, 41], "connect": [6, 10, 18, 20, 27, 35, 37, 38, 41], "manytooneconnecttran": [6, 38], "rob_mark_don": 6, "rs_updat": 6, "rf_write": 6, "instanc": [6, 7, 10, 11, 14, 17, 22, 34, 36, 37, 38, 40, 41], "next": [6, 7, 10, 11, 22, 27, 37, 41], "readi": [6, 7, 18, 20, 22, 26, 32, 36, 37, 38, 41], "assum": [6, 13, 27, 38, 40], "differ": [6, 13, 18, 24, 25, 27, 30, 34, 37, 38, 40, 41], "end": [6, 14, 27, 37, 38, 41], "without": [6, 22, 27, 37, 38, 40], "pass": [6, 24, 26, 34, 37, 38, 39, 40], "finish": [6, 18, 21, 38], "rob_peek": 6, "rob_retir": 6, "r_rat_commit": 6, "r_rat_peek": 6, "free_rf_put": 6, "rf_free": 6, "exception_cause_get": 6, "exception_cause_clear": 6, "frat_renam": 6, "fetch_continu": 6, "instr_decr": 6, "trap_entri": 6, "async_interrupt_caus": 6, "cacheinterfac": [7, 11], "associ": [7, 17, 38], "replac": [7, 15, 17, 20, 32], "polici": 7, "pseudo": 7, "random": [7, 39], "scheme": 7, "everi": [7, 13, 18, 24, 34, 37, 38], "trash": 7, "select": [7, 10, 13, 16, 18, 22, 24, 38, 41], "keep": [7, 37], "global": [7, 27], "abstract": [7, 15, 17, 34, 38, 40], "awai": 7, "need": [7, 11, 17, 18, 24, 27, 32, 35, 37, 38], "refiller_start": 7, "whenev": [7, 17, 38], "refiller_accept": 7, "written": [7, 20, 33, 34, 38], "last": [7, 21, 22, 37, 38, 41], "when": [7, 14, 17, 18, 21, 24, 27, 30, 32, 33, 35, 37, 38, 40, 41], "either": [7, 17, 18, 21, 35, 37, 38, 39, 40, 41], "transfer": [7, 18, 37, 38], "over": [7, 20, 37, 38], "shouldn": [7, 34], "until": [7, 11, 27, 38], "start": [7, 13, 14, 18, 21, 27, 37, 38, 41], "layout": [7, 10, 11, 18, 22, 24, 30, 35, 37, 38, 39, 40], "icachelayout": 7, "icacheparamet": [7, 17], "cacherefillerinterfac": 7, "creat": [7, 15, 17, 18, 24, 34, 35, 37, 38, 39, 40, 41], "input": [7, 10, 13, 18, 20, 21, 27, 32, 33, 35, 37, 38, 41], "start_refil": 7, "accept_refil": 7, "deserialize_addr": 7, "raw_addr": 7, "dict": [7, 18, 35, 36, 37, 38, 39, 40, 41], "serialize_addr": 7, "addr": [7, 14, 18, 38], "view": [7, 13, 14, 37, 38, 39, 40, 41], "icachebypass": 7, "bus_mast": 7, "busmasterinterfac": [7, 9, 14, 18], "haselabor": [7, 16, 18, 36, 37, 38, 39, 41], "protocol": [7, 16, 18, 36, 37, 38], "whole": [7, 25, 27, 38], "given": [7, 9, 14, 17, 20, 24, 32, 35, 36, 37, 38, 39, 40, 41], "simplecommonbuscacherefil": 7, "frat": 8, "rrat": 8, "registerfil": 8, "reorderbuff": [8, 21], "corefrontend": 9, "consume_instr": 9, "consum": [9, 11], "resume_from_except": 9, "resum": 9, "pc": [9, 26], "resume_from_unsaf": 9, "unsaf": 9, "stall": [9, 18, 27], "instr_bu": 9, "frontendparam": 9, "fb_addr": 9, "fb_instr_idx": 9, "pc_from_fb": 9, "decodestag": 10, "instanti": [10, 37], "instrdecod": 10, "make": [10, 13, 24, 25, 27, 30, 34, 35, 36, 39], "actual": [10, 24, 26, 35], "combinatori": [10, 35], "manner": [10, 18], "get_raw": 10, "push_decod": 10, "raw": 10, "previou": [10, 11, 18, 27, 38], "step": [10, 11, 22, 24, 27, 34, 35], "fetchlayout": [10, 11], "describ": [10, 11, 14, 22, 27, 34, 36, 37, 38, 39], "decodelayout": [10, 22], "elementari": 10, "etc": [10, 35], "via": [10, 21, 35, 37], "signal": [10, 13, 14, 18, 20, 21, 26, 30, 36, 37, 38, 39, 40, 41], "out": [10, 13, 15, 18, 21, 25, 26, 36, 37, 38, 41], "funct3_v": 10, "seven": 10, "funct7_v": 10, "twelv": 10, "funct12_v": 10, "rd": [10, 17], "reg_cnt_log": 10, "rd_v": 10, "rs1": [10, 17], "hold": [10, 17, 18, 38], "first": [10, 13, 14, 20, 22, 27, 32, 33, 34, 35, 37, 38, 39, 40, 41], "rs1_v": 10, "rs2": [10, 17], "second": [10, 13, 20, 22, 32, 33, 34, 38, 41], "rs2_v": 10, "imm": [10, 17], "immedi": [10, 17, 18], "were": [10, 27, 35], "succ": 10, "successor": 10, "pred": 10, "predecessor": 10, "fm": 10, "sourc": [10, 20, 22, 24, 32, 36, 37, 38], "defin": [10, 14, 20, 35, 37, 38, 40, 41], "kind": [10, 13, 22, 38, 40], "illeg": [10, 17], "success": [10, 18, 39], "fit": 10, "constructor": [10, 35, 37, 40], "repres": [10, 20, 37, 38], "exist": [10, 35], "instr_type_overrid": 10, "specifi": [10, 18, 20, 33, 38, 40], "determin": [10, 11, 27, 34, 38, 40], "instrust": 10, "almost": 10, "correct": [10, 11, 14, 27, 32, 33, 34], "rd_zero": 10, "bool": [10, 14, 17, 20, 36, 37, 38, 39, 40, 41], "constant": 10, "other": [10, 17, 20, 24, 26, 35, 36, 37, 38, 41], "accordingli": 10, "default": [10, 18, 20, 24, 35, 36, 37, 38, 40, 41], "fals": [10, 13, 14, 24, 35, 36, 37, 38, 40, 41], "rs1_zero": 10, "instrdecompress": 10, "decompr_reg": 10, "rvc_reg": 10, "instr_mux": 10, "sel": [10, 18], "list": [10, 13, 17, 18, 24, 26, 30, 34, 36, 37, 38, 39, 40, 41], "tupl": [10, 11, 13, 18, 20, 22, 36, 37, 38, 39, 40, 41], "is_instr_compress": 10, "fetchunit": 11, "superscalar": 11, "respons": [11, 13, 14, 18, 22, 24, 37, 38, 39], "retriev": [11, 14, 38], "them": [11, 24, 27, 34, 35, 37, 38, 40], "work": [11, 22, 27, 30, 34, 35, 37, 38], "chunk": 11, "fetch_block_byt": 11, "relat": [11, 27, 37, 38, 40], "how": [11, 17, 20, 24, 27, 32, 34, 37, 38], "mani": [11, 17, 20, 24, 27, 34, 35, 36, 37, 38, 40], "onc": [11, 34, 35, 37, 38, 41], "vari": 11, "deal": 11, "expand": 11, "aren": [11, 27, 35, 38], "boundari": [11, 27], "cont": [11, 39], "predecod": 11, "analysi": [11, 26, 36], "jump": [11, 17, 27], "find": [11, 24, 27, 38], "target": [11, 34, 38], "Its": [11, 14, 31, 35], "role": [11, 35], "give": [11, 38, 40], "quick": 11, "feedback": 11, "potenti": [11, 31], "predictor": 11, "help": [11, 24, 27, 38], "redirect": 11, "promptli": 11, "predictioncheck": 11, "predict": 11, "checker": [11, 14], "look": [11, 27, 38], "taken": [11, 20, 22, 34, 37, 38], "mistak": [11, 30], "ones": [11, 35], "wrong": [11, 27], "element": [11, 27, 38], "dispatch": [11, 27, 31, 32, 33], "new": [11, 13, 14, 18, 21, 26, 27, 37, 38, 40, 41], "batch": 11, "onli": [11, 13, 17, 18, 20, 21, 27, 34, 35, 36, 37, 38, 39, 40], "temporari": [11, 20], "workaround": 11, "buffer": [11, 18, 27, 32, 38, 41], "rest": [11, 37], "becom": [11, 18], "elem_layout": 11, "structlayout": [11, 14, 37, 38, 39, 40], "collect": [11, 25, 34, 36, 37, 38, 39, 40, 41], "abc": [11, 17, 37, 38, 39, 40, 41], "iter": [11, 16, 17, 37, 38, 39, 40, 41], "shapelik": [11, 37, 38, 39, 40], "layoutlist": [11, 37, 38, 39, 40], "lsu": [12, 13], "dummylsu": [12, 13], "lsu_request": [12, 13], "pma": [12, 13], "unsigned_multipl": [12, 13], "common": [12, 13, 18, 37, 38, 40], "fast_recurs": [12, 13], "sequenc": [12, 13, 22, 37, 38, 40], "alucompon": 13, "functionalcomponentparam": [13, 14, 17], "zba_en": 13, "zbb_enabl": 13, "get_modul": [13, 14, 17], "funcunit": [13, 14, 16, 17], "get_optyp": [13, 14, 17], "alufuncunit": 13, "alu_fn": 13, "alufn": 13, "divcompon": 13, "ipc": [13, 34], "div_fn": 13, "divfn": 13, "decodermanag": 13, "fn": 13, "get_instruct": 13, "implement": [13, 14, 18, 20, 25, 26, 27, 31, 38, 40, 41], "format": [13, 24, 34, 35, 36, 37, 38, 40, 41], "divunit": 13, "get_input": 13, "arg": [13, 18, 35, 36, 37, 38, 39, 40, 41], "exceptionfuncunit": 13, "unit_fn": 13, "exceptionunitfn": 13, "exceptionunitcompon": 13, "jumpbranchfuncunit": 13, "jb_fn": 13, "jumpbranchfn": 13, "jumpcompon": 13, "mulcompon": 13, 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2, 1, "", "MHPMCOUNTER13H"], [5, 2, 1, "", "MHPMCOUNTER14"], [5, 2, 1, "", "MHPMCOUNTER14H"], [5, 2, 1, "", "MHPMCOUNTER15"], [5, 2, 1, "", "MHPMCOUNTER15H"], [5, 2, 1, "", "MHPMCOUNTER16"], [5, 2, 1, "", "MHPMCOUNTER16H"], [5, 2, 1, "", "MHPMCOUNTER17"], [5, 2, 1, "", "MHPMCOUNTER17H"], [5, 2, 1, "", "MHPMCOUNTER18"], [5, 2, 1, "", "MHPMCOUNTER18H"], [5, 2, 1, "", "MHPMCOUNTER19"], [5, 2, 1, "", "MHPMCOUNTER19H"], [5, 2, 1, "", "MHPMCOUNTER20"], [5, 2, 1, "", "MHPMCOUNTER20H"], [5, 2, 1, "", "MHPMCOUNTER21"], [5, 2, 1, "", "MHPMCOUNTER21H"], [5, 2, 1, "", "MHPMCOUNTER22"], [5, 2, 1, "", "MHPMCOUNTER22H"], [5, 2, 1, "", "MHPMCOUNTER23"], [5, 2, 1, "", "MHPMCOUNTER23H"], [5, 2, 1, "", "MHPMCOUNTER24"], [5, 2, 1, "", "MHPMCOUNTER24H"], [5, 2, 1, "", "MHPMCOUNTER25"], [5, 2, 1, "", "MHPMCOUNTER25H"], [5, 2, 1, "", "MHPMCOUNTER26"], [5, 2, 1, "", "MHPMCOUNTER26H"], [5, 2, 1, "", "MHPMCOUNTER27"], [5, 2, 1, "", "MHPMCOUNTER27H"], [5, 2, 1, "", "MHPMCOUNTER28"], [5, 2, 1, "", "MHPMCOUNTER28H"], [5, 2, 1, "", "MHPMCOUNTER29"], [5, 2, 1, "", "MHPMCOUNTER29H"], [5, 2, 1, "", "MHPMCOUNTER3"], [5, 2, 1, "", "MHPMCOUNTER30"], [5, 2, 1, "", "MHPMCOUNTER30H"], [5, 2, 1, "", "MHPMCOUNTER31"], [5, 2, 1, "", "MHPMCOUNTER31H"], [5, 2, 1, "", "MHPMCOUNTER3H"], [5, 2, 1, "", "MHPMCOUNTER4"], [5, 2, 1, "", "MHPMCOUNTER4H"], [5, 2, 1, "", "MHPMCOUNTER5"], [5, 2, 1, "", "MHPMCOUNTER5H"], [5, 2, 1, "", "MHPMCOUNTER6"], [5, 2, 1, "", "MHPMCOUNTER6H"], [5, 2, 1, "", "MHPMCOUNTER7"], [5, 2, 1, "", "MHPMCOUNTER7H"], [5, 2, 1, "", "MHPMCOUNTER8"], [5, 2, 1, "", "MHPMCOUNTER8H"], [5, 2, 1, "", "MHPMCOUNTER9"], [5, 2, 1, "", "MHPMCOUNTER9H"], [5, 2, 1, "", "MHPMEVENT10"], [5, 2, 1, "", "MHPMEVENT10H"], [5, 2, 1, "", "MHPMEVENT11"], [5, 2, 1, "", "MHPMEVENT11H"], [5, 2, 1, "", "MHPMEVENT12"], [5, 2, 1, "", "MHPMEVENT12H"], [5, 2, 1, "", "MHPMEVENT13"], [5, 2, 1, "", "MHPMEVENT13H"], [5, 2, 1, "", "MHPMEVENT14"], [5, 2, 1, "", "MHPMEVENT14H"], [5, 2, 1, "", "MHPMEVENT15"], [5, 2, 1, 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2, 1, "", "MHPMEVENT31H"], [5, 2, 1, "", "MHPMEVENT3H"], [5, 2, 1, "", "MHPMEVENT4"], [5, 2, 1, "", "MHPMEVENT4H"], [5, 2, 1, "", "MHPMEVENT5"], [5, 2, 1, "", "MHPMEVENT5H"], [5, 2, 1, "", "MHPMEVENT6"], [5, 2, 1, "", "MHPMEVENT6H"], [5, 2, 1, "", "MHPMEVENT7"], [5, 2, 1, "", "MHPMEVENT7H"], [5, 2, 1, "", "MHPMEVENT8"], [5, 2, 1, "", "MHPMEVENT8H"], [5, 2, 1, "", "MHPMEVENT9"], [5, 2, 1, "", "MHPMEVENT9H"], [5, 2, 1, "", "MIDELEG"], [5, 2, 1, "", "MIE"], [5, 2, 1, "", "MIMPID"], [5, 2, 1, "", "MINSTRET"], [5, 2, 1, "", "MINSTRETH"], [5, 2, 1, "", "MIP"], [5, 2, 1, "", "MISA"], [5, 2, 1, "", "MNCAUSE"], [5, 2, 1, "", "MNEPC"], [5, 2, 1, "", "MNSCRATCH"], [5, 2, 1, "", "MNSTATUS"], [5, 2, 1, "", "MSCRATCH"], [5, 2, 1, "", "MSECCFG"], [5, 2, 1, "", "MSECCFGH"], [5, 2, 1, "", "MSTATEEN0"], [5, 2, 1, "", "MSTATEEN0H"], [5, 2, 1, "", "MSTATEEN1"], [5, 2, 1, "", "MSTATEEN1H"], [5, 2, 1, "", "MSTATEEN2"], [5, 2, 1, "", "MSTATEEN2H"], [5, 2, 1, "", "MSTATEEN3"], [5, 2, 1, "", "MSTATEEN3H"], [5, 2, 1, "", "MSTATUS"], [5, 2, 1, "", "MSTATUSH"], [5, 2, 1, "", "MTINST"], [5, 2, 1, "", "MTVAL"], [5, 2, 1, "", "MTVAL2"], [5, 2, 1, "", "MTVEC"], [5, 2, 1, "", "MVENDORID"], [5, 2, 1, "", "PMPADDR0"], [5, 2, 1, "", "PMPADDR1"], [5, 2, 1, "", "PMPADDR10"], [5, 2, 1, "", "PMPADDR11"], [5, 2, 1, "", "PMPADDR12"], [5, 2, 1, "", "PMPADDR13"], [5, 2, 1, "", "PMPADDR14"], [5, 2, 1, "", "PMPADDR15"], [5, 2, 1, "", "PMPADDR16"], [5, 2, 1, "", "PMPADDR17"], [5, 2, 1, "", "PMPADDR18"], [5, 2, 1, "", "PMPADDR19"], [5, 2, 1, "", "PMPADDR2"], [5, 2, 1, "", "PMPADDR20"], [5, 2, 1, "", "PMPADDR21"], [5, 2, 1, "", "PMPADDR22"], [5, 2, 1, "", "PMPADDR23"], [5, 2, 1, "", "PMPADDR24"], [5, 2, 1, "", "PMPADDR25"], [5, 2, 1, "", "PMPADDR26"], [5, 2, 1, "", "PMPADDR27"], [5, 2, 1, "", "PMPADDR28"], [5, 2, 1, "", "PMPADDR29"], [5, 2, 1, "", "PMPADDR3"], [5, 2, 1, "", "PMPADDR30"], [5, 2, 1, "", "PMPADDR31"], [5, 2, 1, "", "PMPADDR32"], [5, 2, 1, "", "PMPADDR33"], [5, 2, 1, "", "PMPADDR34"], [5, 2, 1, "", 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2, 1, "", "TSELECT"], [5, 2, 1, "", "VSATP"], [5, 2, 1, "", "VSCAUSE"], [5, 2, 1, "", "VSEPC"], [5, 2, 1, "", "VSIE"], [5, 2, 1, "", "VSIP"], [5, 2, 1, "", "VSSCRATCH"], [5, 2, 1, "", "VSSTATUS"], [5, 2, 1, "", "VSTVAL"], [5, 2, 1, "", "VSTVEC"], [5, 3, 1, "", "__new__"]], "coreblocks.arch.csr_address.MstatusFieldOffsets": [[5, 2, 1, "", "FS"], [5, 2, 1, "", "MBE"], [5, 2, 1, "", "MIE"], [5, 2, 1, "", "MPIE"], [5, 2, 1, "", "MPP"], [5, 2, 1, "", "MPRV"], [5, 2, 1, "", "MXR"], [5, 2, 1, "", "SBE"], [5, 2, 1, "", "SD"], [5, 2, 1, "", "SIE"], [5, 2, 1, "", "SPIE"], [5, 2, 1, "", "SPP"], [5, 2, 1, "", "SUM"], [5, 2, 1, "", "SXL"], [5, 2, 1, "", "TSR"], [5, 2, 1, "", "TVM"], [5, 2, 1, "", "TW"], [5, 2, 1, "", "UBE"], [5, 2, 1, "", "UXL"], [5, 2, 1, "", "VS"], [5, 2, 1, "", "XS"], [5, 3, 1, "", "__new__"]], "coreblocks.arch.isa": [[5, 1, 1, "", "Extension"], [5, 1, 1, "", "ISA"]], "coreblocks.arch.isa.Extension": [[5, 2, 1, "", "A"], [5, 2, 1, "", "B"], [5, 2, 1, "", "C"], [5, 2, 1, "", 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[5, 1, 1, "", "Funct7"], [5, 1, 1, "", "InstrType"], [5, 1, 1, "", "InterruptCauseNumber"], [5, 1, 1, "", "Opcode"], [5, 1, 1, "", "PrivilegeLevel"], [5, 1, 1, "", "Registers"], [5, 1, 1, "", "XlenEncoding"]], "coreblocks.arch.isa_consts.ExceptionCause": [[5, 2, 1, "", "BREAKPOINT"], [5, 2, 1, "", "ENVIRONMENT_CALL_FROM_M"], [5, 2, 1, "", "ENVIRONMENT_CALL_FROM_S"], [5, 2, 1, "", "ENVIRONMENT_CALL_FROM_U"], [5, 2, 1, "", "ILLEGAL_INSTRUCTION"], [5, 2, 1, "", "INSTRUCTION_ACCESS_FAULT"], [5, 2, 1, "", "INSTRUCTION_ADDRESS_MISALIGNED"], [5, 2, 1, "", "INSTRUCTION_PAGE_FAULT"], [5, 2, 1, "", "LOAD_ACCESS_FAULT"], [5, 2, 1, "", "LOAD_ADDRESS_MISALIGNED"], [5, 2, 1, "", "LOAD_PAGE_FAULT"], [5, 2, 1, "", "STORE_ACCESS_FAULT"], [5, 2, 1, "", "STORE_ADDRESS_MISALIGNED"], [5, 2, 1, "", "STORE_PAGE_FAULT"], [5, 3, 1, "", "__new__"]], "coreblocks.arch.isa_consts.FenceFm": [[5, 2, 1, "", "NONE"], [5, 2, 1, "", "TSO"], [5, 3, 1, "", "__new__"]], "coreblocks.arch.isa_consts.FenceTarget": [[5, 2, 1, "", "DEV_I"], [5, 2, 1, "", "DEV_O"], [5, 2, 1, "", "MEM_R"], [5, 2, 1, "", "MEM_W"], [5, 3, 1, "", "__new__"]], "coreblocks.arch.isa_consts.Funct12": [[5, 2, 1, "", "CLZ"], [5, 2, 1, "", "CPOP"], [5, 2, 1, "", "CTZ"], [5, 2, 1, "", "EBREAK"], [5, 2, 1, "", "ECALL"], [5, 2, 1, "", "MRET"], [5, 2, 1, "", "ORCB"], [5, 2, 1, "", "REV8_32"], [5, 2, 1, "", "REV8_64"], [5, 2, 1, "", "SEXTB"], [5, 2, 1, "", "SEXTH"], [5, 2, 1, "", "SRET"], [5, 2, 1, "", "WFI"], [5, 2, 1, "", "ZEXTH"], [5, 3, 1, "", "__new__"]], "coreblocks.arch.isa_consts.Funct3": [[5, 2, 1, "", "ADD"], [5, 2, 1, "", "AND"], [5, 2, 1, "", "ANDN"], [5, 2, 1, "", "B"], [5, 2, 1, "", "BCLR"], [5, 2, 1, "", "BEQ"], [5, 2, 1, "", "BEXT"], [5, 2, 1, "", "BGE"], [5, 2, 1, "", "BGEU"], [5, 2, 1, "", "BINV"], [5, 2, 1, "", "BLT"], [5, 2, 1, "", "BLTU"], [5, 2, 1, "", "BNE"], [5, 2, 1, "", "BSET"], [5, 2, 1, "", "BU"], [5, 2, 1, "", "CLMUL"], [5, 2, 1, "", "CLMULH"], [5, 2, 1, "", "CLMULR"], [5, 2, 1, "", "CLZ"], [5, 2, 1, "", "CPOP"], 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17, 24, 37, 38, 39, 40], "flow": [5, 11, 38], "There": [5, 38], "main": [5, 24, 27, 31, 34], "invalid": [5, 33, 38], "call": [5, 7, 17, 20, 21, 22, 24, 30, 32, 35, 36, 37, 38, 39, 40, 41], "ret": 5, "just": [5, 24, 35, 38], "special": [5, 26, 38], "respect": [5, 20, 38], "thu": [5, 38], "encod": [5, 10, 17, 27, 36, 38, 40, 41], "wa": [5, 10, 11, 20, 21, 24, 27, 35, 36, 37, 38, 40], "chosen": [5, 27], "wai": [5, 7, 13, 18, 24, 27, 34, 35, 37, 38, 40, 41], "suffici": 5, "check": [5, 11, 14, 24, 27, 30, 32, 33, 34, 37, 40], "lowest": [5, 37], "two": [5, 7, 20, 27, 30, 34, 35, 37, 38, 39, 40], "third": [5, 37, 38], "about": [5, 11, 17, 24, 26, 36, 38, 40], "becaus": [5, 27, 35, 36, 37, 38], "tweak": 5, "helper": 5, "prefer": [5, 18, 35], "us": [5, 6, 7, 10, 11, 13, 14, 15, 17, 18, 20, 21, 22, 26, 27, 30, 34, 35, 37, 38, 39, 40, 41], "cfi": [5, 11], "static": [5, 17, 36, 37, 40, 41], "is_branch": 5, "amaranth": [5, 7, 9, 10, 11, 13, 17, 18, 20, 30, 34, 35, 36, 37, 38, 39, 40, 41], "hdl": [5, 7, 9, 10, 13, 17, 20, 36, 37, 38, 39, 40, 41], "_ast": [5, 7, 9, 10, 13, 17, 20, 37, 38, 39, 40, 41], "valuecast": [5, 9, 10, 17, 20, 37, 38, 39, 40, 41], "is_jal": 5, "is_jalr": 5, "valid": [5, 13, 18, 22, 32, 38, 40, 41], "do": [5, 10, 27, 30, 35, 37, 38, 41], "confus": 5, "address_gener": 5, "arithmet": 5, "bit_manipul": 5, "bit_rot": 5, "compar": [5, 26, 38], "csr_imm": 5, "csr_reg": 5, "div_rem": 5, "caus": [5, 17, 21, 27, 38, 40], "befor": [5, 14, 18, 21, 24, 30, 31, 35, 37, 38], "execut": [5, 6, 13, 18, 22, 24, 26, 31, 33, 35, 36, 37, 38], "logic": [5, 14, 27, 33, 34, 35], "33": 5, "single_bit_manipul": 5, "unary_bit_manipulation_1": 5, "unary_bit_manipulation_2": 5, "unary_bit_manipulation_3": 5, "unary_bit_manipulation_4": 5, "unary_bit_manipulation_5": 5, "unknown": [5, 24, 36, 38, 40], "resultannounc": 6, "elaborat": [6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 18, 20, 21, 22, 35, 36, 37, 38, 39, 40], "simpl": [6, 7, 10, 14, 20, 22, 37, 38, 40, 41], "It": [6, 10, 11, 13, 14, 15, 17, 18, 20, 22, 24, 27, 31, 32, 34, 35, 36, 37, 38, 39, 40, 41], "take": [6, 10, 18, 31, 32, 35, 37, 38, 39, 40], "its": [6, 10, 17, 20, 22, 27, 34, 35, 37, 38, 40, 41], "mark": [6, 26, 27, 36], "complet": [6, 18, 20, 27], "also": [6, 11, 17, 24, 34, 35, 38, 39], "sent": [6, 18, 39], "get_result": [6, 16, 38], "serial": [6, 11, 14, 38], "so": [6, 17, 18, 27, 34, 35, 36, 37, 38, 41], "we": [6, 7, 18, 27, 31, 32, 33, 34, 35, 38, 39], "more": [6, 20, 24, 26, 27, 38, 40, 41], "than": [6, 27, 38, 40, 41], "connect": [6, 10, 18, 20, 27, 35, 37, 38, 41], "manytooneconnecttran": [6, 38], "rob_mark_don": 6, "rs_updat": 6, "rf_write": 6, "instanc": [6, 7, 10, 11, 14, 17, 22, 34, 36, 37, 38, 40, 41], "next": [6, 7, 10, 11, 22, 27, 37, 41], "readi": [6, 7, 18, 20, 22, 26, 32, 36, 37, 38, 41], "assum": [6, 13, 27, 38, 40], "differ": [6, 13, 18, 24, 25, 27, 30, 34, 37, 38, 40, 41], "end": [6, 14, 27, 37, 38, 41], "without": [6, 22, 27, 37, 38, 40], "pass": [6, 24, 26, 34, 37, 38, 39, 40], "finish": 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13, 14, 18, 21, 27, 37, 38, 41], "layout": [7, 10, 11, 18, 22, 24, 30, 35, 37, 38, 39, 40], "icachelayout": 7, "icacheparamet": [7, 17], "cacherefillerinterfac": 7, "creat": [7, 15, 17, 18, 24, 34, 35, 37, 38, 39, 40, 41], "input": [7, 10, 13, 18, 20, 21, 27, 32, 33, 35, 37, 38, 41], "start_refil": 7, "accept_refil": 7, "deserialize_addr": 7, "raw_addr": 7, "dict": [7, 18, 35, 36, 37, 38, 39, 40, 41], "serialize_addr": 7, "addr": [7, 14, 18, 38], "view": [7, 13, 14, 37, 38, 39, 40, 41], "icachebypass": 7, "bus_mast": 7, "busmasterinterfac": [7, 9, 14, 18], "haselabor": [7, 16, 18, 36, 37, 38, 39, 41], "protocol": [7, 16, 18, 36, 37, 38], "whole": [7, 25, 27, 38], "given": [7, 9, 14, 17, 20, 24, 32, 35, 36, 37, 38, 39, 40, 41], "simplecommonbuscacherefil": 7, "frat": 8, "rrat": 8, "registerfil": 8, "reorderbuff": [8, 21], "corefrontend": 9, "consume_instr": 9, "consum": [9, 11], "resume_from_except": 9, "resum": 9, "pc": [9, 26], "resume_from_unsaf": 9, "unsaf": 9, "stall": [9, 18, 27], "instr_bu": 9, "frontendparam": 9, "fb_addr": 9, "fb_instr_idx": 9, "pc_from_fb": 9, "decodestag": 10, "instanti": [10, 37], "instrdecod": 10, "make": [10, 13, 24, 25, 27, 30, 34, 35, 36, 39], "actual": [10, 24, 26, 35], "combinatori": [10, 35], "manner": [10, 18], "get_raw": 10, "push_decod": 10, "raw": 10, "previou": [10, 11, 18, 27, 38], "step": [10, 11, 22, 24, 27, 34, 35], "fetchlayout": [10, 11], "describ": [10, 11, 14, 22, 27, 34, 36, 37, 38, 39], "decodelayout": [10, 22], "elementari": 10, "etc": [10, 35], "via": [10, 21, 35, 37, 38], "signal": [10, 13, 14, 18, 20, 21, 26, 30, 36, 37, 38, 39, 40, 41], "out": [10, 13, 15, 18, 21, 25, 26, 36, 37, 38, 41], "funct3_v": 10, "seven": 10, "funct7_v": 10, "twelv": 10, "funct12_v": 10, "rd": [10, 17], "reg_cnt_log": 10, "rd_v": 10, "rs1": [10, 17], "hold": [10, 17, 18, 38], "first": [10, 13, 14, 20, 22, 27, 32, 33, 34, 35, 37, 38, 39, 40, 41], "rs1_v": 10, "rs2": [10, 17], "second": [10, 13, 20, 22, 32, 33, 34, 38, 41], "rs2_v": 10, "imm": [10, 17], "immedi": [10, 17, 18], "were": [10, 27, 35], "succ": 10, "successor": 10, "pred": 10, "predecessor": 10, "fm": 10, "sourc": [10, 20, 22, 24, 32, 36, 37, 38], "defin": [10, 14, 20, 35, 37, 38, 40, 41], "kind": [10, 13, 22, 38, 40], "illeg": [10, 17], "success": [10, 18, 39], "fit": 10, "constructor": [10, 35, 37, 40], "repres": [10, 20, 37, 38], "exist": [10, 35], "instr_type_overrid": 10, "specifi": [10, 18, 20, 33, 38, 40], "determin": [10, 11, 27, 34, 38, 40], "instrust": 10, "almost": 10, "correct": [10, 11, 14, 27, 32, 33, 34], "rd_zero": 10, "bool": [10, 14, 17, 20, 36, 37, 38, 39, 40, 41], "constant": 10, "other": [10, 17, 20, 24, 26, 35, 36, 37, 38, 41], "accordingli": 10, "default": [10, 18, 20, 24, 35, 36, 37, 38, 40, 41], "fals": [10, 13, 14, 24, 35, 36, 37, 38, 40, 41], "rs1_zero": 10, "instrdecompress": 10, "decompr_reg": 10, "rvc_reg": 10, "instr_mux": 10, "sel": [10, 18], "list": [10, 13, 17, 18, 24, 26, 30, 34, 36, 37, 38, 39, 40, 41], "tupl": [10, 11, 13, 18, 20, 22, 36, 37, 38, 39, 40, 41], "is_instr_compress": 10, "fetchunit": 11, "superscalar": 11, "respons": [11, 13, 14, 18, 22, 24, 37, 38, 39], "retriev": [11, 14, 38], "them": [11, 24, 27, 34, 35, 37, 38, 40], "work": [11, 22, 27, 30, 34, 35, 37, 38], "chunk": 11, "fetch_block_byt": 11, "relat": [11, 27, 37, 38, 40], "how": [11, 17, 20, 24, 27, 32, 34, 37, 38], "mani": [11, 17, 20, 24, 27, 34, 35, 36, 37, 38, 40], "onc": [11, 34, 35, 37, 38, 41], "vari": 11, "deal": 11, "expand": 11, "aren": [11, 27, 35, 38], "boundari": [11, 27], "cont": [11, 39], "predecod": 11, "analysi": [11, 26, 36], "jump": [11, 17, 27], "find": [11, 24, 27, 38], "target": [11, 34, 38], "Its": [11, 14, 31, 35], "role": [11, 35], "give": [11, 38, 40], "quick": 11, "feedback": 11, "potenti": [11, 31], "predictor": 11, "help": [11, 24, 27, 38], "redirect": 11, "promptli": 11, "predictioncheck": 11, "predict": 11, "checker": [11, 14], "look": [11, 27, 38], "taken": [11, 20, 22, 34, 37, 38], "mistak": [11, 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"alufuncunit": 13, "alu_fn": 13, "alufn": 13, "divcompon": 13, "ipc": [13, 34], "div_fn": 13, "divfn": 13, "decodermanag": 13, "fn": 13, "get_instruct": 13, "implement": [13, 14, 18, 20, 25, 26, 27, 31, 38, 40, 41], "format": [13, 24, 34, 35, 36, 37, 38, 40, 41], "divunit": 13, "get_input": 13, "arg": [13, 18, 35, 36, 37, 38, 39, 40, 41], "exceptionfuncunit": 13, "unit_fn": 13, "exceptionunitfn": 13, "exceptionunitcompon": 13, "jumpbranchfuncunit": 13, "jb_fn": 13, "jumpbranchfn": 13, "jumpcompon": 13, "mulcompon": 13, "mul_unit_typ": 13, "multyp": 13, "dsp_width": [13, 15], "mul_fn": 13, "mulfn": 13, "hot": [13, 27, 38, 41], "wire": 13, "recursive_mul": 13, "fastest": 13, "multipli": [13, 15], "costli": [13, 27], "term": 13, "resourc": [13, 21, 27, 34, 35, 37], "sequence_mul": 13, "dsp": [13, 15], "balanc": 13, "between": [13, 14, 24, 27, 35, 37, 38, 40, 41], "cost": [13, 26, 35], "shift_mul": 13, "cheapest": 13, "russian": [13, 15], "peasant": [13, 15], "algorithm": [13, 15, 38], "mulunit": 13, "unsign": [13, 15], "standard": [13, 21, 27, 34, 38, 41], "funcunitlayout": [13, 22], "comput": [13, 15, 17, 21, 27, 38, 40], "mul_typ": 13, "privilegedfn": 13, "classmethod": [13, 36, 37, 38, 40], "privilegedfuncunit": 13, "privilegedunitcompon": 13, "shiftfuncunit": 13, "shift_unit_fn": 13, "shiftunitfn": 13, "shiftunitcompon": 13, "clmultipli": 13, "product": [13, 38], "i1": [13, 15], "factor": 13, "i2": [13, 15], "reset": [13, 20, 26], "busi": 13, "while": [13, 37, 39], "progress": 13, "bit_width": [13, 20], "recursion_depth": 13, "depth": [13, 14, 18, 34, 38], "recurs": [13, 15, 34, 35, 36, 38, 40], "parallel": [13, 38], "power": [13, 40], "iterative_modul": 13, "recursive_modul": 13, "zbccompon": 13, "zbc_fn": 13, "zbcfn": 13, "zbcunit": 13, "zbsfunction": 13, "in1": 13, "in2": 13, "zbscompon": 13, "zbsunit": 13, "zbs_fn": 13, "lsucompon": 14, "lsudummi": 14, "veri": [14, 27, 35], "isn": [14, 34, 37], "compliant": [14, 34], "riscv": [14, 17, 34], "spec": [14, 21], "doesn": [14, 27, 30, 35, 38], "rang": [14, 37, 38, 39, 40, 41], "processor": [14, 25, 26, 31], "master": [14, 18, 34], "lsurequest": 14, "job": [14, 27], "resili": 14, "check_align": 14, "postprocess_load_data": 14, "modulelik": [14, 37, 38, 41], "raw_data": 14, "prepare_bytes_mask": 14, "prepare_data_to_sav": 14, "pmacheck": 14, "physic": [14, 22, 27], "mai": [14, 17, 24, 38, 39, 40], "part": [14, 17, 20, 21, 27, 31, 35, 37, 38], "combin": [14, 26, 30, 37, 38, 40], "circuit": [14, 34, 35, 37, 38, 40], "pmalayout": 14, "pmaregion": 14, "contigu": 14, "region": [14, 27], "includ": [14, 34, 35, 37, 38, 40, 41], "both": [14, 20, 32, 35, 37, 38, 40, 41], "begin": [14, 27, 41], "mmio": 14, "true": [14, 17, 18, 20, 35, 36, 37, 38, 39, 40, 41], "indic": [14, 27, 33, 37, 38, 41], "dspmulunit": 15, "clock": [15, 31, 34, 35, 36, 37, 38], "design": [15, 27, 35, 36], "synthesi": [15, 26, 37], "tool": [15, 24, 34, 36], "o": [15, 27, 35, 37], "same": [15, 17, 20, 24, 35, 37, 38, 40, 41], "mulbaseunsign": 15, "unsignedmulunitlayout": 15, "recursiveunsignedmul": 15, "see": [15, 21, 30, 34, 35, 38], "fast": 15, "within": [15, 24], "pipelinedunsignedmul": 15, "dsp_number": 15, "sequentialunsignedmul": 15, "sequenti": [15, 18], "classic": [15, 27], "shiftunsignedmul": 15, "cheap": 15, "multi": [15, 41], "funcblocksunifi": 16, "blockcomponentparam": [16, 17], "funcblock": [16, 17, 22], "insert": [16, 21, 22, 26, 27, 31, 32, 38], "coreconfigur": 17, "_coreconfigurationdataclass": 17, "kwarg": [17, 18, 36, 37, 38, 39, 40, 41], "self": [17, 35, 37, 39], "get_rs_entry_count": 17, "optypes_support": 17, "dependentcach": [17, 40], "cfg": 17, "addr_width": [17, 18], "word_width": 17, "word": [17, 41], "num_of_wai": 17, "num_of_sets_bit": 17, "line_bytes_log": 17, "disabl": [17, 36, 38, 39], "bypass": 17, "fetch_block_bytes_log": 17, "python": [17, 24, 35, 37, 38, 39, 40], "model": 17, "stefan": 17, "wallentowitz": 17, "http": [17, 34, 39], "github": [17, 25, 34, 39], "com": [17, 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"envversion": {"sphinx.domains.c": 2, "sphinx.domains.changeset": 1, "sphinx.domains.citation": 1, "sphinx.domains.cpp": 6, "sphinx.domains.index": 1, "sphinx.domains.javascript": 2, "sphinx.domains.math": 2, "sphinx.domains.python": 3, "sphinx.domains.rst": 2, "sphinx.domains.std": 2, "sphinx.ext.intersphinx": 1, "sphinx.ext.todo": 2, "sphinx": 56}}) \ No newline at end of file diff --git a/shared-structs/implementation/rs-impl.html b/shared-structs/implementation/rs-impl.html index f324843c1..8de4b69a3 100644 --- a/shared-structs/implementation/rs-impl.html +++ b/shared-structs/implementation/rs-impl.html @@ -252,7 +252,7 @@

Read and clean row

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/shared-structs/rs.html b/shared-structs/rs.html index 408d2bcb2..33a001df2 100644 --- a/shared-structs/rs.html +++ b/shared-structs/rs.html @@ -222,7 +222,7 @@

External interface signals

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/synthesis/synthesis.html b/synthesis/synthesis.html index 29c89ce2e..b5761c4e9 100644 --- a/synthesis/synthesis.html +++ b/synthesis/synthesis.html @@ -266,7 +266,7 @@

Regression tests manual execution

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/transactions.html b/transactions.html index e252927e8..1580a4978 100644 --- a/transactions.html +++ b/transactions.html @@ -409,7 +409,7 @@

Transaction and method nesting

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/transactron.core.html b/transactron.core.html index 6d0448fe2..e7c11143d 100644 --- a/transactron.core.html +++ b/transactron.core.html @@ -106,7 +106,7 @@

Submodules
class transactron.core.manager.TransactionComponent
-

Bases: TransactionModule, Component

+

Bases: TransactionModule, Component

Top-level component for Transactron projects.

The TransactronComponent is a wrapper on Component classes, which adds Transactron support for the wrapped class. The use @@ -156,7 +156,7 @@

Submodules
-debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -252,7 +252,7 @@

Submodules
-__init__(*, name: Optional[str] = None, i: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), o: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), nonexclusive: bool = False, combiner: Optional[Callable[[Module, Sequence[View[StructLayout]], Value], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg] | collections.abc.Mapping[int, AssignArg] | collections.abc.Sequence[AssignArg]]] = None, single_caller: bool = False, src_loc: int | tuple[str, int] = 0)
+__init__(*, name: Optional[str] = None, i: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), o: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), nonexclusive: bool = False, combiner: Optional[Callable[[Module, Sequence[View[StructLayout]], Value], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg] | collections.abc.Mapping[int, AssignArg] | collections.abc.Sequence[AssignArg]]] = None, single_caller: bool = False, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -338,7 +338,7 @@

Submodules
-debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -598,7 +598,7 @@

Submodules
-AvoidedIf(cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+AvoidedIf(cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

@@ -628,7 +628,7 @@

Submodules
-If(cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+If(cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

@@ -638,7 +638,7 @@

Submodules
-Switch(test: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+Switch(test: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

@@ -747,7 +747,7 @@

Submodules
-debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -845,7 +845,7 @@

Submodules
-method_calls: defaultdict[Method, list[tuple[transactron.core.tmodule.CtrlPath, 'View[StructLayout]', amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]]
+method_calls: defaultdict[Method, list[tuple[transactron.core.tmodule.CtrlPath, 'View[StructLayout]', amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]]

@@ -960,7 +960,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/transactron.html b/transactron.html index bbcc901e4..3bf9e8a78 100644 --- a/transactron.html +++ b/transactron.html @@ -752,7 +752,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/transactron.lib.html b/transactron.lib.html index 8741f5984..785cbf199 100644 --- a/transactron.lib.html +++ b/transactron.lib.html @@ -136,10 +136,10 @@

Submodules
class transactron.lib.adapters.AdapterBase
-

Bases: Component

+

Bases: Component

-__init__(iface: Method, layout_in: StructLayout, layout_out: StructLayout)
+__init__(iface: Method, layout_in: StructLayout, layout_out: StructLayout)
@@ -154,7 +154,7 @@

Submodules
-debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

@@ -236,7 +236,7 @@

Submodules
-__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], src_loc: int | tuple[str, int] = 0)
+__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], src_loc: int | tuple[str, int] = 0)
Parameters
@@ -275,7 +275,7 @@

Submodules
-__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], *, src_loc: int | tuple[str, int] = 0)
+__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], *, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -318,7 +318,7 @@

Submodules
-__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), rev_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), *, src_loc: int | tuple[str, int] = 0)
+__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), rev_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), *, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -432,7 +432,7 @@

Submodules
-__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], *, src_loc: int | tuple[str, int] = 0)
+__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], *, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -503,7 +503,7 @@

Submodules
-__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']])
+__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']])
Parameters
@@ -537,7 +537,7 @@

Submodules
-__init__(n: int, layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']])
+__init__(n: int, layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']])

@@ -737,7 +737,7 @@

Submodules
-__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], depth: int, *, src_loc: int | tuple[str, int] = 0) → None
+__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], depth: int, *, src_loc: int | tuple[str, int] = 0) → None
Parameters
@@ -822,7 +822,7 @@

Submodules
-assertion(m: ModuleLike, value: Value, format: str = '', *args, src_loc_at: int = 0, **kwargs)
+assertion(m: ModuleLike, value: Value, format: str = '', *args, src_loc_at: int = 0, **kwargs)

Define an assertion.

This function might help find some hardware bugs which might otherwise be hard to detect. If value is false, it will terminate the simulation or @@ -833,14 +833,14 @@

Submodules
-debug(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)
+debug(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)

Log a message with severity ‘DEBUG’.

See HardwareLogger.log function for more details.

-error(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)
+error(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)

Log a message with severity ‘ERROR’.

This severity level has special semantics. If a log with this serverity level is triggered, the simulation will be terminated.

@@ -849,14 +849,14 @@

Submodules
-info(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)
+info(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)

Log a message with severity ‘INFO’.

See HardwareLogger.log function for more details.

-log(m: ModuleLike, level: int, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, src_loc_at: int = 0)
+log(m: ModuleLike, level: int, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, src_loc_at: int = 0)

Registers a hardware log record with the given severity.

Parameters
@@ -880,7 +880,7 @@

Submodules
-warning(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)
+warning(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)

Log a message with severity ‘WARNING’.

See HardwareLogger.log function for more details.

@@ -1029,7 +1029,7 @@

Submodules
-transactron.lib.logging.get_trigger_bit(level: int, namespace_regexp: str = '.*') → Value
+transactron.lib.logging.get_trigger_bit(level: int, namespace_regexp: str = '.*') → Value

Get a trigger bit for logs of the given severity level and in the specified namespace.

The signal returned by this function is high whenever the trigger signal @@ -1134,7 +1134,7 @@

Submodules
-debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

Returns tree-like SignalBundle composed of all metric registers.

@@ -1236,7 +1236,7 @@

Submodules
-add(m: TModule, sample: Value)
+add(m: TModule, sample: Value)

Adds a new sample to the histogram.

Should be called in the body of either a transaction or a method.

@@ -1568,7 +1568,7 @@

Submodules
-start(m: TModule, *, slot: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+start(m: TModule, *, slot: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

Registers the start of an event for a given slot tag.

Should be called in the body of either a transaction or a method.

@@ -1585,7 +1585,7 @@

Submodules
-stop(m: TModule, *, slot: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+stop(m: TModule, *, slot: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

Registers the end of the event for a given slot tag.

Should be called in the body of either a transaction or a method.

@@ -1645,7 +1645,7 @@

Submodules
-__init__(args_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], results_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], src_loc: int | tuple[str, int] = 0)
+__init__(args_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], results_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], src_loc: int | tuple[str, int] = 0)
Parameters
@@ -1764,24 +1764,28 @@

Submodulesclass transactron.lib.storage.AsyncMemoryBank

Bases: Elaboratable

AsyncMemoryBank module.

-

Provides a transactional interface to asynchronous Amaranth Memory with one -read and one write port. It supports optionally writing with given granularity.

+

Provides a transactional interface to asynchronous Amaranth Memory with arbitrary number of +read and write ports. It supports optionally writing with given granularity.

Attributes
-
read: Method

The read method. Accepts an addr from which data should be read. +

reads: list[Method]

The read methods, one for each read port. Accepts an addr from which data should be read. The read response method. Return data_layout View which was saved on addr given by last -read_req method call.

+write method call.

-
write: Method

The write method. Accepts addr where data should be saved, data in form of data_layout +

writes: list[Method]

The write methods, one for each write port. Accepts write address addr, data in form of data_layout and optionally mask if granularity is not None. 1 in mask means that appropriate part should be written.

+
read: Method

The only method from reads, if the memory has a single read port.

+
+
write: Method

The only method from writes, if the memory has a single write port.

+
-__init__(*, data_layout: list[tuple[str, 'ShapeLike | LayoutList']], elem_count: int, granularity: Optional[int] = None, src_loc: int | tuple[str, int] = 0)
+__init__(*, data_layout: list[tuple[str, 'ShapeLike | LayoutList']], elem_count: int, granularity: Optional[int] = None, read_ports: int = 1, write_ports: int = 1, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -1792,6 +1796,10 @@

Submodules
-__init__(address_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], data_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], entries_number: int)
+__init__(address_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], data_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], entries_number: int)
Parameters
@@ -1856,26 +1864,36 @@

Submodulesclass transactron.lib.storage.MemoryBank

Bases: Elaboratable

MemoryBank module.

-

Provides a transactional interface to synchronous Amaranth Memory with one -read and one write port. It supports optionally writing with given granularity.

+

Provides a transactional interface to synchronous Amaranth Memory with arbitrary +number of read and write ports. It supports optionally writing with given granularity.

Attributes
-
read_req: Method

The read request method. Accepts an addr from which data should be read. -Only ready if there is there is a place to buffer response.

+
read_reqs: list[Method]

The read request methods, one for each read port. Accepts an addr from which data should be read. +Only ready if there is there is a place to buffer response. After calling read_reqs[i], the result +will be available via the method read_resps[i].

-
read_resp: Method

The read response method. Return data_layout View which was saved on addr given by last -read_req method call. Only ready after read_req call.

+
read_resps: list[Method]

The read response methods, one for each read port. Return data_layout View which was saved on addr given +by last corresponding read_reqs method call. Only ready after corresponding read_reqs call.

-
write: Method

The write method. Accepts addr where data should be saved, data in form of data_layout +

writes: list[Method]

The write methods, one for each write port. Accepts write address addr, data in form of data_layout and optionally mask if granularity is not None. 1 in mask means that appropriate part should be written.

+
read_req: Method

The only method from read_reqs, if the memory has a single read port. If it has more ports, this method +is unavailable and read_reqs should be used instead.

+
+
read_resp: Method

The only method from read_resps, if the memory has a single read port. If it has more ports, this method +is unavailable and read_resps should be used instead.

+
+
write: Method

The only method from writes, if the memory has a single write port. If it has more ports, this method +is unavailable and writes should be used instead.

+
-__init__(*, data_layout: list[tuple[str, 'ShapeLike | LayoutList']], elem_count: int, granularity: Optional[int] = None, transparent: bool = False, src_loc: int | tuple[str, int] = 0)
+__init__(*, data_layout: list[tuple[str, 'ShapeLike | LayoutList']], elem_count: int, granularity: Optional[int] = None, transparent: bool = False, read_ports: int = 1, write_ports: int = 1, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -1890,6 +1908,10 @@

Submodules
-__init__(method1: Method, method2: Method, *, i_fun: Optional[Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]] = None, o_fun: Optional[Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]] = None, src_loc: int | tuple[str, int] = 0)
+__init__(method1: Method, method2: Method, *, i_fun: Optional[Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]] = None, o_fun: Optional[Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]] = None, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -2021,7 +2043,7 @@

Submodules
-__init__(target: Method, condition: Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable], default: Optional[Union[Value, int, Enum, ValueCastable, Mapping[str, RecordDict]]] = None, *, use_condition: bool = False, src_loc: int | tuple[str, int] = 0)
+__init__(target: Method, condition: Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable], default: Optional[Union[Value, int, Enum, ValueCastable, Mapping[str, RecordDict]]] = None, *, use_condition: bool = False, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -2066,7 +2088,7 @@

Submodules
-__init__(target: Method, *, i_transform: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, 'View[StructLayout]'], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, o_transform: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, 'View[StructLayout]'], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, src_loc: int | tuple[str, int] = 0)
+__init__(target: Method, *, i_transform: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, 'View[StructLayout]'], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, o_transform: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, 'View[StructLayout]'], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -2096,7 +2118,7 @@

SubmodulesElaboratable, Unifier

-__init__(targets: list[transactron.core.method.Method], combiner: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, list['View[StructLayout]']], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, *, src_loc: int | tuple[str, int] = 0)
+__init__(targets: list[transactron.core.method.Method], combiner: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, list['View[StructLayout]']], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, *, src_loc: int | tuple[str, int] = 0)

Method product.

Takes arbitrary, non-zero number of target methods, and constructs a method which calls all of the target methods using the same @@ -2135,7 +2157,7 @@

SubmodulesElaboratable, Unifier

-__init__(targets: list[transactron.core.method.Method], combiner: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, list[tuple[amaranth.hdl._ast.Value, 'View[StructLayout]']]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, *, src_loc: int | tuple[str, int] = 0)
+__init__(targets: list[transactron.core.method.Method], combiner: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, list[tuple[amaranth.hdl._ast.Value, 'View[StructLayout]']]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, *, src_loc: int | tuple[str, int] = 0)

Method product with optional calling.

Takes arbitrary, non-zero number of target methods, and constructs a method which tries to call all of the target methods using the same @@ -2238,7 +2260,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/transactron.testing.html b/transactron.testing.html index d63da4618..38b6b697c 100644 --- a/transactron.testing.html +++ b/transactron.testing.html @@ -91,7 +91,7 @@

Submodules

transactron.testing.functions module

-transactron.testing.functions.get_outputs(field: View) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Union[int, RecordIntDict]]]
+transactron.testing.functions.get_outputs(field: View) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Union[int, RecordIntDict]]]
@@ -120,7 +120,7 @@

Submodules
class transactron.testing.infrastructure.PysimSimulator
-

Bases: Simulator

+

Bases: Simulator

__init__(module: HasElaborate, max_cycles: float = 100000.0, add_transaction_module=True, traces_file=None, clk_period=1e-06)
@@ -128,7 +128,7 @@

Submodules
-add_process(f: Callable[[], Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, T]])
+add_process(f: Callable[[], Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, T]])

@@ -269,12 +269,12 @@

Submodules
-transactron.testing.input_generation.generate_based_on_layout(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]) → SearchStrategy[Mapping[str, Union[int, RecordIntDict]]]
+transactron.testing.input_generation.generate_based_on_layout(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]) → SearchStrategy[Mapping[str, Union[int, RecordIntDict]]]

-transactron.testing.input_generation.generate_method_input(args: list[tuple[str, amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]]]) → Union[int, ForwardRef('RecordIntDict')]]]]
+transactron.testing.input_generation.generate_method_input(args: list[tuple[str, amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]]]) → Union[int, ForwardRef('RecordIntDict')]]]]
@@ -284,7 +284,7 @@

Submodules
-transactron.testing.input_generation.generate_process_input(elem_count: int, max_nops: int, layouts: list[tuple[str, amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]]]) → OpNOP]]
+transactron.testing.input_generation.generate_process_input(elem_count: int, max_nops: int, layouts: list[tuple[str, amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]]]) → OpNOP]]

@@ -329,7 +329,7 @@

Submodules

transactron.testing.sugar module

-transactron.testing.sugar.def_method_mock(tb_getter: Union[Callable[[], TestbenchIO], Callable[[Any], TestbenchIO]], sched_prio: int = 0, **kwargs) → Callable[[Callable[[...], Optional[Mapping[str, Union[int, RecordIntDict]]]]], Callable[[], Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]]]
+transactron.testing.sugar.def_method_mock(tb_getter: Union[Callable[[], TestbenchIO], Callable[[Any], TestbenchIO]], sched_prio: int = 0, **kwargs) → Callable[[Callable[[...], Optional[Mapping[str, Union[int, RecordIntDict]]]]], Callable[[], Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]]]

Decorator function to create method mock handlers. It should be applied on a function which describes functionality which we want to invoke on method call. Such function will be wrapped by method_handle_loop and called on each @@ -368,87 +368,87 @@

Submodules
-call(data: Mapping[str, Union[int, RecordIntDict]] = {}, /, **kwdata: int | collections.abc.Mapping[str, Union[int, RecordIntDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Any]]
+call(data: Mapping[str, Union[int, RecordIntDict]] = {}, /, **kwdata: int | collections.abc.Mapping[str, Union[int, RecordIntDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Any]]

-call_do() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Union[int, RecordIntDict]]]
+call_do() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Union[int, RecordIntDict]]]
-call_init(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}, /, **kwdata: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, Union[amaranth.hdl._ast.Value, int, enum.Enum, amaranth.hdl._ast.ValueCastable, RecordValueDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
+call_init(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}, /, **kwdata: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, Union[amaranth.hdl._ast.Value, int, enum.Enum, amaranth.hdl._ast.ValueCastable, RecordValueDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
-call_result() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Optional[Mapping[str, Any]]]
+call_result() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Optional[Mapping[str, Any]]]
-call_try(data: Mapping[str, Union[int, RecordIntDict]] = {}, /, **kwdata: int | collections.abc.Mapping[str, Union[int, RecordIntDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Optional[Mapping[str, Any]]]
+call_try(data: Mapping[str, Union[int, RecordIntDict]] = {}, /, **kwdata: int | collections.abc.Mapping[str, Union[int, RecordIntDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Optional[Mapping[str, Any]]]
-debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
-disable() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
+disable() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
-done() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, int]
+done() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, int]
-enable() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
+enable() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
-get_outputs() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Any]]
+get_outputs() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Any]]
-method_argument() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Optional[Mapping[str, Any]]]
+method_argument() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Optional[Mapping[str, Any]]]
-method_handle(function: Callable[[...], Optional[Mapping[str, Union[int, RecordIntDict]]]], *, enable: Optional[Callable[[], bool]] = None, validate_arguments: Optional[Callable[[...], bool]] = None, extra_settle_count: int = 0) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
+method_handle(function: Callable[[...], Optional[Mapping[str, Union[int, RecordIntDict]]]], *, enable: Optional[Callable[[], bool]] = None, validate_arguments: Optional[Callable[[...], bool]] = None, extra_settle_count: int = 0) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
-method_handle_loop(function: Callable[[...], Optional[Mapping[str, Union[int, RecordIntDict]]]], *, enable: Optional[Callable[[], bool]] = None, validate_arguments: Optional[Callable[[...], bool]] = None, extra_settle_count: int = 0) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
+method_handle_loop(function: Callable[[...], Optional[Mapping[str, Union[int, RecordIntDict]]]], *, enable: Optional[Callable[[], bool]] = None, validate_arguments: Optional[Callable[[...], bool]] = None, extra_settle_count: int = 0) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
-method_return(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
+method_return(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
-set_enable(en) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
+set_enable(en) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
-set_inputs(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
+set_inputs(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
-wait_until_done() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
+wait_until_done() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]

@@ -471,7 +471,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/transactron.utils.amaranth_ext.html b/transactron.utils.amaranth_ext.html index afad04211..adbc48e4b 100644 --- a/transactron.utils.amaranth_ext.html +++ b/transactron.utils.amaranth_ext.html @@ -151,7 +151,7 @@

Submodules
-static create(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, outputs_count: int = 1, name: Optional[str] = None) → list[tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]]
+static create(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, outputs_count: int = 1, name: Optional[str] = None) → list[tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]]

Syntax sugar for creating MultiPriorityEncoder

This static method allows to use MultiPriorityEncoder in a more functional way. Instead of creating the instance manually, connecting all the signals and @@ -193,7 +193,7 @@

Submodules
-static create_simple(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, name: Optional[str] = None) → tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]
+static create_simple(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, name: Optional[str] = None) → tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]

Syntax sugar for creating MultiPriorityEncoder

This is the same as create function, but with outputs_count hardcoded to 1.

@@ -202,7 +202,7 @@

Submodules
-transactron.utils.amaranth_ext.elaboratables.OneHotSwitch(m: ModuleLike, test: Value)
+transactron.utils.amaranth_ext.elaboratables.OneHotSwitch(m: ModuleLike, test: Value)

One-hot switch.

This function allows one-hot matching in the style similar to the standard Amaranth Switch. This allows to get the performance benefit of using @@ -232,9 +232,9 @@

Submodules
-transactron.utils.amaranth_ext.elaboratables.OneHotSwitchDynamic(m: ModuleLike, test: Value, *, default: Literal[True]) → Iterable[Optional[int]]
+transactron.utils.amaranth_ext.elaboratables.OneHotSwitchDynamic(m: ModuleLike, test: Value, *, default: Literal[True]) → Iterable[Optional[int]]
-transactron.utils.amaranth_ext.elaboratables.OneHotSwitchDynamic(m: ModuleLike, test: Value, *, default: Literal[False] = False) → Iterable[int]
+transactron.utils.amaranth_ext.elaboratables.OneHotSwitchDynamic(m: ModuleLike, test: Value, *, default: Literal[False] = False) → Iterable[int]

Dynamic one-hot switch.

This function allows simple one-hot matching on signals which can have variable bit widths.

@@ -300,7 +300,7 @@

Submodules
-static create(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, first: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, last: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, outputs_count: int = 1, name: Optional[str] = None) → list[tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]]
+static create(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, first: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, last: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, outputs_count: int = 1, name: Optional[str] = None) → list[tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]]

Syntax sugar for creating RingMultiPriorityEncoder

This static method allows to use RingMultiPriorityEncoder in a more functional way. Instead of creating the instance manually, connecting all the signals and @@ -348,7 +348,7 @@

Submodules
-static create_simple(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, first: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, last: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, name: Optional[str] = None) → tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]
+static create_simple(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, first: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, last: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, name: Optional[str] = None) → tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]

Syntax sugar for creating RingMultiPriorityEncoder

This is the same as create function, but with outputs_count hardcoded to 1.

@@ -436,29 +436,29 @@

Submodules

transactron.utils.amaranth_ext.functions module

-transactron.utils.amaranth_ext.functions.count_leading_zeros(s: Value) → Value
+transactron.utils.amaranth_ext.functions.count_leading_zeros(s: Value) → Value
-transactron.utils.amaranth_ext.functions.count_trailing_zeros(s: Value) → Value
+transactron.utils.amaranth_ext.functions.count_trailing_zeros(s: Value) → Value
-transactron.utils.amaranth_ext.functions.flatten_signals(signals: amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]) → Iterable[Signal]
+transactron.utils.amaranth_ext.functions.flatten_signals(signals: amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]) → Iterable[Signal]

Flattens input data, which can be either a signal, a record, a list (or a dict) of SignalBundle items.

-transactron.utils.amaranth_ext.functions.mod_incr(sig: Value, mod: int) → Value
+transactron.utils.amaranth_ext.functions.mod_incr(sig: Value, mod: int) → Value

Perform (sig+1) % mod operation.

-transactron.utils.amaranth_ext.functions.popcount(s: Value)
+transactron.utils.amaranth_ext.functions.popcount(s: Value)
@@ -478,7 +478,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.

diff --git a/transactron.utils.html b/transactron.utils.html index 92f7e505c..32b84b2e1 100644 --- a/transactron.utils.html +++ b/transactron.utils.html @@ -131,7 +131,7 @@

Submodules
-transactron.utils.assign.assign(lhs: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg] | collections.abc.Mapping[int, AssignArg] | collections.abc.Sequence[AssignArg], rhs: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg] | collections.abc.Mapping[int, AssignArg] | collections.abc.Sequence[AssignArg], *, fields: transactron.utils.assign.AssignType | collections.abc.Iterable[str | int] | collections.abc.Mapping[str | int, AssignFields] = AssignType.RHS, lhs_strict=False, rhs_strict=False) → Iterable[Assign]
+transactron.utils.assign.assign(lhs: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg] | collections.abc.Mapping[int, AssignArg] | collections.abc.Sequence[AssignArg], rhs: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg] | collections.abc.Mapping[int, AssignArg] | collections.abc.Sequence[AssignArg], *, fields: transactron.utils.assign.AssignType | collections.abc.Iterable[str | int] | collections.abc.Mapping[str | int, AssignFields] = AssignType.RHS, lhs_strict=False, rhs_strict=False) → Iterable[Assign]

Safe structured assignment.

This function recursively generates assignment statements for field-containing structures. This includes: @@ -250,7 +250,7 @@

Submodules
-transactron.utils.data_repr.data_layout(val: amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum]) → amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]
+transactron.utils.data_repr.data_layout(val: amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum]) → amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]

@@ -277,7 +277,7 @@

Submodules
-transactron.utils.data_repr.layout_subset(layout: StructLayout, *, fields: set[str]) → StructLayout
+transactron.utils.data_repr.layout_subset(layout: StructLayout, *, fields: set[str]) → StructLayout

@@ -334,7 +334,7 @@

Submodules

transactron.utils.debug_signals module

-transactron.utils.debug_signals.auto_debug_signals(thing) → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
+transactron.utils.debug_signals.auto_debug_signals(thing) → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

Automatic debug signal generation.

Exposes class attributes with debug signals (Amaranth Signals, Records, Arrays and Elaboratables, Methods, classes @@ -735,7 +735,7 @@

Submodules
-transactron.utils.gen.generate_verilog(elaboratable: Elaboratable, ports: Optional[list[amaranth.hdl._ast.Value]] = None, top_name: str = 'top') → tuple[str, transactron.utils.gen.GenerationInfo]
+transactron.utils.gen.generate_verilog(elaboratable: Elaboratable, ports: Optional[list[amaranth.hdl._ast.Value]] = None, top_name: str = 'top') → tuple[str, transactron.utils.gen.GenerationInfo]

@@ -762,12 +762,12 @@

Submodules
-transactron.utils.transactron_helpers.extend_layout(layout: StructLayout, *fields: tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]) → StructLayout
+transactron.utils.transactron_helpers.extend_layout(layout: StructLayout, *fields: tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]) → StructLayout

-transactron.utils.transactron_helpers.from_method_layout(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]]) → StructLayout
+transactron.utils.transactron_helpers.from_method_layout(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]]) → StructLayout
@@ -787,7 +787,7 @@

Submodules
-transactron.utils.transactron_helpers.make_layout(*fields: tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]) → StructLayout
+transactron.utils.transactron_helpers.make_layout(*fields: tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]) → StructLayout

@@ -823,7 +823,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 07:48 2024-10-15. + Last updated on 19:36 2024-11-01.