From 8bdad9caa4471ae88f83b09f1ac01d8568f953e1 Mon Sep 17 00:00:00 2001 From: tilk Date: Tue, 10 Dec 2024 09:56:32 +0000 Subject: [PATCH] Synchronous register file using MemoryBank (#765) --- .doctrees/api.doctree | Bin 2239571 -> 2239571 bytes .doctrees/auto_graph.doctree | Bin 93272 -> 94776 bytes .doctrees/coreblocks.scheduler.doctree | Bin 42480 -> 46611 bytes .doctrees/current-graph.doctree | Bin 94493 -> 95997 bytes .doctrees/environment.pickle | Bin 2676596 -> 2676596 bytes _sources/auto_graph.rst.txt | 618 ++++++++--------- api.html | 2 +- assumptions.html | 2 +- auto_graph.html | 620 +++++++++--------- components/icache.html | 2 +- coreblocks.arch.html | 2 +- coreblocks.backend.html | 2 +- coreblocks.cache.html | 2 +- coreblocks.core_structs.html | 2 +- coreblocks.frontend.decoder.html | 2 +- coreblocks.frontend.fetch.html | 2 +- coreblocks.frontend.html | 2 +- coreblocks.func_blocks.fu.fpu.html | 2 +- coreblocks.func_blocks.fu.html | 2 +- coreblocks.func_blocks.fu.lsu.html | 2 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z2@N+eDX+&<8USFCeQ3APlmS)v9o+x>hjYy>?~`eEcArfjxgzf&!N(pS2Yejyal*$L zA0s|4__*TZhL1Zw9{70Tk diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index da6147e17..8e8952b41 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -6,9 +6,9 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] + WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_request["request"] WishboneMaster_result["result"] - WishboneMaster_WishboneMaster["WishboneMaster"] subgraph Forwarder["result Forwarder"] Forwarder_read["read"] Forwarder_write["write"] @@ -24,37 +24,37 @@ end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_serialize_in0["serialize_in0"] Serializer_serialize_out0["serialize_out0"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] + WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_read["request_read"] WishboneMasterAdapter1_get_write_response["get_write_response"] - WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] - Serializer1_serialize_out0["serialize_out0"] Serializer1_serialize_out1["serialize_out1"] + Serializer1_serialize_out0["serialize_out0"] Serializer1_serialize_in0["serialize_in0"] Serializer1_serialize_in1["serialize_in1"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_write["write"] BasicFifo1_read["read"] + BasicFifo1_write["write"] end end end subgraph CoreFrontend["frontend CoreFrontend"] + CoreFrontend_stall["stall"] CoreFrontend_target_pred_resp["target_pred_resp"] CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] - CoreFrontend_stall["stall"] CoreFrontend_target_pred_req["target_pred_req"] subgraph BasicFifo2["instr_buffer BasicFifo"] BasicFifo2_write["write"] @@ -62,22 +62,22 @@ BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_read["read"] Forwarder2_write["write"] + Forwarder2_read["read"] end end subgraph ICache["icache ICache"] - ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] ICache_ICache["ICache"] ICache_flush["flush"] ICache_ICache1["ICache"] + ICache_accept_res["accept_res"] ICache_MemRead["MemRead"] + ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -105,30 +105,30 @@ end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_peek_arg["peek_arg"] ArgumentsToResultsZipper_write_args["write_args"] + ArgumentsToResultsZipper_peek_arg["peek_arg"] ArgumentsToResultsZipper_write_results["write_results"] ArgumentsToResultsZipper_read["read"] subgraph BasicFifo3["fifo BasicFifo"] BasicFifo3_peek["peek"] - BasicFifo3_write["write"] BasicFifo3_read["read"] + BasicFifo3_write["write"] end subgraph Forwarder3["forwarder Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end end subgraph FetchUnit["fetch FetchUnit"] - FetchUnit_stall_exception["stall_exception"] FetchUnit_Fetch_Stage1["Fetch_Stage1"] - FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] - FetchUnit_resume_from_unsafe["resume_from_unsafe"] - FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] FetchUnit_resume_from_exception["resume_from_exception"] + FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] + FetchUnit_resume_from_unsafe["resume_from_unsafe"] FetchUnit_Fetch_Stage2["Fetch_Stage2"] + FetchUnit_stall_exception["stall_exception"] FetchUnit_Fetch_Stage0["Fetch_Stage0"] + FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] end @@ -148,12 +148,12 @@ BasicFifo4_read["read"] end subgraph Semaphore["req_counter Semaphore"] - Semaphore_acquire["acquire"] Semaphore_release["release"] + Semaphore_acquire["acquire"] end subgraph Pipe["s1_s2_pipe Pipe"] - Pipe_read["read"] Pipe_write["write"] + Pipe_read["read"] end subgraph Predecoder["predecoder_0 Predecoder"] Predecoder_predecode["predecode"] @@ -172,9 +172,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] - Pipe1_read["read"] Pipe1_clean["clean"] Pipe1_write["write"] + Pipe1_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -195,20 +195,29 @@ RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_write["write"] - RegisterFile_read2["read2"] - RegisterFile_free["free"] RegisterFile_perf["perf"] - RegisterFile_read1["read1"] + RegisterFile_read_req1["read_req1"] + RegisterFile_free["free"] + RegisterFile_read_resp2["read_resp2"] + RegisterFile_write["write"] + RegisterFile_read_req2["read_req2"] + RegisterFile_read_resp1["read_resp1"] + subgraph MemoryBank["entries MemoryBank"] + MemoryBank_write0["write0"] + MemoryBank_read_req0["read_req0"] + MemoryBank_read_req1["read_req1"] + MemoryBank_read_resp0["read_resp0"] + MemoryBank_read_resp1["read_resp1"] + end subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer__start["_start"] TaggedLatencyMeasurer__stop["_stop"] + TaggedLatencyMeasurer__start["_start"] subgraph HwExpHistogram1["histogram HwExpHistogram"] HwExpHistogram1__add["_add"] end subgraph AsyncMemoryBank["slots AsyncMemoryBank"] - AsyncMemoryBank_read0["read0"] AsyncMemoryBank_write0["write0"] + AsyncMemoryBank_read0["read0"] end end subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] @@ -216,11 +225,11 @@ end end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_perf["perf"] - ReorderBuffer_retire["retire"] - ReorderBuffer_put["put"] ReorderBuffer_peek["peek"] ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_retire["retire"] + ReorderBuffer_put["put"] + ReorderBuffer_perf["perf"] ReorderBuffer_mark_done["mark_done"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] FIFOLatencyMeasurer1__stop["_stop"] @@ -229,8 +238,8 @@ HwExpHistogram3__add["_add"] end subgraph FIFO1["fifo FIFO"] - FIFO1_read["read"] FIFO1_write["write"] + FIFO1_read["read"] end end subgraph HwExpHistogram4["perf_rob_size HwExpHistogram"] @@ -238,12 +247,12 @@ end end subgraph ExceptionInformationRegister["exception_information_register ExceptionInformationRegister"] - ExceptionInformationRegister_report["report"] - ExceptionInformationRegister_clear["clear"] ExceptionInformationRegister_get["get"] + ExceptionInformationRegister_clear["clear"] + ExceptionInformationRegister_report["report"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] - BasicFifo6_read["read"] BasicFifo6_write["write"] + BasicFifo6_read["read"] end subgraph ConnectTrans1["report_connector ConnectTrans"] ConnectTrans1_ConnectTrans["ConnectTrans"] @@ -275,30 +284,30 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] + RSFuncBlock_select["select"] RSFuncBlock_get_result["get_result"] - RSFuncBlock_update["update"] RSFuncBlock_insert["insert"] - RSFuncBlock_select["select"] + RSFuncBlock_update["update"] subgraph RS["rs RS"] - RS_perf["perf"] - RS_update["update"] + RS_insert["insert"] + RS_take["take"] RS_RS["RS"] + RS_perf["perf"] RS_RS1["RS"] - RS_RS2["RS"] RS_select["select"] - RS_insert["insert"] - RS_take["take"] + RS_RS2["RS"] RS_RS3["RS"] + RS_update["update"] RS_RS4["RS"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__start["_start"] TaggedLatencyMeasurer1__stop["_stop"] + TaggedLatencyMeasurer1__start["_start"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_read0["read0"] AsyncMemoryBank1_write0["write0"] + AsyncMemoryBank1_read0["read0"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -312,8 +321,8 @@ TaggedCounter4__incr["_incr"] end subgraph FIFO2["fifo FIFO"] - FIFO2_write["write"] FIFO2_read["read"] + FIFO2_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] @@ -331,8 +340,8 @@ WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO4["fifo_branch_resolved FIFO"] FIFO4_write["write"] FIFO4_read["read"] @@ -347,16 +356,16 @@ HwCounter8__incr["_incr"] end subgraph BasicFifo7["instr_fifo BasicFifo"] - BasicFifo7_read["read"] BasicFifo7_write["write"] + BasicFifo7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] + ExceptionFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] FIFO5_read["read"] FIFO5_write["write"] @@ -366,16 +375,16 @@ WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] + PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] - PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] - PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] - PrivilegedFuncUnit_issue["issue"] + PrivilegedFuncUnit_accept["accept"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] - BasicFifo8_read["read"] BasicFifo8_write["write"] + BasicFifo8_read["read"] end subgraph TaggedCounter6["perf_instr TaggedCounter"] TaggedCounter6__incr["_incr"] @@ -410,21 +419,21 @@ end end subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] - RSFuncBlock1_update["update"] RSFuncBlock1_get_result["get_result"] - RSFuncBlock1_select["select"] RSFuncBlock1_insert["insert"] + RSFuncBlock1_select["select"] + RSFuncBlock1_update["update"] subgraph RS1["rs RS"] - RS1_update["update"] - RS1_RS["RS"] - RS1_take["take"] - RS1_RS1["RS"] - RS1_perf["perf"] RS1_insert["insert"] + RS1_RS["RS"] + RS1_update["update"] RS1_select["select"] + RS1_perf["perf"] + RS1_RS1["RS"] + RS1_take["take"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer2__start["_start"] TaggedLatencyMeasurer2__stop["_stop"] + TaggedLatencyMeasurer2__start["_start"] subgraph HwExpHistogram7["histogram HwExpHistogram"] HwExpHistogram7__add["_add"] end @@ -438,20 +447,20 @@ end end subgraph MulUnit["func_unit_0 MulUnit"] + MulUnit_issue["issue"] MulUnit_MulUnit["MulUnit"] MulUnit_accept["accept"] - MulUnit_issue["issue"] subgraph FIFO6["result_fifo FIFO"] FIFO6_read["read"] FIFO6_write["write"] end subgraph FIFO7["params_fifo FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end subgraph SequentialUnsignedMul["multiplier SequentialUnsignedMul"] - SequentialUnsignedMul_accept["accept"] SequentialUnsignedMul_issue["issue"] + SequentialUnsignedMul_accept["accept"] subgraph DSPMulUnit["dsp DSPMulUnit"] DSPMulUnit_compute["compute"] end @@ -465,19 +474,19 @@ end subgraph DivUnit["func_unit_1 DivUnit"] DivUnit_DivUnit["DivUnit"] - DivUnit_accept["accept"] DivUnit_issue["issue"] + DivUnit_accept["accept"] subgraph BasicFifo9["result_fifo BasicFifo"] - BasicFifo9_read["read"] BasicFifo9_write["write"] + BasicFifo9_read["read"] end subgraph FIFO8["params_fifo FIFO"] - FIFO8_write["write"] FIFO8_read["read"] + FIFO8_write["write"] end subgraph LongDivider["divider LongDivider"] - LongDivider_issue["issue"] LongDivider_accept["accept"] + LongDivider_issue["issue"] end end subgraph WakeupSelect6["wakeup_select_1 WakeupSelect"] @@ -501,16 +510,16 @@ end subgraph RSFuncBlock2["rs_block_2 RSFuncBlock"] RSFuncBlock2_get_result["get_result"] - RSFuncBlock2_insert["insert"] RSFuncBlock2_select["select"] + RSFuncBlock2_insert["insert"] RSFuncBlock2_update["update"] subgraph FifoRS["rs FifoRS"] + FifoRS_select["select"] FifoRS_perf["perf"] FifoRS_take["take"] + FifoRS_FifoRS["FifoRS"] FifoRS_insert["insert"] - FifoRS_select["select"] FifoRS_update["update"] - FifoRS_FifoRS["FifoRS"] subgraph TaggedLatencyMeasurer3["perf_rs_wait_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer3__start["_start"] TaggedLatencyMeasurer3__stop["_stop"] @@ -518,8 +527,8 @@ HwExpHistogram9__add["_add"] end subgraph AsyncMemoryBank3["slots AsyncMemoryBank"] - AsyncMemoryBank3_write0["write0"] AsyncMemoryBank3_read0["read0"] + AsyncMemoryBank3_write0["write0"] end end subgraph HwExpHistogram10["perf_num_full HwExpHistogram"] @@ -527,22 +536,22 @@ end end subgraph LSUDummy["func_unit_0 LSUDummy"] - LSUDummy_LSUDummy["LSUDummy"] LSUDummy_issue["issue"] + LSUDummy_LSUDummy["LSUDummy"] LSUDummy_accept["accept"] LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_accept_cond1["accept_cond1"] + LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_accept_cond0["accept_cond0"] LSUDummy_LSUDummy3["LSUDummy"] subgraph LSURequester["requester LSURequester"] + LSURequester_accept["accept"] + LSURequester_accept_cond0["accept_cond0"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond2["issue_cond2"] LSURequester_issue["issue"] - LSURequester_accept_cond0["accept_cond0"] - LSURequester_accept_cond1["accept_cond1"] LSURequester_issue_cond0["issue_cond0"] - LSURequester_accept["accept"] - LSURequester_issue_cond2["issue_cond2"] + LSURequester_accept_cond1["accept_cond1"] subgraph BasicFifo10["args_fifo BasicFifo"] BasicFifo10_read["read"] BasicFifo10_write["write"] @@ -557,12 +566,12 @@ FIFO9_write["write"] end subgraph FIFO10["issued FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph FIFO11["issued_noop FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end end subgraph WakeupSelect7["wakeup_select_0 WakeupSelect"] @@ -582,12 +591,12 @@ end end subgraph CSRUnit["rs_block_3 CSRUnit"] - CSRUnit_insert["insert"] CSRUnit_get_result["get_result"] - CSRUnit_CSRUnit["CSRUnit"] CSRUnit_update["update"] - CSRUnit_select["select"] + CSRUnit_insert["insert"] CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_select["select"] + CSRUnit_CSRUnit["CSRUnit"] end end subgraph ResultAnnouncement["announcement ResultAnnouncement"] @@ -621,8 +630,8 @@ end end subgraph CSRRegister4["mscratch CSRRegister"] - CSRRegister4__internal_fu_read["_internal_fu_read"] CSRRegister4__internal_fu_write["_internal_fu_write"] + CSRRegister4__internal_fu_read["_internal_fu_read"] subgraph MethodMap8["fu_write_map MethodMap"] MethodMap8_method["method"] end @@ -649,9 +658,9 @@ end subgraph CSRRegister6["mcause CSRRegister"] CSRRegister6_read["read"] - CSRRegister6__internal_fu_write["_internal_fu_write"] - CSRRegister6_write["write"] CSRRegister6__internal_fu_read["_internal_fu_read"] + CSRRegister6_write["write"] + CSRRegister6__internal_fu_write["_internal_fu_write"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -667,10 +676,10 @@ AliasedCSR2__fu_read["_fu_read"] end subgraph CSRRegister7["mepc CSRRegister"] - CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7__internal_fu_read["_internal_fu_read"] - CSRRegister7_read["read"] CSRRegister7_write["write"] + CSRRegister7__internal_fu_write["_internal_fu_write"] + CSRRegister7_read["read"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] end @@ -713,10 +722,10 @@ CSRRegister10_write["write"] end subgraph CSRRegister11["mstatus_mie CSRRegister"] - CSRRegister11__internal_fu_write["_internal_fu_write"] - CSRRegister11__internal_fu_read["_internal_fu_read"] CSRRegister11_write["write"] + CSRRegister11__internal_fu_write["_internal_fu_write"] CSRRegister11_read["read"] + CSRRegister11__internal_fu_read["_internal_fu_read"] subgraph MethodMap22["fu_write_map MethodMap"] MethodMap22_method["method"] end @@ -728,8 +737,8 @@ end end subgraph CSRRegister12["mstatus_mpie CSRRegister"] - CSRRegister12_read["read"] CSRRegister12__internal_fu_write["_internal_fu_write"] + CSRRegister12_read["read"] CSRRegister12_write["write"] CSRRegister12__internal_fu_read["_internal_fu_read"] subgraph MethodMap24["fu_write_map MethodMap"] @@ -743,10 +752,10 @@ end end subgraph CSRRegister13["mstatus_mpp CSRRegister"] - CSRRegister13__internal_fu_read["_internal_fu_read"] CSRRegister13_write["write"] - CSRRegister13_read["read"] CSRRegister13__internal_fu_write["_internal_fu_write"] + CSRRegister13_read["read"] + CSRRegister13__internal_fu_read["_internal_fu_read"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -758,9 +767,9 @@ end end subgraph CSRRegister14["mstatus_mprv CSRRegister"] + CSRRegister14__internal_fu_write["_internal_fu_write"] CSRRegister14_write["write"] CSRRegister14__internal_fu_read["_internal_fu_read"] - CSRRegister14__internal_fu_write["_internal_fu_write"] subgraph MethodMap28["fu_write_map MethodMap"] MethodMap28_method["method"] end @@ -772,9 +781,9 @@ end end subgraph CSRRegister15["mstatus_tw CSRRegister"] - CSRRegister15__internal_fu_read["_internal_fu_read"] CSRRegister15__internal_fu_write["_internal_fu_write"] CSRRegister15_read["read"] + CSRRegister15__internal_fu_read["_internal_fu_read"] subgraph MethodMap30["fu_write_map MethodMap"] MethodMap30_method["method"] end @@ -786,8 +795,8 @@ end end subgraph CSRRegister16["mtvec_base CSRRegister"] - CSRRegister16__internal_fu_read["_internal_fu_read"] CSRRegister16__internal_fu_write["_internal_fu_write"] + CSRRegister16__internal_fu_read["_internal_fu_read"] CSRRegister16_read["read"] subgraph MethodMap32["fu_write_map MethodMap"] MethodMap32_method["method"] @@ -818,16 +827,16 @@ DoubleCounterCSR_increment["increment"] subgraph CSRRegister18["register_low CSRRegister"] CSRRegister18_read["read"] - CSRRegister18__internal_fu_read["_internal_fu_read"] CSRRegister18_write["write"] + CSRRegister18__internal_fu_read["_internal_fu_read"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] end end subgraph CSRRegister19["register_high CSRRegister"] - CSRRegister19__internal_fu_read["_internal_fu_read"] CSRRegister19_write["write"] CSRRegister19_read["read"] + CSRRegister19__internal_fu_read["_internal_fu_read"] subgraph MethodMap39["fu_read_map MethodMap"] MethodMap39_method["method"] end @@ -844,9 +853,9 @@ end end subgraph CSRRegister21["register_high CSRRegister"] + CSRRegister21_write["write"] CSRRegister21__internal_fu_read["_internal_fu_read"] CSRRegister21_read["read"] - CSRRegister21_write["write"] subgraph MethodMap43["fu_read_map MethodMap"] MethodMap43_method["method"] end @@ -854,16 +863,16 @@ end end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] - InternalInterruptController_mret["mret"] InternalInterruptController_InternalInterruptController["InternalInterruptController"] InternalInterruptController_InternalInterruptController1["InternalInterruptController"] InternalInterruptController_entry["entry"] InternalInterruptController_interrupt_cause["interrupt_cause"] InternalInterruptController_InternalInterruptController2["InternalInterruptController"] + InternalInterruptController_mret["mret"] subgraph CSRRegister22["mie CSRRegister"] - CSRRegister22_read["read"] - CSRRegister22__internal_fu_write["_internal_fu_write"] CSRRegister22__internal_fu_read["_internal_fu_read"] + CSRRegister22__internal_fu_write["_internal_fu_write"] + CSRRegister22_read["read"] subgraph MethodMap44["fu_write_map MethodMap"] MethodMap44_method["method"] end @@ -875,11 +884,11 @@ end end subgraph CSRRegister23["mip CSRRegister"] - CSRRegister23_read_comb["read_comb"] CSRRegister23__internal_fu_write["_internal_fu_write"] - CSRRegister23_write["write"] CSRRegister23__internal_fu_read["_internal_fu_read"] CSRRegister23_read["read"] + CSRRegister23_read_comb["read_comb"] + CSRRegister23_write["write"] subgraph MethodMap46["fu_write_map MethodMap"] MethodMap46_method["method"] end @@ -892,8 +901,8 @@ end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_decrement["decrement"] CoreInstructionCounter_increment["increment"] + CoreInstructionCounter_decrement["decrement"] end subgraph MethodProduct1["get_instr MethodProduct"] MethodProduct1_method["method"] @@ -907,8 +916,8 @@ RegAllocation_RegAllocation["RegAllocation"] end subgraph Connect["rename_out_buf Connect"] - Connect_read["read"] Connect_write["write"] + Connect_read["read"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] @@ -921,8 +930,8 @@ ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO14["rs_select_out_buf FIFO"] - FIFO14_read["read"] FIFO14_write["write"] + FIFO14_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -956,27 +965,27 @@ end subgraph Retirement["retirement Retirement"] Retirement_Retirement["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement1["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_core_state["core_state"] - Retirement_Retirement2["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_precommit["precommit"] + Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister24["register_low CSRRegister"] + CSRRegister24_read["read"] CSRRegister24_write["write"] CSRRegister24__internal_fu_read["_internal_fu_read"] - CSRRegister24_read["read"] subgraph MethodMap49["fu_read_map MethodMap"] MethodMap49_method["method"] end end subgraph CSRRegister25["register_high CSRRegister"] + CSRRegister25__internal_fu_read["_internal_fu_read"] CSRRegister25_read["read"] CSRRegister25_write["write"] - CSRRegister25__internal_fu_read["_internal_fu_read"] subgraph MethodMap51["fu_read_map MethodMap"] MethodMap51_method["method"] end @@ -992,49 +1001,49 @@ HwExpHistogram11__add["_add"] end subgraph FIFO15["fifo FIFO"] - FIFO15_write["write"] FIFO15_read["read"] + FIFO15_write["write"] end end end end end subgraph TransactionManager["transaction_manager TransactionManager"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] - TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] - TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"] + TransactionManager_accept_cond0_ConnectTrans_accept_cond1["accept_cond0_ConnectTrans_accept_cond1"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0["Fetch_Stage2_Fetch_Stage2_cond0"] - TransactionManager_accept_cond0_accept_cond1_ConnectTrans["accept_cond0_accept_cond1_ConnectTrans"] + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1["Fetch_Stage2_Fetch_Stage2_cond1"] + TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_PrivilegedFuncUnit_cond0"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] + TransactionManager_ConnectTrans_accept_cond1["ConnectTrans_accept_cond1"] TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1["Fetch_Stage2_Fetch_Stage2_cond1"] - TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit["PrivilegedFuncUnit_cond1_PrivilegedFuncUnit"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] end end Core_InitFreeRFFifo --> BasicFifo5_write - Retirement_Retirement --> BasicFifo5_write + Retirement_Retirement1 --> BasicFifo5_write TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write - TransactionManager_Retirement_cond0_Retirement --> BasicFifo5_write + TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Serializer_serialize_in0 - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> BasicFifo_write - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMaster_request - WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - Serializer_serialize_out0 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Forwarder2_write - ICache_ICache1 <--> HwCounter4__incr + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_serialize_in0 + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request + WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + Serializer_serialize_out0 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write + ICache_ICache <--> HwCounter4__incr ArgumentsToResultsZipper_peek_arg --> ICache_MemRead BasicFifo3_peek --> ICache_MemRead ICache_MemRead <--> HwCounter1__incr @@ -1042,9 +1051,9 @@ ICache_MemRead --> Forwarder3_write ICache_MemRead <--> HwCounter2__incr ICache_MemRead --> SimpleCommonBusCacheRefiller_start_refill - SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache - Forwarder2_read --> ICache_ICache - ICache_ICache <--> HwCounter3__incr + SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 + Forwarder2_read --> ICache_ICache1 + ICache_ICache1 <--> HwCounter3__incr FetchUnit_Fetch_Stage0 <--> Semaphore_acquire FetchUnit_Fetch_Stage0 --> ICache_issue_req FetchUnit_Fetch_Stage0 <--> HwCounter__incr @@ -1079,20 +1088,20 @@ GenericCSRRegisters_GenericCSRRegisters --> CSRRegister20_write CSRRegister21_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister21_write - CSRRegister11_read --> InternalInterruptController_InternalInterruptController2 + CSRRegister11_read --> InternalInterruptController_InternalInterruptController1 CSRRegister11_read --> InternalInterruptController_InternalInterruptController - CSRRegister10_read --> InternalInterruptController_InternalInterruptController2 + CSRRegister10_read --> InternalInterruptController_InternalInterruptController1 CSRRegister10_read --> InternalInterruptController_InternalInterruptController CSRRegister10_read --> WakeupSelect3_WakeupSelect CSRRegister10_read --> CSRUnit_CSRUnit - CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - CSRRegister22_read --> InternalInterruptController_InternalInterruptController2 - CSRRegister23_read --> InternalInterruptController_InternalInterruptController2 - CSRRegister23_read_comb --> InternalInterruptController_InternalInterruptController1 - InternalInterruptController_InternalInterruptController1 --> CSRRegister23_write + CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + CSRRegister22_read --> InternalInterruptController_InternalInterruptController1 + CSRRegister23_read --> InternalInterruptController_InternalInterruptController1 + CSRRegister23_read_comb --> InternalInterruptController_InternalInterruptController2 + InternalInterruptController_InternalInterruptController2 --> CSRRegister23_write InternalInterruptController_InternalInterruptController --> CSRRegister11_write InternalInterruptController_InternalInterruptController --> CSRRegister12_write InternalInterruptController_InternalInterruptController --> CSRRegister13_write @@ -1106,25 +1115,43 @@ BasicFifo5_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO12_write FIFO13_read --> RSSelection_RSSelection2 + FIFO13_read --> RSSelection_RSSelection FIFO13_read --> RSSelection_RSSelection3 FIFO13_read --> RSSelection_RSSelection1 - FIFO13_read --> RSSelection_RSSelection RSFuncBlock_select --> RSSelection_RSSelection2 RS_select --> RSSelection_RSSelection2 RSSelection_RSSelection2 --> FIFO14_write + RSSelection_RSSelection --> FIFO14_write RSSelection_RSSelection3 --> FIFO14_write RSSelection_RSSelection1 --> FIFO14_write - RSSelection_RSSelection --> FIFO14_write - RSFuncBlock1_select --> RSSelection_RSSelection3 - RS1_select --> RSSelection_RSSelection3 - RSFuncBlock2_select --> RSSelection_RSSelection1 - FifoRS_select --> RSSelection_RSSelection1 - RSSelection_RSSelection <--> CSRUnit_select + RSSelection_RSSelection2 --> RegisterFile_read_req1 + RSSelection_RSSelection --> RegisterFile_read_req1 + RSSelection_RSSelection3 --> RegisterFile_read_req1 + RSSelection_RSSelection1 --> RegisterFile_read_req1 + RSSelection_RSSelection2 --> MemoryBank_read_req0 + RSSelection_RSSelection --> MemoryBank_read_req0 + RSSelection_RSSelection3 --> MemoryBank_read_req0 + RSSelection_RSSelection1 --> MemoryBank_read_req0 + RSSelection_RSSelection2 --> RegisterFile_read_req2 + RSSelection_RSSelection --> RegisterFile_read_req2 + RSSelection_RSSelection3 --> RegisterFile_read_req2 + RSSelection_RSSelection1 --> RegisterFile_read_req2 + RSSelection_RSSelection2 --> MemoryBank_read_req1 + RSSelection_RSSelection --> MemoryBank_read_req1 + RSSelection_RSSelection3 --> MemoryBank_read_req1 + RSSelection_RSSelection1 --> MemoryBank_read_req1 + RSFuncBlock1_select --> RSSelection_RSSelection + RS1_select --> RSSelection_RSSelection + RSFuncBlock2_select --> RSSelection_RSSelection3 + FifoRS_select --> RSSelection_RSSelection3 + RSSelection_RSSelection1 <--> CSRUnit_select FIFO14_read --> RSInsertion_RSInsertion - RegisterFile_read1 --> RSInsertion_RSInsertion - RegisterFile_read2 --> RSInsertion_RSInsertion + RegisterFile_read_resp1 --> RSInsertion_RSInsertion + MemoryBank_read_resp0 --> RSInsertion_RSInsertion + RegisterFile_read_resp2 --> RSInsertion_RSInsertion + MemoryBank_read_resp1 --> RSInsertion_RSInsertion Retirement_core_state --> RSInsertion_RSInsertion - Retirement_core_state --> LSUDummy_LSUDummy2 + Retirement_core_state --> LSUDummy_LSUDummy RSInsertion_RSInsertion --> RSFuncBlock_insert RSInsertion_RSInsertion --> RS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer1__start @@ -1157,6 +1184,7 @@ Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done ResultAnnouncement_ResultAnnouncement --> RegisterFile_write + ResultAnnouncement_ResultAnnouncement --> MemoryBank_write0 ResultAnnouncement_ResultAnnouncement --> TaggedLatencyMeasurer__start ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_write0 ResultAnnouncement_ResultAnnouncement --> MethodProduct_method @@ -1168,7 +1196,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add - RS_RS4 --> WakeupSelect_WakeupSelect + RS_RS1 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -1192,25 +1220,25 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter4__incr WakeupSelect_WakeupSelect --> FIFO2_write - RS_RS1 --> WakeupSelect1_WakeupSelect + RS_RS2 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write - RS_RS --> WakeupSelect2_WakeupSelect + RS_RS3 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write WakeupSelect2_WakeupSelect --> TaggedCounter5__incr - RS_RS3 --> WakeupSelect3_WakeupSelect + RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> BasicFifo6_write ConnectTrans8_ConnectTrans --> BasicFifo6_write ConnectTrans10_ConnectTrans --> BasicFifo6_write ConnectTrans5_ConnectTrans --> BasicFifo6_write + TransactionManager_ConnectTrans_accept_cond1 --> BasicFifo6_write TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo6_write - TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> BasicFifo6_write - TransactionManager_accept_cond1_ConnectTrans --> BasicFifo6_write + TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write - RS_RS2 --> WakeupSelect4_WakeupSelect + RS_RS4 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans6_ConnectTrans --> Forwarder5_write ConnectTrans7_ConnectTrans --> Forwarder5_write @@ -1264,35 +1292,35 @@ BasicFifo9_read --> ConnectTrans12_ConnectTrans FifoRS_perf --> HwExpHistogram10__add Forwarder7_read --> LSUDummy_LSUDummy1 - Forwarder7_read --> TransactionManager_LSUDummy_issue_cond0 Forwarder7_read --> TransactionManager_LSUDummy_issue_cond1 - Forwarder7_read --> TransactionManager_LSUDummy_issue_cond2 + Forwarder7_read --> TransactionManager_issue_cond2_LSUDummy + Forwarder7_read --> TransactionManager_issue_cond0_LSUDummy LSUDummy_LSUDummy1 --> FIFO9_write WakeupSelect7_WakeupSelect --> FIFO9_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO9_write TransactionManager_LSUDummy_issue_cond1 --> FIFO9_write - TransactionManager_LSUDummy_issue_cond2 --> FIFO9_write + TransactionManager_issue_cond2_LSUDummy --> FIFO9_write + TransactionManager_issue_cond0_LSUDummy --> FIFO9_write LSUDummy_LSUDummy1 --> FIFO11_write WakeupSelect7_WakeupSelect --> FIFO11_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO11_write TransactionManager_LSUDummy_issue_cond1 --> FIFO11_write - TransactionManager_LSUDummy_issue_cond2 --> FIFO11_write + TransactionManager_issue_cond2_LSUDummy --> FIFO11_write + TransactionManager_issue_cond0_LSUDummy --> FIFO11_write LSUDummy_LSUDummy3 --> Retirement_precommit CSRUnit_CSRUnit --> Retirement_precommit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> Retirement_precommit - TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> Retirement_precommit TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> Retirement_precommit TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> Retirement_precommit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> Retirement_precommit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> Retirement_precommit ReorderBuffer_peek --> LSUDummy_LSUDummy3 ReorderBuffer_peek --> CSRUnit_CSRUnit - ReorderBuffer_peek --> Retirement_Retirement3 ReorderBuffer_peek --> Retirement_Retirement + ReorderBuffer_peek --> Retirement_Retirement1 ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit - ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 FifoRS_FifoRS --> WakeupSelect7_WakeupSelect FifoRS_take --> WakeupSelect7_WakeupSelect WakeupSelect7_WakeupSelect --> TaggedLatencyMeasurer3__stop @@ -1412,41 +1440,41 @@ Collector3_method --> ConnectTrans4_ConnectTrans Forwarder8_read --> ConnectTrans4_ConnectTrans CSRUnit_get_result --> ConnectTrans5_ConnectTrans - ExceptionInformationRegister_get --> Retirement_Retirement3 + ExceptionInformationRegister_get --> Retirement_Retirement ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond1 - ExceptionInformationRegister_get --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement <--> ReorderBuffer_retire + ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement1 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire - TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire - Retirement_Retirement <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire + Retirement_Retirement1 <--> FIFOLatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop - TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer1__stop - FIFO1_read --> Retirement_Retirement + TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop + FIFO1_read --> Retirement_Retirement1 FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 - FIFO1_read --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement --> HwExpHistogram3__add + FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement1 --> HwExpHistogram3__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram3__add - CoreInstructionCounter_decrement --> Retirement_Retirement + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add + CoreInstructionCounter_decrement --> Retirement_Retirement1 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement - RRAT_peek --> Retirement_Retirement + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 + RRAT_peek --> Retirement_Retirement1 RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement --> RegisterFile_free + Retirement_Retirement1 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free - TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free - Retirement_Retirement --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free + Retirement_Retirement1 --> TaggedLatencyMeasurer__stop TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop - TransactionManager_Retirement_cond0_Retirement --> TaggedLatencyMeasurer__stop - AsyncMemoryBank_read0 --> Retirement_Retirement + TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop + AsyncMemoryBank_read0 --> Retirement_Retirement1 AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond1 - AsyncMemoryBank_read0 --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement --> HwExpHistogram1__add + AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement1 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add - Retirement_Retirement --> FRAT_rename + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add + Retirement_Retirement1 --> FRAT_rename TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename - TransactionManager_ROBAllocation_Renaming --> FRAT_rename + TransactionManager_Renaming_ROBAllocation --> FRAT_rename Retirement_Retirement2 <--> FIFOLatencyMeasurer2__stop FIFO15_read --> Retirement_Retirement2 Retirement_Retirement2 --> HwExpHistogram11__add @@ -1455,77 +1483,59 @@ CSRRegister6_read --> Retirement_Retirement2 Retirement_Retirement2 --> FetchUnit_resume_from_exception Retirement_Retirement2 <--> ExceptionInformationRegister_clear - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 - TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - BasicFifo10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - BasicFifo10_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - FIFO10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - FIFO10_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans + TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans13_ConnectTrans TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans13_ConnectTrans - TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> ConnectTrans13_ConnectTrans - TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans13_ConnectTrans + TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> ConnectTrans13_ConnectTrans + TransactionManager_ConnectTrans_accept_cond1 --> Forwarder8_write TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder8_write - TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> Forwarder8_write - TransactionManager_accept_cond1_ConnectTrans --> Forwarder8_write + TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> Forwarder8_write + LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - Serializer1_serialize_out1 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - Forwarder1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy - TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy - TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy - TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond0 --> BasicFifo10_write - TransactionManager_LSUDummy_issue_cond1 --> BasicFifo10_write - TransactionManager_LSUDummy_issue_cond2 --> BasicFifo10_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO10_write - TransactionManager_LSUDummy_issue_cond1 --> FIFO10_write - TransactionManager_LSUDummy_issue_cond2 --> FIFO10_write - TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 - TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_serialize_in1 - TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request - TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1 - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement1 + LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1 + FIFO9_read --> TransactionManager_ConnectTrans_accept_cond1 + FIFO11_read --> TransactionManager_ConnectTrans_accept_cond1 + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement3 + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement3 TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start - TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer2__start + TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start TransactionManager_Retirement_Retirement_cond1 --> FIFO15_write - TransactionManager_Retirement_cond0_Retirement --> FIFO15_write + TransactionManager_Retirement_Retirement_cond0 --> FIFO15_write InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 - InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond0_Retirement + InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister6_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister7_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry - TransactionManager_Retirement_cond0_Retirement <--> InternalInterruptController_entry + TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 - TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - Serializer1_serialize_out0 --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans - TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 - FIFO9_read --> TransactionManager_accept_cond1_ConnectTrans - FIFO11_read --> TransactionManager_accept_cond1_ConnectTrans - TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 - TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read - TransactionManager_LSUDummy_issue_cond1 --> Serializer1_serialize_in0 + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit + TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment + CSRRegister24_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister24_write + CSRRegister25_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister25_write + TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr + CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2 TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> Semaphore_release @@ -1543,43 +1553,61 @@ TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter3__incr TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2_cond1 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr - CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit - CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret - TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 - TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation - Connect_read --> TransactionManager_ROBAllocation_Renaming - TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put - TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start - TransactionManager_ROBAllocation_Renaming --> FIFO1_write - TransactionManager_ROBAllocation_Renaming --> FIFO13_write - TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming - FIFO12_read --> TransactionManager_ROBAllocation_Renaming - TransactionManager_ROBAllocation_Renaming --> Connect_write - TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> ICache_flush - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_cond0_Retirement --> RRAT_commit - TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment - CSRRegister24_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister24_write - CSRRegister25_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister25_write - TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 + TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond0 + LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + BasicFifo10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + BasicFifo10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + FIFO10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + FIFO10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + Serializer1_serialize_out1 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy2 + TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy2 + TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy2 + TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue + TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond1 --> BasicFifo10_write + TransactionManager_issue_cond2_LSUDummy --> BasicFifo10_write + TransactionManager_issue_cond0_LSUDummy --> BasicFifo10_write + TransactionManager_LSUDummy_issue_cond1 --> FIFO10_write + TransactionManager_issue_cond2_LSUDummy --> FIFO10_write + TransactionManager_issue_cond0_LSUDummy --> FIFO10_write + TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 + TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read + TransactionManager_LSUDummy_issue_cond1 --> Serializer1_serialize_in0 + TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write + TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write + TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request + TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request + TransactionManager_Renaming_ROBAllocation <--> Renaming_Renaming + FIFO12_read --> TransactionManager_Renaming_ROBAllocation + TransactionManager_Renaming_ROBAllocation --> Connect_write + TransactionManager_Renaming_ROBAllocation <--> ROBAllocation_ROBAllocation + Connect_read --> TransactionManager_Renaming_ROBAllocation + TransactionManager_Renaming_ROBAllocation --> ReorderBuffer_put + TransactionManager_Renaming_ROBAllocation <--> FIFOLatencyMeasurer1__start + TransactionManager_Renaming_ROBAllocation --> FIFO1_write + TransactionManager_Renaming_ROBAllocation --> FIFO13_write TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret + TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 + TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write + TransactionManager_issue_cond0_LSUDummy --> Serializer1_serialize_in1 + TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + Serializer1_serialize_out0 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 diff --git a/api.html b/api.html index f385f3858..4791e94c6 100644 --- a/api.html +++ b/api.html @@ -192,7 +192,7 @@

coreblocks

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/assumptions.html b/assumptions.html index 161b93ba7..c631672c7 100644 --- a/assumptions.html +++ b/assumptions.html @@ -103,7 +103,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/auto_graph.html b/auto_graph.html index 689a2fbf3..6f3f944cc 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -84,9 +84,9 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] + WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_request["request"] WishboneMaster_result["result"] - WishboneMaster_WishboneMaster["WishboneMaster"] subgraph Forwarder["result Forwarder"] Forwarder_read["read"] Forwarder_write["write"] @@ -102,37 +102,37 @@ end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_serialize_in0["serialize_in0"] Serializer_serialize_out0["serialize_out0"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] + WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_read["request_read"] WishboneMasterAdapter1_get_write_response["get_write_response"] - WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] - Serializer1_serialize_out0["serialize_out0"] Serializer1_serialize_out1["serialize_out1"] + Serializer1_serialize_out0["serialize_out0"] Serializer1_serialize_in0["serialize_in0"] Serializer1_serialize_in1["serialize_in1"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_write["write"] BasicFifo1_read["read"] + BasicFifo1_write["write"] end end end subgraph CoreFrontend["frontend CoreFrontend"] + CoreFrontend_stall["stall"] CoreFrontend_target_pred_resp["target_pred_resp"] CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] - CoreFrontend_stall["stall"] CoreFrontend_target_pred_req["target_pred_req"] subgraph BasicFifo2["instr_buffer BasicFifo"] BasicFifo2_write["write"] @@ -140,22 +140,22 @@ BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_read["read"] Forwarder2_write["write"] + Forwarder2_read["read"] end end subgraph ICache["icache ICache"] - ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] ICache_ICache["ICache"] ICache_flush["flush"] ICache_ICache1["ICache"] + ICache_accept_res["accept_res"] ICache_MemRead["MemRead"] + ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -183,30 +183,30 @@ end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_peek_arg["peek_arg"] ArgumentsToResultsZipper_write_args["write_args"] + ArgumentsToResultsZipper_peek_arg["peek_arg"] ArgumentsToResultsZipper_write_results["write_results"] ArgumentsToResultsZipper_read["read"] subgraph BasicFifo3["fifo BasicFifo"] BasicFifo3_peek["peek"] - BasicFifo3_write["write"] BasicFifo3_read["read"] + BasicFifo3_write["write"] end subgraph Forwarder3["forwarder Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end end subgraph FetchUnit["fetch FetchUnit"] - FetchUnit_stall_exception["stall_exception"] FetchUnit_Fetch_Stage1["Fetch_Stage1"] - FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] - FetchUnit_resume_from_unsafe["resume_from_unsafe"] - FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] FetchUnit_resume_from_exception["resume_from_exception"] + FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] + FetchUnit_resume_from_unsafe["resume_from_unsafe"] FetchUnit_Fetch_Stage2["Fetch_Stage2"] + FetchUnit_stall_exception["stall_exception"] FetchUnit_Fetch_Stage0["Fetch_Stage0"] + FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] end @@ -226,12 +226,12 @@ BasicFifo4_read["read"] end subgraph Semaphore["req_counter Semaphore"] - Semaphore_acquire["acquire"] Semaphore_release["release"] + Semaphore_acquire["acquire"] end subgraph Pipe["s1_s2_pipe Pipe"] - Pipe_read["read"] Pipe_write["write"] + Pipe_read["read"] end subgraph Predecoder["predecoder_0 Predecoder"] Predecoder_predecode["predecode"] @@ -250,9 +250,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] - Pipe1_read["read"] Pipe1_clean["clean"] Pipe1_write["write"] + Pipe1_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -273,20 +273,29 @@ RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_write["write"] - RegisterFile_read2["read2"] - RegisterFile_free["free"] RegisterFile_perf["perf"] - RegisterFile_read1["read1"] + RegisterFile_read_req1["read_req1"] + RegisterFile_free["free"] + RegisterFile_read_resp2["read_resp2"] + RegisterFile_write["write"] + RegisterFile_read_req2["read_req2"] + RegisterFile_read_resp1["read_resp1"] + subgraph MemoryBank["entries MemoryBank"] + MemoryBank_write0["write0"] + MemoryBank_read_req0["read_req0"] + MemoryBank_read_req1["read_req1"] + MemoryBank_read_resp0["read_resp0"] + MemoryBank_read_resp1["read_resp1"] + end subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer__start["_start"] TaggedLatencyMeasurer__stop["_stop"] + TaggedLatencyMeasurer__start["_start"] subgraph HwExpHistogram1["histogram HwExpHistogram"] HwExpHistogram1__add["_add"] end subgraph AsyncMemoryBank["slots AsyncMemoryBank"] - AsyncMemoryBank_read0["read0"] AsyncMemoryBank_write0["write0"] + AsyncMemoryBank_read0["read0"] end end subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] @@ -294,11 +303,11 @@ end end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_perf["perf"] - ReorderBuffer_retire["retire"] - ReorderBuffer_put["put"] ReorderBuffer_peek["peek"] ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_retire["retire"] + ReorderBuffer_put["put"] + ReorderBuffer_perf["perf"] ReorderBuffer_mark_done["mark_done"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] FIFOLatencyMeasurer1__stop["_stop"] @@ -307,8 +316,8 @@ HwExpHistogram3__add["_add"] end subgraph FIFO1["fifo FIFO"] - FIFO1_read["read"] FIFO1_write["write"] + FIFO1_read["read"] end end subgraph HwExpHistogram4["perf_rob_size HwExpHistogram"] @@ -316,12 +325,12 @@ end end subgraph ExceptionInformationRegister["exception_information_register ExceptionInformationRegister"] - ExceptionInformationRegister_report["report"] - ExceptionInformationRegister_clear["clear"] ExceptionInformationRegister_get["get"] + ExceptionInformationRegister_clear["clear"] + ExceptionInformationRegister_report["report"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] - BasicFifo6_read["read"] BasicFifo6_write["write"] + BasicFifo6_read["read"] end subgraph ConnectTrans1["report_connector ConnectTrans"] ConnectTrans1_ConnectTrans["ConnectTrans"] @@ -353,30 +362,30 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] + RSFuncBlock_select["select"] RSFuncBlock_get_result["get_result"] - RSFuncBlock_update["update"] RSFuncBlock_insert["insert"] - RSFuncBlock_select["select"] + RSFuncBlock_update["update"] subgraph RS["rs RS"] - RS_perf["perf"] - RS_update["update"] + RS_insert["insert"] + RS_take["take"] RS_RS["RS"] + RS_perf["perf"] RS_RS1["RS"] - RS_RS2["RS"] RS_select["select"] - RS_insert["insert"] - RS_take["take"] + RS_RS2["RS"] RS_RS3["RS"] + RS_update["update"] RS_RS4["RS"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__start["_start"] TaggedLatencyMeasurer1__stop["_stop"] + TaggedLatencyMeasurer1__start["_start"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_read0["read0"] AsyncMemoryBank1_write0["write0"] + AsyncMemoryBank1_read0["read0"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -390,8 +399,8 @@ TaggedCounter4__incr["_incr"] end subgraph FIFO2["fifo FIFO"] - FIFO2_write["write"] FIFO2_read["read"] + FIFO2_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] @@ -409,8 +418,8 @@ WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO4["fifo_branch_resolved FIFO"] FIFO4_write["write"] FIFO4_read["read"] @@ -425,16 +434,16 @@ HwCounter8__incr["_incr"] end subgraph BasicFifo7["instr_fifo BasicFifo"] - BasicFifo7_read["read"] BasicFifo7_write["write"] + BasicFifo7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] + ExceptionFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] FIFO5_read["read"] FIFO5_write["write"] @@ -444,16 +453,16 @@ WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] + PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] - PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] - PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] - PrivilegedFuncUnit_issue["issue"] + PrivilegedFuncUnit_accept["accept"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] - BasicFifo8_read["read"] BasicFifo8_write["write"] + BasicFifo8_read["read"] end subgraph TaggedCounter6["perf_instr TaggedCounter"] TaggedCounter6__incr["_incr"] @@ -488,21 +497,21 @@ end end subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] - RSFuncBlock1_update["update"] RSFuncBlock1_get_result["get_result"] - RSFuncBlock1_select["select"] RSFuncBlock1_insert["insert"] + RSFuncBlock1_select["select"] + RSFuncBlock1_update["update"] subgraph RS1["rs RS"] - RS1_update["update"] - RS1_RS["RS"] - RS1_take["take"] - RS1_RS1["RS"] - RS1_perf["perf"] RS1_insert["insert"] + RS1_RS["RS"] + RS1_update["update"] RS1_select["select"] + RS1_perf["perf"] + RS1_RS1["RS"] + RS1_take["take"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer2__start["_start"] TaggedLatencyMeasurer2__stop["_stop"] + TaggedLatencyMeasurer2__start["_start"] subgraph HwExpHistogram7["histogram HwExpHistogram"] HwExpHistogram7__add["_add"] end @@ -516,20 +525,20 @@ end end subgraph MulUnit["func_unit_0 MulUnit"] + MulUnit_issue["issue"] MulUnit_MulUnit["MulUnit"] MulUnit_accept["accept"] - MulUnit_issue["issue"] subgraph FIFO6["result_fifo FIFO"] FIFO6_read["read"] FIFO6_write["write"] end subgraph FIFO7["params_fifo FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end subgraph SequentialUnsignedMul["multiplier SequentialUnsignedMul"] - SequentialUnsignedMul_accept["accept"] SequentialUnsignedMul_issue["issue"] + SequentialUnsignedMul_accept["accept"] subgraph DSPMulUnit["dsp DSPMulUnit"] DSPMulUnit_compute["compute"] end @@ -543,19 +552,19 @@ end subgraph DivUnit["func_unit_1 DivUnit"] DivUnit_DivUnit["DivUnit"] - DivUnit_accept["accept"] DivUnit_issue["issue"] + DivUnit_accept["accept"] subgraph BasicFifo9["result_fifo BasicFifo"] - BasicFifo9_read["read"] BasicFifo9_write["write"] + BasicFifo9_read["read"] end subgraph FIFO8["params_fifo FIFO"] - FIFO8_write["write"] FIFO8_read["read"] + FIFO8_write["write"] end subgraph LongDivider["divider LongDivider"] - LongDivider_issue["issue"] LongDivider_accept["accept"] + LongDivider_issue["issue"] end end subgraph WakeupSelect6["wakeup_select_1 WakeupSelect"] @@ -579,16 +588,16 @@ end subgraph RSFuncBlock2["rs_block_2 RSFuncBlock"] RSFuncBlock2_get_result["get_result"] - RSFuncBlock2_insert["insert"] RSFuncBlock2_select["select"] + RSFuncBlock2_insert["insert"] RSFuncBlock2_update["update"] subgraph FifoRS["rs FifoRS"] + FifoRS_select["select"] FifoRS_perf["perf"] FifoRS_take["take"] + FifoRS_FifoRS["FifoRS"] FifoRS_insert["insert"] - FifoRS_select["select"] FifoRS_update["update"] - FifoRS_FifoRS["FifoRS"] subgraph TaggedLatencyMeasurer3["perf_rs_wait_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer3__start["_start"] TaggedLatencyMeasurer3__stop["_stop"] @@ -596,8 +605,8 @@ HwExpHistogram9__add["_add"] end subgraph AsyncMemoryBank3["slots AsyncMemoryBank"] - AsyncMemoryBank3_write0["write0"] AsyncMemoryBank3_read0["read0"] + AsyncMemoryBank3_write0["write0"] end end subgraph HwExpHistogram10["perf_num_full HwExpHistogram"] @@ -605,22 +614,22 @@ end end subgraph LSUDummy["func_unit_0 LSUDummy"] - LSUDummy_LSUDummy["LSUDummy"] LSUDummy_issue["issue"] + LSUDummy_LSUDummy["LSUDummy"] LSUDummy_accept["accept"] LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_accept_cond1["accept_cond1"] + LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_accept_cond0["accept_cond0"] LSUDummy_LSUDummy3["LSUDummy"] subgraph LSURequester["requester LSURequester"] + LSURequester_accept["accept"] + LSURequester_accept_cond0["accept_cond0"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond2["issue_cond2"] LSURequester_issue["issue"] - LSURequester_accept_cond0["accept_cond0"] - LSURequester_accept_cond1["accept_cond1"] LSURequester_issue_cond0["issue_cond0"] - LSURequester_accept["accept"] - LSURequester_issue_cond2["issue_cond2"] + LSURequester_accept_cond1["accept_cond1"] subgraph BasicFifo10["args_fifo BasicFifo"] BasicFifo10_read["read"] BasicFifo10_write["write"] @@ -635,12 +644,12 @@ FIFO9_write["write"] end subgraph FIFO10["issued FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph FIFO11["issued_noop FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end end subgraph WakeupSelect7["wakeup_select_0 WakeupSelect"] @@ -660,12 +669,12 @@ end end subgraph CSRUnit["rs_block_3 CSRUnit"] - CSRUnit_insert["insert"] CSRUnit_get_result["get_result"] - CSRUnit_CSRUnit["CSRUnit"] CSRUnit_update["update"] - CSRUnit_select["select"] + CSRUnit_insert["insert"] CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_select["select"] + CSRUnit_CSRUnit["CSRUnit"] end end subgraph ResultAnnouncement["announcement ResultAnnouncement"] @@ -699,8 +708,8 @@ end end subgraph CSRRegister4["mscratch CSRRegister"] - CSRRegister4__internal_fu_read["_internal_fu_read"] CSRRegister4__internal_fu_write["_internal_fu_write"] + CSRRegister4__internal_fu_read["_internal_fu_read"] subgraph MethodMap8["fu_write_map MethodMap"] MethodMap8_method["method"] end @@ -727,9 +736,9 @@ end subgraph CSRRegister6["mcause CSRRegister"] CSRRegister6_read["read"] - CSRRegister6__internal_fu_write["_internal_fu_write"] - CSRRegister6_write["write"] CSRRegister6__internal_fu_read["_internal_fu_read"] + CSRRegister6_write["write"] + CSRRegister6__internal_fu_write["_internal_fu_write"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -745,10 +754,10 @@ AliasedCSR2__fu_read["_fu_read"] end subgraph CSRRegister7["mepc CSRRegister"] - CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7__internal_fu_read["_internal_fu_read"] - CSRRegister7_read["read"] CSRRegister7_write["write"] + CSRRegister7__internal_fu_write["_internal_fu_write"] + CSRRegister7_read["read"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] end @@ -791,10 +800,10 @@ CSRRegister10_write["write"] end subgraph CSRRegister11["mstatus_mie CSRRegister"] - CSRRegister11__internal_fu_write["_internal_fu_write"] - CSRRegister11__internal_fu_read["_internal_fu_read"] CSRRegister11_write["write"] + CSRRegister11__internal_fu_write["_internal_fu_write"] CSRRegister11_read["read"] + CSRRegister11__internal_fu_read["_internal_fu_read"] subgraph MethodMap22["fu_write_map MethodMap"] MethodMap22_method["method"] end @@ -806,8 +815,8 @@ end end subgraph CSRRegister12["mstatus_mpie CSRRegister"] - CSRRegister12_read["read"] CSRRegister12__internal_fu_write["_internal_fu_write"] + CSRRegister12_read["read"] CSRRegister12_write["write"] CSRRegister12__internal_fu_read["_internal_fu_read"] subgraph MethodMap24["fu_write_map MethodMap"] @@ -821,10 +830,10 @@ end end subgraph CSRRegister13["mstatus_mpp CSRRegister"] - CSRRegister13__internal_fu_read["_internal_fu_read"] CSRRegister13_write["write"] - CSRRegister13_read["read"] CSRRegister13__internal_fu_write["_internal_fu_write"] + CSRRegister13_read["read"] + CSRRegister13__internal_fu_read["_internal_fu_read"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -836,9 +845,9 @@ end end subgraph CSRRegister14["mstatus_mprv CSRRegister"] + CSRRegister14__internal_fu_write["_internal_fu_write"] CSRRegister14_write["write"] CSRRegister14__internal_fu_read["_internal_fu_read"] - CSRRegister14__internal_fu_write["_internal_fu_write"] subgraph MethodMap28["fu_write_map MethodMap"] MethodMap28_method["method"] end @@ -850,9 +859,9 @@ end end subgraph CSRRegister15["mstatus_tw CSRRegister"] - CSRRegister15__internal_fu_read["_internal_fu_read"] CSRRegister15__internal_fu_write["_internal_fu_write"] CSRRegister15_read["read"] + CSRRegister15__internal_fu_read["_internal_fu_read"] subgraph MethodMap30["fu_write_map MethodMap"] MethodMap30_method["method"] end @@ -864,8 +873,8 @@ end end subgraph CSRRegister16["mtvec_base CSRRegister"] - CSRRegister16__internal_fu_read["_internal_fu_read"] CSRRegister16__internal_fu_write["_internal_fu_write"] + CSRRegister16__internal_fu_read["_internal_fu_read"] CSRRegister16_read["read"] subgraph MethodMap32["fu_write_map MethodMap"] MethodMap32_method["method"] @@ -896,16 +905,16 @@ DoubleCounterCSR_increment["increment"] subgraph CSRRegister18["register_low CSRRegister"] CSRRegister18_read["read"] - CSRRegister18__internal_fu_read["_internal_fu_read"] CSRRegister18_write["write"] + CSRRegister18__internal_fu_read["_internal_fu_read"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] end end subgraph CSRRegister19["register_high CSRRegister"] - CSRRegister19__internal_fu_read["_internal_fu_read"] CSRRegister19_write["write"] CSRRegister19_read["read"] + CSRRegister19__internal_fu_read["_internal_fu_read"] subgraph MethodMap39["fu_read_map MethodMap"] MethodMap39_method["method"] end @@ -922,9 +931,9 @@ end end subgraph CSRRegister21["register_high CSRRegister"] + CSRRegister21_write["write"] CSRRegister21__internal_fu_read["_internal_fu_read"] CSRRegister21_read["read"] - CSRRegister21_write["write"] subgraph MethodMap43["fu_read_map MethodMap"] MethodMap43_method["method"] end @@ -932,16 +941,16 @@ end end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] - InternalInterruptController_mret["mret"] InternalInterruptController_InternalInterruptController["InternalInterruptController"] InternalInterruptController_InternalInterruptController1["InternalInterruptController"] InternalInterruptController_entry["entry"] InternalInterruptController_interrupt_cause["interrupt_cause"] InternalInterruptController_InternalInterruptController2["InternalInterruptController"] + InternalInterruptController_mret["mret"] subgraph CSRRegister22["mie CSRRegister"] - CSRRegister22_read["read"] - CSRRegister22__internal_fu_write["_internal_fu_write"] CSRRegister22__internal_fu_read["_internal_fu_read"] + CSRRegister22__internal_fu_write["_internal_fu_write"] + CSRRegister22_read["read"] subgraph MethodMap44["fu_write_map MethodMap"] MethodMap44_method["method"] end @@ -953,11 +962,11 @@ end end subgraph CSRRegister23["mip CSRRegister"] - CSRRegister23_read_comb["read_comb"] CSRRegister23__internal_fu_write["_internal_fu_write"] - CSRRegister23_write["write"] CSRRegister23__internal_fu_read["_internal_fu_read"] CSRRegister23_read["read"] + CSRRegister23_read_comb["read_comb"] + CSRRegister23_write["write"] subgraph MethodMap46["fu_write_map MethodMap"] MethodMap46_method["method"] end @@ -970,8 +979,8 @@ end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_decrement["decrement"] CoreInstructionCounter_increment["increment"] + CoreInstructionCounter_decrement["decrement"] end subgraph MethodProduct1["get_instr MethodProduct"] MethodProduct1_method["method"] @@ -985,8 +994,8 @@ RegAllocation_RegAllocation["RegAllocation"] end subgraph Connect["rename_out_buf Connect"] - Connect_read["read"] Connect_write["write"] + Connect_read["read"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] @@ -999,8 +1008,8 @@ ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO14["rs_select_out_buf FIFO"] - FIFO14_read["read"] FIFO14_write["write"] + FIFO14_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -1034,27 +1043,27 @@ end subgraph Retirement["retirement Retirement"] Retirement_Retirement["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement1["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_core_state["core_state"] - Retirement_Retirement2["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_precommit["precommit"] + Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister24["register_low CSRRegister"] + CSRRegister24_read["read"] CSRRegister24_write["write"] CSRRegister24__internal_fu_read["_internal_fu_read"] - CSRRegister24_read["read"] subgraph MethodMap49["fu_read_map MethodMap"] MethodMap49_method["method"] end end subgraph CSRRegister25["register_high CSRRegister"] + CSRRegister25__internal_fu_read["_internal_fu_read"] CSRRegister25_read["read"] CSRRegister25_write["write"] - CSRRegister25__internal_fu_read["_internal_fu_read"] subgraph MethodMap51["fu_read_map MethodMap"] MethodMap51_method["method"] end @@ -1070,49 +1079,49 @@ HwExpHistogram11__add["_add"] end subgraph FIFO15["fifo FIFO"] - FIFO15_write["write"] FIFO15_read["read"] + FIFO15_write["write"] end end end end end subgraph TransactionManager["transaction_manager TransactionManager"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] - TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] - TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"] + TransactionManager_accept_cond0_ConnectTrans_accept_cond1["accept_cond0_ConnectTrans_accept_cond1"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0["Fetch_Stage2_Fetch_Stage2_cond0"] - TransactionManager_accept_cond0_accept_cond1_ConnectTrans["accept_cond0_accept_cond1_ConnectTrans"] + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1["Fetch_Stage2_Fetch_Stage2_cond1"] + TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_PrivilegedFuncUnit_cond0"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] + TransactionManager_ConnectTrans_accept_cond1["ConnectTrans_accept_cond1"] TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1["Fetch_Stage2_Fetch_Stage2_cond1"] - TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit["PrivilegedFuncUnit_cond1_PrivilegedFuncUnit"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] end end Core_InitFreeRFFifo --> BasicFifo5_write -Retirement_Retirement --> BasicFifo5_write +Retirement_Retirement1 --> BasicFifo5_write TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write -TransactionManager_Retirement_cond0_Retirement --> BasicFifo5_write +TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMasterAdapter_request_read -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Serializer_serialize_in0 -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> BasicFifo_write -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMaster_request -WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -Serializer_serialize_out0 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Forwarder2_write -ICache_ICache1 <--> HwCounter4__incr +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_serialize_in0 +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request +WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +Serializer_serialize_out0 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write +ICache_ICache <--> HwCounter4__incr ArgumentsToResultsZipper_peek_arg --> ICache_MemRead BasicFifo3_peek --> ICache_MemRead ICache_MemRead <--> HwCounter1__incr @@ -1120,9 +1129,9 @@ ICache_MemRead --> Forwarder3_write ICache_MemRead <--> HwCounter2__incr ICache_MemRead --> SimpleCommonBusCacheRefiller_start_refill -SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache -Forwarder2_read --> ICache_ICache -ICache_ICache <--> HwCounter3__incr +SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 +Forwarder2_read --> ICache_ICache1 +ICache_ICache1 <--> HwCounter3__incr FetchUnit_Fetch_Stage0 <--> Semaphore_acquire FetchUnit_Fetch_Stage0 --> ICache_issue_req FetchUnit_Fetch_Stage0 <--> HwCounter__incr @@ -1157,20 +1166,20 @@ GenericCSRRegisters_GenericCSRRegisters --> CSRRegister20_write CSRRegister21_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister21_write -CSRRegister11_read --> InternalInterruptController_InternalInterruptController2 +CSRRegister11_read --> InternalInterruptController_InternalInterruptController1 CSRRegister11_read --> InternalInterruptController_InternalInterruptController -CSRRegister10_read --> InternalInterruptController_InternalInterruptController2 +CSRRegister10_read --> InternalInterruptController_InternalInterruptController1 CSRRegister10_read --> InternalInterruptController_InternalInterruptController CSRRegister10_read --> WakeupSelect3_WakeupSelect CSRRegister10_read --> CSRUnit_CSRUnit -CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -CSRRegister22_read --> InternalInterruptController_InternalInterruptController2 -CSRRegister23_read --> InternalInterruptController_InternalInterruptController2 -CSRRegister23_read_comb --> InternalInterruptController_InternalInterruptController1 -InternalInterruptController_InternalInterruptController1 --> CSRRegister23_write +CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 +CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +CSRRegister22_read --> InternalInterruptController_InternalInterruptController1 +CSRRegister23_read --> InternalInterruptController_InternalInterruptController1 +CSRRegister23_read_comb --> InternalInterruptController_InternalInterruptController2 +InternalInterruptController_InternalInterruptController2 --> CSRRegister23_write InternalInterruptController_InternalInterruptController --> CSRRegister11_write InternalInterruptController_InternalInterruptController --> CSRRegister12_write InternalInterruptController_InternalInterruptController --> CSRRegister13_write @@ -1184,25 +1193,43 @@ BasicFifo5_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO12_write FIFO13_read --> RSSelection_RSSelection2 +FIFO13_read --> RSSelection_RSSelection FIFO13_read --> RSSelection_RSSelection3 FIFO13_read --> RSSelection_RSSelection1 -FIFO13_read --> RSSelection_RSSelection RSFuncBlock_select --> RSSelection_RSSelection2 RS_select --> RSSelection_RSSelection2 RSSelection_RSSelection2 --> FIFO14_write +RSSelection_RSSelection --> FIFO14_write RSSelection_RSSelection3 --> FIFO14_write RSSelection_RSSelection1 --> FIFO14_write -RSSelection_RSSelection --> FIFO14_write -RSFuncBlock1_select --> RSSelection_RSSelection3 -RS1_select --> RSSelection_RSSelection3 -RSFuncBlock2_select --> RSSelection_RSSelection1 -FifoRS_select --> RSSelection_RSSelection1 -RSSelection_RSSelection <--> CSRUnit_select +RSSelection_RSSelection2 --> RegisterFile_read_req1 +RSSelection_RSSelection --> RegisterFile_read_req1 +RSSelection_RSSelection3 --> RegisterFile_read_req1 +RSSelection_RSSelection1 --> RegisterFile_read_req1 +RSSelection_RSSelection2 --> MemoryBank_read_req0 +RSSelection_RSSelection --> MemoryBank_read_req0 +RSSelection_RSSelection3 --> MemoryBank_read_req0 +RSSelection_RSSelection1 --> MemoryBank_read_req0 +RSSelection_RSSelection2 --> RegisterFile_read_req2 +RSSelection_RSSelection --> RegisterFile_read_req2 +RSSelection_RSSelection3 --> RegisterFile_read_req2 +RSSelection_RSSelection1 --> RegisterFile_read_req2 +RSSelection_RSSelection2 --> MemoryBank_read_req1 +RSSelection_RSSelection --> MemoryBank_read_req1 +RSSelection_RSSelection3 --> MemoryBank_read_req1 +RSSelection_RSSelection1 --> MemoryBank_read_req1 +RSFuncBlock1_select --> RSSelection_RSSelection +RS1_select --> RSSelection_RSSelection +RSFuncBlock2_select --> RSSelection_RSSelection3 +FifoRS_select --> RSSelection_RSSelection3 +RSSelection_RSSelection1 <--> CSRUnit_select FIFO14_read --> RSInsertion_RSInsertion -RegisterFile_read1 --> RSInsertion_RSInsertion -RegisterFile_read2 --> RSInsertion_RSInsertion +RegisterFile_read_resp1 --> RSInsertion_RSInsertion +MemoryBank_read_resp0 --> RSInsertion_RSInsertion +RegisterFile_read_resp2 --> RSInsertion_RSInsertion +MemoryBank_read_resp1 --> RSInsertion_RSInsertion Retirement_core_state --> RSInsertion_RSInsertion -Retirement_core_state --> LSUDummy_LSUDummy2 +Retirement_core_state --> LSUDummy_LSUDummy RSInsertion_RSInsertion --> RSFuncBlock_insert RSInsertion_RSInsertion --> RS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer1__start @@ -1235,6 +1262,7 @@ Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done ResultAnnouncement_ResultAnnouncement --> RegisterFile_write +ResultAnnouncement_ResultAnnouncement --> MemoryBank_write0 ResultAnnouncement_ResultAnnouncement --> TaggedLatencyMeasurer__start ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_write0 ResultAnnouncement_ResultAnnouncement --> MethodProduct_method @@ -1246,7 +1274,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add -RS_RS4 --> WakeupSelect_WakeupSelect +RS_RS1 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -1270,25 +1298,25 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter4__incr WakeupSelect_WakeupSelect --> FIFO2_write -RS_RS1 --> WakeupSelect1_WakeupSelect +RS_RS2 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write -RS_RS --> WakeupSelect2_WakeupSelect +RS_RS3 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write WakeupSelect2_WakeupSelect --> TaggedCounter5__incr -RS_RS3 --> WakeupSelect3_WakeupSelect +RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> BasicFifo6_write ConnectTrans8_ConnectTrans --> BasicFifo6_write ConnectTrans10_ConnectTrans --> BasicFifo6_write ConnectTrans5_ConnectTrans --> BasicFifo6_write +TransactionManager_ConnectTrans_accept_cond1 --> BasicFifo6_write TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo6_write -TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> BasicFifo6_write -TransactionManager_accept_cond1_ConnectTrans --> BasicFifo6_write +TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write -RS_RS2 --> WakeupSelect4_WakeupSelect +RS_RS4 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans6_ConnectTrans --> Forwarder5_write ConnectTrans7_ConnectTrans --> Forwarder5_write @@ -1342,35 +1370,35 @@ BasicFifo9_read --> ConnectTrans12_ConnectTrans FifoRS_perf --> HwExpHistogram10__add Forwarder7_read --> LSUDummy_LSUDummy1 -Forwarder7_read --> TransactionManager_LSUDummy_issue_cond0 Forwarder7_read --> TransactionManager_LSUDummy_issue_cond1 -Forwarder7_read --> TransactionManager_LSUDummy_issue_cond2 +Forwarder7_read --> TransactionManager_issue_cond2_LSUDummy +Forwarder7_read --> TransactionManager_issue_cond0_LSUDummy LSUDummy_LSUDummy1 --> FIFO9_write WakeupSelect7_WakeupSelect --> FIFO9_write -TransactionManager_LSUDummy_issue_cond0 --> FIFO9_write TransactionManager_LSUDummy_issue_cond1 --> FIFO9_write -TransactionManager_LSUDummy_issue_cond2 --> FIFO9_write +TransactionManager_issue_cond2_LSUDummy --> FIFO9_write +TransactionManager_issue_cond0_LSUDummy --> FIFO9_write LSUDummy_LSUDummy1 --> FIFO11_write WakeupSelect7_WakeupSelect --> FIFO11_write -TransactionManager_LSUDummy_issue_cond0 --> FIFO11_write TransactionManager_LSUDummy_issue_cond1 --> FIFO11_write -TransactionManager_LSUDummy_issue_cond2 --> FIFO11_write +TransactionManager_issue_cond2_LSUDummy --> FIFO11_write +TransactionManager_issue_cond0_LSUDummy --> FIFO11_write LSUDummy_LSUDummy3 --> Retirement_precommit CSRUnit_CSRUnit --> Retirement_precommit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> Retirement_precommit -TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> Retirement_precommit TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> Retirement_precommit TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> Retirement_precommit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> Retirement_precommit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> Retirement_precommit ReorderBuffer_peek --> LSUDummy_LSUDummy3 ReorderBuffer_peek --> CSRUnit_CSRUnit -ReorderBuffer_peek --> Retirement_Retirement3 ReorderBuffer_peek --> Retirement_Retirement +ReorderBuffer_peek --> Retirement_Retirement1 ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit -ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 FifoRS_FifoRS --> WakeupSelect7_WakeupSelect FifoRS_take --> WakeupSelect7_WakeupSelect WakeupSelect7_WakeupSelect --> TaggedLatencyMeasurer3__stop @@ -1490,41 +1518,41 @@ Collector3_method --> ConnectTrans4_ConnectTrans Forwarder8_read --> ConnectTrans4_ConnectTrans CSRUnit_get_result --> ConnectTrans5_ConnectTrans -ExceptionInformationRegister_get --> Retirement_Retirement3 +ExceptionInformationRegister_get --> Retirement_Retirement ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond1 -ExceptionInformationRegister_get --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement <--> ReorderBuffer_retire +ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement1 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire -TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire -Retirement_Retirement <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire +Retirement_Retirement1 <--> FIFOLatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop -TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer1__stop -FIFO1_read --> Retirement_Retirement +TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop +FIFO1_read --> Retirement_Retirement1 FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 -FIFO1_read --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement --> HwExpHistogram3__add +FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement1 --> HwExpHistogram3__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram3__add -CoreInstructionCounter_decrement --> Retirement_Retirement +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add +CoreInstructionCounter_decrement --> Retirement_Retirement1 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement -RRAT_peek --> Retirement_Retirement +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 +RRAT_peek --> Retirement_Retirement1 RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement --> RegisterFile_free +Retirement_Retirement1 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free -TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free -Retirement_Retirement --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free +Retirement_Retirement1 --> TaggedLatencyMeasurer__stop TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop -TransactionManager_Retirement_cond0_Retirement --> TaggedLatencyMeasurer__stop -AsyncMemoryBank_read0 --> Retirement_Retirement +TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop +AsyncMemoryBank_read0 --> Retirement_Retirement1 AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond1 -AsyncMemoryBank_read0 --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement --> HwExpHistogram1__add +AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement1 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add -Retirement_Retirement --> FRAT_rename +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add +Retirement_Retirement1 --> FRAT_rename TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename -TransactionManager_ROBAllocation_Renaming --> FRAT_rename +TransactionManager_Renaming_ROBAllocation --> FRAT_rename Retirement_Retirement2 <--> FIFOLatencyMeasurer2__stop FIFO15_read --> Retirement_Retirement2 Retirement_Retirement2 --> HwExpHistogram11__add @@ -1533,77 +1561,59 @@ CSRRegister6_read --> Retirement_Retirement2 Retirement_Retirement2 --> FetchUnit_resume_from_exception Retirement_Retirement2 <--> ExceptionInformationRegister_clear -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 -TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond0 -LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -LSURequester_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -BasicFifo10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -BasicFifo10_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -FIFO10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -FIFO10_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans +TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans13_ConnectTrans TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans13_ConnectTrans -TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> ConnectTrans13_ConnectTrans -TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans13_ConnectTrans +TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> ConnectTrans13_ConnectTrans +TransactionManager_ConnectTrans_accept_cond1 --> Forwarder8_write TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder8_write -TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> Forwarder8_write -TransactionManager_accept_cond1_ConnectTrans --> Forwarder8_write +TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> Forwarder8_write +LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -Serializer1_serialize_out1 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -Forwarder1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy -TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy -TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy -TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond0 --> BasicFifo10_write -TransactionManager_LSUDummy_issue_cond1 --> BasicFifo10_write -TransactionManager_LSUDummy_issue_cond2 --> BasicFifo10_write -TransactionManager_LSUDummy_issue_cond0 --> FIFO10_write -TransactionManager_LSUDummy_issue_cond1 --> FIFO10_write -TransactionManager_LSUDummy_issue_cond2 --> FIFO10_write -TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 -TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write -TransactionManager_LSUDummy_issue_cond0 --> Serializer1_serialize_in1 -TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write -TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write -TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request -TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1 -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement1 +LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1 +FIFO9_read --> TransactionManager_ConnectTrans_accept_cond1 +FIFO11_read --> TransactionManager_ConnectTrans_accept_cond1 +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement3 +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement3 TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start -TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer2__start +TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start TransactionManager_Retirement_Retirement_cond1 --> FIFO15_write -TransactionManager_Retirement_cond0_Retirement --> FIFO15_write +TransactionManager_Retirement_Retirement_cond0 --> FIFO15_write InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 -InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond0_Retirement +InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister6_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister7_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry -TransactionManager_Retirement_cond0_Retirement <--> InternalInterruptController_entry +TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 -TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -Serializer1_serialize_out0 --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans -TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 -FIFO9_read --> TransactionManager_accept_cond1_ConnectTrans -FIFO11_read --> TransactionManager_accept_cond1_ConnectTrans -TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 -TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read -TransactionManager_LSUDummy_issue_cond1 --> Serializer1_serialize_in0 +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit +TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment +CSRRegister24_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister24_write +CSRRegister25_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister25_write +TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr +CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 +CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2 TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> Semaphore_release @@ -1621,46 +1631,64 @@ TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter3__incr TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2_cond1 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr -CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit -CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret -TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 -TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation -Connect_read --> TransactionManager_ROBAllocation_Renaming -TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put -TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start -TransactionManager_ROBAllocation_Renaming --> FIFO1_write -TransactionManager_ROBAllocation_Renaming --> FIFO13_write -TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming -FIFO12_read --> TransactionManager_ROBAllocation_Renaming -TransactionManager_ROBAllocation_Renaming --> Connect_write -TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 -TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> ICache_flush -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_cond0_Retirement --> RRAT_commit -TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment -CSRRegister24_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister24_write -CSRRegister25_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister25_write -TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 +TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond0 +LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +BasicFifo10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +BasicFifo10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +FIFO10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +FIFO10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +Serializer1_serialize_out1 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy2 +TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy2 +TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy2 +TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue +TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond1 --> BasicFifo10_write +TransactionManager_issue_cond2_LSUDummy --> BasicFifo10_write +TransactionManager_issue_cond0_LSUDummy --> BasicFifo10_write +TransactionManager_LSUDummy_issue_cond1 --> FIFO10_write +TransactionManager_issue_cond2_LSUDummy --> FIFO10_write +TransactionManager_issue_cond0_LSUDummy --> FIFO10_write +TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 +TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read +TransactionManager_LSUDummy_issue_cond1 --> Serializer1_serialize_in0 +TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write +TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write +TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request +TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request +TransactionManager_Renaming_ROBAllocation <--> Renaming_Renaming +FIFO12_read --> TransactionManager_Renaming_ROBAllocation +TransactionManager_Renaming_ROBAllocation --> Connect_write +TransactionManager_Renaming_ROBAllocation <--> ROBAllocation_ROBAllocation +Connect_read --> TransactionManager_Renaming_ROBAllocation +TransactionManager_Renaming_ROBAllocation --> ReorderBuffer_put +TransactionManager_Renaming_ROBAllocation <--> FIFOLatencyMeasurer1__start +TransactionManager_Renaming_ROBAllocation --> FIFO1_write +TransactionManager_Renaming_ROBAllocation --> FIFO13_write TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret +TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 +TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write +TransactionManager_issue_cond0_LSUDummy --> Serializer1_serialize_in1 +TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +Serializer1_serialize_out0 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 @@ -1671,7 +1699,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/components/icache.html b/components/icache.html index be4922f00..25e5d989e 100644 --- a/components/icache.html +++ b/components/icache.html @@ -130,7 +130,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.arch.html b/coreblocks.arch.html index c9ce82a38..6249efe28 100644 --- a/coreblocks.arch.html +++ b/coreblocks.arch.html @@ -3948,7 +3948,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.backend.html b/coreblocks.backend.html index c9310b081..43bae6461 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -164,7 +164,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index 5ed07c8ec..4b2027ea8 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -240,7 +240,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index 3af7f668b..958dd0920 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -156,7 +156,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index d893eebb3..9fe1c9039 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -312,7 +312,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index 1cd2036f1..679923857 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -209,7 +209,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 3fc9787f6..0e3f97a80 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -186,7 +186,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.func_blocks.fu.fpu.html b/coreblocks.func_blocks.fu.fpu.html index 5fc3d64c8..b809048bd 100644 --- a/coreblocks.func_blocks.fu.fpu.html +++ b/coreblocks.func_blocks.fu.fpu.html @@ -302,7 +302,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index 3c8160cfb..8b3903a81 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -893,7 +893,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.func_blocks.fu.lsu.html b/coreblocks.func_blocks.fu.lsu.html index 63342f4dc..f98924307 100644 --- a/coreblocks.func_blocks.fu.lsu.html +++ b/coreblocks.func_blocks.fu.lsu.html @@ -289,7 +289,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index d1141422c..831868a87 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -259,7 +259,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index 79ac13d20..432edb94d 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -157,7 +157,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index 8b0124454..533411a03 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -163,7 +163,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.html b/coreblocks.html index f919b9de7..9abd3384d 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -272,7 +272,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.params.html b/coreblocks.params.html index 2adc440d6..d34136c9d 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -831,7 +831,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index 0b7196701..a6cd39b22 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -745,7 +745,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html index b4cdd92ca..6529001bd 100644 --- a/coreblocks.priv.csr.html +++ b/coreblocks.priv.csr.html @@ -305,7 +305,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.priv.html b/coreblocks.priv.html index c90e1b021..fa4866b84 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -123,7 +123,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index d56d2f701..61f31b0be 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -204,7 +204,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 41047db01..db8b2ed24 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -106,7 +106,7 @@

Submodules
-__init__(*, get_instr: Method, get_free_reg: Method, rat_rename: Method, rob_put: Method, rf_read1: Method, rf_read2: Method, reservation_stations: Sequence[tuple[coreblocks.func_blocks.interface.func_protocols.FuncBlock, set[coreblocks.arch.optypes.OpType]]], gen_params: GenParams)
+__init__(*, get_instr: Method, get_free_reg: Method, rat_rename: Method, rob_put: Method, rf_read_req1: Method, rf_read_req2: Method, rf_read_resp1: Method, rf_read_resp2: Method, reservation_stations: Sequence[tuple[coreblocks.func_blocks.interface.func_protocols.FuncBlock, set[coreblocks.arch.optypes.OpType]]], gen_params: GenParams)
Parameters
@@ -120,10 +120,16 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/current-graph.html b/current-graph.html index aea632bfd..dc837278f 100644 --- a/current-graph.html +++ b/current-graph.html @@ -90,9 +90,9 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/development-environment.html b/development-environment.html index d6950c4ef..70a53c0c3 100644 --- a/development-environment.html +++ b/development-environment.html @@ -208,7 +208,7 @@

tprof.py

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/genindex.html b/genindex.html index e8f7a073c..050afe32f 100644 --- a/genindex.html +++ b/genindex.html @@ -3430,7 +3430,7 @@

Z

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/home.html b/home.html index fb2f0cdfa..0866dc89e 100644 --- a/home.html +++ b/home.html @@ -128,7 +128,7 @@

Documentation

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/index.html b/index.html index d6ad81998..8dfeed745 100644 --- a/index.html +++ b/index.html @@ -202,7 +202,7 @@

Coreblocks

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html index b389c2745..2c5cc3405 100644 --- a/miscellany/exceptions-summary.html +++ b/miscellany/exceptions-summary.html @@ -270,7 +270,7 @@

Summary

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/modules-coreblocks.html b/modules-coreblocks.html index 9b2046b7f..36bc9668d 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -178,7 +178,7 @@

coreblocks

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/problem-checklist.html b/problem-checklist.html index 6cb972775..ed3d2fa1c 100644 --- a/problem-checklist.html +++ b/problem-checklist.html @@ -104,7 +104,7 @@

Problem checklist

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/py-modindex.html b/py-modindex.html index a3a7e4204..02daeed75 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -492,7 +492,7 @@

Python Module Index

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/scheduler/overview.html b/scheduler/overview.html index 7a13a9e25..01d1d29bb 100644 --- a/scheduler/overview.html +++ b/scheduler/overview.html @@ -145,7 +145,7 @@

More detailed description of each block

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/search.html b/search.html index 0b678617d..f1fd4b253 100644 --- a/search.html +++ b/search.html @@ -100,7 +100,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 22:06 2024-12-09. + Last updated on 09:56 2024-12-10.

diff --git a/searchindex.js b/searchindex.js index 79f60b0a4..c24e99af7 100644 --- a/searchindex.js +++ b/searchindex.js @@ -1 +1 @@ -Search.setIndex({"docnames": ["api", "assumptions", "auto_graph", "components/icache", "coreblocks", "coreblocks.arch", "coreblocks.backend", "coreblocks.cache", "coreblocks.core_structs", "coreblocks.frontend", "coreblocks.frontend.decoder", "coreblocks.frontend.fetch", "coreblocks.func_blocks", "coreblocks.func_blocks.fu", "coreblocks.func_blocks.fu.fpu", "coreblocks.func_blocks.fu.lsu", "coreblocks.func_blocks.fu.unsigned_multiplication", "coreblocks.func_blocks.interface", "coreblocks.params", "coreblocks.peripherals", "coreblocks.priv", "coreblocks.priv.csr", "coreblocks.priv.traps", "coreblocks.scheduler", "current-graph", "development-environment", "home", "index", "miscellany/exceptions-summary", "modules-coreblocks", "problem-checklist", "scheduler/overview", "shared-structs/implementation/rs-impl", "shared-structs/rs", "synthesis/synthesis"], "filenames": ["api.md", "assumptions.md", "auto_graph.rst", "components/icache.md", "coreblocks.rst", "coreblocks.arch.rst", "coreblocks.backend.rst", "coreblocks.cache.rst", "coreblocks.core_structs.rst", "coreblocks.frontend.rst", "coreblocks.frontend.decoder.rst", "coreblocks.frontend.fetch.rst", "coreblocks.func_blocks.rst", "coreblocks.func_blocks.fu.rst", "coreblocks.func_blocks.fu.fpu.rst", "coreblocks.func_blocks.fu.lsu.rst", "coreblocks.func_blocks.fu.unsigned_multiplication.rst", "coreblocks.func_blocks.interface.rst", "coreblocks.params.rst", "coreblocks.peripherals.rst", "coreblocks.priv.rst", "coreblocks.priv.csr.rst", "coreblocks.priv.traps.rst", "coreblocks.scheduler.rst", "current-graph.md", "development-environment.md", "home.md", "index.md", "miscellany/exceptions-summary.md", "modules-coreblocks.rst", "problem-checklist.md", "scheduler/overview.md", "shared-structs/implementation/rs-impl.md", "shared-structs/rs.md", "synthesis/synthesis.md"], "titles": ["API", "List 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[5, 10, 22, 32], "xlenencod": 5, "w128": 5, "w32": 5, "w64": 5, "cfityp": 5, "type": [5, 10, 11, 13, 18, 25], "flow": [5, 11], "There": 5, "main": [5, 25, 28, 31, 34], "invalid": [5, 33], "call": [5, 7, 18, 21, 22, 23, 25, 30, 32], "ret": 5, "just": [5, 25], "special": 5, "respect": [5, 21], "thu": 5, "encod": [5, 10, 18, 28], "wa": [5, 10, 11, 21, 22, 25, 28], "chosen": [5, 28], "wai": [5, 7, 13, 19, 25, 28, 34], "suffici": 5, "check": [5, 11, 14, 15, 25, 28, 30, 32, 33, 34], "lowest": 5, "two": [5, 7, 21, 28, 30, 34], "third": 5, "about": [5, 11, 18, 25, 27], "becaus": [5, 28], "tweak": 5, "helper": 5, "function": [5, 10, 13, 18, 21, 23, 28, 30], "prefer": [5, 19], "us": [5, 6, 7, 10, 11, 13, 15, 16, 18, 19, 21, 22, 23, 27, 28, 30, 34], "cfi": [5, 11], "static": [5, 18], "is_branch": 5, "amaranth": [5, 7, 9, 10, 11, 13, 18, 19, 21, 30, 34], "hdl": [5, 7, 9, 10, 13, 18, 21], "_ast": [5, 7, 9, 10, 13, 18, 21], "valuecast": [5, 9, 10, 18, 21], "is_jal": 5, "is_jalr": 5, "valid": [5, 13, 19, 23, 32], "do": [5, 10, 28, 30], "confus": 5, "address_gener": 5, "arithmet": [5, 14], "bit_manipul": 5, "bit_rot": 5, "compar": [5, 27], "csr_imm": 5, "csr_reg": 5, "div_rem": 5, "35": 5, "caus": [5, 18, 22, 28], "befor": [5, 15, 19, 22, 25, 30, 31], "execut": [5, 6, 13, 19, 23, 25, 27, 31, 33], "logic": [5, 15, 28, 33, 34], "33": 5, "single_bit_manipul": 5, "unary_bit_manipulation_1": 5, "unary_bit_manipulation_2": 5, "unary_bit_manipulation_3": 5, "unary_bit_manipulation_4": 5, "unary_bit_manipulation_5": 5, "unknown": [5, 25], "resultannounc": 6, "elaborat": [6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 19, 21, 22, 23], "simpl": [6, 7, 10, 15, 21, 23], "It": [6, 10, 11, 13, 15, 16, 18, 19, 21, 23, 25, 28, 31, 32, 34], "take": [6, 10, 14, 19, 31, 32], "its": [6, 10, 18, 21, 23, 28, 34], "mark": [6, 27, 28], "complet": [6, 19, 21, 28], "also": [6, 11, 18, 25, 34], "sent": [6, 19], "get_result": [6, 17], "serial": [6, 11, 15], "so": [6, 18, 19, 28, 34], "we": [6, 7, 19, 28, 31, 32, 33, 34], "more": [6, 21, 25, 27, 28], "than": [6, 28], "connect": [6, 10, 19, 21, 28], "manytooneconnecttran": 6, "fifo": [6, 28], "rob_mark_don": 6, "rs_updat": 6, "rf_write": 6, "instanc": [6, 7, 10, 11, 15, 18, 23, 34], "next": [6, 7, 10, 11, 23, 28], "readi": [6, 7, 19, 21, 23, 27, 32], "assum": [6, 13, 28], "differ": [6, 13, 19, 25, 26, 28, 30, 34], "end": [6, 15, 28], "without": [6, 23, 28], "pass": [6, 25, 34], "finish": [6, 19, 22], "debug_sign": 6, "rob_peek": 6, "rob_retir": 6, "r_rat_commit": 6, "r_rat_peek": 6, "free_rf_put": 6, "rf_free": 6, "exception_cause_get": 6, "exception_cause_clear": 6, "frat_renam": 6, "fetch_continu": 6, "instr_decr": 6, "trap_entri": 6, "async_interrupt_caus": 6, "cacheinterfac": [7, 11], "associ": [7, 18], "replac": [7, 16, 18, 21, 32], "polici": 7, "pseudo": 7, "random": 7, "scheme": 7, "everi": [7, 13, 19, 25, 34], "trash": 7, "select": [7, 10, 13, 17, 19, 23, 25], "keep": 7, "global": [7, 28], "abstract": [7, 16, 18, 34], "awai": 7, "need": [7, 11, 18, 19, 25, 28, 32], "refiller_start": 7, "whenev": [7, 18], "refiller_accept": 7, "written": [7, 21, 33, 34], "last": [7, 22, 23], "when": [7, 15, 18, 19, 22, 25, 28, 30, 32, 33], "either": [7, 18, 19, 22], "transfer": [7, 19], "over": [7, 21], "shouldn": [7, 34], "until": [7, 11, 28], "start": [7, 13, 15, 19, 22, 28], "layout": [7, 10, 11, 14, 19, 23, 25, 30], "icachelayout": 7, "icacheparamet": [7, 18], "cacherefillerinterfac": 7, "creat": [7, 16, 18, 19, 25, 34], "input": [7, 10, 13, 14, 19, 21, 22, 28, 32, 33], "start_refil": 7, "accept_refil": 7, "deserialize_addr": 7, "raw_addr": 7, "dict": [7, 19], "serialize_addr": 7, "addr": [7, 15, 19], "view": [7, 13, 15], "icachebypass": 7, "bus_mast": 7, "busmasterinterfac": [7, 9, 15, 19], "haselabor": [7, 17, 19], "protocol": [7, 17, 19], "whole": [7, 26, 28], "given": [7, 9, 15, 18, 21, 25, 32], "simplecommonbuscacherefil": 7, "frat": 8, "rrat": 8, "registerfil": 8, "reorderbuff": [8, 22], "corefrontend": 9, "consume_instr": 9, "consum": [9, 11], "resume_from_except": 9, "resum": 9, "pc": [9, 27], "resume_from_unsaf": 9, "unsaf": 9, "stall": [9, 19, 28], "instr_bu": 9, "frontendparam": 9, "fb_addr": 9, "fb_instr_idx": 9, "pc_from_fb": 9, "decodestag": 10, "instanti": 10, "instrdecod": 10, "make": [10, 13, 25, 26, 28, 30, 34], "actual": [10, 25, 27], "combinatori": 10, "manner": [10, 19], "get_raw": 10, "push_decod": 10, "raw": 10, "previou": [10, 11, 14, 19, 28], "step": [10, 11, 23, 25, 28, 34], "fetchlayout": [10, 11], "describ": [10, 11, 15, 23, 28, 34], "decodelayout": [10, 23], "elementari": 10, "etc": 10, "via": [10, 22], "gen": [10, 13, 16], "out": [10, 13, 16, 19, 22, 26, 27], "funct3_v": 10, "seven": 10, "funct7_v": 10, "twelv": 10, "funct12_v": 10, "rd": [10, 18], "reg_cnt_log": 10, "rd_v": 10, "rs1": [10, 18], "hold": [10, 18, 19], "first": [10, 13, 15, 21, 23, 28, 32, 33, 34], "rs1_v": 10, "rs2": [10, 18], "second": [10, 13, 21, 23, 32, 33, 34], "rs2_v": 10, "imm": [10, 18], "immedi": [10, 18, 19], "were": [10, 28], "succ": 10, "successor": 10, "pred": 10, "predecessor": 10, "fm": 10, "sourc": [10, 21, 23, 25, 32], "defin": [10, 15, 21], "kind": [10, 13, 23], "illeg": [10, 18], "success": [10, 19], "fit": 10, "constructor": 10, "repres": [10, 21], "exist": 10, "instr_type_overrid": 10, "specifi": [10, 19, 21, 33], "determin": [10, 11, 28, 34], "instrust": 10, "almost": 10, "correct": [10, 11, 15, 28, 32, 33, 34], "rd_zero": 10, "bool": [10, 15, 18, 21], "constant": 10, "other": [10, 18, 21, 25, 27], "accordingli": 10, "default": [10, 19, 21, 25], "fals": [10, 13, 15, 25], "rs1_zero": 10, "instrdecompress": 10, "decompr_reg": 10, "rvc_reg": 10, "instr_mux": 10, "sel": [10, 19], "list": [10, 13, 18, 19, 25, 27, 30, 34], "tupl": [10, 11, 13, 19, 21, 23], "is_instr_compress": 10, "fetchunit": 11, "superscalar": 11, "respons": [11, 13, 15, 19, 23, 25], "retriev": [11, 15], "them": [11, 25, 28, 34], "work": [11, 23, 28, 30, 34], "chunk": 11, "fetch_block_byt": 11, "relat": [11, 28], "how": [11, 18, 21, 25, 28, 32, 34], "mani": [11, 18, 21, 25, 28, 34], "onc": [11, 34], "vari": 11, "deal": 11, "expand": 11, "manag": [11, 13, 25, 27], "aren": [11, 28], "boundari": [11, 28], "cont": 11, "predecod": 11, "analysi": [11, 27], "jump": [11, 18, 28], "find": [11, 25, 28], "target": [11, 34], "Its": [11, 14, 15, 31], "role": 11, "give": 11, "quick": 11, "feedback": 11, "potenti": [11, 31], "predictor": 11, "help": [11, 25, 28], "redirect": 11, "promptli": 11, "predictioncheck": 11, "predict": 11, "checker": [11, 15], "look": [11, 28], "taken": [11, 21, 23, 34], "mistak": [11, 30], "ones": 11, "wrong": [11, 28], "element": [11, 28], "dispatch": [11, 28, 31, 32, 33], "new": [11, 13, 15, 19, 22, 27, 28], "batch": 11, "onli": [11, 13, 18, 19, 21, 22, 28, 34], "temporari": [11, 21], "workaround": 11, "buffer": [11, 19, 28, 32], "rest": 11, "becom": [11, 19], "elem_layout": 11, "lib": [11, 21], "structlayout": [11, 15], "collect": [11, 26, 34], "abc": [11, 18], "iter": [11, 17, 18], "shapelik": 11, "layoutlist": 11, "fpu": [12, 13], "fpu_common": [12, 13], "fpu_error_modul": [12, 13], "fpu_rounding_modul": [12, 13], "lsu": [12, 13], "dummylsu": [12, 13], "lsu_request": [12, 13], "pma": [12, 13], "unsigned_multipl": [12, 13], "common": [12, 13, 19], "fast_recurs": [12, 13], "sequenc": [12, 13, 23], "alucompon": 13, "functionalcomponentparam": [13, 15, 18], "zba_en": 13, "zbb_enabl": 13, "zicond_en": 13, "get_modul": [13, 15, 18], "funcunit": [13, 15, 17, 18], "get_optyp": [13, 15, 18], "alufuncunit": 13, "alu_fn": 13, "alufn": 13, "divcompon": 13, "ipc": [13, 34], "div_fn": 13, "divfn": 13, "decodermanag": 13, "fn": 13, "get_instruct": 13, "implement": [13, 15, 19, 21, 26, 27, 28, 31], "format": [13, 25, 34], "divunit": 13, "get_input": 13, "arg": [13, 19], "exceptionfuncunit": 13, "unit_fn": 13, "exceptionunitfn": 13, "exceptionunitcompon": 13, "jumpbranchfuncunit": 13, "jb_fn": 13, "jumpbranchfn": 13, "jumpcompon": 13, "mulcompon": 13, "mul_unit_typ": 13, "multyp": 13, "dsp_width": [13, 16], "mul_fn": 13, "mulfn": 13, "hot": [13, 28], "wire": 13, "recursive_mul": 13, "fastest": 13, "multipli": [13, 16], "costli": [13, 28], "term": 13, "resourc": [13, 22, 28, 34], "sequence_mul": 13, "dsp": [13, 16], "balanc": 13, "between": [13, 15, 25, 28], "cost": [13, 27], "shift_mul": 13, "cheapest": 13, "russian": [13, 16], "peasant": [13, 16], "algorithm": [13, 16], "mulunit": 13, "unsign": [13, 16], "standard": [13, 22, 28, 34], "funcunitlayout": [13, 23], "comput": [13, 16, 18, 22, 28], "mul_typ": 13, "privilegedfn": 13, "classmethod": 13, "privilegedfuncunit": 13, "privilegedunitcompon": 13, "shiftfuncunit": 13, "shift_unit_fn": 13, "shiftunitfn": 13, "shiftunitcompon": 13, "clmultipli": 13, "product": 13, "i1": [13, 16], "factor": 13, "i2": [13, 16], "reset": [13, 21, 27], "busi": 13, "while": 13, "progress": 13, "bit_width": [13, 21], "recursion_depth": 13, "depth": [13, 15, 19, 34], "recurs": [13, 16, 34], "parallel": 13, "power": 13, "iterative_modul": 13, "recursive_modul": 13, "zbccompon": 13, "zbc_fn": 13, "zbcfn": 13, "zbcunit": 13, "zbsfunction": 13, "in1": 13, "in2": 13, "zbscompon": 13, "zbsunit": 13, "zbs_fn": 13, "division_by_zero": 14, "inexact": 14, "invalid_oper": 14, "overflow": [14, 21], "underflow": 14, "fpuparam": 14, "sig_width": 14, "significand": 14, "includ": [14, 15, 34], "implicit": 14, "exp_width": 14, "expon": 14, "roundingmod": 14, "round_down": 14, "round_nearest_awai": 14, "round_nearest_even": 14, "round_up": 14, "round_zero": 14, "fpuerrormethodlayout": 14, "fpu_param": 14, "input_inf": 14, "flag": 14, "come": 14, "purpos": [14, 28], "indic": [14, 15, 28, 33], "infin": 14, "fpuerrormodul": 14, "round": [14, 19], "error_checking_request": 14, "initi": [14, 19, 27], "error_in_layout": 14, "argument": [14, 19, 23, 25, 33, 34], "final": 14, "error_out_layout": 14, "fpuroudningmethodlayout": 14, "fpuround": 14, "rounding_request": 14, "rounding_in_layout": 14, "rounding_out_layout": 14, "lsucompon": 15, "lsudummi": 15, "veri": [15, 28], "isn": [15, 34], "compliant": [15, 34], "riscv": [15, 18, 34], "spec": [15, 22], "doesn": [15, 28, 30], "rang": 15, "processor": [15, 26, 27, 31], "master": [15, 19, 34], "lsurequest": 15, "job": [15, 28], "resili": 15, "check_align": 15, "tmodul": [15, 19, 21, 22], "postprocess_load_data": 15, "modulelik": 15, "raw_data": 15, "prepare_bytes_mask": 15, "prepare_data_to_sav": 15, "pmacheck": 15, "physic": [15, 23, 28], "mai": [15, 18, 25], "part": [15, 18, 21, 22, 28, 31], "combin": [15, 30], "circuit": [15, 34], "pmalayout": 15, "pmaregion": 15, "contigu": 15, "region": [15, 28], "both": [15, 21, 32], "begin": [15, 28], "mmio": 15, "true": [15, 18, 19, 21], "dspmulunit": 16, "clock": [16, 31, 34], "design": [16, 28], "synthesi": [16, 27], "tool": [16, 25, 34], "o": [16, 28], "same": [16, 18, 21, 25], "mulbaseunsign": 16, "unsignedmulunitlayout": 16, "recursiveunsignedmul": 16, "see": [16, 22, 30, 34], "fast": 16, "within": [16, 25], "pipelinedunsignedmul": 16, "dsp_number": 16, "sequentialunsignedmul": 16, "sequenti": [16, 19], "classic": [16, 28], "shiftunsignedmul": 16, "cheap": 16, "multi": 16, "funcblocksunifi": 17, "blockcomponentparam": [17, 18], "funcblock": [17, 18, 23], "insert": [17, 22, 23, 27, 28, 31, 32], "coreconfigur": 18, "_coreconfigurationdataclass": 18, "kwarg": [18, 19], "self": 18, "get_rs_entry_count": 18, "optypes_support": 18, "dependentcach": 18, "cfg": 18, "addr_width": [18, 19], "word_width": 18, "word": 18, "num_of_wai": 18, "num_of_sets_bit": 18, "log": [18, 19, 28], "line_bytes_log": 18, "disabl": 18, "bypass": 18, "fetch_block_bytes_log": 18, "python": [18, 25], "model": 18, "stefan": 18, "wallentowitz": 18, "http": [18, 34], "github": [18, 26, 34], "com": [18, 34], "wallento": 18, "btypeinstr": 18, "instructionfunct3typ": 18, "posit": [18, 23, 32, 33], "where": [18, 19, 23, 25, 28, 32, 33], "would": [18, 25, 28], "map": [18, 21, 27, 28], "sign": 18, "whether": [18, 34], "skip": 18, "exampl": [18, 21, 25, 27, 32], "signific": 18, "affect": [18, 34], "procedur": [18, 28], "extern": [18, 27, 34], "static_valu": 18, "ebreakinstr": 18, "itypeinstr": 18, "illegalinstr": 18, "riscvinstr": 18, "cat": [18, 34], "const": 18, "d1": 18, "jtypeinstr": 18, "as_valu": 18, "convert": 18, "concret": 18, "usual": [18, 28], "deleg": 18, "must": [18, 19], "idempot": 18, "twice": 18, "exactli": 18, "code": [18, 25, 26, 28, 30, 34], "recogn": 18, "cast": 18, "rais": [18, 28], "convers": 18, "cannot": 18, "done": [18, 28, 34], "propag": 18, "caller": [18, 25], "directli": 18, "recommend": 18, "shape": 18, "itself": [18, 28], "discov": 18, "castabl": 18, "subclass": 18, "richer": 18, "represent": 18, "shapecast": 18, "rtypeinstr": 18, "instructionfunct7typ": 18, "stypeinstr": 18, "utypeinstr": 18, "axiliteinterfac": 19, "abstractinterfac": 19, "abstractsignatur": 19, "read_address": 19, "axilitereadaddressinterfac": 19, "read_data": 19, "axilitereaddatainterfac": 19, "write_address": 19, "axilitewriteaddressinterfac": 19, "write_data": 19, "axilitewritedatainterfac": 19, "write_respons": 19, "axilitewriteresponseinterfac": 19, "axilitemast": 19, "axi": 19, "lite": 19, "axil_param": 19, "axiliteparamet": 19, "ra_request": 19, "channel": 19, "being": [19, 25], "ra_request_layout": 19, "rd_respons": 19, "availab": 19, "state": [19, 22, 27, 28], "rd_response_layout": 19, "wa_request": 19, "wa_request_layout": 19, "wd_request": 19, "wd_request_layout": 19, "wr_respons": 19, "wr_response_layout": 19, "axil_mast": 19, "result_handl": 19, "start_request_transact": 19, "is_address_channel": 19, "state_machine_request": 19, "request_sign": 19, "data_width": 19, "axilitesignatur": 19, "signatur": 19, "patamet": 19, "axilitemasteradapt": 19, "adapt": 19, "place": [19, 28, 32, 34], "expect": 19, "busparametersinterfac": 19, "method_layout": 19, "commonbusmastermethodlayout": 19, "request_read": 19, "underli": 19, "request_read_layout": 19, "request_writ": 19, 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Read and clean row

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diff --git a/shared-structs/rs.html b/shared-structs/rs.html index 9bf6fe528..cae8410bd 100644 --- a/shared-structs/rs.html +++ b/shared-structs/rs.html @@ -221,7 +221,7 @@

External interface signals

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diff --git a/synthesis/synthesis.html b/synthesis/synthesis.html index 531dd2eda..65ef2c1b1 100644 --- a/synthesis/synthesis.html +++ b/synthesis/synthesis.html @@ -265,7 +265,7 @@

Regression tests manual execution

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