From 04871936e2c20c9a2429a8543f72114ff36d62e9 Mon Sep 17 00:00:00 2001 From: lekcyjna123 <34948061+lekcyjna123@users.noreply.github.com> Date: Mon, 11 Mar 2024 17:05:12 +0100 Subject: [PATCH 1/4] Add CI runs for #604 (#608) --- .github/workflows/main.yml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 90b928b38..5ee446967 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -263,6 +263,12 @@ jobs: . venv/bin/activate scripts/run_tests.py -a regression + - name: Check regression with pysim + run: | + . venv/bin/activate + ./scripts/run_tests.py -c 1 -a -b pysim regression + + unit-test: name: Run unit tests runs-on: ubuntu-latest @@ -292,6 +298,9 @@ jobs: - name: Check traces and profiles run: ./scripts/run_tests.py -t -p -c 1 TestCore + - name: Check listing tests + run: ./scripts/run_tests.py -l + lint: name: Check code formatting and typing runs-on: ubuntu-latest From 6d8bba8dad67f1cb9a884762ef495bcbd13850da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jakub=20Urba=C5=84czyk?= Date: Tue, 12 Mar 2024 16:49:18 +0000 Subject: [PATCH 2/4] Add B extension support to the toolchain Dockerfile (#615) --- docker/riscv-toolchain.Dockerfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docker/riscv-toolchain.Dockerfile b/docker/riscv-toolchain.Dockerfile index 957141eb0..a998e79e3 100644 --- a/docker/riscv-toolchain.Dockerfile +++ b/docker/riscv-toolchain.Dockerfile @@ -12,8 +12,8 @@ RUN apt-get update && \ RUN git clone --shallow-since=2023.05.01 https://github.com/riscv/riscv-gnu-toolchain && \ cd riscv-gnu-toolchain && \ - git checkout 2023.05.14 && \ - ./configure --with-multilib-generator="rv32i-ilp32--a*zifence*zicsr;rv32im-ilp32--a*zifence*zicsr;rv32ic-ilp32--a*zifence*zicsr;rv32imc-ilp32--a*zifence*zicsr;rv32imfc-ilp32f--a*zifence;rv32i_zmmul-ilp32--a*zifence*zicsr;rv32ic_zmmul-ilp32--a*zifence*zicsr" && \ + git checkout 2023.12.10 && \ + ./configure --with-multilib-generator="rv32i-ilp32--a*zifence*zicsr;rv32im-ilp32--a*zifence*zicsr;rv32ic-ilp32--a*zifence*zicsr;rv32imc-ilp32--a*zifence*zicsr;rv32imfc-ilp32f--a*zifence;rv32imc_zba_zbb_zbc_zbs-ilp32--a*zifence*zicsr" && \ make -j$(nproc) && \ cd / && rm -rf riscv-gnu-toolchain From 58249da625a3b981af7d4bafab97b47b6e73f811 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jakub=20Urba=C5=84czyk?= Date: Tue, 12 Mar 2024 17:21:11 +0000 Subject: [PATCH 3/4] Enable division and bit manipulation extensions in benchmarks (#616) --- .github/workflows/benchmark.yml | 2 +- .github/workflows/main.yml | 4 ++-- test/external/embench/board_config/coreblocks-sim/board.cfg | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/benchmark.yml b/.github/workflows/benchmark.yml index 45429f68d..1fc7fac1d 100644 --- a/.github/workflows/benchmark.yml +++ b/.github/workflows/benchmark.yml @@ -63,7 +63,7 @@ jobs: build-perf-benchmarks: name: Build performance benchmarks runs-on: ubuntu-latest - container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.11.19_v + container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12 steps: - name: Checkout uses: actions/checkout@v3 diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 5ee446967..23c1aa56c 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -48,7 +48,7 @@ jobs: build-riscof-tests: name: Build regression tests (riscv-arch-test) runs-on: ubuntu-latest - container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.11.19_v + container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12 timeout-minutes: 10 env: PYENV_ROOT: "/root/.pyenv" @@ -180,7 +180,7 @@ jobs: build-regression-tests: name: Build regression tests (riscv-tests) runs-on: ubuntu-latest - container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.11.19_v + container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12 timeout-minutes: 10 outputs: cache_hit: ${{ steps.cache-regression.outputs.cache-hit }} diff --git a/test/external/embench/board_config/coreblocks-sim/board.cfg b/test/external/embench/board_config/coreblocks-sim/board.cfg index 96eaae307..b1a885340 100644 --- a/test/external/embench/board_config/coreblocks-sim/board.cfg +++ b/test/external/embench/board_config/coreblocks-sim/board.cfg @@ -1,5 +1,5 @@ cc = 'riscv64-unknown-elf-gcc' -cflags = (['-c', '-fdata-sections', '-march=rv32ic_zmmul_zicsr', '-mabi=ilp32']) -ldflags = (['-Wl,-gc-sections', '-march=rv32ic_zmmul_zicsr', '-mabi=ilp32', '-nostartfiles', '-T../../../common/link.ld']) +cflags = (['-c', '-fdata-sections', '-march=rv32imc_zba_zbb_zbc_zbs_zicsr', '-mabi=ilp32']) +ldflags = (['-Wl,-gc-sections', '-march=rv32imc_zba_zbb_zbc_zbs_zicsr', '-mabi=ilp32', '-nostartfiles', '-T../../../common/link.ld']) user_libs = (['-lm']) cpu_mhz = 0.01 From 182c85a06a2e2370742cdc5104895823a55b0bb4 Mon Sep 17 00:00:00 2001 From: lekcyjna123 <34948061+lekcyjna123@users.noreply.github.com> Date: Tue, 12 Mar 2024 23:19:51 +0100 Subject: [PATCH 4/4] Fix profiles on newer yosys version (#607) --- test/regression/cocotb.py | 7 +++---- transactron/utils/gen.py | 7 ++----- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/test/regression/cocotb.py b/test/regression/cocotb.py index 87c043688..e68c6f9ca 100644 --- a/test/regression/cocotb.py +++ b/test/regression/cocotb.py @@ -157,10 +157,9 @@ def get_cocotb_handle(self, path_components: list[str]) -> ModifiableObject: # function instead of 'getattr' - this is required by cocotb. obj = obj._id(component, extended=False) except AttributeError: - if component[0] == "\\" and component[-1] == " ": - # workaround for cocotb/verilator weirdness - # for some escaped names lookup fails, but works when unescaped - obj = obj._id(component[1:-1], extended=False) + # Try with escaped name + if component[0] != "\\" and component[-1] != " ": + obj = obj._id("\\" + component + " ", extended=False) else: raise diff --git a/transactron/utils/gen.py b/transactron/utils/gen.py index 2ff40dec2..f87706750 100644 --- a/transactron/utils/gen.py +++ b/transactron/utils/gen.py @@ -149,7 +149,7 @@ def escape_verilog_identifier(identifier: str) -> str: # The standard says how to escape a identifier, but not when. So this is # a non-exhaustive list of characters that Yosys escapes (it is used # by Amaranth when generating Verilog code). - characters_to_escape = [".", "$"] + characters_to_escape = [".", "$", "-"] for char in characters_to_escape: if char in identifier: @@ -160,10 +160,7 @@ def escape_verilog_identifier(identifier: str) -> str: def get_signal_location(signal: Signal, name_map: "SignalDict") -> list[str]: raw_location = name_map[signal] - - # Amaranth escapes identifiers when generating Verilog code, but returns non-escaped identifiers - # in the name map, so we need to escape it manually. - return [escape_verilog_identifier(component) for component in raw_location] + return raw_location def collect_metric_locations(name_map: "SignalDict") -> dict[str, MetricLocation]: