diff --git a/coreblocks/peripherals/wishbone.py b/coreblocks/peripherals/wishbone.py
index 4f7fb4272..e71617682 100644
--- a/coreblocks/peripherals/wishbone.py
+++ b/coreblocks/peripherals/wishbone.py
@@ -309,10 +309,10 @@ class WishboneMuxer(Component):
 
     Parameters
     ----------
-    master_wb: WishboneInterface
-        Master inteface.
-    slaves: list of WishboneInterface
-        List of connected slaves' Wishbone interfaces.
+    wb_params: WishboneParameters
+        Parameters for bus generation.
+    num_slaves: int
+        Number of slave devices to multiplex.
     ssel_tga: Signal
         Signal that selects the slave to connect. Signal width is the number of slaves and each bit coresponds
         to a slave. This signal is a Wishbone TGA (address tag), so it needs to be valid every time Wishbone STB
@@ -321,6 +321,13 @@ class WishboneMuxer(Component):
         different `ssel_tga` value, all pending request have to be finished (and `stall` cleared) and
         there have to be  one cycle delay from previouse request (to deassert the STB signal).  Holding new
         requests should be implemented in block that controlls `ssel_tga` signal, before the Wishbone Master.
+
+    Attributes
+    ----------
+    master_wb: WishboneInterface
+        Master inteface.
+    slaves: list of WishboneInterface
+        List of connected slaves' Wishbone interfaces.
     """
 
     master_wb: WishboneInterface
@@ -383,6 +390,13 @@ class WishboneArbiter(Component):
 
     Parameters
     ----------
+    wb_params: WishboneParameters
+        Parameters for bus generation.
+    num_slaves: int
+        Number of master devices.
+
+    Attributes
+    ----------
     slave_wb: WishboneInterface
         Slave inteface.
     masters: list of WishboneInterface