diff --git a/coreblocks/core.py b/coreblocks/core.py
index 409ab3238..1cec20059 100644
--- a/coreblocks/core.py
+++ b/coreblocks/core.py
@@ -20,7 +20,7 @@
 from coreblocks.frontend.icache import ICache, SimpleWBCacheRefiller, ICacheBypass
 from coreblocks.peripherals.wishbone import WishboneMaster, WishboneBus
 from coreblocks.frontend.fetch import Fetch, UnalignedFetch
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils.fifo import BasicFifo
 
 __all__ = ["Core"]
 
diff --git a/coreblocks/frontend/fetch.py b/coreblocks/frontend/fetch.py
index 3b1090b51..74c3861a1 100644
--- a/coreblocks/frontend/fetch.py
+++ b/coreblocks/frontend/fetch.py
@@ -1,5 +1,5 @@
 from amaranth import *
-from coreblocks.utils.fifo import BasicFifo, Semaphore
+from transactron.utils.fifo import BasicFifo, Semaphore
 from coreblocks.frontend.icache import ICacheInterface
 from coreblocks.frontend.rvc import InstrDecompress, is_instr_compressed
 from transactron import def_method, Method, Transaction, TModule
diff --git a/coreblocks/frontend/icache.py b/coreblocks/frontend/icache.py
index d5cbb8d8a..6fd7d38d1 100644
--- a/coreblocks/frontend/icache.py
+++ b/coreblocks/frontend/icache.py
@@ -8,8 +8,8 @@
 from transactron.core import def_method, Priority, TModule
 from transactron import Method, Transaction
 from coreblocks.params import ICacheLayouts, ICacheParameters
-from coreblocks.utils import assign, OneHotSwitchDynamic
-from coreblocks.utils._typing import HasElaborate
+from transactron.utils import assign, OneHotSwitchDynamic
+from transactron.utils._typing import HasElaborate
 from transactron.lib import *
 from coreblocks.peripherals.wishbone import WishboneMaster
 
diff --git a/coreblocks/frontend/rvc.py b/coreblocks/frontend/rvc.py
index 17be75d62..ad5156ebc 100644
--- a/coreblocks/frontend/rvc.py
+++ b/coreblocks/frontend/rvc.py
@@ -2,7 +2,7 @@
 
 from transactron import TModule
 from coreblocks.params import *
-from coreblocks.utils import ValueLike
+from transactron.utils import ValueLike
 
 
 # An instruction or an instruction with the valid signal
diff --git a/coreblocks/fu/alu.py b/coreblocks/fu/alu.py
index 76de2188f..f9a2bad21 100644
--- a/coreblocks/fu/alu.py
+++ b/coreblocks/fu/alu.py
@@ -5,14 +5,14 @@
 from transactron.lib import FIFO
 
 from coreblocks.params import OpType, Funct3, Funct7, GenParams, FuncUnitLayouts, FunctionalComponentParams
-from coreblocks.utils import HasElaborate, OneHotSwitch
+from transactron.utils import HasElaborate, OneHotSwitch
 
 from coreblocks.fu.fu_decoder import DecoderManager
 from enum import IntFlag, auto
 
 from coreblocks.utils.protocols import FuncUnit
 
-from coreblocks.utils.utils import popcount, count_leading_zeros
+from transactron.utils.utils import popcount, count_leading_zeros
 
 __all__ = ["AluFuncUnit", "ALUComponent"]
 
diff --git a/coreblocks/fu/div_unit.py b/coreblocks/fu/div_unit.py
index c874d439f..a39390af8 100644
--- a/coreblocks/fu/div_unit.py
+++ b/coreblocks/fu/div_unit.py
@@ -12,8 +12,8 @@
 
 from coreblocks.fu.fu_decoder import DecoderManager
 
-from coreblocks.utils import OneHotSwitch
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils import OneHotSwitch
+from transactron.utils.fifo import BasicFifo
 from coreblocks.utils.protocols import FuncUnit
 from coreblocks.fu.division.long_division import LongDivider
 
diff --git a/coreblocks/fu/exception.py b/coreblocks/fu/exception.py
index bca24f08b..4ef733e8c 100644
--- a/coreblocks/fu/exception.py
+++ b/coreblocks/fu/exception.py
@@ -7,7 +7,7 @@
 from transactron.lib import FIFO
 
 from coreblocks.params import OpType, GenParams, FuncUnitLayouts, FunctionalComponentParams
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.params.keys import ExceptionReportKey
 
 from coreblocks.fu.fu_decoder import DecoderManager
diff --git a/coreblocks/fu/jumpbranch.py b/coreblocks/fu/jumpbranch.py
index dcd5f0936..b42320a23 100644
--- a/coreblocks/fu/jumpbranch.py
+++ b/coreblocks/fu/jumpbranch.py
@@ -9,7 +9,7 @@
 from transactron.lib import *
 
 from coreblocks.params import *
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.utils.protocols import FuncUnit
 
 from coreblocks.fu.fu_decoder import DecoderManager
diff --git a/coreblocks/fu/mul_unit.py b/coreblocks/fu/mul_unit.py
index 3d4888cfa..47f9e9f6e 100644
--- a/coreblocks/fu/mul_unit.py
+++ b/coreblocks/fu/mul_unit.py
@@ -18,7 +18,7 @@
 
 __all__ = ["MulUnit", "MulFn", "MulComponent", "MulType"]
 
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.utils.protocols import FuncUnit
 
 
diff --git a/coreblocks/fu/shift_unit.py b/coreblocks/fu/shift_unit.py
index 14a8ae6e7..7e73ae2f4 100644
--- a/coreblocks/fu/shift_unit.py
+++ b/coreblocks/fu/shift_unit.py
@@ -5,7 +5,7 @@
 from transactron.lib import FIFO
 
 from coreblocks.params import OpType, Funct3, Funct7, GenParams, FuncUnitLayouts, FunctionalComponentParams
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 
 from coreblocks.fu.fu_decoder import DecoderManager
 from enum import IntFlag, auto
diff --git a/coreblocks/fu/zbc.py b/coreblocks/fu/zbc.py
index bba84ddb3..8834d40fe 100644
--- a/coreblocks/fu/zbc.py
+++ b/coreblocks/fu/zbc.py
@@ -14,7 +14,7 @@
 )
 from transactron import Method, def_method, TModule
 from transactron.lib import FIFO
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.utils.protocols import FuncUnit
 
 
diff --git a/coreblocks/fu/zbs.py b/coreblocks/fu/zbs.py
index fa0b9e86e..d135c5e75 100644
--- a/coreblocks/fu/zbs.py
+++ b/coreblocks/fu/zbs.py
@@ -5,7 +5,7 @@
 from coreblocks.params import Funct3, GenParams, FuncUnitLayouts, OpType, Funct7, FunctionalComponentParams
 from transactron import Method, TModule, def_method
 from transactron.lib import FIFO
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.utils.protocols import FuncUnit
 
 from coreblocks.fu.fu_decoder import DecoderManager
diff --git a/coreblocks/lsu/dummyLsu.py b/coreblocks/lsu/dummyLsu.py
index 497ef3355..cb506aafc 100644
--- a/coreblocks/lsu/dummyLsu.py
+++ b/coreblocks/lsu/dummyLsu.py
@@ -3,7 +3,7 @@
 from transactron import Method, def_method, Transaction, TModule
 from coreblocks.params import *
 from coreblocks.peripherals.wishbone import WishboneMaster
-from coreblocks.utils import assign, ModuleLike
+from transactron.utils import assign, ModuleLike
 from coreblocks.utils.protocols import FuncBlock
 
 
diff --git a/coreblocks/params/instr.py b/coreblocks/params/instr.py
index 5e77763fa..ae207b1dd 100644
--- a/coreblocks/params/instr.py
+++ b/coreblocks/params/instr.py
@@ -3,7 +3,7 @@
 from amaranth.hdl.ast import ValueCastable
 from amaranth import *
 
-from coreblocks.utils import ValueLike
+from transactron.utils import ValueLike
 from coreblocks.params.isa import *
 
 
diff --git a/coreblocks/params/layouts.py b/coreblocks/params/layouts.py
index 9386d11e0..2a0f1a3e0 100644
--- a/coreblocks/params/layouts.py
+++ b/coreblocks/params/layouts.py
@@ -1,6 +1,6 @@
 from coreblocks.params import GenParams, OpType, Funct7, Funct3
 from coreblocks.params.isa import ExceptionCause
-from coreblocks.utils.utils import layout_subset
+from transactron.utils.utils import layout_subset
 
 __all__ = [
     "SchedulerLayouts",
diff --git a/coreblocks/peripherals/wishbone.py b/coreblocks/peripherals/wishbone.py
index c6035431d..01f80338e 100644
--- a/coreblocks/peripherals/wishbone.py
+++ b/coreblocks/peripherals/wishbone.py
@@ -7,8 +7,8 @@
 
 from transactron import Method, def_method, TModule
 from transactron.lib import AdapterTrans
-from coreblocks.utils.utils import OneHotSwitchDynamic, assign
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils.utils import OneHotSwitchDynamic, assign
+from transactron.utils.fifo import BasicFifo
 
 
 class WishboneParameters:
diff --git a/coreblocks/scheduler/scheduler.py b/coreblocks/scheduler/scheduler.py
index eab680fe2..3fe9ea293 100644
--- a/coreblocks/scheduler/scheduler.py
+++ b/coreblocks/scheduler/scheduler.py
@@ -5,7 +5,7 @@
 from transactron import Method, Transaction, TModule
 from transactron.lib import FIFO, Forwarder
 from coreblocks.params import SchedulerLayouts, GenParams, OpType
-from coreblocks.utils import assign, AssignType
+from transactron.utils import assign, AssignType
 from coreblocks.utils.protocols import FuncBlock
 
 
diff --git a/coreblocks/scheduler/wakeup_select.py b/coreblocks/scheduler/wakeup_select.py
index 7480a3936..fbe6d40a4 100644
--- a/coreblocks/scheduler/wakeup_select.py
+++ b/coreblocks/scheduler/wakeup_select.py
@@ -1,7 +1,7 @@
 from amaranth import *
 
 from coreblocks.params import GenParams, FuncUnitLayouts
-from coreblocks.utils import assign, AssignType
+from transactron.utils import assign, AssignType
 from transactron.core import *
 
 __all__ = ["WakeupSelect"]
diff --git a/coreblocks/structs_common/csr.py b/coreblocks/structs_common/csr.py
index 0f8eba862..3dc4763d6 100644
--- a/coreblocks/structs_common/csr.py
+++ b/coreblocks/structs_common/csr.py
@@ -3,7 +3,7 @@
 from dataclasses import dataclass
 
 from transactron import Method, def_method, Transaction, TModule
-from coreblocks.utils import assign, bits_from_int
+from transactron.utils import assign, bits_from_int
 from coreblocks.params.genparams import GenParams
 from coreblocks.params.dependencies import DependencyManager, ListKey
 from coreblocks.params.fu_params import BlockComponentParams
diff --git a/coreblocks/utils/__init__.py b/coreblocks/utils/__init__.py
index a1cd9d2e0..e69de29bb 100644
--- a/coreblocks/utils/__init__.py
+++ b/coreblocks/utils/__init__.py
@@ -1,3 +0,0 @@
-from .utils import *  # noqa: F401
-from ._typing import *  # noqa: F401
-from .debug_signals import *  # noqa: F401
diff --git a/coreblocks/utils/protocols.py b/coreblocks/utils/protocols.py
index bc7885274..70f542bc2 100644
--- a/coreblocks/utils/protocols.py
+++ b/coreblocks/utils/protocols.py
@@ -1,6 +1,6 @@
 from typing import Protocol
 from transactron import Method
-from ._typing import HasElaborate
+from transactron.utils._typing import HasElaborate
 
 
 __all__ = ["FuncUnit", "FuncBlock", "Unifier"]
diff --git a/scripts/gen_verilog.py b/scripts/gen_verilog.py
index 4f388a825..42bf94e4e 100755
--- a/scripts/gen_verilog.py
+++ b/scripts/gen_verilog.py
@@ -16,7 +16,7 @@
 from coreblocks.peripherals.wishbone import WishboneBus
 from coreblocks.core import Core
 from transactron import TransactionModule
-from coreblocks.utils.utils import flatten_signals
+from transactron.utils.utils import flatten_signals
 
 from coreblocks.params.configurations import *
 
diff --git a/scripts/synthesize.py b/scripts/synthesize.py
index 3763b921f..572e4b77a 100755
--- a/scripts/synthesize.py
+++ b/scripts/synthesize.py
@@ -13,7 +13,7 @@
     sys.path.insert(0, parent)
 
 
-from coreblocks.utils.utils import ModuleConnector
+from transactron.utils.utils import ModuleConnector
 from coreblocks.params.genparams import GenParams
 from coreblocks.params.fu_params import FunctionalComponentParams
 from coreblocks.core import Core
diff --git a/test/common/functions.py b/test/common/functions.py
index c4ffc814a..42b43cdf1 100644
--- a/test/common/functions.py
+++ b/test/common/functions.py
@@ -2,7 +2,7 @@
 from amaranth.hdl.ast import Statement
 from amaranth.sim.core import Command
 from typing import TypeVar, Any, Generator, TypeAlias
-from coreblocks.utils._typing import RecordValueDict, RecordIntDict
+from transactron.utils._typing import RecordValueDict, RecordIntDict
 
 T = TypeVar("T")
 TestGen: TypeAlias = Generator[Command | Value | Statement | None, Any, T]
diff --git a/test/common/infrastructure.py b/test/common/infrastructure.py
index fe0b337d4..e1141a0eb 100644
--- a/test/common/infrastructure.py
+++ b/test/common/infrastructure.py
@@ -11,7 +11,7 @@
 from transactron import Method
 from transactron.lib import AdapterTrans
 from transactron.core import TransactionModule
-from coreblocks.utils import ModuleConnector, HasElaborate, auto_debug_signals, HasDebugSignals
+from transactron.utils import ModuleConnector, HasElaborate, auto_debug_signals, HasDebugSignals
 
 T = TypeVar("T")
 _T_nested_collection = T | list["_T_nested_collection[T]"] | dict[str, "_T_nested_collection[T]"]
diff --git a/test/common/sugar.py b/test/common/sugar.py
index beb4acf3a..e0ac3473c 100644
--- a/test/common/sugar.py
+++ b/test/common/sugar.py
@@ -1,7 +1,7 @@
 import functools
 from typing import Callable, Any, Optional
 from .testbenchio import TestbenchIO, TestGen
-from coreblocks.utils._typing import RecordIntDict
+from transactron.utils._typing import RecordIntDict
 
 
 def def_method_mock(
diff --git a/test/common/testbenchio.py b/test/common/testbenchio.py
index 9a2c956d8..0ff3e9d74 100644
--- a/test/common/testbenchio.py
+++ b/test/common/testbenchio.py
@@ -4,7 +4,7 @@
 from transactron.lib import AdapterBase
 from transactron.core import ValueLike, SignalBundle
 from transactron._utils import mock_def_helper
-from coreblocks.utils._typing import RecordIntDictRet, RecordValueDict, RecordIntDict
+from transactron.utils._typing import RecordIntDictRet, RecordValueDict, RecordIntDict
 from .functions import set_inputs, get_outputs, TestGen
 
 
diff --git a/test/frontend/test_fetch.py b/test/frontend/test_fetch.py
index 9df857ea5..3817c0312 100644
--- a/test/frontend/test_fetch.py
+++ b/test/frontend/test_fetch.py
@@ -11,7 +11,7 @@
 from coreblocks.frontend.icache import ICacheInterface
 from coreblocks.params import *
 from coreblocks.params.configurations import test_core_config
-from coreblocks.utils import ModuleConnector
+from transactron.utils import ModuleConnector
 from ..common import TestCaseWithSimulator, TestbenchIO, def_method_mock
 
 
diff --git a/test/frontend/test_rvc.py b/test/frontend/test_rvc.py
index 188339cd9..e8d9e4d5b 100644
--- a/test/frontend/test_rvc.py
+++ b/test/frontend/test_rvc.py
@@ -6,7 +6,7 @@
 from coreblocks.frontend.rvc import InstrDecompress
 from coreblocks.params import *
 from coreblocks.params.configurations import test_core_config
-from coreblocks.utils import ValueLike
+from transactron.utils import ValueLike
 
 from ..common import TestCaseWithSimulator
 
diff --git a/test/gtkw_extension.py b/test/gtkw_extension.py
index 4d8582f93..d548ad6e7 100644
--- a/test/gtkw_extension.py
+++ b/test/gtkw_extension.py
@@ -2,7 +2,7 @@
 from contextlib import contextmanager
 from amaranth.sim.pysim import _VCDWriter
 from amaranth import *
-from coreblocks.utils.utils import flatten_signals
+from transactron.utils.utils import flatten_signals
 
 
 class _VCDWriterExt(_VCDWriter):
diff --git a/test/regression/memory.py b/test/regression/memory.py
index f1640f71a..38abacd63 100644
--- a/test/regression/memory.py
+++ b/test/regression/memory.py
@@ -6,7 +6,7 @@
 from elftools.elf.constants import P_FLAGS
 from elftools.elf.elffile import ELFFile, Segment
 from coreblocks.params.configurations import CoreConfiguration
-from coreblocks.utils.utils import align_to_power_of_two, align_down_to_power_of_two
+from transactron.utils.utils import align_to_power_of_two, align_down_to_power_of_two
 
 all = [
     "ReplyStatus",
diff --git a/test/structs_common/test_exception.py b/test/structs_common/test_exception.py
index f8bde5c56..12238c8f0 100644
--- a/test/structs_common/test_exception.py
+++ b/test/structs_common/test_exception.py
@@ -6,7 +6,7 @@
 from coreblocks.params.isa import ExceptionCause
 from coreblocks.params.configurations import test_core_config
 from transactron.lib import Adapter
-from coreblocks.utils.utils import ModuleConnector
+from transactron.utils.utils import ModuleConnector
 
 from ..common import *
 
diff --git a/test/test_core.py b/test/test_core.py
index aa03c64e3..a44d92c12 100644
--- a/test/test_core.py
+++ b/test/test_core.py
@@ -1,7 +1,7 @@
 from amaranth import Elaboratable, Module
 
 from transactron.lib import AdapterTrans
-from coreblocks.utils import align_to_power_of_two
+from transactron.utils import align_to_power_of_two
 
 from .common import TestCaseWithSimulator, TestbenchIO
 
diff --git a/test/transactions/test_assign.py b/test/transactions/test_assign.py
index 6f0569dbc..7f472b57f 100644
--- a/test/transactions/test_assign.py
+++ b/test/transactions/test_assign.py
@@ -3,8 +3,8 @@
 from amaranth.lib import data
 from amaranth.hdl.ast import ArrayProxy, Slice
 
-from coreblocks.utils._typing import LayoutLike
-from coreblocks.utils.utils import AssignArg, AssignType, AssignFields, assign
+from transactron.utils._typing import LayoutLike
+from transactron.utils.utils import AssignArg, AssignType, AssignFields, assign
 
 from unittest import TestCase
 from parameterized import parameterized_class, parameterized
diff --git a/test/transactions/test_simultaneous.py b/test/transactions/test_simultaneous.py
index ac3009ac7..0f33d2021 100644
--- a/test/transactions/test_simultaneous.py
+++ b/test/transactions/test_simultaneous.py
@@ -3,7 +3,7 @@
 from amaranth import *
 from amaranth.sim import *
 
-from coreblocks.utils.utils import ModuleConnector
+from transactron.utils.utils import ModuleConnector
 
 from ..common import SimpleTestCircuit, TestCaseWithSimulator, TestbenchIO, def_method_mock
 
diff --git a/test/transactions/test_transaction_lib.py b/test/transactions/test_transaction_lib.py
index a23ee077e..d43540860 100644
--- a/test/transactions/test_transaction_lib.py
+++ b/test/transactions/test_transaction_lib.py
@@ -13,8 +13,8 @@
 from transactron.core import RecordDict
 from transactron.lib import *
 from coreblocks.utils import *
-from coreblocks.utils._typing import LayoutLike, ModuleLike
-from coreblocks.utils import ModuleConnector
+from transactron.utils._typing import LayoutLike, ModuleLike
+from transactron.utils import ModuleConnector
 from ..common import (
     SimpleTestCircuit,
     TestCaseWithSimulator,
diff --git a/test/utils/test_fifo.py b/test/utils/test_fifo.py
index 81c764099..2f5608141 100644
--- a/test/utils/test_fifo.py
+++ b/test/utils/test_fifo.py
@@ -1,6 +1,6 @@
 from amaranth import *
 
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils.fifo import BasicFifo
 from transactron.lib import AdapterTrans
 
 from test.common import TestCaseWithSimulator, TestbenchIO, data_layout
diff --git a/test/utils/test_onehotswitch.py b/test/utils/test_onehotswitch.py
index d6c70180f..12d8373b9 100644
--- a/test/utils/test_onehotswitch.py
+++ b/test/utils/test_onehotswitch.py
@@ -1,7 +1,7 @@
 from amaranth import *
 from amaranth.sim import *
 
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 
 from test.common import TestCaseWithSimulator
 
diff --git a/test/utils/test_utils.py b/test/utils/test_utils.py
index 6a948f490..a26567003 100644
--- a/test/utils/test_utils.py
+++ b/test/utils/test_utils.py
@@ -3,7 +3,7 @@
 
 from amaranth import *
 from test.common import *
-from coreblocks.utils import (
+from transactron.utils import (
     align_to_power_of_two,
     align_down_to_power_of_two,
     popcount,
diff --git a/transactron/_utils.py b/transactron/_utils.py
index bcd60d8db..1ad803e1f 100644
--- a/transactron/_utils.py
+++ b/transactron/_utils.py
@@ -4,8 +4,8 @@
 from typing import Any, Concatenate, Optional, TypeAlias, TypeGuard, TypeVar
 from collections.abc import Callable, Iterable, Mapping
 from amaranth import *
-from coreblocks.utils._typing import LayoutLike, ShapeLike
-from coreblocks.utils import OneHotSwitchDynamic
+from transactron.utils._typing import LayoutLike, ShapeLike
+from transactron.utils import OneHotSwitchDynamic
 
 __all__ = [
     "Scheduler",
diff --git a/transactron/core.py b/transactron/core.py
index 035b3b588..363a59f06 100644
--- a/transactron/core.py
+++ b/transactron/core.py
@@ -21,11 +21,10 @@
 from itertools import count, chain, filterfalse, product
 from amaranth.hdl.dsl import FSM, _ModuleBuilderDomain
 
-from coreblocks.utils import AssignType, assign, ModuleConnector
-from coreblocks.utils.utils import OneHotSwitchDynamic
+from transactron.utils import AssignType, assign, ModuleConnector, silence_mustuse
+from transactron.utils.utils import OneHotSwitchDynamic
 from ._utils import *
-from coreblocks.utils import silence_mustuse
-from coreblocks.utils._typing import ValueLike, SignalBundle, HasElaborate, SwitchKey, ModuleLike
+from transactron.utils._typing import ValueLike, SignalBundle, HasElaborate, SwitchKey, ModuleLike
 from .graph import Owned, OwnershipGraph, Direction
 
 __all__ = [
diff --git a/transactron/lib/reqres.py b/transactron/lib/reqres.py
index ace563c1b..3587edc3e 100644
--- a/transactron/lib/reqres.py
+++ b/transactron/lib/reqres.py
@@ -1,7 +1,7 @@
 from amaranth import *
 from ..core import *
 from .connectors import Forwarder, FIFO
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils.fifo import BasicFifo
 from amaranth.utils import *
 
 __all__ = [
diff --git a/transactron/lib/simultaneous.py b/transactron/lib/simultaneous.py
index 093bfb78d..48814cde8 100644
--- a/transactron/lib/simultaneous.py
+++ b/transactron/lib/simultaneous.py
@@ -3,7 +3,7 @@
 from ..core import TransactionBase
 from contextlib import contextmanager
 from typing import Optional
-from coreblocks.utils import ValueLike
+from transactron.utils import ValueLike
 
 __all__ = [
     "condition",
diff --git a/transactron/lib/storage.py b/transactron/lib/storage.py
index 4723e3713..9d95f6a83 100644
--- a/transactron/lib/storage.py
+++ b/transactron/lib/storage.py
@@ -2,7 +2,7 @@
 from amaranth.utils import *
 from ..core import *
 from typing import Optional
-from coreblocks.utils import assign, AssignType
+from transactron.utils import assign, AssignType
 from .reqres import ArgumentsToResultsZipper
 
 __all__ = ["MemoryBank"]
diff --git a/transactron/lib/transformers.py b/transactron/lib/transformers.py
index e4b7aa0c0..b3d1e2470 100644
--- a/transactron/lib/transformers.py
+++ b/transactron/lib/transformers.py
@@ -3,7 +3,7 @@
 from ..core import RecordDict
 from typing import Optional
 from collections.abc import Callable
-from coreblocks.utils import ValueLike, assign, AssignType
+from transactron.utils import ValueLike, assign, AssignType
 from .connectors import Forwarder, ManyToOneConnectTrans, ConnectTrans
 
 __all__ = [
diff --git a/transactron/tracing.py b/transactron/tracing.py
index 2a944ce6d..036044aed 100644
--- a/transactron/tracing.py
+++ b/transactron/tracing.py
@@ -7,7 +7,7 @@
 from amaranth.hdl.ir import Elaboratable, Fragment, Instance
 from amaranth.hdl.xfrm import FragmentTransformer
 from amaranth.hdl import dsl, ir, mem, xfrm
-from coreblocks.utils import HasElaborate
+from transactron.utils import HasElaborate
 from . import core
 
 
diff --git a/transactron/utils/__init__.py b/transactron/utils/__init__.py
new file mode 100644
index 000000000..a1cd9d2e0
--- /dev/null
+++ b/transactron/utils/__init__.py
@@ -0,0 +1,3 @@
+from .utils import *  # noqa: F401
+from ._typing import *  # noqa: F401
+from .debug_signals import *  # noqa: F401
diff --git a/coreblocks/utils/_typing.py b/transactron/utils/_typing.py
similarity index 100%
rename from coreblocks/utils/_typing.py
rename to transactron/utils/_typing.py
diff --git a/coreblocks/utils/debug_signals.py b/transactron/utils/debug_signals.py
similarity index 100%
rename from coreblocks/utils/debug_signals.py
rename to transactron/utils/debug_signals.py
diff --git a/coreblocks/utils/fifo.py b/transactron/utils/fifo.py
similarity index 99%
rename from coreblocks/utils/fifo.py
rename to transactron/utils/fifo.py
index 2f95adf19..94e136e13 100644
--- a/coreblocks/utils/fifo.py
+++ b/transactron/utils/fifo.py
@@ -1,7 +1,7 @@
 from amaranth import *
 from transactron import Method, def_method, Priority, TModule
 from transactron._utils import MethodLayout
-from coreblocks.utils._typing import ValueLike
+from transactron.utils._typing import ValueLike
 
 
 class BasicFifo(Elaboratable):
diff --git a/coreblocks/utils/utils.py b/transactron/utils/utils.py
similarity index 100%
rename from coreblocks/utils/utils.py
rename to transactron/utils/utils.py