From 741df1857628242a6ed6811ef7d56868945b5c71 Mon Sep 17 00:00:00 2001
From: tilk <tilk@tilk.eu>
Date: Sun, 24 Mar 2024 21:22:32 +0000
Subject: [PATCH] Remove riscvmodel dependency (#627)

---
 .doctrees/api.doctree                         | Bin 21253 -> 21253 bytes
 .doctrees/auto_graph.doctree                  | Bin 44181 -> 44170 bytes
 .doctrees/coreblocks.params.doctree           | Bin 265757 -> 294694 bytes
 .doctrees/current-graph.doctree               | Bin 45402 -> 45391 bytes
 .doctrees/environment.pickle                  | Bin 503922 -> 505265 bytes
 _sources/auto_graph.rst.txt                   | 306 ++++++++---------
 api.html                                      |   2 +-
 assumptions.html                              |   2 +-
 auto_graph.html                               | 308 +++++++++---------
 components/icache.html                        |   2 +-
 coreblocks.backend.html                       |   2 +-
 coreblocks.cache.html                         |   2 +-
 coreblocks.core_structs.html                  |   2 +-
 coreblocks.frontend.decoder.html              |   2 +-
 coreblocks.frontend.fetch.html                |   2 +-
 coreblocks.frontend.html                      |   2 +-
 coreblocks.func_blocks.fu.html                |   2 +-
 ...unc_blocks.fu.unsigned_multiplication.html |   2 +-
 coreblocks.func_blocks.html                   |   2 +-
 coreblocks.func_blocks.interface.html         |   2 +-
 coreblocks.func_blocks.lsu.html               |   2 +-
 coreblocks.html                               |   2 +-
 coreblocks.params.html                        |  37 ++-
 coreblocks.peripherals.html                   |   2 +-
 coreblocks.priv.csr.html                      |   2 +-
 coreblocks.priv.html                          |   2 +-
 coreblocks.priv.traps.html                    |   2 +-
 coreblocks.scheduler.html                     |   2 +-
 current-graph.html                            | 308 +++++++++---------
 development-environment.html                  |   2 +-
 genindex.html                                 |  22 +-
 home.html                                     |   2 +-
 index.html                                    |   2 +-
 miscellany/exceptions-summary.html            |   2 +-
 modules-coreblocks.html                       |   2 +-
 modules-transactron.html                      |   2 +-
 objects.inv                                   | Bin 10491 -> 10520 bytes
 problem-checklist.html                        |   2 +-
 py-modindex.html                              |   2 +-
 scheduler/overview.html                       |   2 +-
 search.html                                   |   2 +-
 searchindex.js                                |   2 +-
 shared-structs/implementation/rs-impl.html    |   2 +-
 shared-structs/rs.html                        |   2 +-
 synthesis/synthesis.html                      |   2 +-
 transactions.html                             |   2 +-
 transactron.core.html                         |   2 +-
 transactron.html                              |   2 +-
 transactron.lib.html                          |   2 +-
 transactron.testing.html                      |   2 +-
 transactron.utils.amaranth_ext.html           |   2 +-
 transactron.utils.html                        |   2 +-
 52 files changed, 556 insertions(+), 507 deletions(-)

diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree
index 19112a7e04844d1d4bae2f034ad9ce8ca3009eb3..bc67edd998ea397f2445c31876ac0b1dc5a58ed1 100644
GIT binary patch
delta 499
zcmY+By-EW?6om<>VB%jAG%hL{f(k-bvB+j+!56T#)G#|4vqN@gmYLbr#-Aou+uiLf
z#3qGRz|!7Fu(cI@09$7hqOlw9J@cJ&@9p(-y?$=+-hfYQV`)(d#3aH>aAx|{g{swn
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z=gd;<^O%U3lFMPX-^3vjD9~$J{QG5wg2rhw<?(=M!bHPGxI3CI6x{VmP}g+a^{Lc*
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PHigE*iDSInI`=C-W3IqM

delta 532
zcmY*V%Sr<=6s7oB_-;o=EF$;-b<q|#ov{?$`wt>%8lBKg5|f$n0n(K#gPWUg5JV6`
z`~v?$Kfpgw+?!F9xI5f??m6e4%bUvOP37UG4KfNVlW^Nz2~0Iph--v1C3rK>DAO<!
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PGTZ_jN5SKH_bU7XRK(AR

diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree
index 8dbfba44e4c32b4cb29a03c78e14da92e2b7bda5..238dffa2b09d3aa3b34b9e31d89b97f2e7ff45cb 100644
GIT binary patch
delta 2751
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delta 2501
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diff --git a/.doctrees/coreblocks.params.doctree b/.doctrees/coreblocks.params.doctree
index bbf2b3b489cef50b5b569e39d2ef326883d06ab1..47500e28a8236d0658a3e5055259afa3f7d1ab9a 100644
GIT binary patch
delta 36327
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diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree
index 421bb7c314b252e80acd0a8753a9ee57fc654688..acc70ebf54f66afd20ac540281166d39a5105599 100644
GIT binary patch
delta 2786
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delta 2521
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diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle
index d870bb378d889ee6728bff85c70db7a4ebad39c7..d61ad87eaed82d49f22d24e7cf2f1c4a20f4f0f6 100644
GIT binary patch
delta 58454
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Lyg&XEDhd4$Pcsqx

diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt
index 37f3bf235..6e03e683f 100644
--- a/_sources/auto_graph.rst.txt
+++ b/_sources/auto_graph.rst.txt
@@ -4,15 +4,15 @@
        subgraph TransactionModule["TransactionModule"]
            subgraph CoreTestElaboratable["elaboratable CoreTestElaboratable"]
                subgraph Core["core Core"]
-                   Core_InitFreeRFFifo["InitFreeRFFifo"]
                    Core_DiscardBranchVerify["DiscardBranchVerify"]
+                   Core_InitFreeRFFifo["InitFreeRFFifo"]
                    subgraph WishboneMaster["wb_master_instr WishboneMaster"]
                        WishboneMaster_WishboneMaster["WishboneMaster"]
-                       WishboneMaster_result["result"]
                        WishboneMaster_request["request"]
+                       WishboneMaster_result["result"]
                        subgraph Forwarder["result Forwarder"]
-                           Forwarder_write["write"]
                            Forwarder_read["read"]
+                           Forwarder_write["write"]
                        end
                    end
                    subgraph WishboneMaster1["wb_master_data WishboneMaster"]
@@ -20,8 +20,8 @@
                        WishboneMaster1_request["request"]
                        WishboneMaster1_result["result"]
                        subgraph Forwarder1["result Forwarder"]
-                           Forwarder1_read["read"]
                            Forwarder1_write["write"]
+                           Forwarder1_read["read"]
                        end
                    end
                    subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"]
@@ -31,8 +31,8 @@
                            Serializer_Serializer["Serializer"]
                            Serializer_Serializer1["Serializer"]
                            subgraph BasicFifo["pending_requests BasicFifo"]
-                               BasicFifo_write["write"]
                                BasicFifo_read["read"]
+                               BasicFifo_write["write"]
                            end
                        end
                    end
@@ -47,18 +47,18 @@
                            Serializer1_Serializer2["Serializer"]
                            Serializer1_Serializer3["Serializer"]
                            subgraph BasicFifo1["pending_requests BasicFifo"]
-                               BasicFifo1_write["write"]
                                BasicFifo1_read["read"]
+                               BasicFifo1_write["write"]
                            end
                        end
                    end
                    subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"]
-                       CoreInstructionCounter_increment["increment"]
                        CoreInstructionCounter_decrement["decrement"]
+                       CoreInstructionCounter_increment["increment"]
                    end
                    subgraph FIFO["fifo_fetch FIFO"]
-                       FIFO_read["read"]
                        FIFO_write["write"]
+                       FIFO_read["read"]
                    end
                    subgraph MethodMap["core_counter_increment_discard_map MethodMap"]
                        MethodMap_method["method"]
@@ -72,16 +72,16 @@
                    end
                    subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"]
                        SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"]
-                       SimpleCommonBusCacheRefiller_accept_refill["accept_refill"]
                        SimpleCommonBusCacheRefiller_start_refill["start_refill"]
+                       SimpleCommonBusCacheRefiller_accept_refill["accept_refill"]
                        subgraph Forwarder2["address_fwd Forwarder"]
-                           Forwarder2_write["write"]
                            Forwarder2_read["read"]
+                           Forwarder2_write["write"]
                        end
                    end
                    subgraph ICache["icache ICache"]
-                       ICache_ICache["ICache"]
                        ICache_accept_res["accept_res"]
+                       ICache_ICache["ICache"]
                        ICache_ICache1["ICache"]
                        ICache_ICache2["ICache"]
                        ICache_issue_req["issue_req"]
@@ -102,19 +102,19 @@
                            HwCounter4__incr["_incr"]
                        end
                        subgraph LatencyMeasurer["req_latency LatencyMeasurer"]
-                           LatencyMeasurer__start["_start"]
                            LatencyMeasurer__stop["_stop"]
+                           LatencyMeasurer__start["_start"]
                            subgraph HwExpHistogram["histogram HwExpHistogram"]
                                HwExpHistogram__add["_add"]
                            end
                            subgraph FIFO1["fifo FIFO"]
-                               FIFO1_write["write"]
                                FIFO1_read["read"]
+                               FIFO1_write["write"]
                            end
                        end
                        subgraph FIFO2["req_fifo FIFO"]
-                           FIFO2_read["read"]
                            FIFO2_write["write"]
+                           FIFO2_read["read"]
                        end
                        subgraph Forwarder3["res_fwd Forwarder"]
                            Forwarder3_write["write"]
@@ -125,50 +125,50 @@
                        FRAT_rename["rename"]
                    end
                    subgraph RRAT["RRAT RRAT"]
-                       RRAT_commit["commit"]
                        RRAT_peek["peek"]
+                       RRAT_commit["commit"]
                    end
                    subgraph RegisterFile["RF RegisterFile"]
+                       RegisterFile_read2["read2"]
                        RegisterFile_read1["read1"]
-                       RegisterFile_free["free"]
                        RegisterFile_write["write"]
-                       RegisterFile_read2["read2"]
+                       RegisterFile_free["free"]
                    end
                    subgraph ReorderBuffer["ROB ReorderBuffer"]
                        ReorderBuffer_put["put"]
-                       ReorderBuffer_get_indices["get_indices"]
-                       ReorderBuffer_mark_done["mark_done"]
                        ReorderBuffer_retire["retire"]
+                       ReorderBuffer_mark_done["mark_done"]
+                       ReorderBuffer_get_indices["get_indices"]
                        ReorderBuffer_peek["peek"]
                        subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"]
-                           LatencyMeasurer1__stop["_stop"]
                            LatencyMeasurer1__start["_start"]
+                           LatencyMeasurer1__stop["_stop"]
                            subgraph HwExpHistogram1["histogram HwExpHistogram"]
                                HwExpHistogram1__add["_add"]
                            end
                            subgraph FIFO3["fifo FIFO"]
-                               FIFO3_read["read"]
                                FIFO3_write["write"]
+                               FIFO3_read["read"]
                            end
                        end
                    end
                    subgraph Fetch["fetch Fetch"]
                        Fetch_Fetch["Fetch"]
                        Fetch_Fetch1["Fetch"]
-                       Fetch_resume["resume"]
                        Fetch_stall_exception["stall_exception"]
+                       Fetch_resume["resume"]
                        subgraph BasicFifo3["fetch_target_queue BasicFifo"]
                            BasicFifo3_read["read"]
                            BasicFifo3_write["write"]
                        end
                    end
                    subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"]
+                       ExceptionCauseRegister_clear["clear"]
                        ExceptionCauseRegister_get["get"]
                        ExceptionCauseRegister_report["report"]
-                       ExceptionCauseRegister_clear["clear"]
                        subgraph BasicFifo4["fu_report_fifo BasicFifo"]
-                           BasicFifo4_read["read"]
                            BasicFifo4_write["write"]
+                           BasicFifo4_read["read"]
                        end
                        subgraph ConnectTrans["report_connector ConnectTrans"]
                            ConnectTrans_ConnectTrans["ConnectTrans"]
@@ -178,8 +178,8 @@
                        subgraph Collector["result_collector Collector"]
                            Collector_method["method"]
                            subgraph Forwarder4["forwarder Forwarder"]
-                               Forwarder4_read["read"]
                                Forwarder4_write["write"]
+                               Forwarder4_read["read"]
                            end
                            subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"]
                                subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"]
@@ -197,15 +197,15 @@
                            MethodProduct1_method["method"]
                        end
                        subgraph RSFuncBlock["rs_block_0 RSFuncBlock"]
-                           RSFuncBlock_get_result["get_result"]
-                           RSFuncBlock_select["select"]
                            RSFuncBlock_insert["insert"]
                            RSFuncBlock_update["update"]
+                           RSFuncBlock_get_result["get_result"]
+                           RSFuncBlock_select["select"]
                            subgraph RS["rs RS"]
                                RS_update["update"]
+                               RS_select["select"]
                                RS_RS["RS"]
                                RS_RS1["RS"]
-                               RS_select["select"]
                                RS_take["take"]
                                RS_RS2["RS"]
                                RS_RS3["RS"]
@@ -213,11 +213,11 @@
                                RS_insert["insert"]
                            end
                            subgraph AluFuncUnit["func_unit_0 AluFuncUnit"]
-                               AluFuncUnit_issue["issue"]
                                AluFuncUnit_accept["accept"]
+                               AluFuncUnit_issue["issue"]
                                subgraph FIFO4["fifo FIFO"]
-                                   FIFO4_read["read"]
                                    FIFO4_write["write"]
+                                   FIFO4_read["read"]
                                end
                            end
                            subgraph WakeupSelect["wakeup_select_0 WakeupSelect"]
@@ -227,16 +227,16 @@
                                ShiftFuncUnit_issue["issue"]
                                ShiftFuncUnit_accept["accept"]
                                subgraph FIFO5["fifo FIFO"]
-                                   FIFO5_read["read"]
                                    FIFO5_write["write"]
+                                   FIFO5_read["read"]
                                end
                            end
                            subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"]
                                WakeupSelect1_WakeupSelect["WakeupSelect"]
                            end
                            subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"]
-                               JumpBranchFuncUnit_accept["accept"]
                                JumpBranchFuncUnit_issue["issue"]
+                               JumpBranchFuncUnit_accept["accept"]
                                subgraph FIFO6["fifo_branch_resolved FIFO"]
                                    FIFO6_read["read"]
                                    FIFO6_write["write"]
@@ -251,16 +251,16 @@
                                    HwCounter7__incr["_incr"]
                                end
                                subgraph FIFO7["fifo_res FIFO"]
-                                   FIFO7_write["write"]
                                    FIFO7_read["read"]
+                                   FIFO7_write["write"]
                                end
                            end
                            subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"]
                                WakeupSelect2_WakeupSelect["WakeupSelect"]
                            end
                            subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"]
-                               ExceptionFuncUnit_issue["issue"]
                                ExceptionFuncUnit_accept["accept"]
+                               ExceptionFuncUnit_issue["issue"]
                                subgraph FIFO8["fifo FIFO"]
                                    FIFO8_read["read"]
                                    FIFO8_write["write"]
@@ -274,8 +274,8 @@
                                PrivilegedFuncUnit_precommit["precommit"]
                                PrivilegedFuncUnit_issue["issue"]
                                subgraph BasicFifo5["fetch_resume_fifo BasicFifo"]
-                                   BasicFifo5_read["read"]
                                    BasicFifo5_write["write"]
+                                   BasicFifo5_read["read"]
                                end
                            end
                            subgraph WakeupSelect4["wakeup_select_4 WakeupSelect"]
@@ -284,8 +284,8 @@
                            subgraph Collector1["collector Collector"]
                                Collector1_method["method"]
                                subgraph Forwarder5["forwarder Forwarder"]
-                                   Forwarder5_write["write"]
                                    Forwarder5_read["read"]
+                                   Forwarder5_write["write"]
                                end
                                subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"]
                                    subgraph ConnectTrans4["ManyToOneConnectTrans_input_0 ConnectTrans"]
@@ -307,36 +307,36 @@
                            end
                        end
                        subgraph LSUDummy["rs_block_1 LSUDummy"]
-                           LSUDummy_insert["insert"]
-                           LSUDummy_precommit["precommit"]
                            LSUDummy_get_result["get_result"]
-                           LSUDummy_update["update"]
                            LSUDummy_LSUDummy["LSUDummy"]
                            LSUDummy_LSUDummy1["LSUDummy"]
-                           LSUDummy_LSUDummy2["LSUDummy"]
+                           LSUDummy_insert["insert"]
                            LSUDummy_select["select"]
+                           LSUDummy_LSUDummy2["LSUDummy"]
+                           LSUDummy_update["update"]
+                           LSUDummy_precommit["precommit"]
                            subgraph Forwarder6["forwarder Forwarder"]
                                Forwarder6_write["write"]
                                Forwarder6_read["read"]
                            end
                            subgraph LSURequester["requester LSURequester"]
-                               LSURequester_accept["accept"]
-                               LSURequester_accept_cond0["accept_cond0"]
                                LSURequester_issue_cond2["issue_cond2"]
-                               LSURequester_issue["issue"]
-                               LSURequester_accept_cond1["accept_cond1"]
-                               LSURequester_issue_cond0["issue_cond0"]
+                               LSURequester_accept_cond0["accept_cond0"]
                                LSURequester_issue_cond1["issue_cond1"]
+                               LSURequester_issue_cond0["issue_cond0"]
+                               LSURequester_accept["accept"]
+                               LSURequester_accept_cond1["accept_cond1"]
+                               LSURequester_issue["issue"]
                            end
                        end
                        subgraph CSRUnit["rs_block_2 CSRUnit"]
-                           CSRUnit_select["select"]
-                           CSRUnit_CSRUnit["CSRUnit"]
-                           CSRUnit_update["update"]
-                           CSRUnit_precommit["precommit"]
                            CSRUnit_get_result["get_result"]
+                           CSRUnit_CSRUnit["CSRUnit"]
                            CSRUnit_insert["insert"]
+                           CSRUnit_select["select"]
                            CSRUnit_fetch_resume["fetch_resume"]
+                           CSRUnit_update["update"]
+                           CSRUnit_precommit["precommit"]
                        end
                        subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"]
                            MethodTryProduct_MethodTryProduct["MethodTryProduct"]
@@ -365,8 +365,8 @@
                    end
                    subgraph InterruptController["interrupt_controller InterruptController"]
                        InterruptController_report_interrupt["report_interrupt"]
-                       InterruptController_entry["entry"]
                        InterruptController_mret["mret"]
+                       InterruptController_entry["entry"]
                    end
                    subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"]
                        GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"]
@@ -377,41 +377,41 @@
                                CSRRegister_write["write"]
                            end
                            subgraph CSRRegister1["mtvec CSRRegister"]
-                               CSRRegister1__fu_read["_fu_read"]
-                               CSRRegister1_read["read"]
                                CSRRegister1__fu_write["_fu_write"]
+                               CSRRegister1_read["read"]
+                               CSRRegister1__fu_read["_fu_read"]
                            end
                            subgraph CSRRegister2["mepc CSRRegister"]
                                CSRRegister2_read["read"]
+                               CSRRegister2__fu_read["_fu_read"]
                                CSRRegister2_write["write"]
                                CSRRegister2__fu_write["_fu_write"]
-                               CSRRegister2__fu_read["_fu_read"]
                            end
                        end
                        subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"]
                            DoubleCounterCSR_increment["increment"]
                            subgraph CSRRegister3["register_low CSRRegister"]
-                               CSRRegister3__fu_read["_fu_read"]
-                               CSRRegister3_write["write"]
                                CSRRegister3_read["read"]
+                               CSRRegister3_write["write"]
+                               CSRRegister3__fu_read["_fu_read"]
                            end
                            subgraph CSRRegister4["register_high CSRRegister"]
+                               CSRRegister4__fu_read["_fu_read"]
                                CSRRegister4_read["read"]
                                CSRRegister4_write["write"]
-                               CSRRegister4__fu_read["_fu_read"]
                            end
                        end
                        subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"]
                            DoubleCounterCSR1_increment["increment"]
                            subgraph CSRRegister5["register_low CSRRegister"]
-                               CSRRegister5__fu_read["_fu_read"]
                                CSRRegister5_read["read"]
                                CSRRegister5_write["write"]
+                               CSRRegister5__fu_read["_fu_read"]
                            end
                            subgraph CSRRegister6["register_high CSRRegister"]
                                CSRRegister6_write["write"]
-                               CSRRegister6__fu_read["_fu_read"]
                                CSRRegister6_read["read"]
+                               CSRRegister6__fu_read["_fu_read"]
                            end
                        end
                    end
@@ -434,8 +434,8 @@
                            RegAllocation_RegAllocation["RegAllocation"]
                        end
                        subgraph FIFO11["rename_out_buf FIFO"]
-                           FIFO11_write["write"]
                            FIFO11_read["read"]
+                           FIFO11_write["write"]
                        end
                        subgraph Renaming["renaming Renaming"]
                            Renaming_Renaming["Renaming"]
@@ -469,25 +469,25 @@
                        ConnectTrans11_ConnectTrans["ConnectTrans"]
                    end
                    subgraph Retirement["retirement Retirement"]
-                       Retirement_Retirement_cond1["Retirement_cond1"]
                        Retirement_Retirement["Retirement"]
+                       Retirement_Retirement_cond1["Retirement_cond1"]
+                       Retirement_Retirement_cond0["Retirement_cond0"]
                        Retirement_Retirement1["Retirement"]
                        Retirement_Retirement2["Retirement"]
                        Retirement_Retirement3["Retirement"]
-                       Retirement_Retirement4["Retirement"]
-                       Retirement_Retirement_cond0["Retirement_cond0"]
                        Retirement_core_state["core_state"]
+                       Retirement_Retirement4["Retirement"]
                        subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"]
                            DoubleCounterCSR2_increment["increment"]
                            subgraph CSRRegister7["register_low CSRRegister"]
-                               CSRRegister7__fu_read["_fu_read"]
                                CSRRegister7_write["write"]
+                               CSRRegister7__fu_read["_fu_read"]
                                CSRRegister7_read["read"]
                            end
                            subgraph CSRRegister8["register_high CSRRegister"]
                                CSRRegister8_read["read"]
-                               CSRRegister8_write["write"]
                                CSRRegister8__fu_read["_fu_read"]
+                               CSRRegister8_write["write"]
                            end
                        end
                        subgraph HwCounter9["perf_instr_ret HwCounter"]
@@ -507,13 +507,13 @@
                end
            end
            subgraph TransactionManager["transactionManager TransactionManager"]
-               TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"]
-               TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"]
-               TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"]
+               TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"]
                TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"]
+               TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"]
+               TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"]
                TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"]
-               TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"]
-               TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"]
+               TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"]
+               TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"]
            end
        end
    Core_InitFreeRFFifo --> BasicFifo2_write
@@ -528,40 +528,40 @@
    SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1
    SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write
    SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request
-   ICache_ICache1 <--> HwCounter4__incr
+   ICache_ICache3 <--> HwCounter4__incr
    ICache_ICache2 <--> HwCounter3__incr
    ICache_ICache2 <--> HwCounter2__incr
    ICache_ICache2 <--> HwCounter1__incr
    ICache_ICache2 --> Forwarder3_write
-   ICache_ICache --> SimpleCommonBusCacheRefiller_start_refill
+   ICache_ICache1 --> SimpleCommonBusCacheRefiller_start_refill
+   ICache_ICache1 --> Forwarder2_write
    ICache_ICache --> Forwarder2_write
-   ICache_ICache3 --> Forwarder2_write
-   SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3
-   WishboneMasterAdapter_get_read_response --> ICache_ICache3
-   Serializer_Serializer --> ICache_ICache3
-   BasicFifo_read --> ICache_ICache3
-   WishboneMaster_result --> ICache_ICache3
-   Forwarder_read --> ICache_ICache3
-   Fetch_Fetch --> ICache_issue_req
-   Fetch_Fetch <--> HwCounter__incr
-   Fetch_Fetch <--> LatencyMeasurer__start
-   Fetch_Fetch --> FIFO1_write
-   Fetch_Fetch --> FIFO2_write
-   Fetch_Fetch --> BasicFifo3_write
-   BasicFifo3_read --> Fetch_Fetch1
-   ICache_accept_res --> Fetch_Fetch1
-   FIFO2_read --> Fetch_Fetch1
-   Fetch_Fetch1 <--> LatencyMeasurer__stop
-   FIFO1_read --> Fetch_Fetch1
-   Fetch_Fetch1 --> HwExpHistogram__add
-   Forwarder3_read --> Fetch_Fetch1
-   Fetch_Fetch1 --> MethodProduct_method
+   SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache
+   WishboneMasterAdapter_get_read_response --> ICache_ICache
+   Serializer_Serializer --> ICache_ICache
+   BasicFifo_read --> ICache_ICache
+   WishboneMaster_result --> ICache_ICache
+   Forwarder_read --> ICache_ICache
+   Fetch_Fetch1 --> ICache_issue_req
+   Fetch_Fetch1 <--> HwCounter__incr
+   Fetch_Fetch1 <--> LatencyMeasurer__start
+   Fetch_Fetch1 --> FIFO1_write
+   Fetch_Fetch1 --> FIFO2_write
+   Fetch_Fetch1 --> BasicFifo3_write
+   BasicFifo3_read --> Fetch_Fetch
+   ICache_accept_res --> Fetch_Fetch
+   FIFO2_read --> Fetch_Fetch
+   Fetch_Fetch <--> LatencyMeasurer__stop
+   FIFO1_read --> Fetch_Fetch
+   Fetch_Fetch --> HwExpHistogram__add
+   Forwarder3_read --> Fetch_Fetch
+   Fetch_Fetch --> MethodProduct_method
    AdapterTrans_AdapterTrans_method --> MethodProduct_method
-   Fetch_Fetch1 --> FIFO_write
+   Fetch_Fetch --> FIFO_write
    AdapterTrans_AdapterTrans_method --> FIFO_write
-   Fetch_Fetch1 --> MethodMap_method
+   Fetch_Fetch --> MethodMap_method
    AdapterTrans_AdapterTrans_method --> MethodMap_method
-   Fetch_Fetch1 <--> CoreInstructionCounter_increment
+   Fetch_Fetch <--> CoreInstructionCounter_increment
    AdapterTrans_AdapterTrans_method <--> CoreInstructionCounter_increment
    FIFO_read --> DecodeStage_DecodeStage
    DecodeStage_DecodeStage <--> HwCounter8__incr
@@ -579,17 +579,17 @@
    ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start
    ROBAllocation_ROBAllocation --> FIFO3_write
    ROBAllocation_ROBAllocation --> FIFO12_write
-   FIFO12_read --> RSSelection_RSSelection1
-   RSSelection_RSSelection1 --> Forwarder8_write
+   FIFO12_read --> RSSelection_RSSelection3
+   RSSelection_RSSelection3 --> Forwarder8_write
    Forwarder8_read --> RSSelection_RSSelection
-   Forwarder8_read --> RSSelection_RSSelection3
+   Forwarder8_read --> RSSelection_RSSelection1
    Forwarder8_read --> RSSelection_RSSelection2
    RSFuncBlock_select --> RSSelection_RSSelection
    RS_select --> RSSelection_RSSelection
    RSSelection_RSSelection --> FIFO13_write
-   RSSelection_RSSelection3 --> FIFO13_write
+   RSSelection_RSSelection1 --> FIFO13_write
    RSSelection_RSSelection2 --> FIFO13_write
-   RSSelection_RSSelection3 <--> LSUDummy_select
+   RSSelection_RSSelection1 <--> LSUDummy_select
    RSSelection_RSSelection2 <--> CSRUnit_select
    FIFO13_read --> RSInsertion_RSInsertion
    RegisterFile_read1 --> RSInsertion_RSInsertion
@@ -606,7 +606,7 @@
    Collector2_method --> ConnectTrans11_ConnectTrans
    Forwarder7_read --> ConnectTrans11_ConnectTrans
    ConnectTrans11_ConnectTrans --> Fetch_resume
-   Retirement_Retirement4 --> Fetch_resume
+   Retirement_Retirement3 --> Fetch_resume
    Collector_method --> ResultAnnouncement_ResultAnnouncement
    Forwarder4_read --> ResultAnnouncement_ResultAnnouncement
    ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done
@@ -616,7 +616,7 @@
    ResultAnnouncement_ResultAnnouncement --> RS_update
    ResultAnnouncement_ResultAnnouncement --> LSUDummy_update
    ResultAnnouncement_ResultAnnouncement --> CSRUnit_update
-   RS_RS2 --> WakeupSelect_WakeupSelect
+   RS_RS --> WakeupSelect_WakeupSelect
    RS_take --> WakeupSelect_WakeupSelect
    RS_take --> WakeupSelect1_WakeupSelect
    RS_take --> WakeupSelect2_WakeupSelect
@@ -624,10 +624,10 @@
    RS_take --> WakeupSelect4_WakeupSelect
    WakeupSelect_WakeupSelect --> AluFuncUnit_issue
    WakeupSelect_WakeupSelect --> FIFO4_write
-   RS_RS --> WakeupSelect1_WakeupSelect
+   RS_RS4 --> WakeupSelect1_WakeupSelect
    WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue
    WakeupSelect1_WakeupSelect --> FIFO5_write
-   RS_RS4 --> WakeupSelect2_WakeupSelect
+   RS_RS2 --> WakeupSelect2_WakeupSelect
    WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue
    WakeupSelect2_WakeupSelect <--> HwCounter5__incr
    WakeupSelect2_WakeupSelect <--> HwCounter6__incr
@@ -639,10 +639,10 @@
    ConnectTrans3_ConnectTrans --> BasicFifo4_write
    WakeupSelect2_WakeupSelect --> FIFO7_write
    WakeupSelect2_WakeupSelect --> FIFO6_write
-   RS_RS1 --> WakeupSelect3_WakeupSelect
+   RS_RS3 --> WakeupSelect3_WakeupSelect
    WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue
    WakeupSelect3_WakeupSelect --> FIFO8_write
-   RS_RS3 --> WakeupSelect4_WakeupSelect
+   RS_RS1 --> WakeupSelect4_WakeupSelect
    WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue
    ConnectTrans4_ConnectTrans --> Forwarder5_write
    ConnectTrans5_ConnectTrans --> Forwarder5_write
@@ -661,11 +661,11 @@
    CSRRegister2_read --> ConnectTrans8_ConnectTrans
    ConnectTrans8_ConnectTrans --> BasicFifo5_write
    LSUDummy_LSUDummy1 --> Forwarder6_write
-   TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write
-   TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write
-   TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write
+   TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write
+   TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write
+   TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write
+   TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write
    TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write
-   TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write
    CSRRegister__fu_read --> CSRUnit_CSRUnit
    CSRUnit_CSRUnit --> CSRRegister__fu_write
    CSRRegister1__fu_read --> CSRUnit_CSRUnit
@@ -687,21 +687,21 @@
    LSUDummy_get_result --> ConnectTrans2_ConnectTrans
    Forwarder6_read --> ConnectTrans2_ConnectTrans
    CSRUnit_get_result --> ConnectTrans3_ConnectTrans
-   MethodTryProduct_MethodTryProduct2 --> PrivilegedFuncUnit_precommit
-   MethodTryProduct_MethodTryProduct2 <--> InterruptController_mret
-   MethodTryProduct_MethodTryProduct --> LSUDummy_precommit
-   MethodTryProduct_MethodTryProduct1 --> CSRUnit_precommit
+   MethodTryProduct_MethodTryProduct --> PrivilegedFuncUnit_precommit
+   MethodTryProduct_MethodTryProduct <--> InterruptController_mret
+   MethodTryProduct_MethodTryProduct1 --> LSUDummy_precommit
+   MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit
    ConnectTrans9_ConnectTrans --> Forwarder7_write
    ConnectTrans10_ConnectTrans --> Forwarder7_write
    BasicFifo5_read --> ConnectTrans9_ConnectTrans
    CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans
-   ReorderBuffer_peek --> Retirement_Retirement2
-   ReorderBuffer_peek --> Retirement_Retirement3
+   ReorderBuffer_peek --> Retirement_Retirement4
+   ReorderBuffer_peek --> Retirement_Retirement1
    ReorderBuffer_peek --> Retirement_Retirement
    ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1
    ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0
-   Retirement_Retirement2 --> MethodTryProduct_method
-   ExceptionCauseRegister_get --> Retirement_Retirement3
+   Retirement_Retirement4 --> MethodTryProduct_method
+   ExceptionCauseRegister_get --> Retirement_Retirement1
    ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1
    ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0
    Retirement_Retirement <--> ReorderBuffer_retire
@@ -724,8 +724,8 @@
    Retirement_Retirement --> RegisterFile_free
    TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free
    TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free
-   CSRRegister1_read --> Retirement_Retirement4
-   Retirement_Retirement4 <--> ExceptionCauseRegister_clear
+   CSRRegister1_read --> Retirement_Retirement3
+   Retirement_Retirement3 <--> ExceptionCauseRegister_clear
    GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment
    CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters
    GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write
@@ -737,41 +737,35 @@
    CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters
    GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write
    AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt
-   TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0
-   WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy
-   Serializer1_Serializer1 --> TransactionManager_accept_cond0_LSUDummy
-   BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy
-   BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy
-   WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy
-   WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy
-   Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy
-   Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy
-   TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy2
-   TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy2
-   LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy
-   LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy
-   TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1
-   TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read
-   TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3
-   TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write
-   TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write
-   TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request
-   TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request
-   TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy
-   TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy
+   TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy
+   TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy
    TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy
-   TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue
-   TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue
+   TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue
+   TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue
    TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue
-   TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2
-   TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0
-   TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write
-   TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer2
-   TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1
-   WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy
-   Serializer1_Serializer --> TransactionManager_accept_cond1_LSUDummy
-   TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1
-   TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement1
+   TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1
+   TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read
+   TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer
+   TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write
+   TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write
+   TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request
+   TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request
+   TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy2
+   TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2
+   LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1
+   LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0
+   TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1
+   WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1
+   Serializer1_Serializer2 --> TransactionManager_LSUDummy_accept_cond1
+   BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1
+   BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0
+   WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1
+   WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0
+   Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1
+   Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0
+   TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2
+   TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement2
+   TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2
    TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write
    TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write
    TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write
@@ -779,6 +773,9 @@
    TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry
    TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry
    TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1
+   TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0
+   WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0
+   Serializer1_Serializer1 --> TransactionManager_LSUDummy_accept_cond0
    TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0
    TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit
    TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment
@@ -787,3 +784,6 @@
    CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0
    TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write
    TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr
+   TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0
+   TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write
+   TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3
diff --git a/api.html b/api.html
index 1253a360c..02e172adc 100644
--- a/api.html
+++ b/api.html
@@ -259,7 +259,7 @@ <h2>transactron<a class="headerlink" href="#transactron" title="Permalink to thi
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/assumptions.html b/assumptions.html
index 0cecb73f5..6b09ae243 100644
--- a/assumptions.html
+++ b/assumptions.html
@@ -104,7 +104,7 @@ <h1>List of assumptions made during development<a class="headerlink" href="#list
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/auto_graph.html b/auto_graph.html
index 6a7c82749..b6fd7b590 100644
--- a/auto_graph.html
+++ b/auto_graph.html
@@ -83,15 +83,15 @@
     subgraph TransactionModule[&quot;TransactionModule&quot;]
         subgraph CoreTestElaboratable[&quot;elaboratable CoreTestElaboratable&quot;]
             subgraph Core[&quot;core Core&quot;]
-                Core_InitFreeRFFifo[&quot;InitFreeRFFifo&quot;]
                 Core_DiscardBranchVerify[&quot;DiscardBranchVerify&quot;]
+                Core_InitFreeRFFifo[&quot;InitFreeRFFifo&quot;]
                 subgraph WishboneMaster[&quot;wb_master_instr WishboneMaster&quot;]
                     WishboneMaster_WishboneMaster[&quot;WishboneMaster&quot;]
-                    WishboneMaster_result[&quot;result&quot;]
                     WishboneMaster_request[&quot;request&quot;]
+                    WishboneMaster_result[&quot;result&quot;]
                     subgraph Forwarder[&quot;result Forwarder&quot;]
-                        Forwarder_write[&quot;write&quot;]
                         Forwarder_read[&quot;read&quot;]
+                        Forwarder_write[&quot;write&quot;]
                     end
                 end
                 subgraph WishboneMaster1[&quot;wb_master_data WishboneMaster&quot;]
@@ -99,8 +99,8 @@
                     WishboneMaster1_request[&quot;request&quot;]
                     WishboneMaster1_result[&quot;result&quot;]
                     subgraph Forwarder1[&quot;result Forwarder&quot;]
-                        Forwarder1_read[&quot;read&quot;]
                         Forwarder1_write[&quot;write&quot;]
+                        Forwarder1_read[&quot;read&quot;]
                     end
                 end
                 subgraph WishboneMasterAdapter[&quot;bus_master_instr_adapter WishboneMasterAdapter&quot;]
@@ -110,8 +110,8 @@
                         Serializer_Serializer[&quot;Serializer&quot;]
                         Serializer_Serializer1[&quot;Serializer&quot;]
                         subgraph BasicFifo[&quot;pending_requests BasicFifo&quot;]
-                            BasicFifo_write[&quot;write&quot;]
                             BasicFifo_read[&quot;read&quot;]
+                            BasicFifo_write[&quot;write&quot;]
                         end
                     end
                 end
@@ -126,18 +126,18 @@
                         Serializer1_Serializer2[&quot;Serializer&quot;]
                         Serializer1_Serializer3[&quot;Serializer&quot;]
                         subgraph BasicFifo1[&quot;pending_requests BasicFifo&quot;]
-                            BasicFifo1_write[&quot;write&quot;]
                             BasicFifo1_read[&quot;read&quot;]
+                            BasicFifo1_write[&quot;write&quot;]
                         end
                     end
                 end
                 subgraph CoreInstructionCounter[&quot;core_counter CoreInstructionCounter&quot;]
-                    CoreInstructionCounter_increment[&quot;increment&quot;]
                     CoreInstructionCounter_decrement[&quot;decrement&quot;]
+                    CoreInstructionCounter_increment[&quot;increment&quot;]
                 end
                 subgraph FIFO[&quot;fifo_fetch FIFO&quot;]
-                    FIFO_read[&quot;read&quot;]
                     FIFO_write[&quot;write&quot;]
+                    FIFO_read[&quot;read&quot;]
                 end
                 subgraph MethodMap[&quot;core_counter_increment_discard_map MethodMap&quot;]
                     MethodMap_method[&quot;method&quot;]
@@ -151,16 +151,16 @@
                 end
                 subgraph SimpleCommonBusCacheRefiller[&quot;icache_refiller SimpleCommonBusCacheRefiller&quot;]
                     SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller[&quot;SimpleCommonBusCacheRefiller&quot;]
-                    SimpleCommonBusCacheRefiller_accept_refill[&quot;accept_refill&quot;]
                     SimpleCommonBusCacheRefiller_start_refill[&quot;start_refill&quot;]
+                    SimpleCommonBusCacheRefiller_accept_refill[&quot;accept_refill&quot;]
                     subgraph Forwarder2[&quot;address_fwd Forwarder&quot;]
-                        Forwarder2_write[&quot;write&quot;]
                         Forwarder2_read[&quot;read&quot;]
+                        Forwarder2_write[&quot;write&quot;]
                     end
                 end
                 subgraph ICache[&quot;icache ICache&quot;]
-                    ICache_ICache[&quot;ICache&quot;]
                     ICache_accept_res[&quot;accept_res&quot;]
+                    ICache_ICache[&quot;ICache&quot;]
                     ICache_ICache1[&quot;ICache&quot;]
                     ICache_ICache2[&quot;ICache&quot;]
                     ICache_issue_req[&quot;issue_req&quot;]
@@ -181,19 +181,19 @@
                         HwCounter4__incr[&quot;_incr&quot;]
                     end
                     subgraph LatencyMeasurer[&quot;req_latency LatencyMeasurer&quot;]
-                        LatencyMeasurer__start[&quot;_start&quot;]
                         LatencyMeasurer__stop[&quot;_stop&quot;]
+                        LatencyMeasurer__start[&quot;_start&quot;]
                         subgraph HwExpHistogram[&quot;histogram HwExpHistogram&quot;]
                             HwExpHistogram__add[&quot;_add&quot;]
                         end
                         subgraph FIFO1[&quot;fifo FIFO&quot;]
-                            FIFO1_write[&quot;write&quot;]
                             FIFO1_read[&quot;read&quot;]
+                            FIFO1_write[&quot;write&quot;]
                         end
                     end
                     subgraph FIFO2[&quot;req_fifo FIFO&quot;]
-                        FIFO2_read[&quot;read&quot;]
                         FIFO2_write[&quot;write&quot;]
+                        FIFO2_read[&quot;read&quot;]
                     end
                     subgraph Forwarder3[&quot;res_fwd Forwarder&quot;]
                         Forwarder3_write[&quot;write&quot;]
@@ -204,50 +204,50 @@
                     FRAT_rename[&quot;rename&quot;]
                 end
                 subgraph RRAT[&quot;RRAT RRAT&quot;]
-                    RRAT_commit[&quot;commit&quot;]
                     RRAT_peek[&quot;peek&quot;]
+                    RRAT_commit[&quot;commit&quot;]
                 end
                 subgraph RegisterFile[&quot;RF RegisterFile&quot;]
+                    RegisterFile_read2[&quot;read2&quot;]
                     RegisterFile_read1[&quot;read1&quot;]
-                    RegisterFile_free[&quot;free&quot;]
                     RegisterFile_write[&quot;write&quot;]
-                    RegisterFile_read2[&quot;read2&quot;]
+                    RegisterFile_free[&quot;free&quot;]
                 end
                 subgraph ReorderBuffer[&quot;ROB ReorderBuffer&quot;]
                     ReorderBuffer_put[&quot;put&quot;]
-                    ReorderBuffer_get_indices[&quot;get_indices&quot;]
-                    ReorderBuffer_mark_done[&quot;mark_done&quot;]
                     ReorderBuffer_retire[&quot;retire&quot;]
+                    ReorderBuffer_mark_done[&quot;mark_done&quot;]
+                    ReorderBuffer_get_indices[&quot;get_indices&quot;]
                     ReorderBuffer_peek[&quot;peek&quot;]
                     subgraph LatencyMeasurer1[&quot;perf_rob_wait_time LatencyMeasurer&quot;]
-                        LatencyMeasurer1__stop[&quot;_stop&quot;]
                         LatencyMeasurer1__start[&quot;_start&quot;]
+                        LatencyMeasurer1__stop[&quot;_stop&quot;]
                         subgraph HwExpHistogram1[&quot;histogram HwExpHistogram&quot;]
                             HwExpHistogram1__add[&quot;_add&quot;]
                         end
                         subgraph FIFO3[&quot;fifo FIFO&quot;]
-                            FIFO3_read[&quot;read&quot;]
                             FIFO3_write[&quot;write&quot;]
+                            FIFO3_read[&quot;read&quot;]
                         end
                     end
                 end
                 subgraph Fetch[&quot;fetch Fetch&quot;]
                     Fetch_Fetch[&quot;Fetch&quot;]
                     Fetch_Fetch1[&quot;Fetch&quot;]
-                    Fetch_resume[&quot;resume&quot;]
                     Fetch_stall_exception[&quot;stall_exception&quot;]
+                    Fetch_resume[&quot;resume&quot;]
                     subgraph BasicFifo3[&quot;fetch_target_queue BasicFifo&quot;]
                         BasicFifo3_read[&quot;read&quot;]
                         BasicFifo3_write[&quot;write&quot;]
                     end
                 end
                 subgraph ExceptionCauseRegister[&quot;exception_cause_register ExceptionCauseRegister&quot;]
+                    ExceptionCauseRegister_clear[&quot;clear&quot;]
                     ExceptionCauseRegister_get[&quot;get&quot;]
                     ExceptionCauseRegister_report[&quot;report&quot;]
-                    ExceptionCauseRegister_clear[&quot;clear&quot;]
                     subgraph BasicFifo4[&quot;fu_report_fifo BasicFifo&quot;]
-                        BasicFifo4_read[&quot;read&quot;]
                         BasicFifo4_write[&quot;write&quot;]
+                        BasicFifo4_read[&quot;read&quot;]
                     end
                     subgraph ConnectTrans[&quot;report_connector ConnectTrans&quot;]
                         ConnectTrans_ConnectTrans[&quot;ConnectTrans&quot;]
@@ -257,8 +257,8 @@
                     subgraph Collector[&quot;result_collector Collector&quot;]
                         Collector_method[&quot;method&quot;]
                         subgraph Forwarder4[&quot;forwarder Forwarder&quot;]
-                            Forwarder4_read[&quot;read&quot;]
                             Forwarder4_write[&quot;write&quot;]
+                            Forwarder4_read[&quot;read&quot;]
                         end
                         subgraph ManyToOneConnectTrans[&quot;connect ManyToOneConnectTrans&quot;]
                             subgraph ConnectTrans1[&quot;ManyToOneConnectTrans_input_0 ConnectTrans&quot;]
@@ -276,15 +276,15 @@
                         MethodProduct1_method[&quot;method&quot;]
                     end
                     subgraph RSFuncBlock[&quot;rs_block_0 RSFuncBlock&quot;]
-                        RSFuncBlock_get_result[&quot;get_result&quot;]
-                        RSFuncBlock_select[&quot;select&quot;]
                         RSFuncBlock_insert[&quot;insert&quot;]
                         RSFuncBlock_update[&quot;update&quot;]
+                        RSFuncBlock_get_result[&quot;get_result&quot;]
+                        RSFuncBlock_select[&quot;select&quot;]
                         subgraph RS[&quot;rs RS&quot;]
                             RS_update[&quot;update&quot;]
+                            RS_select[&quot;select&quot;]
                             RS_RS[&quot;RS&quot;]
                             RS_RS1[&quot;RS&quot;]
-                            RS_select[&quot;select&quot;]
                             RS_take[&quot;take&quot;]
                             RS_RS2[&quot;RS&quot;]
                             RS_RS3[&quot;RS&quot;]
@@ -292,11 +292,11 @@
                             RS_insert[&quot;insert&quot;]
                         end
                         subgraph AluFuncUnit[&quot;func_unit_0 AluFuncUnit&quot;]
-                            AluFuncUnit_issue[&quot;issue&quot;]
                             AluFuncUnit_accept[&quot;accept&quot;]
+                            AluFuncUnit_issue[&quot;issue&quot;]
                             subgraph FIFO4[&quot;fifo FIFO&quot;]
-                                FIFO4_read[&quot;read&quot;]
                                 FIFO4_write[&quot;write&quot;]
+                                FIFO4_read[&quot;read&quot;]
                             end
                         end
                         subgraph WakeupSelect[&quot;wakeup_select_0 WakeupSelect&quot;]
@@ -306,16 +306,16 @@
                             ShiftFuncUnit_issue[&quot;issue&quot;]
                             ShiftFuncUnit_accept[&quot;accept&quot;]
                             subgraph FIFO5[&quot;fifo FIFO&quot;]
-                                FIFO5_read[&quot;read&quot;]
                                 FIFO5_write[&quot;write&quot;]
+                                FIFO5_read[&quot;read&quot;]
                             end
                         end
                         subgraph WakeupSelect1[&quot;wakeup_select_1 WakeupSelect&quot;]
                             WakeupSelect1_WakeupSelect[&quot;WakeupSelect&quot;]
                         end
                         subgraph JumpBranchFuncUnit[&quot;func_unit_2 JumpBranchFuncUnit&quot;]
-                            JumpBranchFuncUnit_accept[&quot;accept&quot;]
                             JumpBranchFuncUnit_issue[&quot;issue&quot;]
+                            JumpBranchFuncUnit_accept[&quot;accept&quot;]
                             subgraph FIFO6[&quot;fifo_branch_resolved FIFO&quot;]
                                 FIFO6_read[&quot;read&quot;]
                                 FIFO6_write[&quot;write&quot;]
@@ -330,16 +330,16 @@
                                 HwCounter7__incr[&quot;_incr&quot;]
                             end
                             subgraph FIFO7[&quot;fifo_res FIFO&quot;]
-                                FIFO7_write[&quot;write&quot;]
                                 FIFO7_read[&quot;read&quot;]
+                                FIFO7_write[&quot;write&quot;]
                             end
                         end
                         subgraph WakeupSelect2[&quot;wakeup_select_2 WakeupSelect&quot;]
                             WakeupSelect2_WakeupSelect[&quot;WakeupSelect&quot;]
                         end
                         subgraph ExceptionFuncUnit[&quot;func_unit_3 ExceptionFuncUnit&quot;]
-                            ExceptionFuncUnit_issue[&quot;issue&quot;]
                             ExceptionFuncUnit_accept[&quot;accept&quot;]
+                            ExceptionFuncUnit_issue[&quot;issue&quot;]
                             subgraph FIFO8[&quot;fifo FIFO&quot;]
                                 FIFO8_read[&quot;read&quot;]
                                 FIFO8_write[&quot;write&quot;]
@@ -353,8 +353,8 @@
                             PrivilegedFuncUnit_precommit[&quot;precommit&quot;]
                             PrivilegedFuncUnit_issue[&quot;issue&quot;]
                             subgraph BasicFifo5[&quot;fetch_resume_fifo BasicFifo&quot;]
-                                BasicFifo5_read[&quot;read&quot;]
                                 BasicFifo5_write[&quot;write&quot;]
+                                BasicFifo5_read[&quot;read&quot;]
                             end
                         end
                         subgraph WakeupSelect4[&quot;wakeup_select_4 WakeupSelect&quot;]
@@ -363,8 +363,8 @@
                         subgraph Collector1[&quot;collector Collector&quot;]
                             Collector1_method[&quot;method&quot;]
                             subgraph Forwarder5[&quot;forwarder Forwarder&quot;]
-                                Forwarder5_write[&quot;write&quot;]
                                 Forwarder5_read[&quot;read&quot;]
+                                Forwarder5_write[&quot;write&quot;]
                             end
                             subgraph ManyToOneConnectTrans1[&quot;connect ManyToOneConnectTrans&quot;]
                                 subgraph ConnectTrans4[&quot;ManyToOneConnectTrans_input_0 ConnectTrans&quot;]
@@ -386,36 +386,36 @@
                         end
                     end
                     subgraph LSUDummy[&quot;rs_block_1 LSUDummy&quot;]
-                        LSUDummy_insert[&quot;insert&quot;]
-                        LSUDummy_precommit[&quot;precommit&quot;]
                         LSUDummy_get_result[&quot;get_result&quot;]
-                        LSUDummy_update[&quot;update&quot;]
                         LSUDummy_LSUDummy[&quot;LSUDummy&quot;]
                         LSUDummy_LSUDummy1[&quot;LSUDummy&quot;]
-                        LSUDummy_LSUDummy2[&quot;LSUDummy&quot;]
+                        LSUDummy_insert[&quot;insert&quot;]
                         LSUDummy_select[&quot;select&quot;]
+                        LSUDummy_LSUDummy2[&quot;LSUDummy&quot;]
+                        LSUDummy_update[&quot;update&quot;]
+                        LSUDummy_precommit[&quot;precommit&quot;]
                         subgraph Forwarder6[&quot;forwarder Forwarder&quot;]
                             Forwarder6_write[&quot;write&quot;]
                             Forwarder6_read[&quot;read&quot;]
                         end
                         subgraph LSURequester[&quot;requester LSURequester&quot;]
-                            LSURequester_accept[&quot;accept&quot;]
-                            LSURequester_accept_cond0[&quot;accept_cond0&quot;]
                             LSURequester_issue_cond2[&quot;issue_cond2&quot;]
-                            LSURequester_issue[&quot;issue&quot;]
-                            LSURequester_accept_cond1[&quot;accept_cond1&quot;]
-                            LSURequester_issue_cond0[&quot;issue_cond0&quot;]
+                            LSURequester_accept_cond0[&quot;accept_cond0&quot;]
                             LSURequester_issue_cond1[&quot;issue_cond1&quot;]
+                            LSURequester_issue_cond0[&quot;issue_cond0&quot;]
+                            LSURequester_accept[&quot;accept&quot;]
+                            LSURequester_accept_cond1[&quot;accept_cond1&quot;]
+                            LSURequester_issue[&quot;issue&quot;]
                         end
                     end
                     subgraph CSRUnit[&quot;rs_block_2 CSRUnit&quot;]
-                        CSRUnit_select[&quot;select&quot;]
-                        CSRUnit_CSRUnit[&quot;CSRUnit&quot;]
-                        CSRUnit_update[&quot;update&quot;]
-                        CSRUnit_precommit[&quot;precommit&quot;]
                         CSRUnit_get_result[&quot;get_result&quot;]
+                        CSRUnit_CSRUnit[&quot;CSRUnit&quot;]
                         CSRUnit_insert[&quot;insert&quot;]
+                        CSRUnit_select[&quot;select&quot;]
                         CSRUnit_fetch_resume[&quot;fetch_resume&quot;]
+                        CSRUnit_update[&quot;update&quot;]
+                        CSRUnit_precommit[&quot;precommit&quot;]
                     end
                     subgraph MethodTryProduct[&quot;InstructionPrecommitKey_unifier MethodTryProduct&quot;]
                         MethodTryProduct_MethodTryProduct[&quot;MethodTryProduct&quot;]
@@ -444,8 +444,8 @@
                 end
                 subgraph InterruptController[&quot;interrupt_controller InterruptController&quot;]
                     InterruptController_report_interrupt[&quot;report_interrupt&quot;]
-                    InterruptController_entry[&quot;entry&quot;]
                     InterruptController_mret[&quot;mret&quot;]
+                    InterruptController_entry[&quot;entry&quot;]
                 end
                 subgraph GenericCSRRegisters[&quot;csr_generic GenericCSRRegisters&quot;]
                     GenericCSRRegisters_GenericCSRRegisters[&quot;GenericCSRRegisters&quot;]
@@ -456,41 +456,41 @@
                             CSRRegister_write[&quot;write&quot;]
                         end
                         subgraph CSRRegister1[&quot;mtvec CSRRegister&quot;]
-                            CSRRegister1__fu_read[&quot;_fu_read&quot;]
-                            CSRRegister1_read[&quot;read&quot;]
                             CSRRegister1__fu_write[&quot;_fu_write&quot;]
+                            CSRRegister1_read[&quot;read&quot;]
+                            CSRRegister1__fu_read[&quot;_fu_read&quot;]
                         end
                         subgraph CSRRegister2[&quot;mepc CSRRegister&quot;]
                             CSRRegister2_read[&quot;read&quot;]
+                            CSRRegister2__fu_read[&quot;_fu_read&quot;]
                             CSRRegister2_write[&quot;write&quot;]
                             CSRRegister2__fu_write[&quot;_fu_write&quot;]
-                            CSRRegister2__fu_read[&quot;_fu_read&quot;]
                         end
                     end
                     subgraph DoubleCounterCSR[&quot;csr_cycle DoubleCounterCSR&quot;]
                         DoubleCounterCSR_increment[&quot;increment&quot;]
                         subgraph CSRRegister3[&quot;register_low CSRRegister&quot;]
-                            CSRRegister3__fu_read[&quot;_fu_read&quot;]
-                            CSRRegister3_write[&quot;write&quot;]
                             CSRRegister3_read[&quot;read&quot;]
+                            CSRRegister3_write[&quot;write&quot;]
+                            CSRRegister3__fu_read[&quot;_fu_read&quot;]
                         end
                         subgraph CSRRegister4[&quot;register_high CSRRegister&quot;]
+                            CSRRegister4__fu_read[&quot;_fu_read&quot;]
                             CSRRegister4_read[&quot;read&quot;]
                             CSRRegister4_write[&quot;write&quot;]
-                            CSRRegister4__fu_read[&quot;_fu_read&quot;]
                         end
                     end
                     subgraph DoubleCounterCSR1[&quot;csr_time DoubleCounterCSR&quot;]
                         DoubleCounterCSR1_increment[&quot;increment&quot;]
                         subgraph CSRRegister5[&quot;register_low CSRRegister&quot;]
-                            CSRRegister5__fu_read[&quot;_fu_read&quot;]
                             CSRRegister5_read[&quot;read&quot;]
                             CSRRegister5_write[&quot;write&quot;]
+                            CSRRegister5__fu_read[&quot;_fu_read&quot;]
                         end
                         subgraph CSRRegister6[&quot;register_high CSRRegister&quot;]
                             CSRRegister6_write[&quot;write&quot;]
-                            CSRRegister6__fu_read[&quot;_fu_read&quot;]
                             CSRRegister6_read[&quot;read&quot;]
+                            CSRRegister6__fu_read[&quot;_fu_read&quot;]
                         end
                     end
                 end
@@ -513,8 +513,8 @@
                         RegAllocation_RegAllocation[&quot;RegAllocation&quot;]
                     end
                     subgraph FIFO11[&quot;rename_out_buf FIFO&quot;]
-                        FIFO11_write[&quot;write&quot;]
                         FIFO11_read[&quot;read&quot;]
+                        FIFO11_write[&quot;write&quot;]
                     end
                     subgraph Renaming[&quot;renaming Renaming&quot;]
                         Renaming_Renaming[&quot;Renaming&quot;]
@@ -548,25 +548,25 @@
                     ConnectTrans11_ConnectTrans[&quot;ConnectTrans&quot;]
                 end
                 subgraph Retirement[&quot;retirement Retirement&quot;]
-                    Retirement_Retirement_cond1[&quot;Retirement_cond1&quot;]
                     Retirement_Retirement[&quot;Retirement&quot;]
+                    Retirement_Retirement_cond1[&quot;Retirement_cond1&quot;]
+                    Retirement_Retirement_cond0[&quot;Retirement_cond0&quot;]
                     Retirement_Retirement1[&quot;Retirement&quot;]
                     Retirement_Retirement2[&quot;Retirement&quot;]
                     Retirement_Retirement3[&quot;Retirement&quot;]
-                    Retirement_Retirement4[&quot;Retirement&quot;]
-                    Retirement_Retirement_cond0[&quot;Retirement_cond0&quot;]
                     Retirement_core_state[&quot;core_state&quot;]
+                    Retirement_Retirement4[&quot;Retirement&quot;]
                     subgraph DoubleCounterCSR2[&quot;instret_csr DoubleCounterCSR&quot;]
                         DoubleCounterCSR2_increment[&quot;increment&quot;]
                         subgraph CSRRegister7[&quot;register_low CSRRegister&quot;]
-                            CSRRegister7__fu_read[&quot;_fu_read&quot;]
                             CSRRegister7_write[&quot;write&quot;]
+                            CSRRegister7__fu_read[&quot;_fu_read&quot;]
                             CSRRegister7_read[&quot;read&quot;]
                         end
                         subgraph CSRRegister8[&quot;register_high CSRRegister&quot;]
                             CSRRegister8_read[&quot;read&quot;]
-                            CSRRegister8_write[&quot;write&quot;]
                             CSRRegister8__fu_read[&quot;_fu_read&quot;]
+                            CSRRegister8_write[&quot;write&quot;]
                         end
                     end
                     subgraph HwCounter9[&quot;perf_instr_ret HwCounter&quot;]
@@ -586,13 +586,13 @@
             end
         end
         subgraph TransactionManager[&quot;transactionManager TransactionManager&quot;]
-            TransactionManager_issue_cond2_LSUDummy[&quot;issue_cond2_LSUDummy&quot;]
-            TransactionManager_accept_cond0_LSUDummy[&quot;accept_cond0_LSUDummy&quot;]
-            TransactionManager_issue_cond0_LSUDummy[&quot;issue_cond0_LSUDummy&quot;]
+            TransactionManager_LSUDummy_accept_cond1[&quot;LSUDummy_accept_cond1&quot;]
             TransactionManager_Retirement_Retirement_cond1[&quot;Retirement_Retirement_cond1&quot;]
+            TransactionManager_issue_cond0_LSUDummy[&quot;issue_cond0_LSUDummy&quot;]
+            TransactionManager_LSUDummy_issue_cond2[&quot;LSUDummy_issue_cond2&quot;]
             TransactionManager_Retirement_Retirement_cond0[&quot;Retirement_Retirement_cond0&quot;]
-            TransactionManager_issue_cond1_LSUDummy[&quot;issue_cond1_LSUDummy&quot;]
-            TransactionManager_accept_cond1_LSUDummy[&quot;accept_cond1_LSUDummy&quot;]
+            TransactionManager_LSUDummy_issue_cond1[&quot;LSUDummy_issue_cond1&quot;]
+            TransactionManager_LSUDummy_accept_cond0[&quot;LSUDummy_accept_cond0&quot;]
         end
     end
 Core_InitFreeRFFifo --&gt; BasicFifo2_write
@@ -607,40 +607,40 @@
 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; Serializer_Serializer1
 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; BasicFifo_write
 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; WishboneMaster_request
-ICache_ICache1 &lt;--&gt; HwCounter4__incr
+ICache_ICache3 &lt;--&gt; HwCounter4__incr
 ICache_ICache2 &lt;--&gt; HwCounter3__incr
 ICache_ICache2 &lt;--&gt; HwCounter2__incr
 ICache_ICache2 &lt;--&gt; HwCounter1__incr
 ICache_ICache2 --&gt; Forwarder3_write
-ICache_ICache --&gt; SimpleCommonBusCacheRefiller_start_refill
+ICache_ICache1 --&gt; SimpleCommonBusCacheRefiller_start_refill
+ICache_ICache1 --&gt; Forwarder2_write
 ICache_ICache --&gt; Forwarder2_write
-ICache_ICache3 --&gt; Forwarder2_write
-SimpleCommonBusCacheRefiller_accept_refill --&gt; ICache_ICache3
-WishboneMasterAdapter_get_read_response --&gt; ICache_ICache3
-Serializer_Serializer --&gt; ICache_ICache3
-BasicFifo_read --&gt; ICache_ICache3
-WishboneMaster_result --&gt; ICache_ICache3
-Forwarder_read --&gt; ICache_ICache3
-Fetch_Fetch --&gt; ICache_issue_req
-Fetch_Fetch &lt;--&gt; HwCounter__incr
-Fetch_Fetch &lt;--&gt; LatencyMeasurer__start
-Fetch_Fetch --&gt; FIFO1_write
-Fetch_Fetch --&gt; FIFO2_write
-Fetch_Fetch --&gt; BasicFifo3_write
-BasicFifo3_read --&gt; Fetch_Fetch1
-ICache_accept_res --&gt; Fetch_Fetch1
-FIFO2_read --&gt; Fetch_Fetch1
-Fetch_Fetch1 &lt;--&gt; LatencyMeasurer__stop
-FIFO1_read --&gt; Fetch_Fetch1
-Fetch_Fetch1 --&gt; HwExpHistogram__add
-Forwarder3_read --&gt; Fetch_Fetch1
-Fetch_Fetch1 --&gt; MethodProduct_method
+SimpleCommonBusCacheRefiller_accept_refill --&gt; ICache_ICache
+WishboneMasterAdapter_get_read_response --&gt; ICache_ICache
+Serializer_Serializer --&gt; ICache_ICache
+BasicFifo_read --&gt; ICache_ICache
+WishboneMaster_result --&gt; ICache_ICache
+Forwarder_read --&gt; ICache_ICache
+Fetch_Fetch1 --&gt; ICache_issue_req
+Fetch_Fetch1 &lt;--&gt; HwCounter__incr
+Fetch_Fetch1 &lt;--&gt; LatencyMeasurer__start
+Fetch_Fetch1 --&gt; FIFO1_write
+Fetch_Fetch1 --&gt; FIFO2_write
+Fetch_Fetch1 --&gt; BasicFifo3_write
+BasicFifo3_read --&gt; Fetch_Fetch
+ICache_accept_res --&gt; Fetch_Fetch
+FIFO2_read --&gt; Fetch_Fetch
+Fetch_Fetch &lt;--&gt; LatencyMeasurer__stop
+FIFO1_read --&gt; Fetch_Fetch
+Fetch_Fetch --&gt; HwExpHistogram__add
+Forwarder3_read --&gt; Fetch_Fetch
+Fetch_Fetch --&gt; MethodProduct_method
 AdapterTrans_AdapterTrans_method --&gt; MethodProduct_method
-Fetch_Fetch1 --&gt; FIFO_write
+Fetch_Fetch --&gt; FIFO_write
 AdapterTrans_AdapterTrans_method --&gt; FIFO_write
-Fetch_Fetch1 --&gt; MethodMap_method
+Fetch_Fetch --&gt; MethodMap_method
 AdapterTrans_AdapterTrans_method --&gt; MethodMap_method
-Fetch_Fetch1 &lt;--&gt; CoreInstructionCounter_increment
+Fetch_Fetch &lt;--&gt; CoreInstructionCounter_increment
 AdapterTrans_AdapterTrans_method &lt;--&gt; CoreInstructionCounter_increment
 FIFO_read --&gt; DecodeStage_DecodeStage
 DecodeStage_DecodeStage &lt;--&gt; HwCounter8__incr
@@ -658,17 +658,17 @@
 ROBAllocation_ROBAllocation &lt;--&gt; LatencyMeasurer1__start
 ROBAllocation_ROBAllocation --&gt; FIFO3_write
 ROBAllocation_ROBAllocation --&gt; FIFO12_write
-FIFO12_read --&gt; RSSelection_RSSelection1
-RSSelection_RSSelection1 --&gt; Forwarder8_write
+FIFO12_read --&gt; RSSelection_RSSelection3
+RSSelection_RSSelection3 --&gt; Forwarder8_write
 Forwarder8_read --&gt; RSSelection_RSSelection
-Forwarder8_read --&gt; RSSelection_RSSelection3
+Forwarder8_read --&gt; RSSelection_RSSelection1
 Forwarder8_read --&gt; RSSelection_RSSelection2
 RSFuncBlock_select --&gt; RSSelection_RSSelection
 RS_select --&gt; RSSelection_RSSelection
 RSSelection_RSSelection --&gt; FIFO13_write
-RSSelection_RSSelection3 --&gt; FIFO13_write
+RSSelection_RSSelection1 --&gt; FIFO13_write
 RSSelection_RSSelection2 --&gt; FIFO13_write
-RSSelection_RSSelection3 &lt;--&gt; LSUDummy_select
+RSSelection_RSSelection1 &lt;--&gt; LSUDummy_select
 RSSelection_RSSelection2 &lt;--&gt; CSRUnit_select
 FIFO13_read --&gt; RSInsertion_RSInsertion
 RegisterFile_read1 --&gt; RSInsertion_RSInsertion
@@ -685,7 +685,7 @@
 Collector2_method --&gt; ConnectTrans11_ConnectTrans
 Forwarder7_read --&gt; ConnectTrans11_ConnectTrans
 ConnectTrans11_ConnectTrans --&gt; Fetch_resume
-Retirement_Retirement4 --&gt; Fetch_resume
+Retirement_Retirement3 --&gt; Fetch_resume
 Collector_method --&gt; ResultAnnouncement_ResultAnnouncement
 Forwarder4_read --&gt; ResultAnnouncement_ResultAnnouncement
 ResultAnnouncement_ResultAnnouncement --&gt; ReorderBuffer_mark_done
@@ -695,7 +695,7 @@
 ResultAnnouncement_ResultAnnouncement --&gt; RS_update
 ResultAnnouncement_ResultAnnouncement --&gt; LSUDummy_update
 ResultAnnouncement_ResultAnnouncement --&gt; CSRUnit_update
-RS_RS2 --&gt; WakeupSelect_WakeupSelect
+RS_RS --&gt; WakeupSelect_WakeupSelect
 RS_take --&gt; WakeupSelect_WakeupSelect
 RS_take --&gt; WakeupSelect1_WakeupSelect
 RS_take --&gt; WakeupSelect2_WakeupSelect
@@ -703,10 +703,10 @@
 RS_take --&gt; WakeupSelect4_WakeupSelect
 WakeupSelect_WakeupSelect --&gt; AluFuncUnit_issue
 WakeupSelect_WakeupSelect --&gt; FIFO4_write
-RS_RS --&gt; WakeupSelect1_WakeupSelect
+RS_RS4 --&gt; WakeupSelect1_WakeupSelect
 WakeupSelect1_WakeupSelect --&gt; ShiftFuncUnit_issue
 WakeupSelect1_WakeupSelect --&gt; FIFO5_write
-RS_RS4 --&gt; WakeupSelect2_WakeupSelect
+RS_RS2 --&gt; WakeupSelect2_WakeupSelect
 WakeupSelect2_WakeupSelect --&gt; JumpBranchFuncUnit_issue
 WakeupSelect2_WakeupSelect &lt;--&gt; HwCounter5__incr
 WakeupSelect2_WakeupSelect &lt;--&gt; HwCounter6__incr
@@ -718,10 +718,10 @@
 ConnectTrans3_ConnectTrans --&gt; BasicFifo4_write
 WakeupSelect2_WakeupSelect --&gt; FIFO7_write
 WakeupSelect2_WakeupSelect --&gt; FIFO6_write
-RS_RS1 --&gt; WakeupSelect3_WakeupSelect
+RS_RS3 --&gt; WakeupSelect3_WakeupSelect
 WakeupSelect3_WakeupSelect --&gt; ExceptionFuncUnit_issue
 WakeupSelect3_WakeupSelect --&gt; FIFO8_write
-RS_RS3 --&gt; WakeupSelect4_WakeupSelect
+RS_RS1 --&gt; WakeupSelect4_WakeupSelect
 WakeupSelect4_WakeupSelect --&gt; PrivilegedFuncUnit_issue
 ConnectTrans4_ConnectTrans --&gt; Forwarder5_write
 ConnectTrans5_ConnectTrans --&gt; Forwarder5_write
@@ -740,11 +740,11 @@
 CSRRegister2_read --&gt; ConnectTrans8_ConnectTrans
 ConnectTrans8_ConnectTrans --&gt; BasicFifo5_write
 LSUDummy_LSUDummy1 --&gt; Forwarder6_write
-TransactionManager_accept_cond0_LSUDummy --&gt; Forwarder6_write
-TransactionManager_issue_cond1_LSUDummy --&gt; Forwarder6_write
-TransactionManager_issue_cond2_LSUDummy --&gt; Forwarder6_write
+TransactionManager_LSUDummy_issue_cond1 --&gt; Forwarder6_write
+TransactionManager_LSUDummy_accept_cond1 --&gt; Forwarder6_write
+TransactionManager_LSUDummy_issue_cond2 --&gt; Forwarder6_write
+TransactionManager_LSUDummy_accept_cond0 --&gt; Forwarder6_write
 TransactionManager_issue_cond0_LSUDummy --&gt; Forwarder6_write
-TransactionManager_accept_cond1_LSUDummy --&gt; Forwarder6_write
 CSRRegister__fu_read --&gt; CSRUnit_CSRUnit
 CSRUnit_CSRUnit --&gt; CSRRegister__fu_write
 CSRRegister1__fu_read --&gt; CSRUnit_CSRUnit
@@ -766,21 +766,21 @@
 LSUDummy_get_result --&gt; ConnectTrans2_ConnectTrans
 Forwarder6_read --&gt; ConnectTrans2_ConnectTrans
 CSRUnit_get_result --&gt; ConnectTrans3_ConnectTrans
-MethodTryProduct_MethodTryProduct2 --&gt; PrivilegedFuncUnit_precommit
-MethodTryProduct_MethodTryProduct2 &lt;--&gt; InterruptController_mret
-MethodTryProduct_MethodTryProduct --&gt; LSUDummy_precommit
-MethodTryProduct_MethodTryProduct1 --&gt; CSRUnit_precommit
+MethodTryProduct_MethodTryProduct --&gt; PrivilegedFuncUnit_precommit
+MethodTryProduct_MethodTryProduct &lt;--&gt; InterruptController_mret
+MethodTryProduct_MethodTryProduct1 --&gt; LSUDummy_precommit
+MethodTryProduct_MethodTryProduct2 --&gt; CSRUnit_precommit
 ConnectTrans9_ConnectTrans --&gt; Forwarder7_write
 ConnectTrans10_ConnectTrans --&gt; Forwarder7_write
 BasicFifo5_read --&gt; ConnectTrans9_ConnectTrans
 CSRUnit_fetch_resume --&gt; ConnectTrans10_ConnectTrans
-ReorderBuffer_peek --&gt; Retirement_Retirement2
-ReorderBuffer_peek --&gt; Retirement_Retirement3
+ReorderBuffer_peek --&gt; Retirement_Retirement4
+ReorderBuffer_peek --&gt; Retirement_Retirement1
 ReorderBuffer_peek --&gt; Retirement_Retirement
 ReorderBuffer_peek --&gt; TransactionManager_Retirement_Retirement_cond1
 ReorderBuffer_peek --&gt; TransactionManager_Retirement_Retirement_cond0
-Retirement_Retirement2 --&gt; MethodTryProduct_method
-ExceptionCauseRegister_get --&gt; Retirement_Retirement3
+Retirement_Retirement4 --&gt; MethodTryProduct_method
+ExceptionCauseRegister_get --&gt; Retirement_Retirement1
 ExceptionCauseRegister_get --&gt; TransactionManager_Retirement_Retirement_cond1
 ExceptionCauseRegister_get --&gt; TransactionManager_Retirement_Retirement_cond0
 Retirement_Retirement &lt;--&gt; ReorderBuffer_retire
@@ -803,8 +803,8 @@
 Retirement_Retirement --&gt; RegisterFile_free
 TransactionManager_Retirement_Retirement_cond1 --&gt; RegisterFile_free
 TransactionManager_Retirement_Retirement_cond0 --&gt; RegisterFile_free
-CSRRegister1_read --&gt; Retirement_Retirement4
-Retirement_Retirement4 &lt;--&gt; ExceptionCauseRegister_clear
+CSRRegister1_read --&gt; Retirement_Retirement3
+Retirement_Retirement3 &lt;--&gt; ExceptionCauseRegister_clear
 GenericCSRRegisters_GenericCSRRegisters &lt;--&gt; DoubleCounterCSR_increment
 CSRRegister3_read --&gt; GenericCSRRegisters_GenericCSRRegisters
 GenericCSRRegisters_GenericCSRRegisters --&gt; CSRRegister3_write
@@ -816,41 +816,35 @@
 CSRRegister6_read --&gt; GenericCSRRegisters_GenericCSRRegisters
 GenericCSRRegisters_GenericCSRRegisters --&gt; CSRRegister6_write
 AdapterTrans1_AdapterTrans_report_interrupt &lt;--&gt; InterruptController_report_interrupt
-TransactionManager_accept_cond0_LSUDummy &lt;--&gt; LSURequester_accept_cond0
-WishboneMasterAdapter1_get_write_response --&gt; TransactionManager_accept_cond0_LSUDummy
-Serializer1_Serializer1 --&gt; TransactionManager_accept_cond0_LSUDummy
-BasicFifo1_read --&gt; TransactionManager_accept_cond0_LSUDummy
-BasicFifo1_read --&gt; TransactionManager_accept_cond1_LSUDummy
-WishboneMaster1_result --&gt; TransactionManager_accept_cond0_LSUDummy
-WishboneMaster1_result --&gt; TransactionManager_accept_cond1_LSUDummy
-Forwarder1_read --&gt; TransactionManager_accept_cond0_LSUDummy
-Forwarder1_read --&gt; TransactionManager_accept_cond1_LSUDummy
-TransactionManager_accept_cond0_LSUDummy &lt;--&gt; LSUDummy_LSUDummy2
-TransactionManager_accept_cond1_LSUDummy &lt;--&gt; LSUDummy_LSUDummy2
-LSURequester_accept --&gt; TransactionManager_accept_cond0_LSUDummy
-LSURequester_accept --&gt; TransactionManager_accept_cond1_LSUDummy
-TransactionManager_issue_cond1_LSUDummy &lt;--&gt; LSURequester_issue_cond1
-TransactionManager_issue_cond1_LSUDummy --&gt; WishboneMasterAdapter1_request_read
-TransactionManager_issue_cond1_LSUDummy --&gt; Serializer1_Serializer3
-TransactionManager_issue_cond1_LSUDummy --&gt; BasicFifo1_write
-TransactionManager_issue_cond0_LSUDummy --&gt; BasicFifo1_write
-TransactionManager_issue_cond1_LSUDummy --&gt; WishboneMaster1_request
-TransactionManager_issue_cond0_LSUDummy --&gt; WishboneMaster1_request
-TransactionManager_issue_cond1_LSUDummy &lt;--&gt; LSUDummy_LSUDummy
-TransactionManager_issue_cond2_LSUDummy &lt;--&gt; LSUDummy_LSUDummy
+TransactionManager_LSUDummy_issue_cond1 &lt;--&gt; LSUDummy_LSUDummy
+TransactionManager_LSUDummy_issue_cond2 &lt;--&gt; LSUDummy_LSUDummy
 TransactionManager_issue_cond0_LSUDummy &lt;--&gt; LSUDummy_LSUDummy
-TransactionManager_issue_cond1_LSUDummy --&gt; LSURequester_issue
-TransactionManager_issue_cond2_LSUDummy --&gt; LSURequester_issue
+TransactionManager_LSUDummy_issue_cond1 --&gt; LSURequester_issue
+TransactionManager_LSUDummy_issue_cond2 --&gt; LSURequester_issue
 TransactionManager_issue_cond0_LSUDummy --&gt; LSURequester_issue
-TransactionManager_issue_cond2_LSUDummy &lt;--&gt; LSURequester_issue_cond2
-TransactionManager_issue_cond0_LSUDummy &lt;--&gt; LSURequester_issue_cond0
-TransactionManager_issue_cond0_LSUDummy --&gt; WishboneMasterAdapter1_request_write
-TransactionManager_issue_cond0_LSUDummy --&gt; Serializer1_Serializer2
-TransactionManager_accept_cond1_LSUDummy &lt;--&gt; LSURequester_accept_cond1
-WishboneMasterAdapter1_get_read_response --&gt; TransactionManager_accept_cond1_LSUDummy
-Serializer1_Serializer --&gt; TransactionManager_accept_cond1_LSUDummy
-TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; Retirement_Retirement1
-TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; Retirement_Retirement1
+TransactionManager_LSUDummy_issue_cond1 &lt;--&gt; LSURequester_issue_cond1
+TransactionManager_LSUDummy_issue_cond1 --&gt; WishboneMasterAdapter1_request_read
+TransactionManager_LSUDummy_issue_cond1 --&gt; Serializer1_Serializer
+TransactionManager_LSUDummy_issue_cond1 --&gt; BasicFifo1_write
+TransactionManager_issue_cond0_LSUDummy --&gt; BasicFifo1_write
+TransactionManager_LSUDummy_issue_cond1 --&gt; WishboneMaster1_request
+TransactionManager_issue_cond0_LSUDummy --&gt; WishboneMaster1_request
+TransactionManager_LSUDummy_accept_cond1 &lt;--&gt; LSUDummy_LSUDummy2
+TransactionManager_LSUDummy_accept_cond0 &lt;--&gt; LSUDummy_LSUDummy2
+LSURequester_accept --&gt; TransactionManager_LSUDummy_accept_cond1
+LSURequester_accept --&gt; TransactionManager_LSUDummy_accept_cond0
+TransactionManager_LSUDummy_accept_cond1 &lt;--&gt; LSURequester_accept_cond1
+WishboneMasterAdapter1_get_read_response --&gt; TransactionManager_LSUDummy_accept_cond1
+Serializer1_Serializer2 --&gt; TransactionManager_LSUDummy_accept_cond1
+BasicFifo1_read --&gt; TransactionManager_LSUDummy_accept_cond1
+BasicFifo1_read --&gt; TransactionManager_LSUDummy_accept_cond0
+WishboneMaster1_result --&gt; TransactionManager_LSUDummy_accept_cond1
+WishboneMaster1_result --&gt; TransactionManager_LSUDummy_accept_cond0
+Forwarder1_read --&gt; TransactionManager_LSUDummy_accept_cond1
+Forwarder1_read --&gt; TransactionManager_LSUDummy_accept_cond0
+TransactionManager_LSUDummy_issue_cond2 &lt;--&gt; LSURequester_issue_cond2
+TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; Retirement_Retirement2
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; Retirement_Retirement2
 TransactionManager_Retirement_Retirement_cond1 --&gt; CSRRegister_write
 TransactionManager_Retirement_Retirement_cond0 --&gt; CSRRegister_write
 TransactionManager_Retirement_Retirement_cond1 --&gt; CSRRegister2_write
@@ -858,6 +852,9 @@
 TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; InterruptController_entry
 TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; InterruptController_entry
 TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; Retirement_Retirement_cond1
+TransactionManager_LSUDummy_accept_cond0 &lt;--&gt; LSURequester_accept_cond0
+WishboneMasterAdapter1_get_write_response --&gt; TransactionManager_LSUDummy_accept_cond0
+Serializer1_Serializer1 --&gt; TransactionManager_LSUDummy_accept_cond0
 TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; Retirement_Retirement_cond0
 TransactionManager_Retirement_Retirement_cond0 --&gt; RRAT_commit
 TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; DoubleCounterCSR2_increment
@@ -866,6 +863,9 @@
 CSRRegister8_read --&gt; TransactionManager_Retirement_Retirement_cond0
 TransactionManager_Retirement_Retirement_cond0 --&gt; CSRRegister8_write
 TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; HwCounter9__incr
+TransactionManager_issue_cond0_LSUDummy &lt;--&gt; LSURequester_issue_cond0
+TransactionManager_issue_cond0_LSUDummy --&gt; WishboneMasterAdapter1_request_write
+TransactionManager_issue_cond0_LSUDummy --&gt; Serializer1_Serializer3
         </div>
 
            </div>
@@ -876,7 +876,7 @@
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/components/icache.html b/components/icache.html
index aa05823bc..78e774ac4 100644
--- a/components/icache.html
+++ b/components/icache.html
@@ -131,7 +131,7 @@ <h2>Address mapping example<a class="headerlink" href="#address-mapping-example"
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.backend.html b/coreblocks.backend.html
index 24991ac0e..8ca620e2a 100644
--- a/coreblocks.backend.html
+++ b/coreblocks.backend.html
@@ -165,7 +165,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.cache.html b/coreblocks.cache.html
index e2de09b93..5e0ad8827 100644
--- a/coreblocks.cache.html
+++ b/coreblocks.cache.html
@@ -241,7 +241,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html
index 0d465d639..5faee2cdd 100644
--- a/coreblocks.core_structs.html
+++ b/coreblocks.core_structs.html
@@ -157,7 +157,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html
index 99a89bada..3635b343a 100644
--- a/coreblocks.frontend.decoder.html
+++ b/coreblocks.frontend.decoder.html
@@ -1721,7 +1721,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html
index d910ad1e6..3bd653edc 100644
--- a/coreblocks.frontend.fetch.html
+++ b/coreblocks.frontend.fetch.html
@@ -161,7 +161,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html
index 5d8f76344..63eb31300 100644
--- a/coreblocks.frontend.html
+++ b/coreblocks.frontend.html
@@ -125,7 +125,7 @@ <h2>Subpackages<a class="headerlink" href="#subpackages" title="Permalink to thi
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html
index 2b0a043fe..dbec25617 100644
--- a/coreblocks.func_blocks.fu.html
+++ b/coreblocks.func_blocks.fu.html
@@ -867,7 +867,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html
index 4c6b81ed3..2a566cce9 100644
--- a/coreblocks.func_blocks.fu.unsigned_multiplication.html
+++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html
@@ -238,7 +238,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html
index 42bdee983..5f1f0f611 100644
--- a/coreblocks.func_blocks.html
+++ b/coreblocks.func_blocks.html
@@ -148,7 +148,7 @@ <h2>Subpackages<a class="headerlink" href="#subpackages" title="Permalink to thi
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html
index 948a43281..4191a28ce 100644
--- a/coreblocks.func_blocks.interface.html
+++ b/coreblocks.func_blocks.interface.html
@@ -169,7 +169,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.func_blocks.lsu.html b/coreblocks.func_blocks.lsu.html
index 715ca2b02..223142a7a 100644
--- a/coreblocks.func_blocks.lsu.html
+++ b/coreblocks.func_blocks.lsu.html
@@ -248,7 +248,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.html b/coreblocks.html
index 7dfd22868..2d7ee919c 100644
--- a/coreblocks.html
+++ b/coreblocks.html
@@ -255,7 +255,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.params.html b/coreblocks.params.html
index 18033bef4..364719de0 100644
--- a/coreblocks.params.html
+++ b/coreblocks.params.html
@@ -317,6 +317,11 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 <span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">imm</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">funct3</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs1</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs2</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.BTypeInstr.__init__" title="Permalink to this definition"></a></dt>
 <dd></dd></dl>
 
+<dl class="py method">
+<dt class="sig sig-object py" id="coreblocks.params.instr.BTypeInstr.encode">
+<em class="property"><span class="pre">static</span><span class="w"> </span></em><span class="sig-name descname"><span class="pre">encode</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">imm</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">funct3</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs1</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs2</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.BTypeInstr.encode" title="Permalink to this definition"></a></dt>
+<dd></dd></dl>
+
 <dl class="py method">
 <dt class="sig sig-object py" id="coreblocks.params.instr.BTypeInstr.pack">
 <span class="sig-name descname"><span class="pre">pack</span></span><span class="sig-paren">(</span><span class="sig-paren">)</span> <span class="sig-return"><span class="sig-return-icon">&#x2192;</span> <span class="sig-return-typehint"><span class="pre">Value</span></span></span><a class="headerlink" href="#coreblocks.params.instr.BTypeInstr.pack" title="Permalink to this definition"></a></dt>
@@ -344,6 +349,11 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 <span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rd</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">funct3</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs1</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">imm</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.ITypeInstr.__init__" title="Permalink to this definition"></a></dt>
 <dd></dd></dl>
 
+<dl class="py method">
+<dt class="sig sig-object py" id="coreblocks.params.instr.ITypeInstr.encode">
+<em class="property"><span class="pre">static</span><span class="w"> </span></em><span class="sig-name descname"><span class="pre">encode</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rd</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">funct3</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs1</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">imm</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.ITypeInstr.encode" title="Permalink to this definition"></a></dt>
+<dd></dd></dl>
+
 <dl class="py method">
 <dt class="sig sig-object py" id="coreblocks.params.instr.ITypeInstr.pack">
 <span class="sig-name descname"><span class="pre">pack</span></span><span class="sig-paren">(</span><span class="sig-paren">)</span> <span class="sig-return"><span class="sig-return-icon">&#x2192;</span> <span class="sig-return-typehint"><span class="pre">Value</span></span></span><a class="headerlink" href="#coreblocks.params.instr.ITypeInstr.pack" title="Permalink to this definition"></a></dt>
@@ -360,6 +370,11 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 <span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.IllegalInstr.__init__" title="Permalink to this definition"></a></dt>
 <dd></dd></dl>
 
+<dl class="py method">
+<dt class="sig sig-object py" id="coreblocks.params.instr.IllegalInstr.encode">
+<em class="property"><span class="pre">static</span><span class="w"> </span></em><span class="sig-name descname"><span class="pre">encode</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rd</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">imm</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.IllegalInstr.encode" title="Permalink to this definition"></a></dt>
+<dd></dd></dl>
+
 <dl class="py method">
 <dt class="sig sig-object py" id="coreblocks.params.instr.IllegalInstr.pack">
 <span class="sig-name descname"><span class="pre">pack</span></span><span class="sig-paren">(</span><span class="sig-paren">)</span> <span class="sig-return"><span class="sig-return-icon">&#x2192;</span> <span class="sig-return-typehint"><span class="pre">Value</span></span></span><a class="headerlink" href="#coreblocks.params.instr.IllegalInstr.pack" title="Permalink to this definition"></a></dt>
@@ -376,6 +391,11 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 <span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rd</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">imm</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.JTypeInstr.__init__" title="Permalink to this definition"></a></dt>
 <dd></dd></dl>
 
+<dl class="py method">
+<dt class="sig sig-object py" id="coreblocks.params.instr.JTypeInstr.encode">
+<em class="property"><span class="pre">static</span><span class="w"> </span></em><span class="sig-name descname"><span class="pre">encode</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rd</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">imm</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.JTypeInstr.encode" title="Permalink to this definition"></a></dt>
+<dd></dd></dl>
+
 <dl class="py method">
 <dt class="sig sig-object py" id="coreblocks.params.instr.JTypeInstr.pack">
 <span class="sig-name descname"><span class="pre">pack</span></span><span class="sig-paren">(</span><span class="sig-paren">)</span> <span class="sig-return"><span class="sig-return-icon">&#x2192;</span> <span class="sig-return-typehint"><span class="pre">Value</span></span></span><a class="headerlink" href="#coreblocks.params.instr.JTypeInstr.pack" title="Permalink to this definition"></a></dt>
@@ -392,6 +412,11 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 <span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rd</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">funct3</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs1</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs2</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">funct7</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.RTypeInstr.__init__" title="Permalink to this definition"></a></dt>
 <dd></dd></dl>
 
+<dl class="py method">
+<dt class="sig sig-object py" id="coreblocks.params.instr.RTypeInstr.encode">
+<em class="property"><span class="pre">static</span><span class="w"> </span></em><span class="sig-name descname"><span class="pre">encode</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rd</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">funct3</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs1</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs2</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">funct7</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.RTypeInstr.encode" title="Permalink to this definition"></a></dt>
+<dd></dd></dl>
+
 <dl class="py method">
 <dt class="sig sig-object py" id="coreblocks.params.instr.RTypeInstr.pack">
 <span class="sig-name descname"><span class="pre">pack</span></span><span class="sig-paren">(</span><span class="sig-paren">)</span> <span class="sig-return"><span class="sig-return-icon">&#x2192;</span> <span class="sig-return-typehint"><span class="pre">Value</span></span></span><a class="headerlink" href="#coreblocks.params.instr.RTypeInstr.pack" title="Permalink to this definition"></a></dt>
@@ -408,6 +433,11 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 <span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">imm</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">funct3</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs1</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs2</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.STypeInstr.__init__" title="Permalink to this definition"></a></dt>
 <dd></dd></dl>
 
+<dl class="py method">
+<dt class="sig sig-object py" id="coreblocks.params.instr.STypeInstr.encode">
+<em class="property"><span class="pre">static</span><span class="w"> </span></em><span class="sig-name descname"><span class="pre">encode</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">imm</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">funct3</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs1</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rs2</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.STypeInstr.encode" title="Permalink to this definition"></a></dt>
+<dd></dd></dl>
+
 <dl class="py method">
 <dt class="sig sig-object py" id="coreblocks.params.instr.STypeInstr.pack">
 <span class="sig-name descname"><span class="pre">pack</span></span><span class="sig-paren">(</span><span class="sig-paren">)</span> <span class="sig-return"><span class="sig-return-icon">&#x2192;</span> <span class="sig-return-typehint"><span class="pre">Value</span></span></span><a class="headerlink" href="#coreblocks.params.instr.STypeInstr.pack" title="Permalink to this definition"></a></dt>
@@ -424,6 +454,11 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 <span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rd</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">imm</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">amaranth.hdl._ast.Value</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">int</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">enum.Enum</span><span class="w"> </span><span class="p"><span class="pre">|</span></span><span class="w"> </span><span class="pre">amaranth.hdl._ast.ValueCastable</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.UTypeInstr.__init__" title="Permalink to this definition"></a></dt>
 <dd></dd></dl>
 
+<dl class="py method">
+<dt class="sig sig-object py" id="coreblocks.params.instr.UTypeInstr.encode">
+<em class="property"><span class="pre">static</span><span class="w"> </span></em><span class="sig-name descname"><span class="pre">encode</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">opcode</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">rd</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em>, <em class="sig-param"><span class="n"><span class="pre">imm</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><span class="pre">int</span></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.params.instr.UTypeInstr.encode" title="Permalink to this definition"></a></dt>
+<dd></dd></dl>
+
 <dl class="py method">
 <dt class="sig sig-object py" id="coreblocks.params.instr.UTypeInstr.pack">
 <span class="sig-name descname"><span class="pre">pack</span></span><span class="sig-paren">(</span><span class="sig-paren">)</span> <span class="sig-return"><span class="sig-return-icon">&#x2192;</span> <span class="sig-return-typehint"><span class="pre">Value</span></span></span><a class="headerlink" href="#coreblocks.params.instr.UTypeInstr.pack" title="Permalink to this definition"></a></dt>
@@ -719,7 +754,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html
index 42234c558..745fe25e8 100644
--- a/coreblocks.peripherals.html
+++ b/coreblocks.peripherals.html
@@ -746,7 +746,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html
index d9c11b7c8..13b086ef7 100644
--- a/coreblocks.priv.csr.html
+++ b/coreblocks.priv.csr.html
@@ -327,7 +327,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.priv.html b/coreblocks.priv.html
index 07e3b1106..63b60be71 100644
--- a/coreblocks.priv.html
+++ b/coreblocks.priv.html
@@ -123,7 +123,7 @@ <h2>Subpackages<a class="headerlink" href="#subpackages" title="Permalink to thi
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html
index a169e7c37..391b14c5e 100644
--- a/coreblocks.priv.traps.html
+++ b/coreblocks.priv.traps.html
@@ -171,7 +171,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html
index c699016e8..c229e558b 100644
--- a/coreblocks.scheduler.html
+++ b/coreblocks.scheduler.html
@@ -191,7 +191,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/current-graph.html b/current-graph.html
index 8086e9ded..2dc845472 100644
--- a/current-graph.html
+++ b/current-graph.html
@@ -89,15 +89,15 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
     subgraph TransactionModule[&quot;TransactionModule&quot;]
         subgraph CoreTestElaboratable[&quot;elaboratable CoreTestElaboratable&quot;]
             subgraph Core[&quot;core Core&quot;]
-                Core_InitFreeRFFifo[&quot;InitFreeRFFifo&quot;]
                 Core_DiscardBranchVerify[&quot;DiscardBranchVerify&quot;]
+                Core_InitFreeRFFifo[&quot;InitFreeRFFifo&quot;]
                 subgraph WishboneMaster[&quot;wb_master_instr WishboneMaster&quot;]
                     WishboneMaster_WishboneMaster[&quot;WishboneMaster&quot;]
-                    WishboneMaster_result[&quot;result&quot;]
                     WishboneMaster_request[&quot;request&quot;]
+                    WishboneMaster_result[&quot;result&quot;]
                     subgraph Forwarder[&quot;result Forwarder&quot;]
-                        Forwarder_write[&quot;write&quot;]
                         Forwarder_read[&quot;read&quot;]
+                        Forwarder_write[&quot;write&quot;]
                     end
                 end
                 subgraph WishboneMaster1[&quot;wb_master_data WishboneMaster&quot;]
@@ -105,8 +105,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     WishboneMaster1_request[&quot;request&quot;]
                     WishboneMaster1_result[&quot;result&quot;]
                     subgraph Forwarder1[&quot;result Forwarder&quot;]
-                        Forwarder1_read[&quot;read&quot;]
                         Forwarder1_write[&quot;write&quot;]
+                        Forwarder1_read[&quot;read&quot;]
                     end
                 end
                 subgraph WishboneMasterAdapter[&quot;bus_master_instr_adapter WishboneMasterAdapter&quot;]
@@ -116,8 +116,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         Serializer_Serializer[&quot;Serializer&quot;]
                         Serializer_Serializer1[&quot;Serializer&quot;]
                         subgraph BasicFifo[&quot;pending_requests BasicFifo&quot;]
-                            BasicFifo_write[&quot;write&quot;]
                             BasicFifo_read[&quot;read&quot;]
+                            BasicFifo_write[&quot;write&quot;]
                         end
                     end
                 end
@@ -132,18 +132,18 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         Serializer1_Serializer2[&quot;Serializer&quot;]
                         Serializer1_Serializer3[&quot;Serializer&quot;]
                         subgraph BasicFifo1[&quot;pending_requests BasicFifo&quot;]
-                            BasicFifo1_write[&quot;write&quot;]
                             BasicFifo1_read[&quot;read&quot;]
+                            BasicFifo1_write[&quot;write&quot;]
                         end
                     end
                 end
                 subgraph CoreInstructionCounter[&quot;core_counter CoreInstructionCounter&quot;]
-                    CoreInstructionCounter_increment[&quot;increment&quot;]
                     CoreInstructionCounter_decrement[&quot;decrement&quot;]
+                    CoreInstructionCounter_increment[&quot;increment&quot;]
                 end
                 subgraph FIFO[&quot;fifo_fetch FIFO&quot;]
-                    FIFO_read[&quot;read&quot;]
                     FIFO_write[&quot;write&quot;]
+                    FIFO_read[&quot;read&quot;]
                 end
                 subgraph MethodMap[&quot;core_counter_increment_discard_map MethodMap&quot;]
                     MethodMap_method[&quot;method&quot;]
@@ -157,16 +157,16 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                 end
                 subgraph SimpleCommonBusCacheRefiller[&quot;icache_refiller SimpleCommonBusCacheRefiller&quot;]
                     SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller[&quot;SimpleCommonBusCacheRefiller&quot;]
-                    SimpleCommonBusCacheRefiller_accept_refill[&quot;accept_refill&quot;]
                     SimpleCommonBusCacheRefiller_start_refill[&quot;start_refill&quot;]
+                    SimpleCommonBusCacheRefiller_accept_refill[&quot;accept_refill&quot;]
                     subgraph Forwarder2[&quot;address_fwd Forwarder&quot;]
-                        Forwarder2_write[&quot;write&quot;]
                         Forwarder2_read[&quot;read&quot;]
+                        Forwarder2_write[&quot;write&quot;]
                     end
                 end
                 subgraph ICache[&quot;icache ICache&quot;]
-                    ICache_ICache[&quot;ICache&quot;]
                     ICache_accept_res[&quot;accept_res&quot;]
+                    ICache_ICache[&quot;ICache&quot;]
                     ICache_ICache1[&quot;ICache&quot;]
                     ICache_ICache2[&quot;ICache&quot;]
                     ICache_issue_req[&quot;issue_req&quot;]
@@ -187,19 +187,19 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         HwCounter4__incr[&quot;_incr&quot;]
                     end
                     subgraph LatencyMeasurer[&quot;req_latency LatencyMeasurer&quot;]
-                        LatencyMeasurer__start[&quot;_start&quot;]
                         LatencyMeasurer__stop[&quot;_stop&quot;]
+                        LatencyMeasurer__start[&quot;_start&quot;]
                         subgraph HwExpHistogram[&quot;histogram HwExpHistogram&quot;]
                             HwExpHistogram__add[&quot;_add&quot;]
                         end
                         subgraph FIFO1[&quot;fifo FIFO&quot;]
-                            FIFO1_write[&quot;write&quot;]
                             FIFO1_read[&quot;read&quot;]
+                            FIFO1_write[&quot;write&quot;]
                         end
                     end
                     subgraph FIFO2[&quot;req_fifo FIFO&quot;]
-                        FIFO2_read[&quot;read&quot;]
                         FIFO2_write[&quot;write&quot;]
+                        FIFO2_read[&quot;read&quot;]
                     end
                     subgraph Forwarder3[&quot;res_fwd Forwarder&quot;]
                         Forwarder3_write[&quot;write&quot;]
@@ -210,50 +210,50 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     FRAT_rename[&quot;rename&quot;]
                 end
                 subgraph RRAT[&quot;RRAT RRAT&quot;]
-                    RRAT_commit[&quot;commit&quot;]
                     RRAT_peek[&quot;peek&quot;]
+                    RRAT_commit[&quot;commit&quot;]
                 end
                 subgraph RegisterFile[&quot;RF RegisterFile&quot;]
+                    RegisterFile_read2[&quot;read2&quot;]
                     RegisterFile_read1[&quot;read1&quot;]
-                    RegisterFile_free[&quot;free&quot;]
                     RegisterFile_write[&quot;write&quot;]
-                    RegisterFile_read2[&quot;read2&quot;]
+                    RegisterFile_free[&quot;free&quot;]
                 end
                 subgraph ReorderBuffer[&quot;ROB ReorderBuffer&quot;]
                     ReorderBuffer_put[&quot;put&quot;]
-                    ReorderBuffer_get_indices[&quot;get_indices&quot;]
-                    ReorderBuffer_mark_done[&quot;mark_done&quot;]
                     ReorderBuffer_retire[&quot;retire&quot;]
+                    ReorderBuffer_mark_done[&quot;mark_done&quot;]
+                    ReorderBuffer_get_indices[&quot;get_indices&quot;]
                     ReorderBuffer_peek[&quot;peek&quot;]
                     subgraph LatencyMeasurer1[&quot;perf_rob_wait_time LatencyMeasurer&quot;]
-                        LatencyMeasurer1__stop[&quot;_stop&quot;]
                         LatencyMeasurer1__start[&quot;_start&quot;]
+                        LatencyMeasurer1__stop[&quot;_stop&quot;]
                         subgraph HwExpHistogram1[&quot;histogram HwExpHistogram&quot;]
                             HwExpHistogram1__add[&quot;_add&quot;]
                         end
                         subgraph FIFO3[&quot;fifo FIFO&quot;]
-                            FIFO3_read[&quot;read&quot;]
                             FIFO3_write[&quot;write&quot;]
+                            FIFO3_read[&quot;read&quot;]
                         end
                     end
                 end
                 subgraph Fetch[&quot;fetch Fetch&quot;]
                     Fetch_Fetch[&quot;Fetch&quot;]
                     Fetch_Fetch1[&quot;Fetch&quot;]
-                    Fetch_resume[&quot;resume&quot;]
                     Fetch_stall_exception[&quot;stall_exception&quot;]
+                    Fetch_resume[&quot;resume&quot;]
                     subgraph BasicFifo3[&quot;fetch_target_queue BasicFifo&quot;]
                         BasicFifo3_read[&quot;read&quot;]
                         BasicFifo3_write[&quot;write&quot;]
                     end
                 end
                 subgraph ExceptionCauseRegister[&quot;exception_cause_register ExceptionCauseRegister&quot;]
+                    ExceptionCauseRegister_clear[&quot;clear&quot;]
                     ExceptionCauseRegister_get[&quot;get&quot;]
                     ExceptionCauseRegister_report[&quot;report&quot;]
-                    ExceptionCauseRegister_clear[&quot;clear&quot;]
                     subgraph BasicFifo4[&quot;fu_report_fifo BasicFifo&quot;]
-                        BasicFifo4_read[&quot;read&quot;]
                         BasicFifo4_write[&quot;write&quot;]
+                        BasicFifo4_read[&quot;read&quot;]
                     end
                     subgraph ConnectTrans[&quot;report_connector ConnectTrans&quot;]
                         ConnectTrans_ConnectTrans[&quot;ConnectTrans&quot;]
@@ -263,8 +263,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     subgraph Collector[&quot;result_collector Collector&quot;]
                         Collector_method[&quot;method&quot;]
                         subgraph Forwarder4[&quot;forwarder Forwarder&quot;]
-                            Forwarder4_read[&quot;read&quot;]
                             Forwarder4_write[&quot;write&quot;]
+                            Forwarder4_read[&quot;read&quot;]
                         end
                         subgraph ManyToOneConnectTrans[&quot;connect ManyToOneConnectTrans&quot;]
                             subgraph ConnectTrans1[&quot;ManyToOneConnectTrans_input_0 ConnectTrans&quot;]
@@ -282,15 +282,15 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         MethodProduct1_method[&quot;method&quot;]
                     end
                     subgraph RSFuncBlock[&quot;rs_block_0 RSFuncBlock&quot;]
-                        RSFuncBlock_get_result[&quot;get_result&quot;]
-                        RSFuncBlock_select[&quot;select&quot;]
                         RSFuncBlock_insert[&quot;insert&quot;]
                         RSFuncBlock_update[&quot;update&quot;]
+                        RSFuncBlock_get_result[&quot;get_result&quot;]
+                        RSFuncBlock_select[&quot;select&quot;]
                         subgraph RS[&quot;rs RS&quot;]
                             RS_update[&quot;update&quot;]
+                            RS_select[&quot;select&quot;]
                             RS_RS[&quot;RS&quot;]
                             RS_RS1[&quot;RS&quot;]
-                            RS_select[&quot;select&quot;]
                             RS_take[&quot;take&quot;]
                             RS_RS2[&quot;RS&quot;]
                             RS_RS3[&quot;RS&quot;]
@@ -298,11 +298,11 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                             RS_insert[&quot;insert&quot;]
                         end
                         subgraph AluFuncUnit[&quot;func_unit_0 AluFuncUnit&quot;]
-                            AluFuncUnit_issue[&quot;issue&quot;]
                             AluFuncUnit_accept[&quot;accept&quot;]
+                            AluFuncUnit_issue[&quot;issue&quot;]
                             subgraph FIFO4[&quot;fifo FIFO&quot;]
-                                FIFO4_read[&quot;read&quot;]
                                 FIFO4_write[&quot;write&quot;]
+                                FIFO4_read[&quot;read&quot;]
                             end
                         end
                         subgraph WakeupSelect[&quot;wakeup_select_0 WakeupSelect&quot;]
@@ -312,16 +312,16 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                             ShiftFuncUnit_issue[&quot;issue&quot;]
                             ShiftFuncUnit_accept[&quot;accept&quot;]
                             subgraph FIFO5[&quot;fifo FIFO&quot;]
-                                FIFO5_read[&quot;read&quot;]
                                 FIFO5_write[&quot;write&quot;]
+                                FIFO5_read[&quot;read&quot;]
                             end
                         end
                         subgraph WakeupSelect1[&quot;wakeup_select_1 WakeupSelect&quot;]
                             WakeupSelect1_WakeupSelect[&quot;WakeupSelect&quot;]
                         end
                         subgraph JumpBranchFuncUnit[&quot;func_unit_2 JumpBranchFuncUnit&quot;]
-                            JumpBranchFuncUnit_accept[&quot;accept&quot;]
                             JumpBranchFuncUnit_issue[&quot;issue&quot;]
+                            JumpBranchFuncUnit_accept[&quot;accept&quot;]
                             subgraph FIFO6[&quot;fifo_branch_resolved FIFO&quot;]
                                 FIFO6_read[&quot;read&quot;]
                                 FIFO6_write[&quot;write&quot;]
@@ -336,16 +336,16 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                                 HwCounter7__incr[&quot;_incr&quot;]
                             end
                             subgraph FIFO7[&quot;fifo_res FIFO&quot;]
-                                FIFO7_write[&quot;write&quot;]
                                 FIFO7_read[&quot;read&quot;]
+                                FIFO7_write[&quot;write&quot;]
                             end
                         end
                         subgraph WakeupSelect2[&quot;wakeup_select_2 WakeupSelect&quot;]
                             WakeupSelect2_WakeupSelect[&quot;WakeupSelect&quot;]
                         end
                         subgraph ExceptionFuncUnit[&quot;func_unit_3 ExceptionFuncUnit&quot;]
-                            ExceptionFuncUnit_issue[&quot;issue&quot;]
                             ExceptionFuncUnit_accept[&quot;accept&quot;]
+                            ExceptionFuncUnit_issue[&quot;issue&quot;]
                             subgraph FIFO8[&quot;fifo FIFO&quot;]
                                 FIFO8_read[&quot;read&quot;]
                                 FIFO8_write[&quot;write&quot;]
@@ -359,8 +359,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                             PrivilegedFuncUnit_precommit[&quot;precommit&quot;]
                             PrivilegedFuncUnit_issue[&quot;issue&quot;]
                             subgraph BasicFifo5[&quot;fetch_resume_fifo BasicFifo&quot;]
-                                BasicFifo5_read[&quot;read&quot;]
                                 BasicFifo5_write[&quot;write&quot;]
+                                BasicFifo5_read[&quot;read&quot;]
                             end
                         end
                         subgraph WakeupSelect4[&quot;wakeup_select_4 WakeupSelect&quot;]
@@ -369,8 +369,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         subgraph Collector1[&quot;collector Collector&quot;]
                             Collector1_method[&quot;method&quot;]
                             subgraph Forwarder5[&quot;forwarder Forwarder&quot;]
-                                Forwarder5_write[&quot;write&quot;]
                                 Forwarder5_read[&quot;read&quot;]
+                                Forwarder5_write[&quot;write&quot;]
                             end
                             subgraph ManyToOneConnectTrans1[&quot;connect ManyToOneConnectTrans&quot;]
                                 subgraph ConnectTrans4[&quot;ManyToOneConnectTrans_input_0 ConnectTrans&quot;]
@@ -392,36 +392,36 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         end
                     end
                     subgraph LSUDummy[&quot;rs_block_1 LSUDummy&quot;]
-                        LSUDummy_insert[&quot;insert&quot;]
-                        LSUDummy_precommit[&quot;precommit&quot;]
                         LSUDummy_get_result[&quot;get_result&quot;]
-                        LSUDummy_update[&quot;update&quot;]
                         LSUDummy_LSUDummy[&quot;LSUDummy&quot;]
                         LSUDummy_LSUDummy1[&quot;LSUDummy&quot;]
-                        LSUDummy_LSUDummy2[&quot;LSUDummy&quot;]
+                        LSUDummy_insert[&quot;insert&quot;]
                         LSUDummy_select[&quot;select&quot;]
+                        LSUDummy_LSUDummy2[&quot;LSUDummy&quot;]
+                        LSUDummy_update[&quot;update&quot;]
+                        LSUDummy_precommit[&quot;precommit&quot;]
                         subgraph Forwarder6[&quot;forwarder Forwarder&quot;]
                             Forwarder6_write[&quot;write&quot;]
                             Forwarder6_read[&quot;read&quot;]
                         end
                         subgraph LSURequester[&quot;requester LSURequester&quot;]
-                            LSURequester_accept[&quot;accept&quot;]
-                            LSURequester_accept_cond0[&quot;accept_cond0&quot;]
                             LSURequester_issue_cond2[&quot;issue_cond2&quot;]
-                            LSURequester_issue[&quot;issue&quot;]
-                            LSURequester_accept_cond1[&quot;accept_cond1&quot;]
-                            LSURequester_issue_cond0[&quot;issue_cond0&quot;]
+                            LSURequester_accept_cond0[&quot;accept_cond0&quot;]
                             LSURequester_issue_cond1[&quot;issue_cond1&quot;]
+                            LSURequester_issue_cond0[&quot;issue_cond0&quot;]
+                            LSURequester_accept[&quot;accept&quot;]
+                            LSURequester_accept_cond1[&quot;accept_cond1&quot;]
+                            LSURequester_issue[&quot;issue&quot;]
                         end
                     end
                     subgraph CSRUnit[&quot;rs_block_2 CSRUnit&quot;]
-                        CSRUnit_select[&quot;select&quot;]
-                        CSRUnit_CSRUnit[&quot;CSRUnit&quot;]
-                        CSRUnit_update[&quot;update&quot;]
-                        CSRUnit_precommit[&quot;precommit&quot;]
                         CSRUnit_get_result[&quot;get_result&quot;]
+                        CSRUnit_CSRUnit[&quot;CSRUnit&quot;]
                         CSRUnit_insert[&quot;insert&quot;]
+                        CSRUnit_select[&quot;select&quot;]
                         CSRUnit_fetch_resume[&quot;fetch_resume&quot;]
+                        CSRUnit_update[&quot;update&quot;]
+                        CSRUnit_precommit[&quot;precommit&quot;]
                     end
                     subgraph MethodTryProduct[&quot;InstructionPrecommitKey_unifier MethodTryProduct&quot;]
                         MethodTryProduct_MethodTryProduct[&quot;MethodTryProduct&quot;]
@@ -450,8 +450,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                 end
                 subgraph InterruptController[&quot;interrupt_controller InterruptController&quot;]
                     InterruptController_report_interrupt[&quot;report_interrupt&quot;]
-                    InterruptController_entry[&quot;entry&quot;]
                     InterruptController_mret[&quot;mret&quot;]
+                    InterruptController_entry[&quot;entry&quot;]
                 end
                 subgraph GenericCSRRegisters[&quot;csr_generic GenericCSRRegisters&quot;]
                     GenericCSRRegisters_GenericCSRRegisters[&quot;GenericCSRRegisters&quot;]
@@ -462,41 +462,41 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                             CSRRegister_write[&quot;write&quot;]
                         end
                         subgraph CSRRegister1[&quot;mtvec CSRRegister&quot;]
-                            CSRRegister1__fu_read[&quot;_fu_read&quot;]
-                            CSRRegister1_read[&quot;read&quot;]
                             CSRRegister1__fu_write[&quot;_fu_write&quot;]
+                            CSRRegister1_read[&quot;read&quot;]
+                            CSRRegister1__fu_read[&quot;_fu_read&quot;]
                         end
                         subgraph CSRRegister2[&quot;mepc CSRRegister&quot;]
                             CSRRegister2_read[&quot;read&quot;]
+                            CSRRegister2__fu_read[&quot;_fu_read&quot;]
                             CSRRegister2_write[&quot;write&quot;]
                             CSRRegister2__fu_write[&quot;_fu_write&quot;]
-                            CSRRegister2__fu_read[&quot;_fu_read&quot;]
                         end
                     end
                     subgraph DoubleCounterCSR[&quot;csr_cycle DoubleCounterCSR&quot;]
                         DoubleCounterCSR_increment[&quot;increment&quot;]
                         subgraph CSRRegister3[&quot;register_low CSRRegister&quot;]
-                            CSRRegister3__fu_read[&quot;_fu_read&quot;]
-                            CSRRegister3_write[&quot;write&quot;]
                             CSRRegister3_read[&quot;read&quot;]
+                            CSRRegister3_write[&quot;write&quot;]
+                            CSRRegister3__fu_read[&quot;_fu_read&quot;]
                         end
                         subgraph CSRRegister4[&quot;register_high CSRRegister&quot;]
+                            CSRRegister4__fu_read[&quot;_fu_read&quot;]
                             CSRRegister4_read[&quot;read&quot;]
                             CSRRegister4_write[&quot;write&quot;]
-                            CSRRegister4__fu_read[&quot;_fu_read&quot;]
                         end
                     end
                     subgraph DoubleCounterCSR1[&quot;csr_time DoubleCounterCSR&quot;]
                         DoubleCounterCSR1_increment[&quot;increment&quot;]
                         subgraph CSRRegister5[&quot;register_low CSRRegister&quot;]
-                            CSRRegister5__fu_read[&quot;_fu_read&quot;]
                             CSRRegister5_read[&quot;read&quot;]
                             CSRRegister5_write[&quot;write&quot;]
+                            CSRRegister5__fu_read[&quot;_fu_read&quot;]
                         end
                         subgraph CSRRegister6[&quot;register_high CSRRegister&quot;]
                             CSRRegister6_write[&quot;write&quot;]
-                            CSRRegister6__fu_read[&quot;_fu_read&quot;]
                             CSRRegister6_read[&quot;read&quot;]
+                            CSRRegister6__fu_read[&quot;_fu_read&quot;]
                         end
                     end
                 end
@@ -519,8 +519,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                         RegAllocation_RegAllocation[&quot;RegAllocation&quot;]
                     end
                     subgraph FIFO11[&quot;rename_out_buf FIFO&quot;]
-                        FIFO11_write[&quot;write&quot;]
                         FIFO11_read[&quot;read&quot;]
+                        FIFO11_write[&quot;write&quot;]
                     end
                     subgraph Renaming[&quot;renaming Renaming&quot;]
                         Renaming_Renaming[&quot;Renaming&quot;]
@@ -554,25 +554,25 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
                     ConnectTrans11_ConnectTrans[&quot;ConnectTrans&quot;]
                 end
                 subgraph Retirement[&quot;retirement Retirement&quot;]
-                    Retirement_Retirement_cond1[&quot;Retirement_cond1&quot;]
                     Retirement_Retirement[&quot;Retirement&quot;]
+                    Retirement_Retirement_cond1[&quot;Retirement_cond1&quot;]
+                    Retirement_Retirement_cond0[&quot;Retirement_cond0&quot;]
                     Retirement_Retirement1[&quot;Retirement&quot;]
                     Retirement_Retirement2[&quot;Retirement&quot;]
                     Retirement_Retirement3[&quot;Retirement&quot;]
-                    Retirement_Retirement4[&quot;Retirement&quot;]
-                    Retirement_Retirement_cond0[&quot;Retirement_cond0&quot;]
                     Retirement_core_state[&quot;core_state&quot;]
+                    Retirement_Retirement4[&quot;Retirement&quot;]
                     subgraph DoubleCounterCSR2[&quot;instret_csr DoubleCounterCSR&quot;]
                         DoubleCounterCSR2_increment[&quot;increment&quot;]
                         subgraph CSRRegister7[&quot;register_low CSRRegister&quot;]
-                            CSRRegister7__fu_read[&quot;_fu_read&quot;]
                             CSRRegister7_write[&quot;write&quot;]
+                            CSRRegister7__fu_read[&quot;_fu_read&quot;]
                             CSRRegister7_read[&quot;read&quot;]
                         end
                         subgraph CSRRegister8[&quot;register_high CSRRegister&quot;]
                             CSRRegister8_read[&quot;read&quot;]
-                            CSRRegister8_write[&quot;write&quot;]
                             CSRRegister8__fu_read[&quot;_fu_read&quot;]
+                            CSRRegister8_write[&quot;write&quot;]
                         end
                     end
                     subgraph HwCounter9[&quot;perf_instr_ret HwCounter&quot;]
@@ -592,13 +592,13 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
             end
         end
         subgraph TransactionManager[&quot;transactionManager TransactionManager&quot;]
-            TransactionManager_issue_cond2_LSUDummy[&quot;issue_cond2_LSUDummy&quot;]
-            TransactionManager_accept_cond0_LSUDummy[&quot;accept_cond0_LSUDummy&quot;]
-            TransactionManager_issue_cond0_LSUDummy[&quot;issue_cond0_LSUDummy&quot;]
+            TransactionManager_LSUDummy_accept_cond1[&quot;LSUDummy_accept_cond1&quot;]
             TransactionManager_Retirement_Retirement_cond1[&quot;Retirement_Retirement_cond1&quot;]
+            TransactionManager_issue_cond0_LSUDummy[&quot;issue_cond0_LSUDummy&quot;]
+            TransactionManager_LSUDummy_issue_cond2[&quot;LSUDummy_issue_cond2&quot;]
             TransactionManager_Retirement_Retirement_cond0[&quot;Retirement_Retirement_cond0&quot;]
-            TransactionManager_issue_cond1_LSUDummy[&quot;issue_cond1_LSUDummy&quot;]
-            TransactionManager_accept_cond1_LSUDummy[&quot;accept_cond1_LSUDummy&quot;]
+            TransactionManager_LSUDummy_issue_cond1[&quot;LSUDummy_issue_cond1&quot;]
+            TransactionManager_LSUDummy_accept_cond0[&quot;LSUDummy_accept_cond0&quot;]
         end
     end
 Core_InitFreeRFFifo --&gt; BasicFifo2_write
@@ -613,40 +613,40 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; Serializer_Serializer1
 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; BasicFifo_write
 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --&gt; WishboneMaster_request
-ICache_ICache1 &lt;--&gt; HwCounter4__incr
+ICache_ICache3 &lt;--&gt; HwCounter4__incr
 ICache_ICache2 &lt;--&gt; HwCounter3__incr
 ICache_ICache2 &lt;--&gt; HwCounter2__incr
 ICache_ICache2 &lt;--&gt; HwCounter1__incr
 ICache_ICache2 --&gt; Forwarder3_write
-ICache_ICache --&gt; SimpleCommonBusCacheRefiller_start_refill
+ICache_ICache1 --&gt; SimpleCommonBusCacheRefiller_start_refill
+ICache_ICache1 --&gt; Forwarder2_write
 ICache_ICache --&gt; Forwarder2_write
-ICache_ICache3 --&gt; Forwarder2_write
-SimpleCommonBusCacheRefiller_accept_refill --&gt; ICache_ICache3
-WishboneMasterAdapter_get_read_response --&gt; ICache_ICache3
-Serializer_Serializer --&gt; ICache_ICache3
-BasicFifo_read --&gt; ICache_ICache3
-WishboneMaster_result --&gt; ICache_ICache3
-Forwarder_read --&gt; ICache_ICache3
-Fetch_Fetch --&gt; ICache_issue_req
-Fetch_Fetch &lt;--&gt; HwCounter__incr
-Fetch_Fetch &lt;--&gt; LatencyMeasurer__start
-Fetch_Fetch --&gt; FIFO1_write
-Fetch_Fetch --&gt; FIFO2_write
-Fetch_Fetch --&gt; BasicFifo3_write
-BasicFifo3_read --&gt; Fetch_Fetch1
-ICache_accept_res --&gt; Fetch_Fetch1
-FIFO2_read --&gt; Fetch_Fetch1
-Fetch_Fetch1 &lt;--&gt; LatencyMeasurer__stop
-FIFO1_read --&gt; Fetch_Fetch1
-Fetch_Fetch1 --&gt; HwExpHistogram__add
-Forwarder3_read --&gt; Fetch_Fetch1
-Fetch_Fetch1 --&gt; MethodProduct_method
+SimpleCommonBusCacheRefiller_accept_refill --&gt; ICache_ICache
+WishboneMasterAdapter_get_read_response --&gt; ICache_ICache
+Serializer_Serializer --&gt; ICache_ICache
+BasicFifo_read --&gt; ICache_ICache
+WishboneMaster_result --&gt; ICache_ICache
+Forwarder_read --&gt; ICache_ICache
+Fetch_Fetch1 --&gt; ICache_issue_req
+Fetch_Fetch1 &lt;--&gt; HwCounter__incr
+Fetch_Fetch1 &lt;--&gt; LatencyMeasurer__start
+Fetch_Fetch1 --&gt; FIFO1_write
+Fetch_Fetch1 --&gt; FIFO2_write
+Fetch_Fetch1 --&gt; BasicFifo3_write
+BasicFifo3_read --&gt; Fetch_Fetch
+ICache_accept_res --&gt; Fetch_Fetch
+FIFO2_read --&gt; Fetch_Fetch
+Fetch_Fetch &lt;--&gt; LatencyMeasurer__stop
+FIFO1_read --&gt; Fetch_Fetch
+Fetch_Fetch --&gt; HwExpHistogram__add
+Forwarder3_read --&gt; Fetch_Fetch
+Fetch_Fetch --&gt; MethodProduct_method
 AdapterTrans_AdapterTrans_method --&gt; MethodProduct_method
-Fetch_Fetch1 --&gt; FIFO_write
+Fetch_Fetch --&gt; FIFO_write
 AdapterTrans_AdapterTrans_method --&gt; FIFO_write
-Fetch_Fetch1 --&gt; MethodMap_method
+Fetch_Fetch --&gt; MethodMap_method
 AdapterTrans_AdapterTrans_method --&gt; MethodMap_method
-Fetch_Fetch1 &lt;--&gt; CoreInstructionCounter_increment
+Fetch_Fetch &lt;--&gt; CoreInstructionCounter_increment
 AdapterTrans_AdapterTrans_method &lt;--&gt; CoreInstructionCounter_increment
 FIFO_read --&gt; DecodeStage_DecodeStage
 DecodeStage_DecodeStage &lt;--&gt; HwCounter8__incr
@@ -664,17 +664,17 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 ROBAllocation_ROBAllocation &lt;--&gt; LatencyMeasurer1__start
 ROBAllocation_ROBAllocation --&gt; FIFO3_write
 ROBAllocation_ROBAllocation --&gt; FIFO12_write
-FIFO12_read --&gt; RSSelection_RSSelection1
-RSSelection_RSSelection1 --&gt; Forwarder8_write
+FIFO12_read --&gt; RSSelection_RSSelection3
+RSSelection_RSSelection3 --&gt; Forwarder8_write
 Forwarder8_read --&gt; RSSelection_RSSelection
-Forwarder8_read --&gt; RSSelection_RSSelection3
+Forwarder8_read --&gt; RSSelection_RSSelection1
 Forwarder8_read --&gt; RSSelection_RSSelection2
 RSFuncBlock_select --&gt; RSSelection_RSSelection
 RS_select --&gt; RSSelection_RSSelection
 RSSelection_RSSelection --&gt; FIFO13_write
-RSSelection_RSSelection3 --&gt; FIFO13_write
+RSSelection_RSSelection1 --&gt; FIFO13_write
 RSSelection_RSSelection2 --&gt; FIFO13_write
-RSSelection_RSSelection3 &lt;--&gt; LSUDummy_select
+RSSelection_RSSelection1 &lt;--&gt; LSUDummy_select
 RSSelection_RSSelection2 &lt;--&gt; CSRUnit_select
 FIFO13_read --&gt; RSInsertion_RSInsertion
 RegisterFile_read1 --&gt; RSInsertion_RSInsertion
@@ -691,7 +691,7 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 Collector2_method --&gt; ConnectTrans11_ConnectTrans
 Forwarder7_read --&gt; ConnectTrans11_ConnectTrans
 ConnectTrans11_ConnectTrans --&gt; Fetch_resume
-Retirement_Retirement4 --&gt; Fetch_resume
+Retirement_Retirement3 --&gt; Fetch_resume
 Collector_method --&gt; ResultAnnouncement_ResultAnnouncement
 Forwarder4_read --&gt; ResultAnnouncement_ResultAnnouncement
 ResultAnnouncement_ResultAnnouncement --&gt; ReorderBuffer_mark_done
@@ -701,7 +701,7 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 ResultAnnouncement_ResultAnnouncement --&gt; RS_update
 ResultAnnouncement_ResultAnnouncement --&gt; LSUDummy_update
 ResultAnnouncement_ResultAnnouncement --&gt; CSRUnit_update
-RS_RS2 --&gt; WakeupSelect_WakeupSelect
+RS_RS --&gt; WakeupSelect_WakeupSelect
 RS_take --&gt; WakeupSelect_WakeupSelect
 RS_take --&gt; WakeupSelect1_WakeupSelect
 RS_take --&gt; WakeupSelect2_WakeupSelect
@@ -709,10 +709,10 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 RS_take --&gt; WakeupSelect4_WakeupSelect
 WakeupSelect_WakeupSelect --&gt; AluFuncUnit_issue
 WakeupSelect_WakeupSelect --&gt; FIFO4_write
-RS_RS --&gt; WakeupSelect1_WakeupSelect
+RS_RS4 --&gt; WakeupSelect1_WakeupSelect
 WakeupSelect1_WakeupSelect --&gt; ShiftFuncUnit_issue
 WakeupSelect1_WakeupSelect --&gt; FIFO5_write
-RS_RS4 --&gt; WakeupSelect2_WakeupSelect
+RS_RS2 --&gt; WakeupSelect2_WakeupSelect
 WakeupSelect2_WakeupSelect --&gt; JumpBranchFuncUnit_issue
 WakeupSelect2_WakeupSelect &lt;--&gt; HwCounter5__incr
 WakeupSelect2_WakeupSelect &lt;--&gt; HwCounter6__incr
@@ -724,10 +724,10 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 ConnectTrans3_ConnectTrans --&gt; BasicFifo4_write
 WakeupSelect2_WakeupSelect --&gt; FIFO7_write
 WakeupSelect2_WakeupSelect --&gt; FIFO6_write
-RS_RS1 --&gt; WakeupSelect3_WakeupSelect
+RS_RS3 --&gt; WakeupSelect3_WakeupSelect
 WakeupSelect3_WakeupSelect --&gt; ExceptionFuncUnit_issue
 WakeupSelect3_WakeupSelect --&gt; FIFO8_write
-RS_RS3 --&gt; WakeupSelect4_WakeupSelect
+RS_RS1 --&gt; WakeupSelect4_WakeupSelect
 WakeupSelect4_WakeupSelect --&gt; PrivilegedFuncUnit_issue
 ConnectTrans4_ConnectTrans --&gt; Forwarder5_write
 ConnectTrans5_ConnectTrans --&gt; Forwarder5_write
@@ -746,11 +746,11 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 CSRRegister2_read --&gt; ConnectTrans8_ConnectTrans
 ConnectTrans8_ConnectTrans --&gt; BasicFifo5_write
 LSUDummy_LSUDummy1 --&gt; Forwarder6_write
-TransactionManager_accept_cond0_LSUDummy --&gt; Forwarder6_write
-TransactionManager_issue_cond1_LSUDummy --&gt; Forwarder6_write
-TransactionManager_issue_cond2_LSUDummy --&gt; Forwarder6_write
+TransactionManager_LSUDummy_issue_cond1 --&gt; Forwarder6_write
+TransactionManager_LSUDummy_accept_cond1 --&gt; Forwarder6_write
+TransactionManager_LSUDummy_issue_cond2 --&gt; Forwarder6_write
+TransactionManager_LSUDummy_accept_cond0 --&gt; Forwarder6_write
 TransactionManager_issue_cond0_LSUDummy --&gt; Forwarder6_write
-TransactionManager_accept_cond1_LSUDummy --&gt; Forwarder6_write
 CSRRegister__fu_read --&gt; CSRUnit_CSRUnit
 CSRUnit_CSRUnit --&gt; CSRRegister__fu_write
 CSRRegister1__fu_read --&gt; CSRUnit_CSRUnit
@@ -772,21 +772,21 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 LSUDummy_get_result --&gt; ConnectTrans2_ConnectTrans
 Forwarder6_read --&gt; ConnectTrans2_ConnectTrans
 CSRUnit_get_result --&gt; ConnectTrans3_ConnectTrans
-MethodTryProduct_MethodTryProduct2 --&gt; PrivilegedFuncUnit_precommit
-MethodTryProduct_MethodTryProduct2 &lt;--&gt; InterruptController_mret
-MethodTryProduct_MethodTryProduct --&gt; LSUDummy_precommit
-MethodTryProduct_MethodTryProduct1 --&gt; CSRUnit_precommit
+MethodTryProduct_MethodTryProduct --&gt; PrivilegedFuncUnit_precommit
+MethodTryProduct_MethodTryProduct &lt;--&gt; InterruptController_mret
+MethodTryProduct_MethodTryProduct1 --&gt; LSUDummy_precommit
+MethodTryProduct_MethodTryProduct2 --&gt; CSRUnit_precommit
 ConnectTrans9_ConnectTrans --&gt; Forwarder7_write
 ConnectTrans10_ConnectTrans --&gt; Forwarder7_write
 BasicFifo5_read --&gt; ConnectTrans9_ConnectTrans
 CSRUnit_fetch_resume --&gt; ConnectTrans10_ConnectTrans
-ReorderBuffer_peek --&gt; Retirement_Retirement2
-ReorderBuffer_peek --&gt; Retirement_Retirement3
+ReorderBuffer_peek --&gt; Retirement_Retirement4
+ReorderBuffer_peek --&gt; Retirement_Retirement1
 ReorderBuffer_peek --&gt; Retirement_Retirement
 ReorderBuffer_peek --&gt; TransactionManager_Retirement_Retirement_cond1
 ReorderBuffer_peek --&gt; TransactionManager_Retirement_Retirement_cond0
-Retirement_Retirement2 --&gt; MethodTryProduct_method
-ExceptionCauseRegister_get --&gt; Retirement_Retirement3
+Retirement_Retirement4 --&gt; MethodTryProduct_method
+ExceptionCauseRegister_get --&gt; Retirement_Retirement1
 ExceptionCauseRegister_get --&gt; TransactionManager_Retirement_Retirement_cond1
 ExceptionCauseRegister_get --&gt; TransactionManager_Retirement_Retirement_cond0
 Retirement_Retirement &lt;--&gt; ReorderBuffer_retire
@@ -809,8 +809,8 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 Retirement_Retirement --&gt; RegisterFile_free
 TransactionManager_Retirement_Retirement_cond1 --&gt; RegisterFile_free
 TransactionManager_Retirement_Retirement_cond0 --&gt; RegisterFile_free
-CSRRegister1_read --&gt; Retirement_Retirement4
-Retirement_Retirement4 &lt;--&gt; ExceptionCauseRegister_clear
+CSRRegister1_read --&gt; Retirement_Retirement3
+Retirement_Retirement3 &lt;--&gt; ExceptionCauseRegister_clear
 GenericCSRRegisters_GenericCSRRegisters &lt;--&gt; DoubleCounterCSR_increment
 CSRRegister3_read --&gt; GenericCSRRegisters_GenericCSRRegisters
 GenericCSRRegisters_GenericCSRRegisters --&gt; CSRRegister3_write
@@ -822,41 +822,35 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 CSRRegister6_read --&gt; GenericCSRRegisters_GenericCSRRegisters
 GenericCSRRegisters_GenericCSRRegisters --&gt; CSRRegister6_write
 AdapterTrans1_AdapterTrans_report_interrupt &lt;--&gt; InterruptController_report_interrupt
-TransactionManager_accept_cond0_LSUDummy &lt;--&gt; LSURequester_accept_cond0
-WishboneMasterAdapter1_get_write_response --&gt; TransactionManager_accept_cond0_LSUDummy
-Serializer1_Serializer1 --&gt; TransactionManager_accept_cond0_LSUDummy
-BasicFifo1_read --&gt; TransactionManager_accept_cond0_LSUDummy
-BasicFifo1_read --&gt; TransactionManager_accept_cond1_LSUDummy
-WishboneMaster1_result --&gt; TransactionManager_accept_cond0_LSUDummy
-WishboneMaster1_result --&gt; TransactionManager_accept_cond1_LSUDummy
-Forwarder1_read --&gt; TransactionManager_accept_cond0_LSUDummy
-Forwarder1_read --&gt; TransactionManager_accept_cond1_LSUDummy
-TransactionManager_accept_cond0_LSUDummy &lt;--&gt; LSUDummy_LSUDummy2
-TransactionManager_accept_cond1_LSUDummy &lt;--&gt; LSUDummy_LSUDummy2
-LSURequester_accept --&gt; TransactionManager_accept_cond0_LSUDummy
-LSURequester_accept --&gt; TransactionManager_accept_cond1_LSUDummy
-TransactionManager_issue_cond1_LSUDummy &lt;--&gt; LSURequester_issue_cond1
-TransactionManager_issue_cond1_LSUDummy --&gt; WishboneMasterAdapter1_request_read
-TransactionManager_issue_cond1_LSUDummy --&gt; Serializer1_Serializer3
-TransactionManager_issue_cond1_LSUDummy --&gt; BasicFifo1_write
-TransactionManager_issue_cond0_LSUDummy --&gt; BasicFifo1_write
-TransactionManager_issue_cond1_LSUDummy --&gt; WishboneMaster1_request
-TransactionManager_issue_cond0_LSUDummy --&gt; WishboneMaster1_request
-TransactionManager_issue_cond1_LSUDummy &lt;--&gt; LSUDummy_LSUDummy
-TransactionManager_issue_cond2_LSUDummy &lt;--&gt; LSUDummy_LSUDummy
+TransactionManager_LSUDummy_issue_cond1 &lt;--&gt; LSUDummy_LSUDummy
+TransactionManager_LSUDummy_issue_cond2 &lt;--&gt; LSUDummy_LSUDummy
 TransactionManager_issue_cond0_LSUDummy &lt;--&gt; LSUDummy_LSUDummy
-TransactionManager_issue_cond1_LSUDummy --&gt; LSURequester_issue
-TransactionManager_issue_cond2_LSUDummy --&gt; LSURequester_issue
+TransactionManager_LSUDummy_issue_cond1 --&gt; LSURequester_issue
+TransactionManager_LSUDummy_issue_cond2 --&gt; LSURequester_issue
 TransactionManager_issue_cond0_LSUDummy --&gt; LSURequester_issue
-TransactionManager_issue_cond2_LSUDummy &lt;--&gt; LSURequester_issue_cond2
-TransactionManager_issue_cond0_LSUDummy &lt;--&gt; LSURequester_issue_cond0
-TransactionManager_issue_cond0_LSUDummy --&gt; WishboneMasterAdapter1_request_write
-TransactionManager_issue_cond0_LSUDummy --&gt; Serializer1_Serializer2
-TransactionManager_accept_cond1_LSUDummy &lt;--&gt; LSURequester_accept_cond1
-WishboneMasterAdapter1_get_read_response --&gt; TransactionManager_accept_cond1_LSUDummy
-Serializer1_Serializer --&gt; TransactionManager_accept_cond1_LSUDummy
-TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; Retirement_Retirement1
-TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; Retirement_Retirement1
+TransactionManager_LSUDummy_issue_cond1 &lt;--&gt; LSURequester_issue_cond1
+TransactionManager_LSUDummy_issue_cond1 --&gt; WishboneMasterAdapter1_request_read
+TransactionManager_LSUDummy_issue_cond1 --&gt; Serializer1_Serializer
+TransactionManager_LSUDummy_issue_cond1 --&gt; BasicFifo1_write
+TransactionManager_issue_cond0_LSUDummy --&gt; BasicFifo1_write
+TransactionManager_LSUDummy_issue_cond1 --&gt; WishboneMaster1_request
+TransactionManager_issue_cond0_LSUDummy --&gt; WishboneMaster1_request
+TransactionManager_LSUDummy_accept_cond1 &lt;--&gt; LSUDummy_LSUDummy2
+TransactionManager_LSUDummy_accept_cond0 &lt;--&gt; LSUDummy_LSUDummy2
+LSURequester_accept --&gt; TransactionManager_LSUDummy_accept_cond1
+LSURequester_accept --&gt; TransactionManager_LSUDummy_accept_cond0
+TransactionManager_LSUDummy_accept_cond1 &lt;--&gt; LSURequester_accept_cond1
+WishboneMasterAdapter1_get_read_response --&gt; TransactionManager_LSUDummy_accept_cond1
+Serializer1_Serializer2 --&gt; TransactionManager_LSUDummy_accept_cond1
+BasicFifo1_read --&gt; TransactionManager_LSUDummy_accept_cond1
+BasicFifo1_read --&gt; TransactionManager_LSUDummy_accept_cond0
+WishboneMaster1_result --&gt; TransactionManager_LSUDummy_accept_cond1
+WishboneMaster1_result --&gt; TransactionManager_LSUDummy_accept_cond0
+Forwarder1_read --&gt; TransactionManager_LSUDummy_accept_cond1
+Forwarder1_read --&gt; TransactionManager_LSUDummy_accept_cond0
+TransactionManager_LSUDummy_issue_cond2 &lt;--&gt; LSURequester_issue_cond2
+TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; Retirement_Retirement2
+TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; Retirement_Retirement2
 TransactionManager_Retirement_Retirement_cond1 --&gt; CSRRegister_write
 TransactionManager_Retirement_Retirement_cond0 --&gt; CSRRegister_write
 TransactionManager_Retirement_Retirement_cond1 --&gt; CSRRegister2_write
@@ -864,6 +858,9 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; InterruptController_entry
 TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; InterruptController_entry
 TransactionManager_Retirement_Retirement_cond1 &lt;--&gt; Retirement_Retirement_cond1
+TransactionManager_LSUDummy_accept_cond0 &lt;--&gt; LSURequester_accept_cond0
+WishboneMasterAdapter1_get_write_response --&gt; TransactionManager_LSUDummy_accept_cond0
+Serializer1_Serializer1 --&gt; TransactionManager_LSUDummy_accept_cond0
 TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; Retirement_Retirement_cond0
 TransactionManager_Retirement_Retirement_cond0 --&gt; RRAT_commit
 TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; DoubleCounterCSR2_increment
@@ -872,6 +869,9 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 CSRRegister8_read --&gt; TransactionManager_Retirement_Retirement_cond0
 TransactionManager_Retirement_Retirement_cond0 --&gt; CSRRegister8_write
 TransactionManager_Retirement_Retirement_cond0 &lt;--&gt; HwCounter9__incr
+TransactionManager_issue_cond0_LSUDummy &lt;--&gt; LSURequester_issue_cond0
+TransactionManager_issue_cond0_LSUDummy --&gt; WishboneMasterAdapter1_request_write
+TransactionManager_issue_cond0_LSUDummy --&gt; Serializer1_Serializer3
         </div></div>
 </div>
 </div>
@@ -888,7 +888,7 @@ <h1>Full transaction-method graph<a class="headerlink" href="#full-transaction-m
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/development-environment.html b/development-environment.html
index 8e3376640..34d604de8 100644
--- a/development-environment.html
+++ b/development-environment.html
@@ -209,7 +209,7 @@ <h3>tprof.py<a class="headerlink" href="#tprof-py" title="Permalink to this head
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/genindex.html b/genindex.html
index cf70764ac..1fc6bba36 100644
--- a/genindex.html
+++ b/genindex.html
@@ -1516,16 +1516,30 @@ <h2 id="E">E</h2>
         <li><a href="transactron.utils.html#transactron.utils.dependencies.ListKey.empty_valid">(transactron.utils.dependencies.ListKey attribute)</a>
 </li>
       </ul></li>
-  </ul></td>
-  <td style="width: 33%; vertical-align: top;"><ul>
       <li><a href="transactron.testing.html#transactron.testing.testbenchio.TestbenchIO.enable">enable() (transactron.testing.testbenchio.TestbenchIO method)</a>
 </li>
-      <li><a href="transactron.html#transactron.profiler.Profile.encode">encode() (transactron.profiler.Profile method)</a>
+      <li><a href="coreblocks.params.html#coreblocks.params.instr.BTypeInstr.encode">encode() (coreblocks.params.instr.BTypeInstr static method)</a>
 
       <ul>
+        <li><a href="coreblocks.params.html#coreblocks.params.instr.IllegalInstr.encode">(coreblocks.params.instr.IllegalInstr static method)</a>
+</li>
+        <li><a href="coreblocks.params.html#coreblocks.params.instr.ITypeInstr.encode">(coreblocks.params.instr.ITypeInstr static method)</a>
+</li>
+        <li><a href="coreblocks.params.html#coreblocks.params.instr.JTypeInstr.encode">(coreblocks.params.instr.JTypeInstr static method)</a>
+</li>
+        <li><a href="coreblocks.params.html#coreblocks.params.instr.RTypeInstr.encode">(coreblocks.params.instr.RTypeInstr static method)</a>
+</li>
+        <li><a href="coreblocks.params.html#coreblocks.params.instr.STypeInstr.encode">(coreblocks.params.instr.STypeInstr static method)</a>
+</li>
+        <li><a href="coreblocks.params.html#coreblocks.params.instr.UTypeInstr.encode">(coreblocks.params.instr.UTypeInstr static method)</a>
+</li>
+        <li><a href="transactron.html#transactron.profiler.Profile.encode">(transactron.profiler.Profile method)</a>
+</li>
         <li><a href="transactron.utils.html#transactron.utils.gen.GenerationInfo.encode">(transactron.utils.gen.GenerationInfo method)</a>
 </li>
       </ul></li>
+  </ul></td>
+  <td style="width: 33%; vertical-align: top;"><ul>
       <li><a href="coreblocks.frontend.decoder.html#coreblocks.frontend.decoder.instr_description.Encoding">Encoding (class in coreblocks.frontend.decoder.instr_description)</a>
 </li>
       <li><a href="coreblocks.func_blocks.lsu.html#coreblocks.func_blocks.lsu.pma.PMARegion.end">end (coreblocks.func_blocks.lsu.pma.PMARegion attribute)</a>
@@ -3737,7 +3751,7 @@ <h2 id="Z">Z</h2>
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/home.html b/home.html
index bc1a271aa..3861b3ae1 100644
--- a/home.html
+++ b/home.html
@@ -129,7 +129,7 @@ <h2>Documentation<a class="headerlink" href="#documentation" title="Permalink to
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/index.html b/index.html
index 8e082afa3..fb8c9b257 100644
--- a/index.html
+++ b/index.html
@@ -229,7 +229,7 @@ <h1>Coreblocks<a class="headerlink" href="#coreblocks" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html
index 294ed7514..4df4276e5 100644
--- a/miscellany/exceptions-summary.html
+++ b/miscellany/exceptions-summary.html
@@ -271,7 +271,7 @@ <h2>Summary<a class="headerlink" href="#summary" title="Permalink to this headin
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/modules-coreblocks.html b/modules-coreblocks.html
index af6549138..e614cecf3 100644
--- a/modules-coreblocks.html
+++ b/modules-coreblocks.html
@@ -168,7 +168,7 @@ <h1>coreblocks<a class="headerlink" href="#coreblocks" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/modules-transactron.html b/modules-transactron.html
index 945bd5f58..bdd546981 100644
--- a/modules-transactron.html
+++ b/modules-transactron.html
@@ -161,7 +161,7 @@ <h1>transactron<a class="headerlink" href="#transactron" title="Permalink to thi
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/objects.inv b/objects.inv
index 92662cc52d584825c033e668b28a7362bd4bff8c..bba8c03c72de9c1e157ad29727a3930d59483ab3 100644
GIT binary patch
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diff --git a/problem-checklist.html b/problem-checklist.html
index e559cb007..99413d9c0 100644
--- a/problem-checklist.html
+++ b/problem-checklist.html
@@ -105,7 +105,7 @@ <h1>Problem checklist<a class="headerlink" href="#problem-checklist" title="Perm
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/py-modindex.html b/py-modindex.html
index aab3a16cc..51b555dfe 100644
--- a/py-modindex.html
+++ b/py-modindex.html
@@ -668,7 +668,7 @@ <h1>Python Module Index</h1>
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/scheduler/overview.html b/scheduler/overview.html
index b47f236a3..3fa1afac1 100644
--- a/scheduler/overview.html
+++ b/scheduler/overview.html
@@ -146,7 +146,7 @@ <h2>More detailed description of each block<a class="headerlink" href="#more-det
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/search.html b/search.html
index 65537fbde..acf025fd9 100644
--- a/search.html
+++ b/search.html
@@ -101,7 +101,7 @@
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 23:12 2024-03-21.
+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
       </span></p>
   </div>
 
diff --git a/searchindex.js b/searchindex.js
index 72038488a..c14818eb6 100644
--- a/searchindex.js
+++ b/searchindex.js
@@ -1 +1 @@
-Search.setIndex({"docnames": ["api", "assumptions", "auto_graph", "components/icache", "coreblocks", "coreblocks.backend", "coreblocks.cache", "coreblocks.core_structs", "coreblocks.frontend", "coreblocks.frontend.decoder", "coreblocks.frontend.fetch", "coreblocks.func_blocks", "coreblocks.func_blocks.fu", "coreblocks.func_blocks.fu.unsigned_multiplication", "coreblocks.func_blocks.interface", "coreblocks.func_blocks.lsu", "coreblocks.params", "coreblocks.peripherals", "coreblocks.priv", "coreblocks.priv.csr", "coreblocks.priv.traps", "coreblocks.scheduler", "current-graph", "development-environment", "home", "index", "miscellany/exceptions-summary", "modules-coreblocks", "modules-transactron", "problem-checklist", "scheduler/overview", "shared-structs/implementation/rs-impl", "shared-structs/rs", "synthesis/synthesis", "transactions", "transactron", "transactron.core", "transactron.lib", "transactron.testing", "transactron.utils", "transactron.utils.amaranth_ext"], "filenames": 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21, 34, 36, 37, 39], "option": [9, 12, 16, 17, 19, 23, 34, 35, 36, 37, 38, 39, 40], "exist": [9, 34], "instr_type_overrid": 9, "instrtyp": 9, "specifi": [9, 16, 17, 19, 32, 37, 38, 39], "determin": [9, 26, 33, 37, 39], "instrust": 9, "almost": 9, "correct": [9, 15, 26, 31, 32, 33], "rd_zero": 9, "bool": [9, 15, 16, 19, 35, 36, 37, 38, 39, 40], "field": [9, 15, 16, 19, 23, 31, 32, 34, 35, 36, 37, 38, 39], "constant": 9, "zero": [9, 20, 31, 37, 40], "other": [9, 19, 23, 25, 34, 35, 36, 37, 40], "accordingli": 9, "default": [9, 17, 23, 34, 35, 36, 37, 39, 40], "fals": [9, 12, 15, 16, 23, 34, 35, 36, 37, 39, 40], "rs1_zero": 9, "exceptioncaus": 9, "intenum": [9, 12, 19], "breakpoint": 9, "3": [9, 12, 19, 23, 35, 36, 39], "environment_call_from_m": 9, "environment_call_from_": 9, "9": 9, "environment_call_from_u": 9, "8": [9, 12, 13, 16, 17, 36, 37], "illegal_instruct": 9, "2": [9, 12, 13, 16, 17, 19, 33, 35, 36, 37, 39], "instruction_access_fault": 9, "instruction_address_misalign": 9, "instruction_page_fault": 9, "load_access_fault": 9, "5": [9, 12, 16, 30, 37, 38], "load_address_misalign": 9, "load_page_fault": 9, "store_access_fault": 9, "7": [9, 16], "store_address_misalign": 9, "6": [9, 16, 26], "store_page_fault": 9, "__new__": [9, 12, 16, 19, 35], "tso": 9, "intflag": [9, 12, 16, 35], "dev_i": 9, "dev_o": 9, "mem_r": 9, "mem_w": 9, "clz": 9, "1536": 9, "cpop": 9, "1538": 9, "ctz": 9, "1537": 9, "ebreak": 9, "ecal": 9, "mret": [9, 12], "770": 9, "orcb": 9, "647": 9, "rev8_32": 9, "1688": 9, "rev8_64": 9, "1720": 9, "sextb": 9, "1540": 9, "sexth": 9, "1541": 9, "sret": 9, "258": 9, "wfi": 9, "261": 9, "zexth": 9, "add": [9, 34, 36, 37, 39], "AND": 9, "andn": 9, "b": [9, 16], "bclr": [9, 12], "beq": 9, "bext": [9, 12], "bge": 9, "bgeu": 9, "binv": [9, 12], "blt": 9, "bltu": 9, "bne": 9, "bset": [9, 12], "clmul": [9, 12], "clmulh": [9, 12], "clmulr": [9, 12], "csrrc": 9, "csrrci": 9, "csrr": 9, "csrrsi": 9, "csrrw": 9, "csrrwi": 9, "d": [9, 16, 34, 36, 39], "div": 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"unary_bit_manipulation_1": 9, "unary_bit_manipulation_2": 9, "unary_bit_manipulation_3": 9, "unary_bit_manipulation_4": 9, "unary_bit_manipulation_5": 9, "unknown": [9, 23, 35, 37, 39], "optypes_required_by_extens": 9, "resolve_impl": 9, "true": [9, 15, 16, 17, 34, 35, 36, 37, 38, 39, 40], "ignore_unsupport": 9, "instrdecompress": 9, "decompr_reg": 9, "rvc_reg": 9, "instr_mux": 9, "sel": [9, 17], "list": [9, 12, 16, 17, 19, 23, 25, 29, 33, 35, 36, 37, 38, 39, 40], "int": [9, 12, 13, 15, 16, 17, 19, 35, 36, 37, 38, 39, 40], "valuecast": [9, 16, 36, 37, 38, 39], "tupl": [9, 12, 17, 19, 21, 35, 36, 37, 39], "is_instr_compress": 9, "pc": [10, 25], "insid": [10, 33, 34, 36, 37], "increment": [10, 19, 20], "ilen_byt": 10, "cont": [10, 38], "unalignedfetch": 10, "work": [10, 21, 26, 29, 33, 34, 36, 37], "unalign": 10, "unsigned_multipl": [11, 12], "common": [11, 12, 17, 36, 37, 39], "fast_recurs": [11, 12], "sequenc": [11, 12, 21, 37], "alucompon": [12, 16], "functionalcomponentparam": [12, 16], "zba_en": 12, "zbb_enabl": 12, "get_modul": [12, 15, 16], "funcunit": [12, 14, 16], "get_optyp": [12, 15, 16], "alufuncunit": 12, "alu_fn": 12, "alufn": 12, "divcompon": 12, "ipc": [12, 33], "div_fn": 12, "divfn": 12, "decodermanag": 12, "fn": 12, "get_instruct": 12, "valid": [12, 17, 21, 31, 37, 39, 40], "implement": [12, 15, 17, 24, 25, 26, 30, 37, 39, 40], "format": [12, 23, 33, 34, 35, 36, 37, 39], "divunit": 12, "get_input": 12, "arg": [12, 17, 34, 35, 36, 37, 38, 39, 40], "exceptionfuncunit": 12, "unit_fn": 12, "exceptionunitfn": 12, "exceptionunitcompon": [12, 16], "jumpbranchfuncunit": 12, "jb_fn": 12, "jumpbranchfn": 12, "jumpcompon": [12, 16], "mulcompon": 12, "mul_unit_typ": 12, "multyp": 12, "dsp_width": [12, 13], "mul_fn": 12, "mulfn": 12, "hot": [12, 26, 40], "wire": 12, "recursive_mul": 12, "fastest": 12, "multipli": [12, 13], "onli": [12, 17, 19, 20, 26, 33, 34, 35, 36, 37, 38, 39], "costli": [12, 26], "term": 12, "resourc": [12, 20, 26, 33, 34, 36], "sequence_mul": 12, "dsp": [12, 13], "balanc": 12, "between": [12, 23, 26, 34, 36, 37, 39, 40], "cost": [12, 25, 34], "shift_mul": 12, "cheapest": 12, "russian": [12, 13], "peasant": [12, 13], "algorithm": [12, 13], "mulunit": 12, "respons": [12, 17, 21, 23, 36, 37, 38], "unsign": [12, 13], "integ": [12, 16, 38, 39], "standard": [12, 26, 33, 37, 40], "funcunitlayout": [12, 21], "comput": [12, 13, 15, 20, 26, 37, 39], "mul_typ": 12, "privilegedfn": 12, "classmethod": [12, 35, 36, 37, 39], "privilegedfuncunit": 12, "privilegedunitcompon": [12, 16], "shiftfuncunit": 12, "shift_unit_fn": 12, "shiftunitfn": 12, "shiftunitcompon": [12, 16], "clmultipli": 12, "carri": [12, 16, 33], "less": [12, 16], "product": [12, 37], "i1": [12, 13], "n": [12, 13, 16], "factor": 12, "i2": [12, 13], "reset": [12, 19, 25, 36], "new": [12, 15, 17, 20, 25, 26, 36, 37, 39, 40], "busi": 12, "while": [12, 36, 38], "progress": 12, "bit_width": 12, "recursion_depth": 12, "width": [12, 13, 16, 17, 19, 37, 39, 40], "depth": [12, 17, 33, 37], "recurs": [12, 13, 33, 34, 35, 39], "parallel": [12, 37], "power": [12, 39], "iterative_modul": 12, "recursive_modul": 12, "zbccompon": 12, "zbc_fn": 12, "zbcfn": 12, "zbcunit": 12, "zbsfunction": 12, "in1": 12, "in2": 12, "zbscompon": 12, "zbsunit": 12, "zbs_fn": 12, "dspmulunit": 13, "clock": [13, 30, 33, 34, 35, 36, 37], "design": [13, 26, 34, 35], "synthesi": [13, 25], "tool": [13, 23, 33, 35], "o": [13, 26, 34, 36], "same": [13, 15, 23, 34, 36, 37, 39], "number": [13, 16, 17, 23, 26, 33, 35, 36, 37, 38, 39, 40], "mulbaseunsign": 13, "unsignedmulunitlayout": 13, "recursiveunsignedmul": 13, "see": [13, 29, 33, 34, 37], "fast": 13, "within": [13, 23], "sequentialunsignedmul": 13, "sequenti": [13, 17], "classic": [13, 26], "shiftunsignedmul": 13, "cheap": 13, "multi": 13, "funcblocksunifi": 14, "iter": [14, 16, 36, 37, 38, 39, 40], "blockcomponentparam": [14, 15, 16], "extra_methods_requir": 14, "unifierkei": [14, 37], "get_extra_method": 14, "item": [14, 39, 40], "funcblock": [14, 15, 16, 21], "insert": [14, 15, 21, 25, 26, 30, 31], "lsublockcompon": [15, 16], "get_rs_entry_count": [15, 16], "lsudummi": 15, "veri": [15, 26, 34], "all": [15, 16, 17, 20, 23, 25, 26, 29, 34, 35, 36, 37, 39, 40], "isn": [15, 33, 36], "compliant": [15, 33], "riscv": [15, 33], "spec": 15, "doesn": [15, 26, 29, 34, 37], "check": [15, 23, 26, 29, 31, 32, 33, 36, 39], "rang": [15, 36, 37, 38, 39, 40], "reserv": [15, 16, 25, 26], "place": [15, 17, 26, 31, 33, 34, 36, 37], "intruct": 15, "put": [15, 31, 33, 37], "receiv": [15, 17, 34, 36, 37], "calcul": [15, 37], "further": [15, 23, 37], "To": [15, 23, 26, 33, 37, 39], "processor": [15, 24, 25, 30], "master": [15, 17, 33], "pmacheck": 15, "physic": [15, 16, 21, 26], "memori": [15, 16, 17, 26, 36, 37], "checker": 15, "mai": [15, 23, 37, 38, 39], "part": [15, 19, 26, 30, 34, 36, 37], "combin": [15, 25, 29, 36, 37, 39], "circuit": [15, 33, 34, 36, 37, 39], "pmalayout": 15, "structlayout": [15, 36, 37, 39], "pmaregion": [15, 16], "contigu": [15, 16], "region": [15, 26], "includ": [15, 33, 34, 36, 37, 39, 40], "both": [15, 31, 34, 36, 37, 39], "begin": [15, 26], "mmio": 15, "indic": [15, 26, 32, 36, 37], "coreconfigur": 16, "func_units_config": 16, "collect": [16, 19, 24, 33, 35, 36, 37, 38, 39, 40], "station": [16, 25], "exampl": [16, 19, 23, 25, 31, 34, 36, 37, 40], "rsblockcompon": 16, "rs_entri": 16, "compress": 16, "enabl": [16, 37, 38, 39], "embed": 16, "reduc": [16, 26, 36], "debug": [16, 23, 37, 39], "hardwar": [16, 25, 30, 34, 37], "disabl": [16, 35, 37, 38], "them": [16, 23, 26, 33, 34, 36, 37, 39], "synthes": [16, 33, 37], "phys_regs_bit": 16, "file": [16, 23, 26, 33, 39], "rob_entries_bit": 16, "reorder": [16, 26, 37], "buffer": [16, 17, 26, 31, 37], "start_pc": 16, "initi": [16, 17, 25, 37, 38], "program": [16, 26, 33, 34], "icache_en": 16, "bypass": 16, "directli": [16, 34, 36], "icache_wai": 16, "icache_sets_bit": 16, "icache_block_size_bit": 16, "allow_partial_extens": 16, "allow": [16, 24, 26, 33, 34, 36, 37, 40], "partial": [16, 35, 37, 39], "_implied_extens": 16, "extenst": 16, "flag": 16, "definit": [16, 25, 36], "per": [16, 33], "segment": 16, "abc": [16, 36, 37, 38, 39, 40], "func_unit": 16, "csrblockcompon": 16, "factori": [16, 35, 37, 39], "kwarg": [16, 17, 35, 36, 37, 38, 39, 40], "optypes_support": 16, "dependentcach": [16, 39], "cfg": 16, "addr_width": [16, 17], "length": [16, 26, 36, 39], "word_width": 16, "machin": [16, 19], "num_of_wai": 16, "num_of_sets_bit": 16, "block_size_bit": 16, "btypeinstr": 16, "riscvinstr": 16, "pack": 16, "ebreakinstr": 16, "itypeinstr": 16, "illegalinstr": 16, "jtypeinstr": 16, "rtypeinstr": 16, "stypeinstr": 16, "utypeinstr": 16, "avail": [16, 17, 19, 21, 23, 24, 33, 37], "atom": [16, 31, 34], "512": 16, "manipul": 16, "256": 16, "doubl": [16, 19, 26], "precis": [16, 26, 33], "float": [16, 35, 37, 38, 39], "point": [16, 26, 29, 33], "64": [16, 17], "f": [16, 21, 23, 33, 38], "98366": 16, "contain": [16, 23, 33, 34, 36, 37, 39], "basic": [16, 25, 33, 37], "full": [16, 23, 25, 26, 33, 37], "1024": 16, "dynam": [16, 26, 40], "languag": [16, 34], "l": [16, 23], "decim": 16, "m": [16, 17, 19, 20, 23, 26, 33, 34, 36, 37, 40], "divis": 16, "16384": 16, "user": [16, 19, 26, 33, 37], "level": [16, 17, 24, 26, 33, 34, 37, 38, 39], "interrupt": [16, 25], "p": [16, 23], "4096": 16, "simd": 16, "q": 16, "quad": 16, "2048": 16, "8192": 16, "vector": [16, 21, 25, 26], "xintmachinemod": 16, "8589934592": 16, "categor": 16, "privilieg": 16, "xintsupervisor": 16, "17179869184": 16, "supervisor": [16, 19], "zam": 16, "2097152": 16, "misalign": 16, "zba": 16, "268435456": 16, "extend": [16, 29, 36], "zbb": 16, "536870912": 16, "1073741824": 16, "2147483648": 16, "zdinx": 16, "33554432": 16, "zfh": 16, "4194304": 16, "half": 16, "zfhmin": 16, "8388608": 16, "minim": 16, "zfinx": 16, "16777216": 16, "zhinx": 16, "67108864": 16, "zicntr": 16, "524288": 16, "timer": [16, 19], "zicsr": 16, "32768": 16, "statu": [16, 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15], "bu": [1, 9, 15, 16, 17], "read": [1, 15, 17, 19, 23, 25, 29, 34, 37, 39], "x0": [1, 9], "rf0": 1, "return": [1, 3, 12, 15, 17, 20, 25, 26, 36, 37, 38, 39], "0": [1, 9, 12, 16, 17, 19, 21, 31, 32, 33, 35, 36, 37, 38], "write": [1, 6, 9, 17, 19, 26, 32, 34, 36, 37], "i": [1, 3, 5, 6, 9, 12, 13, 15, 16, 17, 19, 20, 21, 23, 24, 26, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40], "noop": 1, "separ": [1, 30, 35, 36, 37, 39], "r": [1, 5, 9, 15, 21, 23, 26, 30, 31, 32, 33], "each": [1, 10, 12, 16, 17, 19, 23, 25, 26, 31, 32, 34, 35, 36, 37, 38, 39], "fu": [1, 4, 5, 9, 11, 16, 20, 31, 32, 37], "writeback": 1, "stage": [1, 15, 20], "save": [1, 5, 16, 20, 23, 26, 31, 32, 35, 37, 39], "after": [1, 3, 6, 10, 17, 20, 26, 30, 33, 34, 37], "get": [1, 5, 9, 12, 13, 21, 23, 25, 35, 36, 37, 38, 39, 40], "output": [1, 5, 6, 15, 17, 23, 26, 31, 32, 36, 37, 40], "commit": [1, 23, 26, 33], "updat": [1, 14, 15, 19, 33, 40], "The": [3, 5, 6, 12, 17, 23, 24, 25, 26, 30, 31, 32, 33, 35, 36, 37, 38, 39, 40], "should": [3, 5, 6, 9, 10, 17, 20, 21, 23, 24, 26, 30, 31, 32, 33, 34, 36, 37, 38, 39, 40], "expos": [3, 37, 39], "three": [3, 9, 26, 33, 36], "issue_req": [3, 6], "thi": [3, 5, 6, 9, 12, 13, 15, 17, 19, 20, 21, 23, 26, 29, 31, 32, 33, 34, 35, 36, 37, 39, 40], "issu": [3, 6, 12, 13, 14, 21, 23, 34, 37], "an": [3, 5, 6, 15, 17, 21, 23, 24, 26, 29, 31, 33, 34, 35, 36, 37, 38, 39, 40], "lookup": [3, 6], "request": [3, 6, 12, 13, 15, 16, 17, 34, 35, 36, 37, 40], "accept_resp": 3, "result": [3, 5, 6, 9, 12, 13, 15, 17, 20, 26, 33, 34, 37, 39], "flush": [3, 6, 20, 26], "entir": [3, 33, 34], "oper": [3, 9, 12, 16, 26, 34, 36, 37, 40], "under": [3, 34, 35, 36], "follow": [3, 12, 21, 23, 31, 33, 34, 37, 39], "ar": [3, 5, 9, 15, 16, 17, 19, 23, 24, 26, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40], "alwai": [3, 9, 19, 33, 34, 36, 37, 38], "multipl": [3, 12, 13, 16, 17, 21, 34, 36, 37, 39], "4": [3, 9, 12, 16, 37], "byte": [3, 16, 35, 37, 39], "risc": [3, 9, 16, 24, 33], "v": [3, 9, 16, 23, 24, 26, 31, 33], "specif": [3, 9, 16, 17, 23, 26, 33, 37], "requir": [3, 19, 23, 26, 33, 34, 35, 36], "align": [3, 15, 39], "c": [3, 16, 26, 33], "extens": [3, 9, 16, 33], "introduc": [3, 26, 34], "16": [3, 9, 16, 26, 36], "bit": [3, 6, 9, 12, 13, 16, 17, 19, 20, 26, 31, 32, 34, 37, 39, 40], "relax": [3, 34], "fetch": [3, 4, 5, 8, 9, 16, 20, 26], "unit": [3, 5, 9, 10, 12, 13, 16, 17, 21, 23, 30, 33], "handl": [3, 12, 20, 25, 34, 36], "case": [3, 5, 17, 21, 26, 29, 34, 36, 37, 39, 40], "fulli": [3, 15, 37], "pipelin": [3, 15, 17, 21, 26, 31, 37], "process": [3, 20, 23, 25, 33, 37, 38], "order": [3, 16, 20, 21, 23, 24, 25, 33, 36, 37], "As": [3, 26, 34, 37], "can": [3, 5, 15, 17, 19, 20, 23, 24, 26, 30, 31, 33, 34, 35, 36, 37, 38, 39, 40], "invok": [3, 5, 9, 10, 21, 26, 31, 38], "independ": [3, 34, 37], "accept_r": [3, 6], "If": [3, 9, 16, 17, 19, 20, 26, 29, 31, 34, 35, 36, 37, 39], "space": [3, 26], "anoth": [3, 6, 23, 34, 36, 37], "simpli": 3, "block": [3, 13, 14, 16, 17, 21, 25, 26, 34, 36, 37], "latenc": [3, 26, 33, 37], "least": 3, "one": [3, 5, 6, 12, 17, 20, 23, 26, 30, 31, 32, 34, 36, 37, 38, 39, 40], "cycl": [3, 12, 13, 17, 19, 20, 23, 26, 30, 33, 34, 35, 36, 37, 38], "miss": [3, 26], "occur": [3, 6], "arbitrarili": 3, "long": [3, 32, 33, 37], "ensur": [3, 33], "ani": [3, 9, 17, 21, 26, 29, 37, 38, 39, 40], "refetch": 3, "howev": [3, 36, 37], "guarante": [3, 26], "have": [3, 5, 15, 17, 23, 26, 29, 33, 34, 36, 37, 38, 39, 40], "alreadi": [3, 5, 26, 37, 39], "been": 3, "still": [3, 26, 32, 36], "wait": [3, 5, 17, 20, 23, 26, 31, 32, 36, 38], "accept": [3, 6, 12, 13, 14, 33, 36, 37, 39], "inform": [3, 15, 21, 23, 35, 37, 39], "regard": 3, "error": [3, 6, 17, 36, 37, 39], "mean": [3, 21, 23, 32, 36, 37], "dure": [3, 15, 25, 30, 37, 38], "line": [3, 6, 16, 23, 25], "subsequ": 3, "access": [3, 16, 17, 19, 26, 34, 37, 38, 39], "trigger": [3, 19, 37, 39], "which": [3, 5, 6, 9, 10, 12, 15, 17, 21, 23, 24, 26, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40], "most": [3, 26, 34, 36, 37], "like": [3, 9, 26, 34, 36, 37], "For": [3, 16, 23, 31, 32, 34, 35, 37, 39, 40], "32": [3, 9, 12, 13, 16, 17, 26, 34, 37], "128": [3, 9, 16], "set": [3, 6, 9, 12, 15, 16, 19, 20, 21, 25, 31, 33, 36, 37, 39, 40], "size": [3, 16, 17, 26, 34, 37, 39], "equal": [3, 20, 37], "31": [3, 9], "15": [3, 9], "14": [3, 9], "13": [3, 9], "12": [3, 9], "11": [3, 9, 23, 33], "10": [3, 9, 26], "09": 3, "08": 3, "07": 3, "06": [3, 38], "05": 3, "04": 3, "03": 3, "02": 3, "01": 3, "00": 3, "tag": [3, 17, 26, 31, 32], "index": [3, 35, 36, 40], "offset": 3, "decod": [4, 8, 12, 15, 21, 35, 39], "decode_stag": [4, 8], "instr_decod": [4, 8], "instr_descript": [4, 8], "isa": [4, 8, 10, 16, 19], "optyp": [4, 8, 12, 15, 16, 21], "rvc": [4, 8, 10], "alu": [4, 11, 16], "div_unit": [4, 11], "except": [4, 5, 9, 11, 16, 18, 25, 29, 36, 38, 39], "jumpbranch": [4, 11, 16, 37], "mul_unit": [4, 11], "shift_unit": [4, 11, 16], "zbc": [4, 11, 16], "zb": [4, 11, 16], "interfac": [4, 6, 9, 11, 13, 15, 17, 21, 25, 33, 34, 36, 37], "func_blocks_unifi": [4, 11], "func_protocol": [4, 11, 21], "lsu": [4, 11, 16], "dummylsu": [4, 11, 16], "pma": [4, 11, 16], "csr": [4, 9, 16, 18], "csr_instanc": [4, 18], "csr_regist": [4, 18], "trap": [4, 18], "instr_count": [4, 18], "interrupt_control": [4, 18], "class": [4, 5, 6, 7, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 34, 35, 36, 37, 38, 39, 40], "base": [4, 5, 6, 7, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 26, 35, 36, 37, 38, 39, 40], "elaborat": [4, 5, 6, 7, 9, 10, 12, 13, 14, 15, 17, 19, 20, 21, 34, 35, 36, 37, 38, 39], "__init__": [4, 5, 6, 7, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 34, 35, 36, 37, 38, 39, 40], "gen_param": [4, 5, 7, 9, 10, 12, 13, 14, 15, 16, 19, 20, 21], "wb_instr_bu": 4, "wishboneinterfac": [4, 17], "wb_data_bu": 4, "resultannounc": 5, "simpl": [5, 6, 9, 10, 15, 21, 36, 37, 39, 40], "It": [5, 9, 10, 12, 13, 15, 17, 21, 23, 26, 30, 31, 33, 34, 35, 36, 37, 38, 39, 40], "take": [5, 9, 17, 30, 31, 34, 36, 37, 38, 39], "execut": [5, 9, 12, 17, 21, 23, 25, 30, 32, 34, 35, 36, 37, 38], "instruct": [5, 6, 9, 10, 12, 15, 16, 19, 20, 21, 25, 26, 30, 31, 33], "send": [5, 9, 10, 16, 17, 21], "its": [5, 9, 19, 21, 26, 33, 34, 36, 37, 39, 40], "mark": [5, 25, 26, 35], "complet": [5, 17, 26], "store": [5, 9, 15, 16, 20, 26, 31, 32, 36, 37, 39], "valu": [5, 6, 9, 12, 15, 16, 17, 19, 20, 21, 25, 29, 31, 32, 35, 36, 37, 38, 39, 40], "also": [5, 23, 33, 34, 37, 38], "sent": [5, 17, 38], "get_result": [5, 14, 15, 37], "serial": [5, 15, 37], "so": [5, 17, 26, 33, 34, 35, 36, 37], "we": [5, 6, 15, 17, 26, 30, 31, 32, 33, 34, 38], "more": [5, 23, 25, 26, 37, 39], "than": [5, 26, 37, 39], "connect": [5, 9, 17, 19, 26, 34, 36, 37], "manytooneconnecttran": [5, 37], "rob_mark_don": 5, "rs_updat": 5, "rf_write": 5, "paramet": [5, 6, 9, 10, 12, 13, 15, 16, 17, 19, 20, 21, 34, 36, 37, 38, 39, 40], "instanc": [5, 6, 9, 10, 15, 21, 33, 35, 36, 37, 38, 39], "us": [5, 6, 9, 10, 12, 13, 15, 16, 17, 19, 20, 21, 25, 26, 29, 33, 34, 36, 37, 38, 39, 40], "gener": [5, 6, 9, 10, 12, 13, 15, 16, 17, 19, 21, 23, 24, 26, 29, 33, 35, 36, 37, 38, 39], "next": [5, 6, 9, 10, 15, 21, 26, 36, 40], "readi": [5, 6, 15, 17, 19, 21, 25, 31, 35, 36, 37], "assum": [5, 12, 26, 37, 39], "differ": [5, 12, 17, 23, 24, 26, 29, 33, 36, 37, 39], "end": [5, 15, 26, 36, 37], "without": [5, 21, 26, 36, 37, 39], "pass": [5, 23, 25, 33, 36, 37, 38, 39], "finish": [5, 17, 20, 37], "rob_peek": 5, "rob_retir": 5, "r_rat_commit": 5, "r_rat_peek": 5, "free_rf_put": 5, "rf_free": 5, "precommit": [5, 15, 23], "exception_cause_get": 5, "exception_cause_clear": 5, "frat_renam": 5, "fetch_continu": 5, "instr_decr": 5, "trap_entri": 5, "cacheinterfac": [6, 10], "A": [6, 16, 17, 33, 34, 35, 36, 37, 39], "associ": [6, 16, 37], "replac": [6, 13, 16, 31], "polici": 6, "pseudo": 6, "random": [6, 38], "scheme": 6, "everi": [6, 12, 17, 23, 33, 36, 37], "time": [6, 17, 19, 26, 36, 37], "trash": 6, "select": [6, 9, 12, 14, 15, 17, 21, 23], "wai": [6, 12, 17, 23, 26, 33, 34, 36, 37, 39], "keep": [6, 36], "global": [6, 19, 26], "counter": [6, 16, 19, 20, 23, 37], "abstract": [6, 13, 16, 33, 37, 39], "awai": 6, "need": [6, 17, 23, 26, 31, 34, 36], "two": [6, 19, 26, 29, 33, 34, 36, 37, 38, 39], "refiller_start": 6, "call": [6, 19, 20, 21, 23, 29, 31, 34, 35, 36, 37, 38, 39], "whenev": [6, 37], "refiller_accept": 6, "word": [6, 16], "written": [6, 19, 32, 33, 37], "last": [6, 20, 21, 36, 37], "when": [6, 17, 20, 23, 26, 29, 31, 32, 34, 36, 37, 38, 39, 40], "either": [6, 17, 34, 36, 37, 38, 39, 40], "transfer": [6, 17, 36, 37], "over": [6, 19, 36, 37], "shouldn": [6, 33], "t": [6, 9, 15, 16, 23, 26, 29, 31, 33, 34, 36, 37, 38, 39], "until": [6, 26, 37], "start": [6, 12, 15, 17, 26, 36, 37], "layout": [6, 9, 10, 17, 21, 23, 29, 34, 36, 37, 39], "icachelayout": 6, "icacheparamet": [6, 16], "cacherefillerinterfac": 6, "none": [6, 7, 9, 10, 12, 15, 16, 19, 35, 36, 37, 38, 39, 40], "creat": [6, 13, 17, 23, 33, 34, 36, 37, 38, 39, 40], "input": [6, 9, 12, 17, 26, 31, 32, 34, 36, 37, 40], "start_refil": 6, "accept_refil": 6, "deserialize_addr": 6, "raw_addr": 6, "dict": [6, 17, 34, 35, 36, 37, 38, 39, 40], "str": [6, 16, 17, 35, 36, 37, 38, 39, 40], "amaranth": [6, 9, 12, 16, 17, 29, 33, 34, 35, 36, 37, 38, 39, 40], "hdl": [6, 9, 12, 16, 35, 36, 37, 38, 39, 40], "_ast": [6, 9, 12, 16, 36, 37, 38, 39, 40], "serialize_addr": 6, "addr": [6, 15, 17, 37], "view": [6, 12, 15, 36, 37, 38, 39, 40], "icachebypass": 6, "bus_mast": 6, "busmasterinterfac": [6, 15, 17], "haselabor": [6, 14, 17, 35, 36, 37, 38, 40], "protocol": [6, 14, 17, 35, 36, 37], "whole": [6, 24, 26, 37], "given": [6, 15, 23, 31, 34, 35, 36, 37, 38, 39, 40], "simplecommonbuscacherefil": 6, "frat": 7, "rrat": 7, "registerfil": 7, "reorderbuff": [7, 20], "decodestag": 9, "instanti": [9, 36], "instrdecod": 9, "make": [9, 12, 23, 24, 26, 29, 33, 34, 35, 38], "actual": [9, 23, 25, 34], "combinatori": [9, 34], "manner": [9, 17], "get_raw": 9, "push_decod": 9, "raw": 9, "previou": [9, 17, 26, 37], "step": [9, 10, 21, 23, 26, 33, 34], "e": [9, 16, 23, 26, 29, 34, 37, 39, 40], "g": [9, 16, 23, 26, 29, 34, 37, 39, 40], "fetchlayout": [9, 10], "describ": [9, 10, 21, 26, 33, 35, 36, 37, 38], "decodelayout": [9, 21], "perform": [9, 12, 13, 16, 21, 23, 33, 34, 36, 37, 39, 40], "elementari": 9, "compon": [9, 16, 17, 24, 36, 37], "opcod": [9, 16, 31, 32], "funct3": [9, 12, 16], "etc": [9, 16, 34], "via": [9, 34, 36], "attribut": [9, 12, 13, 15, 16, 17, 19, 20, 35, 36, 37, 39, 40], "signal": [9, 12, 15, 16, 17, 25, 29, 35, 36, 37, 38, 39, 40], "ilen": [9, 16], "out": [9, 12, 13, 17, 24, 25, 35, 36, 37, 40], "identifi": [9, 16, 31, 37], "funct3_v": 9, "1": [9, 12, 13, 16, 19, 21, 26, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40], "funct7": [9, 12, 16], "seven": 9, "funct7_v": 9, "funct12": 9, "twelv": 9, "funct12_v": 9, "rd": [9, 16], "reg_cnt_log": 9, "address": [9, 15, 16, 17, 19, 25, 26], "regist": [9, 16, 19, 21, 26, 30, 36, 37, 39], "rd_v": 9, "rs1": [9, 16], "hold": [9, 17, 37], "first": [9, 12, 21, 26, 31, 32, 33, 34, 37, 38, 39], "rs1_v": 9, "form": [9, 16, 19, 26, 33, 37], "rs2": [9, 16], "second": [9, 12, 21, 31, 32, 33, 37], "rs2_v": 9, "imm": [9, 16], "xlen": [9, 12, 16, 19, 39], "immedi": [9, 17], "provid": [9, 12, 16, 19, 21, 33, 34, 37, 38, 39], "were": [9, 26, 34], "succ": 9, "fencetarget": 9, "successor": 9, "fenc": [9, 16], "pred": 9, "predecessor": 9, "fm": 9, "fencefm": 9, "mode": [9, 16, 23, 26], "csr_alen": [9, 16], "control": [9, 16, 17, 33, 35, 36, 37, 40], "sourc": [9, 21, 23, 31, 35, 36, 37], "type": [9, 12, 23, 36, 37, 38, 39], "defin": [9, 15, 19, 34, 36, 37, 39, 40], "kind": [9, 12, 21, 37, 39], "illeg": 9, "wa": [9, 19, 20, 23, 26, 34, 35, 36, 37, 39], "success": [9, 17, 38], "do": [9, 26, 29, 34, 36], "fit": 9, "support": [9, 15, 16, 21, 23, 25, 36, 37], "constructor": [9, 34, 36, 39], "encod": [9, 16, 26, 35, 39, 40], "object": [9, 12, 15, 16, 17, 33, 34, 35, 37, 38, 39], "repres": [9, 19, 36, 37], "singl": [9, 12, 13, 16, 20, 21, 34, 36, 37, 39], "option": [9, 12, 16, 17, 19, 23, 34, 35, 36, 37, 38, 39, 40], "exist": [9, 34], "instr_type_overrid": 9, "instrtyp": 9, "specifi": [9, 16, 17, 19, 32, 37, 38, 39], "determin": [9, 26, 33, 37, 39], "instrust": 9, "almost": 9, "correct": [9, 15, 26, 31, 32, 33], "rd_zero": 9, "bool": [9, 15, 16, 19, 35, 36, 37, 38, 39, 40], "field": [9, 15, 16, 19, 23, 31, 32, 34, 35, 36, 37, 38, 39], "constant": 9, "zero": [9, 20, 31, 37, 40], "other": [9, 19, 23, 25, 34, 35, 36, 37, 40], "accordingli": 9, "default": [9, 17, 23, 34, 35, 36, 37, 39, 40], "fals": [9, 12, 15, 16, 23, 34, 35, 36, 37, 39, 40], "rs1_zero": 9, "exceptioncaus": 9, "intenum": [9, 12, 19], "breakpoint": 9, "3": [9, 12, 19, 23, 35, 36, 39], "environment_call_from_m": 9, "environment_call_from_": 9, "9": 9, "environment_call_from_u": 9, "8": [9, 12, 13, 16, 17, 36, 37], "illegal_instruct": 9, "2": [9, 12, 13, 16, 17, 19, 33, 35, 36, 37, 39], "instruction_access_fault": 9, "instruction_address_misalign": 9, "instruction_page_fault": 9, "load_access_fault": 9, "5": [9, 12, 16, 30, 37, 38], "load_address_misalign": 9, "load_page_fault": 9, "store_access_fault": 9, "7": [9, 16], "store_address_misalign": 9, "6": [9, 16, 26], "store_page_fault": 9, "__new__": [9, 12, 16, 19, 35], "tso": 9, "intflag": [9, 12, 16, 35], "dev_i": 9, "dev_o": 9, "mem_r": 9, "mem_w": 9, "clz": 9, "1536": 9, "cpop": 9, "1538": 9, "ctz": 9, "1537": 9, "ebreak": 9, "ecal": 9, "mret": [9, 12], "770": 9, "orcb": 9, "647": 9, "rev8_32": 9, "1688": 9, "rev8_64": 9, "1720": 9, "sextb": 9, "1540": 9, "sexth": 9, "1541": 9, "sret": 9, "258": 9, "wfi": 9, "261": 9, "zexth": 9, "add": [9, 34, 36, 37, 39], "AND": 9, "andn": 9, "b": [9, 16], "bclr": [9, 12], "beq": 9, "bext": [9, 12], "bge": 9, "bgeu": 9, "binv": [9, 12], "blt": 9, "bltu": 9, "bne": 9, "bset": [9, 12], "clmul": [9, 12], "clmulh": [9, 12], "clmulr": [9, 12], "csrrc": 9, "csrrci": 9, "csrr": 9, "csrrsi": 9, "csrrw": 9, "csrrwi": 9, "d": [9, 16, 34, 36, 39], "div": [9, 12], "divu": [9, 12], "divuw": 9, "divw": 9, "fencei": 9, "h": [9, 26], "hu": 9, "jalr": 9, "max": [9, 33], "maxu": 9, "min": [9, 37], "minu": 9, "mul": [9, 12], "mulh": [9, 12], "mulhsu": [9, 12], "mulhu": [9, 12], "mulw": 9, "OR": 9, "orn": 9, "rem": [9, 12], "remu": [9, 12], "remuw": 9, "remw": 9, "rev8": 9, "rol": 9, "ror": 9, "sh1add": 9, "sh2add": 9, "sh3add": 9, "sll": 9, "slt": 9, "sltu": 9, "sr": 9, "sub": [9, 37], "w": [9, 26], "xnor": 9, "xor": 9, "36": 9, "52": 9, "20": 9, "48": 9, "muldiv": 9, "sa": 9, "sfencevma": 9, "sl": 9, "enum": [9, 12, 16, 36, 37, 38, 39], "j": [9, 16], "": [9, 16, 17, 26, 34, 35, 36, 37, 39, 40], "u": [9, 26, 33, 37, 39], "auipc": 9, "branch": [9, 26, 33, 37], "24": 9, "jal": 9, "27": 9, "25": 9, "load": [9, 15, 26, 37, 39], "load_fp": 9, "lui": 9, "misc_mem": 9, "op": 9, "op32": 9, "op_imm": 9, "op_imm_32": 9, "store_fp": 9, "system": [9, 33, 34, 39], "28": [9, 26], "a0": 9, "a1": 9, "a2": 9, "a3": 9, "a4": 9, "a5": 9, "a6": 9, "a7": 9, "17": 9, "fp": [9, 35], "gp": [9, 12, 20], "ra": 9, "s0": 9, "s1": 9, "s10": 9, "26": 9, "s11": 9, "s2": 9, "18": 9, "s3": 9, "19": 9, "s4": 9, "s5": 9, "21": 9, "s6": 9, "22": 9, "s7": 9, "23": 9, "s8": 9, "s9": 9, "sp": 9, "t0": 9, "t1": [9, 34], "t2": [9, 34], "t3": 9, "t4": 9, "29": 9, "t5": 9, "30": [9, 26], "t6": 9, "tp": [9, 39], "x1": 9, "x10": 9, "x11": 9, "x12": 9, "x13": 9, "x14": 9, "x15": 9, "x16": 9, "x17": 9, "x18": 9, "x19": 9, "x2": 9, "x20": 9, "x21": 9, "x22": 9, "x23": 9, "x24": 9, "x25": 9, "x26": 9, "x27": 9, "x28": 9, "x29": 9, "x3": 9, "x30": 9, "x31": 9, "x4": 9, "x5": 9, "x6": 9, "x7": 9, "x8": 9, "x9": 9, "confus": 9, "address_gener": 9, "arithmet": 9, "bit_manipul": 9, "bit_rot": 9, "compar": [9, 25], "csr_imm": 9, "csr_reg": 9, "div_rem": 9, "34": 9, "intern": [9, 16, 25, 34, 36, 37], "caus": [9, 26, 37, 39], "befor": [9, 17, 20, 23, 29, 30, 34, 36, 37], "logic": [9, 26, 32, 33, 34], "33": 9, "shift": [9, 11, 12, 16], "single_bit_manipul": 9, "unary_bit_manipulation_1": 9, "unary_bit_manipulation_2": 9, "unary_bit_manipulation_3": 9, "unary_bit_manipulation_4": 9, "unary_bit_manipulation_5": 9, "unknown": [9, 23, 35, 37, 39], "optypes_required_by_extens": 9, "resolve_impl": 9, "true": [9, 15, 16, 17, 34, 35, 36, 37, 38, 39, 40], "ignore_unsupport": 9, "instrdecompress": 9, "decompr_reg": 9, "rvc_reg": 9, "instr_mux": 9, "sel": [9, 17], "list": [9, 12, 16, 17, 19, 23, 25, 29, 33, 35, 36, 37, 38, 39, 40], "int": [9, 12, 13, 15, 16, 17, 19, 35, 36, 37, 38, 39, 40], "valuecast": [9, 16, 36, 37, 38, 39], "tupl": [9, 12, 17, 19, 21, 35, 36, 37, 39], "is_instr_compress": 9, "pc": [10, 25], "insid": [10, 33, 34, 36, 37], "increment": [10, 19, 20], "ilen_byt": 10, "cont": [10, 38], "unalignedfetch": 10, "work": [10, 21, 26, 29, 33, 34, 36, 37], "unalign": 10, "unsigned_multipl": [11, 12], "common": [11, 12, 17, 36, 37, 39], "fast_recurs": [11, 12], "sequenc": [11, 12, 21, 37], "alucompon": [12, 16], "functionalcomponentparam": [12, 16], "zba_en": 12, "zbb_enabl": 12, "get_modul": [12, 15, 16], "funcunit": [12, 14, 16], "get_optyp": [12, 15, 16], "alufuncunit": 12, "alu_fn": 12, "alufn": 12, "divcompon": 12, "ipc": [12, 33], "div_fn": 12, "divfn": 12, "decodermanag": 12, "fn": 12, "get_instruct": 12, "valid": [12, 17, 21, 31, 37, 39, 40], "implement": [12, 15, 17, 24, 25, 26, 30, 37, 39, 40], "format": [12, 23, 33, 34, 35, 36, 37, 39], "divunit": 12, "get_input": 12, "arg": [12, 17, 34, 35, 36, 37, 38, 39, 40], "exceptionfuncunit": 12, "unit_fn": 12, "exceptionunitfn": 12, "exceptionunitcompon": [12, 16], "jumpbranchfuncunit": 12, "jb_fn": 12, "jumpbranchfn": 12, "jumpcompon": [12, 16], "mulcompon": 12, "mul_unit_typ": 12, "multyp": 12, "dsp_width": [12, 13], "mul_fn": 12, "mulfn": 12, "hot": [12, 26, 40], "wire": 12, "recursive_mul": 12, "fastest": 12, "multipli": [12, 13], "onli": [12, 17, 19, 20, 26, 33, 34, 35, 36, 37, 38, 39], "costli": [12, 26], "term": 12, "resourc": [12, 20, 26, 33, 34, 36], "sequence_mul": 12, "dsp": [12, 13], "balanc": 12, "between": [12, 23, 26, 34, 36, 37, 39, 40], "cost": [12, 25, 34], "shift_mul": 12, "cheapest": 12, "russian": [12, 13], "peasant": [12, 13], "algorithm": [12, 13], "mulunit": 12, "respons": [12, 17, 21, 23, 36, 37, 38], "unsign": [12, 13], "integ": [12, 16, 38, 39], "standard": [12, 26, 33, 37, 40], "funcunitlayout": [12, 21], "comput": [12, 13, 15, 20, 26, 37, 39], "mul_typ": 12, "privilegedfn": 12, "classmethod": [12, 35, 36, 37, 39], "privilegedfuncunit": 12, "privilegedunitcompon": [12, 16], "shiftfuncunit": 12, "shift_unit_fn": 12, "shiftunitfn": 12, "shiftunitcompon": [12, 16], "clmultipli": 12, "carri": [12, 16, 33], "less": [12, 16], "product": [12, 37], "i1": [12, 13], "n": [12, 13, 16], "factor": 12, "i2": [12, 13], "reset": [12, 19, 25, 36], "new": [12, 15, 17, 20, 25, 26, 36, 37, 39, 40], "busi": 12, "while": [12, 36, 38], "progress": 12, "bit_width": 12, "recursion_depth": 12, "width": [12, 13, 16, 17, 19, 37, 39, 40], "depth": [12, 17, 33, 37], "recurs": [12, 13, 33, 34, 35, 39], "parallel": [12, 37], "power": [12, 39], "iterative_modul": 12, "recursive_modul": 12, "zbccompon": 12, "zbc_fn": 12, "zbcfn": 12, "zbcunit": 12, "zbsfunction": 12, "in1": 12, "in2": 12, "zbscompon": 12, "zbsunit": 12, "zbs_fn": 12, "dspmulunit": 13, "clock": [13, 30, 33, 34, 35, 36, 37], "design": [13, 26, 34, 35], "synthesi": [13, 25], "tool": [13, 23, 33, 35], "o": [13, 26, 34, 36], "same": [13, 15, 23, 34, 36, 37, 39], "number": [13, 16, 17, 23, 26, 33, 35, 36, 37, 38, 39, 40], "mulbaseunsign": 13, "unsignedmulunitlayout": 13, "recursiveunsignedmul": 13, "see": [13, 29, 33, 34, 37], "fast": 13, "within": [13, 23], "sequentialunsignedmul": 13, "sequenti": [13, 17], "classic": [13, 26], "shiftunsignedmul": 13, "cheap": 13, "multi": 13, "funcblocksunifi": 14, "iter": [14, 16, 36, 37, 38, 39, 40], "blockcomponentparam": [14, 15, 16], "extra_methods_requir": 14, "unifierkei": [14, 37], "get_extra_method": 14, "item": [14, 39, 40], "funcblock": [14, 15, 16, 21], "insert": [14, 15, 21, 25, 26, 30, 31], "lsublockcompon": [15, 16], "get_rs_entry_count": [15, 16], "lsudummi": 15, "veri": [15, 26, 34], "all": [15, 16, 17, 20, 23, 25, 26, 29, 34, 35, 36, 37, 39, 40], "isn": [15, 33, 36], "compliant": [15, 33], "riscv": [15, 33], "spec": 15, "doesn": [15, 26, 29, 34, 37], "check": [15, 23, 26, 29, 31, 32, 33, 36, 39], "rang": [15, 36, 37, 38, 39, 40], "reserv": [15, 16, 25, 26], "place": [15, 17, 26, 31, 33, 34, 36, 37], "intruct": 15, "put": [15, 31, 33, 37], "receiv": [15, 17, 34, 36, 37], "calcul": [15, 37], "further": [15, 23, 37], "To": [15, 23, 26, 33, 37, 39], "processor": [15, 24, 25, 30], "master": [15, 17, 33], "pmacheck": 15, "physic": [15, 16, 21, 26], "memori": [15, 16, 17, 26, 36, 37], "checker": 15, "mai": [15, 23, 37, 38, 39], "part": [15, 19, 26, 30, 34, 36, 37], "combin": [15, 25, 29, 36, 37, 39], "circuit": [15, 33, 34, 36, 37, 39], "pmalayout": 15, "structlayout": [15, 36, 37, 39], "pmaregion": [15, 16], "contigu": [15, 16], "region": [15, 26], "includ": [15, 33, 34, 36, 37, 39, 40], "both": [15, 31, 34, 36, 37, 39], "begin": [15, 26], "mmio": 15, "indic": [15, 26, 32, 36, 37], "coreconfigur": 16, "func_units_config": 16, "collect": [16, 19, 24, 33, 35, 36, 37, 38, 39, 40], "station": [16, 25], "exampl": [16, 19, 23, 25, 31, 34, 36, 37, 40], "rsblockcompon": 16, "rs_entri": 16, "compress": 16, "enabl": [16, 37, 38, 39], "embed": 16, "reduc": [16, 26, 36], "debug": [16, 23, 37, 39], "hardwar": [16, 25, 30, 34, 37], "disabl": [16, 35, 37, 38], "them": [16, 23, 26, 33, 34, 36, 37, 39], "synthes": [16, 33, 37], "phys_regs_bit": 16, "file": [16, 23, 26, 33, 39], "rob_entries_bit": 16, "reorder": [16, 26, 37], "buffer": [16, 17, 26, 31, 37], "start_pc": 16, "initi": [16, 17, 25, 37, 38], "program": [16, 26, 33, 34], "icache_en": 16, "bypass": 16, "directli": [16, 34, 36], "icache_wai": 16, "icache_sets_bit": 16, "icache_block_size_bit": 16, "allow_partial_extens": 16, "allow": [16, 24, 26, 33, 34, 36, 37, 40], "partial": [16, 35, 37, 39], "_implied_extens": 16, "extenst": 16, "flag": 16, "definit": [16, 25, 36], "per": [16, 33], "segment": 16, "abc": [16, 36, 37, 38, 39, 40], "func_unit": 16, "csrblockcompon": 16, "factori": [16, 35, 37, 39], "kwarg": [16, 17, 35, 36, 37, 38, 39, 40], "optypes_support": 16, "dependentcach": [16, 39], "cfg": 16, "addr_width": [16, 17], "length": [16, 26, 36, 39], "word_width": 16, "machin": [16, 19], "num_of_wai": 16, "num_of_sets_bit": 16, "block_size_bit": 16, "btypeinstr": 16, "riscvinstr": 16, "static": [16, 35, 36, 39], "pack": 16, "ebreakinstr": 16, "itypeinstr": 16, "illegalinstr": 16, "jtypeinstr": 16, "rtypeinstr": 16, "stypeinstr": 16, "utypeinstr": 16, "avail": [16, 17, 19, 21, 23, 24, 33, 37], "atom": [16, 31, 34], "512": 16, "manipul": 16, "256": 16, "doubl": [16, 19, 26], "precis": [16, 26, 33], "float": [16, 35, 37, 38, 39], "point": [16, 26, 29, 33], "64": [16, 17], "f": [16, 21, 23, 33, 38], "98366": 16, "contain": [16, 23, 33, 34, 36, 37, 39], "basic": [16, 25, 33, 37], "full": [16, 23, 25, 26, 33, 37], "1024": 16, "dynam": [16, 26, 40], "languag": [16, 34], "l": [16, 23], "decim": 16, "m": [16, 17, 19, 20, 23, 26, 33, 34, 36, 37, 40], "divis": 16, "16384": 16, "user": [16, 19, 26, 33, 37], "level": [16, 17, 24, 26, 33, 34, 37, 38, 39], "interrupt": [16, 25], "p": [16, 23], "4096": 16, "simd": 16, "q": 16, "quad": 16, "2048": 16, "8192": 16, "vector": [16, 21, 25, 26], "xintmachinemod": 16, "8589934592": 16, "categor": 16, "privilieg": 16, "xintsupervisor": 16, "17179869184": 16, "supervisor": [16, 19], "zam": 16, "2097152": 16, "misalign": 16, "zba": 16, "268435456": 16, "extend": [16, 29, 36], "zbb": 16, "536870912": 16, "1073741824": 16, "2147483648": 16, "zdinx": 16, "33554432": 16, "zfh": 16, "4194304": 16, "half": 16, "zfhmin": 16, "8388608": 16, "minim": 16, "zfinx": 16, "16777216": 16, "zhinx": 16, "67108864": 16, "zicntr": 16, "524288": 16, "timer": [16, 19], "zicsr": 16, "32768": 16, "statu": [16, 19, 38], "zifencei": 16, "65536": 16, "zihintntl": 16, "262144": 16, "non": [16, 31, 36, 37, 38], "tempor": 16, "local": [16, 20, 23], "hint": [16, 36], "zihintpaus": 16, "131072": 16, "paus": 16, "energi": 16, "zihpm": 16, "1048576": 16, "zmmul": 16, "134217728": 16, "ztso": 16, "4294967296": 16, "total": 16, "gather": 16, "numer": 16, "val": [16, 39], "correspond": [16, 31, 36, 40], "val_log": 16, "relev": [16, 35], "nativ": 16, "reg_cnt": 16, "maximum": [16, 33, 37], "bitwis": 16, "isa_str": 16, "string": [16, 37, 38], "pleas": [16, 23, 29, 34], "refer": [16, 35, 39], "gcc": 16, "arch": [16, 23, 33], "detail": [16, 20, 25, 37], "axiliteinterfac": 17, "abstractinterfac": 17, "abstractsignatur": 17, "read_address": 17, "axilitereadaddressinterfac": 17, "read_data": 17, "axilitereaddatainterfac": 17, "write_address": 17, "axilitewriteaddressinterfac": 17, "write_data": 17, "axilitewritedatainterfac": 17, "write_respons": 17, "axilitewriteresponseinterfac": 17, "axilitemast": 17, "axi": 17, "lite": 17, "axil_param": 17, "axiliteparamet": 17, "ra_request": 17, "channel": 17, "being": [17, 23, 37, 39, 40], "ra_request_layout": 17, "argument": [17, 21, 23, 25, 32, 33, 36, 37, 38, 39, 40], "rd_respons": 17, "availab": 17, "state": [17, 25, 26, 34, 36, 37, 38], "rd_response_layout": 17, "wa_request": 17, "wa_request_layout": 17, "wd_request": 17, "wd_request_layout": 17, "wr_respons": 17, "wr_response_layout": 17, "axil_mast": 17, "result_handl": 17, "start_request_transact": 17, "is_address_channel": 17, "state_machine_request": 17, "request_sign": 17, "data_width": 17, "must": [17, 36, 37, 39], "axilitesignatur": 17, "signatur": 17, "patamet": 17, "axilitemasteradapt": 17, "where": [17, 21, 23, 26, 31, 32, 34, 36, 37, 38, 39], "expect": 17, "busparametersinterfac": 17, "method_layout": 17, "commonbusmastermethodlayout": 17, "request_read": 17, "underli": 17, "request_read_layout": 17, "request_writ": 17, "request_write_layout": 17, "get_read_respons": 17, "action": [17, 19, 36, 37, 39], "read_response_layout": 17, "get_write_respons": 17, "write_response_layout": 17, "prefer": [17, 34], "gain": 17, "simplifi": 17, "interchang": 17, "buse": 17, "previous": 17, "wishbonemasteradapt": 17, "wishbonemast": 17, "pipelinedwishbonemast": 17, "wb_param": 17, "wishboneparamet": 17, "max_req": 17, "limit": [17, 34, 37], "pend": 17, "wb": 17, "request_layout": 17, "result_layout": 17, "requests_finish": 17, "generate_method_layout": 17, "wishbonearbit": 17, "arbit": 17, "slave": 17, "assert": [17, 37, 40], "cyc": 17, "grant": [17, 34, 35, 36, 37, 40], "round": [17, 36, 39, 40], "robin": [17, 36, 40], "num_slav": 17, "devic": 17, "slave_wb": 17, "intefac": 17, "num_mast": 17, "ack": 17, "adr": 17, "dat_r": 17, "dat_w": 17, "err": 17, "lock": [17, 23, 26, 34, 35, 37], "rst": 17, "rty": 17, "stall": [17, 26], "stb": 17, "name": [17, 23, 34, 35, 36, 37, 38, 39, 40], "wb_master": 17, "becom": 17, "wishbonemastermethodlayout": 17, "wishbonememoryslav": 17, "underneath": 17, "keyword": [17, 34, 36, 37, 38, 39], "thei": [17, 19, 23, 26, 30, 33, 34, 36, 37], "re": [17, 26, 29, 34, 36], "infer": [17, 36], "wishbonemux": 17, "muxer": 17, "multiplex": [17, 34], "ssel_tga": 17, "corespond": 17, "tga": 17, "note": [17, 19, 37], "stare": 17, "clear": [17, 31, 32, 37], "delai": [17, 34], "deassert": [17, 40], "master_wb": 17, "singal": 17, "granular": [17, 37], "smallest": 17, "port": [17, 36, 37, 39, 40], "capabl": 17, "wishbonesignatur": 17, "path": [17, 36, 37], "src_loc_at": [17, 37], "csraddress": 19, "3072": 19, "cycleh": 19, "3200": 19, "instret": 19, "3074": 19, "instreth": 19, "3202": 19, "mcaus": 19, "834": 19, "mepc": 19, "833": 19, "mtvec": 19, "773": 19, "3073": 19, "timeh": 19, "3201": 19, "doublecountercsr": 19, "group": 19, "csrregist": 19, "At": 19, "overflow": [19, 37], "low_addr": 19, "high_addr": 19, "lower": [19, 39], "higher": 19, "synthetis": 19, "genericcsrregist": 19, "machinemodecsrregist": 19, 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+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
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diff --git a/shared-structs/rs.html b/shared-structs/rs.html
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+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
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+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
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+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
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+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
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+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
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+      <span class="lastupdated">Last updated on 21:22 2024-03-24.
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