diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index 47e17ded4..4eda203e7 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index 48a695f2a..0773c04f1 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/coreblocks.func_blocks.fu.doctree b/.doctrees/coreblocks.func_blocks.fu.doctree index b88a966bd..4c567d5d4 100644 Binary files a/.doctrees/coreblocks.func_blocks.fu.doctree and b/.doctrees/coreblocks.func_blocks.fu.doctree differ diff --git a/.doctrees/coreblocks.priv.traps.doctree b/.doctrees/coreblocks.priv.traps.doctree index 287418bd8..0b4f2d09e 100644 Binary files a/.doctrees/coreblocks.priv.traps.doctree and b/.doctrees/coreblocks.priv.traps.doctree differ diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree index 5bed826f9..463cde5e9 100644 Binary files a/.doctrees/current-graph.doctree and b/.doctrees/current-graph.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index a6c1d42ac..c17477fde 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/.doctrees/transactron.utils.doctree b/.doctrees/transactron.utils.doctree index 18e0cbb25..aacf910df 100644 Binary files a/.doctrees/transactron.utils.doctree and b/.doctrees/transactron.utils.doctree differ diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 757b03fa7..e1832a581 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -15,69 +15,69 @@ end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] + WishboneMaster1_request["request"] WishboneMaster1_WishboneMaster["WishboneMaster"] WishboneMaster1_result["result"] - WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] Forwarder1_read["read"] Forwarder1_write["write"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_write["write"] BasicFifo_read["read"] + BasicFifo_write["write"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_request_read["request_read"] - WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_get_read_response["get_read_response"] + WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_write["write"] BasicFifo1_read["read"] + BasicFifo1_write["write"] end end end subgraph CoreFrontend["frontend CoreFrontend"] - CoreFrontend_target_pred_resp["target_pred_resp"] - CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] CoreFrontend_stall["stall"] + CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] CoreFrontend_target_pred_req["target_pred_req"] + CoreFrontend_target_pred_resp["target_pred_resp"] subgraph BasicFifo2["instr_buffer BasicFifo"] - BasicFifo2_write["write"] BasicFifo2_read["read"] BasicFifo2_clear["clear"] + BasicFifo2_write["write"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end end subgraph ICache["icache ICache"] ICache_MemRead["MemRead"] ICache_ICache["ICache"] ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] ICache_ICache1["ICache"] ICache_flush["flush"] + ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -100,35 +100,35 @@ HwExpHistogram__add["_add"] end subgraph FIFO["fifo FIFO"] - FIFO_write["write"] FIFO_read["read"] + FIFO_write["write"] end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_write_results["write_results"] - ArgumentsToResultsZipper_read["read"] ArgumentsToResultsZipper_write_args["write_args"] ArgumentsToResultsZipper_peek_arg["peek_arg"] + ArgumentsToResultsZipper_write_results["write_results"] + ArgumentsToResultsZipper_read["read"] subgraph BasicFifo3["fifo BasicFifo"] BasicFifo3_read["read"] BasicFifo3_peek["peek"] BasicFifo3_write["write"] end subgraph Forwarder3["forwarder Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end end subgraph FetchUnit["fetch FetchUnit"] + FetchUnit_Fetch_Stage1["Fetch_Stage1"] + FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] FetchUnit_resume_from_exception["resume_from_exception"] - FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] FetchUnit_Fetch_Stage2["Fetch_Stage2"] - FetchUnit_resume_from_unsafe["resume_from_unsafe"] - FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] - FetchUnit_Fetch_Stage1["Fetch_Stage1"] - FetchUnit_stall_exception["stall_exception"] FetchUnit_Fetch_Stage0["Fetch_Stage0"] + FetchUnit_stall_exception["stall_exception"] + FetchUnit_resume_from_unsafe["resume_from_unsafe"] + FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] end @@ -137,8 +137,8 @@ end subgraph Serializer["serializer Serializer"] Serializer_clean["clean"] - Serializer_read["read"] Serializer_write["write"] + Serializer_read["read"] end subgraph ConnectTrans["serializer_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -148,8 +148,8 @@ BasicFifo4_write["write"] end subgraph Semaphore["req_counter Semaphore"] - Semaphore_release["release"] Semaphore_acquire["acquire"] + Semaphore_release["release"] end subgraph Pipe["s1_s2_pipe Pipe"] Pipe_read["read"] @@ -172,9 +172,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] - Pipe1_read["read"] - Pipe1_write["write"] Pipe1_clean["clean"] + Pipe1_write["write"] + Pipe1_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -195,20 +195,20 @@ RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read2["read2"] + RegisterFile_write["write"] RegisterFile_free["free"] RegisterFile_perf["perf"] + RegisterFile_read2["read2"] RegisterFile_read1["read1"] - RegisterFile_write["write"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer__stop["_stop"] TaggedLatencyMeasurer__start["_start"] + TaggedLatencyMeasurer__stop["_stop"] subgraph HwExpHistogram1["histogram HwExpHistogram"] HwExpHistogram1__add["_add"] end subgraph AsyncMemoryBank["slots AsyncMemoryBank"] - AsyncMemoryBank_read["read"] AsyncMemoryBank_write["write"] + AsyncMemoryBank_read["read"] end end subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] @@ -217,14 +217,14 @@ end subgraph ReorderBuffer["ROB ReorderBuffer"] ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_perf["perf"] - ReorderBuffer_peek["peek"] + ReorderBuffer_retire["retire"] ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_retire["retire"] + ReorderBuffer_perf["perf"] + ReorderBuffer_peek["peek"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] - FIFOLatencyMeasurer1__stop["_stop"] FIFOLatencyMeasurer1__start["_start"] + FIFOLatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram3["histogram HwExpHistogram"] HwExpHistogram3__add["_add"] end @@ -237,13 +237,13 @@ HwExpHistogram4__add["_add"] end end - subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_get["get"] - ExceptionCauseRegister_clear["clear"] - ExceptionCauseRegister_report["report"] + subgraph ExceptionInformationRegister["exception_information_register ExceptionInformationRegister"] + ExceptionInformationRegister_report["report"] + ExceptionInformationRegister_clear["clear"] + ExceptionInformationRegister_get["get"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] - BasicFifo6_read["read"] BasicFifo6_write["write"] + BasicFifo6_read["read"] end subgraph ConnectTrans1["report_connector ConnectTrans"] ConnectTrans1_ConnectTrans["ConnectTrans"] @@ -253,8 +253,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_read["read"] Forwarder4_write["write"] + Forwarder4_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans2["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -272,30 +272,30 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_update["update"] - RSFuncBlock_select["select"] RSFuncBlock_insert["insert"] + RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] + RSFuncBlock_select["select"] subgraph RS["rs RS"] - RS_select["select"] RS_RS["RS"] - RS_RS1["RS"] RS_insert["insert"] + RS_RS1["RS"] + RS_take["take"] RS_RS2["RS"] RS_perf["perf"] RS_RS3["RS"] RS_RS4["RS"] - RS_take["take"] RS_update["update"] + RS_select["select"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__stop["_stop"] TaggedLatencyMeasurer1__start["_start"] + TaggedLatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_read["read"] AsyncMemoryBank1_write["write"] + AsyncMemoryBank1_read["read"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -303,22 +303,22 @@ end end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph TaggedCounter4["perf_instr TaggedCounter"] TaggedCounter4__incr["_incr"] end subgraph FIFO2["fifo FIFO"] - FIFO2_write["write"] FIFO2_read["read"] + FIFO2_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_issue["issue"] ShiftFuncUnit_accept["accept"] + ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] FIFO3_write["write"] FIFO3_read["read"] @@ -328,8 +328,8 @@ WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO4["fifo_branch_resolved FIFO"] FIFO4_read["read"] FIFO4_write["write"] @@ -344,8 +344,8 @@ HwCounter8__incr["_incr"] end subgraph BasicFifo7["instr_fifo BasicFifo"] - BasicFifo7_read["read"] BasicFifo7_write["write"] + BasicFifo7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -363,16 +363,16 @@ WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] PrivilegedFuncUnit_issue["issue"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] - BasicFifo8_read["read"] BasicFifo8_write["write"] + BasicFifo8_read["read"] end subgraph TaggedCounter6["perf_instr TaggedCounter"] TaggedCounter6__incr["_incr"] @@ -384,8 +384,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_read["read"] Forwarder5_write["write"] + Forwarder5_read["read"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans5["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -407,26 +407,26 @@ end end subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] - RSFuncBlock1_insert["insert"] RSFuncBlock1_update["update"] - RSFuncBlock1_select["select"] + RSFuncBlock1_insert["insert"] RSFuncBlock1_get_result["get_result"] + RSFuncBlock1_select["select"] subgraph FifoRS["rs FifoRS"] - FifoRS_FifoRS["FifoRS"] FifoRS_update["update"] - FifoRS_take["take"] FifoRS_insert["insert"] FifoRS_perf["perf"] + FifoRS_take["take"] FifoRS_select["select"] + FifoRS_FifoRS["FifoRS"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer2__start["_start"] TaggedLatencyMeasurer2__stop["_stop"] + TaggedLatencyMeasurer2__start["_start"] subgraph HwExpHistogram7["histogram HwExpHistogram"] HwExpHistogram7__add["_add"] end subgraph AsyncMemoryBank2["slots AsyncMemoryBank"] - AsyncMemoryBank2_read["read"] AsyncMemoryBank2_write["write"] + AsyncMemoryBank2_read["read"] end end subgraph HwExpHistogram8["perf_num_full HwExpHistogram"] @@ -434,21 +434,21 @@ end end subgraph LSUDummy["func_unit_0 LSUDummy"] - LSUDummy_accept_cond1["accept_cond1"] - LSUDummy_LSUDummy["LSUDummy"] LSUDummy_accept_cond0["accept_cond0"] + LSUDummy_LSUDummy["LSUDummy"] LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_issue["issue"] LSUDummy_accept["accept"] - LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_accept_cond1["accept_cond1"] subgraph LSURequester["requester LSURequester"] - LSURequester_accept_cond1["accept_cond1"] - LSURequester_issue_cond0["issue_cond0"] - LSURequester_issue_cond1["issue_cond1"] + LSURequester_accept["accept"] LSURequester_issue_cond2["issue_cond2"] + LSURequester_accept_cond1["accept_cond1"] LSURequester_accept_cond0["accept_cond0"] LSURequester_issue["issue"] - LSURequester_accept["accept"] + LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond0["issue_cond0"] subgraph BasicFifo9["args_fifo BasicFifo"] BasicFifo9_write["write"] BasicFifo9_read["read"] @@ -459,12 +459,12 @@ Forwarder6_read["read"] end subgraph FIFO6["results_noop FIFO"] - FIFO6_write["write"] FIFO6_read["read"] + FIFO6_write["write"] end subgraph FIFO7["issued FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end subgraph FIFO8["issued_noop FIFO"] FIFO8_read["read"] @@ -477,8 +477,8 @@ subgraph Collector2["collector Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_write["write"] Forwarder7_read["read"] + Forwarder7_write["write"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans10["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -488,13 +488,13 @@ end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_select["select"] CSRUnit_fetch_resume["fetch_resume"] - CSRUnit_CSRUnit["CSRUnit"] - CSRUnit_get_result["get_result"] + CSRUnit_insert["insert"] CSRUnit_update["update"] + CSRUnit_select["select"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_CSRUnit1["CSRUnit"] - CSRUnit_insert["insert"] + CSRUnit_get_result["get_result"] end end subgraph ResultAnnouncement["announcement ResultAnnouncement"] @@ -555,9 +555,9 @@ AliasedCSR1__fu_read["_fu_read"] end subgraph CSRRegister6["mcause CSRRegister"] + CSRRegister6__internal_fu_read["_internal_fu_read"] CSRRegister6_write["write"] CSRRegister6__internal_fu_write["_internal_fu_write"] - CSRRegister6__internal_fu_read["_internal_fu_read"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -570,8 +570,8 @@ end subgraph CSRRegister7["mtvec CSRRegister"] CSRRegister7__internal_fu_read["_internal_fu_read"] - CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7_read["read"] + CSRRegister7__internal_fu_write["_internal_fu_write"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] end @@ -584,9 +584,9 @@ end subgraph CSRRegister8["mepc CSRRegister"] CSRRegister8__internal_fu_read["_internal_fu_read"] + CSRRegister8_write["write"] CSRRegister8__internal_fu_write["_internal_fu_write"] CSRRegister8_read["read"] - CSRRegister8_write["write"] subgraph MethodMap16["fu_write_map MethodMap"] MethodMap16_method["method"] end @@ -597,30 +597,29 @@ MethodMap17_method["method"] end end - subgraph CSRRegister9["priv_mode CSRRegister"] - CSRRegister9_read["read"] + subgraph CSRRegister9["mtval CSRRegister"] + CSRRegister9__internal_fu_write["_internal_fu_write"] CSRRegister9_write["write"] - end - subgraph CSRRegister10["mstatus_mie CSRRegister"] - CSRRegister10_write["write"] - CSRRegister10__internal_fu_write["_internal_fu_write"] - CSRRegister10_read["read"] - CSRRegister10__internal_fu_read["_internal_fu_read"] - subgraph MethodMap20["fu_write_map MethodMap"] - MethodMap20_method["method"] + CSRRegister9__internal_fu_read["_internal_fu_read"] + subgraph MethodMap18["fu_write_map MethodMap"] + MethodMap18_method["method"] end - subgraph MethodFilter10["fu_write_filter MethodFilter"] - MethodFilter10_method["method"] + subgraph MethodFilter9["fu_write_filter MethodFilter"] + MethodFilter9_method["method"] end - subgraph MethodMap21["fu_read_map MethodMap"] - MethodMap21_method["method"] + subgraph MethodMap19["fu_read_map MethodMap"] + MethodMap19_method["method"] end end - subgraph CSRRegister11["mstatus_mpie CSRRegister"] - CSRRegister11__internal_fu_read["_internal_fu_read"] + subgraph CSRRegister10["priv_mode CSRRegister"] + CSRRegister10_write["write"] + CSRRegister10_read["read"] + end + subgraph CSRRegister11["mstatus_mie CSRRegister"] CSRRegister11_write["write"] CSRRegister11__internal_fu_write["_internal_fu_write"] CSRRegister11_read["read"] + CSRRegister11__internal_fu_read["_internal_fu_read"] subgraph MethodMap22["fu_write_map MethodMap"] MethodMap22_method["method"] end @@ -631,11 +630,11 @@ MethodMap23_method["method"] end end - subgraph CSRRegister12["mstatus_mpp CSRRegister"] + subgraph CSRRegister12["mstatus_mpie CSRRegister"] CSRRegister12__internal_fu_read["_internal_fu_read"] - CSRRegister12_read["read"] - CSRRegister12_write["write"] CSRRegister12__internal_fu_write["_internal_fu_write"] + CSRRegister12_write["write"] + CSRRegister12_read["read"] subgraph MethodMap24["fu_write_map MethodMap"] MethodMap24_method["method"] end @@ -646,10 +645,11 @@ MethodMap25_method["method"] end end - subgraph CSRRegister13["mstatus_mprv CSRRegister"] - CSRRegister13__internal_fu_write["_internal_fu_write"] + subgraph CSRRegister13["mstatus_mpp CSRRegister"] CSRRegister13__internal_fu_read["_internal_fu_read"] + CSRRegister13_read["read"] CSRRegister13_write["write"] + CSRRegister13__internal_fu_write["_internal_fu_write"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -660,10 +660,10 @@ MethodMap27_method["method"] end end - subgraph CSRRegister14["mstatus_tw CSRRegister"] - CSRRegister14__internal_fu_write["_internal_fu_write"] + subgraph CSRRegister14["mstatus_mprv CSRRegister"] + CSRRegister14_write["write"] CSRRegister14__internal_fu_read["_internal_fu_read"] - CSRRegister14_read["read"] + CSRRegister14__internal_fu_write["_internal_fu_write"] subgraph MethodMap28["fu_write_map MethodMap"] MethodMap28_method["method"] end @@ -674,73 +674,71 @@ MethodMap29_method["method"] end end - end - subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] - DoubleCounterCSR_increment["increment"] - subgraph CSRRegister15["register_low CSRRegister"] - CSRRegister15_read["read"] - CSRRegister15_write["write"] + subgraph CSRRegister15["mstatus_tw CSRRegister"] CSRRegister15__internal_fu_read["_internal_fu_read"] + CSRRegister15__internal_fu_write["_internal_fu_write"] + CSRRegister15_read["read"] + subgraph MethodMap30["fu_write_map MethodMap"] + MethodMap30_method["method"] + end + subgraph MethodFilter15["fu_write_filter MethodFilter"] + MethodFilter15_method["method"] + end subgraph MethodMap31["fu_read_map MethodMap"] MethodMap31_method["method"] end end - subgraph CSRRegister16["register_high CSRRegister"] - CSRRegister16_read["read"] + end + subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] + DoubleCounterCSR_increment["increment"] + subgraph CSRRegister16["register_low CSRRegister"] CSRRegister16_write["write"] + CSRRegister16_read["read"] CSRRegister16__internal_fu_read["_internal_fu_read"] subgraph MethodMap33["fu_read_map MethodMap"] MethodMap33_method["method"] end end - end - subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] - DoubleCounterCSR1_increment["increment"] - subgraph CSRRegister17["register_low CSRRegister"] + subgraph CSRRegister17["register_high CSRRegister"] CSRRegister17_write["write"] - CSRRegister17_read["read"] CSRRegister17__internal_fu_read["_internal_fu_read"] + CSRRegister17_read["read"] subgraph MethodMap35["fu_read_map MethodMap"] MethodMap35_method["method"] end end - subgraph CSRRegister18["register_high CSRRegister"] - CSRRegister18_read["read"] + end + subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] + DoubleCounterCSR1_increment["increment"] + subgraph CSRRegister18["register_low CSRRegister"] CSRRegister18__internal_fu_read["_internal_fu_read"] CSRRegister18_write["write"] + CSRRegister18_read["read"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] end end + subgraph CSRRegister19["register_high CSRRegister"] + CSRRegister19_write["write"] + CSRRegister19_read["read"] + CSRRegister19__internal_fu_read["_internal_fu_read"] + subgraph MethodMap39["fu_read_map MethodMap"] + MethodMap39_method["method"] + end + end end end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] - InternalInterruptController_InternalInterruptController["InternalInterruptController"] - InternalInterruptController_InternalInterruptController1["InternalInterruptController"] - InternalInterruptController_InternalInterruptController2["InternalInterruptController"] InternalInterruptController_interrupt_cause["interrupt_cause"] + InternalInterruptController_InternalInterruptController["InternalInterruptController"] InternalInterruptController_mret["mret"] InternalInterruptController_entry["entry"] - subgraph CSRRegister19["mie CSRRegister"] - CSRRegister19_read["read"] - CSRRegister19__internal_fu_read["_internal_fu_read"] - CSRRegister19__internal_fu_write["_internal_fu_write"] - subgraph MethodMap38["fu_write_map MethodMap"] - MethodMap38_method["method"] - end - subgraph MethodFilter19["fu_write_filter MethodFilter"] - MethodFilter19_method["method"] - end - subgraph MethodMap39["fu_read_map MethodMap"] - MethodMap39_method["method"] - end - end - subgraph CSRRegister20["mip CSRRegister"] - CSRRegister20_read["read"] + InternalInterruptController_InternalInterruptController1["InternalInterruptController"] + InternalInterruptController_InternalInterruptController2["InternalInterruptController"] + subgraph CSRRegister20["mie CSRRegister"] CSRRegister20__internal_fu_read["_internal_fu_read"] - CSRRegister20_read_comb["read_comb"] + CSRRegister20_read["read"] CSRRegister20__internal_fu_write["_internal_fu_write"] - CSRRegister20_write["write"] subgraph MethodMap40["fu_write_map MethodMap"] MethodMap40_method["method"] end @@ -751,18 +749,34 @@ MethodMap41_method["method"] end end + subgraph CSRRegister21["mip CSRRegister"] + CSRRegister21_write["write"] + CSRRegister21_read["read"] + CSRRegister21__internal_fu_read["_internal_fu_read"] + CSRRegister21_read_comb["read_comb"] + CSRRegister21__internal_fu_write["_internal_fu_write"] + subgraph MethodMap42["fu_write_map MethodMap"] + MethodMap42_method["method"] + end + subgraph MethodFilter21["fu_write_filter MethodFilter"] + MethodFilter21_method["method"] + end + subgraph MethodMap43["fu_read_map MethodMap"] + MethodMap43_method["method"] + end + end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph MethodProduct1["get_instr MethodProduct"] MethodProduct1_method["method"] end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO9["alloc_rename_buf FIFO"] - FIFO9_write["write"] FIFO9_read["read"] + FIFO9_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -775,15 +789,15 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO11["rs_select_out_buf FIFO"] - FIFO11_read["read"] FIFO11_write["write"] + FIFO11_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -798,8 +812,8 @@ subgraph Collector3["FetchResumeKey_unifier Collector"] Collector3_method["method"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_write["write"] Forwarder8_read["read"] + Forwarder8_write["write"] end subgraph ManyToOneConnectTrans3["connect ManyToOneConnectTrans"] subgraph ConnectTrans11["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -815,32 +829,32 @@ ConnectTrans13_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] - Retirement_precommit["precommit"] - Retirement_core_state["core_state"] Retirement_Retirement1["Retirement"] + Retirement_core_state["core_state"] + Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement2["Retirement"] + Retirement_precommit["precommit"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement3["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] - subgraph CSRRegister21["register_low CSRRegister"] - CSRRegister21_read["read"] - CSRRegister21_write["write"] - CSRRegister21__internal_fu_read["_internal_fu_read"] - subgraph MethodMap43["fu_read_map MethodMap"] - MethodMap43_method["method"] - end - end - subgraph CSRRegister22["register_high CSRRegister"] - CSRRegister22__internal_fu_read["_internal_fu_read"] - CSRRegister22_read["read"] + subgraph CSRRegister22["register_low CSRRegister"] CSRRegister22_write["write"] + CSRRegister22_read["read"] + CSRRegister22__internal_fu_read["_internal_fu_read"] subgraph MethodMap45["fu_read_map MethodMap"] MethodMap45_method["method"] end end + subgraph CSRRegister23["register_high CSRRegister"] + CSRRegister23_read["read"] + CSRRegister23_write["write"] + CSRRegister23__internal_fu_read["_internal_fu_read"] + subgraph MethodMap47["fu_read_map MethodMap"] + MethodMap47_method["method"] + end + end end subgraph HwCounter9["perf_instr_ret HwCounter"] HwCounter9__incr["_incr"] @@ -852,8 +866,8 @@ HwExpHistogram9__add["_add"] end subgraph FIFO12["fifo FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end end end @@ -861,26 +875,26 @@ end subgraph TransactionManager["transaction_manager TransactionManager"] TransactionManager_ConnectTrans_accept_cond1["ConnectTrans_accept_cond1"] - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2["Fetch_Stage2_cond1_Fetch_Stage2"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] - TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] - TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] - TransactionManager_accept_cond1_ConnectTrans_accept_cond0["accept_cond1_ConnectTrans_accept_cond0"] TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0["Fetch_Stage2_Fetch_Stage2_cond0"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit["PrivilegedFuncUnit_cond2_PrivilegedFuncUnit"] TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_PrivilegedFuncUnit_cond0"] + TransactionManager_accept_cond1_accept_cond0_ConnectTrans["accept_cond1_accept_cond0_ConnectTrans"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit["PrivilegedFuncUnit_cond1_PrivilegedFuncUnit"] + TransactionManager_accept_cond0_accept_cond0_ConnectTrans["accept_cond0_accept_cond0_ConnectTrans"] + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2["Fetch_Stage2_cond1_Fetch_Stage2"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2["Fetch_Stage2_cond0_Fetch_Stage2"] + TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit["PrivilegedFuncUnit_cond0_PrivilegedFuncUnit"] end end Core_InitFreeRFFifo --> BasicFifo5_write - Retirement_Retirement3 --> BasicFifo5_write - TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write + Retirement_Retirement --> BasicFifo5_write TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write + TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify @@ -930,51 +944,51 @@ RegisterFile_perf --> HwExpHistogram2__add ReorderBuffer_perf --> HwExpHistogram4__add GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment - CSRRegister15_read --> GenericCSRRegisters_GenericCSRRegisters - GenericCSRRegisters_GenericCSRRegisters --> CSRRegister15_write CSRRegister16_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister16_write - GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR1_increment CSRRegister17_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister17_write + GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR1_increment CSRRegister18_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister18_write - CSRRegister10_read --> InternalInterruptController_InternalInterruptController - CSRRegister10_read --> InternalInterruptController_InternalInterruptController1 - CSRRegister9_read --> InternalInterruptController_InternalInterruptController - CSRRegister9_read --> InternalInterruptController_InternalInterruptController1 - CSRRegister9_read --> WakeupSelect3_WakeupSelect - CSRRegister9_read --> CSRUnit_CSRUnit - CSRRegister9_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - CSRRegister9_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - CSRRegister9_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - CSRRegister9_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - CSRRegister19_read --> InternalInterruptController_InternalInterruptController - CSRRegister20_read --> InternalInterruptController_InternalInterruptController - CSRRegister20_read_comb --> InternalInterruptController_InternalInterruptController2 - InternalInterruptController_InternalInterruptController2 --> CSRRegister20_write - InternalInterruptController_InternalInterruptController1 --> CSRRegister10_write - InternalInterruptController_InternalInterruptController1 --> CSRRegister11_write - InternalInterruptController_InternalInterruptController1 --> CSRRegister12_write - InternalInterruptController_InternalInterruptController1 --> CSRRegister9_write + CSRRegister19_read --> GenericCSRRegisters_GenericCSRRegisters + GenericCSRRegisters_GenericCSRRegisters --> CSRRegister19_write CSRRegister11_read --> InternalInterruptController_InternalInterruptController1 - CSRRegister12_read --> InternalInterruptController_InternalInterruptController1 - InternalInterruptController_InternalInterruptController1 --> CSRRegister13_write + CSRRegister11_read --> InternalInterruptController_InternalInterruptController2 + CSRRegister10_read --> InternalInterruptController_InternalInterruptController1 + CSRRegister10_read --> InternalInterruptController_InternalInterruptController2 + CSRRegister10_read --> WakeupSelect3_WakeupSelect + CSRRegister10_read --> CSRUnit_CSRUnit + CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit + CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit + CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit + CSRRegister20_read --> InternalInterruptController_InternalInterruptController1 + CSRRegister21_read --> InternalInterruptController_InternalInterruptController1 + CSRRegister21_read_comb --> InternalInterruptController_InternalInterruptController + InternalInterruptController_InternalInterruptController --> CSRRegister21_write + InternalInterruptController_InternalInterruptController2 --> CSRRegister11_write + InternalInterruptController_InternalInterruptController2 --> CSRRegister12_write + InternalInterruptController_InternalInterruptController2 --> CSRRegister13_write + InternalInterruptController_InternalInterruptController2 --> CSRRegister10_write + CSRRegister12_read --> InternalInterruptController_InternalInterruptController2 + CSRRegister13_read --> InternalInterruptController_InternalInterruptController2 + InternalInterruptController_InternalInterruptController2 --> CSRRegister14_write MethodProduct1_method --> RegAllocation_RegAllocation Pipe1_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation <--> CoreInstructionCounter_increment BasicFifo5_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO9_write - FIFO10_read --> RSSelection_RSSelection1 FIFO10_read --> RSSelection_RSSelection + FIFO10_read --> RSSelection_RSSelection1 FIFO10_read --> RSSelection_RSSelection2 - RSFuncBlock_select --> RSSelection_RSSelection1 - RS_select --> RSSelection_RSSelection1 - RSSelection_RSSelection1 --> FIFO11_write + RSFuncBlock_select --> RSSelection_RSSelection + RS_select --> RSSelection_RSSelection RSSelection_RSSelection --> FIFO11_write + RSSelection_RSSelection1 --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write - RSFuncBlock1_select --> RSSelection_RSSelection - FifoRS_select --> RSSelection_RSSelection + RSFuncBlock1_select --> RSSelection_RSSelection1 + FifoRS_select --> RSSelection_RSSelection1 RSSelection_RSSelection2 <--> CSRUnit_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion @@ -990,7 +1004,7 @@ RSInsertion_RSInsertion --> AsyncMemoryBank2_write RSInsertion_RSInsertion --> CSRUnit_insert BasicFifo6_read --> ConnectTrans1_ConnectTrans - ConnectTrans1_ConnectTrans --> ExceptionCauseRegister_report + ConnectTrans1_ConnectTrans --> ExceptionInformationRegister_report ReorderBuffer_get_indices --> ConnectTrans1_ConnectTrans ConnectTrans1_ConnectTrans <--> CoreFrontend_stall ConnectTrans1_ConnectTrans <--> FetchUnit_stall_exception @@ -1041,10 +1055,10 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter4__incr WakeupSelect_WakeupSelect --> FIFO2_write - RS_RS4 --> WakeupSelect1_WakeupSelect + RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write - RS_RS3 --> WakeupSelect2_WakeupSelect + RS_RS4 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write @@ -1055,9 +1069,9 @@ ConnectTrans7_ConnectTrans --> BasicFifo6_write ConnectTrans9_ConnectTrans --> BasicFifo6_write ConnectTrans4_ConnectTrans --> BasicFifo6_write - TransactionManager_accept_cond1_ConnectTrans_accept_cond0 --> BasicFifo6_write - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write TransactionManager_ConnectTrans_accept_cond1 --> BasicFifo6_write + TransactionManager_accept_cond0_accept_cond0_ConnectTrans --> BasicFifo6_write + TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write RS_RS1 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue @@ -1082,36 +1096,36 @@ CSRRegister8_read --> ConnectTrans9_ConnectTrans ConnectTrans9_ConnectTrans --> BasicFifo8_write FifoRS_perf --> HwExpHistogram8__add - Forwarder6_read --> LSUDummy_LSUDummy + Forwarder6_read --> LSUDummy_LSUDummy1 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond1 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 - LSUDummy_LSUDummy --> FIFO6_write + LSUDummy_LSUDummy1 --> FIFO6_write WakeupSelect5_WakeupSelect --> FIFO6_write TransactionManager_LSUDummy_issue_cond1 --> FIFO6_write TransactionManager_LSUDummy_issue_cond0 --> FIFO6_write TransactionManager_LSUDummy_issue_cond2 --> FIFO6_write - LSUDummy_LSUDummy --> FIFO8_write + LSUDummy_LSUDummy1 --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write TransactionManager_LSUDummy_issue_cond1 --> FIFO8_write TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write Retirement_precommit --> LSUDummy_LSUDummy2 Retirement_precommit --> CSRUnit_CSRUnit1 - Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit + Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit + Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit ReorderBuffer_peek --> LSUDummy_LSUDummy2 ReorderBuffer_peek --> CSRUnit_CSRUnit1 + ReorderBuffer_peek --> Retirement_Retirement2 ReorderBuffer_peek --> Retirement_Retirement - ReorderBuffer_peek --> Retirement_Retirement3 - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop @@ -1135,8 +1149,6 @@ MethodMap11_method --> CSRUnit_CSRUnit CSRRegister5__internal_fu_read --> CSRUnit_CSRUnit AliasedCSR__fu_read --> CSRUnit_CSRUnit - MethodMap21_method --> CSRUnit_CSRUnit - CSRRegister10__internal_fu_read --> CSRUnit_CSRUnit MethodMap23_method --> CSRUnit_CSRUnit CSRRegister11__internal_fu_read --> CSRUnit_CSRUnit MethodMap25_method --> CSRUnit_CSRUnit @@ -1145,10 +1157,9 @@ CSRRegister13__internal_fu_read --> CSRUnit_CSRUnit MethodMap29_method --> CSRUnit_CSRUnit CSRRegister14__internal_fu_read --> CSRUnit_CSRUnit + MethodMap31_method --> CSRUnit_CSRUnit + CSRRegister15__internal_fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> AliasedCSR__fu_write - CSRUnit_CSRUnit --> MethodFilter10_method - CSRUnit_CSRUnit --> MethodMap20_method - CSRUnit_CSRUnit --> CSRRegister10__internal_fu_write CSRUnit_CSRUnit --> MethodFilter11_method CSRUnit_CSRUnit --> MethodMap22_method CSRUnit_CSRUnit --> CSRRegister11__internal_fu_write @@ -1161,6 +1172,9 @@ CSRUnit_CSRUnit --> MethodFilter14_method CSRUnit_CSRUnit --> MethodMap28_method CSRUnit_CSRUnit --> CSRRegister14__internal_fu_write + CSRUnit_CSRUnit --> MethodFilter15_method + CSRUnit_CSRUnit --> MethodMap30_method + CSRUnit_CSRUnit --> CSRRegister15__internal_fu_write AliasedCSR1__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> AliasedCSR1__fu_write MethodMap13_method --> CSRUnit_CSRUnit @@ -1178,8 +1192,11 @@ CSRUnit_CSRUnit --> MethodFilter8_method CSRUnit_CSRUnit --> MethodMap16_method CSRUnit_CSRUnit --> CSRRegister8__internal_fu_write - MethodMap31_method --> CSRUnit_CSRUnit - CSRRegister15__internal_fu_read --> CSRUnit_CSRUnit + MethodMap19_method --> CSRUnit_CSRUnit + CSRRegister9__internal_fu_read --> CSRUnit_CSRUnit + CSRUnit_CSRUnit --> MethodFilter9_method + CSRUnit_CSRUnit --> MethodMap18_method + CSRUnit_CSRUnit --> CSRRegister9__internal_fu_write MethodMap33_method --> CSRUnit_CSRUnit CSRRegister16__internal_fu_read --> CSRUnit_CSRUnit MethodMap35_method --> CSRUnit_CSRUnit @@ -1188,9 +1205,6 @@ CSRRegister18__internal_fu_read --> CSRUnit_CSRUnit MethodMap39_method --> CSRUnit_CSRUnit CSRRegister19__internal_fu_read --> CSRUnit_CSRUnit - CSRUnit_CSRUnit --> MethodFilter19_method - CSRUnit_CSRUnit --> MethodMap38_method - CSRUnit_CSRUnit --> CSRRegister19__internal_fu_write MethodMap41_method --> CSRUnit_CSRUnit CSRRegister20__internal_fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> MethodFilter20_method @@ -1198,8 +1212,13 @@ CSRUnit_CSRUnit --> CSRRegister20__internal_fu_write MethodMap43_method --> CSRUnit_CSRUnit CSRRegister21__internal_fu_read --> CSRUnit_CSRUnit + CSRUnit_CSRUnit --> MethodFilter21_method + CSRUnit_CSRUnit --> MethodMap42_method + CSRUnit_CSRUnit --> CSRRegister21__internal_fu_write MethodMap45_method --> CSRUnit_CSRUnit CSRRegister22__internal_fu_read --> CSRUnit_CSRUnit + MethodMap47_method --> CSRUnit_CSRUnit + CSRRegister23__internal_fu_read --> CSRUnit_CSRUnit ConnectTrans2_ConnectTrans --> Forwarder4_write ConnectTrans3_ConnectTrans --> Forwarder4_write ConnectTrans4_ConnectTrans --> Forwarder4_write @@ -1210,71 +1229,75 @@ Collector2_method --> ConnectTrans3_ConnectTrans Forwarder7_read --> ConnectTrans3_ConnectTrans CSRUnit_get_result --> ConnectTrans4_ConnectTrans - ExceptionCauseRegister_get --> Retirement_Retirement - ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 - ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement3 <--> ReorderBuffer_retire - TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire + ExceptionInformationRegister_get --> Retirement_Retirement2 + ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond0 + ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire - Retirement_Retirement3 <--> FIFOLatencyMeasurer1__stop - TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire + Retirement_Retirement <--> FIFOLatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop - FIFO1_read --> Retirement_Retirement3 - FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 + TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop + FIFO1_read --> Retirement_Retirement FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement3 --> HwExpHistogram3__add - TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add + FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement --> HwExpHistogram3__add TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add - CoreInstructionCounter_decrement --> Retirement_Retirement3 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 + TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add + CoreInstructionCounter_decrement --> Retirement_Retirement CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 - RRAT_peek --> Retirement_Retirement3 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 + RRAT_peek --> Retirement_Retirement RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement3 --> RegisterFile_free - TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free + Retirement_Retirement --> RegisterFile_free TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free - Retirement_Retirement3 --> TaggedLatencyMeasurer__stop - TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free + Retirement_Retirement --> TaggedLatencyMeasurer__stop TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop - AsyncMemoryBank_read --> Retirement_Retirement3 - AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1 + TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop + AsyncMemoryBank_read --> Retirement_Retirement AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement3 --> HwExpHistogram1__add - TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add + AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add - Retirement_Retirement3 --> FRAT_rename + TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add + Retirement_Retirement --> FRAT_rename + TransactionManager_Renaming_ROBAllocation --> FRAT_rename TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename - TransactionManager_ROBAllocation_Renaming --> FRAT_rename Retirement_Retirement1 <--> FIFOLatencyMeasurer2__stop FIFO12_read --> Retirement_Retirement1 Retirement_Retirement1 --> HwExpHistogram9__add CSRRegister7_read --> Retirement_Retirement1 Retirement_Retirement1 --> FetchUnit_resume_from_exception - Retirement_Retirement1 <--> ExceptionCauseRegister_clear - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> Semaphore_release - Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 - Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Predecoder_predecode - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> PredictionChecker_check - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter1__incr - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter2__incr - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write - TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy1 - TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy1 - TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy1 + Retirement_Retirement1 <--> ExceptionInformationRegister_clear + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit --> TaggedCounter6__incr + CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit + CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit + CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans + TransactionManager_accept_cond0_accept_cond0_ConnectTrans <--> ConnectTrans10_ConnectTrans + TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> ConnectTrans10_ConnectTrans + TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write + TransactionManager_accept_cond0_accept_cond0_ConnectTrans --> Forwarder7_write + TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> Forwarder7_write + LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 + LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans + LSUDummy_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1 + FIFO6_read --> TransactionManager_ConnectTrans_accept_cond1 + FIFO8_read --> TransactionManager_ConnectTrans_accept_cond1 + TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy + TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy + TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue @@ -1286,94 +1309,92 @@ TransactionManager_LSUDummy_issue_cond2 --> FIFO7_write TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read - TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer + TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer3 TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement2 - TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2 - TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> Semaphore_release + Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 + Pipe_read --> TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Predecoder_predecode + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> PredictionChecker_check + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter1__incr + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter2__incr + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter3__incr + TransactionManager_Renaming_ROBAllocation <--> Renaming_Renaming + FIFO9_read --> TransactionManager_Renaming_ROBAllocation + TransactionManager_Renaming_ROBAllocation --> Connect_write + TransactionManager_Renaming_ROBAllocation <--> ROBAllocation_ROBAllocation + Connect_read --> TransactionManager_Renaming_ROBAllocation + TransactionManager_Renaming_ROBAllocation --> ReorderBuffer_put + TransactionManager_Renaming_ROBAllocation <--> FIFOLatencyMeasurer1__start + TransactionManager_Renaming_ROBAllocation --> FIFO1_write + TransactionManager_Renaming_ROBAllocation --> FIFO10_write + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement3 + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement3 TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start - TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write + TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start TransactionManager_Retirement_Retirement_cond0 --> FIFO12_write - InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 + TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write + InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write - TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister9_write + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister9_write TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 - TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 - TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 - TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - Serializer1_Serializer3 --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - BasicFifo1_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - WishboneMaster1_result --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - Forwarder1_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans - TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond1_ConnectTrans_accept_cond0 --> Forwarder7_write - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write - TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write - LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 - TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - BasicFifo9_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - FIFO7_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - Serializer1_Serializer2 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation - Connect_read --> TransactionManager_ROBAllocation_Renaming - TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put - TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start - TransactionManager_ROBAllocation_Renaming --> FIFO1_write - TransactionManager_ROBAllocation_Renaming --> FIFO10_write - TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming - FIFO9_read --> TransactionManager_ROBAllocation_Renaming - TransactionManager_ROBAllocation_Renaming --> Connect_write - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr - CSRRegister14_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - CSRRegister14_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - CSRRegister14_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - CSRRegister14_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret - TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1 - FIFO6_read --> TransactionManager_ConnectTrans_accept_cond1 - FIFO8_read --> TransactionManager_ConnectTrans_accept_cond1 + TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment - CSRRegister21_read --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister21_write CSRRegister22_read --> TransactionManager_Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond0 --> CSRRegister22_write + CSRRegister23_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister23_write TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 + TransactionManager_accept_cond0_accept_cond0_ConnectTrans <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans + Serializer1_Serializer --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans + BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans + BasicFifo1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans + WishboneMaster1_result --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + Forwarder1_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans + Forwarder1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + TransactionManager_accept_cond0_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 + TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 + LSURequester_accept --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans + LSURequester_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + BasicFifo9_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans + BasicFifo9_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + FIFO7_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans + FIFO7_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> ICache_flush + TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + Serializer1_Serializer2 --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 + TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write + TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond0 + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> HwCounter5__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Serializer_write TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> InternalInterruptController_mret diff --git a/api.html b/api.html index a391871d8..c4b464b9b 100644 --- a/api.html +++ b/api.html @@ -271,7 +271,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/assumptions.html b/assumptions.html index 80d6fa174..9bd3ebfb7 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/auto_graph.html b/auto_graph.html index 3f16f0df2..24382c5e3 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -94,69 +94,69 @@ end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] + WishboneMaster1_request["request"] WishboneMaster1_WishboneMaster["WishboneMaster"] WishboneMaster1_result["result"] - WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] Forwarder1_read["read"] Forwarder1_write["write"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_write["write"] BasicFifo_read["read"] + BasicFifo_write["write"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_request_read["request_read"] - WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_get_read_response["get_read_response"] + WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_write["write"] BasicFifo1_read["read"] + BasicFifo1_write["write"] end end end subgraph CoreFrontend["frontend CoreFrontend"] - CoreFrontend_target_pred_resp["target_pred_resp"] - CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] CoreFrontend_stall["stall"] + CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] CoreFrontend_target_pred_req["target_pred_req"] + CoreFrontend_target_pred_resp["target_pred_resp"] subgraph BasicFifo2["instr_buffer BasicFifo"] - BasicFifo2_write["write"] BasicFifo2_read["read"] BasicFifo2_clear["clear"] + BasicFifo2_write["write"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end end subgraph ICache["icache ICache"] ICache_MemRead["MemRead"] ICache_ICache["ICache"] ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] ICache_ICache1["ICache"] ICache_flush["flush"] + ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -179,35 +179,35 @@ HwExpHistogram__add["_add"] end subgraph FIFO["fifo FIFO"] - FIFO_write["write"] FIFO_read["read"] + FIFO_write["write"] end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_write_results["write_results"] - ArgumentsToResultsZipper_read["read"] ArgumentsToResultsZipper_write_args["write_args"] ArgumentsToResultsZipper_peek_arg["peek_arg"] + ArgumentsToResultsZipper_write_results["write_results"] + ArgumentsToResultsZipper_read["read"] subgraph BasicFifo3["fifo BasicFifo"] BasicFifo3_read["read"] BasicFifo3_peek["peek"] BasicFifo3_write["write"] end subgraph Forwarder3["forwarder Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end end subgraph FetchUnit["fetch FetchUnit"] + FetchUnit_Fetch_Stage1["Fetch_Stage1"] + FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] FetchUnit_resume_from_exception["resume_from_exception"] - FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] FetchUnit_Fetch_Stage2["Fetch_Stage2"] - FetchUnit_resume_from_unsafe["resume_from_unsafe"] - FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] - FetchUnit_Fetch_Stage1["Fetch_Stage1"] - FetchUnit_stall_exception["stall_exception"] FetchUnit_Fetch_Stage0["Fetch_Stage0"] + FetchUnit_stall_exception["stall_exception"] + FetchUnit_resume_from_unsafe["resume_from_unsafe"] + FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] end @@ -216,8 +216,8 @@ end subgraph Serializer["serializer Serializer"] Serializer_clean["clean"] - Serializer_read["read"] Serializer_write["write"] + Serializer_read["read"] end subgraph ConnectTrans["serializer_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -227,8 +227,8 @@ BasicFifo4_write["write"] end subgraph Semaphore["req_counter Semaphore"] - Semaphore_release["release"] Semaphore_acquire["acquire"] + Semaphore_release["release"] end subgraph Pipe["s1_s2_pipe Pipe"] Pipe_read["read"] @@ -251,9 +251,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] - Pipe1_read["read"] - Pipe1_write["write"] Pipe1_clean["clean"] + Pipe1_write["write"] + Pipe1_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -274,20 +274,20 @@ RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read2["read2"] + RegisterFile_write["write"] RegisterFile_free["free"] RegisterFile_perf["perf"] + RegisterFile_read2["read2"] RegisterFile_read1["read1"] - RegisterFile_write["write"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer__stop["_stop"] TaggedLatencyMeasurer__start["_start"] + TaggedLatencyMeasurer__stop["_stop"] subgraph HwExpHistogram1["histogram HwExpHistogram"] HwExpHistogram1__add["_add"] end subgraph AsyncMemoryBank["slots AsyncMemoryBank"] - AsyncMemoryBank_read["read"] AsyncMemoryBank_write["write"] + AsyncMemoryBank_read["read"] end end subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] @@ -296,14 +296,14 @@ end subgraph ReorderBuffer["ROB ReorderBuffer"] ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_perf["perf"] - ReorderBuffer_peek["peek"] + ReorderBuffer_retire["retire"] ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_retire["retire"] + ReorderBuffer_perf["perf"] + ReorderBuffer_peek["peek"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] - FIFOLatencyMeasurer1__stop["_stop"] FIFOLatencyMeasurer1__start["_start"] + FIFOLatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram3["histogram HwExpHistogram"] HwExpHistogram3__add["_add"] end @@ -316,13 +316,13 @@ HwExpHistogram4__add["_add"] end end - subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_get["get"] - ExceptionCauseRegister_clear["clear"] - ExceptionCauseRegister_report["report"] + subgraph ExceptionInformationRegister["exception_information_register ExceptionInformationRegister"] + ExceptionInformationRegister_report["report"] + ExceptionInformationRegister_clear["clear"] + ExceptionInformationRegister_get["get"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] - BasicFifo6_read["read"] BasicFifo6_write["write"] + BasicFifo6_read["read"] end subgraph ConnectTrans1["report_connector ConnectTrans"] ConnectTrans1_ConnectTrans["ConnectTrans"] @@ -332,8 +332,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_read["read"] Forwarder4_write["write"] + Forwarder4_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans2["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -351,30 +351,30 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_update["update"] - RSFuncBlock_select["select"] RSFuncBlock_insert["insert"] + RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] + RSFuncBlock_select["select"] subgraph RS["rs RS"] - RS_select["select"] RS_RS["RS"] - RS_RS1["RS"] RS_insert["insert"] + RS_RS1["RS"] + RS_take["take"] RS_RS2["RS"] RS_perf["perf"] RS_RS3["RS"] RS_RS4["RS"] - RS_take["take"] RS_update["update"] + RS_select["select"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__stop["_stop"] TaggedLatencyMeasurer1__start["_start"] + TaggedLatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_read["read"] AsyncMemoryBank1_write["write"] + AsyncMemoryBank1_read["read"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -382,22 +382,22 @@ end end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph TaggedCounter4["perf_instr TaggedCounter"] TaggedCounter4__incr["_incr"] end subgraph FIFO2["fifo FIFO"] - FIFO2_write["write"] FIFO2_read["read"] + FIFO2_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_issue["issue"] ShiftFuncUnit_accept["accept"] + ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] FIFO3_write["write"] FIFO3_read["read"] @@ -407,8 +407,8 @@ WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO4["fifo_branch_resolved FIFO"] FIFO4_read["read"] FIFO4_write["write"] @@ -423,8 +423,8 @@ HwCounter8__incr["_incr"] end subgraph BasicFifo7["instr_fifo BasicFifo"] - BasicFifo7_read["read"] BasicFifo7_write["write"] + BasicFifo7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -442,16 +442,16 @@ WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] PrivilegedFuncUnit_issue["issue"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] - BasicFifo8_read["read"] BasicFifo8_write["write"] + BasicFifo8_read["read"] end subgraph TaggedCounter6["perf_instr TaggedCounter"] TaggedCounter6__incr["_incr"] @@ -463,8 +463,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_read["read"] Forwarder5_write["write"] + Forwarder5_read["read"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans5["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -486,26 +486,26 @@ end end subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] - RSFuncBlock1_insert["insert"] RSFuncBlock1_update["update"] - RSFuncBlock1_select["select"] + RSFuncBlock1_insert["insert"] RSFuncBlock1_get_result["get_result"] + RSFuncBlock1_select["select"] subgraph FifoRS["rs FifoRS"] - FifoRS_FifoRS["FifoRS"] FifoRS_update["update"] - FifoRS_take["take"] FifoRS_insert["insert"] FifoRS_perf["perf"] + FifoRS_take["take"] FifoRS_select["select"] + FifoRS_FifoRS["FifoRS"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer2__start["_start"] TaggedLatencyMeasurer2__stop["_stop"] + TaggedLatencyMeasurer2__start["_start"] subgraph HwExpHistogram7["histogram HwExpHistogram"] HwExpHistogram7__add["_add"] end subgraph AsyncMemoryBank2["slots AsyncMemoryBank"] - AsyncMemoryBank2_read["read"] AsyncMemoryBank2_write["write"] + AsyncMemoryBank2_read["read"] end end subgraph HwExpHistogram8["perf_num_full HwExpHistogram"] @@ -513,21 +513,21 @@ end end subgraph LSUDummy["func_unit_0 LSUDummy"] - LSUDummy_accept_cond1["accept_cond1"] - LSUDummy_LSUDummy["LSUDummy"] LSUDummy_accept_cond0["accept_cond0"] + LSUDummy_LSUDummy["LSUDummy"] LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_issue["issue"] LSUDummy_accept["accept"] - LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_accept_cond1["accept_cond1"] subgraph LSURequester["requester LSURequester"] - LSURequester_accept_cond1["accept_cond1"] - LSURequester_issue_cond0["issue_cond0"] - LSURequester_issue_cond1["issue_cond1"] + LSURequester_accept["accept"] LSURequester_issue_cond2["issue_cond2"] + LSURequester_accept_cond1["accept_cond1"] LSURequester_accept_cond0["accept_cond0"] LSURequester_issue["issue"] - LSURequester_accept["accept"] + LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond0["issue_cond0"] subgraph BasicFifo9["args_fifo BasicFifo"] BasicFifo9_write["write"] BasicFifo9_read["read"] @@ -538,12 +538,12 @@ Forwarder6_read["read"] end subgraph FIFO6["results_noop FIFO"] - FIFO6_write["write"] FIFO6_read["read"] + FIFO6_write["write"] end subgraph FIFO7["issued FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end subgraph FIFO8["issued_noop FIFO"] FIFO8_read["read"] @@ -556,8 +556,8 @@ subgraph Collector2["collector Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_write["write"] Forwarder7_read["read"] + Forwarder7_write["write"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans10["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -567,13 +567,13 @@ end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_select["select"] CSRUnit_fetch_resume["fetch_resume"] - CSRUnit_CSRUnit["CSRUnit"] - CSRUnit_get_result["get_result"] + CSRUnit_insert["insert"] CSRUnit_update["update"] + CSRUnit_select["select"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_CSRUnit1["CSRUnit"] - CSRUnit_insert["insert"] + CSRUnit_get_result["get_result"] end end subgraph ResultAnnouncement["announcement ResultAnnouncement"] @@ -634,9 +634,9 @@ AliasedCSR1__fu_read["_fu_read"] end subgraph CSRRegister6["mcause CSRRegister"] + CSRRegister6__internal_fu_read["_internal_fu_read"] CSRRegister6_write["write"] CSRRegister6__internal_fu_write["_internal_fu_write"] - CSRRegister6__internal_fu_read["_internal_fu_read"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -649,8 +649,8 @@ end subgraph CSRRegister7["mtvec CSRRegister"] CSRRegister7__internal_fu_read["_internal_fu_read"] - CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7_read["read"] + CSRRegister7__internal_fu_write["_internal_fu_write"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] end @@ -663,9 +663,9 @@ end subgraph CSRRegister8["mepc CSRRegister"] CSRRegister8__internal_fu_read["_internal_fu_read"] + CSRRegister8_write["write"] CSRRegister8__internal_fu_write["_internal_fu_write"] CSRRegister8_read["read"] - CSRRegister8_write["write"] subgraph MethodMap16["fu_write_map MethodMap"] MethodMap16_method["method"] end @@ -676,30 +676,29 @@ MethodMap17_method["method"] end end - subgraph CSRRegister9["priv_mode CSRRegister"] - CSRRegister9_read["read"] + subgraph CSRRegister9["mtval CSRRegister"] + CSRRegister9__internal_fu_write["_internal_fu_write"] CSRRegister9_write["write"] - end - subgraph CSRRegister10["mstatus_mie CSRRegister"] - CSRRegister10_write["write"] - CSRRegister10__internal_fu_write["_internal_fu_write"] - CSRRegister10_read["read"] - CSRRegister10__internal_fu_read["_internal_fu_read"] - subgraph MethodMap20["fu_write_map MethodMap"] - MethodMap20_method["method"] + CSRRegister9__internal_fu_read["_internal_fu_read"] + subgraph MethodMap18["fu_write_map MethodMap"] + MethodMap18_method["method"] end - subgraph MethodFilter10["fu_write_filter MethodFilter"] - MethodFilter10_method["method"] + subgraph MethodFilter9["fu_write_filter MethodFilter"] + MethodFilter9_method["method"] end - subgraph MethodMap21["fu_read_map MethodMap"] - MethodMap21_method["method"] + subgraph MethodMap19["fu_read_map MethodMap"] + MethodMap19_method["method"] end end - subgraph CSRRegister11["mstatus_mpie CSRRegister"] - CSRRegister11__internal_fu_read["_internal_fu_read"] + subgraph CSRRegister10["priv_mode CSRRegister"] + CSRRegister10_write["write"] + CSRRegister10_read["read"] + end + subgraph CSRRegister11["mstatus_mie CSRRegister"] CSRRegister11_write["write"] CSRRegister11__internal_fu_write["_internal_fu_write"] CSRRegister11_read["read"] + CSRRegister11__internal_fu_read["_internal_fu_read"] subgraph MethodMap22["fu_write_map MethodMap"] MethodMap22_method["method"] end @@ -710,11 +709,11 @@ MethodMap23_method["method"] end end - subgraph CSRRegister12["mstatus_mpp CSRRegister"] + subgraph CSRRegister12["mstatus_mpie CSRRegister"] CSRRegister12__internal_fu_read["_internal_fu_read"] - CSRRegister12_read["read"] - CSRRegister12_write["write"] CSRRegister12__internal_fu_write["_internal_fu_write"] + CSRRegister12_write["write"] + CSRRegister12_read["read"] subgraph MethodMap24["fu_write_map MethodMap"] MethodMap24_method["method"] end @@ -725,10 +724,11 @@ MethodMap25_method["method"] end end - subgraph CSRRegister13["mstatus_mprv CSRRegister"] - CSRRegister13__internal_fu_write["_internal_fu_write"] + subgraph CSRRegister13["mstatus_mpp CSRRegister"] CSRRegister13__internal_fu_read["_internal_fu_read"] + CSRRegister13_read["read"] CSRRegister13_write["write"] + CSRRegister13__internal_fu_write["_internal_fu_write"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -739,10 +739,10 @@ MethodMap27_method["method"] end end - subgraph CSRRegister14["mstatus_tw CSRRegister"] - CSRRegister14__internal_fu_write["_internal_fu_write"] + subgraph CSRRegister14["mstatus_mprv CSRRegister"] + CSRRegister14_write["write"] CSRRegister14__internal_fu_read["_internal_fu_read"] - CSRRegister14_read["read"] + CSRRegister14__internal_fu_write["_internal_fu_write"] subgraph MethodMap28["fu_write_map MethodMap"] MethodMap28_method["method"] end @@ -753,73 +753,71 @@ MethodMap29_method["method"] end end - end - subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] - DoubleCounterCSR_increment["increment"] - subgraph CSRRegister15["register_low CSRRegister"] - CSRRegister15_read["read"] - CSRRegister15_write["write"] + subgraph CSRRegister15["mstatus_tw CSRRegister"] CSRRegister15__internal_fu_read["_internal_fu_read"] + CSRRegister15__internal_fu_write["_internal_fu_write"] + CSRRegister15_read["read"] + subgraph MethodMap30["fu_write_map MethodMap"] + MethodMap30_method["method"] + end + subgraph MethodFilter15["fu_write_filter MethodFilter"] + MethodFilter15_method["method"] + end subgraph MethodMap31["fu_read_map MethodMap"] MethodMap31_method["method"] end end - subgraph CSRRegister16["register_high CSRRegister"] - CSRRegister16_read["read"] + end + subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] + DoubleCounterCSR_increment["increment"] + subgraph CSRRegister16["register_low CSRRegister"] CSRRegister16_write["write"] + CSRRegister16_read["read"] CSRRegister16__internal_fu_read["_internal_fu_read"] subgraph MethodMap33["fu_read_map MethodMap"] MethodMap33_method["method"] end end - end - subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] - DoubleCounterCSR1_increment["increment"] - subgraph CSRRegister17["register_low CSRRegister"] + subgraph CSRRegister17["register_high CSRRegister"] CSRRegister17_write["write"] - CSRRegister17_read["read"] CSRRegister17__internal_fu_read["_internal_fu_read"] + CSRRegister17_read["read"] subgraph MethodMap35["fu_read_map MethodMap"] MethodMap35_method["method"] end end - subgraph CSRRegister18["register_high CSRRegister"] - CSRRegister18_read["read"] + end + subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] + DoubleCounterCSR1_increment["increment"] + subgraph CSRRegister18["register_low CSRRegister"] CSRRegister18__internal_fu_read["_internal_fu_read"] CSRRegister18_write["write"] + CSRRegister18_read["read"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] end end + subgraph CSRRegister19["register_high CSRRegister"] + CSRRegister19_write["write"] + CSRRegister19_read["read"] + CSRRegister19__internal_fu_read["_internal_fu_read"] + subgraph MethodMap39["fu_read_map MethodMap"] + MethodMap39_method["method"] + end + end end end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] - InternalInterruptController_InternalInterruptController["InternalInterruptController"] - InternalInterruptController_InternalInterruptController1["InternalInterruptController"] - InternalInterruptController_InternalInterruptController2["InternalInterruptController"] InternalInterruptController_interrupt_cause["interrupt_cause"] + InternalInterruptController_InternalInterruptController["InternalInterruptController"] InternalInterruptController_mret["mret"] InternalInterruptController_entry["entry"] - subgraph CSRRegister19["mie CSRRegister"] - CSRRegister19_read["read"] - CSRRegister19__internal_fu_read["_internal_fu_read"] - CSRRegister19__internal_fu_write["_internal_fu_write"] - subgraph MethodMap38["fu_write_map MethodMap"] - MethodMap38_method["method"] - end - subgraph MethodFilter19["fu_write_filter MethodFilter"] - MethodFilter19_method["method"] - end - subgraph MethodMap39["fu_read_map MethodMap"] - MethodMap39_method["method"] - end - end - subgraph CSRRegister20["mip CSRRegister"] - CSRRegister20_read["read"] + InternalInterruptController_InternalInterruptController1["InternalInterruptController"] + InternalInterruptController_InternalInterruptController2["InternalInterruptController"] + subgraph CSRRegister20["mie CSRRegister"] CSRRegister20__internal_fu_read["_internal_fu_read"] - CSRRegister20_read_comb["read_comb"] + CSRRegister20_read["read"] CSRRegister20__internal_fu_write["_internal_fu_write"] - CSRRegister20_write["write"] subgraph MethodMap40["fu_write_map MethodMap"] MethodMap40_method["method"] end @@ -830,18 +828,34 @@ MethodMap41_method["method"] end end + subgraph CSRRegister21["mip CSRRegister"] + CSRRegister21_write["write"] + CSRRegister21_read["read"] + CSRRegister21__internal_fu_read["_internal_fu_read"] + CSRRegister21_read_comb["read_comb"] + CSRRegister21__internal_fu_write["_internal_fu_write"] + subgraph MethodMap42["fu_write_map MethodMap"] + MethodMap42_method["method"] + end + subgraph MethodFilter21["fu_write_filter MethodFilter"] + MethodFilter21_method["method"] + end + subgraph MethodMap43["fu_read_map MethodMap"] + MethodMap43_method["method"] + end + end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph MethodProduct1["get_instr MethodProduct"] MethodProduct1_method["method"] end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO9["alloc_rename_buf FIFO"] - FIFO9_write["write"] FIFO9_read["read"] + FIFO9_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -854,15 +868,15 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO11["rs_select_out_buf FIFO"] - FIFO11_read["read"] FIFO11_write["write"] + FIFO11_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -877,8 +891,8 @@ subgraph Collector3["FetchResumeKey_unifier Collector"] Collector3_method["method"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_write["write"] Forwarder8_read["read"] + Forwarder8_write["write"] end subgraph ManyToOneConnectTrans3["connect ManyToOneConnectTrans"] subgraph ConnectTrans11["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -894,32 +908,32 @@ ConnectTrans13_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] - Retirement_precommit["precommit"] - Retirement_core_state["core_state"] Retirement_Retirement1["Retirement"] + Retirement_core_state["core_state"] + Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement2["Retirement"] + Retirement_precommit["precommit"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement3["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] - subgraph CSRRegister21["register_low CSRRegister"] - CSRRegister21_read["read"] - CSRRegister21_write["write"] - CSRRegister21__internal_fu_read["_internal_fu_read"] - subgraph MethodMap43["fu_read_map MethodMap"] - MethodMap43_method["method"] - end - end - subgraph CSRRegister22["register_high CSRRegister"] - CSRRegister22__internal_fu_read["_internal_fu_read"] - CSRRegister22_read["read"] + subgraph CSRRegister22["register_low CSRRegister"] CSRRegister22_write["write"] + CSRRegister22_read["read"] + CSRRegister22__internal_fu_read["_internal_fu_read"] subgraph MethodMap45["fu_read_map MethodMap"] MethodMap45_method["method"] end end + subgraph CSRRegister23["register_high CSRRegister"] + CSRRegister23_read["read"] + CSRRegister23_write["write"] + CSRRegister23__internal_fu_read["_internal_fu_read"] + subgraph MethodMap47["fu_read_map MethodMap"] + MethodMap47_method["method"] + end + end end subgraph HwCounter9["perf_instr_ret HwCounter"] HwCounter9__incr["_incr"] @@ -931,8 +945,8 @@ HwExpHistogram9__add["_add"] end subgraph FIFO12["fifo FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end end end @@ -940,26 +954,26 @@ end subgraph TransactionManager["transaction_manager TransactionManager"] TransactionManager_ConnectTrans_accept_cond1["ConnectTrans_accept_cond1"] - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2["Fetch_Stage2_cond1_Fetch_Stage2"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] - TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] - TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] - TransactionManager_accept_cond1_ConnectTrans_accept_cond0["accept_cond1_ConnectTrans_accept_cond0"] TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0["Fetch_Stage2_Fetch_Stage2_cond0"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit["PrivilegedFuncUnit_cond2_PrivilegedFuncUnit"] TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_PrivilegedFuncUnit_cond0"] + TransactionManager_accept_cond1_accept_cond0_ConnectTrans["accept_cond1_accept_cond0_ConnectTrans"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit["PrivilegedFuncUnit_cond1_PrivilegedFuncUnit"] + TransactionManager_accept_cond0_accept_cond0_ConnectTrans["accept_cond0_accept_cond0_ConnectTrans"] + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2["Fetch_Stage2_cond1_Fetch_Stage2"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2["Fetch_Stage2_cond0_Fetch_Stage2"] + TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit["PrivilegedFuncUnit_cond0_PrivilegedFuncUnit"] end end Core_InitFreeRFFifo --> BasicFifo5_write -Retirement_Retirement3 --> BasicFifo5_write -TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write +Retirement_Retirement --> BasicFifo5_write TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write +TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify @@ -1009,51 +1023,51 @@ RegisterFile_perf --> HwExpHistogram2__add ReorderBuffer_perf --> HwExpHistogram4__add GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment -CSRRegister15_read --> GenericCSRRegisters_GenericCSRRegisters -GenericCSRRegisters_GenericCSRRegisters --> CSRRegister15_write CSRRegister16_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister16_write -GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR1_increment CSRRegister17_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister17_write +GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR1_increment CSRRegister18_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister18_write -CSRRegister10_read --> InternalInterruptController_InternalInterruptController -CSRRegister10_read --> InternalInterruptController_InternalInterruptController1 -CSRRegister9_read --> InternalInterruptController_InternalInterruptController -CSRRegister9_read --> InternalInterruptController_InternalInterruptController1 -CSRRegister9_read --> WakeupSelect3_WakeupSelect -CSRRegister9_read --> CSRUnit_CSRUnit -CSRRegister9_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -CSRRegister9_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -CSRRegister9_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 -CSRRegister9_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -CSRRegister19_read --> InternalInterruptController_InternalInterruptController -CSRRegister20_read --> InternalInterruptController_InternalInterruptController -CSRRegister20_read_comb --> InternalInterruptController_InternalInterruptController2 -InternalInterruptController_InternalInterruptController2 --> CSRRegister20_write -InternalInterruptController_InternalInterruptController1 --> CSRRegister10_write -InternalInterruptController_InternalInterruptController1 --> CSRRegister11_write -InternalInterruptController_InternalInterruptController1 --> CSRRegister12_write -InternalInterruptController_InternalInterruptController1 --> CSRRegister9_write +CSRRegister19_read --> GenericCSRRegisters_GenericCSRRegisters +GenericCSRRegisters_GenericCSRRegisters --> CSRRegister19_write CSRRegister11_read --> InternalInterruptController_InternalInterruptController1 -CSRRegister12_read --> InternalInterruptController_InternalInterruptController1 -InternalInterruptController_InternalInterruptController1 --> CSRRegister13_write +CSRRegister11_read --> InternalInterruptController_InternalInterruptController2 +CSRRegister10_read --> InternalInterruptController_InternalInterruptController1 +CSRRegister10_read --> InternalInterruptController_InternalInterruptController2 +CSRRegister10_read --> WakeupSelect3_WakeupSelect +CSRRegister10_read --> CSRUnit_CSRUnit +CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit +CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit +CSRRegister10_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit +CSRRegister20_read --> InternalInterruptController_InternalInterruptController1 +CSRRegister21_read --> InternalInterruptController_InternalInterruptController1 +CSRRegister21_read_comb --> InternalInterruptController_InternalInterruptController +InternalInterruptController_InternalInterruptController --> CSRRegister21_write +InternalInterruptController_InternalInterruptController2 --> CSRRegister11_write +InternalInterruptController_InternalInterruptController2 --> CSRRegister12_write +InternalInterruptController_InternalInterruptController2 --> CSRRegister13_write +InternalInterruptController_InternalInterruptController2 --> CSRRegister10_write +CSRRegister12_read --> InternalInterruptController_InternalInterruptController2 +CSRRegister13_read --> InternalInterruptController_InternalInterruptController2 +InternalInterruptController_InternalInterruptController2 --> CSRRegister14_write MethodProduct1_method --> RegAllocation_RegAllocation Pipe1_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation <--> CoreInstructionCounter_increment BasicFifo5_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO9_write -FIFO10_read --> RSSelection_RSSelection1 FIFO10_read --> RSSelection_RSSelection +FIFO10_read --> RSSelection_RSSelection1 FIFO10_read --> RSSelection_RSSelection2 -RSFuncBlock_select --> RSSelection_RSSelection1 -RS_select --> RSSelection_RSSelection1 -RSSelection_RSSelection1 --> FIFO11_write +RSFuncBlock_select --> RSSelection_RSSelection +RS_select --> RSSelection_RSSelection RSSelection_RSSelection --> FIFO11_write +RSSelection_RSSelection1 --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write -RSFuncBlock1_select --> RSSelection_RSSelection -FifoRS_select --> RSSelection_RSSelection +RSFuncBlock1_select --> RSSelection_RSSelection1 +FifoRS_select --> RSSelection_RSSelection1 RSSelection_RSSelection2 <--> CSRUnit_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion @@ -1069,7 +1083,7 @@ RSInsertion_RSInsertion --> AsyncMemoryBank2_write RSInsertion_RSInsertion --> CSRUnit_insert BasicFifo6_read --> ConnectTrans1_ConnectTrans -ConnectTrans1_ConnectTrans --> ExceptionCauseRegister_report +ConnectTrans1_ConnectTrans --> ExceptionInformationRegister_report ReorderBuffer_get_indices --> ConnectTrans1_ConnectTrans ConnectTrans1_ConnectTrans <--> CoreFrontend_stall ConnectTrans1_ConnectTrans <--> FetchUnit_stall_exception @@ -1120,10 +1134,10 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter4__incr WakeupSelect_WakeupSelect --> FIFO2_write -RS_RS4 --> WakeupSelect1_WakeupSelect +RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write -RS_RS3 --> WakeupSelect2_WakeupSelect +RS_RS4 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write @@ -1134,9 +1148,9 @@ ConnectTrans7_ConnectTrans --> BasicFifo6_write ConnectTrans9_ConnectTrans --> BasicFifo6_write ConnectTrans4_ConnectTrans --> BasicFifo6_write -TransactionManager_accept_cond1_ConnectTrans_accept_cond0 --> BasicFifo6_write -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write TransactionManager_ConnectTrans_accept_cond1 --> BasicFifo6_write +TransactionManager_accept_cond0_accept_cond0_ConnectTrans --> BasicFifo6_write +TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write RS_RS1 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue @@ -1161,36 +1175,36 @@ CSRRegister8_read --> ConnectTrans9_ConnectTrans ConnectTrans9_ConnectTrans --> BasicFifo8_write FifoRS_perf --> HwExpHistogram8__add -Forwarder6_read --> LSUDummy_LSUDummy +Forwarder6_read --> LSUDummy_LSUDummy1 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond1 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 -LSUDummy_LSUDummy --> FIFO6_write +LSUDummy_LSUDummy1 --> FIFO6_write WakeupSelect5_WakeupSelect --> FIFO6_write TransactionManager_LSUDummy_issue_cond1 --> FIFO6_write TransactionManager_LSUDummy_issue_cond0 --> FIFO6_write TransactionManager_LSUDummy_issue_cond2 --> FIFO6_write -LSUDummy_LSUDummy --> FIFO8_write +LSUDummy_LSUDummy1 --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write TransactionManager_LSUDummy_issue_cond1 --> FIFO8_write TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write Retirement_precommit --> LSUDummy_LSUDummy2 Retirement_precommit --> CSRUnit_CSRUnit1 -Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit +Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit +Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit ReorderBuffer_peek --> LSUDummy_LSUDummy2 ReorderBuffer_peek --> CSRUnit_CSRUnit1 +ReorderBuffer_peek --> Retirement_Retirement2 ReorderBuffer_peek --> Retirement_Retirement -ReorderBuffer_peek --> Retirement_Retirement3 -ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop @@ -1214,8 +1228,6 @@ MethodMap11_method --> CSRUnit_CSRUnit CSRRegister5__internal_fu_read --> CSRUnit_CSRUnit AliasedCSR__fu_read --> CSRUnit_CSRUnit -MethodMap21_method --> CSRUnit_CSRUnit -CSRRegister10__internal_fu_read --> CSRUnit_CSRUnit MethodMap23_method --> CSRUnit_CSRUnit CSRRegister11__internal_fu_read --> CSRUnit_CSRUnit MethodMap25_method --> CSRUnit_CSRUnit @@ -1224,10 +1236,9 @@ CSRRegister13__internal_fu_read --> CSRUnit_CSRUnit MethodMap29_method --> CSRUnit_CSRUnit CSRRegister14__internal_fu_read --> CSRUnit_CSRUnit +MethodMap31_method --> CSRUnit_CSRUnit +CSRRegister15__internal_fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> AliasedCSR__fu_write -CSRUnit_CSRUnit --> MethodFilter10_method -CSRUnit_CSRUnit --> MethodMap20_method -CSRUnit_CSRUnit --> CSRRegister10__internal_fu_write CSRUnit_CSRUnit --> MethodFilter11_method CSRUnit_CSRUnit --> MethodMap22_method CSRUnit_CSRUnit --> CSRRegister11__internal_fu_write @@ -1240,6 +1251,9 @@ CSRUnit_CSRUnit --> MethodFilter14_method CSRUnit_CSRUnit --> MethodMap28_method CSRUnit_CSRUnit --> CSRRegister14__internal_fu_write +CSRUnit_CSRUnit --> MethodFilter15_method +CSRUnit_CSRUnit --> MethodMap30_method +CSRUnit_CSRUnit --> CSRRegister15__internal_fu_write AliasedCSR1__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> AliasedCSR1__fu_write MethodMap13_method --> CSRUnit_CSRUnit @@ -1257,8 +1271,11 @@ CSRUnit_CSRUnit --> MethodFilter8_method CSRUnit_CSRUnit --> MethodMap16_method CSRUnit_CSRUnit --> CSRRegister8__internal_fu_write -MethodMap31_method --> CSRUnit_CSRUnit -CSRRegister15__internal_fu_read --> CSRUnit_CSRUnit +MethodMap19_method --> CSRUnit_CSRUnit +CSRRegister9__internal_fu_read --> CSRUnit_CSRUnit +CSRUnit_CSRUnit --> MethodFilter9_method +CSRUnit_CSRUnit --> MethodMap18_method +CSRUnit_CSRUnit --> CSRRegister9__internal_fu_write MethodMap33_method --> CSRUnit_CSRUnit CSRRegister16__internal_fu_read --> CSRUnit_CSRUnit MethodMap35_method --> CSRUnit_CSRUnit @@ -1267,9 +1284,6 @@ CSRRegister18__internal_fu_read --> CSRUnit_CSRUnit MethodMap39_method --> CSRUnit_CSRUnit CSRRegister19__internal_fu_read --> CSRUnit_CSRUnit -CSRUnit_CSRUnit --> MethodFilter19_method -CSRUnit_CSRUnit --> MethodMap38_method -CSRUnit_CSRUnit --> CSRRegister19__internal_fu_write MethodMap41_method --> CSRUnit_CSRUnit CSRRegister20__internal_fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> MethodFilter20_method @@ -1277,8 +1291,13 @@ CSRUnit_CSRUnit --> CSRRegister20__internal_fu_write MethodMap43_method --> CSRUnit_CSRUnit CSRRegister21__internal_fu_read --> CSRUnit_CSRUnit +CSRUnit_CSRUnit --> MethodFilter21_method +CSRUnit_CSRUnit --> MethodMap42_method +CSRUnit_CSRUnit --> CSRRegister21__internal_fu_write MethodMap45_method --> CSRUnit_CSRUnit CSRRegister22__internal_fu_read --> CSRUnit_CSRUnit +MethodMap47_method --> CSRUnit_CSRUnit +CSRRegister23__internal_fu_read --> CSRUnit_CSRUnit ConnectTrans2_ConnectTrans --> Forwarder4_write ConnectTrans3_ConnectTrans --> Forwarder4_write ConnectTrans4_ConnectTrans --> Forwarder4_write @@ -1289,71 +1308,75 @@ Collector2_method --> ConnectTrans3_ConnectTrans Forwarder7_read --> ConnectTrans3_ConnectTrans CSRUnit_get_result --> ConnectTrans4_ConnectTrans -ExceptionCauseRegister_get --> Retirement_Retirement -ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 -ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement3 <--> ReorderBuffer_retire -TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire +ExceptionInformationRegister_get --> Retirement_Retirement2 +ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond0 +ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire -Retirement_Retirement3 <--> FIFOLatencyMeasurer1__stop -TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire +Retirement_Retirement <--> FIFOLatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop -FIFO1_read --> Retirement_Retirement3 -FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 +TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop +FIFO1_read --> Retirement_Retirement FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement3 --> HwExpHistogram3__add -TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add +FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement --> HwExpHistogram3__add TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add -CoreInstructionCounter_decrement --> Retirement_Retirement3 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 +TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add +CoreInstructionCounter_decrement --> Retirement_Retirement CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 -RRAT_peek --> Retirement_Retirement3 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 +RRAT_peek --> Retirement_Retirement RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement3 --> RegisterFile_free -TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free +Retirement_Retirement --> RegisterFile_free TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free -Retirement_Retirement3 --> TaggedLatencyMeasurer__stop -TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free +Retirement_Retirement --> TaggedLatencyMeasurer__stop TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop -AsyncMemoryBank_read --> Retirement_Retirement3 -AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1 +TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop +AsyncMemoryBank_read --> Retirement_Retirement AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement3 --> HwExpHistogram1__add -TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add +AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add -Retirement_Retirement3 --> FRAT_rename +TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add +Retirement_Retirement --> FRAT_rename +TransactionManager_Renaming_ROBAllocation --> FRAT_rename TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename -TransactionManager_ROBAllocation_Renaming --> FRAT_rename Retirement_Retirement1 <--> FIFOLatencyMeasurer2__stop FIFO12_read --> Retirement_Retirement1 Retirement_Retirement1 --> HwExpHistogram9__add CSRRegister7_read --> Retirement_Retirement1 Retirement_Retirement1 --> FetchUnit_resume_from_exception -Retirement_Retirement1 <--> ExceptionCauseRegister_clear -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> Semaphore_release -Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 -Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Predecoder_predecode -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> PredictionChecker_check -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter1__incr -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter2__incr -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write -TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy1 -TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy1 -TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy1 +Retirement_Retirement1 <--> ExceptionInformationRegister_clear +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit --> TaggedCounter6__incr +CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit +CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit +CSRRegister15_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans +TransactionManager_accept_cond0_accept_cond0_ConnectTrans <--> ConnectTrans10_ConnectTrans +TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> ConnectTrans10_ConnectTrans +TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write +TransactionManager_accept_cond0_accept_cond0_ConnectTrans --> Forwarder7_write +TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> Forwarder7_write +LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 +LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans +LSUDummy_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1 +FIFO6_read --> TransactionManager_ConnectTrans_accept_cond1 +FIFO8_read --> TransactionManager_ConnectTrans_accept_cond1 +TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy +TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy +TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue @@ -1365,97 +1388,95 @@ TransactionManager_LSUDummy_issue_cond2 --> FIFO7_write TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read -TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer +TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer3 TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement2 -TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2 -TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start +TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> Semaphore_release +Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 +Pipe_read --> TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Predecoder_predecode +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> PredictionChecker_check +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter1__incr +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter2__incr +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter3__incr +TransactionManager_Renaming_ROBAllocation <--> Renaming_Renaming +FIFO9_read --> TransactionManager_Renaming_ROBAllocation +TransactionManager_Renaming_ROBAllocation --> Connect_write +TransactionManager_Renaming_ROBAllocation <--> ROBAllocation_ROBAllocation +Connect_read --> TransactionManager_Renaming_ROBAllocation +TransactionManager_Renaming_ROBAllocation --> ReorderBuffer_put +TransactionManager_Renaming_ROBAllocation <--> FIFOLatencyMeasurer1__start +TransactionManager_Renaming_ROBAllocation --> FIFO1_write +TransactionManager_Renaming_ROBAllocation --> FIFO10_write +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement3 +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement3 TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start -TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write +TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start TransactionManager_Retirement_Retirement_cond0 --> FIFO12_write -InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 +TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write +InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write -TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister9_write +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister9_write TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 -TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 -TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write -TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 -TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -Serializer1_Serializer3 --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -BasicFifo1_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -WishboneMaster1_result --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -Forwarder1_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans -TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans -TransactionManager_accept_cond1_ConnectTrans_accept_cond0 --> Forwarder7_write -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write -TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write -LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 -TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 -LSURequester_accept --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -BasicFifo9_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -FIFO7_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -Serializer1_Serializer2 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation -Connect_read --> TransactionManager_ROBAllocation_Renaming -TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put -TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start -TransactionManager_ROBAllocation_Renaming --> FIFO1_write -TransactionManager_ROBAllocation_Renaming --> FIFO10_write -TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming -FIFO9_read --> TransactionManager_ROBAllocation_Renaming -TransactionManager_ROBAllocation_Renaming --> Connect_write -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr -CSRRegister14_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -CSRRegister14_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -CSRRegister14_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 -CSRRegister14_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret -TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1 -FIFO6_read --> TransactionManager_ConnectTrans_accept_cond1 -FIFO8_read --> TransactionManager_ConnectTrans_accept_cond1 +TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment -CSRRegister21_read --> TransactionManager_Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister21_write CSRRegister22_read --> TransactionManager_Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond0 --> CSRRegister22_write +CSRRegister23_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister23_write TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 +TransactionManager_accept_cond0_accept_cond0_ConnectTrans <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans +Serializer1_Serializer --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans +BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans +BasicFifo1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans +WishboneMaster1_result --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +Forwarder1_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans +Forwarder1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +TransactionManager_accept_cond0_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 +TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 +LSURequester_accept --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans +LSURequester_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +BasicFifo9_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans +BasicFifo9_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +FIFO7_read --> TransactionManager_accept_cond0_accept_cond0_ConnectTrans +FIFO7_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 +TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> ICache_flush +TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +Serializer1_Serializer2 --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 +TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write +TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond0 +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> HwCounter5__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Serializer_write TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> InternalInterruptController_mret @@ -1466,7 +1487,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/components/icache.html b/components/icache.html index 71c38a5ca..ab55af8a9 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.arch.html b/coreblocks.arch.html index c4d717b7b..dbd62a909 100644 --- a/coreblocks.arch.html +++ b/coreblocks.arch.html @@ -92,7 +92,7 @@

Submodules
class coreblocks.arch.csr_address.CSRAddress
-

Bases: IntEnum

+

Bases: IntEnum

COREBLOCKS_TEST_CSR = 2047
@@ -2342,7 +2342,7 @@

Submodules
class coreblocks.arch.isa_consts.ExceptionCause
-

Bases: IntEnum

+

Bases: IntEnum

BREAKPOINT = 3
@@ -2423,7 +2423,7 @@

Submodules
class coreblocks.arch.isa_consts.FenceFm
-

Bases: IntEnum

+

Bases: IntEnum

NONE = 0
@@ -2444,7 +2444,7 @@

Submodules
class coreblocks.arch.isa_consts.FenceTarget
-

Bases: IntFlag

+

Bases: IntFlag

DEV_I = 8
@@ -2475,7 +2475,7 @@

Submodules
class coreblocks.arch.isa_consts.Funct12
-

Bases: IntEnum

+

Bases: IntEnum

CLZ = 1536
@@ -2556,7 +2556,7 @@

Submodules
class coreblocks.arch.isa_consts.Funct3
-

Bases: IntEnum

+

Bases: IntEnum

ADD = 0
@@ -2922,7 +2922,7 @@

Submodules
class coreblocks.arch.isa_consts.Funct7
-

Bases: IntEnum

+

Bases: IntEnum

ADD = 0
@@ -3175,7 +3175,7 @@

Submodules
class coreblocks.arch.isa_consts.Opcode
-

Bases: IntEnum

+

Bases: IntEnum

AUIPC = 5
@@ -3266,7 +3266,7 @@

Submodules
class coreblocks.arch.isa_consts.PrivilegeLevel
-

Bases: IntEnum

+

Bases: IntEnum

MACHINE = 3
@@ -3292,7 +3292,7 @@

Submodules
class coreblocks.arch.isa_consts.Registers
-

Bases: IntEnum

+

Bases: IntEnum

A0 = 10
@@ -3628,7 +3628,7 @@

Submodules
class coreblocks.arch.isa_consts.XlenEncoding
-

Bases: IntEnum

+

Bases: IntEnum

W128 = 3
@@ -3702,22 +3702,22 @@

Submodules
-static is_branch(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
+static is_branch(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value

-static is_jal(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
+static is_jal(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
-static is_jalr(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
+static is_jalr(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
-static valid(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
+static valid(val: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value

@@ -3923,7 +3923,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.backend.html b/coreblocks.backend.html index 5eeab8842..21de702e6 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -165,7 +165,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index 74cd56d7c..fa7c047da 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -124,12 +124,12 @@

Submodules
-deserialize_addr(raw_addr: Value) → dict[str, amaranth.hdl._ast.Value]
+deserialize_addr(raw_addr: Value) → dict[str, amaranth.hdl._ast.Value]

-serialize_addr(addr: View) → Value
+serialize_addr(addr: View) → Value

@@ -241,7 +241,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index d8a2ea761..a3cdd7d8c 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -157,7 +157,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index 6ef990397..d35e4a5bf 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -280,19 +280,19 @@

Submodules
-decompr_reg(rvc_reg: Value) → Value
+decompr_reg(rvc_reg: Value) → Value

-instr_mux(sel: Value, inputs: list[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]) → tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]
+instr_mux(sel: Value, inputs: list[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]) → tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]

-coreblocks.frontend.decoder.rvc.is_instr_compressed(instr: Value) → Value
+coreblocks.frontend.decoder.rvc.is_instr_compressed(instr: Value) → Value
@@ -313,7 +313,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index 1a34e68d9..f1159fdb1 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -187,7 +187,7 @@

Submodules
-__init__(width: int, elem_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]) → None
+__init__(width: int, elem_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]) → None

@@ -210,7 +210,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 09e2cd04c..5b5c82532 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -151,19 +151,19 @@

Submodules
-fb_addr(pc: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
+fb_addr(pc: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value

Returns the fetch block address of a given PC.

-fb_instr_idx(pc: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value
+fb_instr_idx(pc: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) → Value

Returns the index of an instruction in a fetch block for a given instruction PC.

-pc_from_fb(fb_addr: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, fb_instr_idx: int | amaranth.hdl._ast.Value) → Value
+pc_from_fb(fb_addr: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, fb_instr_idx: int | amaranth.hdl._ast.Value) → Value

For a given fetch block address and an instruction index, returns the instruction’s PC.

@@ -187,7 +187,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index 1e23cde58..86a9f7fe0 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -246,7 +246,7 @@

Submodules
-coreblocks.func_blocks.fu.div_unit.get_input(arg: View) → tuple[amaranth.hdl._ast.Value, amaranth.hdl._ast.Value]
+coreblocks.func_blocks.fu.div_unit.get_input(arg: View) → tuple[amaranth.hdl._ast.Value, amaranth.hdl._ast.Value]

@@ -528,7 +528,7 @@

SubmodulesElaboratable

-__init__(gp: GenParams)
+__init__(gen_params: GenParams)

@@ -886,7 +886,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.func_blocks.fu.lsu.html b/coreblocks.func_blocks.fu.lsu.html index d43cecfe2..7e67bc988 100644 --- a/coreblocks.func_blocks.fu.lsu.html +++ b/coreblocks.func_blocks.fu.lsu.html @@ -175,22 +175,22 @@

Submodules
-check_align(m: TModule, funct3: Value, addr: Value)
+check_align(m: TModule, funct3: Value, addr: Value)
-postprocess_load_data(m: ModuleLike, funct3: Value, raw_data: Value, addr: Value)
+postprocess_load_data(m: ModuleLike, funct3: Value, raw_data: Value, addr: Value)
-prepare_bytes_mask(m: ModuleLike, funct3: Value, addr: Value) → Signal
+prepare_bytes_mask(m: ModuleLike, funct3: Value, addr: Value) → Signal
-prepare_data_to_save(m: ModuleLike, funct3: Value, raw_data: Value, addr: Value)
+prepare_data_to_save(m: ModuleLike, funct3: Value, raw_data: Value, addr: Value)

@@ -224,7 +224,7 @@

Submodules
class coreblocks.func_blocks.fu.lsu.pma.PMALayout
-

Bases: StructLayout

+

Bases: StructLayout

__init__()
@@ -290,7 +290,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index e75c241a9..e0cf37c83 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -260,7 +260,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index 0ea9d0178..ca7a483e1 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -150,7 +150,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index 94e796f64..b6ef6b484 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -164,7 +164,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.html b/coreblocks.html index 06b2b7d7f..cdf30992e 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -232,7 +232,7 @@

Submodules
class coreblocks.core.Core
-

Bases: Component

+

Bases: Component

__init__(*, gen_params: GenParams)
@@ -268,7 +268,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.params.html b/coreblocks.params.html index 243069117..76f39e126 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -208,7 +208,7 @@

SubmodulesInstructionFunct3Type

-__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -308,7 +308,7 @@

SubmodulesInstructionFunct3Type

-__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -413,7 +413,7 @@

SubmodulesRISCVInstr

-__init__(opcode: Opcode, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -473,7 +473,7 @@

Submodules
class coreblocks.params.instr.RISCVInstr
-

Bases: ABC, ValueCastable

+

Bases: ABC, ValueCastable

__init__(opcode: Opcode)
@@ -482,7 +482,7 @@

Submodules
as_value()
-

Convert self to a value-like object.

+

Convert self to a value-like object.

This method is called by the Amaranth language to convert self to a concrete Value. It will usually return a Value object, but it may also return another value-like object to delegate its functionality.

@@ -556,7 +556,7 @@

Submodules
Returns
-
A shape-like object.
+
A shape-like object.
Raises
@@ -579,7 +579,7 @@

SubmodulesInstructionFunct3Type, InstructionFunct7Type

-__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct7: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct7: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -668,7 +668,7 @@

SubmodulesInstructionFunct3Type

-__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -757,7 +757,7 @@

SubmodulesRISCVInstr

-__init__(opcode: Opcode, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
@@ -832,7 +832,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index 054ebef77..cedabe6d1 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -123,7 +123,7 @@

Submodules
class coreblocks.peripherals.axi_lite.AXILiteMaster
-

Bases: Component

+

Bases: Component

AXI-Lite master interface.

Parameters
@@ -209,7 +209,7 @@

Submodules
class coreblocks.peripherals.axi_lite.AXILiteSignature
-

Bases: Signature

+

Bases: Signature

AXI-Lite bus signature

Parameters
@@ -375,7 +375,7 @@

Submodules
class coreblocks.peripherals.wishbone.PipelinedWishboneMaster
-

Bases: Component

+

Bases: Component

Pipelined Wishbone bus master interface.

Parameters
@@ -423,7 +423,7 @@

Submodules
class coreblocks.peripherals.wishbone.WishboneArbiter
-

Bases: Component

+

Bases: Component

Wishbone Arbiter.

Connects multiple masters to one slave. Bus is requested by asserting CYC signal and is granted to masters in a round robin manner.

@@ -536,7 +536,7 @@

Submodules
class coreblocks.peripherals.wishbone.WishboneMaster
-

Bases: Component

+

Bases: Component

Wishbone bus master interface.

Parameters
@@ -605,7 +605,7 @@

Submodules
class coreblocks.peripherals.wishbone.WishboneMemorySlave
-

Bases: Component

+

Bases: Component

Wishbone slave with memory Wishbone slave interface with addressable memory underneath.

@@ -641,7 +641,7 @@

Submodules
class coreblocks.peripherals.wishbone.WishboneMuxer
-

Bases: Component

+

Bases: Component

Wishbone Muxer.

Connects one master to multiple slaves.

@@ -714,7 +714,7 @@

Submodules
class coreblocks.peripherals.wishbone.WishboneSignature
-

Bases: Signature

+

Bases: Signature

__init__(wb_params: WishboneParameters)
@@ -746,7 +746,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html index efe87c836..10601ad0e 100644 --- a/coreblocks.priv.csr.html +++ b/coreblocks.priv.csr.html @@ -255,7 +255,7 @@

Submodules
-__init__(csr_number: Optional[int], gen_params: GenParams, *, width: Optional[int] = None, ro_bits: int = 0, init: int | amaranth.lib.enum.Enum = 0, fu_write_priority: bool = True, fu_write_filtermap: Optional[Callable[[TModule, Value], tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]] = None, fu_read_map: Optional[Callable[[TModule, Value], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]] = None, src_loc: int | tuple[str, int] = 0)
+__init__(csr_number: Optional[int], gen_params: GenParams, *, width: Optional[int] = None, ro_bits: int = 0, init: int | amaranth.lib.enum.Enum = 0, fu_write_priority: bool = True, fu_write_filtermap: Optional[Callable[[TModule, Value], tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]] = None, fu_read_map: Optional[Callable[[TModule, Value], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]] = None, src_loc: int | tuple[str, int] = 0)
Parameters
@@ -311,7 +311,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.priv.html b/coreblocks.priv.html index 38d195366..7effce9e0 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -124,7 +124,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index 75ba747e3..8eb3194c3 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -91,25 +91,25 @@

Submodules

coreblocks.priv.traps.exception module

-
-class coreblocks.priv.traps.exception.ExceptionCauseRegister
+
+class coreblocks.priv.traps.exception.ExceptionInformationRegister

Bases: Elaboratable

-

ExceptionCauseRegister

+

ExceptionInformationRegister

Stores parameters of earliest (in instruction order) exception, to save resources in the ReorderBuffer. All FUs that report exceptions should report the details to ExceptionCauseRegister and set exception bit in result data. Exception order is computed in this module. Only one exception can be reported for single instruction, exception priorities should be computed locally before calling report. If exception bit is set in the ROB, Retirement stage fetches exception details from this module.

-
-__init__(gen_params: GenParams, rob_get_indices: Method, fetch_stall_exception: Method)
+
+__init__(gen_params: GenParams, rob_get_indices: Method, fetch_stall_exception: Method)
-coreblocks.priv.traps.exception.should_update_prioriy(m: TModule, current_cause: Value, new_cause: Value) → Value
+coreblocks.priv.traps.exception.should_update_prioriy(m: TModule, current_cause: Value, new_cause: Value) → Value
@@ -145,7 +145,7 @@

Submodules
class coreblocks.priv.traps.interrupt_controller.InternalInterruptController
-

Bases: Component

+

Bases: Component

Core Internal Interrupt Controller Compatible with RISC-V privileged specification. Operates on CSR registers xIE, xIP, and parts of xSTATUS. @@ -205,7 +205,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 0b1953389..b7fe3e885 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/current-graph.html b/current-graph.html index 4fbe99ed8..e51ba3e93 100644 --- a/current-graph.html +++ b/current-graph.html @@ -100,69 +100,69 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/development-environment.html b/development-environment.html index d06542e54..1d468a70e 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

diff --git a/genindex.html b/genindex.html index 24aaea55b..26bc41c16 100644 --- a/genindex.html +++ b/genindex.html @@ -278,7 +278,7 @@

_

  • (coreblocks.priv.csr.csr_register.CSRRegister method)
    • -
  • (coreblocks.priv.traps.exception.ExceptionCauseRegister method) +
  • (coreblocks.priv.traps.exception.ExceptionInformationRegister method)
  • (coreblocks.priv.traps.instr_counter.CoreInstructionCounter method)
    • @@ -1692,12 +1692,14 @@

    E

  • EXCEPTION (coreblocks.arch.optypes.OpType attribute)
  • ExceptionCause (class in coreblocks.arch.isa_consts) -
    • -
  • ExceptionCauseRegister (class in coreblocks.priv.traps.exception)
  • ExceptionFuncUnit (class in coreblocks.func_blocks.fu.exception) +
    • +
  • ExceptionInformationRegister (class in coreblocks.priv.traps.exception)
  • ExceptionUnitComponent (class in coreblocks.func_blocks.fu.exception) +
    • +
  • extend_layout() (in module transactron.utils.transactron_helpers)
  • Extension (class in coreblocks.arch.isa)
    • @@ -2432,6 +2434,8 @@

    M

  • make_hashable() (in module transactron.utils.data_repr) +
    • +
  • make_layout() (in module transactron.utils.transactron_helpers)
  • make_logging_process() (in module transactron.testing.logging)
    • @@ -2792,11 +2796,11 @@

    M

  • MINSTRET (coreblocks.arch.csr_address.CSRAddress attribute) -
    • -
  • MINSTRETH (coreblocks.arch.csr_address.CSRAddress attribute)

    • @@ -252,7 +252,7 @@

    Submodules
    -__init__(*, name: Optional[str] = None, i: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), o: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), nonexclusive: bool = False, combiner: Optional[Callable[[Module, Sequence[View[StructLayout]], Value], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg] | collections.abc.Mapping[int, AssignArg] | collections.abc.Sequence[AssignArg]]] = None, single_caller: bool = False, src_loc: int | tuple[str, int] = 0)
    +__init__(*, name: Optional[str] = None, i: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), o: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), nonexclusive: bool = False, combiner: Optional[Callable[[Module, Sequence[View[StructLayout]], Value], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg] | collections.abc.Mapping[int, AssignArg] | collections.abc.Sequence[AssignArg]]] = None, single_caller: bool = False, src_loc: int | tuple[str, int] = 0)
    Parameters
    @@ -338,7 +338,7 @@

    Submodules
    -debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
    +debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

    @@ -598,7 +598,7 @@

    Submodules
    -AvoidedIf(cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
    +AvoidedIf(cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

    @@ -628,7 +628,7 @@

    Submodules
    -If(cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
    +If(cond: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

    @@ -638,7 +638,7 @@

    Submodules
    -Switch(test: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
    +Switch(test: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

    @@ -747,7 +747,7 @@

    Submodules
    -debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
    +debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

    @@ -845,7 +845,7 @@

    Submodules
    -method_calls: defaultdict[Method, list[tuple[transactron.core.tmodule.CtrlPath, 'View[StructLayout]', amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]]
    +method_calls: defaultdict[Method, list[tuple[transactron.core.tmodule.CtrlPath, 'View[StructLayout]', amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]]

    @@ -960,7 +960,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

    diff --git a/transactron.html b/transactron.html index 8a0c4edfb..a85bbeac4 100644 --- a/transactron.html +++ b/transactron.html @@ -752,7 +752,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

    diff --git a/transactron.lib.html b/transactron.lib.html index e7ebcc6f5..377a21c1a 100644 --- a/transactron.lib.html +++ b/transactron.lib.html @@ -136,10 +136,10 @@

    Submodules
    class transactron.lib.adapters.AdapterBase
    -

    Bases: Component

    +

    Bases: Component

    -__init__(iface: Method, layout_in: StructLayout, layout_out: StructLayout)
    +__init__(iface: Method, layout_in: StructLayout, layout_out: StructLayout)
    @@ -154,7 +154,7 @@

    Submodules
    -debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
    +debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

    @@ -236,7 +236,7 @@

    Submodules
    -__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], src_loc: int | tuple[str, int] = 0)
    +__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], src_loc: int | tuple[str, int] = 0)
    Parameters
    @@ -275,7 +275,7 @@

    Submodules
    -__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], *, src_loc: int | tuple[str, int] = 0)
    +__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], *, src_loc: int | tuple[str, int] = 0)
    Parameters
    @@ -318,7 +318,7 @@

    Submodules
    -__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), rev_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), *, src_loc: int | tuple[str, int] = 0)
    +__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), rev_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']] = (), *, src_loc: int | tuple[str, int] = 0)
    Parameters
    @@ -432,7 +432,7 @@

    Submodules
    -__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], *, src_loc: int | tuple[str, int] = 0)
    +__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], *, src_loc: int | tuple[str, int] = 0)
    Parameters
    @@ -503,7 +503,7 @@

    Submodules
    -__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']])
    +__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']])
    Parameters
    @@ -537,7 +537,7 @@

    Submodules
    -__init__(n: int, layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']])
    +__init__(n: int, layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']])

    @@ -737,7 +737,7 @@

    Submodules
    -__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], depth: int, *, src_loc: int | tuple[str, int] = 0) → None
    +__init__(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], depth: int, *, src_loc: int | tuple[str, int] = 0) → None
    Parameters
    @@ -822,7 +822,7 @@

    Submodules
    -assertion(m: ModuleLike, value: Value, format: str = '', *args, src_loc_at: int = 0, **kwargs)
    +assertion(m: ModuleLike, value: Value, format: str = '', *args, src_loc_at: int = 0, **kwargs)

    Define an assertion.

    This function might help find some hardware bugs which might otherwise be hard to detect. If value is false, it will terminate the simulation or @@ -833,14 +833,14 @@

    Submodules
    -debug(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)
    +debug(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)

    Log a message with severity ‘DEBUG’.

    See HardwareLogger.log function for more details.

    -error(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)
    +error(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)

    Log a message with severity ‘ERROR’.

    This severity level has special semantics. If a log with this serverity level is triggered, the simulation will be terminated.

    @@ -849,14 +849,14 @@

    Submodules
    -info(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)
    +info(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)

    Log a message with severity ‘INFO’.

    See HardwareLogger.log function for more details.

    -log(m: ModuleLike, level: int, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, src_loc_at: int = 0)
    +log(m: ModuleLike, level: int, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, src_loc_at: int = 0)

    Registers a hardware log record with the given severity.

    Parameters
    @@ -880,7 +880,7 @@

    Submodules
    -warning(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)
    +warning(m: ModuleLike, trigger: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, format: str, *args, **kwargs)

    Log a message with severity ‘WARNING’.

    See HardwareLogger.log function for more details.

    @@ -1029,7 +1029,7 @@

    Submodules
    -transactron.lib.logging.get_trigger_bit(level: int, namespace_regexp: str = '.*') → Value
    +transactron.lib.logging.get_trigger_bit(level: int, namespace_regexp: str = '.*') → Value

    Get a trigger bit for logs of the given severity level and in the specified namespace.

    The signal returned by this function is high whenever the trigger signal @@ -1134,7 +1134,7 @@

    Submodules
    -debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
    +debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

    Returns tree-like SignalBundle composed of all metric registers.

    @@ -1236,7 +1236,7 @@

    Submodules
    -add(m: TModule, sample: Value)
    +add(m: TModule, sample: Value)

    Adds a new sample to the histogram.

    Should be called in the body of either a transaction or a method.

    @@ -1568,7 +1568,7 @@

    Submodules
    -start(m: TModule, *, slot: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
    +start(m: TModule, *, slot: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

    Registers the start of an event for a given slot tag.

    Should be called in the body of either a transaction or a method.

    @@ -1585,7 +1585,7 @@

    Submodules
    -stop(m: TModule, *, slot: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
    +stop(m: TModule, *, slot: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)

    Registers the end of the event for a given slot tag.

    Should be called in the body of either a transaction or a method.

    @@ -1645,7 +1645,7 @@

    Submodules
    -__init__(args_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], results_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], src_loc: int | tuple[str, int] = 0)
    +__init__(args_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], results_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], src_loc: int | tuple[str, int] = 0)
    Parameters
    @@ -1834,7 +1834,7 @@

    Submodules
    -__init__(address_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], data_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], entries_number: int)
    +__init__(address_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], data_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], entries_number: int)
    Parameters
    @@ -1975,7 +1975,7 @@

    Submodules
    -__init__(method1: Method, method2: Method, *, i_fun: Optional[Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]] = None, o_fun: Optional[Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]] = None, src_loc: int | tuple[str, int] = 0)
    +__init__(method1: Method, method2: Method, *, i_fun: Optional[Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]] = None, o_fun: Optional[Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, RecordDict]]] = None, src_loc: int | tuple[str, int] = 0)
    Parameters
    @@ -2021,7 +2021,7 @@

    Submodules
    -__init__(target: Method, condition: Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable], default: Optional[Union[Value, int, Enum, ValueCastable, Mapping[str, RecordDict]]] = None, *, use_condition: bool = False, src_loc: int | tuple[str, int] = 0)
    +__init__(target: Method, condition: Callable[[TModule, View[StructLayout]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable], default: Optional[Union[Value, int, Enum, ValueCastable, Mapping[str, RecordDict]]] = None, *, use_condition: bool = False, src_loc: int | tuple[str, int] = 0)
    Parameters
    @@ -2066,7 +2066,7 @@

    Submodules
    -__init__(target: Method, *, i_transform: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, 'View[StructLayout]'], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, o_transform: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, 'View[StructLayout]'], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, src_loc: int | tuple[str, int] = 0)
    +__init__(target: Method, *, i_transform: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, 'View[StructLayout]'], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, o_transform: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, 'View[StructLayout]'], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, src_loc: int | tuple[str, int] = 0)
    Parameters
    @@ -2096,7 +2096,7 @@

    SubmodulesElaboratable, Unifier

    -__init__(targets: list[transactron.core.method.Method], combiner: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, list['View[StructLayout]']], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, *, src_loc: int | tuple[str, int] = 0)
    +__init__(targets: list[transactron.core.method.Method], combiner: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, list['View[StructLayout]']], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, *, src_loc: int | tuple[str, int] = 0)

    Method product.

    Takes arbitrary, non-zero number of target methods, and constructs a method which calls all of the target methods using the same @@ -2135,7 +2135,7 @@

    SubmodulesElaboratable, Unifier

    -__init__(targets: list[transactron.core.method.Method], combiner: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, list[tuple[amaranth.hdl._ast.Value, 'View[StructLayout]']]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, *, src_loc: int | tuple[str, int] = 0)
    +__init__(targets: list[transactron.core.method.Method], combiner: Optional[tuple[amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], collections.abc.Callable[[transactron.core.tmodule.TModule, list[tuple[amaranth.hdl._ast.Value, 'View[StructLayout]']]], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, 'RecordDict']]]] = None, *, src_loc: int | tuple[str, int] = 0)

    Method product with optional calling.

    Takes arbitrary, non-zero number of target methods, and constructs a method which tries to call all of the target methods using the same @@ -2238,7 +2238,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

    diff --git a/transactron.testing.html b/transactron.testing.html index fdf808da2..77ecd2b8b 100644 --- a/transactron.testing.html +++ b/transactron.testing.html @@ -91,7 +91,7 @@

    Submodules

    transactron.testing.functions module

    -transactron.testing.functions.get_outputs(field: View) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Union[int, RecordIntDict]]]
    +transactron.testing.functions.get_outputs(field: View) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Union[int, RecordIntDict]]]
    @@ -120,7 +120,7 @@

    Submodules
    class transactron.testing.infrastructure.PysimSimulator
    -

    Bases: Simulator

    +

    Bases: Simulator

    __init__(module: HasElaborate, max_cycles: float = 100000.0, add_transaction_module=True, traces_file=None, clk_period=1e-06)
    @@ -128,7 +128,7 @@

    Submodules
    -add_process(f: Callable[[], Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, T]])
    +add_process(f: Callable[[], Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, T]])

    @@ -269,12 +269,12 @@

    Submodules
    -transactron.testing.input_generation.generate_based_on_layout(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]) → SearchStrategy[Mapping[str, Union[int, RecordIntDict]]]
    +transactron.testing.input_generation.generate_based_on_layout(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]) → SearchStrategy[Mapping[str, Union[int, RecordIntDict]]]

    -transactron.testing.input_generation.generate_method_input(args: list[tuple[str, amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]]]) → Union[int, ForwardRef('RecordIntDict')]]]]
    +transactron.testing.input_generation.generate_method_input(args: list[tuple[str, amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]]]) → Union[int, ForwardRef('RecordIntDict')]]]]
    @@ -284,7 +284,7 @@

    Submodules
    -transactron.testing.input_generation.generate_process_input(elem_count: int, max_nops: int, layouts: list[tuple[str, amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]]]) → OpNOP]]
    +transactron.testing.input_generation.generate_process_input(elem_count: int, max_nops: int, layouts: list[tuple[str, amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]]]) → OpNOP]]

    @@ -329,7 +329,7 @@

    Submodules

    transactron.testing.sugar module

    -transactron.testing.sugar.def_method_mock(tb_getter: Union[Callable[[], TestbenchIO], Callable[[Any], TestbenchIO]], sched_prio: int = 0, **kwargs) → Callable[[Callable[[...], Optional[Mapping[str, Union[int, RecordIntDict]]]]], Callable[[], Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]]]
    +transactron.testing.sugar.def_method_mock(tb_getter: Union[Callable[[], TestbenchIO], Callable[[Any], TestbenchIO]], sched_prio: int = 0, **kwargs) → Callable[[Callable[[...], Optional[Mapping[str, Union[int, RecordIntDict]]]]], Callable[[], Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]]]

    Decorator function to create method mock handlers. It should be applied on a function which describes functionality which we want to invoke on method call. Such function will be wrapped by method_handle_loop and called on each @@ -368,87 +368,87 @@

    Submodules
    -call(data: Mapping[str, Union[int, RecordIntDict]] = {}, /, **kwdata: int | collections.abc.Mapping[str, Union[int, RecordIntDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Any]]
    +call(data: Mapping[str, Union[int, RecordIntDict]] = {}, /, **kwdata: int | collections.abc.Mapping[str, Union[int, RecordIntDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Any]]

    -call_do() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Union[int, RecordIntDict]]]
    +call_do() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Union[int, RecordIntDict]]]
    -call_init(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}, /, **kwdata: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, Union[amaranth.hdl._ast.Value, int, enum.Enum, amaranth.hdl._ast.ValueCastable, RecordValueDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    +call_init(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}, /, **kwdata: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, Union[amaranth.hdl._ast.Value, int, enum.Enum, amaranth.hdl._ast.ValueCastable, RecordValueDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    -call_result() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Optional[Mapping[str, Any]]]
    +call_result() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Optional[Mapping[str, Any]]]
    -call_try(data: Mapping[str, Union[int, RecordIntDict]] = {}, /, **kwdata: int | collections.abc.Mapping[str, Union[int, RecordIntDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Optional[Mapping[str, Any]]]
    +call_try(data: Mapping[str, Union[int, RecordIntDict]] = {}, /, **kwdata: int | collections.abc.Mapping[str, Union[int, RecordIntDict]]) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Optional[Mapping[str, Any]]]
    -debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
    +debug_signals() → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
    -disable() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    +disable() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    -done() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, int]
    +done() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, int]
    -enable() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    +enable() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    -get_outputs() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Any]]
    +get_outputs() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Mapping[str, Any]]
    -method_argument() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Optional[Mapping[str, Any]]]
    +method_argument() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, Optional[Mapping[str, Any]]]
    -method_handle(function: Callable[[...], Optional[Mapping[str, Union[int, RecordIntDict]]]], *, enable: Optional[Callable[[], bool]] = None, validate_arguments: Optional[Callable[[...], bool]] = None, extra_settle_count: int = 0) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    +method_handle(function: Callable[[...], Optional[Mapping[str, Union[int, RecordIntDict]]]], *, enable: Optional[Callable[[], bool]] = None, validate_arguments: Optional[Callable[[...], bool]] = None, extra_settle_count: int = 0) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    -method_handle_loop(function: Callable[[...], Optional[Mapping[str, Union[int, RecordIntDict]]]], *, enable: Optional[Callable[[], bool]] = None, validate_arguments: Optional[Callable[[...], bool]] = None, extra_settle_count: int = 0) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    +method_handle_loop(function: Callable[[...], Optional[Mapping[str, Union[int, RecordIntDict]]]], *, enable: Optional[Callable[[], bool]] = None, validate_arguments: Optional[Callable[[...], bool]] = None, extra_settle_count: int = 0) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    -method_return(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    +method_return(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    -set_enable(en) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    +set_enable(en) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    -set_inputs(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    +set_inputs(data: Mapping[str, Union[Value, int, Enum, ValueCastable, RecordValueDict]] = {}) → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    -wait_until_done() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]
    +wait_until_done() → Generator[Optional[Union[Command, Value, Statement, CoreblocksCommand]], Any, None]

    @@ -471,7 +471,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

    diff --git a/transactron.utils.amaranth_ext.html b/transactron.utils.amaranth_ext.html index b35c01160..23e198d67 100644 --- a/transactron.utils.amaranth_ext.html +++ b/transactron.utils.amaranth_ext.html @@ -151,7 +151,7 @@

    Submodules
    -static create(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, outputs_count: int = 1, name: Optional[str] = None) → list[tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]]
    +static create(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, outputs_count: int = 1, name: Optional[str] = None) → list[tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]]

    Syntax sugar for creating MultiPriorityEncoder

    This static method allows to use MultiPriorityEncoder in a more functional way. Instead of creating the instance manually, connecting all the signals and @@ -193,7 +193,7 @@

    Submodules
    -static create_simple(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, name: Optional[str] = None) → tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]
    +static create_simple(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, name: Optional[str] = None) → tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]

    Syntax sugar for creating MultiPriorityEncoder

    This is the same as create function, but with outputs_count hardcoded to 1.

    @@ -202,7 +202,7 @@

    Submodules
    -transactron.utils.amaranth_ext.elaboratables.OneHotSwitch(m: ModuleLike, test: Value)
    +transactron.utils.amaranth_ext.elaboratables.OneHotSwitch(m: ModuleLike, test: Value)

    One-hot switch.

    This function allows one-hot matching in the style similar to the standard Amaranth Switch. This allows to get the performance benefit of using @@ -232,9 +232,9 @@

    Submodules
    -transactron.utils.amaranth_ext.elaboratables.OneHotSwitchDynamic(m: ModuleLike, test: Value, *, default: Literal[True]) → Iterable[Optional[int]]
    +transactron.utils.amaranth_ext.elaboratables.OneHotSwitchDynamic(m: ModuleLike, test: Value, *, default: Literal[True]) → Iterable[Optional[int]]
    -transactron.utils.amaranth_ext.elaboratables.OneHotSwitchDynamic(m: ModuleLike, test: Value, *, default: Literal[False] = False) → Iterable[int]
    +transactron.utils.amaranth_ext.elaboratables.OneHotSwitchDynamic(m: ModuleLike, test: Value, *, default: Literal[False] = False) → Iterable[int]

    Dynamic one-hot switch.

    This function allows simple one-hot matching on signals which can have variable bit widths.

    @@ -300,7 +300,7 @@

    Submodules
    -static create(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, first: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, last: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, outputs_count: int = 1, name: Optional[str] = None) → list[tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]]
    +static create(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, first: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, last: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, outputs_count: int = 1, name: Optional[str] = None) → list[tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]]

    Syntax sugar for creating RingMultiPriorityEncoder

    This static method allows to use RingMultiPriorityEncoder in a more functional way. Instead of creating the instance manually, connecting all the signals and @@ -348,7 +348,7 @@

    Submodules
    -static create_simple(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, first: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, last: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, name: Optional[str] = None) → tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]
    +static create_simple(m: Module, input_width: int, input: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, first: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, last: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, name: Optional[str] = None) → tuple[amaranth.hdl._ast.Signal, amaranth.hdl._ast.Signal]

    Syntax sugar for creating RingMultiPriorityEncoder

    This is the same as create function, but with outputs_count hardcoded to 1.

    @@ -436,29 +436,29 @@

    Submodules

    transactron.utils.amaranth_ext.functions module

    -transactron.utils.amaranth_ext.functions.count_leading_zeros(s: Value) → Value
    +transactron.utils.amaranth_ext.functions.count_leading_zeros(s: Value) → Value
    -transactron.utils.amaranth_ext.functions.count_trailing_zeros(s: Value) → Value
    +transactron.utils.amaranth_ext.functions.count_trailing_zeros(s: Value) → Value
    -transactron.utils.amaranth_ext.functions.flatten_signals(signals: amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]) → Iterable[Signal]
    +transactron.utils.amaranth_ext.functions.flatten_signals(signals: amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]) → Iterable[Signal]

    Flattens input data, which can be either a signal, a record, a list (or a dict) of SignalBundle items.

    -transactron.utils.amaranth_ext.functions.mod_incr(sig: Value, mod: int) → Value
    +transactron.utils.amaranth_ext.functions.mod_incr(sig: Value, mod: int) → Value

    Perform (sig+1) % mod operation.

    -transactron.utils.amaranth_ext.functions.popcount(s: Value)
    +transactron.utils.amaranth_ext.functions.popcount(s: Value)
    @@ -478,7 +478,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.

    diff --git a/transactron.utils.html b/transactron.utils.html index 71b91a8e0..1e6bdd50b 100644 --- a/transactron.utils.html +++ b/transactron.utils.html @@ -131,7 +131,7 @@

    Submodules
    -transactron.utils.assign.assign(lhs: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg] | collections.abc.Mapping[int, AssignArg] | collections.abc.Sequence[AssignArg], rhs: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg] | collections.abc.Mapping[int, AssignArg] | collections.abc.Sequence[AssignArg], *, fields: transactron.utils.assign.AssignType | collections.abc.Iterable[str | int] | collections.abc.Mapping[str | int, AssignFields] = AssignType.RHS, lhs_strict=False, rhs_strict=False) → Iterable[Assign]
    +transactron.utils.assign.assign(lhs: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg] | collections.abc.Mapping[int, AssignArg] | collections.abc.Sequence[AssignArg], rhs: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg] | collections.abc.Mapping[int, AssignArg] | collections.abc.Sequence[AssignArg], *, fields: transactron.utils.assign.AssignType | collections.abc.Iterable[str | int] | collections.abc.Mapping[str | int, AssignFields] = AssignType.RHS, lhs_strict=False, rhs_strict=False) → Iterable[Assign]

    Safe structured assignment.

    This function recursively generates assignment statements for field-containing structures. This includes: @@ -250,7 +250,7 @@

    Submodules
    -transactron.utils.data_repr.data_layout(val: amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum]) → amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]
    +transactron.utils.data_repr.data_layout(val: amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum]) → amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']]

    @@ -277,7 +277,7 @@

    Submodules
    -transactron.utils.data_repr.layout_subset(layout: StructLayout, *, fields: set[str]) → StructLayout
    +transactron.utils.data_repr.layout_subset(layout: StructLayout, *, fields: set[str]) → StructLayout

    @@ -334,7 +334,7 @@

    Submodules

    transactron.utils.debug_signals module

    -transactron.utils.debug_signals.auto_debug_signals(thing) → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]
    +transactron.utils.debug_signals.auto_debug_signals(thing) → amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]] | collections.abc.Mapping[str, amaranth.hdl._ast.Signal | amaranth.hdl._rec.Record | amaranth.lib.data.View | collections.abc.Iterable[SignalBundle] | collections.abc.Mapping[str, SignalBundle]]

    Automatic debug signal generation.

    Exposes class attributes with debug signals (Amaranth Signals, Records, Arrays and Elaboratables, Methods, classes @@ -735,7 +735,7 @@

    Submodules
    -transactron.utils.gen.generate_verilog(elaboratable: Elaboratable, ports: Optional[list[amaranth.hdl._ast.Value]] = None, top_name: str = 'top') → tuple[str, transactron.utils.gen.GenerationInfo]
    +transactron.utils.gen.generate_verilog(elaboratable: Elaboratable, ports: Optional[list[amaranth.hdl._ast.Value]] = None, top_name: str = 'top') → tuple[str, transactron.utils.gen.GenerationInfo]

    @@ -760,9 +760,14 @@

    Submodulestransactron.utils.transactron_helpers.def_helper(description, func: Callable[[...], T], tp: type[U], arg: U, /, **kwargs) → T

    +
    +
    +transactron.utils.transactron_helpers.extend_layout(layout: StructLayout, *fields: tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]) → StructLayout
    +
    +
    -transactron.utils.transactron_helpers.from_method_layout(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]]) → StructLayout
    +transactron.utils.transactron_helpers.from_method_layout(layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]]) → StructLayout
    @@ -780,6 +785,11 @@

    Submodulestransactron.utils.transactron_helpers.longest_common_prefix(*seqs: Sequence[T]) → Sequence[T]

    +
    +
    +transactron.utils.transactron_helpers.make_layout(*fields: tuple[str, amaranth.hdl._ast.Shape | amaranth.hdl._ast.ShapeCastable | int | range | type[enum.Enum] | list[tuple[str, ForwardRef('ShapeLike | LayoutList')]]]) → StructLayout
    +
    +
    transactron.utils.transactron_helpers.method_def_helper(method, func: Callable[[...], T], arg: View[StructLayout]) → T
    @@ -813,7 +823,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:37 2024-10-09. + Last updated on 06:35 2024-10-15.