diff --git a/.doctrees/Current_graph.doctree b/.doctrees/Current_graph.doctree index 2e291a1a0..c16c8125f 100644 Binary files a/.doctrees/Current_graph.doctree and b/.doctrees/Current_graph.doctree differ diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index d88a0ca29..4a1bf2615 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index 4673320e5..be71f3acf 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index c51cb5e86..f90d487db 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/Assumptions.html b/Assumptions.html index 01fefcf61..5a2044731 100644 --- a/Assumptions.html +++ b/Assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/Current_graph.html b/Current_graph.html index 799a4d97a..723773610 100644 --- a/Current_graph.html +++ b/Current_graph.html @@ -105,16 +105,16 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/Development_environment.html b/Development_environment.html index accd60330..c2652bc32 100644 --- a/Development_environment.html +++ b/Development_environment.html @@ -178,7 +178,7 @@

build_docs.sh

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/Home.html b/Home.html index ad8e0fbb0..6cb22ffe7 100644 --- a/Home.html +++ b/Home.html @@ -129,7 +129,7 @@

Documentation

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/Problem-checklist.html b/Problem-checklist.html index 3b938dd0a..3c459f8cb 100644 --- a/Problem-checklist.html +++ b/Problem-checklist.html @@ -105,7 +105,7 @@

Problem checklist

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/Transactions.html b/Transactions.html index 4a227c148..d539ccbd6 100644 --- a/Transactions.html +++ b/Transactions.html @@ -409,7 +409,7 @@

Transaction and method nesting

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 5fb22aab3..a75639e9a 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -22,16 +22,16 @@ BasicFifo_read["read"] end subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"] - SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] SimpleWBCacheRefiller_accept_refill["accept_refill"] + SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] SimpleWBCacheRefiller_start_refill["start_refill"] end subgraph ICache["icache ICache"] - ICache_issue_req["issue_req"] ICache_ICache["ICache"] ICache_ICache1["ICache"] - ICache_accept_res["accept_res"] ICache_ICache2["ICache"] + ICache_accept_res["accept_res"] + ICache_issue_req["issue_req"] subgraph FIFO1["req_fifo FIFO"] FIFO1_write["write"] FIFO1_read["read"] @@ -63,10 +63,10 @@ RegisterFile_free["free"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_retire["retire"] - ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_peek["peek"] + ReorderBuffer_retire["retire"] + ReorderBuffer_put["put"] ReorderBuffer_get_indices["get_indices"] end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] @@ -93,23 +93,23 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_update["update"] - RSFuncBlock_get_result["get_result"] RSFuncBlock_insert["insert"] RSFuncBlock_select["select"] + RSFuncBlock_update["update"] + RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] - RS_select["select"] RS_RS["RS"] - RS_take["take"] - RS_insert["insert"] - RS_update["update"] RS_RS1["RS"] + RS_update["update"] RS_RS2["RS"] RS_RS3["RS"] + RS_take["take"] + RS_insert["insert"] + RS_select["select"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph FIFO2["fifo FIFO"] FIFO2_read["read"] FIFO2_write["write"] @@ -122,20 +122,20 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_branch_result["branch_result"] + JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] subgraph FIFO4["fifo_res FIFO"] - FIFO4_write["write"] FIFO4_read["read"] + FIFO4_write["write"] end subgraph FIFO5["fifo_branch FIFO"] FIFO5_read["read"] @@ -146,8 +146,8 @@ WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] + ExceptionFuncUnit_issue["issue"] subgraph FIFO6["fifo FIFO"] FIFO6_write["write"] FIFO6_read["read"] @@ -199,19 +199,19 @@ subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister["register_low CSRRegister"] - CSRRegister_read["read"] CSRRegister_write["write"] + CSRRegister_read["read"] end subgraph CSRRegister1["register_high CSRRegister"] - CSRRegister1_read["read"] CSRRegister1_write["write"] + CSRRegister1_read["read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister2["register_low CSRRegister"] - CSRRegister2_write["write"] CSRRegister2_read["read"] + CSRRegister2_write["write"] end subgraph CSRRegister3["register_high CSRRegister"] CSRRegister3_read["read"] @@ -223,16 +223,16 @@ end end subgraph FIFO7["fifo_decode FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end subgraph Decode["decode Decode"] Decode_Decode["Decode"] end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO8["alloc_rename_buf FIFO"] - FIFO8_read["read"] FIFO8_write["write"] + FIFO8_read["read"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -245,8 +245,8 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -300,12 +300,12 @@ end end Core_InitFreeRFFifo --> BasicFifo_write - Retirement_Retirement --> BasicFifo_write + Retirement_Retirement1 --> BasicFifo_write SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request - ICache_ICache2 --> Forwarder_write - ICache_ICache --> SimpleWBCacheRefiller_start_refill - SimpleWBCacheRefiller_accept_refill --> ICache_ICache1 - WishboneMaster_result --> ICache_ICache1 + ICache_ICache --> Forwarder_write + ICache_ICache1 --> SimpleWBCacheRefiller_start_refill + SimpleWBCacheRefiller_accept_refill --> ICache_ICache2 + WishboneMaster_result --> ICache_ICache2 Fetch_Fetch --> ICache_issue_req Fetch_Fetch --> FIFO1_write Fetch_Fetch --> BasicFifo1_write @@ -353,14 +353,14 @@ ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update - RS_RS --> WakeupSelect_WakeupSelect + RS_RS2 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect RS_take --> WakeupSelect3_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO2_write - RS_RS2 --> WakeupSelect1_WakeupSelect + RS_RS1 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write RS_RS3 --> WakeupSelect2_WakeupSelect @@ -375,7 +375,7 @@ ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals WakeupSelect2_WakeupSelect --> FIFO4_write WakeupSelect2_WakeupSelect --> FIFO5_write - RS_RS1 --> WakeupSelect3_WakeupSelect + RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO6_write ConnectTrans2_ConnectTrans --> Forwarder2_write @@ -398,18 +398,18 @@ Collector1_method --> ConnectTrans_ConnectTrans Forwarder2_read --> ConnectTrans_ConnectTrans LSUDummy_get_result --> ConnectTrans1_ConnectTrans - ReorderBuffer_peek --> Retirement_Retirement1 - Retirement_Retirement1 --> LSUDummy_precommit - ReorderBuffer_retire --> Retirement_Retirement - ExceptionCauseRegister_get --> Retirement_Retirement - Retirement_Retirement --> CSRRegister4_write - Retirement_Retirement --> RRAT_commit - Retirement_Retirement --> RegisterFile_free - Retirement_Retirement <--> DoubleCounterCSR2_increment - CSRRegister5_read --> Retirement_Retirement - Retirement_Retirement --> CSRRegister5_write - CSRRegister6_read --> Retirement_Retirement - Retirement_Retirement --> CSRRegister6_write + ReorderBuffer_peek --> Retirement_Retirement + Retirement_Retirement --> LSUDummy_precommit + ReorderBuffer_retire --> Retirement_Retirement1 + ExceptionCauseRegister_get --> Retirement_Retirement1 + Retirement_Retirement1 --> CSRRegister4_write + Retirement_Retirement1 --> RRAT_commit + Retirement_Retirement1 --> RegisterFile_free + Retirement_Retirement1 <--> DoubleCounterCSR2_increment + CSRRegister5_read --> Retirement_Retirement1 + Retirement_Retirement1 --> CSRRegister5_write + CSRRegister6_read --> Retirement_Retirement1 + Retirement_Retirement1 --> CSRRegister6_write GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister_write diff --git a/api.html b/api.html index ce015243a..1b2e4ec93 100644 --- a/api.html +++ b/api.html @@ -235,7 +235,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/auto_graph.html b/auto_graph.html index 7b90a0a9e..205606384 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -101,16 +101,16 @@ BasicFifo_read["read"] end subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"] - SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] SimpleWBCacheRefiller_accept_refill["accept_refill"] + SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] SimpleWBCacheRefiller_start_refill["start_refill"] end subgraph ICache["icache ICache"] - ICache_issue_req["issue_req"] ICache_ICache["ICache"] ICache_ICache1["ICache"] - ICache_accept_res["accept_res"] ICache_ICache2["ICache"] + ICache_accept_res["accept_res"] + ICache_issue_req["issue_req"] subgraph FIFO1["req_fifo FIFO"] FIFO1_write["write"] FIFO1_read["read"] @@ -142,10 +142,10 @@ RegisterFile_free["free"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_retire["retire"] - ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_peek["peek"] + ReorderBuffer_retire["retire"] + ReorderBuffer_put["put"] ReorderBuffer_get_indices["get_indices"] end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] @@ -172,23 +172,23 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_update["update"] - RSFuncBlock_get_result["get_result"] RSFuncBlock_insert["insert"] RSFuncBlock_select["select"] + RSFuncBlock_update["update"] + RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] - RS_select["select"] RS_RS["RS"] - RS_take["take"] - RS_insert["insert"] - RS_update["update"] RS_RS1["RS"] + RS_update["update"] RS_RS2["RS"] RS_RS3["RS"] + RS_take["take"] + RS_insert["insert"] + RS_select["select"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph FIFO2["fifo FIFO"] FIFO2_read["read"] FIFO2_write["write"] @@ -201,20 +201,20 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_branch_result["branch_result"] + JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] subgraph FIFO4["fifo_res FIFO"] - FIFO4_write["write"] FIFO4_read["read"] + FIFO4_write["write"] end subgraph FIFO5["fifo_branch FIFO"] FIFO5_read["read"] @@ -225,8 +225,8 @@ WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] + ExceptionFuncUnit_issue["issue"] subgraph FIFO6["fifo FIFO"] FIFO6_write["write"] FIFO6_read["read"] @@ -278,19 +278,19 @@ subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister["register_low CSRRegister"] - CSRRegister_read["read"] CSRRegister_write["write"] + CSRRegister_read["read"] end subgraph CSRRegister1["register_high CSRRegister"] - CSRRegister1_read["read"] CSRRegister1_write["write"] + CSRRegister1_read["read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister2["register_low CSRRegister"] - CSRRegister2_write["write"] CSRRegister2_read["read"] + CSRRegister2_write["write"] end subgraph CSRRegister3["register_high CSRRegister"] CSRRegister3_read["read"] @@ -302,16 +302,16 @@ end end subgraph FIFO7["fifo_decode FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end subgraph Decode["decode Decode"] Decode_Decode["Decode"] end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO8["alloc_rename_buf FIFO"] - FIFO8_read["read"] FIFO8_write["write"] + FIFO8_read["read"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -324,8 +324,8 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -379,12 +379,12 @@ end end Core_InitFreeRFFifo --> BasicFifo_write -Retirement_Retirement --> BasicFifo_write +Retirement_Retirement1 --> BasicFifo_write SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request -ICache_ICache2 --> Forwarder_write -ICache_ICache --> SimpleWBCacheRefiller_start_refill -SimpleWBCacheRefiller_accept_refill --> ICache_ICache1 -WishboneMaster_result --> ICache_ICache1 +ICache_ICache --> Forwarder_write +ICache_ICache1 --> SimpleWBCacheRefiller_start_refill +SimpleWBCacheRefiller_accept_refill --> ICache_ICache2 +WishboneMaster_result --> ICache_ICache2 Fetch_Fetch --> ICache_issue_req Fetch_Fetch --> FIFO1_write Fetch_Fetch --> BasicFifo1_write @@ -432,14 +432,14 @@ ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update -RS_RS --> WakeupSelect_WakeupSelect +RS_RS2 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect RS_take --> WakeupSelect3_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO2_write -RS_RS2 --> WakeupSelect1_WakeupSelect +RS_RS1 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write RS_RS3 --> WakeupSelect2_WakeupSelect @@ -454,7 +454,7 @@ ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals WakeupSelect2_WakeupSelect --> FIFO4_write WakeupSelect2_WakeupSelect --> FIFO5_write -RS_RS1 --> WakeupSelect3_WakeupSelect +RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO6_write ConnectTrans2_ConnectTrans --> Forwarder2_write @@ -477,18 +477,18 @@ Collector1_method --> ConnectTrans_ConnectTrans Forwarder2_read --> ConnectTrans_ConnectTrans LSUDummy_get_result --> ConnectTrans1_ConnectTrans -ReorderBuffer_peek --> Retirement_Retirement1 -Retirement_Retirement1 --> LSUDummy_precommit -ReorderBuffer_retire --> Retirement_Retirement -ExceptionCauseRegister_get --> Retirement_Retirement -Retirement_Retirement --> CSRRegister4_write -Retirement_Retirement --> RRAT_commit -Retirement_Retirement --> RegisterFile_free -Retirement_Retirement <--> DoubleCounterCSR2_increment -CSRRegister5_read --> Retirement_Retirement -Retirement_Retirement --> CSRRegister5_write -CSRRegister6_read --> Retirement_Retirement -Retirement_Retirement --> CSRRegister6_write +ReorderBuffer_peek --> Retirement_Retirement +Retirement_Retirement --> LSUDummy_precommit +ReorderBuffer_retire --> Retirement_Retirement1 +ExceptionCauseRegister_get --> Retirement_Retirement1 +Retirement_Retirement1 --> CSRRegister4_write +Retirement_Retirement1 --> RRAT_commit +Retirement_Retirement1 --> RegisterFile_free +Retirement_Retirement1 <--> DoubleCounterCSR2_increment +CSRRegister5_read --> Retirement_Retirement1 +Retirement_Retirement1 --> CSRRegister5_write +CSRRegister6_read --> Retirement_Retirement1 +Retirement_Retirement1 --> CSRRegister6_write GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister_write @@ -509,7 +509,7 @@

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/components/icache.html b/components/icache.html index 53965da31..ec868c72f 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 964c8f985..dd03d89ce 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -399,7 +399,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/coreblocks.fu.html b/coreblocks.fu.html index cd7caea72..bc4946181 100644 --- a/coreblocks.fu.html +++ b/coreblocks.fu.html @@ -817,7 +817,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/coreblocks.fu.unsigned_multiplication.html b/coreblocks.fu.unsigned_multiplication.html index 0b679e87c..8f7ce8708 100644 --- a/coreblocks.fu.unsigned_multiplication.html +++ b/coreblocks.fu.unsigned_multiplication.html @@ -237,7 +237,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/coreblocks.html b/coreblocks.html index 6e694a1ba..824bb16ed 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -218,7 +218,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/coreblocks.params.html b/coreblocks.params.html index ad550cc4f..6e7c8637d 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -2404,7 +2404,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index dd4d9e560..89e4d6a7a 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -348,7 +348,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 184e35b19..d540a21ba 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/coreblocks.stages.html b/coreblocks.stages.html index 2d421a583..539a9a26a 100644 --- a/coreblocks.stages.html +++ b/coreblocks.stages.html @@ -266,7 +266,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/coreblocks.structs_common.html b/coreblocks.structs_common.html index d49840e7d..d2c8c04c1 100644 --- a/coreblocks.structs_common.html +++ b/coreblocks.structs_common.html @@ -454,7 +454,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/coreblocks.utils.html b/coreblocks.utils.html index 53afbfee3..d71f1fd28 100644 --- a/coreblocks.utils.html +++ b/coreblocks.utils.html @@ -478,7 +478,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/genindex.html b/genindex.html index 2875524f3..e9a662495 100644 --- a/genindex.html +++ b/genindex.html @@ -2776,7 +2776,7 @@

Z

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/index.html b/index.html index ab21ef5a1..0b3ead185 100644 --- a/index.html +++ b/index.html @@ -221,7 +221,7 @@

Coreblocks

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/miscellany/exceptionsSummary.html b/miscellany/exceptionsSummary.html index d4bf9bdc6..fbc78bf78 100644 --- a/miscellany/exceptionsSummary.html +++ b/miscellany/exceptionsSummary.html @@ -271,7 +271,7 @@

Summary

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/modules-coreblocks.html b/modules-coreblocks.html index b3797e134..f1c7d1824 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -187,7 +187,7 @@

coreblocks

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/modules-transactron.html b/modules-transactron.html index b12b01ed3..7aad88c22 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -118,7 +118,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/py-modindex.html b/py-modindex.html index d2d0f8b87..69dc1ea20 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -453,7 +453,7 @@

Python Module Index

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 08:22 2023-11-02. + Last updated on 16:15 2023-11-02.

diff --git a/scheduler/Overview.html b/scheduler/Overview.html index dc1ac5429..050be183a 100644 --- a/scheduler/Overview.html +++ b/scheduler/Overview.html @@ -146,7 +146,7 @@

More detailed description of each block

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diff --git a/search.html b/search.html index 2342b23d1..8fa387869 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

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Read and clean row

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