From 58249da625a3b981af7d4bafab97b47b6e73f811 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jakub=20Urba=C5=84czyk?= <xthaid@gmail.com>
Date: Tue, 12 Mar 2024 17:21:11 +0000
Subject: [PATCH] Enable division and bit manipulation extensions in benchmarks
 (#616)

---
 .github/workflows/benchmark.yml                             | 2 +-
 .github/workflows/main.yml                                  | 4 ++--
 test/external/embench/board_config/coreblocks-sim/board.cfg | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/benchmark.yml b/.github/workflows/benchmark.yml
index 45429f68d..1fc7fac1d 100644
--- a/.github/workflows/benchmark.yml
+++ b/.github/workflows/benchmark.yml
@@ -63,7 +63,7 @@ jobs:
   build-perf-benchmarks:
     name: Build performance benchmarks
     runs-on: ubuntu-latest
-    container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.11.19_v
+    container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
     steps:
       - name: Checkout
         uses: actions/checkout@v3
diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 5ee446967..23c1aa56c 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -48,7 +48,7 @@ jobs:
   build-riscof-tests:
     name: Build regression tests (riscv-arch-test)
     runs-on: ubuntu-latest
-    container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.11.19_v
+    container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
     timeout-minutes: 10
     env:
       PYENV_ROOT: "/root/.pyenv"
@@ -180,7 +180,7 @@ jobs:
   build-regression-tests:
     name: Build regression tests (riscv-tests)
     runs-on: ubuntu-latest
-    container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.11.19_v
+    container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
     timeout-minutes: 10
     outputs:
         cache_hit: ${{ steps.cache-regression.outputs.cache-hit }}
diff --git a/test/external/embench/board_config/coreblocks-sim/board.cfg b/test/external/embench/board_config/coreblocks-sim/board.cfg
index 96eaae307..b1a885340 100644
--- a/test/external/embench/board_config/coreblocks-sim/board.cfg
+++ b/test/external/embench/board_config/coreblocks-sim/board.cfg
@@ -1,5 +1,5 @@
 cc = 'riscv64-unknown-elf-gcc'
-cflags = (['-c', '-fdata-sections', '-march=rv32ic_zmmul_zicsr', '-mabi=ilp32'])
-ldflags = (['-Wl,-gc-sections', '-march=rv32ic_zmmul_zicsr', '-mabi=ilp32', '-nostartfiles', '-T../../../common/link.ld'])
+cflags = (['-c', '-fdata-sections', '-march=rv32imc_zba_zbb_zbc_zbs_zicsr', '-mabi=ilp32'])
+ldflags = (['-Wl,-gc-sections', '-march=rv32imc_zba_zbb_zbc_zbs_zicsr', '-mabi=ilp32', '-nostartfiles', '-T../../../common/link.ld'])
 user_libs = (['-lm'])
 cpu_mhz = 0.01