diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index abdcf19bd..48dee204e 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index 39aed0434..fc6d10409 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree index 8863d5cb5..f77df8cc5 100644 Binary files a/.doctrees/current-graph.doctree and b/.doctrees/current-graph.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index 9a4585d01..1c2ebfc54 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 4f4631b4c..a86272271 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -7,9 +7,9 @@ Core_InitFreeRFFifo["InitFreeRFFifo"] Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_request["request"] WishboneMaster_result["result"] + WishboneMaster_WishboneMaster["WishboneMaster"] subgraph Forwarder["result Forwarder"] Forwarder_read["read"] Forwarder_write["write"] @@ -17,8 +17,8 @@ end subgraph WishboneMaster1["wb_master_data WishboneMaster"] WishboneMaster1_result["result"] - WishboneMaster1_WishboneMaster["WishboneMaster"] WishboneMaster1_request["request"] + WishboneMaster1_WishboneMaster["WishboneMaster"] subgraph Forwarder1["result Forwarder"] Forwarder1_write["write"] Forwarder1_read["read"] @@ -38,9 +38,9 @@ end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_get_read_response["get_read_response"] - WishboneMasterAdapter1_request_write["request_write"] - WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_read["request_read"] + WishboneMasterAdapter1_get_write_response["get_write_response"] + WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] @@ -53,8 +53,8 @@ end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph FIFO["fifo_fetch FIFO"] FIFO_write["write"] @@ -67,22 +67,22 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["address_fwd Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end end subgraph ICache["icache ICache"] - ICache_accept_res["accept_res"] ICache_ICache["ICache"] ICache_issue_req["issue_req"] + ICache_accept_res["accept_res"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] ICache_ICache3["ICache"] @@ -113,12 +113,12 @@ end end subgraph FIFO2["req_fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end subgraph FRAT["FRAT FRAT"] @@ -129,17 +129,17 @@ RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] - RegisterFile_read2["read2"] RegisterFile_free["free"] RegisterFile_write["write"] + RegisterFile_read1["read1"] + RegisterFile_read2["read2"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_mark_done["mark_done"] ReorderBuffer_retire["retire"] - ReorderBuffer_peek["peek"] ReorderBuffer_put["put"] ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_peek["peek"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] LatencyMeasurer1__start["_start"] LatencyMeasurer1__stop["_stop"] @@ -153,19 +153,19 @@ end end subgraph Fetch["fetch Fetch"] - Fetch_Fetch["Fetch"] Fetch_stall_exception["stall_exception"] - Fetch_resume["resume"] + Fetch_Fetch["Fetch"] Fetch_Fetch1["Fetch"] + Fetch_resume["resume"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] BasicFifo3_write["write"] BasicFifo3_read["read"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] + ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] ExceptionCauseRegister_clear["clear"] - ExceptionCauseRegister_report["report"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] BasicFifo4_read["read"] BasicFifo4_write["write"] @@ -198,34 +198,34 @@ end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] RSFuncBlock_select["select"] + RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] RSFuncBlock_insert["insert"] - RSFuncBlock_update["update"] subgraph RS["rs RS"] + RS_update["update"] + RS_select["select"] + RS_insert["insert"] RS_RS["RS"] RS_RS1["RS"] - RS_RS2["RS"] RS_take["take"] + RS_RS2["RS"] RS_RS3["RS"] RS_RS4["RS"] - RS_update["update"] - RS_select["select"] - RS_insert["insert"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] subgraph FIFO4["fifo FIFO"] - FIFO4_write["write"] FIFO4_read["read"] + FIFO4_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO5["fifo FIFO"] FIFO5_read["read"] FIFO5_write["write"] @@ -238,8 +238,8 @@ JumpBranchFuncUnit_issue["issue"] JumpBranchFuncUnit_accept["accept"] subgraph FIFO6["fifo_branch_resolved FIFO"] - FIFO6_write["write"] FIFO6_read["read"] + FIFO6_write["write"] end subgraph HwCounter5["perf_jumps HwCounter"] HwCounter5__incr["_incr"] @@ -271,8 +271,8 @@ end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] PrivilegedFuncUnit_issue["issue"] - PrivilegedFuncUnit_precommit["precommit"] PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_precommit["precommit"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] BasicFifo5_write["write"] BasicFifo5_read["read"] @@ -307,41 +307,41 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_update["update"] LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_update["update"] LSUDummy_select["select"] - LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_insert["insert"] LSUDummy_precommit["precommit"] + LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_get_result["get_result"] LSUDummy_LSUDummy2["LSUDummy"] - LSUDummy_insert["insert"] subgraph Forwarder6["forwarder Forwarder"] - Forwarder6_write["write"] Forwarder6_read["read"] + Forwarder6_write["write"] end subgraph LSURequester["requester LSURequester"] + LSURequester_accept["accept"] + LSURequester_issue_cond0["issue_cond0"] LSURequester_accept_cond0["accept_cond0"] - LSURequester_accept_cond1["accept_cond1"] + LSURequester_issue["issue"] LSURequester_issue_cond1["issue_cond1"] LSURequester_issue_cond2["issue_cond2"] - LSURequester_accept["accept"] - LSURequester_issue["issue"] - LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept_cond1["accept_cond1"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_select["select"] - CSRUnit_update["update"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_insert["insert"] + CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_select["select"] CSRUnit_precommit["precommit"] + CSRUnit_update["update"] CSRUnit_get_result["get_result"] - CSRUnit_CSRUnit["CSRUnit"] - CSRUnit_fetch_resume["fetch_resume"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] - MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_method["method"] + MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] end subgraph Collector2["FetchResumeKey_unifier Collector"] @@ -364,28 +364,28 @@ ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"] end subgraph InterruptController["interrupt_controller InterruptController"] + InterruptController_mret["mret"] InterruptController_report_interrupt["report_interrupt"] InterruptController_entry["entry"] - InterruptController_mret["mret"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] + CSRRegister__fu_read["_fu_read"] CSRRegister__fu_write["_fu_write"] CSRRegister_write["write"] - CSRRegister__fu_read["_fu_read"] end subgraph CSRRegister1["mtvec CSRRegister"] CSRRegister1__fu_read["_fu_read"] - CSRRegister1__fu_write["_fu_write"] CSRRegister1_read["read"] + CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2_write["write"] CSRRegister2__fu_read["_fu_read"] - CSRRegister2_read["read"] CSRRegister2__fu_write["_fu_write"] + CSRRegister2_read["read"] + CSRRegister2_write["write"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] @@ -396,28 +396,28 @@ CSRRegister3_write["write"] end subgraph CSRRegister4["register_high CSRRegister"] + CSRRegister4_write["write"] CSRRegister4__fu_read["_fu_read"] CSRRegister4_read["read"] - CSRRegister4_write["write"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_read["read"] CSRRegister5_write["write"] CSRRegister5__fu_read["_fu_read"] + CSRRegister5_read["read"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_write["write"] CSRRegister6_read["read"] + CSRRegister6_write["write"] CSRRegister6__fu_read["_fu_read"] end end end subgraph FIFO9["fifo_decode FIFO"] - FIFO9_read["read"] FIFO9_write["write"] + FIFO9_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -441,8 +441,8 @@ Renaming_Renaming["Renaming"] end subgraph FIFO12["reg_alloc_out_buf FIFO"] - FIFO12_write["write"] FIFO12_read["read"] + FIFO12_write["write"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -457,8 +457,8 @@ RSSelection_RSSelection2["RSSelection"] RSSelection_RSSelection3["RSSelection"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_write["write"] Forwarder8_read["read"] + Forwarder8_write["write"] end end subgraph RSInsertion["rs_insertion RSInsertion"] @@ -469,9 +469,9 @@ ConnectTrans11_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement1["Retirement"] Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement2["Retirement"] @@ -480,14 +480,14 @@ subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] - CSRRegister7_read["read"] CSRRegister7_write["write"] + CSRRegister7_read["read"] CSRRegister7__fu_read["_fu_read"] end subgraph CSRRegister8["register_high CSRRegister"] - CSRRegister8_write["write"] CSRRegister8__fu_read["_fu_read"] CSRRegister8_read["read"] + CSRRegister8_write["write"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -507,25 +507,25 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] + TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] end end Core_InitFreeRFFifo --> BasicFifo2_write - Retirement_Retirement3 --> BasicFifo2_write - TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write - TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write + Retirement_Retirement --> BasicFifo2_write + TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write + TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write Forwarder2_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request ICache_ICache1 <--> HwCounter4__incr @@ -538,7 +538,7 @@ ICache_ICache2 --> Forwarder2_write SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache2 WishboneMasterAdapter_get_read_response --> ICache_ICache2 - Serializer_Serializer --> ICache_ICache2 + Serializer_Serializer1 --> ICache_ICache2 BasicFifo_read --> ICache_ICache2 WishboneMaster_result --> ICache_ICache2 Forwarder_read --> ICache_ICache2 @@ -571,26 +571,26 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename - Retirement_Retirement3 --> FRAT_rename - TransactionManager_Retirement_cond1_Retirement --> FRAT_rename + Retirement_Retirement --> FRAT_rename + TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write - FIFO12_read --> RSSelection_RSSelection3 - RSSelection_RSSelection3 --> Forwarder8_write + FIFO12_read --> RSSelection_RSSelection + RSSelection_RSSelection --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection1 + Forwarder8_read --> RSSelection_RSSelection3 Forwarder8_read --> RSSelection_RSSelection2 - Forwarder8_read --> RSSelection_RSSelection RSFuncBlock_select --> RSSelection_RSSelection1 RS_select --> RSSelection_RSSelection1 RSSelection_RSSelection1 --> FIFO13_write + RSSelection_RSSelection3 --> FIFO13_write RSSelection_RSSelection2 --> FIFO13_write - RSSelection_RSSelection --> FIFO13_write - RSSelection_RSSelection2 <--> LSUDummy_select - RSSelection_RSSelection <--> CSRUnit_select + RSSelection_RSSelection3 <--> LSUDummy_select + RSSelection_RSSelection2 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -606,7 +606,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume - Retirement_Retirement --> Fetch_resume + Retirement_Retirement2 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -616,7 +616,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update - RS_RS1 --> WakeupSelect_WakeupSelect + RS_RS --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -639,10 +639,10 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write - RS_RS --> WakeupSelect3_WakeupSelect + RS_RS2 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write - RS_RS2 --> WakeupSelect4_WakeupSelect + RS_RS1 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -660,12 +660,12 @@ PrivilegedFuncUnit_accept --> ConnectTrans8_ConnectTrans CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write - LSUDummy_LSUDummy1 --> Forwarder6_write - TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write + LSUDummy_LSUDummy2 --> Forwarder6_write + TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write + TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write + TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write - TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write - TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -687,45 +687,45 @@ LSUDummy_get_result --> ConnectTrans2_ConnectTrans Forwarder6_read --> ConnectTrans2_ConnectTrans CSRUnit_get_result --> ConnectTrans3_ConnectTrans - MethodTryProduct_MethodTryProduct2 --> PrivilegedFuncUnit_precommit - MethodTryProduct_MethodTryProduct2 <--> InterruptController_mret + MethodTryProduct_MethodTryProduct --> PrivilegedFuncUnit_precommit + MethodTryProduct_MethodTryProduct <--> InterruptController_mret MethodTryProduct_MethodTryProduct1 --> LSUDummy_precommit - MethodTryProduct_MethodTryProduct --> CSRUnit_precommit + MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans - ReorderBuffer_peek --> Retirement_Retirement1 - ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> Retirement_Retirement3 - ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement - ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement1 --> MethodTryProduct_method + ReorderBuffer_peek --> Retirement_Retirement4 + ReorderBuffer_peek --> Retirement_Retirement + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement3 --> MethodTryProduct_method ExceptionCauseRegister_get --> Retirement_Retirement4 - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement3 <--> ReorderBuffer_retire - TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire - TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire - Retirement_Retirement3 <--> LatencyMeasurer1__stop - TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop - TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop - FIFO3_read --> Retirement_Retirement3 - FIFO3_read --> TransactionManager_Retirement_cond0_Retirement - FIFO3_read --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement3 --> HwExpHistogram1__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add - TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add - CoreInstructionCounter_decrement --> Retirement_Retirement3 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement - RRAT_peek --> Retirement_Retirement3 - RRAT_peek --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement3 --> RegisterFile_free - TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free - TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free - CSRRegister1_read --> Retirement_Retirement - Retirement_Retirement <--> ExceptionCauseRegister_clear + ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 + ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement <--> ReorderBuffer_retire + TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire + TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire + Retirement_Retirement <--> LatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop + FIFO3_read --> Retirement_Retirement + FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 + FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add + CoreInstructionCounter_decrement --> Retirement_Retirement + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 + RRAT_peek --> Retirement_Retirement + RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement --> RegisterFile_free + TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free + TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free + CSRRegister1_read --> Retirement_Retirement2 + Retirement_Retirement2 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -737,53 +737,53 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt - TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy - TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy - TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy - TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 - TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer - TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1 + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement1 + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write + TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 + TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 + TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write + TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer2 + TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request + TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request - TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 - TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read - TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer2 - TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2 - TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy2 - LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue + TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 + TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy + TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 - TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 - Serializer1_Serializer1 --> TransactionManager_LSUDummy_accept_cond0 - BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 + LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 + Serializer1_Serializer1 --> TransactionManager_LSUDummy_accept_cond1 BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 - WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 + BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 - Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 + WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_cond0_Retirement --> RRAT_commit - TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment - CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write - CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write - TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement2 - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement2 - TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write - TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry - TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 - TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 - TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 - Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond1 + Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit + TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment + CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write + CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr + TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 + TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read + TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer3 + TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 + Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond0 diff --git a/api.html b/api.html index 10993f89e..37811ec2c 100644 --- a/api.html +++ b/api.html @@ -282,7 +282,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 13:48 2024-03-07. + Last updated on 15:13 2024-03-10.

diff --git a/assumptions.html b/assumptions.html index 1bca2f9bc..d2aea9c1d 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 13:48 2024-03-07. + Last updated on 15:13 2024-03-10.

diff --git a/auto_graph.html b/auto_graph.html index 996ea039f..c95277fd7 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -86,9 +86,9 @@ Core_InitFreeRFFifo["InitFreeRFFifo"] Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_request["request"] WishboneMaster_result["result"] + WishboneMaster_WishboneMaster["WishboneMaster"] subgraph Forwarder["result Forwarder"] Forwarder_read["read"] Forwarder_write["write"] @@ -96,8 +96,8 @@ end subgraph WishboneMaster1["wb_master_data WishboneMaster"] WishboneMaster1_result["result"] - WishboneMaster1_WishboneMaster["WishboneMaster"] WishboneMaster1_request["request"] + WishboneMaster1_WishboneMaster["WishboneMaster"] subgraph Forwarder1["result Forwarder"] Forwarder1_write["write"] Forwarder1_read["read"] @@ -117,9 +117,9 @@ end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_get_read_response["get_read_response"] - WishboneMasterAdapter1_request_write["request_write"] - WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_read["request_read"] + WishboneMasterAdapter1_get_write_response["get_write_response"] + WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] @@ -132,8 +132,8 @@ end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph FIFO["fifo_fetch FIFO"] FIFO_write["write"] @@ -146,22 +146,22 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["address_fwd Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end end subgraph ICache["icache ICache"] - ICache_accept_res["accept_res"] ICache_ICache["ICache"] ICache_issue_req["issue_req"] + ICache_accept_res["accept_res"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] ICache_ICache3["ICache"] @@ -192,12 +192,12 @@ end end subgraph FIFO2["req_fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end subgraph FRAT["FRAT FRAT"] @@ -208,17 +208,17 @@ RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] - RegisterFile_read2["read2"] RegisterFile_free["free"] RegisterFile_write["write"] + RegisterFile_read1["read1"] + RegisterFile_read2["read2"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_mark_done["mark_done"] ReorderBuffer_retire["retire"] - ReorderBuffer_peek["peek"] ReorderBuffer_put["put"] ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_peek["peek"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] LatencyMeasurer1__start["_start"] LatencyMeasurer1__stop["_stop"] @@ -232,19 +232,19 @@ end end subgraph Fetch["fetch Fetch"] - Fetch_Fetch["Fetch"] Fetch_stall_exception["stall_exception"] - Fetch_resume["resume"] + Fetch_Fetch["Fetch"] Fetch_Fetch1["Fetch"] + Fetch_resume["resume"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] BasicFifo3_write["write"] BasicFifo3_read["read"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] + ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] ExceptionCauseRegister_clear["clear"] - ExceptionCauseRegister_report["report"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] BasicFifo4_read["read"] BasicFifo4_write["write"] @@ -277,34 +277,34 @@ end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] RSFuncBlock_select["select"] + RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] RSFuncBlock_insert["insert"] - RSFuncBlock_update["update"] subgraph RS["rs RS"] + RS_update["update"] + RS_select["select"] + RS_insert["insert"] RS_RS["RS"] RS_RS1["RS"] - RS_RS2["RS"] RS_take["take"] + RS_RS2["RS"] RS_RS3["RS"] RS_RS4["RS"] - RS_update["update"] - RS_select["select"] - RS_insert["insert"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] subgraph FIFO4["fifo FIFO"] - FIFO4_write["write"] FIFO4_read["read"] + FIFO4_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO5["fifo FIFO"] FIFO5_read["read"] FIFO5_write["write"] @@ -317,8 +317,8 @@ JumpBranchFuncUnit_issue["issue"] JumpBranchFuncUnit_accept["accept"] subgraph FIFO6["fifo_branch_resolved FIFO"] - FIFO6_write["write"] FIFO6_read["read"] + FIFO6_write["write"] end subgraph HwCounter5["perf_jumps HwCounter"] HwCounter5__incr["_incr"] @@ -350,8 +350,8 @@ end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] PrivilegedFuncUnit_issue["issue"] - PrivilegedFuncUnit_precommit["precommit"] PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_precommit["precommit"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] BasicFifo5_write["write"] BasicFifo5_read["read"] @@ -386,41 +386,41 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_update["update"] LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_update["update"] LSUDummy_select["select"] - LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_insert["insert"] LSUDummy_precommit["precommit"] + LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_get_result["get_result"] LSUDummy_LSUDummy2["LSUDummy"] - LSUDummy_insert["insert"] subgraph Forwarder6["forwarder Forwarder"] - Forwarder6_write["write"] Forwarder6_read["read"] + Forwarder6_write["write"] end subgraph LSURequester["requester LSURequester"] + LSURequester_accept["accept"] + LSURequester_issue_cond0["issue_cond0"] LSURequester_accept_cond0["accept_cond0"] - LSURequester_accept_cond1["accept_cond1"] + LSURequester_issue["issue"] LSURequester_issue_cond1["issue_cond1"] LSURequester_issue_cond2["issue_cond2"] - LSURequester_accept["accept"] - LSURequester_issue["issue"] - LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept_cond1["accept_cond1"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_select["select"] - CSRUnit_update["update"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_insert["insert"] + CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_select["select"] CSRUnit_precommit["precommit"] + CSRUnit_update["update"] CSRUnit_get_result["get_result"] - CSRUnit_CSRUnit["CSRUnit"] - CSRUnit_fetch_resume["fetch_resume"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] - MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_method["method"] + MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] end subgraph Collector2["FetchResumeKey_unifier Collector"] @@ -443,28 +443,28 @@ ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"] end subgraph InterruptController["interrupt_controller InterruptController"] + InterruptController_mret["mret"] InterruptController_report_interrupt["report_interrupt"] InterruptController_entry["entry"] - InterruptController_mret["mret"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] + CSRRegister__fu_read["_fu_read"] CSRRegister__fu_write["_fu_write"] CSRRegister_write["write"] - CSRRegister__fu_read["_fu_read"] end subgraph CSRRegister1["mtvec CSRRegister"] CSRRegister1__fu_read["_fu_read"] - CSRRegister1__fu_write["_fu_write"] CSRRegister1_read["read"] + CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2_write["write"] CSRRegister2__fu_read["_fu_read"] - CSRRegister2_read["read"] CSRRegister2__fu_write["_fu_write"] + CSRRegister2_read["read"] + CSRRegister2_write["write"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] @@ -475,28 +475,28 @@ CSRRegister3_write["write"] end subgraph CSRRegister4["register_high CSRRegister"] + CSRRegister4_write["write"] CSRRegister4__fu_read["_fu_read"] CSRRegister4_read["read"] - CSRRegister4_write["write"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_read["read"] CSRRegister5_write["write"] CSRRegister5__fu_read["_fu_read"] + CSRRegister5_read["read"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_write["write"] CSRRegister6_read["read"] + CSRRegister6_write["write"] CSRRegister6__fu_read["_fu_read"] end end end subgraph FIFO9["fifo_decode FIFO"] - FIFO9_read["read"] FIFO9_write["write"] + FIFO9_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -520,8 +520,8 @@ Renaming_Renaming["Renaming"] end subgraph FIFO12["reg_alloc_out_buf FIFO"] - FIFO12_write["write"] FIFO12_read["read"] + FIFO12_write["write"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -536,8 +536,8 @@ RSSelection_RSSelection2["RSSelection"] RSSelection_RSSelection3["RSSelection"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_write["write"] Forwarder8_read["read"] + Forwarder8_write["write"] end end subgraph RSInsertion["rs_insertion RSInsertion"] @@ -548,9 +548,9 @@ ConnectTrans11_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement1["Retirement"] Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement2["Retirement"] @@ -559,14 +559,14 @@ subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] - CSRRegister7_read["read"] CSRRegister7_write["write"] + CSRRegister7_read["read"] CSRRegister7__fu_read["_fu_read"] end subgraph CSRRegister8["register_high CSRRegister"] - CSRRegister8_write["write"] CSRRegister8__fu_read["_fu_read"] CSRRegister8_read["read"] + CSRRegister8_write["write"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -586,25 +586,25 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] + TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] end end Core_InitFreeRFFifo --> BasicFifo2_write -Retirement_Retirement3 --> BasicFifo2_write -TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write -TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write +Retirement_Retirement --> BasicFifo2_write +TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write +TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write Forwarder2_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request ICache_ICache1 <--> HwCounter4__incr @@ -617,7 +617,7 @@ ICache_ICache2 --> Forwarder2_write SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache2 WishboneMasterAdapter_get_read_response --> ICache_ICache2 -Serializer_Serializer --> ICache_ICache2 +Serializer_Serializer1 --> ICache_ICache2 BasicFifo_read --> ICache_ICache2 WishboneMaster_result --> ICache_ICache2 Forwarder_read --> ICache_ICache2 @@ -650,26 +650,26 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename -Retirement_Retirement3 --> FRAT_rename -TransactionManager_Retirement_cond1_Retirement --> FRAT_rename +Retirement_Retirement --> FRAT_rename +TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write -FIFO12_read --> RSSelection_RSSelection3 -RSSelection_RSSelection3 --> Forwarder8_write +FIFO12_read --> RSSelection_RSSelection +RSSelection_RSSelection --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection1 +Forwarder8_read --> RSSelection_RSSelection3 Forwarder8_read --> RSSelection_RSSelection2 -Forwarder8_read --> RSSelection_RSSelection RSFuncBlock_select --> RSSelection_RSSelection1 RS_select --> RSSelection_RSSelection1 RSSelection_RSSelection1 --> FIFO13_write +RSSelection_RSSelection3 --> FIFO13_write RSSelection_RSSelection2 --> FIFO13_write -RSSelection_RSSelection --> FIFO13_write -RSSelection_RSSelection2 <--> LSUDummy_select -RSSelection_RSSelection <--> CSRUnit_select +RSSelection_RSSelection3 <--> LSUDummy_select +RSSelection_RSSelection2 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -685,7 +685,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume -Retirement_Retirement --> Fetch_resume +Retirement_Retirement2 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -695,7 +695,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update -RS_RS1 --> WakeupSelect_WakeupSelect +RS_RS --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -718,10 +718,10 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write -RS_RS --> WakeupSelect3_WakeupSelect +RS_RS2 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write -RS_RS2 --> WakeupSelect4_WakeupSelect +RS_RS1 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -739,12 +739,12 @@ PrivilegedFuncUnit_accept --> ConnectTrans8_ConnectTrans CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write -LSUDummy_LSUDummy1 --> Forwarder6_write -TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write +LSUDummy_LSUDummy2 --> Forwarder6_write +TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write +TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write +TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write -TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write -TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -766,45 +766,45 @@ LSUDummy_get_result --> ConnectTrans2_ConnectTrans Forwarder6_read --> ConnectTrans2_ConnectTrans CSRUnit_get_result --> ConnectTrans3_ConnectTrans -MethodTryProduct_MethodTryProduct2 --> PrivilegedFuncUnit_precommit -MethodTryProduct_MethodTryProduct2 <--> InterruptController_mret +MethodTryProduct_MethodTryProduct --> PrivilegedFuncUnit_precommit +MethodTryProduct_MethodTryProduct <--> InterruptController_mret MethodTryProduct_MethodTryProduct1 --> LSUDummy_precommit -MethodTryProduct_MethodTryProduct --> CSRUnit_precommit +MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans -ReorderBuffer_peek --> Retirement_Retirement1 -ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> Retirement_Retirement3 -ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement -ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement1 --> MethodTryProduct_method +ReorderBuffer_peek --> Retirement_Retirement4 +ReorderBuffer_peek --> Retirement_Retirement +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement3 --> MethodTryProduct_method ExceptionCauseRegister_get --> Retirement_Retirement4 -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement3 <--> ReorderBuffer_retire -TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire -TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire -Retirement_Retirement3 <--> LatencyMeasurer1__stop -TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop -TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop -FIFO3_read --> Retirement_Retirement3 -FIFO3_read --> TransactionManager_Retirement_cond0_Retirement -FIFO3_read --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement3 --> HwExpHistogram1__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add -TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add -CoreInstructionCounter_decrement --> Retirement_Retirement3 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement -RRAT_peek --> Retirement_Retirement3 -RRAT_peek --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement3 --> RegisterFile_free -TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free -TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free -CSRRegister1_read --> Retirement_Retirement -Retirement_Retirement <--> ExceptionCauseRegister_clear +ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 +ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement <--> ReorderBuffer_retire +TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire +TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire +Retirement_Retirement <--> LatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop +FIFO3_read --> Retirement_Retirement +FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 +FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement --> HwExpHistogram1__add +TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add +CoreInstructionCounter_decrement --> Retirement_Retirement +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 +RRAT_peek --> Retirement_Retirement +RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement --> RegisterFile_free +TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free +TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free +CSRRegister1_read --> Retirement_Retirement2 +Retirement_Retirement2 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -816,56 +816,56 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt -TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy -TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy -TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy -TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 -TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write -TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer -TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1 +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement1 +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write +TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 +TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 +TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write +TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer2 +TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write -TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request +TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request -TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 -TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read -TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer2 -TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2 -TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy2 -LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 +TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue +TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 +TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy +TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 -TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 -Serializer1_Serializer1 --> TransactionManager_LSUDummy_accept_cond0 -BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 +LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 +TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 +Serializer1_Serializer1 --> TransactionManager_LSUDummy_accept_cond1 BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 -WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 +BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 -Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 +WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_cond0_Retirement --> RRAT_commit -TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment -CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write -CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write -TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement2 -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement2 -TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write -TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry -TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 -TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 -TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 -Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond1 +Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit +TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment +CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write +CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr +TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 +TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read +TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer3 +TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 +Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond0 @@ -876,7 +876,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 13:48 2024-03-07. + Last updated on 15:13 2024-03-10.

diff --git a/components/icache.html b/components/icache.html index ba1b44968..01bdb89f2 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

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diff --git a/coreblocks.cache.html b/coreblocks.cache.html index c28af2fd5..d8a2fece2 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -241,7 +241,7 @@

Submodules

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diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index d9d35fafe..13504b0bf 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -368,7 +368,7 @@

Submodules

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diff --git a/coreblocks.fu.html b/coreblocks.fu.html index e1c37246c..ba47cb1a4 100644 --- a/coreblocks.fu.html +++ b/coreblocks.fu.html @@ -965,7 +965,7 @@

Submodules

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diff --git a/coreblocks.fu.unsigned_multiplication.html b/coreblocks.fu.unsigned_multiplication.html index 84c65f991..696c325d9 100644 --- a/coreblocks.fu.unsigned_multiplication.html +++ b/coreblocks.fu.unsigned_multiplication.html @@ -237,7 +237,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 13:48 2024-03-07. + Last updated on 15:13 2024-03-10.

diff --git a/coreblocks.html b/coreblocks.html index 82f666837..77abe9eba 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -234,7 +234,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 13:48 2024-03-07. + Last updated on 15:13 2024-03-10.

diff --git a/coreblocks.lsu.html b/coreblocks.lsu.html index aac6e7841..987857803 100644 --- a/coreblocks.lsu.html +++ b/coreblocks.lsu.html @@ -236,7 +236,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 13:48 2024-03-07. + Last updated on 15:13 2024-03-10.

diff --git a/coreblocks.params.html b/coreblocks.params.html index 67edfd99c..a7582238f 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -2701,7 +2701,7 @@

Submodules

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diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index 5be2b8e02..b02492bc0 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -598,7 +598,7 @@

Submodules

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diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 65c4477c8..32fff2eeb 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

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diff --git a/coreblocks.stages.html b/coreblocks.stages.html index 396675aa8..1eeaa99a9 100644 --- a/coreblocks.stages.html +++ b/coreblocks.stages.html @@ -263,7 +263,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 13:48 2024-03-07. + Last updated on 15:13 2024-03-10.

diff --git a/coreblocks.structs_common.html b/coreblocks.structs_common.html index 52cbbeaf3..b051c54fd 100644 --- a/coreblocks.structs_common.html +++ b/coreblocks.structs_common.html @@ -522,7 +522,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 13:48 2024-03-07. + Last updated on 15:13 2024-03-10.

diff --git a/coreblocks.utils.html b/coreblocks.utils.html index 8bf4cae9c..dd31e9714 100644 --- a/coreblocks.utils.html +++ b/coreblocks.utils.html @@ -149,7 +149,7 @@

Submodules

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diff --git a/current-graph.html b/current-graph.html index 249757a27..6cfd95589 100644 --- a/current-graph.html +++ b/current-graph.html @@ -92,9 +92,9 @@

Full transaction-method graph

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diff --git a/development-environment.html b/development-environment.html index 11369308e..ecd856c23 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

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diff --git a/genindex.html b/genindex.html index 3f292af72..c365721ea 100644 --- a/genindex.html +++ b/genindex.html @@ -3863,7 +3863,7 @@

Z

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diff --git a/home.html b/home.html index 9d31991a0..20e2049c2 100644 --- a/home.html +++ b/home.html @@ -129,7 +129,7 @@

Documentation

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diff --git a/index.html b/index.html index 79268e3a7..d0b4a8152 100644 --- a/index.html +++ b/index.html @@ -229,7 +229,7 @@

Coreblocks

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diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html index 6d802b6e2..82cbd497a 100644 --- a/miscellany/exceptions-summary.html +++ b/miscellany/exceptions-summary.html @@ -271,7 +271,7 @@

Summary

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diff --git a/modules-coreblocks.html b/modules-coreblocks.html index 1503f8416..01cfd3fb4 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -203,7 +203,7 @@

coreblocks

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diff --git a/modules-transactron.html b/modules-transactron.html index e14220929..d44d4d391 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -149,7 +149,7 @@

transactron

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diff --git a/problem-checklist.html b/problem-checklist.html index 2fd8d10b3..8f5d4186f 100644 --- a/problem-checklist.html +++ b/problem-checklist.html @@ -105,7 +105,7 @@

Problem checklist

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diff --git a/py-modindex.html b/py-modindex.html index 5fc2e9def..b9b8784a3 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -618,7 +618,7 @@

Python Module Index

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diff --git a/scheduler/overview.html b/scheduler/overview.html index 0403489f3..01492c234 100644 --- a/scheduler/overview.html +++ b/scheduler/overview.html @@ -146,7 +146,7 @@

More detailed description of each block

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diff --git a/search.html b/search.html index 051987151..e8905984b 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 13:48 2024-03-07. + Last updated on 15:13 2024-03-10.

diff --git a/shared-structs/implementation/rs-impl.html b/shared-structs/implementation/rs-impl.html index 516bc0b53..ef07495e7 100644 --- a/shared-structs/implementation/rs-impl.html +++ b/shared-structs/implementation/rs-impl.html @@ -252,7 +252,7 @@

Read and clean row

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diff --git a/shared-structs/rs.html b/shared-structs/rs.html index 5ceaac6ea..c72e05810 100644 --- a/shared-structs/rs.html +++ b/shared-structs/rs.html @@ -222,7 +222,7 @@

External interface signals

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diff --git a/synthesis/synthesis.html b/synthesis/synthesis.html index d0c300085..0e3ed3c77 100644 --- a/synthesis/synthesis.html +++ b/synthesis/synthesis.html @@ -266,7 +266,7 @@

Regression tests manual execution

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diff --git a/transactions.html b/transactions.html index 4f17d1457..bf95a14a5 100644 --- a/transactions.html +++ b/transactions.html @@ -409,7 +409,7 @@

Transaction and method nesting

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diff --git a/transactron.html b/transactron.html index 27cb04884..4d742e917 100644 --- a/transactron.html +++ b/transactron.html @@ -1791,7 +1791,7 @@

Submodules

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diff --git a/transactron.lib.html b/transactron.lib.html index 34b24ce89..d7a34e7ea 100644 --- a/transactron.lib.html +++ b/transactron.lib.html @@ -1643,7 +1643,7 @@

Submodules

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diff --git a/transactron.testing.html b/transactron.testing.html index 0c1b9176f..c92de9a79 100644 --- a/transactron.testing.html +++ b/transactron.testing.html @@ -399,7 +399,7 @@

Submodules

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diff --git a/transactron.utils.amaranth_ext.html b/transactron.utils.amaranth_ext.html index 7fe9202dc..d3fd23d9e 100644 --- a/transactron.utils.amaranth_ext.html +++ b/transactron.utils.amaranth_ext.html @@ -293,7 +293,7 @@

Submodules

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diff --git a/transactron.utils.html b/transactron.utils.html index 24d0093bd..772d9a96b 100644 --- a/transactron.utils.html +++ b/transactron.utils.html @@ -850,7 +850,7 @@

Submodules

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