From 4284037936b8137be9a201cbaea9a44512231edb Mon Sep 17 00:00:00 2001 From: tilk Date: Mon, 23 Oct 2023 18:36:27 +0000 Subject: [PATCH] Fix memory protection in regression tests (#481) --- .doctrees/Current_graph.doctree | Bin 24025 -> 24014 bytes .doctrees/api.doctree | Bin 31312 -> 31312 bytes .doctrees/auto_graph.doctree | Bin 23258 -> 23247 bytes .doctrees/environment.pickle | Bin 312944 -> 312944 bytes Assumptions.html | 2 +- Current_graph.html | 114 ++++++++++----------- Development_environment.html | 2 +- Home.html | 2 +- Problem-checklist.html | 2 +- Transactions.html | 2 +- _sources/auto_graph.rst.txt | 112 ++++++++++---------- api.html | 2 +- auto_graph.html | 114 ++++++++++----------- components/icache.html | 2 +- coreblocks.frontend.html | 2 +- coreblocks.fu.html | 2 +- coreblocks.fu.unsigned_multiplication.html | 2 +- coreblocks.html | 2 +- coreblocks.params.html | 2 +- coreblocks.peripherals.html | 2 +- coreblocks.scheduler.html | 2 +- coreblocks.stages.html | 2 +- coreblocks.structs_common.html | 2 +- coreblocks.utils.html | 2 +- genindex.html | 2 +- index.html | 2 +- miscellany/exceptionsSummary.html | 2 +- modules-coreblocks.html | 2 +- modules-transactron.html | 2 +- py-modindex.html | 2 +- scheduler/Overview.html | 2 +- search.html | 2 +- shared_structs/Implementation/RS_impl.html | 2 +- shared_structs/RS.html | 2 +- synthesis/Synthesis.html | 2 +- transactron.html | 2 +- transactron.lib.html | 2 +- 37 files changed, 200 insertions(+), 200 deletions(-) diff --git a/.doctrees/Current_graph.doctree b/.doctrees/Current_graph.doctree index 6feb5f08fa97292919f555e12c6afc64853174c1..ef3362a48e338b6c603cd81d1cbc3d10a454e434 100644 GIT binary patch delta 763 zcmYL_Ur19?9LG8L|7>?#v_H*t*EZeV#5=dUnX8$avv6ZMw|odRQ>3hiqTUK37*WuZ zWZ&wcFe0Jop`s4Hq#@W#RH)!X6qxBlL@)YKFO|`DC3`rW!{_rm=XZYJ50hkel5i#d z=BsC%$dEiWGd%=g{V4f(bhA;!VhT*G1xsue{oFq;V<0a<<2;7H!|C|WDcC1*IP2o@ zmh&0Bflp(M-{8Z1ox$GoGguKKM(sPniQBC*9tZ)$X<`DSq6U`~flU(eQtZWmSdWrh zMp4r7RPt~3C`m!gOGCIMh4I8MK{o~PIjPeL(>Q~x=8HyQ&a4>^2jm0r76i0eJO-bZ ztvD%98*apFLdkLpPqG5S)(yW{W}hs^hv}eIAsDK!$78<<7i=M{xq@`vcACXQdmWD2 zTQF~L#Dqh`6-NwJ&Nu{ziX)CXESHz&h-0tw2CCf={BoKx?=;4t?XD&cs~H||Ji}P? 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z_Jl>B;Xgo-58`kZ!mxulxP`FoAU@kHgjWagRb(Md{D7`R^5g@01WEo88V27VLf0;&_D4LW1pQB6)CxCLOhYJKIf{qTET%L91{~vMY|{voV>k_IaQhf~BaO{_D~LT#TVZ+jaXcc^;LvgG zE)AX>r|HIjg4DZSy``nP6-dPYLRu++)ePYO66tLLtkHln0j$%2^#a(a0p$YNtO4%| zV5s>F8^}9nub_$V72JnBtv_}B@G+@5~K41X<$4rL=aD)LYc6CPua6$u43gDCm zoEE?tBzdCES%G|_iF_)63mR}y0GBo3GXY%DfU5$yt^qd$aFYT2SJAfwa90Dq>5cyc z3LWql4f$4xe9r*>|D=8pzyl3(kd^}QX8>ES zx>f>cs{sK52-biQ0kqeE4g%<`0bK;podNuxVD%6{?=bdHxHu9fkVs9Wj{y2>K$HMt zG+>|r;xu5e01`AHQ2@g=V1xihYe3!@fsEIX2?9vbfQbT_q5)F{FkJ(50!Y(L-G!QLLyHgT5c&TBg~uc_ diff --git a/Assumptions.html b/Assumptions.html index 316915519..bd65768b5 100644 --- a/Assumptions.html +++ b/Assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

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diff --git a/Current_graph.html b/Current_graph.html index 6cef0203b..d89070d04 100644 --- a/Current_graph.html +++ b/Current_graph.html @@ -89,39 +89,39 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 18:20 2023-10-23. + Last updated on 18:36 2023-10-23.

diff --git a/Development_environment.html b/Development_environment.html index d7c699716..0175f6752 100644 --- a/Development_environment.html +++ b/Development_environment.html @@ -178,7 +178,7 @@

build_docs.sh

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 18:20 2023-10-23. + Last updated on 18:36 2023-10-23.

diff --git a/Home.html b/Home.html index be47ecf8b..921e5b166 100644 --- a/Home.html +++ b/Home.html @@ -129,7 +129,7 @@

Documentation

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 18:20 2023-10-23. + Last updated on 18:36 2023-10-23.

diff --git a/Problem-checklist.html b/Problem-checklist.html index 57539c3af..e08016059 100644 --- a/Problem-checklist.html +++ b/Problem-checklist.html @@ -105,7 +105,7 @@

Problem checklist

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diff --git a/Transactions.html b/Transactions.html index 8be34374d..fa35f9306 100644 --- a/Transactions.html +++ b/Transactions.html @@ -267,7 +267,7 @@

Transaction and method nesting

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 18:20 2023-10-23. + Last updated on 18:36 2023-10-23.

diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 552d900d9..21360eb95 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -6,39 +6,39 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_result["result"] WishboneMaster_request["request"] + WishboneMaster_result["result"] end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_result["result"] WishboneMaster1_request["request"] + WishboneMaster1_result["result"] end subgraph FIFO["fifo_fetch FIFO"] - FIFO_write["write"] FIFO_read["read"] + FIFO_write["write"] end subgraph BasicFifo["free_rf_fifo BasicFifo"] - BasicFifo_write["write"] BasicFifo_read["read"] + BasicFifo_write["write"] end subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"] SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] - SimpleWBCacheRefiller_accept_refill["accept_refill"] SimpleWBCacheRefiller_start_refill["start_refill"] + SimpleWBCacheRefiller_accept_refill["accept_refill"] end subgraph ICache["icache ICache"] - ICache_issue_req["issue_req"] ICache_ICache["ICache"] + ICache_accept_res["accept_res"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] - ICache_accept_res["accept_res"] + ICache_issue_req["issue_req"] subgraph FIFO1["req_fifo FIFO"] - FIFO1_write["write"] FIFO1_read["read"] + FIFO1_write["write"] end subgraph Forwarder["res_fwd Forwarder"] - Forwarder_read["read"] Forwarder_write["write"] + Forwarder_read["read"] end end subgraph Fetch["fetch Fetch"] @@ -57,28 +57,28 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] RegisterFile_write["write"] RegisterFile_free["free"] RegisterFile_read2["read2"] + RegisterFile_read1["read1"] end subgraph ReorderBuffer["ROB ReorderBuffer"] + ReorderBuffer_retire["retire"] ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_peek["peek"] ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_retire["retire"] end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_get["get"] ExceptionCauseRegister_report["report"] + ExceptionCauseRegister_get["get"] end subgraph FuncBlocksUnifier["func_blocks_unifier FuncBlocksUnifier"] subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder1["forwarder Forwarder"] - Forwarder1_read["read"] Forwarder1_write["write"] + Forwarder1_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -95,21 +95,21 @@ subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] RSFuncBlock_insert["insert"] RSFuncBlock_update["update"] - RSFuncBlock_get_result["get_result"] RSFuncBlock_select["select"] + RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] + RS_take["take"] + RS_insert["insert"] + RS_select["select"] RS_RS["RS"] - RS_update["update"] RS_RS1["RS"] - RS_insert["insert"] - RS_take["take"] RS_RS2["RS"] - RS_select["select"] + RS_update["update"] RS_RS3["RS"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph FIFO2["fifo FIFO"] FIFO2_read["read"] FIFO2_write["write"] @@ -130,24 +130,24 @@ WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_branch_result["branch_result"] JumpBranchFuncUnit_issue["issue"] JumpBranchFuncUnit_accept["accept"] + JumpBranchFuncUnit_branch_result["branch_result"] subgraph FIFO4["fifo_res FIFO"] FIFO4_read["read"] FIFO4_write["write"] end subgraph FIFO5["fifo_branch FIFO"] - FIFO5_write["write"] FIFO5_read["read"] + FIFO5_write["write"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] + ExceptionFuncUnit_accept["accept"] subgraph FIFO6["fifo FIFO"] FIFO6_read["read"] FIFO6_write["write"] @@ -179,11 +179,11 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_get_result["get_result"] LSUDummy_select["select"] - LSUDummy_precommit["precommit"] LSUDummy_update["update"] LSUDummy_insert["insert"] + LSUDummy_get_result["get_result"] + LSUDummy_precommit["precommit"] subgraph LSUDummyInternals["internal LSUDummyInternals"] LSUDummyInternals_LSUDummyInternals["LSUDummyInternals"] LSUDummyInternals_LSUDummyInternals1["LSUDummyInternals"] @@ -214,8 +214,8 @@ CSRRegister2_write["write"] end subgraph CSRRegister3["register_high CSRRegister"] - CSRRegister3_write["write"] CSRRegister3_read["read"] + CSRRegister3_write["write"] end end subgraph CSRRegister4["mcause CSRRegister"] @@ -231,8 +231,8 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO8["alloc_rename_buf FIFO"] - FIFO8_read["read"] FIFO8_write["write"] + FIFO8_read["read"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -245,8 +245,8 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -260,8 +260,8 @@ RSSelection_RSSelection1["RSSelection"] RSSelection_RSSelection2["RSSelection"] subgraph Forwarder3["forwarder Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end subgraph RSInsertion["rs_insertion RSInsertion"] @@ -277,8 +277,8 @@ subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_read["read"] CSRRegister5_write["write"] + CSRRegister5_read["read"] end subgraph CSRRegister6["register_high CSRRegister"] CSRRegister6_read["read"] @@ -300,7 +300,7 @@ end end Core_InitFreeRFFifo --> BasicFifo_write - Retirement_Retirement1 --> BasicFifo_write + Retirement_Retirement --> BasicFifo_write SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request ICache_ICache2 --> Forwarder_write ICache_ICache1 --> SimpleWBCacheRefiller_start_refill @@ -326,13 +326,13 @@ FIFO9_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation --> FIFO10_write - FIFO10_read --> RSSelection_RSSelection - RSSelection_RSSelection --> Forwarder3_write - Forwarder3_read --> RSSelection_RSSelection1 + FIFO10_read --> RSSelection_RSSelection1 + RSSelection_RSSelection1 --> Forwarder3_write + Forwarder3_read --> RSSelection_RSSelection Forwarder3_read --> RSSelection_RSSelection2 - RSFuncBlock_select --> RSSelection_RSSelection1 - RS_select --> RSSelection_RSSelection1 - RSSelection_RSSelection1 --> FIFO11_write + RSFuncBlock_select --> RSSelection_RSSelection + RS_select --> RSSelection_RSSelection + RSSelection_RSSelection --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write RSSelection_RSSelection2 <--> LSUDummy_select FIFO11_read --> RSInsertion_RSInsertion @@ -353,29 +353,29 @@ ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update - RS_RS1 --> WakeupSelect_WakeupSelect + RS_RS3 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect RS_take --> WakeupSelect3_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO2_write - RS_RS --> WakeupSelect1_WakeupSelect + RS_RS2 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write - RS_RS3 --> WakeupSelect2_WakeupSelect + RS_RS1 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> ExceptionCauseRegister_report WakeupSelect3_WakeupSelect --> ExceptionCauseRegister_report LSUDummyInternals_LSUDummyInternals --> ExceptionCauseRegister_report - LSUDummyInternals_LSUDummyInternals1 --> ExceptionCauseRegister_report + LSUDummyInternals_LSUDummyInternals2 --> ExceptionCauseRegister_report ReorderBuffer_get_indices --> WakeupSelect2_WakeupSelect ReorderBuffer_get_indices --> WakeupSelect3_WakeupSelect ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals - ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals1 + ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals2 WakeupSelect2_WakeupSelect --> FIFO4_write WakeupSelect2_WakeupSelect --> FIFO5_write - RS_RS2 --> WakeupSelect3_WakeupSelect + RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO6_write ConnectTrans2_ConnectTrans --> Forwarder2_write @@ -390,26 +390,26 @@ FIFO4_read --> ConnectTrans4_ConnectTrans ExceptionFuncUnit_accept --> ConnectTrans5_ConnectTrans FIFO6_read --> ConnectTrans5_ConnectTrans - LSUDummyInternals_LSUDummyInternals2 --> WishboneMaster1_request - WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals1 + LSUDummyInternals_LSUDummyInternals1 --> WishboneMaster1_request + WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals2 ConnectTrans_ConnectTrans --> Forwarder1_write ConnectTrans1_ConnectTrans --> Forwarder1_write RSFuncBlock_get_result --> ConnectTrans_ConnectTrans Collector1_method --> ConnectTrans_ConnectTrans Forwarder2_read --> ConnectTrans_ConnectTrans LSUDummy_get_result --> ConnectTrans1_ConnectTrans - ReorderBuffer_peek --> Retirement_Retirement - Retirement_Retirement --> LSUDummy_precommit - ReorderBuffer_retire --> Retirement_Retirement1 - ExceptionCauseRegister_get --> Retirement_Retirement1 - Retirement_Retirement1 --> CSRRegister4_write - Retirement_Retirement1 --> RRAT_commit - Retirement_Retirement1 --> RegisterFile_free - Retirement_Retirement1 <--> DoubleCounterCSR2_increment - CSRRegister5_read --> Retirement_Retirement1 - Retirement_Retirement1 --> CSRRegister5_write - CSRRegister6_read --> Retirement_Retirement1 - Retirement_Retirement1 --> CSRRegister6_write + ReorderBuffer_peek --> Retirement_Retirement1 + Retirement_Retirement1 --> LSUDummy_precommit + ReorderBuffer_retire --> Retirement_Retirement + ExceptionCauseRegister_get --> Retirement_Retirement + Retirement_Retirement --> CSRRegister4_write + Retirement_Retirement --> RRAT_commit + Retirement_Retirement --> RegisterFile_free + Retirement_Retirement <--> DoubleCounterCSR2_increment + CSRRegister5_read --> Retirement_Retirement + Retirement_Retirement --> CSRRegister5_write + CSRRegister6_read --> Retirement_Retirement + Retirement_Retirement --> CSRRegister6_write GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister_write diff --git a/api.html b/api.html index 167683a03..472927ef2 100644 --- a/api.html +++ b/api.html @@ -235,7 +235,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 18:20 2023-10-23. + Last updated on 18:36 2023-10-23.

diff --git a/auto_graph.html b/auto_graph.html index 5df546717..20f76780d 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -85,39 +85,39 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_result["result"] WishboneMaster_request["request"] + WishboneMaster_result["result"] end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_result["result"] WishboneMaster1_request["request"] + WishboneMaster1_result["result"] end subgraph FIFO["fifo_fetch FIFO"] - FIFO_write["write"] FIFO_read["read"] + FIFO_write["write"] end subgraph BasicFifo["free_rf_fifo BasicFifo"] - BasicFifo_write["write"] BasicFifo_read["read"] + BasicFifo_write["write"] end subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"] SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] - SimpleWBCacheRefiller_accept_refill["accept_refill"] SimpleWBCacheRefiller_start_refill["start_refill"] + SimpleWBCacheRefiller_accept_refill["accept_refill"] end subgraph ICache["icache ICache"] - ICache_issue_req["issue_req"] ICache_ICache["ICache"] + ICache_accept_res["accept_res"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] - ICache_accept_res["accept_res"] + ICache_issue_req["issue_req"] subgraph FIFO1["req_fifo FIFO"] - FIFO1_write["write"] FIFO1_read["read"] + FIFO1_write["write"] end subgraph Forwarder["res_fwd Forwarder"] - Forwarder_read["read"] Forwarder_write["write"] + Forwarder_read["read"] end end subgraph Fetch["fetch Fetch"] @@ -136,28 +136,28 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] RegisterFile_write["write"] RegisterFile_free["free"] RegisterFile_read2["read2"] + RegisterFile_read1["read1"] end subgraph ReorderBuffer["ROB ReorderBuffer"] + ReorderBuffer_retire["retire"] ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_peek["peek"] ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_retire["retire"] end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_get["get"] ExceptionCauseRegister_report["report"] + ExceptionCauseRegister_get["get"] end subgraph FuncBlocksUnifier["func_blocks_unifier FuncBlocksUnifier"] subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder1["forwarder Forwarder"] - Forwarder1_read["read"] Forwarder1_write["write"] + Forwarder1_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -174,21 +174,21 @@ subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] RSFuncBlock_insert["insert"] RSFuncBlock_update["update"] - RSFuncBlock_get_result["get_result"] RSFuncBlock_select["select"] + RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] + RS_take["take"] + RS_insert["insert"] + RS_select["select"] RS_RS["RS"] - RS_update["update"] RS_RS1["RS"] - RS_insert["insert"] - RS_take["take"] RS_RS2["RS"] - RS_select["select"] + RS_update["update"] RS_RS3["RS"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph FIFO2["fifo FIFO"] FIFO2_read["read"] FIFO2_write["write"] @@ -209,24 +209,24 @@ WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_branch_result["branch_result"] JumpBranchFuncUnit_issue["issue"] JumpBranchFuncUnit_accept["accept"] + JumpBranchFuncUnit_branch_result["branch_result"] subgraph FIFO4["fifo_res FIFO"] FIFO4_read["read"] FIFO4_write["write"] end subgraph FIFO5["fifo_branch FIFO"] - FIFO5_write["write"] FIFO5_read["read"] + FIFO5_write["write"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] + ExceptionFuncUnit_accept["accept"] subgraph FIFO6["fifo FIFO"] FIFO6_read["read"] FIFO6_write["write"] @@ -258,11 +258,11 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_get_result["get_result"] LSUDummy_select["select"] - LSUDummy_precommit["precommit"] LSUDummy_update["update"] LSUDummy_insert["insert"] + LSUDummy_get_result["get_result"] + LSUDummy_precommit["precommit"] subgraph LSUDummyInternals["internal LSUDummyInternals"] LSUDummyInternals_LSUDummyInternals["LSUDummyInternals"] LSUDummyInternals_LSUDummyInternals1["LSUDummyInternals"] @@ -293,8 +293,8 @@ CSRRegister2_write["write"] end subgraph CSRRegister3["register_high CSRRegister"] - CSRRegister3_write["write"] CSRRegister3_read["read"] + CSRRegister3_write["write"] end end subgraph CSRRegister4["mcause CSRRegister"] @@ -310,8 +310,8 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO8["alloc_rename_buf FIFO"] - FIFO8_read["read"] FIFO8_write["write"] + FIFO8_read["read"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -324,8 +324,8 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -339,8 +339,8 @@ RSSelection_RSSelection1["RSSelection"] RSSelection_RSSelection2["RSSelection"] subgraph Forwarder3["forwarder Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end subgraph RSInsertion["rs_insertion RSInsertion"] @@ -356,8 +356,8 @@ subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_read["read"] CSRRegister5_write["write"] + CSRRegister5_read["read"] end subgraph CSRRegister6["register_high CSRRegister"] CSRRegister6_read["read"] @@ -379,7 +379,7 @@ end end Core_InitFreeRFFifo --> BasicFifo_write -Retirement_Retirement1 --> BasicFifo_write +Retirement_Retirement --> BasicFifo_write SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request ICache_ICache2 --> Forwarder_write ICache_ICache1 --> SimpleWBCacheRefiller_start_refill @@ -405,13 +405,13 @@ FIFO9_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation --> FIFO10_write -FIFO10_read --> RSSelection_RSSelection -RSSelection_RSSelection --> Forwarder3_write -Forwarder3_read --> RSSelection_RSSelection1 +FIFO10_read --> RSSelection_RSSelection1 +RSSelection_RSSelection1 --> Forwarder3_write +Forwarder3_read --> RSSelection_RSSelection Forwarder3_read --> RSSelection_RSSelection2 -RSFuncBlock_select --> RSSelection_RSSelection1 -RS_select --> RSSelection_RSSelection1 -RSSelection_RSSelection1 --> FIFO11_write +RSFuncBlock_select --> RSSelection_RSSelection +RS_select --> RSSelection_RSSelection +RSSelection_RSSelection --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write RSSelection_RSSelection2 <--> LSUDummy_select FIFO11_read --> RSInsertion_RSInsertion @@ -432,29 +432,29 @@ ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update -RS_RS1 --> WakeupSelect_WakeupSelect +RS_RS3 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect RS_take --> WakeupSelect3_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO2_write -RS_RS --> WakeupSelect1_WakeupSelect +RS_RS2 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write -RS_RS3 --> WakeupSelect2_WakeupSelect +RS_RS1 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> ExceptionCauseRegister_report WakeupSelect3_WakeupSelect --> ExceptionCauseRegister_report LSUDummyInternals_LSUDummyInternals --> ExceptionCauseRegister_report -LSUDummyInternals_LSUDummyInternals1 --> ExceptionCauseRegister_report +LSUDummyInternals_LSUDummyInternals2 --> ExceptionCauseRegister_report ReorderBuffer_get_indices --> WakeupSelect2_WakeupSelect ReorderBuffer_get_indices --> WakeupSelect3_WakeupSelect ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals -ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals1 +ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals2 WakeupSelect2_WakeupSelect --> FIFO4_write WakeupSelect2_WakeupSelect --> FIFO5_write -RS_RS2 --> WakeupSelect3_WakeupSelect +RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO6_write ConnectTrans2_ConnectTrans --> Forwarder2_write @@ -469,26 +469,26 @@ FIFO4_read --> ConnectTrans4_ConnectTrans ExceptionFuncUnit_accept --> ConnectTrans5_ConnectTrans FIFO6_read --> ConnectTrans5_ConnectTrans -LSUDummyInternals_LSUDummyInternals2 --> WishboneMaster1_request -WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals1 +LSUDummyInternals_LSUDummyInternals1 --> WishboneMaster1_request +WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals2 ConnectTrans_ConnectTrans --> Forwarder1_write ConnectTrans1_ConnectTrans --> Forwarder1_write RSFuncBlock_get_result --> ConnectTrans_ConnectTrans Collector1_method --> ConnectTrans_ConnectTrans Forwarder2_read --> ConnectTrans_ConnectTrans LSUDummy_get_result --> ConnectTrans1_ConnectTrans -ReorderBuffer_peek --> Retirement_Retirement -Retirement_Retirement --> LSUDummy_precommit -ReorderBuffer_retire --> Retirement_Retirement1 -ExceptionCauseRegister_get --> Retirement_Retirement1 -Retirement_Retirement1 --> CSRRegister4_write -Retirement_Retirement1 --> RRAT_commit -Retirement_Retirement1 --> RegisterFile_free -Retirement_Retirement1 <--> DoubleCounterCSR2_increment -CSRRegister5_read --> Retirement_Retirement1 -Retirement_Retirement1 --> CSRRegister5_write -CSRRegister6_read --> Retirement_Retirement1 -Retirement_Retirement1 --> CSRRegister6_write +ReorderBuffer_peek --> Retirement_Retirement1 +Retirement_Retirement1 --> LSUDummy_precommit +ReorderBuffer_retire --> Retirement_Retirement +ExceptionCauseRegister_get --> Retirement_Retirement +Retirement_Retirement --> CSRRegister4_write +Retirement_Retirement --> RRAT_commit +Retirement_Retirement --> RegisterFile_free +Retirement_Retirement <--> DoubleCounterCSR2_increment +CSRRegister5_read --> Retirement_Retirement +Retirement_Retirement --> CSRRegister5_write +CSRRegister6_read --> Retirement_Retirement +Retirement_Retirement --> CSRRegister6_write GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister_write @@ -509,7 +509,7 @@

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diff --git a/components/icache.html b/components/icache.html index 109da84b9..782483b53 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

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diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index e2b4f5495..d33254c45 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -399,7 +399,7 @@

Submodules

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diff --git a/coreblocks.fu.html b/coreblocks.fu.html index 304136841..8ebe961e4 100644 --- a/coreblocks.fu.html +++ b/coreblocks.fu.html @@ -817,7 +817,7 @@

Submodules

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diff --git a/coreblocks.fu.unsigned_multiplication.html b/coreblocks.fu.unsigned_multiplication.html index cfce9701d..384a318ec 100644 --- a/coreblocks.fu.unsigned_multiplication.html +++ b/coreblocks.fu.unsigned_multiplication.html @@ -237,7 +237,7 @@

Submodules

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diff --git a/coreblocks.html b/coreblocks.html index 03f2f0090..f06effafb 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -218,7 +218,7 @@

Submodules

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diff --git a/coreblocks.params.html b/coreblocks.params.html index 2511048b5..ef398d2c5 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -2404,7 +2404,7 @@

Submodules

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diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index cd054d859..fd0fc8f39 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -348,7 +348,7 @@

Submodules

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diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index f01367dd9..cc3a494b6 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

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diff --git a/coreblocks.stages.html b/coreblocks.stages.html index 71e1466f1..404b34038 100644 --- a/coreblocks.stages.html +++ b/coreblocks.stages.html @@ -266,7 +266,7 @@

Submodules

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diff --git a/coreblocks.structs_common.html b/coreblocks.structs_common.html index d10588fbc..f31b95b92 100644 --- a/coreblocks.structs_common.html +++ b/coreblocks.structs_common.html @@ -454,7 +454,7 @@

Submodules

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diff --git a/coreblocks.utils.html b/coreblocks.utils.html index 0fb19f207..befe3a3cc 100644 --- a/coreblocks.utils.html +++ b/coreblocks.utils.html @@ -456,7 +456,7 @@

Submodules

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diff --git a/genindex.html b/genindex.html index 75549ce0f..e265dbaff 100644 --- a/genindex.html +++ b/genindex.html @@ -2774,7 +2774,7 @@

Z

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diff --git a/index.html b/index.html index 490cc151b..3a905a027 100644 --- a/index.html +++ b/index.html @@ -214,7 +214,7 @@

Coreblocks

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diff --git a/miscellany/exceptionsSummary.html b/miscellany/exceptionsSummary.html index a84280cb1..bedb8f549 100644 --- a/miscellany/exceptionsSummary.html +++ b/miscellany/exceptionsSummary.html @@ -271,7 +271,7 @@

Summary

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diff --git a/modules-coreblocks.html b/modules-coreblocks.html index 8c2c70082..79e297819 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -187,7 +187,7 @@

coreblocks

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diff --git a/modules-transactron.html b/modules-transactron.html index a85bb47ac..99ff84a00 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -118,7 +118,7 @@

transactron

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diff --git a/py-modindex.html b/py-modindex.html index ed7ff6fbc..20fb83eb3 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -453,7 +453,7 @@

Python Module Index

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diff --git a/scheduler/Overview.html b/scheduler/Overview.html index 6876de9c4..8030777c9 100644 --- a/scheduler/Overview.html +++ b/scheduler/Overview.html @@ -146,7 +146,7 @@

More detailed description of each block

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diff --git a/search.html b/search.html index 924dd7735..40847e3c0 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

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diff --git a/shared_structs/Implementation/RS_impl.html b/shared_structs/Implementation/RS_impl.html index 7ba3b5575..df00e7e5b 100644 --- a/shared_structs/Implementation/RS_impl.html +++ b/shared_structs/Implementation/RS_impl.html @@ -252,7 +252,7 @@

Read and clean row

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diff --git a/shared_structs/RS.html b/shared_structs/RS.html index bbf5663d9..0f6e08a5e 100644 --- a/shared_structs/RS.html +++ b/shared_structs/RS.html @@ -222,7 +222,7 @@

External interface signals

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diff --git a/synthesis/Synthesis.html b/synthesis/Synthesis.html index f0361ae1c..6cf3c31b7 100644 --- a/synthesis/Synthesis.html +++ b/synthesis/Synthesis.html @@ -151,7 +151,7 @@

Benchmarks

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diff --git a/transactron.html b/transactron.html index d27cae86b..4d04ee462 100644 --- a/transactron.html +++ b/transactron.html @@ -1297,7 +1297,7 @@

Submodules

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diff --git a/transactron.lib.html b/transactron.lib.html index 94962194d..419dd0bc5 100644 --- a/transactron.lib.html +++ b/transactron.lib.html @@ -895,7 +895,7 @@

Submodules

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