From 38953222b5fa23ecc9c0dd11158a4bf68061a16a Mon Sep 17 00:00:00 2001 From: tilk Date: Mon, 1 Apr 2024 10:00:29 +0000 Subject: [PATCH] Refactor RISC-V instruction models (#631) --- .doctrees/api.doctree | Bin 21253 -> 21253 bytes .doctrees/auto_graph.doctree | Bin 44476 -> 44485 bytes .doctrees/coreblocks.frontend.decoder.doctree | Bin 454594 -> 455809 bytes .doctrees/coreblocks.params.doctree | Bin 297585 -> 372086 bytes .doctrees/current-graph.doctree | Bin 45697 -> 45706 bytes .doctrees/environment.pickle | Bin 505985 -> 507740 bytes _sources/auto_graph.rst.txt | 350 ++++++------ api.html | 2 +- assumptions.html | 2 +- auto_graph.html | 352 ++++++------ components/icache.html | 2 +- coreblocks.backend.html | 2 +- coreblocks.cache.html | 2 +- coreblocks.core_structs.html | 2 +- coreblocks.frontend.decoder.html | 7 +- coreblocks.frontend.fetch.html | 2 +- coreblocks.frontend.html | 2 +- coreblocks.func_blocks.fu.html | 2 +- ...unc_blocks.fu.unsigned_multiplication.html | 2 +- coreblocks.func_blocks.html | 2 +- coreblocks.func_blocks.interface.html | 2 +- coreblocks.func_blocks.lsu.html | 2 +- coreblocks.html | 2 +- coreblocks.params.html | 537 +++++++++++++++--- coreblocks.peripherals.html | 2 +- coreblocks.priv.csr.html | 2 +- coreblocks.priv.html | 2 +- coreblocks.priv.traps.html | 2 +- coreblocks.scheduler.html | 2 +- current-graph.html | 352 ++++++------ development-environment.html | 2 +- genindex.html | 108 ++-- home.html | 2 +- index.html | 2 +- miscellany/exceptions-summary.html | 2 +- modules-coreblocks.html | 2 +- modules-transactron.html | 2 +- objects.inv | Bin 10555 -> 10616 bytes problem-checklist.html | 2 +- py-modindex.html | 2 +- scheduler/overview.html | 2 +- search.html | 2 +- searchindex.js | 2 +- shared-structs/implementation/rs-impl.html | 2 +- shared-structs/rs.html | 2 +- synthesis/synthesis.html | 2 +- transactions.html | 2 +- transactron.core.html | 2 +- transactron.html | 2 +- transactron.lib.html | 2 +- transactron.testing.html | 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zQShpO*A;wMz=afuM?VnqMv6o~67W+6KNIk#f=dG4Qt&GQzftg80l!!9j(~R+{7FFk z&r04C@>hTcyx;c)Tv2dUz%>Q`5b$pW{}J$C1^*K;q%u`$2EXFHHFE&){zpQF=`2|S zMk=^Lz>NxS5-=K|7OOf&z*q&J5-?uDZ2~4JnCL+~nxrIKW|^!YN5E7CxdQSPOcO92 z0LQ!N9svak?h`OW!At@73&8$2TgV)pWv+mE3g!zaQcx_QRKY?4WeUm#R4RB>z!C*Z z0eDQ^ BasicFifo2_write - Retirement_Retirement --> BasicFifo2_write - TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write - TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write + Retirement_Retirement4 --> BasicFifo2_write + TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write + TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + Serializer_Serializer1 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write - ICache_ICache2 <--> HwCounter4__incr - ICache_ICache1 <--> HwCounter3__incr - ICache_ICache1 <--> HwCounter2__incr - ICache_ICache1 <--> HwCounter1__incr - ICache_ICache1 --> Forwarder3_write - ICache_ICache3 --> SimpleCommonBusCacheRefiller_start_refill - SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache - Forwarder2_read --> ICache_ICache + ICache_ICache3 <--> HwCounter4__incr + ICache_ICache2 <--> HwCounter3__incr + ICache_ICache2 <--> HwCounter2__incr + ICache_ICache2 <--> HwCounter1__incr + ICache_ICache2 --> Forwarder3_write + ICache_ICache --> SimpleCommonBusCacheRefiller_start_refill + SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 + Forwarder2_read --> ICache_ICache1 Fetch_Fetch --> ICache_issue_req Fetch_Fetch <--> HwCounter__incr Fetch_Fetch <--> LatencyMeasurer__start @@ -571,25 +571,25 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename - Retirement_Retirement --> FRAT_rename - TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename + Retirement_Retirement4 --> FRAT_rename + TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write - FIFO12_read --> RSSelection_RSSelection2 - RSSelection_RSSelection2 --> Forwarder8_write - Forwarder8_read --> RSSelection_RSSelection1 + FIFO12_read --> RSSelection_RSSelection1 + RSSelection_RSSelection1 --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection3 + Forwarder8_read --> RSSelection_RSSelection2 Forwarder8_read --> RSSelection_RSSelection - RSFuncBlock_select --> RSSelection_RSSelection1 - RS_select --> RSSelection_RSSelection1 - RSSelection_RSSelection1 --> FIFO13_write + RSFuncBlock_select --> RSSelection_RSSelection3 + RS_select --> RSSelection_RSSelection3 RSSelection_RSSelection3 --> FIFO13_write + RSSelection_RSSelection2 --> FIFO13_write RSSelection_RSSelection --> FIFO13_write - RSSelection_RSSelection3 <--> LSUDummy_select + RSSelection_RSSelection2 <--> LSUDummy_select RSSelection_RSSelection <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion @@ -606,7 +606,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume - Retirement_Retirement3 --> Fetch_resume + Retirement_Retirement --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -616,7 +616,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update - RS_RS3 --> WakeupSelect_WakeupSelect + RS_RS1 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -624,10 +624,10 @@ RS_take --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO4_write - RS_RS4 --> WakeupSelect1_WakeupSelect + RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write - RS_RS2 --> WakeupSelect2_WakeupSelect + RS_RS --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -639,10 +639,10 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write - RS_RS1 --> WakeupSelect3_WakeupSelect + RS_RS2 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write - RS_RS --> WakeupSelect4_WakeupSelect + RS_RS4 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -661,11 +661,11 @@ CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write LSUDummy_LSUDummy --> Forwarder6_write - TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write - TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write - TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write - TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write + TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write + TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write + TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write + TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -687,45 +687,45 @@ LSUDummy_get_result --> ConnectTrans2_ConnectTrans Forwarder6_read --> ConnectTrans2_ConnectTrans CSRUnit_get_result --> ConnectTrans3_ConnectTrans - MethodTryProduct_MethodTryProduct --> PrivilegedFuncUnit_precommit - MethodTryProduct_MethodTryProduct <--> InterruptController_mret - MethodTryProduct_MethodTryProduct1 --> LSUDummy_precommit - MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit + MethodTryProduct_MethodTryProduct1 --> PrivilegedFuncUnit_precommit + MethodTryProduct_MethodTryProduct1 <--> InterruptController_mret + MethodTryProduct_MethodTryProduct2 --> LSUDummy_precommit + MethodTryProduct_MethodTryProduct --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans + ReorderBuffer_peek --> Retirement_Retirement3 + ReorderBuffer_peek --> Retirement_Retirement2 ReorderBuffer_peek --> Retirement_Retirement4 - ReorderBuffer_peek --> Retirement_Retirement1 - ReorderBuffer_peek --> Retirement_Retirement - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement4 --> MethodTryProduct_method - ExceptionCauseRegister_get --> Retirement_Retirement1 - ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 - ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement <--> ReorderBuffer_retire - TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire - TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire - Retirement_Retirement <--> LatencyMeasurer1__stop - TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop - TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop - FIFO3_read --> Retirement_Retirement - FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 - FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement --> HwExpHistogram1__add - TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add - TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add - CoreInstructionCounter_decrement --> Retirement_Retirement - CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 - RRAT_peek --> Retirement_Retirement - RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement --> RegisterFile_free - TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free - TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free - CSRRegister1_read --> Retirement_Retirement3 - Retirement_Retirement3 <--> ExceptionCauseRegister_clear + ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement + Retirement_Retirement3 --> MethodTryProduct_method + ExceptionCauseRegister_get --> Retirement_Retirement2 + ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement + ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement + Retirement_Retirement4 <--> ReorderBuffer_retire + TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire + TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire + Retirement_Retirement4 <--> LatencyMeasurer1__stop + TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop + TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop + FIFO3_read --> Retirement_Retirement4 + FIFO3_read --> TransactionManager_Retirement_cond0_Retirement + FIFO3_read --> TransactionManager_Retirement_cond1_Retirement + Retirement_Retirement4 --> HwExpHistogram1__add + TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add + TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add + CoreInstructionCounter_decrement --> Retirement_Retirement4 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement + CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement + RRAT_peek --> Retirement_Retirement4 + RRAT_peek --> TransactionManager_Retirement_cond1_Retirement + Retirement_Retirement4 --> RegisterFile_free + TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free + TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free + CSRRegister1_read --> Retirement_Retirement + Retirement_Retirement <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -737,53 +737,53 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt + TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_cond0_Retirement --> RRAT_commit + TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment + CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write + CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write + TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr + TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement1 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement1 + TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write + TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write + TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write + TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write + TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry + TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry + TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 + TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write + TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer + TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write + TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write + TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request + TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request + TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy1 + TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy Serializer1_Serializer2 --> TransactionManager_accept_cond1_LSUDummy BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy - BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy + BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy - WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy + WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy - Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy + Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy2 - TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy2 + TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2 LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy - LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy - TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 - TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write - TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer1 - TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write - TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write - TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request - TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request - TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 - TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 - TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 - TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue - TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue - TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue - TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 - TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 - TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read - TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer - TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2 - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement2 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write - TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry - TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry - TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit - TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment - CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write - CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write - TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr - TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy - Serializer1_Serializer3 --> TransactionManager_accept_cond0_LSUDummy - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 + LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 + TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 + Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond0 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 + TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 + TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read + TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer1 diff --git a/api.html b/api.html index 8ab3aed4b..619d20cea 100644 --- a/api.html +++ b/api.html @@ -259,7 +259,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/assumptions.html b/assumptions.html index 46da0f858..b70e554a2 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/auto_graph.html b/auto_graph.html index bd241f8d2..6344f33c3 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -83,24 +83,24 @@ subgraph TransactionModule["TransactionModule"] subgraph CoreTestElaboratable["elaboratable CoreTestElaboratable"] subgraph Core["core Core"] - Core_DiscardBranchVerify["DiscardBranchVerify"] Core_InitFreeRFFifo["InitFreeRFFifo"] + Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_result["result"] WishboneMaster_request["request"] + WishboneMaster_result["result"] WishboneMaster_WishboneMaster["WishboneMaster"] subgraph Forwarder["result Forwarder"] - Forwarder_write["write"] Forwarder_read["read"] + Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_WishboneMaster["WishboneMaster"] WishboneMaster1_request["request"] WishboneMaster1_result["result"] + WishboneMaster1_WishboneMaster["WishboneMaster"] subgraph Forwarder1["result Forwarder"] - Forwarder1_read["read"] Forwarder1_write["write"] + Forwarder1_read["read"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] @@ -110,30 +110,30 @@ Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_write["write"] BasicFifo_read["read"] + BasicFifo_write["write"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] - WishboneMasterAdapter1_request_read["request_read"] - WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_get_write_response["get_write_response"] + WishboneMasterAdapter1_request_read["request_read"] + WishboneMasterAdapter1_request_write["request_write"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_read["read"] BasicFifo1_write["write"] + BasicFifo1_read["read"] end end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_decrement["decrement"] CoreInstructionCounter_increment["increment"] + CoreInstructionCounter_decrement["decrement"] end subgraph FIFO["fifo_fetch FIFO"] FIFO_write["write"] @@ -146,13 +146,13 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_write["write"] BasicFifo2_read["read"] + BasicFifo2_write["write"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] subgraph Forwarder2["resp_fwd Forwarder"] Forwarder2_read["read"] @@ -160,10 +160,10 @@ end end subgraph ICache["icache ICache"] + ICache_issue_req["issue_req"] ICache_ICache["ICache"] - ICache_ICache1["ICache"] ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] + ICache_ICache1["ICache"] ICache_ICache2["ICache"] ICache_ICache3["ICache"] subgraph HwCounter["perf_loads HwCounter"] @@ -188,8 +188,8 @@ HwExpHistogram__add["_add"] end subgraph FIFO1["fifo FIFO"] - FIFO1_read["read"] FIFO1_write["write"] + FIFO1_read["read"] end end subgraph FIFO2["req_fifo FIFO"] @@ -197,29 +197,29 @@ FIFO2_read["read"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_read["read"] Forwarder3_write["write"] + Forwarder3_read["read"] end end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_commit["commit"] RRAT_peek["peek"] + RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] - RegisterFile_write["write"] RegisterFile_read2["read2"] + RegisterFile_read1["read1"] RegisterFile_free["free"] + RegisterFile_write["write"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_put["put"] ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_retire["retire"] + ReorderBuffer_put["put"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_peek["peek"] - ReorderBuffer_retire["retire"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] LatencyMeasurer1__stop["_stop"] LatencyMeasurer1__start["_start"] @@ -233,13 +233,13 @@ end end subgraph Fetch["fetch Fetch"] - Fetch_Fetch["Fetch"] Fetch_resume["resume"] - Fetch_Fetch1["Fetch"] Fetch_stall_exception["stall_exception"] + Fetch_Fetch["Fetch"] + Fetch_Fetch1["Fetch"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] - BasicFifo3_read["read"] BasicFifo3_write["write"] + BasicFifo3_read["read"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] @@ -247,8 +247,8 @@ ExceptionCauseRegister_get["get"] ExceptionCauseRegister_clear["clear"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] - BasicFifo4_write["write"] BasicFifo4_read["read"] + BasicFifo4_write["write"] end subgraph ConnectTrans["report_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -283,18 +283,18 @@ RSFuncBlock_insert["insert"] subgraph RS["rs RS"] RS_RS["RS"] - RS_update["update"] - RS_take["take"] + RS_select["select"] RS_RS1["RS"] RS_RS2["RS"] - RS_select["select"] + RS_update["update"] RS_RS3["RS"] - RS_RS4["RS"] RS_insert["insert"] + RS_take["take"] + RS_RS4["RS"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph FIFO4["fifo FIFO"] FIFO4_write["write"] FIFO4_read["read"] @@ -315,8 +315,8 @@ WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO6["fifo_branch_resolved FIFO"] FIFO6_read["read"] FIFO6_write["write"] @@ -331,8 +331,8 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -350,12 +350,12 @@ WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] + PrivilegedFuncUnit_precommit["precommit"] PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_accept["accept"] - PrivilegedFuncUnit_precommit["precommit"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] - BasicFifo5_write["write"] BasicFifo5_read["read"] + BasicFifo5_write["write"] end end subgraph WakeupSelect4["wakeup_select_4 WakeupSelect"] @@ -364,8 +364,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_read["read"] Forwarder5_write["write"] + Forwarder5_read["read"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans4["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -387,13 +387,13 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] + LSUDummy_get_result["get_result"] + LSUDummy_select["select"] LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_insert["insert"] LSUDummy_precommit["precommit"] - LSUDummy_get_result["get_result"] LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_insert["insert"] LSUDummy_LSUDummy2["LSUDummy"] - LSUDummy_select["select"] LSUDummy_update["update"] subgraph Forwarder6["forwarder Forwarder"] Forwarder6_write["write"] @@ -401,22 +401,22 @@ end subgraph LSURequester["requester LSURequester"] LSURequester_accept_cond1["accept_cond1"] - LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept["accept"] LSURequester_accept_cond0["accept_cond0"] - LSURequester_issue_cond2["issue_cond2"] + LSURequester_issue_cond0["issue_cond0"] LSURequester_issue["issue"] - LSURequester_accept["accept"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond2["issue_cond2"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_select["select"] - CSRUnit_update["update"] - CSRUnit_precommit["precommit"] - CSRUnit_get_result["get_result"] + CSRUnit_insert["insert"] CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_precommit["precommit"] CSRUnit_fetch_resume["fetch_resume"] - CSRUnit_insert["insert"] + CSRUnit_update["update"] + CSRUnit_select["select"] + CSRUnit_get_result["get_result"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] @@ -427,8 +427,8 @@ subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_read["read"] Forwarder7_write["write"] + Forwarder7_read["read"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans9["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -445,16 +445,16 @@ end subgraph InterruptController["interrupt_controller InterruptController"] InterruptController_report_interrupt["report_interrupt"] - InterruptController_entry["entry"] InterruptController_mret["mret"] + InterruptController_entry["entry"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] + CSRRegister_write["write"] CSRRegister__fu_read["_fu_read"] CSRRegister__fu_write["_fu_write"] - CSRRegister_write["write"] end subgraph CSRRegister1["mtvec CSRRegister"] CSRRegister1__fu_read["_fu_read"] @@ -463,8 +463,8 @@ end subgraph CSRRegister2["mepc CSRRegister"] CSRRegister2_read["read"] - CSRRegister2__fu_read["_fu_read"] CSRRegister2__fu_write["_fu_write"] + CSRRegister2__fu_read["_fu_read"] CSRRegister2_write["write"] end end @@ -472,8 +472,8 @@ DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] CSRRegister3_read["read"] - CSRRegister3_write["write"] CSRRegister3__fu_read["_fu_read"] + CSRRegister3_write["write"] end subgraph CSRRegister4["register_high CSRRegister"] CSRRegister4__fu_read["_fu_read"] @@ -490,14 +490,14 @@ end subgraph CSRRegister6["register_high CSRRegister"] CSRRegister6_write["write"] - CSRRegister6_read["read"] CSRRegister6__fu_read["_fu_read"] + CSRRegister6_read["read"] end end end subgraph FIFO9["fifo_decode FIFO"] - FIFO9_write["write"] FIFO9_read["read"] + FIFO9_write["write"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -514,8 +514,8 @@ RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO11["rename_out_buf FIFO"] - FIFO11_read["read"] FIFO11_write["write"] + FIFO11_read["read"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] @@ -528,8 +528,8 @@ ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO13["rs_select_out_buf FIFO"] - FIFO13_read["read"] FIFO13_write["write"] + FIFO13_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -549,25 +549,25 @@ ConnectTrans11_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] + Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] Retirement_Retirement1["Retirement"] - Retirement_core_state["core_state"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement4["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] + CSRRegister7__fu_read["_fu_read"] CSRRegister7_read["read"] CSRRegister7_write["write"] - CSRRegister7__fu_read["_fu_read"] end subgraph CSRRegister8["register_high CSRRegister"] - CSRRegister8_read["read"] - CSRRegister8__fu_read["_fu_read"] CSRRegister8_write["write"] + CSRRegister8__fu_read["_fu_read"] + CSRRegister8_read["read"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -587,40 +587,40 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] - TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] - TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] - TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] - TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] - TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] end end Core_InitFreeRFFifo --> BasicFifo2_write -Retirement_Retirement --> BasicFifo2_write -TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write -TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write +Retirement_Retirement4 --> BasicFifo2_write +TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write +TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +Serializer_Serializer1 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write -ICache_ICache2 <--> HwCounter4__incr -ICache_ICache1 <--> HwCounter3__incr -ICache_ICache1 <--> HwCounter2__incr -ICache_ICache1 <--> HwCounter1__incr -ICache_ICache1 --> Forwarder3_write -ICache_ICache3 --> SimpleCommonBusCacheRefiller_start_refill -SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache -Forwarder2_read --> ICache_ICache +ICache_ICache3 <--> HwCounter4__incr +ICache_ICache2 <--> HwCounter3__incr +ICache_ICache2 <--> HwCounter2__incr +ICache_ICache2 <--> HwCounter1__incr +ICache_ICache2 --> Forwarder3_write +ICache_ICache --> SimpleCommonBusCacheRefiller_start_refill +SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 +Forwarder2_read --> ICache_ICache1 Fetch_Fetch --> ICache_issue_req Fetch_Fetch <--> HwCounter__incr Fetch_Fetch <--> LatencyMeasurer__start @@ -650,25 +650,25 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename -Retirement_Retirement --> FRAT_rename -TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename +Retirement_Retirement4 --> FRAT_rename +TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write -FIFO12_read --> RSSelection_RSSelection2 -RSSelection_RSSelection2 --> Forwarder8_write -Forwarder8_read --> RSSelection_RSSelection1 +FIFO12_read --> RSSelection_RSSelection1 +RSSelection_RSSelection1 --> Forwarder8_write Forwarder8_read --> RSSelection_RSSelection3 +Forwarder8_read --> RSSelection_RSSelection2 Forwarder8_read --> RSSelection_RSSelection -RSFuncBlock_select --> RSSelection_RSSelection1 -RS_select --> RSSelection_RSSelection1 -RSSelection_RSSelection1 --> FIFO13_write +RSFuncBlock_select --> RSSelection_RSSelection3 +RS_select --> RSSelection_RSSelection3 RSSelection_RSSelection3 --> FIFO13_write +RSSelection_RSSelection2 --> FIFO13_write RSSelection_RSSelection --> FIFO13_write -RSSelection_RSSelection3 <--> LSUDummy_select +RSSelection_RSSelection2 <--> LSUDummy_select RSSelection_RSSelection <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion @@ -685,7 +685,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume -Retirement_Retirement3 --> Fetch_resume +Retirement_Retirement --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -695,7 +695,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update -RS_RS3 --> WakeupSelect_WakeupSelect +RS_RS1 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -703,10 +703,10 @@ RS_take --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO4_write -RS_RS4 --> WakeupSelect1_WakeupSelect +RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write -RS_RS2 --> WakeupSelect2_WakeupSelect +RS_RS --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -718,10 +718,10 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write -RS_RS1 --> WakeupSelect3_WakeupSelect +RS_RS2 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write -RS_RS --> WakeupSelect4_WakeupSelect +RS_RS4 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -740,11 +740,11 @@ CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write LSUDummy_LSUDummy --> Forwarder6_write -TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write TransactionManager_issue_cond0_LSUDummy --> Forwarder6_write -TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write -TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write -TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write +TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write +TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write +TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write +TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -766,45 +766,45 @@ LSUDummy_get_result --> ConnectTrans2_ConnectTrans Forwarder6_read --> ConnectTrans2_ConnectTrans CSRUnit_get_result --> ConnectTrans3_ConnectTrans -MethodTryProduct_MethodTryProduct --> PrivilegedFuncUnit_precommit -MethodTryProduct_MethodTryProduct <--> InterruptController_mret -MethodTryProduct_MethodTryProduct1 --> LSUDummy_precommit -MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit +MethodTryProduct_MethodTryProduct1 --> PrivilegedFuncUnit_precommit +MethodTryProduct_MethodTryProduct1 <--> InterruptController_mret +MethodTryProduct_MethodTryProduct2 --> LSUDummy_precommit +MethodTryProduct_MethodTryProduct --> CSRUnit_precommit ConnectTrans9_ConnectTrans --> Forwarder7_write ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans +ReorderBuffer_peek --> Retirement_Retirement3 +ReorderBuffer_peek --> Retirement_Retirement2 ReorderBuffer_peek --> Retirement_Retirement4 -ReorderBuffer_peek --> Retirement_Retirement1 -ReorderBuffer_peek --> Retirement_Retirement -ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 -ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement4 --> MethodTryProduct_method -ExceptionCauseRegister_get --> Retirement_Retirement1 -ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 -ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement <--> ReorderBuffer_retire -TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire -TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire -Retirement_Retirement <--> LatencyMeasurer1__stop -TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop -TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop -FIFO3_read --> Retirement_Retirement -FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 -FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement --> HwExpHistogram1__add -TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add -TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add -CoreInstructionCounter_decrement --> Retirement_Retirement -CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 -RRAT_peek --> Retirement_Retirement -RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement --> RegisterFile_free -TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free -TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free -CSRRegister1_read --> Retirement_Retirement3 -Retirement_Retirement3 <--> ExceptionCauseRegister_clear +ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement +ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement +Retirement_Retirement3 --> MethodTryProduct_method +ExceptionCauseRegister_get --> Retirement_Retirement2 +ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement +ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement +Retirement_Retirement4 <--> ReorderBuffer_retire +TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire +TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire +Retirement_Retirement4 <--> LatencyMeasurer1__stop +TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop +TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop +FIFO3_read --> Retirement_Retirement4 +FIFO3_read --> TransactionManager_Retirement_cond0_Retirement +FIFO3_read --> TransactionManager_Retirement_cond1_Retirement +Retirement_Retirement4 --> HwExpHistogram1__add +TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add +TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add +CoreInstructionCounter_decrement --> Retirement_Retirement4 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement +CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement +RRAT_peek --> Retirement_Retirement4 +RRAT_peek --> TransactionManager_Retirement_cond1_Retirement +Retirement_Retirement4 --> RegisterFile_free +TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free +TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free +CSRRegister1_read --> Retirement_Retirement +Retirement_Retirement <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -816,56 +816,56 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt +TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_cond0_Retirement --> RRAT_commit +TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment +CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write +CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write +TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr +TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement1 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement1 +TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write +TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write +TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write +TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write +TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry +TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry +TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 +TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write +TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer +TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write +TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write +TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request +TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request +TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy1 +TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy Serializer1_Serializer2 --> TransactionManager_accept_cond1_LSUDummy BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy -BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy +BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy -WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy +WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy -Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy +Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy2 -TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy2 +TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2 LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy -LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy -TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 -TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write -TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer1 -TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write -TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write -TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request -TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request -TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 -TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 -TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 -TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue -TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue -TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue -TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 -TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 -TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read -TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer -TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2 -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement2 -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write -TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry -TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry -TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit -TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment -CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write -CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write -TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr -TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy -Serializer1_Serializer3 --> TransactionManager_accept_cond0_LSUDummy -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 +LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 +TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 +TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 +Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond0 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 +TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 +TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read +TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer1 @@ -876,7 +876,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/components/icache.html b/components/icache.html index 4a49c5544..f1d01db6a 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.backend.html b/coreblocks.backend.html index 97783cc64..4469ec273 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -165,7 +165,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index b830418b3..ad25052fd 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -241,7 +241,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index ec3cae5c2..56d08ff47 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -157,7 +157,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index 0bf181124..fdc1c3137 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -1125,6 +1125,11 @@

SubmodulesOP_IMM_32 = 6
+
+
+RESERVED = 31
+
+
STORE = 8
@@ -1721,7 +1726,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index 15d16af82..f16c298aa 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -161,7 +161,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index cc3d008ad..56f4e3da1 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -125,7 +125,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index 269d7481f..a478c40ca 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -867,7 +867,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index 49ae16f3b..c750e5f24 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -238,7 +238,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index 30f4c48f1..9fa98c120 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -148,7 +148,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index f3cabe485..6b3067c20 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -169,7 +169,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.func_blocks.lsu.html b/coreblocks.func_blocks.lsu.html index 3fe2759f1..3df11bc52 100644 --- a/coreblocks.func_blocks.lsu.html +++ b/coreblocks.func_blocks.lsu.html @@ -248,7 +248,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.html b/coreblocks.html index db9ee097d..06040f010 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -255,7 +255,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.params.html b/coreblocks.params.html index 693db6b54..321277886 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -315,24 +315,94 @@

Submodules

coreblocks.params.instr module

+

Based on riscv-python-model by Stefan Wallentowitz +https://github.com/wallento/riscv-python-model

class coreblocks.params.instr.BTypeInstr
-

Bases: RISCVInstr

+

Bases: InstructionFunct3Type

-__init__(opcode: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
-
-
-static encode(opcode: int, imm: int, funct3: int, rs1: int, rs2: int)
-
+
+
+imm
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
-
-
-pack() → Value
-
+
+
+rs1
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
+ +
+
+rs2
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
@@ -350,41 +420,104 @@

Submodules
class coreblocks.params.instr.ITypeInstr
-

Bases: RISCVInstr

+

Bases: InstructionFunct3Type

-__init__(opcode: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
-
-
-static encode(opcode: int, rd: int, funct3: int, rs1: int, imm: int)
-
+
+
+imm
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
-
-
-pack() → Value
-
+
+
+rd
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
+ +
+
+rs1
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+

class coreblocks.params.instr.IllegalInstr
-

Bases: RISCVInstr

+

Bases: RISCVInstr

__init__()
-
-
-static encode(opcode: int, rd: int, imm: int)
-
- -
-
-pack() → Value
+
+
+illegal = (cat (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)) (cat (const 1'd1)))
@@ -392,20 +525,114 @@

Submodules
class coreblocks.params.instr.JTypeInstr
-

Bases: RISCVInstr

+

Bases: RISCVInstr

-__init__(opcode: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable) +
+ +
+
+imm
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
+ +
+
+rd
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
+ +
+ +
+
+class coreblocks.params.instr.RISCVInstr
+

Bases: ABC, ValueCastable

+
+
+__init__(opcode: Opcode)
-
-static encode(opcode: int, rd: int, imm: int)
+
+as_value() → Value
-
-pack() → Value
+
+encode() → int
+
+ +
+
+opcode
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
+ +
+
+shape() → Shape
@@ -413,63 +640,241 @@

Submodules
class coreblocks.params.instr.RTypeInstr
-

Bases: RISCVInstr

+

Bases: InstructionFunct3Type, InstructionFunct7Type

-__init__(opcode: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct7: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct7: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
-
-
-static encode(opcode: int, rd: int, funct3: int, rs1: int, rs2: int, funct7: int)
-
+
+
+rd
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
-
-
-pack() → Value
-
+
+
+rs1
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
+ +
+
+rs2
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
class coreblocks.params.instr.STypeInstr
-

Bases: RISCVInstr

+

Bases: InstructionFunct3Type

-__init__(opcode: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, funct3: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs1: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rs2: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
-
-
-static encode(opcode: int, imm: int, funct3: int, rs1: int, rs2: int)
-
+
+
+imm
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
-
-
-pack() → Value
-
+
+
+rs1
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
+ +
+
+rs2
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
class coreblocks.params.instr.UTypeInstr
-

Bases: RISCVInstr

+

Bases: RISCVInstr

-__init__(opcode: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
+__init__(opcode: Opcode, rd: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, imm: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable)
-
-
-static encode(opcode: int, rd: int, imm: int)
-
+
+
+imm
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
-
-
-pack() → Value
-
+
+
+rd
+

Information about a field in a RISC-V instruction.

+
+
Attributes
+
+
base: int | list[int]

A bit position (or a list of positions) where this field (or parts of the field) +would map in the instruction.

+
+
size: int | list[int]

Size (or sizes of the parts) of the field

+
+
signed: bool

Whether this field encodes a signed value.

+
+
offset: int

How many bits of this field should be skipped when encoding the instruction. +For example, the immediate of the jump instruction always skips the least +significant bit. This only affects encoding procedures, so externally (for example +when creating an instance of a instruction) full-size values should be always used.

+
+
static_value: Optional[Value]

Whether the field should have a static value for a given type of an instruction.

+
+
+
+
+
@@ -761,7 +1166,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index 728532bee..848968bce 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -746,7 +746,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html index af2333f5b..d95c1b093 100644 --- a/coreblocks.priv.csr.html +++ b/coreblocks.priv.csr.html @@ -327,7 +327,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.priv.html b/coreblocks.priv.html index 6b8207fad..19dfa2ddb 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -123,7 +123,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index 5faa0d2e3..d5f3d1e16 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -171,7 +171,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 84a18b3cc..bd962bbeb 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/current-graph.html b/current-graph.html index bc0e1328f..34e8779e0 100644 --- a/current-graph.html +++ b/current-graph.html @@ -89,24 +89,24 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/development-environment.html b/development-environment.html index 32e3ec008..8f45cf9d2 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 10:11 2024-03-31. + Last updated on 10:00 2024-04-01.

diff --git a/genindex.html b/genindex.html index abcead821..d83f75916 100644 --- a/genindex.html +++ b/genindex.html @@ -217,6 +217,8 @@

_

  • (coreblocks.params.instr.ITypeInstr method)
  • (coreblocks.params.instr.JTypeInstr method) +
    • +
  • (coreblocks.params.instr.RISCVInstr method)
  • (coreblocks.params.instr.RTypeInstr method)
    • @@ -556,6 +558,8 @@

    A

  • ArgumentsToResultsZipper (class in transactron.lib.reqres)
  • ARITHMETIC (coreblocks.frontend.decoder.optypes.OpType attribute) +
    • +
  • as_value() (coreblocks.params.instr.RISCVInstr method)
  • assertion() (transactron.lib.logging.HardwareLogger method)
    • @@ -1520,28 +1524,16 @@

    E

  • enable() (transactron.testing.testbenchio.TestbenchIO method)
    • -
  • encode() (coreblocks.params.instr.BTypeInstr static method) + + - + -