diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index f28866d37..7ed1f3446 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index a1ebb50d1..29caa6977 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree index ba52bbde7..8e77bbe0d 100644 Binary files a/.doctrees/current-graph.doctree and b/.doctrees/current-graph.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index 8c0d7d5df..e42a510ad 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/.doctrees/index.doctree b/.doctrees/index.doctree index 641c7e3ed..35e3f0c17 100644 Binary files a/.doctrees/index.doctree and b/.doctrees/index.doctree differ diff --git a/_sources/api.md.txt b/_sources/api.md.txt index 5daa246b7..226f38e51 100644 --- a/_sources/api.md.txt +++ b/_sources/api.md.txt @@ -2,5 +2,4 @@ ```{eval-rst} .. include:: modules-coreblocks.rst -.. include:: modules-transactron.rst ``` diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 967bda91c..ca41387b2 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -15,69 +15,69 @@ end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_request["request"] WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] + WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] Forwarder1_write["write"] Forwarder1_read["read"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] - Serializer_Serializer["Serializer"] - Serializer_Serializer1["Serializer"] + Serializer_serialize_in0["serialize_in0"] + Serializer_serialize_out0["serialize_out0"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_get_write_response["get_write_response"] + WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_request_read["request_read"] - WishboneMasterAdapter1_get_read_response["get_read_response"] subgraph Serializer1["bus_serializer Serializer"] - Serializer1_Serializer["Serializer"] - Serializer1_Serializer1["Serializer"] - Serializer1_Serializer2["Serializer"] - Serializer1_Serializer3["Serializer"] + Serializer1_serialize_out1["serialize_out1"] + Serializer1_serialize_in0["serialize_in0"] + Serializer1_serialize_in1["serialize_in1"] + Serializer1_serialize_out0["serialize_out0"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_read["read"] BasicFifo1_write["write"] + BasicFifo1_read["read"] end end end subgraph CoreFrontend["frontend CoreFrontend"] - CoreFrontend_target_pred_req["target_pred_req"] - CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] CoreFrontend_target_pred_resp["target_pred_resp"] + CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] + CoreFrontend_target_pred_req["target_pred_req"] CoreFrontend_stall["stall"] subgraph BasicFifo2["instr_buffer BasicFifo"] - BasicFifo2_read["read"] - BasicFifo2_write["write"] BasicFifo2_clear["clear"] + BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end end subgraph ICache["icache ICache"] - ICache_flush["flush"] - ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] ICache_ICache["ICache"] + ICache_flush["flush"] ICache_ICache1["ICache"] + ICache_issue_req["issue_req"] ICache_MemRead["MemRead"] + ICache_accept_res["accept_res"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -105,14 +105,14 @@ end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_read["read"] ArgumentsToResultsZipper_write_results["write_results"] - ArgumentsToResultsZipper_peek_arg["peek_arg"] ArgumentsToResultsZipper_write_args["write_args"] + ArgumentsToResultsZipper_peek_arg["peek_arg"] + ArgumentsToResultsZipper_read["read"] subgraph BasicFifo3["fifo BasicFifo"] - BasicFifo3_read["read"] BasicFifo3_write["write"] BasicFifo3_peek["peek"] + BasicFifo3_read["read"] end subgraph Forwarder3["forwarder Forwarder"] Forwarder3_read["read"] @@ -121,14 +121,14 @@ end end subgraph FetchUnit["fetch FetchUnit"] - FetchUnit_resume_from_unsafe["resume_from_unsafe"] + FetchUnit_Fetch_Stage2["Fetch_Stage2"] + FetchUnit_Fetch_Stage0["Fetch_Stage0"] + FetchUnit_resume_from_exception["resume_from_exception"] FetchUnit_Fetch_Stage1["Fetch_Stage1"] + FetchUnit_resume_from_unsafe["resume_from_unsafe"] FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] FetchUnit_stall_exception["stall_exception"] - FetchUnit_resume_from_exception["resume_from_exception"] - FetchUnit_Fetch_Stage2["Fetch_Stage2"] FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] - FetchUnit_Fetch_Stage0["Fetch_Stage0"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] end @@ -136,8 +136,8 @@ HwCounter5__incr["_incr"] end subgraph Serializer["serializer Serializer"] - Serializer_write["write"] Serializer_read["read"] + Serializer_write["write"] Serializer_clean["clean"] end subgraph ConnectTrans["serializer_connector ConnectTrans"] @@ -172,9 +172,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] - Pipe1_read["read"] - Pipe1_clean["clean"] Pipe1_write["write"] + Pipe1_clean["clean"] + Pipe1_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -184,8 +184,8 @@ end end subgraph BasicFifo5["free_rf_fifo BasicFifo"] - BasicFifo5_read["read"] BasicFifo5_write["write"] + BasicFifo5_read["read"] end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] @@ -195,11 +195,11 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] RegisterFile_write["write"] RegisterFile_read2["read2"] - RegisterFile_perf["perf"] RegisterFile_free["free"] + RegisterFile_read1["read1"] + RegisterFile_perf["perf"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer__stop["_stop"] TaggedLatencyMeasurer__start["_start"] @@ -207,8 +207,8 @@ HwExpHistogram1__add["_add"] end subgraph AsyncMemoryBank["slots AsyncMemoryBank"] - AsyncMemoryBank_AsyncMemoryBank["AsyncMemoryBank"] - AsyncMemoryBank_AsyncMemoryBank1["AsyncMemoryBank"] + AsyncMemoryBank_read0["read0"] + AsyncMemoryBank_write0["write0"] end end subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] @@ -216,15 +216,15 @@ end end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_retire["retire"] ReorderBuffer_perf["perf"] + ReorderBuffer_retire["retire"] ReorderBuffer_put["put"] - ReorderBuffer_peek["peek"] ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_peek["peek"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] - FIFOLatencyMeasurer1__start["_start"] FIFOLatencyMeasurer1__stop["_stop"] + FIFOLatencyMeasurer1__start["_start"] subgraph HwExpHistogram3["histogram HwExpHistogram"] HwExpHistogram3__add["_add"] end @@ -238,9 +238,9 @@ end end subgraph ExceptionInformationRegister["exception_information_register ExceptionInformationRegister"] + ExceptionInformationRegister_report["report"] ExceptionInformationRegister_clear["clear"] ExceptionInformationRegister_get["get"] - ExceptionInformationRegister_report["report"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] BasicFifo6_write["write"] BasicFifo6_read["read"] @@ -253,8 +253,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_read["read"] Forwarder4_write["write"] + Forwarder4_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans2["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -273,29 +273,29 @@ end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] RSFuncBlock_update["update"] + RSFuncBlock_get_result["get_result"] RSFuncBlock_insert["insert"] RSFuncBlock_select["select"] - RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] + RS_insert["insert"] RS_RS["RS"] - RS_RS1["RS"] RS_take["take"] + RS_update["update"] + RS_RS1["RS"] RS_RS2["RS"] - RS_insert["insert"] RS_RS3["RS"] - RS_select["select"] - RS_update["update"] RS_RS4["RS"] RS_perf["perf"] + RS_select["select"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__stop["_stop"] TaggedLatencyMeasurer1__start["_start"] + TaggedLatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_AsyncMemoryBank["AsyncMemoryBank"] - AsyncMemoryBank1_AsyncMemoryBank1["AsyncMemoryBank"] + AsyncMemoryBank1_read0["read0"] + AsyncMemoryBank1_write0["write0"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -303,14 +303,14 @@ end end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph TaggedCounter4["perf_instr TaggedCounter"] TaggedCounter4__incr["_incr"] end subgraph FIFO2["fifo FIFO"] - FIFO2_write["write"] FIFO2_read["read"] + FIFO2_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] @@ -320,19 +320,19 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO4["fifo_branch_resolved FIFO"] - FIFO4_read["read"] FIFO4_write["write"] + FIFO4_read["read"] end subgraph TaggedCounter5["perf_instr TaggedCounter"] TaggedCounter5__incr["_incr"] @@ -355,24 +355,24 @@ ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] - FIFO5_write["write"] FIFO5_read["read"] + FIFO5_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] + PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] + PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] - PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] - PrivilegedFuncUnit_issue["issue"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] - BasicFifo8_write["write"] BasicFifo8_read["read"] + BasicFifo8_write["write"] end subgraph TaggedCounter6["perf_instr TaggedCounter"] TaggedCounter6__incr["_incr"] @@ -384,8 +384,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_write["write"] Forwarder5_read["read"] + Forwarder5_write["write"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans5["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -409,13 +409,13 @@ subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] RSFuncBlock1_select["select"] RSFuncBlock1_get_result["get_result"] - RSFuncBlock1_insert["insert"] RSFuncBlock1_update["update"] + RSFuncBlock1_insert["insert"] subgraph FifoRS["rs FifoRS"] - FifoRS_perf["perf"] - FifoRS_update["update"] FifoRS_FifoRS["FifoRS"] FifoRS_take["take"] + FifoRS_perf["perf"] + FifoRS_update["update"] FifoRS_select["select"] FifoRS_insert["insert"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] @@ -425,8 +425,8 @@ HwExpHistogram7__add["_add"] end subgraph AsyncMemoryBank2["slots AsyncMemoryBank"] - AsyncMemoryBank2_AsyncMemoryBank["AsyncMemoryBank"] - AsyncMemoryBank2_AsyncMemoryBank1["AsyncMemoryBank"] + AsyncMemoryBank2_write0["write0"] + AsyncMemoryBank2_read0["read0"] end end subgraph HwExpHistogram8["perf_num_full HwExpHistogram"] @@ -434,30 +434,30 @@ end end subgraph LSUDummy["func_unit_0 LSUDummy"] + LSUDummy_accept_cond1["accept_cond1"] LSUDummy_accept["accept"] LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_accept_cond0["accept_cond0"] LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_LSUDummy3["LSUDummy"] - LSUDummy_accept_cond1["accept_cond1"] LSUDummy_issue["issue"] - LSUDummy_accept_cond0["accept_cond0"] subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond1["issue_cond1"] - LSURequester_issue_cond0["issue_cond0"] - LSURequester_accept["accept"] - LSURequester_accept_cond0["accept_cond0"] - LSURequester_issue_cond2["issue_cond2"] LSURequester_issue["issue"] LSURequester_accept_cond1["accept_cond1"] + LSURequester_issue_cond2["issue_cond2"] + LSURequester_issue_cond1["issue_cond1"] + LSURequester_accept_cond0["accept_cond0"] + LSURequester_accept["accept"] + LSURequester_issue_cond0["issue_cond0"] subgraph BasicFifo9["args_fifo BasicFifo"] - BasicFifo9_write["write"] BasicFifo9_read["read"] + BasicFifo9_write["write"] end end subgraph Forwarder6["requests Forwarder"] - Forwarder6_read["read"] Forwarder6_write["write"] + Forwarder6_read["read"] end subgraph FIFO6["results_noop FIFO"] FIFO6_read["read"] @@ -489,12 +489,12 @@ end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_update["update"] - CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_get_result["get_result"] CSRUnit_insert["insert"] - CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_select["select"] - CSRUnit_get_result["get_result"] + CSRUnit_update["update"] + CSRUnit_fetch_resume["fetch_resume"] end end subgraph ResultAnnouncement["announcement ResultAnnouncement"] @@ -547,17 +547,17 @@ end end subgraph AliasedCSR["mstatus AliasedCSR"] - AliasedCSR__fu_write["_fu_write"] AliasedCSR__fu_read["_fu_read"] + AliasedCSR__fu_write["_fu_write"] end subgraph AliasedCSR1["mstatush AliasedCSR"] AliasedCSR1__fu_read["_fu_read"] AliasedCSR1__fu_write["_fu_write"] end subgraph CSRRegister6["mcause CSRRegister"] - CSRRegister6__internal_fu_write["_internal_fu_write"] - CSRRegister6__internal_fu_read["_internal_fu_read"] CSRRegister6_write["write"] + CSRRegister6__internal_fu_read["_internal_fu_read"] + CSRRegister6__internal_fu_write["_internal_fu_write"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -569,9 +569,9 @@ end end subgraph CSRRegister7["mtvec CSRRegister"] + CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7_read["read"] CSRRegister7__internal_fu_read["_internal_fu_read"] - CSRRegister7__internal_fu_write["_internal_fu_write"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] end @@ -583,10 +583,10 @@ end end subgraph CSRRegister8["mepc CSRRegister"] + CSRRegister8__internal_fu_write["_internal_fu_write"] + CSRRegister8_write["write"] CSRRegister8__internal_fu_read["_internal_fu_read"] CSRRegister8_read["read"] - CSRRegister8_write["write"] - CSRRegister8__internal_fu_write["_internal_fu_write"] subgraph MethodMap16["fu_write_map MethodMap"] MethodMap16_method["method"] end @@ -598,9 +598,9 @@ end end subgraph CSRRegister9["mtval CSRRegister"] - CSRRegister9__internal_fu_read["_internal_fu_read"] CSRRegister9__internal_fu_write["_internal_fu_write"] CSRRegister9_write["write"] + CSRRegister9__internal_fu_read["_internal_fu_read"] subgraph MethodMap18["fu_write_map MethodMap"] MethodMap18_method["method"] end @@ -612,8 +612,8 @@ end end subgraph CSRRegister10["misa CSRRegister"] - CSRRegister10__internal_fu_write["_internal_fu_write"] CSRRegister10__internal_fu_read["_internal_fu_read"] + CSRRegister10__internal_fu_write["_internal_fu_write"] subgraph MethodMap20["fu_write_map MethodMap"] MethodMap20_method["method"] end @@ -625,13 +625,13 @@ end end subgraph CSRRegister11["priv_mode CSRRegister"] - CSRRegister11_write["write"] CSRRegister11_read["read"] + CSRRegister11_write["write"] end subgraph CSRRegister12["mstatus_mie CSRRegister"] - CSRRegister12_read["read"] - CSRRegister12__internal_fu_write["_internal_fu_write"] CSRRegister12_write["write"] + CSRRegister12__internal_fu_write["_internal_fu_write"] + CSRRegister12_read["read"] CSRRegister12__internal_fu_read["_internal_fu_read"] subgraph MethodMap24["fu_write_map MethodMap"] MethodMap24_method["method"] @@ -644,10 +644,10 @@ end end subgraph CSRRegister13["mstatus_mpie CSRRegister"] - CSRRegister13__internal_fu_read["_internal_fu_read"] - CSRRegister13_write["write"] CSRRegister13__internal_fu_write["_internal_fu_write"] CSRRegister13_read["read"] + CSRRegister13__internal_fu_read["_internal_fu_read"] + CSRRegister13_write["write"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -659,10 +659,10 @@ end end subgraph CSRRegister14["mstatus_mpp CSRRegister"] + CSRRegister14_write["write"] CSRRegister14__internal_fu_read["_internal_fu_read"] CSRRegister14_read["read"] CSRRegister14__internal_fu_write["_internal_fu_write"] - CSRRegister14_write["write"] subgraph MethodMap28["fu_write_map MethodMap"] MethodMap28_method["method"] end @@ -674,9 +674,9 @@ end end subgraph CSRRegister15["mstatus_mprv CSRRegister"] - CSRRegister15__internal_fu_write["_internal_fu_write"] - CSRRegister15_write["write"] CSRRegister15__internal_fu_read["_internal_fu_read"] + CSRRegister15_write["write"] + CSRRegister15__internal_fu_write["_internal_fu_write"] subgraph MethodMap30["fu_write_map MethodMap"] MethodMap30_method["method"] end @@ -688,8 +688,8 @@ end end subgraph CSRRegister16["mstatus_tw CSRRegister"] - CSRRegister16__internal_fu_write["_internal_fu_write"] CSRRegister16__internal_fu_read["_internal_fu_read"] + CSRRegister16__internal_fu_write["_internal_fu_write"] CSRRegister16_read["read"] subgraph MethodMap32["fu_write_map MethodMap"] MethodMap32_method["method"] @@ -705,17 +705,17 @@ subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister17["register_low CSRRegister"] - CSRRegister17_write["write"] - CSRRegister17__internal_fu_read["_internal_fu_read"] CSRRegister17_read["read"] + CSRRegister17__internal_fu_read["_internal_fu_read"] + CSRRegister17_write["write"] subgraph MethodMap35["fu_read_map MethodMap"] MethodMap35_method["method"] end end subgraph CSRRegister18["register_high CSRRegister"] - CSRRegister18_write["write"] - CSRRegister18_read["read"] CSRRegister18__internal_fu_read["_internal_fu_read"] + CSRRegister18_read["read"] + CSRRegister18_write["write"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] end @@ -724,16 +724,16 @@ subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister19["register_low CSRRegister"] - CSRRegister19__internal_fu_read["_internal_fu_read"] CSRRegister19_read["read"] + CSRRegister19__internal_fu_read["_internal_fu_read"] CSRRegister19_write["write"] subgraph MethodMap39["fu_read_map MethodMap"] MethodMap39_method["method"] end end subgraph CSRRegister20["register_high CSRRegister"] - CSRRegister20_read["read"] CSRRegister20__internal_fu_read["_internal_fu_read"] + CSRRegister20_read["read"] CSRRegister20_write["write"] subgraph MethodMap41["fu_read_map MethodMap"] MethodMap41_method["method"] @@ -742,16 +742,16 @@ end end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] + InternalInterruptController_interrupt_cause["interrupt_cause"] InternalInterruptController_InternalInterruptController["InternalInterruptController"] - InternalInterruptController_entry["entry"] InternalInterruptController_InternalInterruptController1["InternalInterruptController"] - InternalInterruptController_interrupt_cause["interrupt_cause"] - InternalInterruptController_InternalInterruptController2["InternalInterruptController"] InternalInterruptController_mret["mret"] + InternalInterruptController_InternalInterruptController2["InternalInterruptController"] + InternalInterruptController_entry["entry"] subgraph CSRRegister21["mie CSRRegister"] + CSRRegister21_read["read"] CSRRegister21__internal_fu_read["_internal_fu_read"] CSRRegister21__internal_fu_write["_internal_fu_write"] - CSRRegister21_read["read"] subgraph MethodMap42["fu_write_map MethodMap"] MethodMap42_method["method"] end @@ -764,10 +764,10 @@ end subgraph CSRRegister22["mip CSRRegister"] CSRRegister22__internal_fu_write["_internal_fu_write"] - CSRRegister22_read["read"] CSRRegister22_read_comb["read_comb"] - CSRRegister22_write["write"] CSRRegister22__internal_fu_read["_internal_fu_read"] + CSRRegister22_read["read"] + CSRRegister22_write["write"] subgraph MethodMap44["fu_write_map MethodMap"] MethodMap44_method["method"] end @@ -802,15 +802,15 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO11["rs_select_out_buf FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -825,8 +825,8 @@ subgraph Collector3["FetchResumeKey_unifier Collector"] Collector3_method["method"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_write["write"] Forwarder8_read["read"] + Forwarder8_write["write"] end subgraph ManyToOneConnectTrans3["connect ManyToOneConnectTrans"] subgraph ConnectTrans11["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -842,19 +842,19 @@ ConnectTrans13_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_core_state["core_state"] + Retirement_precommit["precommit"] Retirement_Retirement1["Retirement"] Retirement_Retirement2["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement3["Retirement"] - Retirement_precommit["precommit"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister23["register_low CSRRegister"] - CSRRegister23__internal_fu_read["_internal_fu_read"] CSRRegister23_read["read"] + CSRRegister23__internal_fu_read["_internal_fu_read"] CSRRegister23_write["write"] subgraph MethodMap47["fu_read_map MethodMap"] MethodMap47_method["method"] @@ -862,8 +862,8 @@ end subgraph CSRRegister24["register_high CSRRegister"] CSRRegister24_read["read"] - CSRRegister24__internal_fu_read["_internal_fu_read"] CSRRegister24_write["write"] + CSRRegister24__internal_fu_read["_internal_fu_read"] subgraph MethodMap49["fu_read_map MethodMap"] MethodMap49_method["method"] end @@ -879,44 +879,44 @@ HwExpHistogram9__add["_add"] end subgraph FIFO12["fifo FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end end end end end subgraph TransactionManager["transaction_manager TransactionManager"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] - TransactionManager_accept_cond0_ConnectTrans_accept_cond1["accept_cond0_ConnectTrans_accept_cond1"] - TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] - TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit["PrivilegedFuncUnit_cond1_PrivilegedFuncUnit"] TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0["Fetch_Stage2_Fetch_Stage2_cond0"] - TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"] - TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit["PrivilegedFuncUnit_cond3_PrivilegedFuncUnit"] TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2["Fetch_Stage2_cond0_Fetch_Stage2"] + TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit["PrivilegedFuncUnit_cond0_PrivilegedFuncUnit"] + TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2["Fetch_Stage2_cond1_Fetch_Stage2"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_PrivilegedFuncUnit_cond0"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] + TransactionManager_accept_cond1_accept_cond0_ConnectTrans["accept_cond1_accept_cond0_ConnectTrans"] + TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit["PrivilegedFuncUnit_cond2_PrivilegedFuncUnit"] + TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] end end Core_InitFreeRFFifo --> BasicFifo5_write - Retirement_Retirement1 --> BasicFifo5_write + Retirement_Retirement3 --> BasicFifo5_write TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write - TransactionManager_Retirement_cond0_Retirement --> BasicFifo5_write + TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_serialize_in0 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - Serializer_Serializer1 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + Serializer_serialize_out0 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 @@ -966,56 +966,56 @@ GenericCSRRegisters_GenericCSRRegisters --> CSRRegister19_write CSRRegister20_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister20_write - CSRRegister12_read --> InternalInterruptController_InternalInterruptController2 CSRRegister12_read --> InternalInterruptController_InternalInterruptController - CSRRegister11_read --> InternalInterruptController_InternalInterruptController2 + CSRRegister12_read --> InternalInterruptController_InternalInterruptController1 CSRRegister11_read --> InternalInterruptController_InternalInterruptController + CSRRegister11_read --> InternalInterruptController_InternalInterruptController1 CSRRegister11_read --> WakeupSelect3_WakeupSelect CSRRegister11_read --> CSRUnit_CSRUnit - CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - CSRRegister21_read --> InternalInterruptController_InternalInterruptController2 - CSRRegister22_read --> InternalInterruptController_InternalInterruptController2 - CSRRegister22_read_comb --> InternalInterruptController_InternalInterruptController1 - InternalInterruptController_InternalInterruptController1 --> CSRRegister22_write - InternalInterruptController_InternalInterruptController --> CSRRegister12_write - InternalInterruptController_InternalInterruptController --> CSRRegister13_write - InternalInterruptController_InternalInterruptController --> CSRRegister14_write - InternalInterruptController_InternalInterruptController --> CSRRegister11_write - CSRRegister13_read --> InternalInterruptController_InternalInterruptController - CSRRegister14_read --> InternalInterruptController_InternalInterruptController - InternalInterruptController_InternalInterruptController --> CSRRegister15_write + CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit + CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit + CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit + CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit + CSRRegister21_read --> InternalInterruptController_InternalInterruptController + CSRRegister22_read --> InternalInterruptController_InternalInterruptController + CSRRegister22_read_comb --> InternalInterruptController_InternalInterruptController2 + InternalInterruptController_InternalInterruptController2 --> CSRRegister22_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister12_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister13_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister14_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister11_write + CSRRegister13_read --> InternalInterruptController_InternalInterruptController1 + CSRRegister14_read --> InternalInterruptController_InternalInterruptController1 + InternalInterruptController_InternalInterruptController1 --> CSRRegister15_write MethodProduct1_method --> RegAllocation_RegAllocation Pipe1_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation <--> CoreInstructionCounter_increment BasicFifo5_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO9_write + FIFO10_read --> RSSelection_RSSelection FIFO10_read --> RSSelection_RSSelection1 FIFO10_read --> RSSelection_RSSelection2 - FIFO10_read --> RSSelection_RSSelection - RSFuncBlock_select --> RSSelection_RSSelection1 - RS_select --> RSSelection_RSSelection1 + RSFuncBlock_select --> RSSelection_RSSelection + RS_select --> RSSelection_RSSelection + RSSelection_RSSelection --> FIFO11_write RSSelection_RSSelection1 --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write - RSSelection_RSSelection --> FIFO11_write - RSFuncBlock1_select --> RSSelection_RSSelection2 - FifoRS_select --> RSSelection_RSSelection2 - RSSelection_RSSelection <--> CSRUnit_select + RSFuncBlock1_select --> RSSelection_RSSelection1 + FifoRS_select --> RSSelection_RSSelection1 + RSSelection_RSSelection2 <--> CSRUnit_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion Retirement_core_state --> RSInsertion_RSInsertion - Retirement_core_state --> LSUDummy_LSUDummy + Retirement_core_state --> LSUDummy_LSUDummy2 RSInsertion_RSInsertion --> RSFuncBlock_insert RSInsertion_RSInsertion --> RS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer1__start - RSInsertion_RSInsertion --> AsyncMemoryBank1_AsyncMemoryBank1 + RSInsertion_RSInsertion --> AsyncMemoryBank1_write0 RSInsertion_RSInsertion --> RSFuncBlock1_insert RSInsertion_RSInsertion --> FifoRS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer2__start - RSInsertion_RSInsertion --> AsyncMemoryBank2_AsyncMemoryBank + RSInsertion_RSInsertion --> AsyncMemoryBank2_write0 RSInsertion_RSInsertion --> CSRUnit_insert BasicFifo6_read --> ConnectTrans1_ConnectTrans ConnectTrans1_ConnectTrans --> ExceptionInformationRegister_report @@ -1037,7 +1037,7 @@ ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done ResultAnnouncement_ResultAnnouncement --> RegisterFile_write ResultAnnouncement_ResultAnnouncement --> TaggedLatencyMeasurer__start - ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_AsyncMemoryBank + ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_write0 ResultAnnouncement_ResultAnnouncement --> MethodProduct_method ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update @@ -1045,7 +1045,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add - RS_RS2 --> WakeupSelect_WakeupSelect + RS_RS3 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -1056,11 +1056,11 @@ WakeupSelect2_WakeupSelect --> TaggedLatencyMeasurer1__stop WakeupSelect3_WakeupSelect --> TaggedLatencyMeasurer1__stop WakeupSelect4_WakeupSelect --> TaggedLatencyMeasurer1__stop - AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect_WakeupSelect - AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect1_WakeupSelect - AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect2_WakeupSelect - AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect3_WakeupSelect - AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect4_WakeupSelect + AsyncMemoryBank1_read0 --> WakeupSelect_WakeupSelect + AsyncMemoryBank1_read0 --> WakeupSelect1_WakeupSelect + AsyncMemoryBank1_read0 --> WakeupSelect2_WakeupSelect + AsyncMemoryBank1_read0 --> WakeupSelect3_WakeupSelect + AsyncMemoryBank1_read0 --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> HwExpHistogram5__add WakeupSelect1_WakeupSelect --> HwExpHistogram5__add WakeupSelect2_WakeupSelect --> HwExpHistogram5__add @@ -1069,25 +1069,25 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter4__incr WakeupSelect_WakeupSelect --> FIFO2_write - RS_RS1 --> WakeupSelect1_WakeupSelect + RS_RS4 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write - RS_RS --> WakeupSelect2_WakeupSelect + RS_RS1 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write WakeupSelect2_WakeupSelect --> TaggedCounter5__incr - RS_RS4 --> WakeupSelect3_WakeupSelect + RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> BasicFifo6_write ConnectTrans7_ConnectTrans --> BasicFifo6_write ConnectTrans9_ConnectTrans --> BasicFifo6_write ConnectTrans4_ConnectTrans --> BasicFifo6_write - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo6_write - TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> BasicFifo6_write TransactionManager_accept_cond1_ConnectTrans --> BasicFifo6_write + TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> BasicFifo6_write + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write - RS_RS3 --> WakeupSelect4_WakeupSelect + RS_RS2 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans5_ConnectTrans --> Forwarder5_write ConnectTrans6_ConnectTrans --> Forwarder5_write @@ -1110,40 +1110,40 @@ CSRRegister8_read --> ConnectTrans9_ConnectTrans ConnectTrans9_ConnectTrans --> BasicFifo8_write FifoRS_perf --> HwExpHistogram8__add - Forwarder6_read --> LSUDummy_LSUDummy2 + Forwarder6_read --> LSUDummy_LSUDummy Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond1 - Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 - LSUDummy_LSUDummy2 --> FIFO6_write + Forwarder6_read --> TransactionManager_issue_cond0_LSUDummy + LSUDummy_LSUDummy --> FIFO6_write WakeupSelect5_WakeupSelect --> FIFO6_write TransactionManager_LSUDummy_issue_cond2 --> FIFO6_write TransactionManager_LSUDummy_issue_cond1 --> FIFO6_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO6_write - LSUDummy_LSUDummy2 --> FIFO8_write + TransactionManager_issue_cond0_LSUDummy --> FIFO6_write + LSUDummy_LSUDummy --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write TransactionManager_LSUDummy_issue_cond1 --> FIFO8_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write + TransactionManager_issue_cond0_LSUDummy --> FIFO8_write LSUDummy_LSUDummy1 --> Retirement_precommit CSRUnit_CSRUnit --> Retirement_precommit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> Retirement_precommit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> Retirement_precommit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> Retirement_precommit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> Retirement_precommit + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> Retirement_precommit + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit --> Retirement_precommit + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit --> Retirement_precommit + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit --> Retirement_precommit ReorderBuffer_peek --> LSUDummy_LSUDummy1 ReorderBuffer_peek --> CSRUnit_CSRUnit + ReorderBuffer_peek --> Retirement_Retirement2 ReorderBuffer_peek --> Retirement_Retirement3 - ReorderBuffer_peek --> Retirement_Retirement1 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop - AsyncMemoryBank2_AsyncMemoryBank1 --> WakeupSelect5_WakeupSelect + AsyncMemoryBank2_read0 --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> HwExpHistogram7__add WakeupSelect5_WakeupSelect --> LSUDummy_issue WakeupSelect5_WakeupSelect --> Forwarder6_write @@ -1248,172 +1248,172 @@ Collector2_method --> ConnectTrans3_ConnectTrans Forwarder7_read --> ConnectTrans3_ConnectTrans CSRUnit_get_result --> ConnectTrans4_ConnectTrans - ExceptionInformationRegister_get --> Retirement_Retirement3 + ExceptionInformationRegister_get --> Retirement_Retirement2 ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond1 - ExceptionInformationRegister_get --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement1 <--> ReorderBuffer_retire + ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement3 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire - TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire - Retirement_Retirement1 <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire + Retirement_Retirement3 <--> FIFOLatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop - TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer1__stop - FIFO1_read --> Retirement_Retirement1 + TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop + FIFO1_read --> Retirement_Retirement3 FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 - FIFO1_read --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement1 --> HwExpHistogram3__add + FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement3 --> HwExpHistogram3__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram3__add - CoreInstructionCounter_decrement --> Retirement_Retirement1 + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add + CoreInstructionCounter_decrement --> Retirement_Retirement3 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement - RRAT_peek --> Retirement_Retirement1 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 + RRAT_peek --> Retirement_Retirement3 RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement1 --> RegisterFile_free + Retirement_Retirement3 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free - TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free - Retirement_Retirement1 --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free + Retirement_Retirement3 --> TaggedLatencyMeasurer__stop TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop - TransactionManager_Retirement_cond0_Retirement --> TaggedLatencyMeasurer__stop - AsyncMemoryBank_AsyncMemoryBank1 --> Retirement_Retirement1 - AsyncMemoryBank_AsyncMemoryBank1 --> TransactionManager_Retirement_Retirement_cond1 - AsyncMemoryBank_AsyncMemoryBank1 --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement1 --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop + AsyncMemoryBank_read0 --> Retirement_Retirement3 + AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond1 + AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement3 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add - Retirement_Retirement1 --> FRAT_rename + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add + Retirement_Retirement3 --> FRAT_rename TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename - TransactionManager_ROBAllocation_Renaming --> FRAT_rename - Retirement_Retirement2 <--> FIFOLatencyMeasurer2__stop - FIFO12_read --> Retirement_Retirement2 - Retirement_Retirement2 --> HwExpHistogram9__add - CSRRegister7_read --> Retirement_Retirement2 - Retirement_Retirement2 --> FetchUnit_resume_from_exception - Retirement_Retirement2 <--> ExceptionInformationRegister_clear - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 + TransactionManager_Renaming_ROBAllocation --> FRAT_rename + Retirement_Retirement1 <--> FIFOLatencyMeasurer2__stop + FIFO12_read --> Retirement_Retirement1 + Retirement_Retirement1 --> HwExpHistogram9__add + CSRRegister7_read --> Retirement_Retirement1 + Retirement_Retirement1 --> FetchUnit_resume_from_exception + Retirement_Retirement1 <--> ExceptionInformationRegister_clear + TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 + FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans + FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans + TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans + TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> ConnectTrans10_ConnectTrans + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans + TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write + TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> Forwarder7_write + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write + LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans + LSUDummy_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond0 + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> HwCounter5__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Serializer_write + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> Semaphore_release + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> Semaphore_release TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release - Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 + Pipe_read --> TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Predecoder_predecode + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Predecoder_predecode TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> PredictionChecker_check + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> PredictionChecker_check TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter1__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter1__incr TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter2__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter2__incr TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter3__incr TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write - TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy3 - TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy3 - TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy3 - TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond2 --> BasicFifo9_write - TransactionManager_LSUDummy_issue_cond1 --> BasicFifo9_write - TransactionManager_LSUDummy_issue_cond0 --> BasicFifo9_write - TransactionManager_LSUDummy_issue_cond2 --> FIFO7_write - TransactionManager_LSUDummy_issue_cond1 --> FIFO7_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO7_write - TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr - CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 - TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - BasicFifo9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - BasicFifo9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - FIFO7_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - FIFO7_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write - TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> Forwarder7_write - TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write - LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - Serializer1_Serializer3 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> ICache_flush + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit --> TaggedCounter6__incr + CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit + CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit + CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit + CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start - TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer2__start + TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write - TransactionManager_Retirement_cond0_Retirement --> FIFO12_write + TransactionManager_Retirement_Retirement_cond0 --> FIFO12_write InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 - InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond0_Retirement + InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister6_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister9_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister9_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister9_write TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry - TransactionManager_Retirement_cond0_Retirement <--> InternalInterruptController_entry + TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> InternalInterruptController_mret + TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + Serializer1_serialize_out0 --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + BasicFifo1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + WishboneMaster1_result --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + Forwarder1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 + LSURequester_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + BasicFifo9_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + FIFO7_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy3 + TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy3 + TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy3 + TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue + TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond2 --> BasicFifo9_write + TransactionManager_LSUDummy_issue_cond1 --> BasicFifo9_write + TransactionManager_issue_cond0_LSUDummy --> BasicFifo9_write + TransactionManager_LSUDummy_issue_cond2 --> FIFO7_write + TransactionManager_LSUDummy_issue_cond1 --> FIFO7_write + TransactionManager_issue_cond0_LSUDummy --> FIFO7_write + TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit + TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment + CSRRegister23_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister23_write + CSRRegister24_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister24_write + TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read - TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer + TransactionManager_LSUDummy_issue_cond1 --> Serializer1_serialize_in0 TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write + TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request - TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request - TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - Serializer1_Serializer2 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 - FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans - FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 - TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_cond0_Retirement --> RRAT_commit - TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment - CSRRegister23_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister23_write - CSRRegister24_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister24_write - TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr - TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation - Connect_read --> TransactionManager_ROBAllocation_Renaming - TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put - TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start - TransactionManager_ROBAllocation_Renaming --> FIFO1_write - TransactionManager_ROBAllocation_Renaming --> FIFO10_write - TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming - FIFO9_read --> TransactionManager_ROBAllocation_Renaming - TransactionManager_ROBAllocation_Renaming --> Connect_write + TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request + TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 + TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write + TransactionManager_issue_cond0_LSUDummy --> Serializer1_serialize_in1 + TransactionManager_Renaming_ROBAllocation <--> Renaming_Renaming + FIFO9_read --> TransactionManager_Renaming_ROBAllocation + TransactionManager_Renaming_ROBAllocation --> Connect_write + TransactionManager_Renaming_ROBAllocation <--> ROBAllocation_ROBAllocation + Connect_read --> TransactionManager_Renaming_ROBAllocation + TransactionManager_Renaming_ROBAllocation --> ReorderBuffer_put + TransactionManager_Renaming_ROBAllocation <--> FIFOLatencyMeasurer1__start + TransactionManager_Renaming_ROBAllocation --> FIFO1_write + TransactionManager_Renaming_ROBAllocation --> FIFO10_write + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + Serializer1_serialize_out1 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 diff --git a/_sources/index.md.txt b/_sources/index.md.txt index 0e16a25ec..6a9b5afba 100644 --- a/_sources/index.md.txt +++ b/_sources/index.md.txt @@ -8,7 +8,6 @@ maxdepth: 3 home.md assumptions.md development-environment.md -transactions.md scheduler/overview.md shared-structs/implementation/rs-impl.md shared-structs/rs.md diff --git a/api.html b/api.html index 5cff881c2..f2c90a4bd 100644 --- a/api.html +++ b/api.html @@ -44,7 +44,6 @@
© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/assumptions.html b/assumptions.html index 77d546916..e980f089f 100644 --- a/assumptions.html +++ b/assumptions.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/auto_graph.html b/auto_graph.html index 6434f3c18..c44a8261c 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -42,7 +42,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.arch.html b/coreblocks.arch.html index f6e002d8c..095899b30 100644 --- a/coreblocks.arch.html +++ b/coreblocks.arch.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.backend.html b/coreblocks.backend.html index ac88c2a0f..49dc411cd 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.cache.html b/coreblocks.cache.html index 5fecc6e23..9e19fd75c 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index f1e6cd45a..a9cd039d1 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index 11434cefd..f7ff41c9f 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index cf96c3dbb..4e4a88415 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 60b909fa9..617088b61 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.func_blocks.fu.fpu.html b/coreblocks.func_blocks.fu.fpu.html index 3e145fe1b..63b54852d 100644 --- a/coreblocks.func_blocks.fu.fpu.html +++ b/coreblocks.func_blocks.fu.fpu.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index 65921824f..5a870be6c 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.func_blocks.fu.lsu.html b/coreblocks.func_blocks.fu.lsu.html index 7f7fe558f..7e1f90142 100644 --- a/coreblocks.func_blocks.fu.lsu.html +++ b/coreblocks.func_blocks.fu.lsu.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index 9edecae88..6df061f4a 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index 0b7ba6f76..3e75912ba 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index d432e5f39..4959c233d 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -44,7 +44,6 @@Protocol
Protocol
© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.html b/coreblocks.html index 58c9e48b8..220265b8c 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.params.html b/coreblocks.params.html index 990bc35d0..f7fc26867 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -44,7 +44,6 @@Bases: DependentCache
Bases: DependentCache
© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index eecc528d0..e821317a7 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html index 8906eda1e..9acc14c02 100644 --- a/coreblocks.priv.csr.html +++ b/coreblocks.priv.csr.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.priv.html b/coreblocks.priv.html index 477b38316..478697bc7 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index 94a7e7719..d1f9ba33e 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 85d65f724..8a4799307 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -20,7 +20,6 @@ - @@ -44,7 +43,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/development-environment.html b/development-environment.html index 4310ea2f8..5211f570a 100644 --- a/development-environment.html +++ b/development-environment.html @@ -20,7 +20,7 @@ - + @@ -55,7 +55,6 @@ -© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
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+ - | -
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© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/index.html b/index.html index 801b74ac2..1f68555fc 100644 --- a/index.html +++ b/index.html @@ -43,7 +43,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html index 8e7824034..06c372bc7 100644 --- a/miscellany/exceptions-summary.html +++ b/miscellany/exceptions-summary.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/modules-coreblocks.html b/modules-coreblocks.html index c6760c289..f0c0fa118 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -42,7 +42,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/objects.inv b/objects.inv index 6aea754ba..6545ef748 100644 Binary files a/objects.inv and b/objects.inv differ diff --git a/problem-checklist.html b/problem-checklist.html index cd12652d6..13c5da4b0 100644 --- a/problem-checklist.html +++ b/problem-checklist.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/py-modindex.html b/py-modindex.html index 830d6b8d5..d0773e527 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -45,7 +45,6 @@
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- transactron.testing.tick_count | - |
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- transactron.tracing | - |
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- transactron.utils | - |
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- transactron.utils.amaranth_ext | - |
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- transactron.utils.amaranth_ext.coding | - |
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- transactron.utils.amaranth_ext.functions | - |
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- transactron.utils.dependencies | - |
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- transactron.utils.gen | - |
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- transactron.utils.idgen | - |
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- transactron.utils.transactron_helpers | - |
© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/search.html b/search.html index 1b5f3fecf..7a056ff9f 100644 --- a/search.html +++ b/search.html @@ -45,7 +45,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
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diff --git a/shared-structs/rs.html b/shared-structs/rs.html index 02bc96321..640cfe239 100644 --- a/shared-structs/rs.html +++ b/shared-structs/rs.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.
diff --git a/synthesis/synthesis.html b/synthesis/synthesis.html index e38c7175e..d37cba67b 100644 --- a/synthesis/synthesis.html +++ b/synthesis/synthesis.html @@ -44,7 +44,6 @@© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.