diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index f28866d37..7ed1f3446 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index a1ebb50d1..29caa6977 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree index ba52bbde7..8e77bbe0d 100644 Binary files a/.doctrees/current-graph.doctree and b/.doctrees/current-graph.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index 8c0d7d5df..e42a510ad 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/.doctrees/index.doctree b/.doctrees/index.doctree index 641c7e3ed..35e3f0c17 100644 Binary files a/.doctrees/index.doctree and b/.doctrees/index.doctree differ diff --git a/_sources/api.md.txt b/_sources/api.md.txt index 5daa246b7..226f38e51 100644 --- a/_sources/api.md.txt +++ b/_sources/api.md.txt @@ -2,5 +2,4 @@ ```{eval-rst} .. include:: modules-coreblocks.rst -.. include:: modules-transactron.rst ``` diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 967bda91c..ca41387b2 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -15,69 +15,69 @@ end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_request["request"] WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] + WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] Forwarder1_write["write"] Forwarder1_read["read"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] - Serializer_Serializer["Serializer"] - Serializer_Serializer1["Serializer"] + Serializer_serialize_in0["serialize_in0"] + Serializer_serialize_out0["serialize_out0"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_get_write_response["get_write_response"] + WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_request_read["request_read"] - WishboneMasterAdapter1_get_read_response["get_read_response"] subgraph Serializer1["bus_serializer Serializer"] - Serializer1_Serializer["Serializer"] - Serializer1_Serializer1["Serializer"] - Serializer1_Serializer2["Serializer"] - Serializer1_Serializer3["Serializer"] + Serializer1_serialize_out1["serialize_out1"] + Serializer1_serialize_in0["serialize_in0"] + Serializer1_serialize_in1["serialize_in1"] + Serializer1_serialize_out0["serialize_out0"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_read["read"] BasicFifo1_write["write"] + BasicFifo1_read["read"] end end end subgraph CoreFrontend["frontend CoreFrontend"] - CoreFrontend_target_pred_req["target_pred_req"] - CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] CoreFrontend_target_pred_resp["target_pred_resp"] + CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] + CoreFrontend_target_pred_req["target_pred_req"] CoreFrontend_stall["stall"] subgraph BasicFifo2["instr_buffer BasicFifo"] - BasicFifo2_read["read"] - BasicFifo2_write["write"] BasicFifo2_clear["clear"] + BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end end subgraph ICache["icache ICache"] - ICache_flush["flush"] - ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] ICache_ICache["ICache"] + ICache_flush["flush"] ICache_ICache1["ICache"] + ICache_issue_req["issue_req"] ICache_MemRead["MemRead"] + ICache_accept_res["accept_res"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -105,14 +105,14 @@ end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_read["read"] ArgumentsToResultsZipper_write_results["write_results"] - ArgumentsToResultsZipper_peek_arg["peek_arg"] ArgumentsToResultsZipper_write_args["write_args"] + ArgumentsToResultsZipper_peek_arg["peek_arg"] + ArgumentsToResultsZipper_read["read"] subgraph BasicFifo3["fifo BasicFifo"] - BasicFifo3_read["read"] BasicFifo3_write["write"] BasicFifo3_peek["peek"] + BasicFifo3_read["read"] end subgraph Forwarder3["forwarder Forwarder"] Forwarder3_read["read"] @@ -121,14 +121,14 @@ end end subgraph FetchUnit["fetch FetchUnit"] - FetchUnit_resume_from_unsafe["resume_from_unsafe"] + FetchUnit_Fetch_Stage2["Fetch_Stage2"] + FetchUnit_Fetch_Stage0["Fetch_Stage0"] + FetchUnit_resume_from_exception["resume_from_exception"] FetchUnit_Fetch_Stage1["Fetch_Stage1"] + FetchUnit_resume_from_unsafe["resume_from_unsafe"] FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] FetchUnit_stall_exception["stall_exception"] - FetchUnit_resume_from_exception["resume_from_exception"] - FetchUnit_Fetch_Stage2["Fetch_Stage2"] FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] - FetchUnit_Fetch_Stage0["Fetch_Stage0"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] end @@ -136,8 +136,8 @@ HwCounter5__incr["_incr"] end subgraph Serializer["serializer Serializer"] - Serializer_write["write"] Serializer_read["read"] + Serializer_write["write"] Serializer_clean["clean"] end subgraph ConnectTrans["serializer_connector ConnectTrans"] @@ -172,9 +172,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] - Pipe1_read["read"] - Pipe1_clean["clean"] Pipe1_write["write"] + Pipe1_clean["clean"] + Pipe1_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -184,8 +184,8 @@ end end subgraph BasicFifo5["free_rf_fifo BasicFifo"] - BasicFifo5_read["read"] BasicFifo5_write["write"] + BasicFifo5_read["read"] end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] @@ -195,11 +195,11 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] RegisterFile_write["write"] RegisterFile_read2["read2"] - RegisterFile_perf["perf"] RegisterFile_free["free"] + RegisterFile_read1["read1"] + RegisterFile_perf["perf"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer__stop["_stop"] TaggedLatencyMeasurer__start["_start"] @@ -207,8 +207,8 @@ HwExpHistogram1__add["_add"] end subgraph AsyncMemoryBank["slots AsyncMemoryBank"] - AsyncMemoryBank_AsyncMemoryBank["AsyncMemoryBank"] - AsyncMemoryBank_AsyncMemoryBank1["AsyncMemoryBank"] + AsyncMemoryBank_read0["read0"] + AsyncMemoryBank_write0["write0"] end end subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] @@ -216,15 +216,15 @@ end end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_retire["retire"] ReorderBuffer_perf["perf"] + ReorderBuffer_retire["retire"] ReorderBuffer_put["put"] - ReorderBuffer_peek["peek"] ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_peek["peek"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] - FIFOLatencyMeasurer1__start["_start"] FIFOLatencyMeasurer1__stop["_stop"] + FIFOLatencyMeasurer1__start["_start"] subgraph HwExpHistogram3["histogram HwExpHistogram"] HwExpHistogram3__add["_add"] end @@ -238,9 +238,9 @@ end end subgraph ExceptionInformationRegister["exception_information_register ExceptionInformationRegister"] + ExceptionInformationRegister_report["report"] ExceptionInformationRegister_clear["clear"] ExceptionInformationRegister_get["get"] - ExceptionInformationRegister_report["report"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] BasicFifo6_write["write"] BasicFifo6_read["read"] @@ -253,8 +253,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_read["read"] Forwarder4_write["write"] + Forwarder4_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans2["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -273,29 +273,29 @@ end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] RSFuncBlock_update["update"] + RSFuncBlock_get_result["get_result"] RSFuncBlock_insert["insert"] RSFuncBlock_select["select"] - RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] + RS_insert["insert"] RS_RS["RS"] - RS_RS1["RS"] RS_take["take"] + RS_update["update"] + RS_RS1["RS"] RS_RS2["RS"] - RS_insert["insert"] RS_RS3["RS"] - RS_select["select"] - RS_update["update"] RS_RS4["RS"] RS_perf["perf"] + RS_select["select"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__stop["_stop"] TaggedLatencyMeasurer1__start["_start"] + TaggedLatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_AsyncMemoryBank["AsyncMemoryBank"] - AsyncMemoryBank1_AsyncMemoryBank1["AsyncMemoryBank"] + AsyncMemoryBank1_read0["read0"] + AsyncMemoryBank1_write0["write0"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -303,14 +303,14 @@ end end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph TaggedCounter4["perf_instr TaggedCounter"] TaggedCounter4__incr["_incr"] end subgraph FIFO2["fifo FIFO"] - FIFO2_write["write"] FIFO2_read["read"] + FIFO2_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] @@ -320,19 +320,19 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO4["fifo_branch_resolved FIFO"] - FIFO4_read["read"] FIFO4_write["write"] + FIFO4_read["read"] end subgraph TaggedCounter5["perf_instr TaggedCounter"] TaggedCounter5__incr["_incr"] @@ -355,24 +355,24 @@ ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] - FIFO5_write["write"] FIFO5_read["read"] + FIFO5_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] + PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] + PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] - PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] - PrivilegedFuncUnit_issue["issue"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] - BasicFifo8_write["write"] BasicFifo8_read["read"] + BasicFifo8_write["write"] end subgraph TaggedCounter6["perf_instr TaggedCounter"] TaggedCounter6__incr["_incr"] @@ -384,8 +384,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_write["write"] Forwarder5_read["read"] + Forwarder5_write["write"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans5["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -409,13 +409,13 @@ subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] RSFuncBlock1_select["select"] RSFuncBlock1_get_result["get_result"] - RSFuncBlock1_insert["insert"] RSFuncBlock1_update["update"] + RSFuncBlock1_insert["insert"] subgraph FifoRS["rs FifoRS"] - FifoRS_perf["perf"] - FifoRS_update["update"] FifoRS_FifoRS["FifoRS"] FifoRS_take["take"] + FifoRS_perf["perf"] + FifoRS_update["update"] FifoRS_select["select"] FifoRS_insert["insert"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] @@ -425,8 +425,8 @@ HwExpHistogram7__add["_add"] end subgraph AsyncMemoryBank2["slots AsyncMemoryBank"] - AsyncMemoryBank2_AsyncMemoryBank["AsyncMemoryBank"] - AsyncMemoryBank2_AsyncMemoryBank1["AsyncMemoryBank"] + AsyncMemoryBank2_write0["write0"] + AsyncMemoryBank2_read0["read0"] end end subgraph HwExpHistogram8["perf_num_full HwExpHistogram"] @@ -434,30 +434,30 @@ end end subgraph LSUDummy["func_unit_0 LSUDummy"] + LSUDummy_accept_cond1["accept_cond1"] LSUDummy_accept["accept"] LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_accept_cond0["accept_cond0"] LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_LSUDummy3["LSUDummy"] - LSUDummy_accept_cond1["accept_cond1"] LSUDummy_issue["issue"] - LSUDummy_accept_cond0["accept_cond0"] subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond1["issue_cond1"] - LSURequester_issue_cond0["issue_cond0"] - LSURequester_accept["accept"] - LSURequester_accept_cond0["accept_cond0"] - LSURequester_issue_cond2["issue_cond2"] LSURequester_issue["issue"] LSURequester_accept_cond1["accept_cond1"] + LSURequester_issue_cond2["issue_cond2"] + LSURequester_issue_cond1["issue_cond1"] + LSURequester_accept_cond0["accept_cond0"] + LSURequester_accept["accept"] + LSURequester_issue_cond0["issue_cond0"] subgraph BasicFifo9["args_fifo BasicFifo"] - BasicFifo9_write["write"] BasicFifo9_read["read"] + BasicFifo9_write["write"] end end subgraph Forwarder6["requests Forwarder"] - Forwarder6_read["read"] Forwarder6_write["write"] + Forwarder6_read["read"] end subgraph FIFO6["results_noop FIFO"] FIFO6_read["read"] @@ -489,12 +489,12 @@ end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_update["update"] - CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_get_result["get_result"] CSRUnit_insert["insert"] - CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_select["select"] - CSRUnit_get_result["get_result"] + CSRUnit_update["update"] + CSRUnit_fetch_resume["fetch_resume"] end end subgraph ResultAnnouncement["announcement ResultAnnouncement"] @@ -547,17 +547,17 @@ end end subgraph AliasedCSR["mstatus AliasedCSR"] - AliasedCSR__fu_write["_fu_write"] AliasedCSR__fu_read["_fu_read"] + AliasedCSR__fu_write["_fu_write"] end subgraph AliasedCSR1["mstatush AliasedCSR"] AliasedCSR1__fu_read["_fu_read"] AliasedCSR1__fu_write["_fu_write"] end subgraph CSRRegister6["mcause CSRRegister"] - CSRRegister6__internal_fu_write["_internal_fu_write"] - CSRRegister6__internal_fu_read["_internal_fu_read"] CSRRegister6_write["write"] + CSRRegister6__internal_fu_read["_internal_fu_read"] + CSRRegister6__internal_fu_write["_internal_fu_write"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -569,9 +569,9 @@ end end subgraph CSRRegister7["mtvec CSRRegister"] + CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7_read["read"] CSRRegister7__internal_fu_read["_internal_fu_read"] - CSRRegister7__internal_fu_write["_internal_fu_write"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] end @@ -583,10 +583,10 @@ end end subgraph CSRRegister8["mepc CSRRegister"] + CSRRegister8__internal_fu_write["_internal_fu_write"] + CSRRegister8_write["write"] CSRRegister8__internal_fu_read["_internal_fu_read"] CSRRegister8_read["read"] - CSRRegister8_write["write"] - CSRRegister8__internal_fu_write["_internal_fu_write"] subgraph MethodMap16["fu_write_map MethodMap"] MethodMap16_method["method"] end @@ -598,9 +598,9 @@ end end subgraph CSRRegister9["mtval CSRRegister"] - CSRRegister9__internal_fu_read["_internal_fu_read"] CSRRegister9__internal_fu_write["_internal_fu_write"] CSRRegister9_write["write"] + CSRRegister9__internal_fu_read["_internal_fu_read"] subgraph MethodMap18["fu_write_map MethodMap"] MethodMap18_method["method"] end @@ -612,8 +612,8 @@ end end subgraph CSRRegister10["misa CSRRegister"] - CSRRegister10__internal_fu_write["_internal_fu_write"] CSRRegister10__internal_fu_read["_internal_fu_read"] + CSRRegister10__internal_fu_write["_internal_fu_write"] subgraph MethodMap20["fu_write_map MethodMap"] MethodMap20_method["method"] end @@ -625,13 +625,13 @@ end end subgraph CSRRegister11["priv_mode CSRRegister"] - CSRRegister11_write["write"] CSRRegister11_read["read"] + CSRRegister11_write["write"] end subgraph CSRRegister12["mstatus_mie CSRRegister"] - CSRRegister12_read["read"] - CSRRegister12__internal_fu_write["_internal_fu_write"] CSRRegister12_write["write"] + CSRRegister12__internal_fu_write["_internal_fu_write"] + CSRRegister12_read["read"] CSRRegister12__internal_fu_read["_internal_fu_read"] subgraph MethodMap24["fu_write_map MethodMap"] MethodMap24_method["method"] @@ -644,10 +644,10 @@ end end subgraph CSRRegister13["mstatus_mpie CSRRegister"] - CSRRegister13__internal_fu_read["_internal_fu_read"] - CSRRegister13_write["write"] CSRRegister13__internal_fu_write["_internal_fu_write"] CSRRegister13_read["read"] + CSRRegister13__internal_fu_read["_internal_fu_read"] + CSRRegister13_write["write"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -659,10 +659,10 @@ end end subgraph CSRRegister14["mstatus_mpp CSRRegister"] + CSRRegister14_write["write"] CSRRegister14__internal_fu_read["_internal_fu_read"] CSRRegister14_read["read"] CSRRegister14__internal_fu_write["_internal_fu_write"] - CSRRegister14_write["write"] subgraph MethodMap28["fu_write_map MethodMap"] MethodMap28_method["method"] end @@ -674,9 +674,9 @@ end end subgraph CSRRegister15["mstatus_mprv CSRRegister"] - CSRRegister15__internal_fu_write["_internal_fu_write"] - CSRRegister15_write["write"] CSRRegister15__internal_fu_read["_internal_fu_read"] + CSRRegister15_write["write"] + CSRRegister15__internal_fu_write["_internal_fu_write"] subgraph MethodMap30["fu_write_map MethodMap"] MethodMap30_method["method"] end @@ -688,8 +688,8 @@ end end subgraph CSRRegister16["mstatus_tw CSRRegister"] - CSRRegister16__internal_fu_write["_internal_fu_write"] CSRRegister16__internal_fu_read["_internal_fu_read"] + CSRRegister16__internal_fu_write["_internal_fu_write"] CSRRegister16_read["read"] subgraph MethodMap32["fu_write_map MethodMap"] MethodMap32_method["method"] @@ -705,17 +705,17 @@ subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister17["register_low CSRRegister"] - CSRRegister17_write["write"] - CSRRegister17__internal_fu_read["_internal_fu_read"] CSRRegister17_read["read"] + CSRRegister17__internal_fu_read["_internal_fu_read"] + CSRRegister17_write["write"] subgraph MethodMap35["fu_read_map MethodMap"] MethodMap35_method["method"] end end subgraph CSRRegister18["register_high CSRRegister"] - CSRRegister18_write["write"] - CSRRegister18_read["read"] CSRRegister18__internal_fu_read["_internal_fu_read"] + CSRRegister18_read["read"] + CSRRegister18_write["write"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] end @@ -724,16 +724,16 @@ subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister19["register_low CSRRegister"] - CSRRegister19__internal_fu_read["_internal_fu_read"] CSRRegister19_read["read"] + CSRRegister19__internal_fu_read["_internal_fu_read"] CSRRegister19_write["write"] subgraph MethodMap39["fu_read_map MethodMap"] MethodMap39_method["method"] end end subgraph CSRRegister20["register_high CSRRegister"] - CSRRegister20_read["read"] CSRRegister20__internal_fu_read["_internal_fu_read"] + CSRRegister20_read["read"] CSRRegister20_write["write"] subgraph MethodMap41["fu_read_map MethodMap"] MethodMap41_method["method"] @@ -742,16 +742,16 @@ end end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] + InternalInterruptController_interrupt_cause["interrupt_cause"] InternalInterruptController_InternalInterruptController["InternalInterruptController"] - InternalInterruptController_entry["entry"] InternalInterruptController_InternalInterruptController1["InternalInterruptController"] - InternalInterruptController_interrupt_cause["interrupt_cause"] - InternalInterruptController_InternalInterruptController2["InternalInterruptController"] InternalInterruptController_mret["mret"] + InternalInterruptController_InternalInterruptController2["InternalInterruptController"] + InternalInterruptController_entry["entry"] subgraph CSRRegister21["mie CSRRegister"] + CSRRegister21_read["read"] CSRRegister21__internal_fu_read["_internal_fu_read"] CSRRegister21__internal_fu_write["_internal_fu_write"] - CSRRegister21_read["read"] subgraph MethodMap42["fu_write_map MethodMap"] MethodMap42_method["method"] end @@ -764,10 +764,10 @@ end subgraph CSRRegister22["mip CSRRegister"] CSRRegister22__internal_fu_write["_internal_fu_write"] - CSRRegister22_read["read"] CSRRegister22_read_comb["read_comb"] - CSRRegister22_write["write"] CSRRegister22__internal_fu_read["_internal_fu_read"] + CSRRegister22_read["read"] + CSRRegister22_write["write"] subgraph MethodMap44["fu_write_map MethodMap"] MethodMap44_method["method"] end @@ -802,15 +802,15 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO11["rs_select_out_buf FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -825,8 +825,8 @@ subgraph Collector3["FetchResumeKey_unifier Collector"] Collector3_method["method"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_write["write"] Forwarder8_read["read"] + Forwarder8_write["write"] end subgraph ManyToOneConnectTrans3["connect ManyToOneConnectTrans"] subgraph ConnectTrans11["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -842,19 +842,19 @@ ConnectTrans13_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_core_state["core_state"] + Retirement_precommit["precommit"] Retirement_Retirement1["Retirement"] Retirement_Retirement2["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement3["Retirement"] - Retirement_precommit["precommit"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister23["register_low CSRRegister"] - CSRRegister23__internal_fu_read["_internal_fu_read"] CSRRegister23_read["read"] + CSRRegister23__internal_fu_read["_internal_fu_read"] CSRRegister23_write["write"] subgraph MethodMap47["fu_read_map MethodMap"] MethodMap47_method["method"] @@ -862,8 +862,8 @@ end subgraph CSRRegister24["register_high CSRRegister"] CSRRegister24_read["read"] - CSRRegister24__internal_fu_read["_internal_fu_read"] CSRRegister24_write["write"] + CSRRegister24__internal_fu_read["_internal_fu_read"] subgraph MethodMap49["fu_read_map MethodMap"] MethodMap49_method["method"] end @@ -879,44 +879,44 @@ HwExpHistogram9__add["_add"] end subgraph FIFO12["fifo FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end end end end end subgraph TransactionManager["transaction_manager TransactionManager"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] - TransactionManager_accept_cond0_ConnectTrans_accept_cond1["accept_cond0_ConnectTrans_accept_cond1"] - TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] - TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit["PrivilegedFuncUnit_cond1_PrivilegedFuncUnit"] TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0["Fetch_Stage2_Fetch_Stage2_cond0"] - TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"] - TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit["PrivilegedFuncUnit_cond3_PrivilegedFuncUnit"] TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2["Fetch_Stage2_cond0_Fetch_Stage2"] + TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit["PrivilegedFuncUnit_cond0_PrivilegedFuncUnit"] + TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2["Fetch_Stage2_cond1_Fetch_Stage2"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_PrivilegedFuncUnit_cond0"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] + TransactionManager_accept_cond1_accept_cond0_ConnectTrans["accept_cond1_accept_cond0_ConnectTrans"] + TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit["PrivilegedFuncUnit_cond2_PrivilegedFuncUnit"] + TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] end end Core_InitFreeRFFifo --> BasicFifo5_write - Retirement_Retirement1 --> BasicFifo5_write + Retirement_Retirement3 --> BasicFifo5_write TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write - TransactionManager_Retirement_cond0_Retirement --> BasicFifo5_write + TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_serialize_in0 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - Serializer_Serializer1 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + Serializer_serialize_out0 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 @@ -966,56 +966,56 @@ GenericCSRRegisters_GenericCSRRegisters --> CSRRegister19_write CSRRegister20_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister20_write - CSRRegister12_read --> InternalInterruptController_InternalInterruptController2 CSRRegister12_read --> InternalInterruptController_InternalInterruptController - CSRRegister11_read --> InternalInterruptController_InternalInterruptController2 + CSRRegister12_read --> InternalInterruptController_InternalInterruptController1 CSRRegister11_read --> InternalInterruptController_InternalInterruptController + CSRRegister11_read --> InternalInterruptController_InternalInterruptController1 CSRRegister11_read --> WakeupSelect3_WakeupSelect CSRRegister11_read --> CSRUnit_CSRUnit - CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - CSRRegister21_read --> InternalInterruptController_InternalInterruptController2 - CSRRegister22_read --> InternalInterruptController_InternalInterruptController2 - CSRRegister22_read_comb --> InternalInterruptController_InternalInterruptController1 - InternalInterruptController_InternalInterruptController1 --> CSRRegister22_write - InternalInterruptController_InternalInterruptController --> CSRRegister12_write - InternalInterruptController_InternalInterruptController --> CSRRegister13_write - InternalInterruptController_InternalInterruptController --> CSRRegister14_write - InternalInterruptController_InternalInterruptController --> CSRRegister11_write - CSRRegister13_read --> InternalInterruptController_InternalInterruptController - CSRRegister14_read --> InternalInterruptController_InternalInterruptController - InternalInterruptController_InternalInterruptController --> CSRRegister15_write + CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit + CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit + CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit + CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit + CSRRegister21_read --> InternalInterruptController_InternalInterruptController + CSRRegister22_read --> InternalInterruptController_InternalInterruptController + CSRRegister22_read_comb --> InternalInterruptController_InternalInterruptController2 + InternalInterruptController_InternalInterruptController2 --> CSRRegister22_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister12_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister13_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister14_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister11_write + CSRRegister13_read --> InternalInterruptController_InternalInterruptController1 + CSRRegister14_read --> InternalInterruptController_InternalInterruptController1 + InternalInterruptController_InternalInterruptController1 --> CSRRegister15_write MethodProduct1_method --> RegAllocation_RegAllocation Pipe1_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation <--> CoreInstructionCounter_increment BasicFifo5_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO9_write + FIFO10_read --> RSSelection_RSSelection FIFO10_read --> RSSelection_RSSelection1 FIFO10_read --> RSSelection_RSSelection2 - FIFO10_read --> RSSelection_RSSelection - RSFuncBlock_select --> RSSelection_RSSelection1 - RS_select --> RSSelection_RSSelection1 + RSFuncBlock_select --> RSSelection_RSSelection + RS_select --> RSSelection_RSSelection + RSSelection_RSSelection --> FIFO11_write RSSelection_RSSelection1 --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write - RSSelection_RSSelection --> FIFO11_write - RSFuncBlock1_select --> RSSelection_RSSelection2 - FifoRS_select --> RSSelection_RSSelection2 - RSSelection_RSSelection <--> CSRUnit_select + RSFuncBlock1_select --> RSSelection_RSSelection1 + FifoRS_select --> RSSelection_RSSelection1 + RSSelection_RSSelection2 <--> CSRUnit_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion Retirement_core_state --> RSInsertion_RSInsertion - Retirement_core_state --> LSUDummy_LSUDummy + Retirement_core_state --> LSUDummy_LSUDummy2 RSInsertion_RSInsertion --> RSFuncBlock_insert RSInsertion_RSInsertion --> RS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer1__start - RSInsertion_RSInsertion --> AsyncMemoryBank1_AsyncMemoryBank1 + RSInsertion_RSInsertion --> AsyncMemoryBank1_write0 RSInsertion_RSInsertion --> RSFuncBlock1_insert RSInsertion_RSInsertion --> FifoRS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer2__start - RSInsertion_RSInsertion --> AsyncMemoryBank2_AsyncMemoryBank + RSInsertion_RSInsertion --> AsyncMemoryBank2_write0 RSInsertion_RSInsertion --> CSRUnit_insert BasicFifo6_read --> ConnectTrans1_ConnectTrans ConnectTrans1_ConnectTrans --> ExceptionInformationRegister_report @@ -1037,7 +1037,7 @@ ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done ResultAnnouncement_ResultAnnouncement --> RegisterFile_write ResultAnnouncement_ResultAnnouncement --> TaggedLatencyMeasurer__start - ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_AsyncMemoryBank + ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_write0 ResultAnnouncement_ResultAnnouncement --> MethodProduct_method ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update @@ -1045,7 +1045,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add - RS_RS2 --> WakeupSelect_WakeupSelect + RS_RS3 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -1056,11 +1056,11 @@ WakeupSelect2_WakeupSelect --> TaggedLatencyMeasurer1__stop WakeupSelect3_WakeupSelect --> TaggedLatencyMeasurer1__stop WakeupSelect4_WakeupSelect --> TaggedLatencyMeasurer1__stop - AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect_WakeupSelect - AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect1_WakeupSelect - AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect2_WakeupSelect - AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect3_WakeupSelect - AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect4_WakeupSelect + AsyncMemoryBank1_read0 --> WakeupSelect_WakeupSelect + AsyncMemoryBank1_read0 --> WakeupSelect1_WakeupSelect + AsyncMemoryBank1_read0 --> WakeupSelect2_WakeupSelect + AsyncMemoryBank1_read0 --> WakeupSelect3_WakeupSelect + AsyncMemoryBank1_read0 --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> HwExpHistogram5__add WakeupSelect1_WakeupSelect --> HwExpHistogram5__add WakeupSelect2_WakeupSelect --> HwExpHistogram5__add @@ -1069,25 +1069,25 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter4__incr WakeupSelect_WakeupSelect --> FIFO2_write - RS_RS1 --> WakeupSelect1_WakeupSelect + RS_RS4 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write - RS_RS --> WakeupSelect2_WakeupSelect + RS_RS1 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write WakeupSelect2_WakeupSelect --> TaggedCounter5__incr - RS_RS4 --> WakeupSelect3_WakeupSelect + RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> BasicFifo6_write ConnectTrans7_ConnectTrans --> BasicFifo6_write ConnectTrans9_ConnectTrans --> BasicFifo6_write ConnectTrans4_ConnectTrans --> BasicFifo6_write - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo6_write - TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> BasicFifo6_write TransactionManager_accept_cond1_ConnectTrans --> BasicFifo6_write + TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> BasicFifo6_write + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write - RS_RS3 --> WakeupSelect4_WakeupSelect + RS_RS2 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans5_ConnectTrans --> Forwarder5_write ConnectTrans6_ConnectTrans --> Forwarder5_write @@ -1110,40 +1110,40 @@ CSRRegister8_read --> ConnectTrans9_ConnectTrans ConnectTrans9_ConnectTrans --> BasicFifo8_write FifoRS_perf --> HwExpHistogram8__add - Forwarder6_read --> LSUDummy_LSUDummy2 + Forwarder6_read --> LSUDummy_LSUDummy Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond1 - Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 - LSUDummy_LSUDummy2 --> FIFO6_write + Forwarder6_read --> TransactionManager_issue_cond0_LSUDummy + LSUDummy_LSUDummy --> FIFO6_write WakeupSelect5_WakeupSelect --> FIFO6_write TransactionManager_LSUDummy_issue_cond2 --> FIFO6_write TransactionManager_LSUDummy_issue_cond1 --> FIFO6_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO6_write - LSUDummy_LSUDummy2 --> FIFO8_write + TransactionManager_issue_cond0_LSUDummy --> FIFO6_write + LSUDummy_LSUDummy --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write TransactionManager_LSUDummy_issue_cond1 --> FIFO8_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write + TransactionManager_issue_cond0_LSUDummy --> FIFO8_write LSUDummy_LSUDummy1 --> Retirement_precommit CSRUnit_CSRUnit --> Retirement_precommit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> Retirement_precommit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> Retirement_precommit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> Retirement_precommit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> Retirement_precommit + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> Retirement_precommit + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit --> Retirement_precommit + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit --> Retirement_precommit + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit --> Retirement_precommit ReorderBuffer_peek --> LSUDummy_LSUDummy1 ReorderBuffer_peek --> CSRUnit_CSRUnit + ReorderBuffer_peek --> Retirement_Retirement2 ReorderBuffer_peek --> Retirement_Retirement3 - ReorderBuffer_peek --> Retirement_Retirement1 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop - AsyncMemoryBank2_AsyncMemoryBank1 --> WakeupSelect5_WakeupSelect + AsyncMemoryBank2_read0 --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> HwExpHistogram7__add WakeupSelect5_WakeupSelect --> LSUDummy_issue WakeupSelect5_WakeupSelect --> Forwarder6_write @@ -1248,172 +1248,172 @@ Collector2_method --> ConnectTrans3_ConnectTrans Forwarder7_read --> ConnectTrans3_ConnectTrans CSRUnit_get_result --> ConnectTrans4_ConnectTrans - ExceptionInformationRegister_get --> Retirement_Retirement3 + ExceptionInformationRegister_get --> Retirement_Retirement2 ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond1 - ExceptionInformationRegister_get --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement1 <--> ReorderBuffer_retire + ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement3 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire - TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire - Retirement_Retirement1 <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire + Retirement_Retirement3 <--> FIFOLatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop - TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer1__stop - FIFO1_read --> Retirement_Retirement1 + TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop + FIFO1_read --> Retirement_Retirement3 FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 - FIFO1_read --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement1 --> HwExpHistogram3__add + FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement3 --> HwExpHistogram3__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram3__add - CoreInstructionCounter_decrement --> Retirement_Retirement1 + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add + CoreInstructionCounter_decrement --> Retirement_Retirement3 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement - RRAT_peek --> Retirement_Retirement1 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 + RRAT_peek --> Retirement_Retirement3 RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement1 --> RegisterFile_free + Retirement_Retirement3 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free - TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free - Retirement_Retirement1 --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free + Retirement_Retirement3 --> TaggedLatencyMeasurer__stop TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop - TransactionManager_Retirement_cond0_Retirement --> TaggedLatencyMeasurer__stop - AsyncMemoryBank_AsyncMemoryBank1 --> Retirement_Retirement1 - AsyncMemoryBank_AsyncMemoryBank1 --> TransactionManager_Retirement_Retirement_cond1 - AsyncMemoryBank_AsyncMemoryBank1 --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement1 --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop + AsyncMemoryBank_read0 --> Retirement_Retirement3 + AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond1 + AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement3 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add - Retirement_Retirement1 --> FRAT_rename + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add + Retirement_Retirement3 --> FRAT_rename TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename - TransactionManager_ROBAllocation_Renaming --> FRAT_rename - Retirement_Retirement2 <--> FIFOLatencyMeasurer2__stop - FIFO12_read --> Retirement_Retirement2 - Retirement_Retirement2 --> HwExpHistogram9__add - CSRRegister7_read --> Retirement_Retirement2 - Retirement_Retirement2 --> FetchUnit_resume_from_exception - Retirement_Retirement2 <--> ExceptionInformationRegister_clear - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 + TransactionManager_Renaming_ROBAllocation --> FRAT_rename + Retirement_Retirement1 <--> FIFOLatencyMeasurer2__stop + FIFO12_read --> Retirement_Retirement1 + Retirement_Retirement1 --> HwExpHistogram9__add + CSRRegister7_read --> Retirement_Retirement1 + Retirement_Retirement1 --> FetchUnit_resume_from_exception + Retirement_Retirement1 <--> ExceptionInformationRegister_clear + TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 + FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans + FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans + TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans + TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> ConnectTrans10_ConnectTrans + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans + TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write + TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> Forwarder7_write + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write + LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans + LSUDummy_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond0 + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> HwCounter5__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Serializer_write + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> Semaphore_release + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> Semaphore_release TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release - Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 + Pipe_read --> TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Predecoder_predecode + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Predecoder_predecode TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> PredictionChecker_check + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> PredictionChecker_check TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter1__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter1__incr TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter2__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter2__incr TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter3__incr TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write - TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy3 - TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy3 - TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy3 - TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond2 --> BasicFifo9_write - TransactionManager_LSUDummy_issue_cond1 --> BasicFifo9_write - TransactionManager_LSUDummy_issue_cond0 --> BasicFifo9_write - TransactionManager_LSUDummy_issue_cond2 --> FIFO7_write - TransactionManager_LSUDummy_issue_cond1 --> FIFO7_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO7_write - TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr - CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 - TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - BasicFifo9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - BasicFifo9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - FIFO7_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - FIFO7_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write - TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> Forwarder7_write - TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write - LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - Serializer1_Serializer3 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> ICache_flush + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit --> TaggedCounter6__incr + CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit + CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit + CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit + CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start - TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer2__start + TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write - TransactionManager_Retirement_cond0_Retirement --> FIFO12_write + TransactionManager_Retirement_Retirement_cond0 --> FIFO12_write InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 - InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond0_Retirement + InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister6_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister9_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister9_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister9_write TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry - TransactionManager_Retirement_cond0_Retirement <--> InternalInterruptController_entry + TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> InternalInterruptController_mret + TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + Serializer1_serialize_out0 --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + BasicFifo1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + WishboneMaster1_result --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + Forwarder1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 + LSURequester_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + BasicFifo9_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + FIFO7_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy3 + TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy3 + TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy3 + TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue + TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond2 --> BasicFifo9_write + TransactionManager_LSUDummy_issue_cond1 --> BasicFifo9_write + TransactionManager_issue_cond0_LSUDummy --> BasicFifo9_write + TransactionManager_LSUDummy_issue_cond2 --> FIFO7_write + TransactionManager_LSUDummy_issue_cond1 --> FIFO7_write + TransactionManager_issue_cond0_LSUDummy --> FIFO7_write + TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit + TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment + CSRRegister23_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister23_write + CSRRegister24_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister24_write + TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read - TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer + TransactionManager_LSUDummy_issue_cond1 --> Serializer1_serialize_in0 TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write + TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request - TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request - TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - Serializer1_Serializer2 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 - TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 - FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans - FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 - TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_cond0_Retirement --> RRAT_commit - TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment - CSRRegister23_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister23_write - CSRRegister24_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister24_write - TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr - TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation - Connect_read --> TransactionManager_ROBAllocation_Renaming - TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put - TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start - TransactionManager_ROBAllocation_Renaming --> FIFO1_write - TransactionManager_ROBAllocation_Renaming --> FIFO10_write - TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming - FIFO9_read --> TransactionManager_ROBAllocation_Renaming - TransactionManager_ROBAllocation_Renaming --> Connect_write + TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request + TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 + TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write + TransactionManager_issue_cond0_LSUDummy --> Serializer1_serialize_in1 + TransactionManager_Renaming_ROBAllocation <--> Renaming_Renaming + FIFO9_read --> TransactionManager_Renaming_ROBAllocation + TransactionManager_Renaming_ROBAllocation --> Connect_write + TransactionManager_Renaming_ROBAllocation <--> ROBAllocation_ROBAllocation + Connect_read --> TransactionManager_Renaming_ROBAllocation + TransactionManager_Renaming_ROBAllocation --> ReorderBuffer_put + TransactionManager_Renaming_ROBAllocation <--> FIFOLatencyMeasurer1__start + TransactionManager_Renaming_ROBAllocation --> FIFO1_write + TransactionManager_Renaming_ROBAllocation --> FIFO10_write + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + Serializer1_serialize_out1 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 diff --git a/_sources/index.md.txt b/_sources/index.md.txt index 0e16a25ec..6a9b5afba 100644 --- a/_sources/index.md.txt +++ b/_sources/index.md.txt @@ -8,7 +8,6 @@ maxdepth: 3 home.md assumptions.md development-environment.md -transactions.md scheduler/overview.md shared-structs/implementation/rs-impl.md shared-structs/rs.md diff --git a/api.html b/api.html index 5cff881c2..f2c90a4bd 100644 --- a/api.html +++ b/api.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -58,10 +57,6 @@
  • coreblocks package
  • -
  • transactron -
  • @@ -183,80 +178,6 @@

    coreblocks -

    transactron

    -
    - -
    - @@ -271,7 +192,7 @@

    transactron

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/assumptions.html b/assumptions.html index 77d546916..e980f089f 100644 --- a/assumptions.html +++ b/assumptions.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -104,7 +103,7 @@

    List of assumptions made during development

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/auto_graph.html b/auto_graph.html index 6434f3c18..c44a8261c 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -42,7 +42,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -94,69 +93,69 @@ end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_request["request"] WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] + WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] Forwarder1_write["write"] Forwarder1_read["read"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_request_read["request_read"] WishboneMasterAdapter_get_read_response["get_read_response"] + WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] - Serializer_Serializer["Serializer"] - Serializer_Serializer1["Serializer"] + Serializer_serialize_in0["serialize_in0"] + Serializer_serialize_out0["serialize_out0"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_get_write_response["get_write_response"] + WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_request_read["request_read"] - WishboneMasterAdapter1_get_read_response["get_read_response"] subgraph Serializer1["bus_serializer Serializer"] - Serializer1_Serializer["Serializer"] - Serializer1_Serializer1["Serializer"] - Serializer1_Serializer2["Serializer"] - Serializer1_Serializer3["Serializer"] + Serializer1_serialize_out1["serialize_out1"] + Serializer1_serialize_in0["serialize_in0"] + Serializer1_serialize_in1["serialize_in1"] + Serializer1_serialize_out0["serialize_out0"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_read["read"] BasicFifo1_write["write"] + BasicFifo1_read["read"] end end end subgraph CoreFrontend["frontend CoreFrontend"] - CoreFrontend_target_pred_req["target_pred_req"] - CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] CoreFrontend_target_pred_resp["target_pred_resp"] + CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] + CoreFrontend_target_pred_req["target_pred_req"] CoreFrontend_stall["stall"] subgraph BasicFifo2["instr_buffer BasicFifo"] - BasicFifo2_read["read"] - BasicFifo2_write["write"] BasicFifo2_clear["clear"] + BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_write["write"] Forwarder2_read["read"] + Forwarder2_write["write"] end end subgraph ICache["icache ICache"] - ICache_flush["flush"] - ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] ICache_ICache["ICache"] + ICache_flush["flush"] ICache_ICache1["ICache"] + ICache_issue_req["issue_req"] ICache_MemRead["MemRead"] + ICache_accept_res["accept_res"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -184,14 +183,14 @@ end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_read["read"] ArgumentsToResultsZipper_write_results["write_results"] - ArgumentsToResultsZipper_peek_arg["peek_arg"] ArgumentsToResultsZipper_write_args["write_args"] + ArgumentsToResultsZipper_peek_arg["peek_arg"] + ArgumentsToResultsZipper_read["read"] subgraph BasicFifo3["fifo BasicFifo"] - BasicFifo3_read["read"] BasicFifo3_write["write"] BasicFifo3_peek["peek"] + BasicFifo3_read["read"] end subgraph Forwarder3["forwarder Forwarder"] Forwarder3_read["read"] @@ -200,14 +199,14 @@ end end subgraph FetchUnit["fetch FetchUnit"] - FetchUnit_resume_from_unsafe["resume_from_unsafe"] + FetchUnit_Fetch_Stage2["Fetch_Stage2"] + FetchUnit_Fetch_Stage0["Fetch_Stage0"] + FetchUnit_resume_from_exception["resume_from_exception"] FetchUnit_Fetch_Stage1["Fetch_Stage1"] + FetchUnit_resume_from_unsafe["resume_from_unsafe"] FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] FetchUnit_stall_exception["stall_exception"] - FetchUnit_resume_from_exception["resume_from_exception"] - FetchUnit_Fetch_Stage2["Fetch_Stage2"] FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] - FetchUnit_Fetch_Stage0["Fetch_Stage0"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] end @@ -215,8 +214,8 @@ HwCounter5__incr["_incr"] end subgraph Serializer["serializer Serializer"] - Serializer_write["write"] Serializer_read["read"] + Serializer_write["write"] Serializer_clean["clean"] end subgraph ConnectTrans["serializer_connector ConnectTrans"] @@ -251,9 +250,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] - Pipe1_read["read"] - Pipe1_clean["clean"] Pipe1_write["write"] + Pipe1_clean["clean"] + Pipe1_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -263,8 +262,8 @@ end end subgraph BasicFifo5["free_rf_fifo BasicFifo"] - BasicFifo5_read["read"] BasicFifo5_write["write"] + BasicFifo5_read["read"] end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] @@ -274,11 +273,11 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] RegisterFile_write["write"] RegisterFile_read2["read2"] - RegisterFile_perf["perf"] RegisterFile_free["free"] + RegisterFile_read1["read1"] + RegisterFile_perf["perf"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer__stop["_stop"] TaggedLatencyMeasurer__start["_start"] @@ -286,8 +285,8 @@ HwExpHistogram1__add["_add"] end subgraph AsyncMemoryBank["slots AsyncMemoryBank"] - AsyncMemoryBank_AsyncMemoryBank["AsyncMemoryBank"] - AsyncMemoryBank_AsyncMemoryBank1["AsyncMemoryBank"] + AsyncMemoryBank_read0["read0"] + AsyncMemoryBank_write0["write0"] end end subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] @@ -295,15 +294,15 @@ end end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_retire["retire"] ReorderBuffer_perf["perf"] + ReorderBuffer_retire["retire"] ReorderBuffer_put["put"] - ReorderBuffer_peek["peek"] ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_peek["peek"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] - FIFOLatencyMeasurer1__start["_start"] FIFOLatencyMeasurer1__stop["_stop"] + FIFOLatencyMeasurer1__start["_start"] subgraph HwExpHistogram3["histogram HwExpHistogram"] HwExpHistogram3__add["_add"] end @@ -317,9 +316,9 @@ end end subgraph ExceptionInformationRegister["exception_information_register ExceptionInformationRegister"] + ExceptionInformationRegister_report["report"] ExceptionInformationRegister_clear["clear"] ExceptionInformationRegister_get["get"] - ExceptionInformationRegister_report["report"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] BasicFifo6_write["write"] BasicFifo6_read["read"] @@ -332,8 +331,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_read["read"] Forwarder4_write["write"] + Forwarder4_read["read"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans2["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -352,29 +351,29 @@ end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] RSFuncBlock_update["update"] + RSFuncBlock_get_result["get_result"] RSFuncBlock_insert["insert"] RSFuncBlock_select["select"] - RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] + RS_insert["insert"] RS_RS["RS"] - RS_RS1["RS"] RS_take["take"] + RS_update["update"] + RS_RS1["RS"] RS_RS2["RS"] - RS_insert["insert"] RS_RS3["RS"] - RS_select["select"] - RS_update["update"] RS_RS4["RS"] RS_perf["perf"] + RS_select["select"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__stop["_stop"] TaggedLatencyMeasurer1__start["_start"] + TaggedLatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_AsyncMemoryBank["AsyncMemoryBank"] - AsyncMemoryBank1_AsyncMemoryBank1["AsyncMemoryBank"] + AsyncMemoryBank1_read0["read0"] + AsyncMemoryBank1_write0["write0"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -382,14 +381,14 @@ end end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph TaggedCounter4["perf_instr TaggedCounter"] TaggedCounter4__incr["_incr"] end subgraph FIFO2["fifo FIFO"] - FIFO2_write["write"] FIFO2_read["read"] + FIFO2_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] @@ -399,19 +398,19 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] WakeupSelect1_WakeupSelect["WakeupSelect"] end subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] - JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] + JumpBranchFuncUnit_accept["accept"] subgraph FIFO4["fifo_branch_resolved FIFO"] - FIFO4_read["read"] FIFO4_write["write"] + FIFO4_read["read"] end subgraph TaggedCounter5["perf_instr TaggedCounter"] TaggedCounter5__incr["_incr"] @@ -434,24 +433,24 @@ ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] - FIFO5_write["write"] FIFO5_read["read"] + FIFO5_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] + PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] + PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] - PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] - PrivilegedFuncUnit_issue["issue"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] - BasicFifo8_write["write"] BasicFifo8_read["read"] + BasicFifo8_write["write"] end subgraph TaggedCounter6["perf_instr TaggedCounter"] TaggedCounter6__incr["_incr"] @@ -463,8 +462,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_write["write"] Forwarder5_read["read"] + Forwarder5_write["write"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans5["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -488,13 +487,13 @@ subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] RSFuncBlock1_select["select"] RSFuncBlock1_get_result["get_result"] - RSFuncBlock1_insert["insert"] RSFuncBlock1_update["update"] + RSFuncBlock1_insert["insert"] subgraph FifoRS["rs FifoRS"] - FifoRS_perf["perf"] - FifoRS_update["update"] FifoRS_FifoRS["FifoRS"] FifoRS_take["take"] + FifoRS_perf["perf"] + FifoRS_update["update"] FifoRS_select["select"] FifoRS_insert["insert"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] @@ -504,8 +503,8 @@ HwExpHistogram7__add["_add"] end subgraph AsyncMemoryBank2["slots AsyncMemoryBank"] - AsyncMemoryBank2_AsyncMemoryBank["AsyncMemoryBank"] - AsyncMemoryBank2_AsyncMemoryBank1["AsyncMemoryBank"] + AsyncMemoryBank2_write0["write0"] + AsyncMemoryBank2_read0["read0"] end end subgraph HwExpHistogram8["perf_num_full HwExpHistogram"] @@ -513,30 +512,30 @@ end end subgraph LSUDummy["func_unit_0 LSUDummy"] + LSUDummy_accept_cond1["accept_cond1"] LSUDummy_accept["accept"] LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_accept_cond0["accept_cond0"] LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_LSUDummy3["LSUDummy"] - LSUDummy_accept_cond1["accept_cond1"] LSUDummy_issue["issue"] - LSUDummy_accept_cond0["accept_cond0"] subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond1["issue_cond1"] - LSURequester_issue_cond0["issue_cond0"] - LSURequester_accept["accept"] - LSURequester_accept_cond0["accept_cond0"] - LSURequester_issue_cond2["issue_cond2"] LSURequester_issue["issue"] LSURequester_accept_cond1["accept_cond1"] + LSURequester_issue_cond2["issue_cond2"] + LSURequester_issue_cond1["issue_cond1"] + LSURequester_accept_cond0["accept_cond0"] + LSURequester_accept["accept"] + LSURequester_issue_cond0["issue_cond0"] subgraph BasicFifo9["args_fifo BasicFifo"] - BasicFifo9_write["write"] BasicFifo9_read["read"] + BasicFifo9_write["write"] end end subgraph Forwarder6["requests Forwarder"] - Forwarder6_read["read"] Forwarder6_write["write"] + Forwarder6_read["read"] end subgraph FIFO6["results_noop FIFO"] FIFO6_read["read"] @@ -568,12 +567,12 @@ end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_update["update"] - CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_get_result["get_result"] CSRUnit_insert["insert"] - CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_select["select"] - CSRUnit_get_result["get_result"] + CSRUnit_update["update"] + CSRUnit_fetch_resume["fetch_resume"] end end subgraph ResultAnnouncement["announcement ResultAnnouncement"] @@ -626,17 +625,17 @@ end end subgraph AliasedCSR["mstatus AliasedCSR"] - AliasedCSR__fu_write["_fu_write"] AliasedCSR__fu_read["_fu_read"] + AliasedCSR__fu_write["_fu_write"] end subgraph AliasedCSR1["mstatush AliasedCSR"] AliasedCSR1__fu_read["_fu_read"] AliasedCSR1__fu_write["_fu_write"] end subgraph CSRRegister6["mcause CSRRegister"] - CSRRegister6__internal_fu_write["_internal_fu_write"] - CSRRegister6__internal_fu_read["_internal_fu_read"] CSRRegister6_write["write"] + CSRRegister6__internal_fu_read["_internal_fu_read"] + CSRRegister6__internal_fu_write["_internal_fu_write"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -648,9 +647,9 @@ end end subgraph CSRRegister7["mtvec CSRRegister"] + CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7_read["read"] CSRRegister7__internal_fu_read["_internal_fu_read"] - CSRRegister7__internal_fu_write["_internal_fu_write"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] end @@ -662,10 +661,10 @@ end end subgraph CSRRegister8["mepc CSRRegister"] + CSRRegister8__internal_fu_write["_internal_fu_write"] + CSRRegister8_write["write"] CSRRegister8__internal_fu_read["_internal_fu_read"] CSRRegister8_read["read"] - CSRRegister8_write["write"] - CSRRegister8__internal_fu_write["_internal_fu_write"] subgraph MethodMap16["fu_write_map MethodMap"] MethodMap16_method["method"] end @@ -677,9 +676,9 @@ end end subgraph CSRRegister9["mtval CSRRegister"] - CSRRegister9__internal_fu_read["_internal_fu_read"] CSRRegister9__internal_fu_write["_internal_fu_write"] CSRRegister9_write["write"] + CSRRegister9__internal_fu_read["_internal_fu_read"] subgraph MethodMap18["fu_write_map MethodMap"] MethodMap18_method["method"] end @@ -691,8 +690,8 @@ end end subgraph CSRRegister10["misa CSRRegister"] - CSRRegister10__internal_fu_write["_internal_fu_write"] CSRRegister10__internal_fu_read["_internal_fu_read"] + CSRRegister10__internal_fu_write["_internal_fu_write"] subgraph MethodMap20["fu_write_map MethodMap"] MethodMap20_method["method"] end @@ -704,13 +703,13 @@ end end subgraph CSRRegister11["priv_mode CSRRegister"] - CSRRegister11_write["write"] CSRRegister11_read["read"] + CSRRegister11_write["write"] end subgraph CSRRegister12["mstatus_mie CSRRegister"] - CSRRegister12_read["read"] - CSRRegister12__internal_fu_write["_internal_fu_write"] CSRRegister12_write["write"] + CSRRegister12__internal_fu_write["_internal_fu_write"] + CSRRegister12_read["read"] CSRRegister12__internal_fu_read["_internal_fu_read"] subgraph MethodMap24["fu_write_map MethodMap"] MethodMap24_method["method"] @@ -723,10 +722,10 @@ end end subgraph CSRRegister13["mstatus_mpie CSRRegister"] - CSRRegister13__internal_fu_read["_internal_fu_read"] - CSRRegister13_write["write"] CSRRegister13__internal_fu_write["_internal_fu_write"] CSRRegister13_read["read"] + CSRRegister13__internal_fu_read["_internal_fu_read"] + CSRRegister13_write["write"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -738,10 +737,10 @@ end end subgraph CSRRegister14["mstatus_mpp CSRRegister"] + CSRRegister14_write["write"] CSRRegister14__internal_fu_read["_internal_fu_read"] CSRRegister14_read["read"] CSRRegister14__internal_fu_write["_internal_fu_write"] - CSRRegister14_write["write"] subgraph MethodMap28["fu_write_map MethodMap"] MethodMap28_method["method"] end @@ -753,9 +752,9 @@ end end subgraph CSRRegister15["mstatus_mprv CSRRegister"] - CSRRegister15__internal_fu_write["_internal_fu_write"] - CSRRegister15_write["write"] CSRRegister15__internal_fu_read["_internal_fu_read"] + CSRRegister15_write["write"] + CSRRegister15__internal_fu_write["_internal_fu_write"] subgraph MethodMap30["fu_write_map MethodMap"] MethodMap30_method["method"] end @@ -767,8 +766,8 @@ end end subgraph CSRRegister16["mstatus_tw CSRRegister"] - CSRRegister16__internal_fu_write["_internal_fu_write"] CSRRegister16__internal_fu_read["_internal_fu_read"] + CSRRegister16__internal_fu_write["_internal_fu_write"] CSRRegister16_read["read"] subgraph MethodMap32["fu_write_map MethodMap"] MethodMap32_method["method"] @@ -784,17 +783,17 @@ subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister17["register_low CSRRegister"] - CSRRegister17_write["write"] - CSRRegister17__internal_fu_read["_internal_fu_read"] CSRRegister17_read["read"] + CSRRegister17__internal_fu_read["_internal_fu_read"] + CSRRegister17_write["write"] subgraph MethodMap35["fu_read_map MethodMap"] MethodMap35_method["method"] end end subgraph CSRRegister18["register_high CSRRegister"] - CSRRegister18_write["write"] - CSRRegister18_read["read"] CSRRegister18__internal_fu_read["_internal_fu_read"] + CSRRegister18_read["read"] + CSRRegister18_write["write"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] end @@ -803,16 +802,16 @@ subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister19["register_low CSRRegister"] - CSRRegister19__internal_fu_read["_internal_fu_read"] CSRRegister19_read["read"] + CSRRegister19__internal_fu_read["_internal_fu_read"] CSRRegister19_write["write"] subgraph MethodMap39["fu_read_map MethodMap"] MethodMap39_method["method"] end end subgraph CSRRegister20["register_high CSRRegister"] - CSRRegister20_read["read"] CSRRegister20__internal_fu_read["_internal_fu_read"] + CSRRegister20_read["read"] CSRRegister20_write["write"] subgraph MethodMap41["fu_read_map MethodMap"] MethodMap41_method["method"] @@ -821,16 +820,16 @@ end end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] + InternalInterruptController_interrupt_cause["interrupt_cause"] InternalInterruptController_InternalInterruptController["InternalInterruptController"] - InternalInterruptController_entry["entry"] InternalInterruptController_InternalInterruptController1["InternalInterruptController"] - InternalInterruptController_interrupt_cause["interrupt_cause"] - InternalInterruptController_InternalInterruptController2["InternalInterruptController"] InternalInterruptController_mret["mret"] + InternalInterruptController_InternalInterruptController2["InternalInterruptController"] + InternalInterruptController_entry["entry"] subgraph CSRRegister21["mie CSRRegister"] + CSRRegister21_read["read"] CSRRegister21__internal_fu_read["_internal_fu_read"] CSRRegister21__internal_fu_write["_internal_fu_write"] - CSRRegister21_read["read"] subgraph MethodMap42["fu_write_map MethodMap"] MethodMap42_method["method"] end @@ -843,10 +842,10 @@ end subgraph CSRRegister22["mip CSRRegister"] CSRRegister22__internal_fu_write["_internal_fu_write"] - CSRRegister22_read["read"] CSRRegister22_read_comb["read_comb"] - CSRRegister22_write["write"] CSRRegister22__internal_fu_read["_internal_fu_read"] + CSRRegister22_read["read"] + CSRRegister22_write["write"] subgraph MethodMap44["fu_write_map MethodMap"] MethodMap44_method["method"] end @@ -881,15 +880,15 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO11["rs_select_out_buf FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -904,8 +903,8 @@ subgraph Collector3["FetchResumeKey_unifier Collector"] Collector3_method["method"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_write["write"] Forwarder8_read["read"] + Forwarder8_write["write"] end subgraph ManyToOneConnectTrans3["connect ManyToOneConnectTrans"] subgraph ConnectTrans11["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -921,19 +920,19 @@ ConnectTrans13_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_core_state["core_state"] + Retirement_precommit["precommit"] Retirement_Retirement1["Retirement"] Retirement_Retirement2["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement3["Retirement"] - Retirement_precommit["precommit"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister23["register_low CSRRegister"] - CSRRegister23__internal_fu_read["_internal_fu_read"] CSRRegister23_read["read"] + CSRRegister23__internal_fu_read["_internal_fu_read"] CSRRegister23_write["write"] subgraph MethodMap47["fu_read_map MethodMap"] MethodMap47_method["method"] @@ -941,8 +940,8 @@ end subgraph CSRRegister24["register_high CSRRegister"] CSRRegister24_read["read"] - CSRRegister24__internal_fu_read["_internal_fu_read"] CSRRegister24_write["write"] + CSRRegister24__internal_fu_read["_internal_fu_read"] subgraph MethodMap49["fu_read_map MethodMap"] MethodMap49_method["method"] end @@ -958,44 +957,44 @@ HwExpHistogram9__add["_add"] end subgraph FIFO12["fifo FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end end end end end subgraph TransactionManager["transaction_manager TransactionManager"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] - TransactionManager_accept_cond0_ConnectTrans_accept_cond1["accept_cond0_ConnectTrans_accept_cond1"] - TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] - TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] + TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit["PrivilegedFuncUnit_cond1_PrivilegedFuncUnit"] TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] - TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0["Fetch_Stage2_Fetch_Stage2_cond0"] - TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"] - TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit["PrivilegedFuncUnit_cond3_PrivilegedFuncUnit"] TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2["Fetch_Stage2_cond0_Fetch_Stage2"] + TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit["PrivilegedFuncUnit_cond0_PrivilegedFuncUnit"] + TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2["Fetch_Stage2_cond1_Fetch_Stage2"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_PrivilegedFuncUnit_cond0"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] + TransactionManager_accept_cond1_accept_cond0_ConnectTrans["accept_cond1_accept_cond0_ConnectTrans"] + TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit["PrivilegedFuncUnit_cond2_PrivilegedFuncUnit"] + TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] end end Core_InitFreeRFFifo --> BasicFifo5_write -Retirement_Retirement1 --> BasicFifo5_write +Retirement_Retirement3 --> BasicFifo5_write TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write -TransactionManager_Retirement_cond0_Retirement --> BasicFifo5_write +TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_serialize_in0 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -Serializer_Serializer1 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +Serializer_serialize_out0 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 @@ -1045,56 +1044,56 @@ GenericCSRRegisters_GenericCSRRegisters --> CSRRegister19_write CSRRegister20_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister20_write -CSRRegister12_read --> InternalInterruptController_InternalInterruptController2 CSRRegister12_read --> InternalInterruptController_InternalInterruptController -CSRRegister11_read --> InternalInterruptController_InternalInterruptController2 +CSRRegister12_read --> InternalInterruptController_InternalInterruptController1 CSRRegister11_read --> InternalInterruptController_InternalInterruptController +CSRRegister11_read --> InternalInterruptController_InternalInterruptController1 CSRRegister11_read --> WakeupSelect3_WakeupSelect CSRRegister11_read --> CSRUnit_CSRUnit -CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 -CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -CSRRegister21_read --> InternalInterruptController_InternalInterruptController2 -CSRRegister22_read --> InternalInterruptController_InternalInterruptController2 -CSRRegister22_read_comb --> InternalInterruptController_InternalInterruptController1 -InternalInterruptController_InternalInterruptController1 --> CSRRegister22_write -InternalInterruptController_InternalInterruptController --> CSRRegister12_write -InternalInterruptController_InternalInterruptController --> CSRRegister13_write -InternalInterruptController_InternalInterruptController --> CSRRegister14_write -InternalInterruptController_InternalInterruptController --> CSRRegister11_write -CSRRegister13_read --> InternalInterruptController_InternalInterruptController -CSRRegister14_read --> InternalInterruptController_InternalInterruptController -InternalInterruptController_InternalInterruptController --> CSRRegister15_write +CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit +CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit +CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit +CSRRegister11_read --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit +CSRRegister21_read --> InternalInterruptController_InternalInterruptController +CSRRegister22_read --> InternalInterruptController_InternalInterruptController +CSRRegister22_read_comb --> InternalInterruptController_InternalInterruptController2 +InternalInterruptController_InternalInterruptController2 --> CSRRegister22_write +InternalInterruptController_InternalInterruptController1 --> CSRRegister12_write +InternalInterruptController_InternalInterruptController1 --> CSRRegister13_write +InternalInterruptController_InternalInterruptController1 --> CSRRegister14_write +InternalInterruptController_InternalInterruptController1 --> CSRRegister11_write +CSRRegister13_read --> InternalInterruptController_InternalInterruptController1 +CSRRegister14_read --> InternalInterruptController_InternalInterruptController1 +InternalInterruptController_InternalInterruptController1 --> CSRRegister15_write MethodProduct1_method --> RegAllocation_RegAllocation Pipe1_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation <--> CoreInstructionCounter_increment BasicFifo5_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO9_write +FIFO10_read --> RSSelection_RSSelection FIFO10_read --> RSSelection_RSSelection1 FIFO10_read --> RSSelection_RSSelection2 -FIFO10_read --> RSSelection_RSSelection -RSFuncBlock_select --> RSSelection_RSSelection1 -RS_select --> RSSelection_RSSelection1 +RSFuncBlock_select --> RSSelection_RSSelection +RS_select --> RSSelection_RSSelection +RSSelection_RSSelection --> FIFO11_write RSSelection_RSSelection1 --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write -RSSelection_RSSelection --> FIFO11_write -RSFuncBlock1_select --> RSSelection_RSSelection2 -FifoRS_select --> RSSelection_RSSelection2 -RSSelection_RSSelection <--> CSRUnit_select +RSFuncBlock1_select --> RSSelection_RSSelection1 +FifoRS_select --> RSSelection_RSSelection1 +RSSelection_RSSelection2 <--> CSRUnit_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion Retirement_core_state --> RSInsertion_RSInsertion -Retirement_core_state --> LSUDummy_LSUDummy +Retirement_core_state --> LSUDummy_LSUDummy2 RSInsertion_RSInsertion --> RSFuncBlock_insert RSInsertion_RSInsertion --> RS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer1__start -RSInsertion_RSInsertion --> AsyncMemoryBank1_AsyncMemoryBank1 +RSInsertion_RSInsertion --> AsyncMemoryBank1_write0 RSInsertion_RSInsertion --> RSFuncBlock1_insert RSInsertion_RSInsertion --> FifoRS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer2__start -RSInsertion_RSInsertion --> AsyncMemoryBank2_AsyncMemoryBank +RSInsertion_RSInsertion --> AsyncMemoryBank2_write0 RSInsertion_RSInsertion --> CSRUnit_insert BasicFifo6_read --> ConnectTrans1_ConnectTrans ConnectTrans1_ConnectTrans --> ExceptionInformationRegister_report @@ -1116,7 +1115,7 @@ ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done ResultAnnouncement_ResultAnnouncement --> RegisterFile_write ResultAnnouncement_ResultAnnouncement --> TaggedLatencyMeasurer__start -ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_AsyncMemoryBank +ResultAnnouncement_ResultAnnouncement --> AsyncMemoryBank_write0 ResultAnnouncement_ResultAnnouncement --> MethodProduct_method ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update @@ -1124,7 +1123,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add -RS_RS2 --> WakeupSelect_WakeupSelect +RS_RS3 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -1135,11 +1134,11 @@ WakeupSelect2_WakeupSelect --> TaggedLatencyMeasurer1__stop WakeupSelect3_WakeupSelect --> TaggedLatencyMeasurer1__stop WakeupSelect4_WakeupSelect --> TaggedLatencyMeasurer1__stop -AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect_WakeupSelect -AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect1_WakeupSelect -AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect2_WakeupSelect -AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect3_WakeupSelect -AsyncMemoryBank1_AsyncMemoryBank --> WakeupSelect4_WakeupSelect +AsyncMemoryBank1_read0 --> WakeupSelect_WakeupSelect +AsyncMemoryBank1_read0 --> WakeupSelect1_WakeupSelect +AsyncMemoryBank1_read0 --> WakeupSelect2_WakeupSelect +AsyncMemoryBank1_read0 --> WakeupSelect3_WakeupSelect +AsyncMemoryBank1_read0 --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> HwExpHistogram5__add WakeupSelect1_WakeupSelect --> HwExpHistogram5__add WakeupSelect2_WakeupSelect --> HwExpHistogram5__add @@ -1148,25 +1147,25 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter4__incr WakeupSelect_WakeupSelect --> FIFO2_write -RS_RS1 --> WakeupSelect1_WakeupSelect +RS_RS4 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write -RS_RS --> WakeupSelect2_WakeupSelect +RS_RS1 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write WakeupSelect2_WakeupSelect --> TaggedCounter5__incr -RS_RS4 --> WakeupSelect3_WakeupSelect +RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> BasicFifo6_write ConnectTrans7_ConnectTrans --> BasicFifo6_write ConnectTrans9_ConnectTrans --> BasicFifo6_write ConnectTrans4_ConnectTrans --> BasicFifo6_write -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo6_write -TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> BasicFifo6_write TransactionManager_accept_cond1_ConnectTrans --> BasicFifo6_write +TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> BasicFifo6_write +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write -RS_RS3 --> WakeupSelect4_WakeupSelect +RS_RS2 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans5_ConnectTrans --> Forwarder5_write ConnectTrans6_ConnectTrans --> Forwarder5_write @@ -1189,40 +1188,40 @@ CSRRegister8_read --> ConnectTrans9_ConnectTrans ConnectTrans9_ConnectTrans --> BasicFifo8_write FifoRS_perf --> HwExpHistogram8__add -Forwarder6_read --> LSUDummy_LSUDummy2 +Forwarder6_read --> LSUDummy_LSUDummy Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 Forwarder6_read --> TransactionManager_LSUDummy_issue_cond1 -Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 -LSUDummy_LSUDummy2 --> FIFO6_write +Forwarder6_read --> TransactionManager_issue_cond0_LSUDummy +LSUDummy_LSUDummy --> FIFO6_write WakeupSelect5_WakeupSelect --> FIFO6_write TransactionManager_LSUDummy_issue_cond2 --> FIFO6_write TransactionManager_LSUDummy_issue_cond1 --> FIFO6_write -TransactionManager_LSUDummy_issue_cond0 --> FIFO6_write -LSUDummy_LSUDummy2 --> FIFO8_write +TransactionManager_issue_cond0_LSUDummy --> FIFO6_write +LSUDummy_LSUDummy --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write TransactionManager_LSUDummy_issue_cond1 --> FIFO8_write -TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write +TransactionManager_issue_cond0_LSUDummy --> FIFO8_write LSUDummy_LSUDummy1 --> Retirement_precommit CSRUnit_CSRUnit --> Retirement_precommit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> Retirement_precommit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> Retirement_precommit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> Retirement_precommit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> Retirement_precommit +TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> Retirement_precommit +TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit --> Retirement_precommit +TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit --> Retirement_precommit +TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit --> Retirement_precommit ReorderBuffer_peek --> LSUDummy_LSUDummy1 ReorderBuffer_peek --> CSRUnit_CSRUnit +ReorderBuffer_peek --> Retirement_Retirement2 ReorderBuffer_peek --> Retirement_Retirement3 -ReorderBuffer_peek --> Retirement_Retirement1 -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop -AsyncMemoryBank2_AsyncMemoryBank1 --> WakeupSelect5_WakeupSelect +AsyncMemoryBank2_read0 --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> HwExpHistogram7__add WakeupSelect5_WakeupSelect --> LSUDummy_issue WakeupSelect5_WakeupSelect --> Forwarder6_write @@ -1327,175 +1326,175 @@ Collector2_method --> ConnectTrans3_ConnectTrans Forwarder7_read --> ConnectTrans3_ConnectTrans CSRUnit_get_result --> ConnectTrans4_ConnectTrans -ExceptionInformationRegister_get --> Retirement_Retirement3 +ExceptionInformationRegister_get --> Retirement_Retirement2 ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond1 -ExceptionInformationRegister_get --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement1 <--> ReorderBuffer_retire +ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement3 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire -TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire -Retirement_Retirement1 <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire +Retirement_Retirement3 <--> FIFOLatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop -TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer1__stop -FIFO1_read --> Retirement_Retirement1 +TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop +FIFO1_read --> Retirement_Retirement3 FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 -FIFO1_read --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement1 --> HwExpHistogram3__add +FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement3 --> HwExpHistogram3__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram3__add -CoreInstructionCounter_decrement --> Retirement_Retirement1 +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add +CoreInstructionCounter_decrement --> Retirement_Retirement3 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement -RRAT_peek --> Retirement_Retirement1 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 +RRAT_peek --> Retirement_Retirement3 RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement1 --> RegisterFile_free +Retirement_Retirement3 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free -TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free -Retirement_Retirement1 --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free +Retirement_Retirement3 --> TaggedLatencyMeasurer__stop TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop -TransactionManager_Retirement_cond0_Retirement --> TaggedLatencyMeasurer__stop -AsyncMemoryBank_AsyncMemoryBank1 --> Retirement_Retirement1 -AsyncMemoryBank_AsyncMemoryBank1 --> TransactionManager_Retirement_Retirement_cond1 -AsyncMemoryBank_AsyncMemoryBank1 --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement1 --> HwExpHistogram1__add +TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop +AsyncMemoryBank_read0 --> Retirement_Retirement3 +AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond1 +AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement3 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add -Retirement_Retirement1 --> FRAT_rename +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add +Retirement_Retirement3 --> FRAT_rename TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename -TransactionManager_ROBAllocation_Renaming --> FRAT_rename -Retirement_Retirement2 <--> FIFOLatencyMeasurer2__stop -FIFO12_read --> Retirement_Retirement2 -Retirement_Retirement2 --> HwExpHistogram9__add -CSRRegister7_read --> Retirement_Retirement2 -Retirement_Retirement2 --> FetchUnit_resume_from_exception -Retirement_Retirement2 <--> ExceptionInformationRegister_clear -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 +TransactionManager_Renaming_ROBAllocation --> FRAT_rename +Retirement_Retirement1 <--> FIFOLatencyMeasurer2__stop +FIFO12_read --> Retirement_Retirement1 +Retirement_Retirement1 --> HwExpHistogram9__add +CSRRegister7_read --> Retirement_Retirement1 +Retirement_Retirement1 --> FetchUnit_resume_from_exception +Retirement_Retirement1 <--> ExceptionInformationRegister_clear +TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 +FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans +FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans +TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans +TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> ConnectTrans10_ConnectTrans +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans +TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write +TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> Forwarder7_write +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write +LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans +LSUDummy_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond0 +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> HwCounter5__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Serializer_write +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> Semaphore_release +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> Semaphore_release TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release -Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 +Pipe_read --> TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Predecoder_predecode +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Predecoder_predecode TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> PredictionChecker_check +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> PredictionChecker_check TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter1__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter1__incr TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter2__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter2__incr TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter3__incr TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr -TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write -TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy3 -TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy3 -TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy3 -TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond2 --> BasicFifo9_write -TransactionManager_LSUDummy_issue_cond1 --> BasicFifo9_write -TransactionManager_LSUDummy_issue_cond0 --> BasicFifo9_write -TransactionManager_LSUDummy_issue_cond2 --> FIFO7_write -TransactionManager_LSUDummy_issue_cond1 --> FIFO7_write -TransactionManager_LSUDummy_issue_cond0 --> FIFO7_write -TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr -CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 -CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 -TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond0 -LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 -BasicFifo9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -BasicFifo9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 -FIFO7_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -FIFO7_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans10_ConnectTrans -TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans -TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write -TransactionManager_accept_cond0_ConnectTrans_accept_cond1 --> Forwarder7_write -TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write -LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 -LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -Serializer1_Serializer3 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 -WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 -Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 +TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 +TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> ICache_flush +TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit --> TaggedCounter6__incr +CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit +CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit +CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit +CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start -TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer2__start +TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write -TransactionManager_Retirement_cond0_Retirement --> FIFO12_write +TransactionManager_Retirement_Retirement_cond0 --> FIFO12_write InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 -InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond0_Retirement +InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister6_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write TransactionManager_Retirement_Retirement_cond1 --> CSRRegister9_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister9_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister9_write TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry -TransactionManager_Retirement_cond0_Retirement <--> InternalInterruptController_entry +TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 +TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> InternalInterruptController_mret +TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +Serializer1_serialize_out0 --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +BasicFifo1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +WishboneMaster1_result --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +Forwarder1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 +LSURequester_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +BasicFifo9_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +FIFO7_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy3 +TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy3 +TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy3 +TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue +TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond2 --> BasicFifo9_write +TransactionManager_LSUDummy_issue_cond1 --> BasicFifo9_write +TransactionManager_issue_cond0_LSUDummy --> BasicFifo9_write +TransactionManager_LSUDummy_issue_cond2 --> FIFO7_write +TransactionManager_LSUDummy_issue_cond1 --> FIFO7_write +TransactionManager_issue_cond0_LSUDummy --> FIFO7_write +TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit +TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment +CSRRegister23_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister23_write +CSRRegister24_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister24_write +TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read -TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer +TransactionManager_LSUDummy_issue_cond1 --> Serializer1_serialize_in0 TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write -TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write +TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request -TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request -TransactionManager_accept_cond0_ConnectTrans_accept_cond1 <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 -Serializer1_Serializer2 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond1 -TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 -FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans -FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 -TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write -TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_cond0_Retirement --> RRAT_commit -TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment -CSRRegister23_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister23_write -CSRRegister24_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister24_write -TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr -TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation -Connect_read --> TransactionManager_ROBAllocation_Renaming -TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put -TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start -TransactionManager_ROBAllocation_Renaming --> FIFO1_write -TransactionManager_ROBAllocation_Renaming --> FIFO10_write -TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming -FIFO9_read --> TransactionManager_ROBAllocation_Renaming -TransactionManager_ROBAllocation_Renaming --> Connect_write +TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request +TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 +TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write +TransactionManager_issue_cond0_LSUDummy --> Serializer1_serialize_in1 +TransactionManager_Renaming_ROBAllocation <--> Renaming_Renaming +FIFO9_read --> TransactionManager_Renaming_ROBAllocation +TransactionManager_Renaming_ROBAllocation --> Connect_write +TransactionManager_Renaming_ROBAllocation <--> ROBAllocation_ROBAllocation +Connect_read --> TransactionManager_Renaming_ROBAllocation +TransactionManager_Renaming_ROBAllocation --> ReorderBuffer_put +TransactionManager_Renaming_ROBAllocation <--> FIFOLatencyMeasurer1__start +TransactionManager_Renaming_ROBAllocation --> FIFO1_write +TransactionManager_Renaming_ROBAllocation --> FIFO10_write +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +Serializer1_serialize_out1 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 @@ -1506,7 +1505,7 @@

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/components/icache.html b/components/icache.html index 9d36bed51..69446afc1 100644 --- a/components/icache.html +++ b/components/icache.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -131,7 +130,7 @@

    Address mapping example

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.arch.html b/coreblocks.arch.html index f6e002d8c..095899b30 100644 --- a/coreblocks.arch.html +++ b/coreblocks.arch.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -3923,7 +3922,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.backend.html b/coreblocks.backend.html index ac88c2a0f..49dc411cd 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -103,7 +102,7 @@

    Submodules
    -__init__(*, gen_params: GenParams, get_result: Method, rob_mark_done: Method, rs_update: Method, rf_write: Method)
    +__init__(*, gen_params: GenParams, get_result: Method, rob_mark_done: Method, rs_update: Method, rf_write: Method)
    Parameters
    @@ -142,7 +141,7 @@

    SubmodulesElaboratable

    -__init__(gen_params: GenParams, *, rob_peek: Method, rob_retire: Method, r_rat_commit: Method, r_rat_peek: Method, free_rf_put: Method, rf_free: Method, exception_cause_get: Method, exception_cause_clear: Method, frat_rename: Method, fetch_continue: Method, instr_decrement: Method, trap_entry: Method, async_interrupt_cause: Method)
    +__init__(gen_params: GenParams, *, rob_peek: Method, rob_retire: Method, r_rat_commit: Method, r_rat_peek: Method, free_rf_put: Method, rf_free: Method, exception_cause_get: Method, exception_cause_clear: Method, frat_rename: Method, fetch_continue: Method, instr_decrement: Method, trap_entry: Method, async_interrupt_cause: Method)

    @@ -165,7 +164,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.cache.html b/coreblocks.cache.html index 5fecc6e23..9e19fd75c 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -167,17 +166,17 @@

    Submodules
    -accept_res: Method
    +accept_res: Method
    -flush: Method
    +flush: Method
    -issue_req: Method
    +issue_req: Method

    @@ -199,12 +198,12 @@

    Submodules
    -accept_refill: Method
    +accept_refill: Method
    -start_refill: Method
    +start_refill: Method
    @@ -241,7 +240,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index f1e6cd45a..a9cd039d1 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -157,7 +156,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index 11434cefd..f7ff41c9f 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -99,7 +98,7 @@

    Submodules
    -__init__(gen_params: GenParams, get_raw: Method, push_decoded: Method) None
    +__init__(gen_params: GenParams, get_raw: Method, push_decoded: Method) None
    Parameters
    @@ -313,7 +312,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index cf96c3dbb..4e4a88415 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -103,7 +102,7 @@

    Submodules
    -__init__(gen_params: GenParams, icache: CacheInterface, cont: Method) None
    +__init__(gen_params: GenParams, icache: CacheInterface, cont: Method) None
    Parameters
    @@ -210,7 +209,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 60b909fa9..617088b61 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -187,7 +186,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.func_blocks.fu.fpu.html b/coreblocks.func_blocks.fu.fpu.html index 3e145fe1b..63b54852d 100644 --- a/coreblocks.func_blocks.fu.fpu.html +++ b/coreblocks.func_blocks.fu.fpu.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -303,7 +302,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index 65921824f..5a870be6c 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -894,7 +893,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.func_blocks.fu.lsu.html b/coreblocks.func_blocks.fu.lsu.html index 7f7fe558f..7e1f90142 100644 --- a/coreblocks.func_blocks.fu.lsu.html +++ b/coreblocks.func_blocks.fu.lsu.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -175,7 +174,7 @@

    Submodules
    -check_align(m: TModule, funct3: Value, addr: Value)
    +check_align(m: TModule, funct3: Value, addr: Value)

    @@ -290,7 +289,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index 9edecae88..6df061f4a 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -260,7 +259,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index 0b7ba6f76..3e75912ba 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -158,7 +157,7 @@

    Subpackages

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index d432e5f39..4959c233d 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -110,22 +109,22 @@

    SubmodulesHasElaborate, Protocol

    -get_result: Method
    +get_result: Method
    -insert: Method
    +insert: Method
    -select: Method
    +select: Method
    -update: Method
    +update: Method

    @@ -136,12 +135,12 @@

    SubmodulesHasElaborate, Protocol

    -accept: Method
    +accept: Method
    -issue: Method
    +issue: Method

    @@ -164,7 +163,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.html b/coreblocks.html index 58c9e48b8..220265b8c 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -268,7 +267,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.params.html b/coreblocks.params.html index 990bc35d0..f7fc26867 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -156,7 +155,7 @@

    Submodules
    class coreblocks.params.genparams.GenParams
    -

    Bases: DependentCache

    +

    Bases: DependentCache

    __init__(cfg: CoreConfiguration)
    @@ -832,7 +831,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index eecc528d0..e821317a7 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -169,7 +168,7 @@

    Submodules
    -result_handler(m: TModule, forwarder: Forwarder, *, channel: coreblocks.peripherals.axi_lite.AXILiteWriteResponseInterface | coreblocks.peripherals.axi_lite.AXILiteReadDataInterface)
    +result_handler(m: TModule, forwarder: Forwarder, *, channel: coreblocks.peripherals.axi_lite.AXILiteWriteResponseInterface | coreblocks.peripherals.axi_lite.AXILiteReadDataInterface)

    @@ -179,7 +178,7 @@

    Submodules
    -state_machine_request(m: TModule, method: Method, *, channel: coreblocks.peripherals.axi_lite.AXILiteWriteAddressInterface | coreblocks.peripherals.axi_lite.AXILiteWriteDataInterface | coreblocks.peripherals.axi_lite.AXILiteReadAddressInterface, request_signal: Signal)
    +state_machine_request(m: TModule, method: Method, *, channel: coreblocks.peripherals.axi_lite.AXILiteWriteAddressInterface | coreblocks.peripherals.axi_lite.AXILiteWriteDataInterface | coreblocks.peripherals.axi_lite.AXILiteReadAddressInterface, request_signal: Signal)

    @@ -299,12 +298,12 @@

    Submodules
    -get_read_response: Method
    +get_read_response: Method
    -get_write_response: Method
    +get_write_response: Method
    @@ -314,12 +313,12 @@

    Submodules
    -request_read: Method
    +request_read: Method

    -request_write: Method
    +request_write: Method

    @@ -746,7 +745,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html index 8906eda1e..9acc14c02 100644 --- a/coreblocks.priv.csr.html +++ b/coreblocks.priv.csr.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -250,7 +249,7 @@

    Submodules
    -__init__(csr_number: Optional[int], gen_params: GenParams, *, width: Optional[int] = None, ro_bits: int = 0, init: int | amaranth.lib.enum.Enum = 0, fu_write_priority: bool = True, fu_write_filtermap: Optional[Callable[[TModule, Value], tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]] = None, fu_read_map: Optional[Callable[[TModule, Value], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]] = None, src_loc: int | tuple[str, int] = 0)
    +__init__(csr_number: Optional[int], gen_params: GenParams, *, width: Optional[int] = None, ro_bits: int = 0, init: int | amaranth.lib.enum.Enum = 0, fu_write_priority: bool = True, fu_write_filtermap: Optional[Callable[[TModule, Value], tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]] = None, fu_read_map: Optional[Callable[[TModule, Value], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]] = None, src_loc: int | tuple[str, int] = 0)
    Parameters
    @@ -306,7 +305,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.priv.html b/coreblocks.priv.html index 477b38316..478697bc7 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -124,7 +123,7 @@

    Subpackages

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index 94a7e7719..d1f9ba33e 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -102,14 +101,14 @@

    Submodules
    -__init__(gen_params: GenParams, rob_get_indices: Method, fetch_stall_exception: Method)
    +__init__(gen_params: GenParams, rob_get_indices: Method, fetch_stall_exception: Method)

    -coreblocks.priv.traps.exception.should_update_prioriy(m: TModule, current_cause: Value, new_cause: Value) Value
    +coreblocks.priv.traps.exception.should_update_prioriy(m: TModule, current_cause: Value, new_cause: Value) Value
    @@ -205,7 +204,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 85d65f724..8a4799307 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -20,7 +20,6 @@ - @@ -44,7 +43,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -108,7 +106,7 @@

    Submodules
    -__init__(*, get_instr: Method, get_free_reg: Method, rat_rename: Method, rob_put: Method, rf_read1: Method, rf_read2: Method, reservation_stations: Sequence[tuple[coreblocks.func_blocks.interface.func_protocols.FuncBlock, set[coreblocks.arch.optypes.OpType]]], gen_params: GenParams)
    +__init__(*, get_instr: Method, get_free_reg: Method, rat_rename: Method, rob_put: Method, rf_read1: Method, rf_read2: Method, reservation_stations: Sequence[tuple[coreblocks.func_blocks.interface.func_protocols.FuncBlock, set[coreblocks.arch.optypes.OpType]]], gen_params: GenParams)
    Parameters
    @@ -154,7 +152,7 @@

    Submodules
    -__init__(*, gen_params: GenParams, get_ready: Method, take_row: Method, issue: Method)
    +__init__(*, gen_params: GenParams, get_ready: Method, take_row: Method, issue: Method)
    Parameters
    @@ -184,14 +182,13 @@

    Submodules -

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/current-graph.html b/current-graph.html index 01d54e5ba..4abc7a697 100644 --- a/current-graph.html +++ b/current-graph.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -100,69 +99,69 @@

    Full transaction-method graph

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/development-environment.html b/development-environment.html index 4310ea2f8..5211f570a 100644 --- a/development-environment.html +++ b/development-environment.html @@ -20,7 +20,7 @@ - + @@ -55,7 +55,6 @@ -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -202,14 +201,14 @@

    tprof.py - +

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/genindex.html b/genindex.html index b4096272f..b3b1c73a5 100644 --- a/genindex.html +++ b/genindex.html @@ -42,7 +42,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -297,172 +296,6 @@

    _

  • (coreblocks.scheduler.scheduler.Scheduler method)
  • (coreblocks.scheduler.wakeup_select.WakeupSelect method) -
  • -
  • (transactron.core.keys.TransactionManagerKey method) -
  • -
  • (transactron.core.manager.TransactionComponent method) -
  • -
  • (transactron.core.manager.TransactionManager method) -
  • -
  • (transactron.core.manager.TransactionModule method) -
  • -
  • (transactron.core.method.Method method) -
  • -
  • (transactron.core.tmodule.TModule method) -
  • -
  • (transactron.core.transaction.Transaction method) -
  • -
  • (transactron.core.transaction_base.TransactionBase method) -
  • -
  • (transactron.graph.Owned method) -
  • -
  • (transactron.graph.OwnershipGraph method) -
  • -
  • (transactron.lib.adapters.Adapter method) -
  • -
  • (transactron.lib.adapters.AdapterBase method) -
  • -
  • (transactron.lib.adapters.AdapterTrans method) -
  • -
  • (transactron.lib.buttons.ClickIn method) -
  • -
  • (transactron.lib.buttons.ClickOut method) -
  • -
  • (transactron.lib.connectors.Connect method) -
  • -
  • (transactron.lib.connectors.ConnectTrans method) -
  • -
  • (transactron.lib.connectors.FIFO method) -
  • -
  • (transactron.lib.connectors.Forwarder method) -
  • -
  • (transactron.lib.connectors.ManyToOneConnectTrans method) -
  • -
  • (transactron.lib.connectors.Pipe method) -
  • -
  • (transactron.lib.connectors.StableSelectingNetwork method) -
  • -
  • (transactron.lib.dependencies.DependencyManager method) -
  • -
  • (transactron.lib.fifo.BasicFifo method) -
  • -
  • (transactron.lib.fifo.Semaphore method) -
  • -
  • (transactron.lib.logging.HardwareLogger method) -
  • -
  • (transactron.lib.logging.LogKey method) -
  • -
  • (transactron.lib.logging.LogRecord method) -
  • -
  • (transactron.lib.logging.LogRecordInfo method) -
  • -
  • (transactron.lib.metrics.FIFOLatencyMeasurer method) -
  • -
  • (transactron.lib.metrics.HardwareMetricsManager method) -
  • -
  • (transactron.lib.metrics.HwCounter method) -
  • -
  • (transactron.lib.metrics.HwExpHistogram method) -
  • -
  • (transactron.lib.metrics.HwMetric method) -
  • -
  • (transactron.lib.metrics.HwMetricsEnabledKey method) -
  • -
  • (transactron.lib.metrics.MetricModel method) -
  • -
  • (transactron.lib.metrics.MetricRegisterModel method) -
  • -
  • (transactron.lib.metrics.TaggedCounter method) -
  • -
  • (transactron.lib.metrics.TaggedLatencyMeasurer method) -
  • -
  • (transactron.lib.reqres.ArgumentsToResultsZipper method) -
  • -
  • (transactron.lib.reqres.Serializer method) -
  • -
  • (transactron.lib.storage.AsyncMemoryBank method) -
  • -
  • (transactron.lib.storage.ContentAddressableMemory method) -
  • -
  • (transactron.lib.storage.MemoryBank method) -
  • -
  • (transactron.lib.transformers.CatTrans method) -
  • -
  • (transactron.lib.transformers.Collector method) -
  • -
  • (transactron.lib.transformers.ConnectAndMapTrans method) -
  • -
  • (transactron.lib.transformers.MethodFilter method) -
  • -
  • (transactron.lib.transformers.MethodMap method) -
  • -
  • (transactron.lib.transformers.MethodProduct method) -
  • -
  • (transactron.lib.transformers.MethodTryProduct method) -
  • -
  • (transactron.lib.transformers.Unifier method) -
  • -
  • (transactron.profiler.MethodSamples method) -
  • -
  • (transactron.profiler.Profile method) -
  • -
  • (transactron.profiler.ProfileData method) -
  • -
  • (transactron.profiler.ProfileInfo method) -
  • -
  • (transactron.profiler.ProfileSamples method) -
  • -
  • (transactron.profiler.RunStat method) -
  • -
  • (transactron.profiler.RunStatNode method) -
  • -
  • (transactron.profiler.TransactionSamples method) -
  • -
  • (transactron.testing.infrastructure.PysimSimulator method) -
  • -
  • (transactron.testing.infrastructure.SimpleTestCircuit method) -
  • -
  • (transactron.testing.method_mock.MethodMock method) -
  • -
  • (transactron.testing.testbenchio.CallTrigger method) -
  • -
  • (transactron.testing.testbenchio.TestbenchIO method) -
  • -
  • (transactron.testing.tick_count.TicksKey method) -
  • -
  • (transactron.utils.amaranth_ext.coding.Decoder method) -
  • -
  • (transactron.utils.amaranth_ext.coding.Encoder method) -
  • -
  • (transactron.utils.amaranth_ext.coding.GrayDecoder method) -
  • -
  • (transactron.utils.amaranth_ext.coding.GrayEncoder method) -
  • -
  • (transactron.utils.amaranth_ext.coding.PriorityEncoder method) -
  • -
  • (transactron.utils.amaranth_ext.elaboratables.ModuleConnector method) -
  • -
  • (transactron.utils.amaranth_ext.elaboratables.MultiPriorityEncoder method) -
  • -
  • (transactron.utils.amaranth_ext.elaboratables.RingMultiPriorityEncoder method) -
  • -
  • (transactron.utils.amaranth_ext.elaboratables.RoundRobin method) -
  • -
  • (transactron.utils.amaranth_ext.elaboratables.Scheduler method) -
  • -
  • (transactron.utils.depcache.DependentCache method) -
  • -
  • (transactron.utils.dependencies.DependencyContext method) -
  • -
  • (transactron.utils.dependencies.DependencyManager method) -
  • -
  • (transactron.utils.gen.GeneratedLog method) -
  • -
  • (transactron.utils.gen.GenerationInfo method) -
  • -
  • (transactron.utils.gen.MetricLocation method) -
  • -
  • (transactron.utils.idgen.IdGenerator method)
  • @@ -513,8 +346,6 @@

    _

  • (coreblocks.func_blocks.fu.zbc.ZbcFn.Fn method)
  • (coreblocks.func_blocks.fu.zbs.ZbsFunction.Fn method) -
  • -
  • (transactron.graph.Direction method)
  • @@ -548,60 +379,28 @@

    A

  • accept_res (coreblocks.cache.iface.CacheInterface attribute)
  • ack (coreblocks.peripherals.wishbone.WishboneInterface attribute) -
  • -
  • Adapter (class in transactron.lib.adapters) -
  • -
  • AdapterBase (class in transactron.lib.adapters) -
  • -
  • AdapterTrans (class in transactron.lib.adapters)
  • ADD (coreblocks.arch.isa_consts.Funct3 attribute)
  • -
  • add() (transactron.lib.metrics.HwExpHistogram method) -
  • -
  • add_conflict() (transactron.core.transaction_base.TransactionBase method) -
  • -
  • add_dependency() (transactron.lib.dependencies.DependencyManager method) - -
  • add_field() (coreblocks.priv.csr.aliased.AliasedCSR method) -
  • -
  • add_mock() (transactron.testing.infrastructure.TestCaseWithSimulator method)
  • add_read_only_field() (coreblocks.priv.csr.aliased.AliasedCSR method) -
  • -
  • add_registers() (transactron.lib.metrics.HwMetric method) -
  • -
  • add_transaction() (transactron.core.manager.TransactionManager method)
  • ADDRESS_GENERATION (coreblocks.arch.optypes.OpType attribute) -
  • -
  • adr (coreblocks.peripherals.wishbone.WishboneInterface attribute) -
  • -
  • AliasedCSR (class in coreblocks.priv.csr.aliased)
  • -
  • ArgumentsToResultsZipper (class in transactron.lib.reqres) -
  • ARITHMETIC (coreblocks.arch.optypes.OpType attribute)
  • as_value() (coreblocks.params.instr.RISCVInstr method) -
  • -
  • assertion() (transactron.lib.logging.HardwareLogger method) -
  • -
  • assign() (in module transactron.utils.assign) -
  • -
  • AssignType (class in transactron.utils.assign) -
  • -
  • async_mock_def_helper() (in module transactron.utils.transactron_helpers) -
  • -
  • AsyncMemoryBank (class in transactron.lib.storage)
  • AUIPC (coreblocks.arch.isa_consts.Opcode attribute) @@ -637,12 +424,6 @@

    A

  • (coreblocks.arch.optypes.OpType attribute)
  • -
  • auto_debug_signals() (in module transactron.utils.debug_signals) -
  • -
  • average_dict_of_lists() (in module transactron.utils.data_repr) -
  • -
  • AvoidedIf() (transactron.core.tmodule.TModule method) -
  • axil_master (coreblocks.peripherals.axi_lite.AXILiteMaster attribute)
  • AXILiteInterface (class in coreblocks.peripherals.axi_lite) @@ -669,8 +450,6 @@

    B

  • (coreblocks.arch.isa_consts.InstrType attribute)
  • -
  • BasicFifo (class in transactron.lib.fifo) -
  • BCLR (coreblocks.arch.isa_consts.Funct3 attribute)
      @@ -702,12 +481,10 @@

      B

  • BIT_MANIPULATION (coreblocks.arch.optypes.OpType attribute) -
  • -
  • BIT_ROTATION (coreblocks.arch.optypes.OpType attribute)
  • -
    • coreblocks.func_blocks.fu.fpu.fpu_error_module @@ -1162,6 +861,8 @@

      C

    • module
    + +
  • create() (coreblocks.peripherals.wishbone.WishboneSignature method) - -
  • -
  • create_simple() (transactron.utils.amaranth_ext.elaboratables.MultiPriorityEncoder static method) - -
  • CSR_IMM (coreblocks.arch.optypes.OpType attribute)
  • CSR_REG (coreblocks.arch.optypes.OpType attribute) @@ -1477,12 +1162,6 @@

    C

  • CSRRWI (coreblocks.arch.isa_consts.Funct3 attribute)
  • -
  • ctrl_path (transactron.core.tmodule.TModule property) - -
  • CTZ (coreblocks.arch.isa_consts.Funct12 attribute) @@ -1516,112 +1193,20 @@

    D

  • dat_r (coreblocks.peripherals.wishbone.WishboneInterface attribute)
  • dat_w (coreblocks.peripherals.wishbone.WishboneInterface attribute) -
  • -
  • data_const_to_dict() (in module transactron.testing.functions) -
  • -
  • data_in (transactron.lib.adapters.AdapterBase attribute) -
  • -
  • data_layout() (in module transactron.utils.data_repr) -
  • -
  • data_out (transactron.lib.adapters.AdapterBase attribute)
  • DCSR (coreblocks.arch.csr_address.CSRAddress attribute) -
  • -
  • debug() (transactron.lib.logging.HardwareLogger method)
  • debug_signals() (coreblocks.backend.annoucement.ResultAnnouncement method) - -
  • -
  • decode() (transactron.profiler.Profile static method) - -
  • -
  • Decoder (class in transactron.utils.amaranth_ext.coding)
  • DecodeStage (class in coreblocks.frontend.decoder.decode_stage)
  • decompr_reg() (coreblocks.frontend.decoder.rvc.InstrDecompress method)
  • -
  • def_counter (transactron.core.transaction_base.TransactionBase attribute) -
  • -
  • def_helper() (in module transactron.utils.transactron_helpers) -
  • -
  • def_method() (in module transactron.core.sugar) -
  • -
  • def_method_mock() (in module transactron.testing.method_mock) -
  • -
  • def_methods() (in module transactron.core.sugar) -
  • -
  • def_order (transactron.core.transaction_base.TransactionBase attribute) -
  • -
  • Default() (transactron.core.tmodule.TModule method) -
  • -
  • default_value (transactron.lib.dependencies.SimpleKey attribute) - -
  • -
  • defined (transactron.core.transaction_base.TransactionBase attribute) -
  • -
  • dependency_manager (transactron.testing.infrastructure.TestCaseWithSimulator attribute) -
  • -
  • dependency_provided() (transactron.lib.dependencies.DependencyManager method) - -
  • -
  • DependencyContext (class in transactron.utils.dependencies) -
  • - - + @@ -1686,8 +1259,6 @@

    E

    + - + - - + + -
    -
  • effect() (transactron.testing.method_mock.MethodMock static method) +
  • encode() (coreblocks.params.instr.RISCVInstr method)
  • -
  • effect_process() (transactron.testing.method_mock.MethodMock method) +
  • Encoding (class in coreblocks.frontend.decoder.instr_description)
  • -
  • Elif() (transactron.core.tmodule.TModule method) +
  • end (coreblocks.func_blocks.fu.lsu.pma.PMARegion attribute)
  • -
  • Else() (transactron.core.tmodule.TModule method) +
  • ENVIRONMENT_CALL_FROM_M (coreblocks.arch.isa_consts.ExceptionCause attribute)
  • -
  • empty_valid (transactron.lib.dependencies.DependencyKey attribute) - -
  • -
  • en (transactron.lib.adapters.AdapterBase attribute) -
  • -
  • enable() (transactron.testing.testbenchio.TestbenchIO method) -
  • -
    -
  • IN (transactron.graph.Direction attribute) -
  • -
  • incr() (transactron.lib.metrics.HwCounter method) - -
  • -
  • independent_list (transactron.core.transaction_base.TransactionBase attribute) -
  • INEXACT (coreblocks.func_blocks.fu.fpu.fpu_common.Errors attribute) -
  • -
  • info() (transactron.lib.logging.HardwareLogger method) -
  • -
  • INOUT (transactron.graph.Direction attribute)
  • insert (coreblocks.func_blocks.interface.func_protocols.FuncBlock attribute)
  • -
  • insert_edge() (transactron.graph.OwnershipGraph method) -
  • -
  • insert_node() (transactron.graph.OwnershipGraph method) -
  • -
  • insert_nops() (in module transactron.testing.input_generation) -
  • -
    -
  • ModuleConnector (class in transactron.utils.amaranth_ext.elaboratables) -
  • MPIE (coreblocks.arch.csr_address.MstatusFieldOffsets attribute)
  • MPP (coreblocks.arch.csr_address.MstatusFieldOffsets attribute) @@ -3252,8 +2409,6 @@

    M

  • (coreblocks.func_blocks.fu.mul_unit.MulFn.Fn attribute)
  • -
  • MultiPriorityEncoder (class in transactron.utils.amaranth_ext.elaboratables) -
  • MulType (class in coreblocks.func_blocks.fu.mul_unit)
  • MulUnit (class in coreblocks.func_blocks.fu.mul_unit) @@ -3272,42 +2427,16 @@

    N

  • O

    + -
    -
  • OpNOP (class in transactron.testing.input_generation) -
  • OpType (class in coreblocks.arch.optypes)
  • +
    -
    @@ -3377,14 +2490,8 @@

    P

  • P (coreblocks.arch.isa.Extension attribute)
  • params (coreblocks.peripherals.bus_adapter.BusMasterInterface attribute) -
  • -
  • parse_logging_level() (in module transactron.testing.logging)
  • pc_from_fb() (coreblocks.frontend.frontend_params.FrontendParams method) -
  • -
  • peek() (transactron.core.transaction_base.TransactionBase class method) -
  • -
  • Pipe (class in transactron.lib.connectors)
  • PipelinedUnsignedMul (class in coreblocks.func_blocks.fu.unsigned_multiplication.pipelined)
  • @@ -3478,6 +2585,8 @@

    P

  • PMPADDR45 (coreblocks.arch.csr_address.CSRAddress attribute)
  • + + - @@ -3627,10 +2704,6 @@

    R

  • R (coreblocks.arch.isa_consts.InstrType attribute)
  • RA (coreblocks.arch.isa_consts.Registers attribute) -
  • -
  • random_wait() (transactron.testing.infrastructure.TestCaseWithSimulator method) -
  • -
  • random_wait_geom() (transactron.testing.infrastructure.TestCaseWithSimulator method)
  • rd (coreblocks.params.instr.ITypeInstr attribute) @@ -3659,16 +2732,6 @@

    R

  • RegisterFile (class in coreblocks.core_structs.rf)
  • Registers (class in coreblocks.arch.isa_consts) -
  • -
  • regs (transactron.lib.metrics.MetricModel attribute) - -
  • -
  • reinitialize_fixtures() (transactron.testing.infrastructure.TestCaseWithSimulator method) -
  • -
  • relations (transactron.core.transaction_base.TransactionBase attribute)
  • REM (coreblocks.arch.isa_consts.Funct3 attribute) @@ -3676,10 +2739,6 @@

    R

  • (coreblocks.func_blocks.fu.div_unit.DivFn.Fn attribute)
  • -
  • remember() (transactron.graph.OwnershipGraph method) -
  • -
  • remember_field() (transactron.graph.OwnershipGraph method) -
  • REMU (coreblocks.arch.isa_consts.Funct3 attribute) @@ -3833,47 +2866,15 @@

    S

  • S9 (coreblocks.arch.isa_consts.Registers attribute)
  • SA (coreblocks.arch.isa_consts.Funct7 attribute) -
  • -
  • sample() (transactron.testing.testbenchio.CallTrigger method) -
  • -
  • sample_outputs() (transactron.testing.testbenchio.TestbenchIO method) -
  • -
  • sample_outputs_done() (transactron.testing.testbenchio.TestbenchIO method) -
  • -
  • sample_outputs_until_done() (transactron.testing.testbenchio.TestbenchIO method)
  • SATP (coreblocks.arch.csr_address.CSRAddress attribute)
  • SBE (coreblocks.arch.csr_address.MstatusFieldOffsets attribute)
  • SCAUSE (coreblocks.arch.csr_address.CSRAddress attribute) -
  • -
  • schedule_before() (transactron.core.transaction_base.TransactionBase method)
  • Scheduler (class in coreblocks.scheduler.scheduler) - -
  • -
  • schema() (transactron.lib.logging.LogRecordInfo class method) - -
  • SCONTEXT (coreblocks.arch.csr_address.CSRAddress attribute)
  • SCOUNTEREN (coreblocks.arch.csr_address.CSRAddress attribute) @@ -3889,8 +2890,6 @@

    S

  • sel (coreblocks.peripherals.wishbone.WishboneInterface attribute)
  • select (coreblocks.func_blocks.interface.func_protocols.FuncBlock attribute) -
  • -
  • Semaphore (class in transactron.lib.fifo)
  • SENVCFG (coreblocks.arch.csr_address.CSRAddress attribute)
  • @@ -3903,16 +2902,6 @@

    S

  • serialize_addr() (coreblocks.cache.icache.ICache method)
  • Serializer (class in coreblocks.frontend.fetch.fetch) - -
  • -
  • set() (transactron.lib.adapters.Adapter method) -
  • -
  • set_enable() (transactron.testing.testbenchio.TestbenchIO method) -
  • -
  • set_inputs() (transactron.testing.testbenchio.TestbenchIO method)
  • SEXTB (coreblocks.arch.isa_consts.Funct12 attribute) @@ -3962,12 +2951,12 @@

    S

  • ShiftFuncUnit (class in coreblocks.func_blocks.fu.shift_unit)
  • + + - -
  • signed_to_int() (in module transactron.utils.data_repr) -
  • -
  • silence_mustuse() (in module transactron.utils.transactron_helpers) -
  • SimpleCommonBusCacheRefiller (class in coreblocks.cache.refiller) -
  • -
  • SimpleKey (class in transactron.lib.dependencies) - -
  • -
  • SimpleTestCircuit (class in transactron.testing.infrastructure) -
  • -
  • simultaneous() (transactron.core.transaction_base.TransactionBase method) -
  • -
  • simultaneous_alternatives() (transactron.core.transaction_base.TransactionBase method) -
  • -
  • simultaneous_list (transactron.core.transaction_base.TransactionBase attribute)
  • SINGLE_BIT_MANIPULATION (coreblocks.arch.optypes.OpType attribute)
  • @@ -4024,14 +2995,6 @@

    S

  • SR (coreblocks.arch.isa_consts.Funct3 attribute)
  • -
  • src_loc (transactron.core.transaction_base.TransactionBase attribute) - -
  • SRET (coreblocks.arch.isa_consts.Funct12 attribute) + - - +
  • @@ -229,7 +202,7 @@

    Coreblocks

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html index 8e7824034..06c372bc7 100644 --- a/miscellany/exceptions-summary.html +++ b/miscellany/exceptions-summary.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -271,7 +270,7 @@

    Summary

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/modules-coreblocks.html b/modules-coreblocks.html index c6760c289..f0c0fa118 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -42,7 +42,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -179,7 +178,7 @@

    coreblocks

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/objects.inv b/objects.inv index 6aea754ba..6545ef748 100644 Binary files a/objects.inv and b/objects.inv differ diff --git a/problem-checklist.html b/problem-checklist.html index cd12652d6..13c5da4b0 100644 --- a/problem-checklist.html +++ b/problem-checklist.html @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -105,7 +104,7 @@

    Problem checklist

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/py-modindex.html b/py-modindex.html index 830d6b8d5..d0773e527 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -45,7 +45,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
  • Proposition of Reservation Station implementation
  • Reservation Station
  • @@ -84,8 +83,7 @@

    Python Module Index

    - c | - t + c
    @@ -483,245 +481,6 @@

    Python Module Index

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
        coreblocks.scheduler.wakeup_select
     
    - t
    - transactron -
        - transactron.core -
        - transactron.core.keys -
        - transactron.core.manager -
        - transactron.core.method -
        - transactron.core.schedulers -
        - transactron.core.sugar -
        - transactron.core.tmodule -
        - transactron.core.transaction -
        - transactron.core.transaction_base -
        - transactron.graph -
        - transactron.lib -
        - transactron.lib.adapters -
        - transactron.lib.buttons -
        - transactron.lib.connectors -
        - transactron.lib.dependencies -
        - transactron.lib.fifo -
        - transactron.lib.logging -
        - transactron.lib.metrics -
        - transactron.lib.reqres -
        - transactron.lib.simultaneous -
        - transactron.lib.storage -
        - transactron.lib.transformers -
        - transactron.profiler -
        - transactron.testing -
        - transactron.testing.functions -
        - transactron.testing.infrastructure -
        - transactron.testing.input_generation -
        - transactron.testing.logging -
        - transactron.testing.method_mock -
        - transactron.testing.profiler -
        - transactron.testing.testbenchio -
        - transactron.testing.tick_count -
        - transactron.tracing -
        - transactron.utils -
        - transactron.utils.amaranth_ext -
        - transactron.utils.amaranth_ext.coding -
        - transactron.utils.amaranth_ext.elaboratables -
        - transactron.utils.amaranth_ext.functions -
        - transactron.utils.assign -
        - transactron.utils.data_repr -
        - transactron.utils.debug_signals -
        - transactron.utils.depcache -
        - transactron.utils.dependencies -
        - transactron.utils.gen -
        - transactron.utils.idgen -
        - transactron.utils.transactron_helpers -
    @@ -733,7 +492,7 @@

    Python Module Index

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

    diff --git a/scheduler/overview.html b/scheduler/overview.html index 7a4b54f61..72208ab67 100644 --- a/scheduler/overview.html +++ b/scheduler/overview.html @@ -21,7 +21,7 @@ - + @@ -44,7 +44,6 @@
  • Introduction
  • List of assumptions made during development
  • Development environment
  • -
  • Documentation for Coreblocks transaction framework
  • Scheduler overview
    • Description
    • Schema
    • @@ -138,7 +137,7 @@

      More detailed description of each block - + @@ -146,7 +145,7 @@

      More detailed description of each block

      © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

      diff --git a/search.html b/search.html index 1b5f3fecf..7a056ff9f 100644 --- a/search.html +++ b/search.html @@ -45,7 +45,6 @@
    • Introduction
    • List of assumptions made during development
    • Development environment
    • -
    • Documentation for Coreblocks transaction framework
    • Scheduler overview
    • Proposition of Reservation Station implementation
    • Reservation Station
    • @@ -101,7 +100,7 @@

      © Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-11-25. + Last updated on 14:48 2024-11-25.

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36, 39], "special": [5, 27, 39], "respect": [5, 21, 39], "thu": [5, 39], "encod": [5, 10, 18, 28, 37, 39, 41, 42], "wa": [5, 10, 11, 21, 22, 25, 28, 36, 37, 38, 39, 40, 41], "chosen": [5, 28], "wai": [5, 7, 13, 19, 25, 28, 35, 36, 38, 39, 41, 42], "suffici": 5, "check": [5, 11, 14, 15, 25, 28, 31, 33, 34, 35, 38, 39, 41], "lowest": [5, 38], "two": [5, 7, 21, 28, 31, 35, 36, 38, 39, 41], "third": [5, 38, 39], "about": [5, 11, 18, 25, 27, 37, 39, 41], "becaus": [5, 28, 36, 37, 38, 39, 40], "tweak": 5, "helper": 5, "prefer": [5, 19, 36], "us": [5, 6, 7, 10, 11, 13, 15, 16, 18, 19, 21, 22, 23, 27, 28, 31, 35, 36, 38, 39, 40, 41, 42], "cfi": [5, 11], "static": [5, 18, 37, 38, 40, 41, 42], "is_branch": 5, "amaranth": [5, 7, 9, 10, 11, 13, 18, 19, 21, 31, 35, 36, 37, 38, 39, 40, 41, 42], "hdl": [5, 7, 9, 10, 13, 18, 21, 37, 38, 39, 40, 41, 42], "_ast": [5, 7, 9, 10, 13, 18, 21, 38, 39, 40, 41, 42], "valuecast": [5, 9, 10, 18, 21, 38, 39, 40, 41, 42], "is_jal": 5, "is_jalr": 5, "valid": [5, 13, 19, 23, 33, 39, 40, 41, 42], "do": [5, 10, 28, 31, 36, 38, 39, 40, 42], "confus": 5, "address_gener": 5, "arithmet": [5, 14], "bit_manipul": 5, "bit_rot": 5, "compar": [5, 27, 39], "csr_imm": 5, "csr_reg": 5, "div_rem": 5, "caus": [5, 18, 22, 28, 39, 41], "befor": [5, 15, 19, 22, 25, 31, 32, 36, 38, 39], "execut": [5, 6, 13, 19, 23, 25, 27, 32, 34, 36, 37, 38, 39, 40], "logic": [5, 15, 28, 34, 35, 36], "33": 5, "single_bit_manipul": 5, "unary_bit_manipulation_1": 5, "unary_bit_manipulation_2": 5, "unary_bit_manipulation_3": 5, "unary_bit_manipulation_4": 5, "unary_bit_manipulation_5": 5, "unknown": [5, 25, 37, 39, 41], "resultannounc": 6, "elaborat": [6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 19, 21, 22, 23, 36, 37, 38, 39, 40, 41], "simpl": [6, 7, 10, 15, 21, 23, 38, 39, 41, 42], "It": [6, 10, 11, 13, 15, 16, 18, 19, 21, 23, 25, 28, 32, 33, 35, 36, 37, 38, 39, 40, 41, 42], "take": [6, 10, 14, 19, 32, 33, 36, 38, 39, 40, 41], "its": [6, 10, 18, 21, 23, 28, 35, 36, 38, 39, 40, 41, 42], "mark": [6, 27, 28, 37], "complet": [6, 19, 21, 28], "also": [6, 11, 18, 25, 35, 36, 39, 40], "sent": [6, 19], "get_result": [6, 17, 39], "serial": [6, 11, 15, 39], "so": [6, 18, 19, 28, 35, 36, 37, 38, 39, 42], "we": [6, 7, 19, 28, 32, 33, 34, 35, 36, 39, 40], "more": [6, 21, 25, 27, 28, 39, 40, 41, 42], "than": [6, 28, 39, 41, 42], "connect": [6, 10, 19, 21, 28, 36, 38, 39, 42], "manytooneconnecttran": [6, 39], "rob_mark_don": 6, "rs_updat": 6, "rf_write": 6, "instanc": [6, 7, 10, 11, 15, 18, 23, 35, 37, 38, 39, 41, 42], "next": [6, 7, 10, 11, 23, 28, 38, 40, 42], "readi": [6, 7, 19, 21, 23, 27, 33, 37, 38, 39, 42], "assum": [6, 13, 28, 39, 41], "differ": [6, 13, 19, 25, 26, 28, 31, 35, 38, 39, 40, 41, 42], "end": [6, 15, 28, 38, 39, 42], "without": [6, 23, 28, 38, 39, 41], "pass": [6, 25, 27, 35, 38, 39, 40, 41], "finish": [6, 19, 22, 39], "rob_peek": 6, "rob_retir": 6, "r_rat_commit": 6, "r_rat_peek": 6, "free_rf_put": 6, "rf_free": 6, "exception_cause_get": 6, "exception_cause_clear": 6, "frat_renam": 6, "fetch_continu": 6, "instr_decr": 6, "trap_entri": 6, "async_interrupt_caus": 6, "cacheinterfac": [7, 11], "associ": [7, 18, 39], "replac": [7, 16, 18, 21, 33], "polici": 7, "pseudo": 7, "random": [7, 40], "scheme": 7, "everi": [7, 13, 19, 25, 35, 38, 39, 40], "trash": 7, "select": [7, 10, 13, 17, 19, 23, 25, 39, 42], "keep": [7, 38], "global": [7, 28], "abstract": [7, 16, 18, 35, 39, 41], "awai": 7, "need": [7, 11, 18, 19, 25, 28, 33, 36, 38, 39, 40], "refiller_start": 7, "whenev": [7, 18, 39], "refiller_accept": 7, "written": [7, 21, 34, 35, 39], "last": [7, 22, 23, 38, 39, 42], "when": [7, 15, 18, 19, 22, 25, 28, 31, 33, 34, 36, 38, 39, 40, 41, 42], "either": [7, 18, 19, 22, 36, 38, 39, 40, 41, 42], "transfer": [7, 19, 38, 39], "over": [7, 21, 38, 39, 40], "shouldn": [7, 35], "until": [7, 11, 28, 39, 40], "start": [7, 13, 15, 19, 22, 28, 38, 39, 42], "layout": [7, 10, 11, 14, 19, 23, 25, 31, 36, 38, 39, 40, 41], "icachelayout": 7, "icacheparamet": [7, 18], "cacherefillerinterfac": 7, "creat": [7, 16, 18, 19, 25, 35, 36, 38, 39, 40, 41, 42], "input": [7, 10, 13, 14, 19, 21, 22, 28, 33, 34, 36, 38, 39, 40, 42], "start_refil": 7, "accept_refil": 7, "deserialize_addr": 7, "raw_addr": 7, "dict": [7, 19, 36, 37, 38, 39, 40, 41, 42], "serialize_addr": 7, "addr": [7, 15, 19, 39], "view": [7, 13, 15, 38, 39, 41, 42], "icachebypass": 7, "bus_mast": 7, "busmasterinterfac": [7, 9, 15, 19], "haselabor": [7, 17, 19, 37, 38, 39, 40, 42], "protocol": [7, 17, 19, 37, 38, 39], "whole": [7, 26, 28, 39], "given": [7, 9, 15, 18, 21, 25, 33, 36, 37, 38, 39, 40, 41, 42], "simplecommonbuscacherefil": 7, "frat": 8, "rrat": 8, "registerfil": 8, "reorderbuff": [8, 22], "corefrontend": 9, "consume_instr": 9, "consum": [9, 11], "resume_from_except": 9, "resum": 9, "pc": [9, 27], "resume_from_unsaf": 9, "unsaf": 9, "stall": [9, 19, 28], "instr_bu": 9, "frontendparam": 9, "fb_addr": 9, "fb_instr_idx": 9, "pc_from_fb": 9, "decodestag": 10, "instanti": [10, 38], "instrdecod": 10, "make": [10, 13, 25, 26, 28, 31, 35, 36, 37, 40], "actual": [10, 25, 27, 36], "combinatori": [10, 36], "manner": [10, 19], "get_raw": 10, "push_decod": 10, "raw": 10, "previou": [10, 11, 14, 19, 28, 39], "step": [10, 11, 23, 25, 28, 35, 36], "fetchlayout": [10, 11], "describ": [10, 11, 15, 23, 28, 35, 37, 38, 39, 40], "decodelayout": [10, 23], "elementari": 10, "etc": [10, 36, 40], "via": [10, 22, 36, 38, 39], "signal": [10, 13, 15, 19, 21, 22, 27, 31, 37, 38, 39, 40, 41, 42], "out": [10, 13, 16, 19, 22, 26, 27, 37, 38, 39, 42], "funct3_v": 10, "seven": 10, "funct7_v": 10, "twelv": 10, "funct12_v": 10, "rd": [10, 18], "reg_cnt_log": 10, "rd_v": 10, "rs1": [10, 18], "hold": [10, 18, 19, 39], "first": [10, 13, 15, 21, 23, 28, 33, 34, 35, 36, 38, 39, 40, 41, 42], "rs1_v": 10, "rs2": [10, 18], "second": [10, 13, 21, 23, 33, 34, 35, 39, 42], "rs2_v": 10, "imm": [10, 18], "immedi": [10, 18, 19], "were": [10, 28, 36, 40], "succ": 10, "successor": 10, "pred": 10, "predecessor": 10, "fm": 10, "sourc": [10, 21, 23, 25, 33, 37, 38, 39], "defin": [10, 15, 21, 36, 38, 39, 40, 41, 42], "kind": [10, 13, 23, 39, 41], "illeg": [10, 18], "success": [10, 19, 40], "fit": 10, "constructor": [10, 36, 38, 41], "repres": [10, 21, 38, 39], "exist": [10, 36], "instr_type_overrid": 10, "specifi": [10, 19, 21, 34, 39, 41], "determin": [10, 11, 28, 35, 39, 41], "instrust": 10, "almost": 10, "correct": [10, 11, 15, 28, 33, 34, 35], "rd_zero": 10, "bool": [10, 15, 18, 21, 37, 38, 39, 40, 41, 42], "constant": 10, "other": [10, 18, 21, 25, 27, 36, 37, 38, 39, 42], "accordingli": 10, "default": [10, 19, 21, 25, 36, 37, 38, 39, 41, 42], "fals": [10, 13, 15, 25, 36, 37, 38, 39, 41, 42], "rs1_zero": 10, "instrdecompress": 10, "decompr_reg": 10, "rvc_reg": 10, "instr_mux": 10, "sel": [10, 19], "list": [10, 13, 18, 19, 25, 27, 31, 35, 37, 38, 39, 40, 41, 42], "tupl": [10, 11, 13, 19, 21, 23, 37, 38, 39, 40, 41, 42], "is_instr_compress": 10, "fetchunit": 11, "superscalar": 11, "respons": [11, 13, 15, 19, 23, 25, 38, 39], "retriev": [11, 15, 39], "them": [11, 25, 28, 35, 36, 38, 39, 41], "work": [11, 23, 28, 31, 35, 36, 38, 39, 40], "chunk": 11, "fetch_block_byt": 11, "relat": [11, 28, 38, 39, 41], "how": [11, 18, 21, 25, 28, 33, 35, 38, 39], "mani": [11, 18, 21, 25, 28, 35, 36, 37, 38, 39, 40, 41], "onc": [11, 35, 36, 38, 39, 42], "vari": 11, "deal": 11, "expand": 11, "aren": [11, 28, 36, 39], "boundari": [11, 28], "cont": 11, "predecod": 11, "analysi": [11, 27, 37], "jump": [11, 18, 28], "find": [11, 25, 28, 39], "target": [11, 35, 39], "Its": [11, 14, 15, 32, 36], "role": [11, 36], "give": [11, 39, 41], "quick": 11, "feedback": 11, "potenti": [11, 32], "predictor": 11, "help": [11, 25, 28, 39], "redirect": 11, "promptli": 11, "predictioncheck": 11, "predict": 11, "checker": [11, 15], "look": [11, 28, 39], "taken": [11, 21, 23, 35, 38, 39], "mistak": [11, 31], "ones": [11, 36], "wrong": [11, 28], "element": [11, 28, 39], "dispatch": [11, 28, 32, 33, 34], "new": [11, 13, 15, 19, 22, 27, 28, 38, 39, 41, 42], "batch": 11, "onli": [11, 13, 18, 19, 21, 22, 28, 35, 36, 37, 38, 39, 40, 41, 42], "temporari": [11, 21], "workaround": 11, "buffer": [11, 19, 28, 33, 39, 42], "rest": [11, 38], "becom": [11, 19], "elem_layout": 11, "structlayout": [11, 15, 38, 39, 40, 41], "collect": [11, 26, 35, 37, 38, 39, 40, 41, 42], "abc": [11, 18, 38, 39, 40, 41, 42], "iter": [11, 17, 18, 38, 39, 40, 41, 42], "shapelik": [11, 38, 39, 40, 41], "layoutlist": [11, 38, 39, 40, 41], "fpu": [12, 13], "fpu_common": [12, 13], "fpu_error_modul": [12, 13], "fpu_rounding_modul": [12, 13], "lsu": [12, 13], "dummylsu": [12, 13], "lsu_request": [12, 13], "pma": [12, 13], "unsigned_multipl": [12, 13], "common": [12, 13, 19, 38, 39, 41], "fast_recurs": [12, 13], "sequenc": [12, 13, 23, 38, 39, 41], "alucompon": 13, "functionalcomponentparam": [13, 15, 18], "zba_en": 13, "zbb_enabl": 13, "get_modul": [13, 15, 18], "funcunit": [13, 15, 17, 18], "get_optyp": [13, 15, 18], "alufuncunit": 13, "alu_fn": 13, "alufn": 13, "divcompon": 13, "ipc": [13, 35], "div_fn": 13, "divfn": 13, "decodermanag": 13, "fn": 13, "get_instruct": 13, "implement": [13, 15, 19, 21, 26, 27, 28, 32, 39, 41, 42], "format": [13, 25, 35, 36, 37, 38, 39, 41, 42], "divunit": 13, "get_input": 13, "arg": [13, 19, 36, 37, 38, 39, 40, 41, 42], "exceptionfuncunit": 13, "unit_fn": 13, "exceptionunitfn": 13, "exceptionunitcompon": 13, "jumpbranchfuncunit": 13, "jb_fn": 13, "jumpbranchfn": 13, "jumpcompon": 13, "mulcompon": 13, "mul_unit_typ": 13, "multyp": 13, "dsp_width": [13, 16], "mul_fn": 13, "mulfn": 13, "hot": [13, 28, 39, 42], "wire": 13, "recursive_mul": 13, "fastest": 13, "multipli": [13, 16], "costli": [13, 28], "term": 13, "resourc": [13, 22, 28, 35, 36, 38], "sequence_mul": 13, "dsp": [13, 16], "balanc": 13, "between": [13, 15, 25, 28, 36, 38, 39, 40, 41, 42], "cost": [13, 27, 36], "shift_mul": 13, "cheapest": 13, "russian": [13, 16], "peasant": [13, 16], "algorithm": [13, 16, 39], "mulunit": 13, "unsign": [13, 16], "standard": [13, 22, 28, 35, 39, 40, 42], "funcunitlayout": [13, 23], "comput": [13, 16, 18, 22, 28, 39, 41], "mul_typ": 13, "privilegedfn": 13, "classmethod": [13, 37, 38, 39, 41], "privilegedfuncunit": 13, "privilegedunitcompon": 13, "shiftfuncunit": 13, "shift_unit_fn": 13, "shiftunitfn": 13, "shiftunitcompon": 13, "clmultipli": 13, "product": [13, 39], "i1": [13, 16], "factor": 13, "i2": [13, 16], "reset": [13, 21, 27], "busi": 13, "while": [13, 38, 40], "progress": 13, "bit_width": [13, 21], "recursion_depth": 13, "depth": [13, 15, 19, 35, 39], "recurs": [13, 16, 35, 36, 37, 39, 41], "parallel": [13, 39], "power": [13, 41], "iterative_modul": 13, "recursive_modul": 13, "zbccompon": 13, "zbc_fn": 13, "zbcfn": 13, "zbcunit": 13, "zbsfunction": 13, "in1": 13, "in2": 13, "zbscompon": 13, "zbsunit": 13, "zbs_fn": 13, "division_by_zero": 14, "inexact": 14, "invalid_oper": 14, "overflow": [14, 21, 39], "underflow": 14, "fpuparam": 14, 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2, 1, "", "PMPADDR54"], [5, 2, 1, "", "PMPADDR55"], [5, 2, 1, "", "PMPADDR56"], [5, 2, 1, "", "PMPADDR57"], [5, 2, 1, "", "PMPADDR58"], [5, 2, 1, "", "PMPADDR59"], [5, 2, 1, "", "PMPADDR6"], [5, 2, 1, "", "PMPADDR60"], [5, 2, 1, "", "PMPADDR61"], [5, 2, 1, "", "PMPADDR62"], [5, 2, 1, "", "PMPADDR63"], [5, 2, 1, "", "PMPADDR7"], [5, 2, 1, "", "PMPADDR8"], [5, 2, 1, "", "PMPADDR9"], [5, 2, 1, "", "PMPCFG0"], [5, 2, 1, "", "PMPCFG1"], [5, 2, 1, "", "PMPCFG10"], [5, 2, 1, "", "PMPCFG11"], [5, 2, 1, "", "PMPCFG12"], [5, 2, 1, "", "PMPCFG13"], [5, 2, 1, "", "PMPCFG14"], [5, 2, 1, "", "PMPCFG15"], [5, 2, 1, "", "PMPCFG2"], [5, 2, 1, "", "PMPCFG3"], [5, 2, 1, "", "PMPCFG4"], [5, 2, 1, "", "PMPCFG5"], [5, 2, 1, "", "PMPCFG6"], [5, 2, 1, "", "PMPCFG7"], [5, 2, 1, "", "PMPCFG8"], [5, 2, 1, "", "PMPCFG9"], [5, 2, 1, "", "SATP"], [5, 2, 1, "", "SCAUSE"], [5, 2, 1, "", "SCONTEXT"], [5, 2, 1, "", "SCOUNTEREN"], [5, 2, 1, "", "SCOUNTINHIBIT"], [5, 2, 1, "", "SCOUNTOVF"], [5, 2, 1, "", "SENVCFG"], [5, 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1, "", "ADD"], [5, 2, 1, "", "AND"], [5, 2, 1, "", "ANDN"], [5, 2, 1, "", "B"], [5, 2, 1, "", "BCLR"], [5, 2, 1, "", "BEQ"], [5, 2, 1, "", "BEXT"], [5, 2, 1, "", "BGE"], [5, 2, 1, "", "BGEU"], [5, 2, 1, "", "BINV"], [5, 2, 1, "", "BLT"], [5, 2, 1, "", "BLTU"], [5, 2, 1, "", "BNE"], [5, 2, 1, "", "BSET"], [5, 2, 1, "", "BU"], [5, 2, 1, "", "CLMUL"], [5, 2, 1, "", "CLMULH"], [5, 2, 1, "", "CLMULR"], [5, 2, 1, "", "CLZ"], [5, 2, 1, "", "CPOP"], [5, 2, 1, "", "CSRRC"], [5, 2, 1, "", "CSRRCI"], [5, 2, 1, "", "CSRRS"], [5, 2, 1, "", "CSRRSI"], [5, 2, 1, "", "CSRRW"], [5, 2, 1, "", "CSRRWI"], [5, 2, 1, "", "CTZ"], [5, 2, 1, "", "D"], [5, 2, 1, "", "DIV"], [5, 2, 1, "", "DIVU"], [5, 2, 1, "", "DIVUW"], [5, 2, 1, "", "DIVW"], [5, 2, 1, "", "FENCE"], [5, 2, 1, "", "FENCEI"], [5, 2, 1, "", "H"], [5, 2, 1, "", "HU"], [5, 2, 1, "", "JALR"], [5, 2, 1, "", "MAX"], [5, 2, 1, "", "MAXU"], [5, 2, 1, "", "MIN"], [5, 2, 1, "", "MINU"], [5, 2, 1, "", "MUL"], [5, 2, 1, "", "MULH"], [5, 2, 1, "", "MULHSU"], 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"confus": 5, "address_gener": 5, "arithmet": [5, 14], "bit_manipul": 5, "bit_rot": 5, "compar": [5, 27], "csr_imm": 5, "csr_reg": 5, "div_rem": 5, "caus": [5, 18, 22, 28], "befor": [5, 15, 19, 22, 25, 30, 31], "execut": [5, 6, 13, 19, 23, 25, 27, 31, 33], "logic": [5, 15, 28, 33, 34], "33": 5, "single_bit_manipul": 5, "unary_bit_manipulation_1": 5, "unary_bit_manipulation_2": 5, "unary_bit_manipulation_3": 5, "unary_bit_manipulation_4": 5, "unary_bit_manipulation_5": 5, "unknown": [5, 25], "resultannounc": 6, "elaborat": [6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 19, 21, 22, 23], "simpl": [6, 7, 10, 15, 21, 23], "It": [6, 10, 11, 13, 15, 16, 18, 19, 21, 23, 25, 28, 31, 32, 34], "take": [6, 10, 14, 19, 31, 32], "its": [6, 10, 18, 21, 23, 28, 34], "mark": [6, 27, 28], "complet": [6, 19, 21, 28], "also": [6, 11, 18, 25, 34], "sent": [6, 19], "get_result": [6, 17], "serial": [6, 11, 15], "so": [6, 18, 19, 28, 34], "we": [6, 7, 19, 28, 31, 32, 33, 34], "more": [6, 21, 25, 27, 28], "than": [6, 28], "connect": [6, 10, 19, 21, 28], "manytooneconnecttran": 6, "fifo": [6, 28], "rob_mark_don": 6, "rs_updat": 6, "rf_write": 6, "instanc": [6, 7, 10, 11, 15, 18, 23, 34], "next": [6, 7, 10, 11, 23, 28], "readi": [6, 7, 19, 21, 23, 27, 32], "assum": [6, 13, 28], "differ": [6, 13, 19, 25, 26, 28, 30, 34], "end": [6, 15, 28], "without": [6, 23, 28], "pass": [6, 25, 34], "finish": [6, 19, 22], "debug_sign": 6, "rob_peek": 6, "rob_retir": 6, "r_rat_commit": 6, "r_rat_peek": 6, "free_rf_put": 6, "rf_free": 6, "exception_cause_get": 6, "exception_cause_clear": 6, "frat_renam": 6, "fetch_continu": 6, "instr_decr": 6, "trap_entri": 6, "async_interrupt_caus": 6, "cacheinterfac": [7, 11], "associ": [7, 18], "replac": [7, 16, 18, 21, 32], "polici": 7, "pseudo": 7, "random": 7, "scheme": 7, "everi": [7, 13, 19, 25, 34], "trash": 7, "select": [7, 10, 13, 17, 19, 23, 25], "keep": 7, "global": [7, 28], "abstract": [7, 16, 18, 34], "awai": 7, "need": [7, 11, 18, 19, 25, 28, 32], "refiller_start": 7, "whenev": [7, 18], "refiller_accept": 7, "written": [7, 21, 33, 34], "last": [7, 22, 23], "when": [7, 15, 18, 19, 22, 25, 28, 30, 32, 33], "either": [7, 18, 19, 22], "transfer": [7, 19], "over": [7, 21], "shouldn": [7, 34], "until": [7, 11, 28], "start": [7, 13, 15, 19, 22, 28], "layout": [7, 10, 11, 14, 19, 23, 25, 30], "icachelayout": 7, "icacheparamet": [7, 18], "cacherefillerinterfac": 7, "creat": [7, 16, 18, 19, 25, 34], "input": [7, 10, 13, 14, 19, 21, 22, 28, 32, 33], "start_refil": 7, "accept_refil": 7, "deserialize_addr": 7, "raw_addr": 7, "dict": [7, 19], "serialize_addr": 7, "addr": [7, 15, 19], "view": [7, 13, 15], "icachebypass": 7, "bus_mast": 7, "busmasterinterfac": [7, 9, 15, 19], "haselabor": [7, 17, 19], "protocol": [7, 17, 19], "whole": [7, 26, 28], "given": [7, 9, 15, 18, 21, 25, 32], "simplecommonbuscacherefil": 7, "frat": 8, "rrat": 8, "registerfil": 8, "reorderbuff": [8, 22], "corefrontend": 9, "consume_instr": 9, "consum": [9, 11], "resume_from_except": 9, "resum": 9, "pc": [9, 27], "resume_from_unsaf": 9, "unsaf": 9, "stall": [9, 19, 28], "instr_bu": 9, "frontendparam": 9, "fb_addr": 9, "fb_instr_idx": 9, "pc_from_fb": 9, "decodestag": 10, "instanti": 10, "instrdecod": 10, "make": [10, 13, 25, 26, 28, 30, 34], "actual": [10, 25, 27], "combinatori": 10, "manner": [10, 19], "get_raw": 10, "push_decod": 10, "raw": 10, "previou": [10, 11, 14, 19, 28], "step": [10, 11, 23, 25, 28, 34], "fetchlayout": [10, 11], "describ": [10, 11, 15, 23, 28, 34], "decodelayout": [10, 23], "elementari": 10, "etc": 10, "via": [10, 22], "signal": [10, 13, 15, 19, 21, 22, 27, 30], "gen": [10, 13, 16], "out": [10, 13, 16, 19, 22, 26, 27], "funct3_v": 10, "seven": 10, "funct7_v": 10, "twelv": 10, "funct12_v": 10, "rd": [10, 18], "reg_cnt_log": 10, "rd_v": 10, "rs1": [10, 18], "hold": [10, 18, 19], "first": [10, 13, 15, 21, 23, 28, 32, 33, 34], "rs1_v": 10, "rs2": [10, 18], "second": [10, 13, 21, 23, 32, 33, 34], "rs2_v": 10, "imm": [10, 18], "immedi": [10, 18, 19], "were": [10, 28], "succ": 10, "successor": 10, "pred": 10, "predecessor": 10, "fm": 10, "sourc": [10, 21, 23, 25, 32], "defin": [10, 15, 21], "kind": [10, 13, 23], "illeg": [10, 18], "success": [10, 19], "fit": 10, "constructor": 10, "repres": [10, 21], "exist": 10, "instr_type_overrid": 10, "specifi": [10, 19, 21, 33], "determin": [10, 11, 28, 34], "instrust": 10, "almost": 10, "correct": [10, 11, 15, 28, 32, 33, 34], "rd_zero": 10, "bool": [10, 15, 18, 21], "constant": 10, "other": [10, 18, 21, 25, 27], "accordingli": 10, "default": [10, 19, 21, 25], "fals": [10, 13, 15, 25], "rs1_zero": 10, "instrdecompress": 10, "decompr_reg": 10, "rvc_reg": 10, "instr_mux": 10, "sel": [10, 19], "list": [10, 13, 18, 19, 25, 27, 30, 34], "tupl": [10, 11, 13, 19, 21, 23], "is_instr_compress": 10, "fetchunit": 11, "superscalar": 11, "respons": [11, 13, 15, 19, 23, 25], "retriev": [11, 15], "them": [11, 25, 28, 34], "work": [11, 23, 28, 30, 34], "chunk": 11, "fetch_block_byt": 11, "relat": [11, 28], "how": [11, 18, 21, 25, 28, 32, 34], "mani": [11, 18, 21, 25, 28, 34], "onc": [11, 34], "vari": 11, "deal": 11, "expand": 11, "manag": [11, 13, 25, 27], "aren": [11, 28], "boundari": [11, 28], "cont": 11, "predecod": 11, "analysi": [11, 27], "jump": [11, 18, 28], "find": [11, 25, 28], "target": [11, 34], "Its": [11, 14, 15, 31], "role": 11, "give": 11, "quick": 11, "feedback": 11, "potenti": [11, 31], "predictor": 11, "help": [11, 25, 28], "redirect": 11, "promptli": 11, "predictioncheck": 11, "predict": 11, "checker": [11, 15], "look": [11, 28], "taken": [11, 21, 23, 34], "mistak": [11, 30], "ones": 11, "wrong": [11, 28], "element": [11, 28], "dispatch": [11, 28, 31, 32, 33], "new": [11, 13, 15, 19, 22, 27, 28], "batch": 11, "onli": [11, 13, 18, 19, 21, 22, 28, 34], "temporari": [11, 21], "workaround": 11, "buffer": [11, 19, 28, 32], "rest": 11, "becom": [11, 19], "elem_layout": 11, "lib": [11, 21], "structlayout": [11, 15], "collect": [11, 26, 34], "abc": [11, 18], "iter": [11, 17, 18], "shapelik": 11, "layoutlist": 11, "fpu": [12, 13], "fpu_common": [12, 13], "fpu_error_modul": [12, 13], "fpu_rounding_modul": [12, 13], "lsu": [12, 13], "dummylsu": [12, 13], "lsu_request": [12, 13], "pma": [12, 13], "unsigned_multipl": [12, 13], "common": [12, 13, 19], "fast_recurs": [12, 13], "sequenc": [12, 13, 23], "alucompon": 13, "functionalcomponentparam": [13, 15, 18], "zba_en": 13, "zbb_enabl": 13, "get_modul": [13, 15, 18], "funcunit": [13, 15, 17, 18], "get_optyp": [13, 15, 18], "alufuncunit": 13, "alu_fn": 13, "alufn": 13, "divcompon": 13, "ipc": [13, 34], "div_fn": 13, "divfn": 13, "decodermanag": 13, "fn": 13, "get_instruct": 13, "implement": [13, 15, 19, 21, 26, 27, 28, 31], "format": [13, 25, 34], "divunit": 13, "get_input": 13, "arg": [13, 19], "exceptionfuncunit": 13, "unit_fn": 13, "exceptionunitfn": 13, "exceptionunitcompon": 13, "jumpbranchfuncunit": 13, "jb_fn": 13, "jumpbranchfn": 13, "jumpcompon": 13, "mulcompon": 13, "mul_unit_typ": 13, "multyp": 13, "dsp_width": [13, 16], "mul_fn": 13, "mulfn": 13, "hot": [13, 28], "wire": 13, "recursive_mul": 13, "fastest": 13, "multipli": [13, 16], "costli": [13, 28], "term": 13, "resourc": [13, 22, 28, 34], "sequence_mul": 13, "dsp": [13, 16], "balanc": 13, "between": [13, 15, 25, 28], "cost": [13, 27], "shift_mul": 13, "cheapest": 13, "russian": [13, 16], "peasant": [13, 16], "algorithm": [13, 16], "mulunit": 13, "unsign": [13, 16], "standard": [13, 22, 28, 34], "funcunitlayout": [13, 23], "comput": [13, 16, 18, 22, 28], "mul_typ": 13, "privilegedfn": 13, "classmethod": 13, "privilegedfuncunit": 13, "privilegedunitcompon": 13, "shiftfuncunit": 13, "shift_unit_fn": 13, "shiftunitfn": 13, "shiftunitcompon": 13, "clmultipli": 13, "product": 13, "i1": [13, 16], "factor": 13, "i2": [13, 16], "reset": [13, 21, 27], "busi": 13, "while": 13, "progress": 13, "bit_width": [13, 21], "recursion_depth": 13, "depth": [13, 15, 19, 34], "recurs": [13, 16, 34], "parallel": 13, "power": 13, "iterative_modul": 13, "recursive_modul": 13, "zbccompon": 13, "zbc_fn": 13, "zbcfn": 13, "zbcunit": 13, "zbsfunction": 13, "in1": 13, "in2": 13, "zbscompon": 13, "zbsunit": 13, "zbs_fn": 13, "division_by_zero": 14, "inexact": 14, "invalid_oper": 14, "overflow": [14, 21], "underflow": 14, "fpuparam": 14, "sig_width": 14, "significand": 14, "includ": [14, 15, 34], "implicit": 14, "exp_width": 14, "expon": 14, "roundingmod": 14, "round_down": 14, "round_nearest_awai": 14, "round_nearest_even": 14, "round_up": 14, "round_zero": 14, "fpuerrormethodlayout": 14, "fpu_param": 14, "input_inf": 14, "flag": 14, "come": 14, "purpos": [14, 28], "indic": [14, 15, 28, 33], "infin": 14, "fpuerrormodul": 14, "round": [14, 19], "error_checking_request": 14, "initi": [14, 19, 27], "error_in_layout": 14, "argument": [14, 19, 23, 25, 33, 34], "final": 14, "error_out_layout": 14, "fpuroudningmethodlayout": 14, "fpuround": 14, "rounding_request": 14, "rounding_in_layout": 14, "rounding_out_layout": 14, "lsucompon": 15, "lsudummi": 15, "veri": [15, 28], "isn": [15, 34], "compliant": [15, 34], "riscv": [15, 18, 34], "spec": [15, 22], "doesn": [15, 28, 30], "rang": 15, "processor": [15, 26, 27, 31], "master": [15, 19, 34], "lsurequest": 15, "job": [15, 28], "resili": 15, "check_align": 15, "tmodul": [15, 19, 21, 22], "postprocess_load_data": 15, "modulelik": 15, "raw_data": 15, "prepare_bytes_mask": 15, "prepare_data_to_sav": 15, "pmacheck": 15, "physic": [15, 23, 28], "mai": [15, 18, 25], "part": [15, 18, 21, 22, 28, 31], "combin": [15, 30], "circuit": [15, 34], "pmalayout": 15, "pmaregion": 15, "contigu": 15, "region": [15, 28], "both": [15, 21, 32], "begin": [15, 28], "mmio": 15, "true": [15, 18, 19, 21], "dspmulunit": 16, "clock": [16, 31, 34], "design": [16, 28], "synthesi": [16, 27], "tool": [16, 25, 34], "o": [16, 28], "same": [16, 18, 21, 25], "mulbaseunsign": 16, "unsignedmulunitlayout": 16, "recursiveunsignedmul": 16, "see": [16, 22, 30, 34], "fast": 16, "within": [16, 25], "pipelinedunsignedmul": 16, "dsp_number": 16, "sequentialunsignedmul": 16, "sequenti": [16, 19], "classic": [16, 28], "shiftunsignedmul": 16, "cheap": 16, "multi": 16, "funcblocksunifi": 17, "blockcomponentparam": [17, 18], "funcblock": [17, 18, 23], "insert": [17, 22, 23, 27, 28, 31, 32], "coreconfigur": 18, "_coreconfigurationdataclass": 18, "kwarg": [18, 19], "self": 18, "get_rs_entry_count": 18, "optypes_support": 18, "dependentcach": 18, "cfg": 18, "addr_width": [18, 19], "word_width": 18, "word": 18, "num_of_wai": 18, "num_of_sets_bit": 18, "log": [18, 19, 28], "line_bytes_log": 18, "disabl": 18, "bypass": 18, "fetch_block_bytes_log": 18, "python": [18, 25], "model": 18, "stefan": 18, "wallentowitz": 18, "http": [18, 34], "github": [18, 26, 34], "com": [18, 34], "wallento": 18, "btypeinstr": 18, "instructionfunct3typ": 18, "posit": [18, 23, 32, 33], "where": [18, 19, 23, 25, 28, 32, 33], "would": [18, 25, 28], "map": [18, 21, 27, 28], "sign": 18, "whether": [18, 34], "skip": 18, "exampl": [18, 21, 25, 27, 32], "signific": 18, "affect": [18, 34], "procedur": [18, 28], "extern": [18, 27, 34], "static_valu": 18, "ebreakinstr": 18, "itypeinstr": 18, "illegalinstr": 18, "riscvinstr": 18, "cat": [18, 34], "const": 18, "d1": 18, "jtypeinstr": 18, "as_valu": 18, "convert": 18, "concret": 18, "usual": [18, 28], "deleg": 18, "must": [18, 19], "idempot": 18, "twice": 18, "exactli": 18, "code": [18, 25, 26, 28, 30, 34], "recogn": 18, "cast": 18, "rais": [18, 28], "convers": 18, "cannot": 18, "done": [18, 28, 34], "propag": 18, "caller": [18, 25], "directli": 18, "recommend": 18, "shape": 18, "itself": [18, 28], "discov": 18, "castabl": 18, "subclass": 18, "richer": 18, "represent": 18, "shapecast": 18, "condit": [18, 25], "rtypeinstr": 18, "instructionfunct7typ": 18, "stypeinstr": 18, "utypeinstr": 18, "axiliteinterfac": 19, "abstractinterfac": 19, "abstractsignatur": 19, "read_address": 19, "axilitereadaddressinterfac": 19, "read_data": 19, "axilitereaddatainterfac": 19, "write_address": 19, "axilitewriteaddressinterfac": 19, "write_data": 19, "axilitewritedatainterfac": 19, "write_respons": 19, "axilitewriteresponseinterfac": 19, "axilitemast": 19, "axi": 19, "lite": 19, "axil_param": 19, "axiliteparamet": 19, "ra_request": 19, "channel": 19, "being": [19, 25], "ra_request_layout": 19, "rd_respons": 19, "availab": 19, "state": [19, 22, 27, 28], "rd_response_layout": 19, "wa_request": 19, "wa_request_layout": 19, "wd_request": 19, "wd_request_layout": 19, "wr_respons": 19, "wr_response_layout": 19, "axil_mast": 19, "result_handl": 19, "start_request_transact": 19, "is_address_channel": 19, "state_machine_request": 19, "request_sign": 19, "data_width": 19, "axilitesignatur": 19, "signatur": 19, "patamet": 19, "axilitemasteradapt": 19, "adapt": 19, "place": [19, 28, 32, 34], "expect": 19, "busparametersinterfac": 19, "method_layout": 19, "commonbusmastermethodlayout": 19, "request_read": 19, "underli": 19, "request_read_layout": 19, "request_writ": 19, "request_write_layout": 19, "get_read_respons": 19, "action": [19, 21], "read_response_layout": 19, "get_write_respons": 19, "write_response_layout": 19, "gain": 19, "simplifi": 19, "interchang": 19, "buse": 19, "receiv": 19, "previous": 19, "wishbonemasteradapt": 19, "wishbonemast": 19, "pipelinedwishbonemast": 19, "wb_param": 19, "wishboneparamet": 19, "max_req": 19, "limit": 19, "pend": [19, 22], "wb": 19, "request_layout": 19, "result_layout": 19, "requests_finish": 19, "generate_method_layout": 19, "wishbonearbit": 19, "arbit": 19, "slave": 19, "assert": 19, "cyc": 19, "grant": 19, "robin": 19, "num_slav": 19, "devic": 19, "slave_wb": 19, "intefac": 19, "num_mast": 19, "ack": 19, "adr": 19, "dat_r": 19, "dat_w": 19, "err": 19, "lock": [19, 25, 28], "rst": 19, "rty": 19, "stb": 19, "name": [19, 25], "wb_master": 19, "wishbonemastermethodlayout": 19, "wishbonememoryslav": 19, "underneath": 19, "keyword": 19, "thei": [19, 21, 25, 28, 31, 34], "re": [19, 28, 30], "infer": 19, "wishbonemux": 19, "muxer": 19, "multiplex": 19, "ssel_tga": 19, "corespond": 19, "tga": 19, "note": [19, 21], "stare": 19, "clear": [19, 32, 33], "delai": 19, "deassert": 19, "master_wb": 19, "singal": 19, "granular": 19, "smallest": 19, "port": 19, "capabl": 19, "wishbonesignatur": 19, "path": 19, "src_loc_at": 19, "aliasedcsr": 21, "csrregist": 21, "internalinterruptcontrol": [21, 22], "Will": 21, "soon": 21, "csr_number": 21, "virtual": [21, 25], "automat": [21, 25, 34], "csrunit": 21, "ro_bit": 21, "mask": 21, "_fu_writ": 21, "those": [21, 28], "ignor": 21, "some": [21, 28, 30], "upper": 21, "0b11": 21, "discard": 21, "init": [21, 34], "fu_write_prior": 21, "prioriti": [21, 22], "writeabl": 21, "deafult": 21, "fu_write_filtermap": 21, "valuelik": 21, "filter": [21, 25], "modifi": [21, 28], "fu_read_map": 21, "src_loc": 21, "srcloc": 21, "stack": 21, "frame": 21, "deep": 21, "locat": [21, 25, 26, 31], "altern": 21, "instead": [21, 28, 30], "add_field": 21, "bit_posit": 21, "add_read_only_field": 21, "doublecountercsr": 21, "group": 21, "increment": [21, 22], "At": 21, "low_addr": 21, "high_addr": 21, "lower": 21, "higher": 21, "synthetis": 21, "genericcsrregist": 21, "machinemodecsrregist": 21, "behaviour": [21, 34], "assign": [21, 22, 30], "csrlistkei": 21, "kei": 21, "bodi": 21, "csr_val": 21, "els": [21, 28], "side": [21, 28, 32, 33], "effect": [21, 28, 32, 33], "_fu_read": 21, "current": [21, 22, 23, 28], "read_comb": 21, "submit": 21, "combination": 21, "allow": [21, 26, 28, 34], "callabl": 21, "exceptioninformationregist": 22, "earliest": 22, "report": 22, "exceptioncauseregist": 22, "rob_get_indic": 22, "fetch_stall_except": 22, "should_update_priorii": 22, "current_caus": 22, "new_caus": 22, "coreinstructioncount": 22, "count": [22, 25], "leav": [22, 25], "decrement": 22, "compat": [22, 34], "privileg": [22, 28], "xie": 22, "xip": 22, "xstatu": 22, "interrup": 22, "plain": 22, "internal_report_level": 22, "In": [22, 23, 25, 26, 27, 33, 34], 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index 87b7c8ea2..15c1386c2 100644 --- a/shared-structs/implementation/rs-impl.html +++ b/shared-structs/implementation/rs-impl.html @@ -44,7 +44,6 @@
    • Introduction
    • List of assumptions made during development
    • Development environment
    • -
    • Documentation for Coreblocks transaction framework
    • Scheduler overview
    • Proposition of Reservation Station implementation