From 2dd30d5c4c2a282b47f4616817a6c440449dc3f3 Mon Sep 17 00:00:00 2001 From: Piotro Date: Sat, 28 Oct 2023 18:09:16 +0200 Subject: [PATCH] Align instruction sections to ICache lane size --- test/regression/memory.py | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/test/regression/memory.py b/test/regression/memory.py index 534cd0929..b184ac88e 100644 --- a/test/regression/memory.py +++ b/test/regression/memory.py @@ -5,6 +5,7 @@ from dataclasses import dataclass, replace from elftools.elf.constants import P_FLAGS from elftools.elf.elffile import ELFFile, Segment +from coreblocks.params.configurations import CoreConfiguration all = [ "ReplyStatus", @@ -155,9 +156,20 @@ def load_segment(segment: Segment, *, disable_write_protection: bool = False) -> if flags_raw & P_FLAGS.PF_X: flags |= SegmentFlags.EXECUTABLE - # append safe memory region for instruction fetch prediction - seg_end += 0x10 - data += b"\0" * 0x10 + if flags_raw & P_FLAGS.PF_X: + # align only instruction section to full icache lines + alignment = 2 ** CoreConfiguration().icache_block_size_bits + + def align_down(n: int) -> int: + return (n // alignment) * alignment + + align_front = seg_start - align_down(seg_start) + align_back = align_down(seg_end + alignment - 1) - seg_end + + data = b"\x00" * align_front + data + b"\x00" * align_back + + seg_start -= align_front + seg_end += align_back return RandomAccessMemory(range(seg_start, seg_end), flags, data)