diff --git a/coreblocks/core.py b/coreblocks/core.py
index 6dd621e90..2788efafe 100644
--- a/coreblocks/core.py
+++ b/coreblocks/core.py
@@ -5,7 +5,7 @@
 from transactron.utils.dependencies import DependencyContext
 from coreblocks.priv.traps.instr_counter import CoreInstructionCounter
 from coreblocks.func_blocks.interface.func_blocks_unifier import FuncBlocksUnifier
-from coreblocks.priv.traps.interrupt_controller import InternalInterruptController
+from coreblocks.priv.traps.interrupt_controller import ISA_RESERVED_INTERRUPTS, InternalInterruptController
 from transactron.core import Transaction, TModule
 from transactron.lib import ConnectTrans, MethodProduct
 from coreblocks.interface.layouts import *
@@ -42,7 +42,7 @@ def __init__(self, *, gen_params: GenParams):
             {
                 "wb_instr": Out(WishboneSignature(gen_params.wb_params)),
                 "wb_data": Out(WishboneSignature(gen_params.wb_params)),
-                "interrupts": In(gen_params.isa.xlen),
+                "interrupts": In(ISA_RESERVED_INTERRUPTS + gen_params.interrupt_custom_count),
             }
         )
 
diff --git a/test/test_core.py b/test/test_core.py
index c1875616d..0842de7a1 100644
--- a/test/test_core.py
+++ b/test/test_core.py
@@ -12,6 +12,7 @@
 from coreblocks.params.instr import *
 from coreblocks.params.configurations import *
 from coreblocks.peripherals.wishbone import WishboneMemorySlave
+from coreblocks.priv.traps.interrupt_controller import ISA_RESERVED_INTERRUPTS
 
 import random
 import subprocess
@@ -39,10 +40,12 @@ def elaborate(self, platform):
 
         self.core = Core(gen_params=self.gen_params)
 
-        self.interrupt_level = Signal()
-        self.interrupt_edge = Signal()
-
-        m.d.comb += self.core.interrupt_controller.custom_report.eq(Cat(self.interrupt_edge, self.interrupt_level))
+        if self.gen_params.interrupt_custom_count == 2:
+            self.interrupt_level = Signal()
+            self.interrupt_edge = Signal()
+            m.d.comb += self.core.interrupts.eq(
+                Cat(self.interrupt_edge, self.interrupt_level) << ISA_RESERVED_INTERRUPTS
+            )
 
         m.submodules.wb_mem_slave = self.wb_mem_slave
         m.submodules.wb_mem_slave_data = self.wb_mem_slave_data