diff --git a/coreblocks/core.py b/coreblocks/core.py index 1a107622c..935a789f6 100644 --- a/coreblocks/core.py +++ b/coreblocks/core.py @@ -136,10 +136,11 @@ def elaborate(self, platform): m.submodules.exception_information_register = self.exception_information_register - fetch_resume_fb, fetch_resume_unifiers = self.connections.get_dependency(FetchResumeKey()) - m.submodules.fetch_resume_unifiers = ModuleConnector(**fetch_resume_unifiers) + if self.connections.dependency_provided(FetchResumeKey()): + fetch_resume_fb, fetch_resume_unifiers = self.connections.get_dependency(FetchResumeKey()) + m.submodules.fetch_resume_unifiers = ModuleConnector(**fetch_resume_unifiers) - m.submodules.fetch_resume_connector = ConnectTrans(fetch_resume_fb, self.frontend.resume_from_unsafe) + m.submodules.fetch_resume_connector = ConnectTrans(fetch_resume_fb, self.frontend.resume_from_unsafe) m.submodules.announcement = self.announcement m.submodules.func_blocks_unifier = self.func_blocks_unifier diff --git a/coreblocks/frontend/fetch/fetch.py b/coreblocks/frontend/fetch/fetch.py index 882789fe2..d04735f7b 100644 --- a/coreblocks/frontend/fetch/fetch.py +++ b/coreblocks/frontend/fetch/fetch.py @@ -402,7 +402,12 @@ def _(): if self.gen_params.extra_verification: expect_unstall_unsafe = Signal() prev_stalled_unsafe = Signal() - unifier_ready = DependencyContext.get().get_dependency(FetchResumeKey())[0].ready + dependencies = DependencyContext.get() + if dependencies.dependency_provided(FetchResumeKey()): + unifier_ready = DependencyContext.get().get_dependency(FetchResumeKey())[0].ready + else: + unifier_ready = C(0) + m.d.sync += prev_stalled_unsafe.eq(stalled_unsafe) with m.FSM("running"): with m.State("running"): diff --git a/coreblocks/frontend/frontend.py b/coreblocks/frontend/frontend.py index f36a4fc17..f4212d342 100644 --- a/coreblocks/frontend/frontend.py +++ b/coreblocks/frontend/frontend.py @@ -62,7 +62,7 @@ def __init__(self, *, gen_params: GenParams, instr_bus: BusMasterInterface): def elaborate(self, platform): m = TModule() - if self.icache_refiller: + if self.gen_params.icache_params.enable: m.submodules.icache_refiller = self.icache_refiller m.submodules.icache = self.icache diff --git a/coreblocks/params/configurations.py b/coreblocks/params/configurations.py index 3de46e422..c2f99e858 100644 --- a/coreblocks/params/configurations.py +++ b/coreblocks/params/configurations.py @@ -155,12 +155,15 @@ def replace(self, **kwargs) -> Self: tiny_core_config = CoreConfiguration( embedded=True, func_units_config=( - RSBlockComponent([ALUComponent(), ShiftUnitComponent(), JumpComponent()], rs_entries=2), + RSBlockComponent( + [ALUComponent(), ShiftUnitComponent(), JumpComponent(), ExceptionUnitComponent()], rs_entries=2 + ), RSBlockComponent([LSUComponent()], rs_entries=2, rs_type=FifoRS), ), phys_regs_bits=basic_core_config.phys_regs_bits - 1, rob_entries_bits=basic_core_config.rob_entries_bits - 1, - allow_partial_extensions=True, # No exception unit + icache_enable=False, + user_mode=False, ) # Core configuration with all supported components diff --git a/test/params/test_configurations.py b/test/params/test_configurations.py index deedaed4f..13c0be1f3 100644 --- a/test/params/test_configurations.py +++ b/test/params/test_configurations.py @@ -28,7 +28,7 @@ class ISAStrTest: "rv32imcbzicsr_zifencei_xintmachinemode", "rv32imcbzicsr_zifencei_xintmachinemode", ), - ISAStrTest(tiny_core_config, "rv32e", "rv32", "rv32e"), + ISAStrTest(tiny_core_config, "rv32e", "rv32e", "rv32e"), ISAStrTest(test_core_config, "rv32", "rv32", "rv32i"), ] diff --git a/test/test_core.py b/test/test_core.py index 60c8b6d9c..39e2bfef3 100644 --- a/test/test_core.py +++ b/test/test_core.py @@ -13,7 +13,7 @@ from coreblocks.core import Core from coreblocks.params import GenParams from coreblocks.params.instr import * -from coreblocks.params.configurations import CoreConfiguration, basic_core_config, full_core_config +from coreblocks.params.configurations import * from coreblocks.peripherals.wishbone import WishboneMemorySlave import random @@ -136,6 +136,7 @@ def load_section(section: str): [ ("fibonacci", "fibonacci.asm", 500, {2: 2971215073}, basic_core_config), ("fibonacci_mem", "fibonacci_mem.asm", 400, {3: 55}, basic_core_config), + ("fibonacci_mem_tiny", "fibonacci_mem.asm", 250, {3: 55}, tiny_core_config), ("csr", "csr.asm", 200, {1: 1, 2: 4}, full_core_config), ("csr_mmode", "csr_mmode.asm", 1000, {1: 0, 2: 44, 3: 0, 4: 0, 5: 0, 6: 4, 15: 0}, full_core_config), ("exception", "exception.asm", 200, {1: 1, 2: 2}, basic_core_config), diff --git a/transactron/utils/dependencies.py b/transactron/utils/dependencies.py index 010b03f22..683ff58c2 100644 --- a/transactron/utils/dependencies.py +++ b/transactron/utils/dependencies.py @@ -138,6 +138,10 @@ def get_dependency(self, key: DependencyKey[Any, U]) -> U: return val + def dependency_provided(self, key: DependencyKey) -> bool: + """Checks if any dependency for a key is provided (ignores `empty_valid` parameter)""" + return key in self.dependencies + class DependencyContext: stack: list[DependencyManager] = []