From 22689446ce613b2afdbec8bc16d70b56a5677f72 Mon Sep 17 00:00:00 2001 From: tilk Date: Wed, 10 Apr 2024 08:09:01 +0000 Subject: [PATCH] Drop `unittest` from `TestCaseWithSimulator` (#642) --- .doctrees/api.doctree | Bin 21256 -> 21256 bytes .doctrees/auto_graph.doctree | Bin 55039 -> 55041 bytes .doctrees/current-graph.doctree | Bin 56260 -> 56262 bytes .doctrees/environment.pickle | Bin 510534 -> 511759 bytes .doctrees/transactron.testing.doctree | Bin 269127 -> 275301 bytes _sources/auto_graph.rst.txt | 420 ++++++++--------- api.html | 2 +- assumptions.html | 2 +- auto_graph.html | 422 +++++++++--------- components/icache.html | 2 +- coreblocks.backend.html | 2 +- coreblocks.cache.html | 2 +- coreblocks.core_structs.html | 2 +- coreblocks.frontend.decoder.html | 2 +- coreblocks.frontend.fetch.html | 2 +- coreblocks.frontend.html | 2 +- coreblocks.func_blocks.fu.html | 2 +- coreblocks.func_blocks.fu.lsu.html | 2 +- ...unc_blocks.fu.unsigned_multiplication.html | 2 +- coreblocks.func_blocks.html | 2 +- coreblocks.func_blocks.interface.html | 2 +- coreblocks.html | 2 +- coreblocks.params.html | 2 +- coreblocks.peripherals.html | 2 +- coreblocks.priv.csr.html | 2 +- coreblocks.priv.html | 2 +- coreblocks.priv.traps.html | 2 +- coreblocks.scheduler.html | 2 +- current-graph.html | 422 +++++++++--------- development-environment.html | 2 +- genindex.html | 18 +- home.html | 2 +- index.html | 2 +- miscellany/exceptions-summary.html | 2 +- modules-coreblocks.html | 2 +- modules-transactron.html | 2 +- objects.inv | Bin 10686 -> 10734 bytes problem-checklist.html | 2 +- py-modindex.html | 2 +- scheduler/overview.html | 2 +- search.html | 2 +- searchindex.js | 2 +- shared-structs/implementation/rs-impl.html | 2 +- shared-structs/rs.html | 2 +- synthesis/synthesis.html | 2 +- transactions.html | 2 +- transactron.core.html | 2 +- transactron.html | 2 +- transactron.lib.html | 2 +- transactron.testing.html | 37 +- transactron.utils.amaranth_ext.html | 2 +- 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zi9w(^T5JCrZ#!J7A+<+W+W^VNOry4rd8dhX>4vRZWP9-XLRvnL0m!N{W~DuM`Gb@2$#e< zEZAymNW6wMOYKz>Q>6182-h2>y6|{Uw8*cmtnDp}iprvrvZ$ael$V9#vQSzU3d=%S z+0{yTrscPDOxvUF5{=ZZ(o}8K8}R|^+)IcEp%A9ML{i&#$Z-AV4eK`U)UBhm0)CLp z-{#r07RAX4<)1w8FtU^eVa)W0iMQySMgZT1r1pLg4=$>W&vlJcM>8 ztO7-bOjh36kCk)IJjU+=*1t9!Fq5g>MFM+kWR!1m?eApT8zh92JxM-qC#S16T~_aH4-L?q0JD(B<>(_gv91kA-0nE5sBwWytD=4IEgQx z2JuxA-#s1T84~Ajg}8{su`?jyr>CNc>|P#G53<+;BBb6%`U`9Y`56 zb)eagzt+vUIV_nn^<0oQ>@qSV=&~bZ%x6gKD?waKLQH;_(OmdZ5^1JVhD@g3){m)R zXy~?UWwJHQ92!f81jZgFbM7D^X7$@?l7E0inu(MllZo^Fm}t9mayI)!&d@kAAu#SK zGUR(C#Eptr2thfd8b_Q&CgTqGV;n_00b7x&3nTeMLj|eg?`FG>EGv^ZPU2+}M|VNo zMdG0gARZ=h(}fTRNF2We;$;%bJWS%=8z4SU z;^iA5ULm1>7{Va&(k&3jNzg0b#V>7%S5b*K0E=CK;_#K=Ma8}pv33v~h={3EJBNbq zOr3LbNs9`siv|EW*}Tbga2)6^DhHpF%NBn9pDBMN|BISOa3s+?X}%?FG2V zdTLK%JNIap#?i1=QD{?_euSr%L-FvIUR}XAL*5!hT BasicFifo2_write - Retirement_Retirement1 --> BasicFifo2_write - TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write + Retirement_Retirement3 --> BasicFifo2_write TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write + TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write FIFO5_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write RegisterFile_perf --> HwExpHistogram2__add ReorderBuffer_perf --> HwExpHistogram4__add SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 + Serializer_Serializer1 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 @@ -642,28 +642,28 @@ SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 Forwarder2_read --> ICache_ICache1 ICache_ICache1 <--> HwCounter3__incr - Fetch_Fetch1 --> ICache_issue_req - Fetch_Fetch1 <--> HwCounter__incr - Fetch_Fetch1 <--> FIFOLatencyMeasurer__start - Fetch_Fetch1 --> FIFO1_write - Fetch_Fetch1 --> ArgumentsToResultsZipper_write_args - Fetch_Fetch1 --> BasicFifo3_write - Fetch_Fetch1 --> BasicFifo4_write - BasicFifo4_read --> Fetch_Fetch - ICache_accept_res --> Fetch_Fetch - Fetch_Fetch <--> FIFOLatencyMeasurer__stop - FIFO1_read --> Fetch_Fetch - Fetch_Fetch --> HwExpHistogram__add - ArgumentsToResultsZipper_read --> Fetch_Fetch - BasicFifo3_read --> Fetch_Fetch - Forwarder3_read --> Fetch_Fetch - Fetch_Fetch --> MethodProduct_method + Fetch_Fetch --> ICache_issue_req + Fetch_Fetch <--> HwCounter__incr + Fetch_Fetch <--> FIFOLatencyMeasurer__start + Fetch_Fetch --> FIFO1_write + Fetch_Fetch --> ArgumentsToResultsZipper_write_args + Fetch_Fetch --> BasicFifo3_write + Fetch_Fetch --> BasicFifo4_write + BasicFifo4_read --> Fetch_Fetch1 + ICache_accept_res --> Fetch_Fetch1 + Fetch_Fetch1 <--> FIFOLatencyMeasurer__stop + FIFO1_read --> Fetch_Fetch1 + Fetch_Fetch1 --> HwExpHistogram__add + ArgumentsToResultsZipper_read --> Fetch_Fetch1 + BasicFifo3_read --> Fetch_Fetch1 + Forwarder3_read --> Fetch_Fetch1 + Fetch_Fetch1 --> MethodProduct_method AdapterTrans_AdapterTrans_method --> MethodProduct_method - Fetch_Fetch --> FIFO_write + Fetch_Fetch1 --> FIFO_write AdapterTrans_AdapterTrans_method --> FIFO_write - Fetch_Fetch --> MethodMap_method + Fetch_Fetch1 --> MethodMap_method AdapterTrans_AdapterTrans_method --> MethodMap_method - Fetch_Fetch <--> CoreInstructionCounter_increment + Fetch_Fetch1 <--> CoreInstructionCounter_increment AdapterTrans_AdapterTrans_method <--> CoreInstructionCounter_increment FIFO_read --> DecodeStage_DecodeStage DecodeStage_DecodeStage <--> HwCounter6__incr @@ -673,7 +673,7 @@ RegAllocation_RegAllocation --> FIFO12_write FIFO12_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename - Retirement_Retirement1 --> FRAT_rename + Retirement_Retirement3 --> FRAT_rename TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename Renaming_Renaming --> FIFO13_write FIFO13_read --> ROBAllocation_ROBAllocation @@ -681,19 +681,19 @@ ROBAllocation_ROBAllocation <--> FIFOLatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO2_write ROBAllocation_ROBAllocation --> FIFO14_write - FIFO14_read --> RSSelection_RSSelection - RSSelection_RSSelection --> Forwarder9_write - Forwarder9_read --> RSSelection_RSSelection1 - Forwarder9_read --> RSSelection_RSSelection3 + FIFO14_read --> RSSelection_RSSelection1 + RSSelection_RSSelection1 --> Forwarder9_write Forwarder9_read --> RSSelection_RSSelection2 - RSFuncBlock_select --> RSSelection_RSSelection1 - RS_select --> RSSelection_RSSelection1 - RSSelection_RSSelection1 --> FIFO15_write - RSSelection_RSSelection3 --> FIFO15_write + Forwarder9_read --> RSSelection_RSSelection + Forwarder9_read --> RSSelection_RSSelection3 + RSFuncBlock_select --> RSSelection_RSSelection2 + RS_select --> RSSelection_RSSelection2 RSSelection_RSSelection2 --> FIFO15_write - RSFuncBlock1_select --> RSSelection_RSSelection3 - FifoRS_select --> RSSelection_RSSelection3 - RSSelection_RSSelection2 <--> CSRUnit_select + RSSelection_RSSelection --> FIFO15_write + RSSelection_RSSelection3 --> FIFO15_write + RSFuncBlock1_select --> RSSelection_RSSelection + FifoRS_select --> RSSelection_RSSelection + RSSelection_RSSelection3 <--> CSRUnit_select FIFO15_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -714,7 +714,7 @@ Collector3_method --> ConnectTrans12_ConnectTrans Forwarder8_read --> ConnectTrans12_ConnectTrans ConnectTrans12_ConnectTrans --> Fetch_resume - Retirement_Retirement3 --> Fetch_resume + Retirement_Retirement --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -728,7 +728,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add - RS_RS --> WakeupSelect_WakeupSelect + RS_RS1 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -752,10 +752,10 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter__incr WakeupSelect_WakeupSelect --> FIFO3_write - RS_RS3 --> WakeupSelect1_WakeupSelect + RS_RS4 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO4_write - RS_RS1 --> WakeupSelect2_WakeupSelect + RS_RS3 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> TaggedCounter1__incr WakeupSelect2_WakeupSelect <--> HwCounter5__incr @@ -763,12 +763,12 @@ WakeupSelect3_WakeupSelect --> BasicFifo5_write ConnectTrans8_ConnectTrans --> BasicFifo5_write ConnectTrans3_ConnectTrans --> BasicFifo5_write - TransactionManager_accept_cond1_ConnectTrans_accept_cond0 --> BasicFifo5_write TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo5_write - TransactionManager_accept_cond1_ConnectTrans --> BasicFifo5_write + TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> BasicFifo5_write + TransactionManager_ConnectTrans_accept_cond1 --> BasicFifo5_write WakeupSelect2_WakeupSelect --> FIFO6_write WakeupSelect2_WakeupSelect --> FIFO5_write - RS_RS4 --> WakeupSelect3_WakeupSelect + RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO7_write RS_RS2 --> WakeupSelect4_WakeupSelect @@ -791,18 +791,18 @@ ConnectTrans8_ConnectTrans --> BasicFifo6_write FifoRS_perf --> HwExpHistogram8__add Forwarder6_read --> LSUDummy_LSUDummy - Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 - Forwarder6_read --> TransactionManager_issue_cond2_LSUDummy + Forwarder6_read --> TransactionManager_issue_cond0_LSUDummy + Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 Forwarder6_read --> TransactionManager_issue_cond1_LSUDummy LSUDummy_LSUDummy --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write - TransactionManager_issue_cond2_LSUDummy --> FIFO8_write + TransactionManager_issue_cond0_LSUDummy --> FIFO8_write + TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write TransactionManager_issue_cond1_LSUDummy --> FIFO8_write LSUDummy_LSUDummy --> FIFO10_write WakeupSelect5_WakeupSelect --> FIFO10_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO10_write - TransactionManager_issue_cond2_LSUDummy --> FIFO10_write + TransactionManager_issue_cond0_LSUDummy --> FIFO10_write + TransactionManager_LSUDummy_issue_cond2 --> FIFO10_write TransactionManager_issue_cond1_LSUDummy --> FIFO10_write FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect @@ -835,52 +835,52 @@ CSRUnit_get_result --> ConnectTrans3_ConnectTrans MethodTryProduct_MethodTryProduct1 --> PrivilegedFuncUnit_precommit MethodTryProduct_MethodTryProduct1 <--> InterruptController_mret - MethodTryProduct_MethodTryProduct2 --> LSUDummy_precommit - MethodTryProduct_MethodTryProduct --> CSRUnit_precommit + MethodTryProduct_MethodTryProduct --> LSUDummy_precommit + MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit ConnectTrans10_ConnectTrans --> Forwarder8_write ConnectTrans11_ConnectTrans --> Forwarder8_write BasicFifo6_read --> ConnectTrans10_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans11_ConnectTrans - ReorderBuffer_peek --> Retirement_Retirement2 - ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> Retirement_Retirement1 - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 + ReorderBuffer_peek --> Retirement_Retirement2 + ReorderBuffer_peek --> Retirement_Retirement3 ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement2 --> MethodTryProduct_method - ExceptionCauseRegister_get --> Retirement_Retirement4 - ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement1 --> MethodTryProduct_method + ExceptionCauseRegister_get --> Retirement_Retirement2 ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement1 <--> ReorderBuffer_retire - TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire + ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement3 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire - Retirement_Retirement1 <--> FIFOLatencyMeasurer1__stop - TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire + Retirement_Retirement3 <--> FIFOLatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop - FIFO2_read --> Retirement_Retirement1 - FIFO2_read --> TransactionManager_Retirement_Retirement_cond1 + TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop + FIFO2_read --> Retirement_Retirement3 FIFO2_read --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement1 --> HwExpHistogram3__add - TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add + FIFO2_read --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement3 --> HwExpHistogram3__add TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add - CoreInstructionCounter_decrement --> Retirement_Retirement1 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 + TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add + CoreInstructionCounter_decrement --> Retirement_Retirement3 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 - RRAT_peek --> Retirement_Retirement1 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 + RRAT_peek --> Retirement_Retirement3 RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement1 --> RegisterFile_free - TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free + Retirement_Retirement3 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free - Retirement_Retirement1 --> TaggedLatencyMeasurer__stop - TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free + Retirement_Retirement3 --> TaggedLatencyMeasurer__stop TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop - AsyncMemoryBank_read --> Retirement_Retirement1 - AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1 + TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop + AsyncMemoryBank_read --> Retirement_Retirement3 AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement1 --> HwExpHistogram1__add - TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add + AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement3 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add - CSRRegister1_read --> Retirement_Retirement3 - Retirement_Retirement3 <--> ExceptionCauseRegister_clear + TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add + CSRRegister1_read --> Retirement_Retirement + Retirement_Retirement <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -892,35 +892,14 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt - TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy1 - TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 - TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 - TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue - TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue - TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond0 --> FIFO9_write - TransactionManager_issue_cond2_LSUDummy --> FIFO9_write - TransactionManager_issue_cond1_LSUDummy --> FIFO9_write - TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 - TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer - TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write - TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request - TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request - TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 - TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 - TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read - TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3 - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement - TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement4 + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement4 TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write - TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 + TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment @@ -929,33 +908,54 @@ CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write TransactionManager_Retirement_Retirement_cond0 <--> HwCounter7__incr - TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - Serializer1_Serializer1 --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - BasicFifo1_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - WishboneMaster1_result --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - Forwarder1_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> ConnectTrans9_ConnectTrans - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans9_ConnectTrans - TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans9_ConnectTrans - TransactionManager_accept_cond1_ConnectTrans_accept_cond0 --> Forwarder7_write - TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write - TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write - LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 - LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans - TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 + TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 + TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write + TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3 + TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write + TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write + TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request + TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request + TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue + TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond0_LSUDummy --> FIFO9_write + TransactionManager_LSUDummy_issue_cond2 --> FIFO9_write + TransactionManager_issue_cond1_LSUDummy --> FIFO9_write + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 + TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 + TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 + TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read + TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 + TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond0 LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - FIFO9_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 + LSURequester_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans FIFO9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + FIFO9_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans9_ConnectTrans + TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> ConnectTrans9_ConnectTrans + TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans9_ConnectTrans + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write + TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> Forwarder7_write + TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write + LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans + LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - Serializer1_Serializer2 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 - TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 - FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans - FIFO10_read --> TransactionManager_accept_cond1_ConnectTrans + Serializer1_Serializer1 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans + WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans + Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + Forwarder1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans + TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans + Serializer1_Serializer2 --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans + TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1 + FIFO8_read --> TransactionManager_ConnectTrans_accept_cond1 + FIFO10_read --> TransactionManager_ConnectTrans_accept_cond1 diff --git a/api.html b/api.html index 9695022e1..725879fd0 100644 --- a/api.html +++ b/api.html @@ -259,7 +259,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 17:06 2024-04-09. + Last updated on 08:08 2024-04-10.

diff --git a/assumptions.html b/assumptions.html index 3dddfe39c..448ff7f9c 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 17:06 2024-04-09. + Last updated on 08:08 2024-04-10.

diff --git a/auto_graph.html b/auto_graph.html index ed8aa6bff..4088a14f5 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -86,21 +86,21 @@ Core_InitFreeRFFifo["InitFreeRFFifo"] Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_request["request"] WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_result["result"] + WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] Forwarder_read["read"] Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] + WishboneMaster1_request["request"] WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] - WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] - Forwarder1_write["write"] Forwarder1_read["read"] + Forwarder1_write["write"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] @@ -110,34 +110,34 @@ Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_read["read"] BasicFifo_write["write"] + BasicFifo_read["read"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_request_write["request_write"] + WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_read["request_read"] - WishboneMasterAdapter1_get_read_response["get_read_response"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_read["read"] BasicFifo1_write["write"] + BasicFifo1_read["read"] end end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_decrement["decrement"] CoreInstructionCounter_increment["increment"] + CoreInstructionCounter_decrement["decrement"] end subgraph FIFO["fifo_fetch FIFO"] - FIFO_read["read"] FIFO_write["write"] + FIFO_read["read"] end subgraph MethodMap["core_counter_increment_discard_map MethodMap"] MethodMap_method["method"] @@ -146,25 +146,25 @@ MethodProduct_method["method"] end subgraph BasicFifo2["free_rf_fifo BasicFifo"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] subgraph Forwarder2["resp_fwd Forwarder"] Forwarder2_read["read"] Forwarder2_write["write"] end end subgraph ICache["icache ICache"] + ICache_MemRead["MemRead"] ICache_accept_res["accept_res"] ICache_ICache["ICache"] - ICache_MemRead["MemRead"] - ICache_ICache1["ICache"] ICache_issue_req["issue_req"] + ICache_ICache1["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -192,18 +192,18 @@ end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_peek_arg["peek_arg"] ArgumentsToResultsZipper_write_args["write_args"] ArgumentsToResultsZipper_read["read"] ArgumentsToResultsZipper_write_results["write_results"] + ArgumentsToResultsZipper_peek_arg["peek_arg"] subgraph BasicFifo3["fifo BasicFifo"] + BasicFifo3_peek["peek"] BasicFifo3_write["write"] BasicFifo3_read["read"] - BasicFifo3_peek["peek"] end subgraph Forwarder3["forwarder Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end end @@ -215,11 +215,11 @@ RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read2["read2"] - RegisterFile_perf["perf"] RegisterFile_free["free"] RegisterFile_read1["read1"] RegisterFile_write["write"] + RegisterFile_perf["perf"] + RegisterFile_read2["read2"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer__start["_start"] TaggedLatencyMeasurer__stop["_stop"] @@ -227,8 +227,8 @@ HwExpHistogram1__add["_add"] end subgraph AsyncMemoryBank["slots AsyncMemoryBank"] - AsyncMemoryBank_read["read"] AsyncMemoryBank_write["write"] + AsyncMemoryBank_read["read"] end end subgraph HwExpHistogram2["perf_num_valid HwExpHistogram"] @@ -236,21 +236,21 @@ end end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_put["put"] - ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_perf["perf"] ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_peek["peek"] ReorderBuffer_retire["retire"] + ReorderBuffer_perf["perf"] + ReorderBuffer_put["put"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] - FIFOLatencyMeasurer1__stop["_stop"] FIFOLatencyMeasurer1__start["_start"] + FIFOLatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram3["histogram HwExpHistogram"] HwExpHistogram3__add["_add"] end subgraph FIFO2["fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end end subgraph HwExpHistogram4["perf_rob_size HwExpHistogram"] @@ -258,18 +258,18 @@ end end subgraph Fetch["fetch Fetch"] - Fetch_stall_exception["stall_exception"] Fetch_Fetch["Fetch"] - Fetch_resume["resume"] + Fetch_stall_exception["stall_exception"] Fetch_Fetch1["Fetch"] + Fetch_resume["resume"] subgraph BasicFifo4["fetch_target_queue BasicFifo"] - BasicFifo4_write["write"] BasicFifo4_read["read"] + BasicFifo4_write["write"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_clear["clear"] ExceptionCauseRegister_report["report"] + ExceptionCauseRegister_clear["clear"] ExceptionCauseRegister_get["get"] subgraph BasicFifo5["fu_report_fifo BasicFifo"] BasicFifo5_write["write"] @@ -283,8 +283,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_write["write"] Forwarder4_read["read"] + Forwarder4_write["write"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -302,30 +302,30 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] + RSFuncBlock_update["update"] + RSFuncBlock_insert["insert"] RSFuncBlock_select["select"] RSFuncBlock_get_result["get_result"] - RSFuncBlock_insert["insert"] - RSFuncBlock_update["update"] subgraph RS["rs RS"] - RS_perf["perf"] - RS_RS["RS"] + RS_update["update"] RS_insert["insert"] RS_select["select"] - RS_update["update"] - RS_take["take"] + RS_RS["RS"] RS_RS1["RS"] + RS_perf["perf"] + RS_take["take"] RS_RS2["RS"] RS_RS3["RS"] RS_RS4["RS"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__stop["_stop"] TaggedLatencyMeasurer1__start["_start"] + TaggedLatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_write["write"] AsyncMemoryBank1_read["read"] + AsyncMemoryBank1_write["write"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -339,8 +339,8 @@ TaggedCounter__incr["_incr"] end subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] @@ -371,8 +371,8 @@ HwCounter5__incr["_incr"] end subgraph FIFO6["fifo_res FIFO"] - FIFO6_read["read"] FIFO6_write["write"] + FIFO6_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -390,9 +390,9 @@ WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] - PrivilegedFuncUnit_issue["issue"] - PrivilegedFuncUnit_precommit["precommit"] PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_precommit["precommit"] + PrivilegedFuncUnit_issue["issue"] subgraph BasicFifo6["fetch_resume_fifo BasicFifo"] BasicFifo6_read["read"] BasicFifo6_write["write"] @@ -404,8 +404,8 @@ subgraph Collector1["collector Collector"] Collector1_method["method"] subgraph Forwarder5["forwarder Forwarder"] - Forwarder5_write["write"] Forwarder5_read["read"] + Forwarder5_write["write"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] subgraph ConnectTrans4["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -429,18 +429,18 @@ subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] RSFuncBlock1_update["update"] RSFuncBlock1_select["select"] - RSFuncBlock1_insert["insert"] RSFuncBlock1_get_result["get_result"] + RSFuncBlock1_insert["insert"] subgraph FifoRS["rs FifoRS"] + FifoRS_select["select"] FifoRS_perf["perf"] - FifoRS_update["update"] + FifoRS_take["take"] FifoRS_FifoRS["FifoRS"] - FifoRS_select["select"] FifoRS_insert["insert"] - FifoRS_take["take"] + FifoRS_update["update"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer2__stop["_stop"] TaggedLatencyMeasurer2__start["_start"] + TaggedLatencyMeasurer2__stop["_stop"] subgraph HwExpHistogram7["histogram HwExpHistogram"] HwExpHistogram7__add["_add"] end @@ -454,37 +454,37 @@ end end subgraph LSUDummy["func_unit_0 LSUDummy"] - LSUDummy_issue["issue"] - LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_accept["accept"] LSUDummy_accept_cond0["accept_cond0"] + LSUDummy_precommit["precommit"] + LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_issue["issue"] LSUDummy_LSUDummy1["LSUDummy"] LSUDummy_accept_cond1["accept_cond1"] - LSUDummy_precommit["precommit"] - LSUDummy_accept["accept"] subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond0["issue_cond0"] - LSURequester_accept_cond0["accept_cond0"] LSURequester_accept_cond1["accept_cond1"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond0["issue_cond0"] LSURequester_issue_cond2["issue_cond2"] LSURequester_issue["issue"] LSURequester_accept["accept"] + LSURequester_accept_cond0["accept_cond0"] end subgraph Forwarder6["requests Forwarder"] Forwarder6_write["write"] Forwarder6_read["read"] end subgraph FIFO8["results_noop FIFO"] - FIFO8_write["write"] FIFO8_read["read"] + FIFO8_write["write"] end subgraph FIFO9["issued FIFO"] FIFO9_read["read"] FIFO9_write["write"] end subgraph FIFO10["issued_noop FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end end subgraph WakeupSelect5["wakeup_select_0 WakeupSelect"] @@ -493,8 +493,8 @@ subgraph Collector2["collector Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_write["write"] Forwarder7_read["read"] + Forwarder7_write["write"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans9["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -504,18 +504,18 @@ end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_insert["insert"] - CSRUnit_CSRUnit["CSRUnit"] - CSRUnit_fetch_resume["fetch_resume"] - CSRUnit_select["select"] - CSRUnit_update["update"] CSRUnit_precommit["precommit"] + CSRUnit_select["select"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_get_result["get_result"] + CSRUnit_update["update"] + CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_insert["insert"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] - MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_method["method"] + MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] end subgraph Collector3["FetchResumeKey_unifier Collector"] @@ -538,49 +538,49 @@ ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"] end subgraph InterruptController["interrupt_controller InterruptController"] - InterruptController_report_interrupt["report_interrupt"] InterruptController_entry["entry"] InterruptController_mret["mret"] + InterruptController_report_interrupt["report_interrupt"] end subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] CSRRegister__fu_read["_fu_read"] - CSRRegister_write["write"] CSRRegister__fu_write["_fu_write"] + CSRRegister_write["write"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_write["_fu_write"] - CSRRegister1_read["read"] CSRRegister1__fu_read["_fu_read"] + CSRRegister1_read["read"] + CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2__fu_read["_fu_read"] + CSRRegister2_write["write"] CSRRegister2__fu_write["_fu_write"] CSRRegister2_read["read"] - CSRRegister2_write["write"] + CSRRegister2__fu_read["_fu_read"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] + CSRRegister3_write["write"] CSRRegister3__fu_read["_fu_read"] CSRRegister3_read["read"] - CSRRegister3_write["write"] end subgraph CSRRegister4["register_high CSRRegister"] - CSRRegister4_read["read"] CSRRegister4_write["write"] CSRRegister4__fu_read["_fu_read"] + CSRRegister4_read["read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5__fu_read["_fu_read"] CSRRegister5_read["read"] CSRRegister5_write["write"] + CSRRegister5__fu_read["_fu_read"] end subgraph CSRRegister6["register_high CSRRegister"] CSRRegister6_write["write"] @@ -622,8 +622,8 @@ ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO15["rs_select_out_buf FIFO"] - FIFO15_read["read"] FIFO15_write["write"] + FIFO15_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -631,8 +631,8 @@ RSSelection_RSSelection2["RSSelection"] RSSelection_RSSelection3["RSSelection"] subgraph Forwarder9["forwarder Forwarder"] - Forwarder9_read["read"] Forwarder9_write["write"] + Forwarder9_read["read"] end end subgraph RSInsertion["rs_insertion RSInsertion"] @@ -643,14 +643,14 @@ ConnectTrans12_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement["Retirement"] - Retirement_core_state["core_state"] Retirement_Retirement1["Retirement"] Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement4["Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] + Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_core_state["core_state"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] @@ -659,9 +659,9 @@ CSRRegister7_write["write"] end subgraph CSRRegister8["register_high CSRRegister"] - CSRRegister8_read["read"] CSRRegister8__fu_read["_fu_read"] CSRRegister8_write["write"] + CSRRegister8_read["read"] end end subgraph HwCounter7["perf_instr_ret HwCounter"] @@ -681,31 +681,31 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] - TransactionManager_accept_cond1_ConnectTrans_accept_cond0["accept_cond1_ConnectTrans_accept_cond0"] - TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"] - TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] - TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] - TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] + TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] + TransactionManager_ConnectTrans_accept_cond1["ConnectTrans_accept_cond1"] + TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"] + TransactionManager_accept_cond0_accept_cond1_ConnectTrans["accept_cond0_accept_cond1_ConnectTrans"] end end Core_InitFreeRFFifo --> BasicFifo2_write -Retirement_Retirement1 --> BasicFifo2_write -TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write +Retirement_Retirement3 --> BasicFifo2_write TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write +TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write FIFO5_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write RegisterFile_perf --> HwExpHistogram2__add ReorderBuffer_perf --> HwExpHistogram4__add SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -Serializer_Serializer --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 +Serializer_Serializer1 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 @@ -721,28 +721,28 @@ SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache1 Forwarder2_read --> ICache_ICache1 ICache_ICache1 <--> HwCounter3__incr -Fetch_Fetch1 --> ICache_issue_req -Fetch_Fetch1 <--> HwCounter__incr -Fetch_Fetch1 <--> FIFOLatencyMeasurer__start -Fetch_Fetch1 --> FIFO1_write -Fetch_Fetch1 --> ArgumentsToResultsZipper_write_args -Fetch_Fetch1 --> BasicFifo3_write -Fetch_Fetch1 --> BasicFifo4_write -BasicFifo4_read --> Fetch_Fetch -ICache_accept_res --> Fetch_Fetch -Fetch_Fetch <--> FIFOLatencyMeasurer__stop -FIFO1_read --> Fetch_Fetch -Fetch_Fetch --> HwExpHistogram__add -ArgumentsToResultsZipper_read --> Fetch_Fetch -BasicFifo3_read --> Fetch_Fetch -Forwarder3_read --> Fetch_Fetch -Fetch_Fetch --> MethodProduct_method +Fetch_Fetch --> ICache_issue_req +Fetch_Fetch <--> HwCounter__incr +Fetch_Fetch <--> FIFOLatencyMeasurer__start +Fetch_Fetch --> FIFO1_write +Fetch_Fetch --> ArgumentsToResultsZipper_write_args +Fetch_Fetch --> BasicFifo3_write +Fetch_Fetch --> BasicFifo4_write +BasicFifo4_read --> Fetch_Fetch1 +ICache_accept_res --> Fetch_Fetch1 +Fetch_Fetch1 <--> FIFOLatencyMeasurer__stop +FIFO1_read --> Fetch_Fetch1 +Fetch_Fetch1 --> HwExpHistogram__add +ArgumentsToResultsZipper_read --> Fetch_Fetch1 +BasicFifo3_read --> Fetch_Fetch1 +Forwarder3_read --> Fetch_Fetch1 +Fetch_Fetch1 --> MethodProduct_method AdapterTrans_AdapterTrans_method --> MethodProduct_method -Fetch_Fetch --> FIFO_write +Fetch_Fetch1 --> FIFO_write AdapterTrans_AdapterTrans_method --> FIFO_write -Fetch_Fetch --> MethodMap_method +Fetch_Fetch1 --> MethodMap_method AdapterTrans_AdapterTrans_method --> MethodMap_method -Fetch_Fetch <--> CoreInstructionCounter_increment +Fetch_Fetch1 <--> CoreInstructionCounter_increment AdapterTrans_AdapterTrans_method <--> CoreInstructionCounter_increment FIFO_read --> DecodeStage_DecodeStage DecodeStage_DecodeStage <--> HwCounter6__incr @@ -752,7 +752,7 @@ RegAllocation_RegAllocation --> FIFO12_write FIFO12_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename -Retirement_Retirement1 --> FRAT_rename +Retirement_Retirement3 --> FRAT_rename TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename Renaming_Renaming --> FIFO13_write FIFO13_read --> ROBAllocation_ROBAllocation @@ -760,19 +760,19 @@ ROBAllocation_ROBAllocation <--> FIFOLatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO2_write ROBAllocation_ROBAllocation --> FIFO14_write -FIFO14_read --> RSSelection_RSSelection -RSSelection_RSSelection --> Forwarder9_write -Forwarder9_read --> RSSelection_RSSelection1 -Forwarder9_read --> RSSelection_RSSelection3 +FIFO14_read --> RSSelection_RSSelection1 +RSSelection_RSSelection1 --> Forwarder9_write Forwarder9_read --> RSSelection_RSSelection2 -RSFuncBlock_select --> RSSelection_RSSelection1 -RS_select --> RSSelection_RSSelection1 -RSSelection_RSSelection1 --> FIFO15_write -RSSelection_RSSelection3 --> FIFO15_write +Forwarder9_read --> RSSelection_RSSelection +Forwarder9_read --> RSSelection_RSSelection3 +RSFuncBlock_select --> RSSelection_RSSelection2 +RS_select --> RSSelection_RSSelection2 RSSelection_RSSelection2 --> FIFO15_write -RSFuncBlock1_select --> RSSelection_RSSelection3 -FifoRS_select --> RSSelection_RSSelection3 -RSSelection_RSSelection2 <--> CSRUnit_select +RSSelection_RSSelection --> FIFO15_write +RSSelection_RSSelection3 --> FIFO15_write +RSFuncBlock1_select --> RSSelection_RSSelection +FifoRS_select --> RSSelection_RSSelection +RSSelection_RSSelection3 <--> CSRUnit_select FIFO15_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -793,7 +793,7 @@ Collector3_method --> ConnectTrans12_ConnectTrans Forwarder8_read --> ConnectTrans12_ConnectTrans ConnectTrans12_ConnectTrans --> Fetch_resume -Retirement_Retirement3 --> Fetch_resume +Retirement_Retirement --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -807,7 +807,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add -RS_RS --> WakeupSelect_WakeupSelect +RS_RS1 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -831,10 +831,10 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter__incr WakeupSelect_WakeupSelect --> FIFO3_write -RS_RS3 --> WakeupSelect1_WakeupSelect +RS_RS4 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO4_write -RS_RS1 --> WakeupSelect2_WakeupSelect +RS_RS3 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> TaggedCounter1__incr WakeupSelect2_WakeupSelect <--> HwCounter5__incr @@ -842,12 +842,12 @@ WakeupSelect3_WakeupSelect --> BasicFifo5_write ConnectTrans8_ConnectTrans --> BasicFifo5_write ConnectTrans3_ConnectTrans --> BasicFifo5_write -TransactionManager_accept_cond1_ConnectTrans_accept_cond0 --> BasicFifo5_write TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo5_write -TransactionManager_accept_cond1_ConnectTrans --> BasicFifo5_write +TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> BasicFifo5_write +TransactionManager_ConnectTrans_accept_cond1 --> BasicFifo5_write WakeupSelect2_WakeupSelect --> FIFO6_write WakeupSelect2_WakeupSelect --> FIFO5_write -RS_RS4 --> WakeupSelect3_WakeupSelect +RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO7_write RS_RS2 --> WakeupSelect4_WakeupSelect @@ -870,18 +870,18 @@ ConnectTrans8_ConnectTrans --> BasicFifo6_write FifoRS_perf --> HwExpHistogram8__add Forwarder6_read --> LSUDummy_LSUDummy -Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 -Forwarder6_read --> TransactionManager_issue_cond2_LSUDummy +Forwarder6_read --> TransactionManager_issue_cond0_LSUDummy +Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 Forwarder6_read --> TransactionManager_issue_cond1_LSUDummy LSUDummy_LSUDummy --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write -TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write -TransactionManager_issue_cond2_LSUDummy --> FIFO8_write +TransactionManager_issue_cond0_LSUDummy --> FIFO8_write +TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write TransactionManager_issue_cond1_LSUDummy --> FIFO8_write LSUDummy_LSUDummy --> FIFO10_write WakeupSelect5_WakeupSelect --> FIFO10_write -TransactionManager_LSUDummy_issue_cond0 --> FIFO10_write -TransactionManager_issue_cond2_LSUDummy --> FIFO10_write +TransactionManager_issue_cond0_LSUDummy --> FIFO10_write +TransactionManager_LSUDummy_issue_cond2 --> FIFO10_write TransactionManager_issue_cond1_LSUDummy --> FIFO10_write FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect @@ -914,52 +914,52 @@ CSRUnit_get_result --> ConnectTrans3_ConnectTrans MethodTryProduct_MethodTryProduct1 --> PrivilegedFuncUnit_precommit MethodTryProduct_MethodTryProduct1 <--> InterruptController_mret -MethodTryProduct_MethodTryProduct2 --> LSUDummy_precommit -MethodTryProduct_MethodTryProduct --> CSRUnit_precommit +MethodTryProduct_MethodTryProduct --> LSUDummy_precommit +MethodTryProduct_MethodTryProduct2 --> CSRUnit_precommit ConnectTrans10_ConnectTrans --> Forwarder8_write ConnectTrans11_ConnectTrans --> Forwarder8_write BasicFifo6_read --> ConnectTrans10_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans11_ConnectTrans -ReorderBuffer_peek --> Retirement_Retirement2 -ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> Retirement_Retirement1 -ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 +ReorderBuffer_peek --> Retirement_Retirement2 +ReorderBuffer_peek --> Retirement_Retirement3 ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement2 --> MethodTryProduct_method -ExceptionCauseRegister_get --> Retirement_Retirement4 -ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement1 --> MethodTryProduct_method +ExceptionCauseRegister_get --> Retirement_Retirement2 ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement1 <--> ReorderBuffer_retire -TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire +ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement3 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire -Retirement_Retirement1 <--> FIFOLatencyMeasurer1__stop -TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire +Retirement_Retirement3 <--> FIFOLatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop -FIFO2_read --> Retirement_Retirement1 -FIFO2_read --> TransactionManager_Retirement_Retirement_cond1 +TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop +FIFO2_read --> Retirement_Retirement3 FIFO2_read --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement1 --> HwExpHistogram3__add -TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add +FIFO2_read --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement3 --> HwExpHistogram3__add TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add -CoreInstructionCounter_decrement --> Retirement_Retirement1 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 +TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add +CoreInstructionCounter_decrement --> Retirement_Retirement3 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 -RRAT_peek --> Retirement_Retirement1 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 +RRAT_peek --> Retirement_Retirement3 RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement1 --> RegisterFile_free -TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free +Retirement_Retirement3 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free -Retirement_Retirement1 --> TaggedLatencyMeasurer__stop -TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free +Retirement_Retirement3 --> TaggedLatencyMeasurer__stop TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop -AsyncMemoryBank_read --> Retirement_Retirement1 -AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1 +TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop +AsyncMemoryBank_read --> Retirement_Retirement3 AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement1 --> HwExpHistogram1__add -TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add +AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement3 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add -CSRRegister1_read --> Retirement_Retirement3 -Retirement_Retirement3 <--> ExceptionCauseRegister_clear +TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add +CSRRegister1_read --> Retirement_Retirement +Retirement_Retirement <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -971,35 +971,14 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt -TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy1 -TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 -TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 -TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue -TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue -TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond0 --> FIFO9_write -TransactionManager_issue_cond2_LSUDummy --> FIFO9_write -TransactionManager_issue_cond1_LSUDummy --> FIFO9_write -TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 -TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write -TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer -TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write -TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write -TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request -TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request -TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 -TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 -TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read -TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3 -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement -TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement4 +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement4 TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write -TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 +TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment @@ -1008,36 +987,57 @@ CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write TransactionManager_Retirement_Retirement_cond0 <--> HwCounter7__incr -TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -Serializer1_Serializer1 --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -BasicFifo1_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -WishboneMaster1_result --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -Forwarder1_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> ConnectTrans9_ConnectTrans -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans9_ConnectTrans -TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans9_ConnectTrans -TransactionManager_accept_cond1_ConnectTrans_accept_cond0 --> Forwarder7_write -TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write -TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write -LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 -LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans -TransactionManager_accept_cond1_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 +TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 +TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write +TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3 +TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write +TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write +TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request +TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request +TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue +TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond0_LSUDummy --> FIFO9_write +TransactionManager_LSUDummy_issue_cond2 --> FIFO9_write +TransactionManager_issue_cond1_LSUDummy --> FIFO9_write +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 +TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 +TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 +TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read +TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 -LSURequester_accept --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 +TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond0 LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -FIFO9_read --> TransactionManager_accept_cond1_ConnectTrans_accept_cond0 +LSURequester_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans FIFO9_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +FIFO9_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans9_ConnectTrans +TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> ConnectTrans9_ConnectTrans +TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans9_ConnectTrans +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder7_write +TransactionManager_accept_cond0_accept_cond1_ConnectTrans --> Forwarder7_write +TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write +LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +LSUDummy_accept --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans +LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -Serializer1_Serializer2 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 -TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 -FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans -FIFO10_read --> TransactionManager_accept_cond1_ConnectTrans +Serializer1_Serializer1 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +BasicFifo1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans +WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +WishboneMaster1_result --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans +Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +Forwarder1_read --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans +TransactionManager_accept_cond0_accept_cond1_ConnectTrans <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans +Serializer1_Serializer2 --> TransactionManager_accept_cond0_accept_cond1_ConnectTrans +TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1 +FIFO8_read --> TransactionManager_ConnectTrans_accept_cond1 +FIFO10_read --> TransactionManager_ConnectTrans_accept_cond1 @@ -1048,7 +1048,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 17:06 2024-04-09. + Last updated on 08:08 2024-04-10.

diff --git a/components/icache.html b/components/icache.html index 47e9df94e..8e91a0cfa 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 17:06 2024-04-09. + Last updated on 08:08 2024-04-10.

diff --git a/coreblocks.backend.html b/coreblocks.backend.html index 40e7c4142..7b09cda8c 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -165,7 +165,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 17:06 2024-04-09. + Last updated on 08:08 2024-04-10.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index 1ddcb72a4..1d987985e 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -241,7 +241,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 17:06 2024-04-09. + Last updated on 08:08 2024-04-10.

diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index 805643b51..aa9def032 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -157,7 +157,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 17:06 2024-04-09. + Last updated on 08:08 2024-04-10.

diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index 9960654a0..d1b101da4 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -1726,7 +1726,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 17:06 2024-04-09. + Last updated on 08:08 2024-04-10.

diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index 5ac6ee347..5529a38d3 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -161,7 +161,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 17:06 2024-04-09. + Last updated on 08:08 2024-04-10.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index e7b659a0e..60130e524 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -125,7 +125,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 17:06 2024-04-09. + Last updated on 08:08 2024-04-10.

diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index ac2d85c44..c7adc1746 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -874,7 +874,7 @@

Submodules

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diff --git a/coreblocks.func_blocks.fu.lsu.html b/coreblocks.func_blocks.fu.lsu.html index c6dd56ad8..ef6574a48 100644 --- a/coreblocks.func_blocks.fu.lsu.html +++ b/coreblocks.func_blocks.fu.lsu.html @@ -231,7 +231,7 @@

Submodules

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diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index 9b78bff72..8157f9542 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -238,7 +238,7 @@

Submodules

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diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index 85e2cf4e1..96c0cff94 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -148,7 +148,7 @@

Subpackages

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diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index cf829a67f..68f534350 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -169,7 +169,7 @@

Submodules

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diff --git a/coreblocks.html b/coreblocks.html index 4581ed858..1e837a2a1 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -248,7 +248,7 @@

Submodules

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diff --git a/coreblocks.params.html b/coreblocks.params.html index 56e039b03..6ea0e6f20 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -1171,7 +1171,7 @@

Submodules

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diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index 0158d3208..d531b7ce3 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -746,7 +746,7 @@

Submodules

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diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html index ec01feae2..fbaadff73 100644 --- a/coreblocks.priv.csr.html +++ b/coreblocks.priv.csr.html @@ -327,7 +327,7 @@

Submodules

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diff --git a/coreblocks.priv.html b/coreblocks.priv.html index b33ea048a..551895551 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -123,7 +123,7 @@

Subpackages

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diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index 9e5b1f8fd..1af65ea42 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -171,7 +171,7 @@

Submodules

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diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index a50b987dd..a4b9cc9d5 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

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diff --git a/current-graph.html b/current-graph.html index 7a8396e5a..f0a3d5b39 100644 --- a/current-graph.html +++ b/current-graph.html @@ -92,21 +92,21 @@

Full transaction-method graph

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diff --git a/development-environment.html b/development-environment.html index e1f50481e..ca0741fde 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

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diff --git a/genindex.html b/genindex.html index 01c20fb9d..6358bd3c1 100644 --- a/genindex.html +++ b/genindex.html @@ -399,8 +399,6 @@

_

  • (transactron.testing.infrastructure.SimpleTestCircuit method)
  • (transactron.testing.infrastructure.SyncProcessWrapper method) -
    • -
  • (transactron.testing.infrastructure.TestCaseWithSimulator method)
  • (transactron.testing.testbenchio.TestbenchIO method)
    • @@ -786,6 +784,14 @@

    C

  • compressed (coreblocks.params.configurations.CoreConfiguration attribute)
  • condition() (in module transactron.lib.simultaneous) +
    • +
  • configure_dependency_context() (transactron.testing.infrastructure.TestCaseWithSimulator method) +
    • +
  • configure_logging() (transactron.testing.infrastructure.TestCaseWithSimulator method) +
    • +
  • configure_profiles() (transactron.testing.infrastructure.TestCaseWithSimulator method) +
    • +
  • configure_traces() (transactron.testing.infrastructure.TestCaseWithSimulator method)
  • Connect (class in transactron.lib.connectors)
    • @@ -1004,6 +1010,8 @@

    C

  • module
    • + +
    • coreblocks.func_blocks.fu.lsu @@ -1011,8 +1019,6 @@

      C

    • module
    - -