From 1e3c9215d08da4b5c020d472a6a751b23f513f43 Mon Sep 17 00:00:00 2001 From: tilk Date: Thu, 14 Mar 2024 09:21:06 +0000 Subject: [PATCH] Destroy all records (#612) --- .doctrees/api.doctree | Bin 21036 -> 21036 bytes .doctrees/auto_graph.doctree | Bin 44183 -> 44187 bytes .doctrees/coreblocks.cache.doctree | Bin 56728 -> 56716 bytes .doctrees/coreblocks.fu.doctree | Bin 280343 -> 280321 bytes .doctrees/coreblocks.lsu.doctree | Bin 47588 -> 50762 bytes .doctrees/coreblocks.params.doctree | Bin 789257 -> 785254 bytes .doctrees/current-graph.doctree | Bin 45404 -> 45408 bytes .doctrees/environment.pickle | Bin 455691 -> 455643 bytes .doctrees/transactron.lib.doctree | Bin 685671 -> 684906 bytes .doctrees/transactron.utils.doctree | Bin 415875 -> 415260 bytes _sources/auto_graph.rst.txt | 334 ++++++++++---------- api.html | 2 +- assumptions.html | 2 +- auto_graph.html | 336 ++++++++++----------- components/icache.html | 2 +- coreblocks.cache.html | 4 +- coreblocks.frontend.html | 2 +- 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zPYJ|#1h|F3vz-8P3H-S;!0QAa=n9Zd;KuF%T?qVVPk?6$oaqJd4S~mc13W>XE*{`L z0^ATCsa=NjYthmtZ3y0Q0cp5V>%#q3{>_xap=vTEewY9^-6(3wM+msJdL)svy8M_& z{FtXxQmw0oQ(^~AHf4E^!0opI3?s0LKnVen1rm*V0xs(MK`vDXQ?0z59f)(#eM`wM z5Xik9AfG_rB!C10ZxW~@@X}y_Z3O-?6yP|48N&f)6NtG3paX%A2^=MmI|3k|Km&o# z2s}9oAS;dFTXzENBak>6Ac??{y8#*ql#Br=BQWhAfSCl2j00#Oz;Zr`#6F9FTg$9_ zeX-DKS4GVwxu9fDU5hDkn82_10T|-}HYEdWCD1bkpbvp9zXPC$?d{Zw0Q5w(Z9WJ< z&k)<65unFO?Ig^|Y$lRrhv_CjjVD zc6&Dgx?$N)nhikrsoHPiMopV8=Cn&~0J`(ho=vwG(w&I*=LG07FuVLI0J_%4{(b?# zMFRIN0ic7%_JC{vI&5oCpNNA)HXWX{e;`1IlI&-e0?-i#`^Ovr@@uy*KMz2znf9(c z0CJ+T+pYkhO+R}vb{%Zm%@DIf+XeO^0xshZVGjjD?@Df96JcnXW3b&l2B_!vl$DnJ z?YvR|S{fHCMe|)-VQtJq48!axx}G+*8n4g4XPPt7w(bNONaH9QEz;R#VE|fC zvS*h8(3IXDQ~^NqD!XMR0F8a^uh#-lM{oa91wj1}n@F21y1k!(TfhD2t3;`veb9Qw N*j9VtLF*Rde*rjQM9TmG diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index d75831106..d74f0281e 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -7,18 +7,18 @@ Core_InitFreeRFFifo["InitFreeRFFifo"] Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_result["result"] WishboneMaster_WishboneMaster["WishboneMaster"] + WishboneMaster_result["result"] WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] - Forwarder_read["read"] Forwarder_write["write"] + Forwarder_read["read"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] + WishboneMaster1_WishboneMaster["WishboneMaster"] WishboneMaster1_result["result"] WishboneMaster1_request["request"] - WishboneMaster1_WishboneMaster["WishboneMaster"] subgraph Forwarder1["result Forwarder"] Forwarder1_read["read"] Forwarder1_write["write"] @@ -37,18 +37,18 @@ end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] + WishboneMasterAdapter1_get_write_response["get_write_response"] + WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_read["request_read"] - WishboneMasterAdapter1_request_write["request_write"] - WishboneMasterAdapter1_get_write_response["get_write_response"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_read["read"] BasicFifo1_write["write"] + BasicFifo1_read["read"] end end end @@ -71,21 +71,21 @@ BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["address_fwd Forwarder"] Forwarder2_write["write"] Forwarder2_read["read"] end end subgraph ICache["icache ICache"] - ICache_accept_res["accept_res"] ICache_ICache["ICache"] + ICache_issue_req["issue_req"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] + ICache_accept_res["accept_res"] ICache_ICache3["ICache"] - ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -102,19 +102,19 @@ HwCounter4__incr["_incr"] end subgraph LatencyMeasurer["req_latency LatencyMeasurer"] - LatencyMeasurer__stop["_stop"] LatencyMeasurer__start["_start"] + LatencyMeasurer__stop["_stop"] subgraph HwExpHistogram["histogram HwExpHistogram"] HwExpHistogram__add["_add"] end subgraph FIFO1["fifo FIFO"] - FIFO1_read["read"] FIFO1_write["write"] + FIFO1_read["read"] end end subgraph FIFO2["req_fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end subgraph Forwarder3["res_fwd Forwarder"] Forwarder3_read["read"] @@ -129,26 +129,26 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] RegisterFile_read2["read2"] - RegisterFile_free["free"] RegisterFile_write["write"] + RegisterFile_free["free"] + RegisterFile_read1["read1"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_put["put"] - ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_peek["peek"] ReorderBuffer_retire["retire"] + ReorderBuffer_peek["peek"] + ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_put["put"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] - LatencyMeasurer1__start["_start"] LatencyMeasurer1__stop["_stop"] + LatencyMeasurer1__start["_start"] subgraph HwExpHistogram1["histogram HwExpHistogram"] HwExpHistogram1__add["_add"] end subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end end @@ -158,17 +158,17 @@ Fetch_Fetch1["Fetch"] Fetch_resume["resume"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] - BasicFifo3_write["write"] BasicFifo3_read["read"] + BasicFifo3_write["write"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] ExceptionCauseRegister_report["report"] - ExceptionCauseRegister_clear["clear"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_clear["clear"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] - BasicFifo4_read["read"] BasicFifo4_write["write"] + BasicFifo4_read["read"] end subgraph ConnectTrans["report_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -197,35 +197,35 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_select["select"] RSFuncBlock_insert["insert"] - RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] + RSFuncBlock_select["select"] + RSFuncBlock_update["update"] subgraph RS["rs RS"] RS_RS["RS"] RS_RS1["RS"] - RS_select["select"] - RS_insert["insert"] - RS_take["take"] RS_RS2["RS"] RS_RS3["RS"] RS_update["update"] + RS_insert["insert"] + RS_take["take"] + RS_select["select"] RS_RS4["RS"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph FIFO4["fifo FIFO"] - FIFO4_write["write"] FIFO4_read["read"] + FIFO4_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO5["fifo FIFO"] FIFO5_write["write"] FIFO5_read["read"] @@ -271,8 +271,8 @@ end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] PrivilegedFuncUnit_precommit["precommit"] - PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_issue["issue"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] BasicFifo5_read["read"] BasicFifo5_write["write"] @@ -307,42 +307,42 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_insert["insert"] LSUDummy_LSUDummy["LSUDummy"] - LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_update["update"] - LSUDummy_select["select"] LSUDummy_precommit["precommit"] LSUDummy_get_result["get_result"] + LSUDummy_select["select"] + LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_insert["insert"] subgraph Forwarder6["forwarder Forwarder"] Forwarder6_write["write"] Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond2["issue_cond2"] - LSURequester_accept["accept"] + LSURequester_accept_cond0["accept_cond0"] LSURequester_issue["issue"] LSURequester_accept_cond1["accept_cond1"] - LSURequester_accept_cond0["accept_cond0"] + LSURequester_accept["accept"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond2["issue_cond2"] LSURequester_issue_cond0["issue_cond0"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_insert["insert"] - CSRUnit_fetch_resume["fetch_resume"] CSRUnit_get_result["get_result"] + CSRUnit_fetch_resume["fetch_resume"] CSRUnit_select["select"] - CSRUnit_update["update"] CSRUnit_precommit["precommit"] - CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_update["update"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] - MethodTryProduct_method["method"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] + MethodTryProduct_method["method"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] @@ -372,20 +372,20 @@ GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] - CSRRegister__fu_read["_fu_read"] CSRRegister__fu_write["_fu_write"] CSRRegister_write["write"] + CSRRegister__fu_read["_fu_read"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_write["_fu_write"] - CSRRegister1_read["read"] CSRRegister1__fu_read["_fu_read"] + CSRRegister1_read["read"] + CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2__fu_write["_fu_write"] - CSRRegister2__fu_read["_fu_read"] CSRRegister2_read["read"] CSRRegister2_write["write"] + CSRRegister2__fu_write["_fu_write"] + CSRRegister2__fu_read["_fu_read"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] @@ -396,28 +396,28 @@ CSRRegister3_read["read"] end subgraph CSRRegister4["register_high CSRRegister"] + CSRRegister4_read["read"] CSRRegister4__fu_read["_fu_read"] CSRRegister4_write["write"] - CSRRegister4_read["read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5__fu_read["_fu_read"] CSRRegister5_read["read"] + CSRRegister5__fu_read["_fu_read"] CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_read["read"] CSRRegister6__fu_read["_fu_read"] + CSRRegister6_read["read"] CSRRegister6_write["write"] end end end subgraph FIFO9["fifo_decode FIFO"] - FIFO9_write["write"] FIFO9_read["read"] + FIFO9_write["write"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -441,8 +441,8 @@ Renaming_Renaming["Renaming"] end subgraph FIFO12["reg_alloc_out_buf FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -457,8 +457,8 @@ RSSelection_RSSelection2["RSSelection"] RSSelection_RSSelection3["RSSelection"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_write["write"] Forwarder8_read["read"] + Forwarder8_write["write"] end end subgraph RSInsertion["rs_insertion RSInsertion"] @@ -472,22 +472,22 @@ Retirement_Retirement["Retirement"] Retirement_Retirement1["Retirement"] Retirement_Retirement_cond1["Retirement_cond1"] - Retirement_core_state["core_state"] Retirement_Retirement2["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] + Retirement_core_state["core_state"] Retirement_Retirement3["Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement4["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] + CSRRegister7__fu_read["_fu_read"] CSRRegister7_write["write"] CSRRegister7_read["read"] - CSRRegister7__fu_read["_fu_read"] end subgraph CSRRegister8["register_high CSRRegister"] CSRRegister8_read["read"] - CSRRegister8_write["write"] CSRRegister8__fu_read["_fu_read"] + CSRRegister8_write["write"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -508,18 +508,18 @@ end subgraph TransactionManager["transactionManager TransactionManager"] TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] - TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] end end Core_InitFreeRFFifo --> BasicFifo2_write - Retirement_Retirement --> BasicFifo2_write - TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write + Retirement_Retirement4 --> BasicFifo2_write TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write + TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write @@ -528,13 +528,13 @@ SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request - ICache_ICache1 <--> HwCounter4__incr - ICache_ICache2 <--> HwCounter3__incr - ICache_ICache2 <--> HwCounter2__incr - ICache_ICache2 <--> HwCounter1__incr - ICache_ICache2 --> Forwarder3_write - ICache_ICache --> SimpleCommonBusCacheRefiller_start_refill - ICache_ICache --> Forwarder2_write + ICache_ICache <--> HwCounter4__incr + ICache_ICache1 <--> HwCounter3__incr + ICache_ICache1 <--> HwCounter2__incr + ICache_ICache1 <--> HwCounter1__incr + ICache_ICache1 --> Forwarder3_write + ICache_ICache2 --> SimpleCommonBusCacheRefiller_start_refill + ICache_ICache2 --> Forwarder2_write ICache_ICache3 --> Forwarder2_write SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3 WishboneMasterAdapter_get_read_response --> ICache_ICache3 @@ -542,26 +542,26 @@ BasicFifo_read --> ICache_ICache3 WishboneMaster_result --> ICache_ICache3 Forwarder_read --> ICache_ICache3 - Fetch_Fetch --> ICache_issue_req - Fetch_Fetch <--> HwCounter__incr - Fetch_Fetch <--> LatencyMeasurer__start - Fetch_Fetch --> FIFO1_write - Fetch_Fetch --> FIFO2_write - Fetch_Fetch --> BasicFifo3_write - BasicFifo3_read --> Fetch_Fetch1 - ICache_accept_res --> Fetch_Fetch1 - FIFO2_read --> Fetch_Fetch1 - Fetch_Fetch1 <--> LatencyMeasurer__stop - FIFO1_read --> Fetch_Fetch1 - Fetch_Fetch1 --> HwExpHistogram__add - Forwarder3_read --> Fetch_Fetch1 - Fetch_Fetch1 --> MethodProduct_method + Fetch_Fetch1 --> ICache_issue_req + Fetch_Fetch1 <--> HwCounter__incr + Fetch_Fetch1 <--> LatencyMeasurer__start + Fetch_Fetch1 --> FIFO1_write + Fetch_Fetch1 --> FIFO2_write + Fetch_Fetch1 --> BasicFifo3_write + BasicFifo3_read --> Fetch_Fetch + ICache_accept_res --> Fetch_Fetch + FIFO2_read --> Fetch_Fetch + Fetch_Fetch <--> LatencyMeasurer__stop + FIFO1_read --> Fetch_Fetch + Fetch_Fetch --> HwExpHistogram__add + Forwarder3_read --> Fetch_Fetch + Fetch_Fetch --> MethodProduct_method AdapterTrans_AdapterTrans_method --> MethodProduct_method - Fetch_Fetch1 --> FIFO_write + Fetch_Fetch --> FIFO_write AdapterTrans_AdapterTrans_method --> FIFO_write - Fetch_Fetch1 --> MethodMap_method + Fetch_Fetch --> MethodMap_method AdapterTrans_AdapterTrans_method --> MethodMap_method - Fetch_Fetch1 <--> CoreInstructionCounter_increment + Fetch_Fetch <--> CoreInstructionCounter_increment AdapterTrans_AdapterTrans_method <--> CoreInstructionCounter_increment FIFO_read --> DecodeStage_DecodeStage DecodeStage_DecodeStage <--> HwCounter8__incr @@ -571,7 +571,7 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename - Retirement_Retirement --> FRAT_rename + Retirement_Retirement4 --> FRAT_rename TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation @@ -579,18 +579,18 @@ ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write - FIFO12_read --> RSSelection_RSSelection - RSSelection_RSSelection --> Forwarder8_write - Forwarder8_read --> RSSelection_RSSelection1 + FIFO12_read --> RSSelection_RSSelection2 + RSSelection_RSSelection2 --> Forwarder8_write + Forwarder8_read --> RSSelection_RSSelection Forwarder8_read --> RSSelection_RSSelection3 - Forwarder8_read --> RSSelection_RSSelection2 - RSFuncBlock_select --> RSSelection_RSSelection1 - RS_select --> RSSelection_RSSelection1 - RSSelection_RSSelection1 --> FIFO13_write + Forwarder8_read --> RSSelection_RSSelection1 + RSFuncBlock_select --> RSSelection_RSSelection + RS_select --> RSSelection_RSSelection + RSSelection_RSSelection --> FIFO13_write RSSelection_RSSelection3 --> FIFO13_write - RSSelection_RSSelection2 --> FIFO13_write + RSSelection_RSSelection1 --> FIFO13_write RSSelection_RSSelection3 <--> LSUDummy_select - RSSelection_RSSelection2 <--> CSRUnit_select + RSSelection_RSSelection1 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -606,7 +606,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume - Retirement_Retirement2 --> Fetch_resume + Retirement_Retirement1 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -616,7 +616,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update - RS_RS1 --> WakeupSelect_WakeupSelect + RS_RS4 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -624,10 +624,10 @@ RS_take --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO4_write - RS_RS2 --> WakeupSelect1_WakeupSelect + RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write - RS_RS3 --> WakeupSelect2_WakeupSelect + RS_RS1 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -642,7 +642,7 @@ RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write - RS_RS4 --> WakeupSelect4_WakeupSelect + RS_RS2 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -660,12 +660,12 @@ PrivilegedFuncUnit_accept --> ConnectTrans8_ConnectTrans CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write - LSUDummy_LSUDummy2 --> Forwarder6_write - TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write - TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write - TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write + LSUDummy_LSUDummy --> Forwarder6_write TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write + TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write + TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write + TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -695,37 +695,37 @@ ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans - ReorderBuffer_peek --> Retirement_Retirement4 - ReorderBuffer_peek --> Retirement_Retirement1 + ReorderBuffer_peek --> Retirement_Retirement3 ReorderBuffer_peek --> Retirement_Retirement - ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement4 --> MethodTryProduct_method - ExceptionCauseRegister_get --> Retirement_Retirement1 - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement + ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement3 --> MethodTryProduct_method + ExceptionCauseRegister_get --> Retirement_Retirement ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement <--> ReorderBuffer_retire - TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire + ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement4 <--> ReorderBuffer_retire TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire - Retirement_Retirement <--> LatencyMeasurer1__stop - TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop + TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire + Retirement_Retirement4 <--> LatencyMeasurer1__stop TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop - FIFO3_read --> Retirement_Retirement - FIFO3_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop + FIFO3_read --> Retirement_Retirement4 FIFO3_read --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement --> HwExpHistogram1__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add + FIFO3_read --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement4 --> HwExpHistogram1__add TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add - CoreInstructionCounter_decrement --> Retirement_Retirement - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add + CoreInstructionCounter_decrement --> Retirement_Retirement4 CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement - RRAT_peek --> Retirement_Retirement + CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement + RRAT_peek --> Retirement_Retirement4 RRAT_peek --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement --> RegisterFile_free - TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free + Retirement_Retirement4 --> RegisterFile_free TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free - CSRRegister1_read --> Retirement_Retirement2 - Retirement_Retirement2 <--> ExceptionCauseRegister_clear + TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free + CSRRegister1_read --> Retirement_Retirement1 + Retirement_Retirement1 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -737,6 +737,45 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt + TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy2 + TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy2 + TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy2 + TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 + TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy + Serializer1_Serializer --> TransactionManager_accept_cond0_LSUDummy + BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy + BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 + WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy + WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 + Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy + Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 + TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy1 + LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy + LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement2 + TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement2 + TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write + TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write + TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write + TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write + TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry + TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry + TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 + TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read + TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer2 + TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write + TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write + TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request + TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request + TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 + Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond1 TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 TransactionManager_Retirement_cond0_Retirement --> RRAT_commit TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment @@ -745,45 +784,6 @@ CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement3 - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3 - TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write - TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry - TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry - TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy1 - TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy1 - LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 - LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 - TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 - Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond1 - BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 - BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 - WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 - WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 - Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 - Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 - TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy - TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy - TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy - TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer2 - TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request - TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request - TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 - Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond0 - TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 - TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 - TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read - TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer1 - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 + TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 diff --git a/api.html b/api.html index b563ca069..e38b5192d 100644 --- a/api.html +++ b/api.html @@ -282,7 +282,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/assumptions.html b/assumptions.html index c488796fe..934d8f494 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/auto_graph.html b/auto_graph.html index aa0de148d..67ed89e33 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -86,18 +86,18 @@ Core_InitFreeRFFifo["InitFreeRFFifo"] Core_DiscardBranchVerify["DiscardBranchVerify"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_result["result"] WishboneMaster_WishboneMaster["WishboneMaster"] + WishboneMaster_result["result"] WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] - Forwarder_read["read"] Forwarder_write["write"] + Forwarder_read["read"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] + WishboneMaster1_WishboneMaster["WishboneMaster"] WishboneMaster1_result["result"] WishboneMaster1_request["request"] - WishboneMaster1_WishboneMaster["WishboneMaster"] subgraph Forwarder1["result Forwarder"] Forwarder1_read["read"] Forwarder1_write["write"] @@ -116,18 +116,18 @@ end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] + WishboneMasterAdapter1_get_write_response["get_write_response"] + WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_get_read_response["get_read_response"] WishboneMasterAdapter1_request_read["request_read"] - WishboneMasterAdapter1_request_write["request_write"] - WishboneMasterAdapter1_get_write_response["get_write_response"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] Serializer1_Serializer1["Serializer"] Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_read["read"] BasicFifo1_write["write"] + BasicFifo1_read["read"] end end end @@ -150,21 +150,21 @@ BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] subgraph Forwarder2["address_fwd Forwarder"] Forwarder2_write["write"] Forwarder2_read["read"] end end subgraph ICache["icache ICache"] - ICache_accept_res["accept_res"] ICache_ICache["ICache"] + ICache_issue_req["issue_req"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] + ICache_accept_res["accept_res"] ICache_ICache3["ICache"] - ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -181,19 +181,19 @@ HwCounter4__incr["_incr"] end subgraph LatencyMeasurer["req_latency LatencyMeasurer"] - LatencyMeasurer__stop["_stop"] LatencyMeasurer__start["_start"] + LatencyMeasurer__stop["_stop"] subgraph HwExpHistogram["histogram HwExpHistogram"] HwExpHistogram__add["_add"] end subgraph FIFO1["fifo FIFO"] - FIFO1_read["read"] FIFO1_write["write"] + FIFO1_read["read"] end end subgraph FIFO2["req_fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end subgraph Forwarder3["res_fwd Forwarder"] Forwarder3_read["read"] @@ -208,26 +208,26 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] RegisterFile_read2["read2"] - RegisterFile_free["free"] RegisterFile_write["write"] + RegisterFile_free["free"] + RegisterFile_read1["read1"] end subgraph ReorderBuffer["ROB ReorderBuffer"] - ReorderBuffer_put["put"] - ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_peek["peek"] ReorderBuffer_retire["retire"] + ReorderBuffer_peek["peek"] + ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_put["put"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] - LatencyMeasurer1__start["_start"] LatencyMeasurer1__stop["_stop"] + LatencyMeasurer1__start["_start"] subgraph HwExpHistogram1["histogram HwExpHistogram"] HwExpHistogram1__add["_add"] end subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end end @@ -237,17 +237,17 @@ Fetch_Fetch1["Fetch"] Fetch_resume["resume"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] - BasicFifo3_write["write"] BasicFifo3_read["read"] + BasicFifo3_write["write"] end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] ExceptionCauseRegister_report["report"] - ExceptionCauseRegister_clear["clear"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_clear["clear"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] - BasicFifo4_read["read"] BasicFifo4_write["write"] + BasicFifo4_read["read"] end subgraph ConnectTrans["report_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -276,35 +276,35 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_select["select"] RSFuncBlock_insert["insert"] - RSFuncBlock_update["update"] RSFuncBlock_get_result["get_result"] + RSFuncBlock_select["select"] + RSFuncBlock_update["update"] subgraph RS["rs RS"] RS_RS["RS"] RS_RS1["RS"] - RS_select["select"] - RS_insert["insert"] - RS_take["take"] RS_RS2["RS"] RS_RS3["RS"] RS_update["update"] + RS_insert["insert"] + RS_take["take"] + RS_select["select"] RS_RS4["RS"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_issue["issue"] AluFuncUnit_accept["accept"] + AluFuncUnit_issue["issue"] subgraph FIFO4["fifo FIFO"] - FIFO4_write["write"] FIFO4_read["read"] + FIFO4_write["write"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO5["fifo FIFO"] FIFO5_write["write"] FIFO5_read["read"] @@ -350,8 +350,8 @@ end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] PrivilegedFuncUnit_precommit["precommit"] - PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_issue["issue"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] BasicFifo5_read["read"] BasicFifo5_write["write"] @@ -386,42 +386,42 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_insert["insert"] LSUDummy_LSUDummy["LSUDummy"] - LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_update["update"] - LSUDummy_select["select"] LSUDummy_precommit["precommit"] LSUDummy_get_result["get_result"] + LSUDummy_select["select"] + LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_insert["insert"] subgraph Forwarder6["forwarder Forwarder"] Forwarder6_write["write"] Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_issue_cond2["issue_cond2"] - LSURequester_accept["accept"] + LSURequester_accept_cond0["accept_cond0"] LSURequester_issue["issue"] LSURequester_accept_cond1["accept_cond1"] - LSURequester_accept_cond0["accept_cond0"] + LSURequester_accept["accept"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond2["issue_cond2"] LSURequester_issue_cond0["issue_cond0"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_insert["insert"] - CSRUnit_fetch_resume["fetch_resume"] CSRUnit_get_result["get_result"] + CSRUnit_fetch_resume["fetch_resume"] CSRUnit_select["select"] - CSRUnit_update["update"] CSRUnit_precommit["precommit"] - CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_update["update"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] - MethodTryProduct_method["method"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] MethodTryProduct_MethodTryProduct1["MethodTryProduct"] MethodTryProduct_MethodTryProduct2["MethodTryProduct"] + MethodTryProduct_method["method"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] @@ -451,20 +451,20 @@ GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] subgraph MachineModeCSRRegisters["m_mode MachineModeCSRRegisters"] subgraph CSRRegister["mcause CSRRegister"] - CSRRegister__fu_read["_fu_read"] CSRRegister__fu_write["_fu_write"] CSRRegister_write["write"] + CSRRegister__fu_read["_fu_read"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_write["_fu_write"] - CSRRegister1_read["read"] CSRRegister1__fu_read["_fu_read"] + CSRRegister1_read["read"] + CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] - CSRRegister2__fu_write["_fu_write"] - CSRRegister2__fu_read["_fu_read"] CSRRegister2_read["read"] CSRRegister2_write["write"] + CSRRegister2__fu_write["_fu_write"] + CSRRegister2__fu_read["_fu_read"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] @@ -475,28 +475,28 @@ CSRRegister3_read["read"] end subgraph CSRRegister4["register_high CSRRegister"] + CSRRegister4_read["read"] CSRRegister4__fu_read["_fu_read"] CSRRegister4_write["write"] - CSRRegister4_read["read"] end end subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5__fu_read["_fu_read"] CSRRegister5_read["read"] + CSRRegister5__fu_read["_fu_read"] CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] - CSRRegister6_read["read"] CSRRegister6__fu_read["_fu_read"] + CSRRegister6_read["read"] CSRRegister6_write["write"] end end end subgraph FIFO9["fifo_decode FIFO"] - FIFO9_write["write"] FIFO9_read["read"] + FIFO9_write["write"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -520,8 +520,8 @@ Renaming_Renaming["Renaming"] end subgraph FIFO12["reg_alloc_out_buf FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -536,8 +536,8 @@ RSSelection_RSSelection2["RSSelection"] RSSelection_RSSelection3["RSSelection"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_write["write"] Forwarder8_read["read"] + Forwarder8_write["write"] end end subgraph RSInsertion["rs_insertion RSInsertion"] @@ -551,22 +551,22 @@ Retirement_Retirement["Retirement"] Retirement_Retirement1["Retirement"] Retirement_Retirement_cond1["Retirement_cond1"] - Retirement_core_state["core_state"] Retirement_Retirement2["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] + Retirement_core_state["core_state"] Retirement_Retirement3["Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement4["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] + CSRRegister7__fu_read["_fu_read"] CSRRegister7_write["write"] CSRRegister7_read["read"] - CSRRegister7__fu_read["_fu_read"] end subgraph CSRRegister8["register_high CSRRegister"] CSRRegister8_read["read"] - CSRRegister8_write["write"] CSRRegister8__fu_read["_fu_read"] + CSRRegister8_write["write"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -587,18 +587,18 @@ end subgraph TransactionManager["transactionManager TransactionManager"] TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] - TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] - TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] end end Core_InitFreeRFFifo --> BasicFifo2_write -Retirement_Retirement --> BasicFifo2_write -TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write +Retirement_Retirement4 --> BasicFifo2_write TransactionManager_Retirement_cond1_Retirement --> BasicFifo2_write +TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write @@ -607,13 +607,13 @@ SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_Serializer1 SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request -ICache_ICache1 <--> HwCounter4__incr -ICache_ICache2 <--> HwCounter3__incr -ICache_ICache2 <--> HwCounter2__incr -ICache_ICache2 <--> HwCounter1__incr -ICache_ICache2 --> Forwarder3_write -ICache_ICache --> SimpleCommonBusCacheRefiller_start_refill -ICache_ICache --> Forwarder2_write +ICache_ICache <--> HwCounter4__incr +ICache_ICache1 <--> HwCounter3__incr +ICache_ICache1 <--> HwCounter2__incr +ICache_ICache1 <--> HwCounter1__incr +ICache_ICache1 --> Forwarder3_write +ICache_ICache2 --> SimpleCommonBusCacheRefiller_start_refill +ICache_ICache2 --> Forwarder2_write ICache_ICache3 --> Forwarder2_write SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3 WishboneMasterAdapter_get_read_response --> ICache_ICache3 @@ -621,26 +621,26 @@ BasicFifo_read --> ICache_ICache3 WishboneMaster_result --> ICache_ICache3 Forwarder_read --> ICache_ICache3 -Fetch_Fetch --> ICache_issue_req -Fetch_Fetch <--> HwCounter__incr -Fetch_Fetch <--> LatencyMeasurer__start -Fetch_Fetch --> FIFO1_write -Fetch_Fetch --> FIFO2_write -Fetch_Fetch --> BasicFifo3_write -BasicFifo3_read --> Fetch_Fetch1 -ICache_accept_res --> Fetch_Fetch1 -FIFO2_read --> Fetch_Fetch1 -Fetch_Fetch1 <--> LatencyMeasurer__stop -FIFO1_read --> Fetch_Fetch1 -Fetch_Fetch1 --> HwExpHistogram__add -Forwarder3_read --> Fetch_Fetch1 -Fetch_Fetch1 --> MethodProduct_method +Fetch_Fetch1 --> ICache_issue_req +Fetch_Fetch1 <--> HwCounter__incr +Fetch_Fetch1 <--> LatencyMeasurer__start +Fetch_Fetch1 --> FIFO1_write +Fetch_Fetch1 --> FIFO2_write +Fetch_Fetch1 --> BasicFifo3_write +BasicFifo3_read --> Fetch_Fetch +ICache_accept_res --> Fetch_Fetch +FIFO2_read --> Fetch_Fetch +Fetch_Fetch <--> LatencyMeasurer__stop +FIFO1_read --> Fetch_Fetch +Fetch_Fetch --> HwExpHistogram__add +Forwarder3_read --> Fetch_Fetch +Fetch_Fetch --> MethodProduct_method AdapterTrans_AdapterTrans_method --> MethodProduct_method -Fetch_Fetch1 --> FIFO_write +Fetch_Fetch --> FIFO_write AdapterTrans_AdapterTrans_method --> FIFO_write -Fetch_Fetch1 --> MethodMap_method +Fetch_Fetch --> MethodMap_method AdapterTrans_AdapterTrans_method --> MethodMap_method -Fetch_Fetch1 <--> CoreInstructionCounter_increment +Fetch_Fetch <--> CoreInstructionCounter_increment AdapterTrans_AdapterTrans_method <--> CoreInstructionCounter_increment FIFO_read --> DecodeStage_DecodeStage DecodeStage_DecodeStage <--> HwCounter8__incr @@ -650,7 +650,7 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename -Retirement_Retirement --> FRAT_rename +Retirement_Retirement4 --> FRAT_rename TransactionManager_Retirement_cond1_Retirement --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation @@ -658,18 +658,18 @@ ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write -FIFO12_read --> RSSelection_RSSelection -RSSelection_RSSelection --> Forwarder8_write -Forwarder8_read --> RSSelection_RSSelection1 +FIFO12_read --> RSSelection_RSSelection2 +RSSelection_RSSelection2 --> Forwarder8_write +Forwarder8_read --> RSSelection_RSSelection Forwarder8_read --> RSSelection_RSSelection3 -Forwarder8_read --> RSSelection_RSSelection2 -RSFuncBlock_select --> RSSelection_RSSelection1 -RS_select --> RSSelection_RSSelection1 -RSSelection_RSSelection1 --> FIFO13_write +Forwarder8_read --> RSSelection_RSSelection1 +RSFuncBlock_select --> RSSelection_RSSelection +RS_select --> RSSelection_RSSelection +RSSelection_RSSelection --> FIFO13_write RSSelection_RSSelection3 --> FIFO13_write -RSSelection_RSSelection2 --> FIFO13_write +RSSelection_RSSelection1 --> FIFO13_write RSSelection_RSSelection3 <--> LSUDummy_select -RSSelection_RSSelection2 <--> CSRUnit_select +RSSelection_RSSelection1 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -685,7 +685,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume -Retirement_Retirement2 --> Fetch_resume +Retirement_Retirement1 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -695,7 +695,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update -RS_RS1 --> WakeupSelect_WakeupSelect +RS_RS4 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -703,10 +703,10 @@ RS_take --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO4_write -RS_RS2 --> WakeupSelect1_WakeupSelect +RS_RS3 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write -RS_RS3 --> WakeupSelect2_WakeupSelect +RS_RS1 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -721,7 +721,7 @@ RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write -RS_RS4 --> WakeupSelect4_WakeupSelect +RS_RS2 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -739,12 +739,12 @@ PrivilegedFuncUnit_accept --> ConnectTrans8_ConnectTrans CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write -LSUDummy_LSUDummy2 --> Forwarder6_write -TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write -TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write -TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write +LSUDummy_LSUDummy --> Forwarder6_write TransactionManager_LSUDummy_issue_cond2 --> Forwarder6_write +TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write TransactionManager_LSUDummy_issue_cond1 --> Forwarder6_write +TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write +TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write CSRRegister1__fu_read --> CSRUnit_CSRUnit @@ -774,37 +774,37 @@ ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans -ReorderBuffer_peek --> Retirement_Retirement4 -ReorderBuffer_peek --> Retirement_Retirement1 +ReorderBuffer_peek --> Retirement_Retirement3 ReorderBuffer_peek --> Retirement_Retirement -ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement +ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement4 --> MethodTryProduct_method -ExceptionCauseRegister_get --> Retirement_Retirement1 -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement +ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement +Retirement_Retirement3 --> MethodTryProduct_method +ExceptionCauseRegister_get --> Retirement_Retirement ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement <--> ReorderBuffer_retire -TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire +ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement +Retirement_Retirement4 <--> ReorderBuffer_retire TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire -Retirement_Retirement <--> LatencyMeasurer1__stop -TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop +TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire +Retirement_Retirement4 <--> LatencyMeasurer1__stop TransactionManager_Retirement_cond1_Retirement <--> LatencyMeasurer1__stop -FIFO3_read --> Retirement_Retirement -FIFO3_read --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop +FIFO3_read --> Retirement_Retirement4 FIFO3_read --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement --> HwExpHistogram1__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add +FIFO3_read --> TransactionManager_Retirement_cond0_Retirement +Retirement_Retirement4 --> HwExpHistogram1__add TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add -CoreInstructionCounter_decrement --> Retirement_Retirement -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add +CoreInstructionCounter_decrement --> Retirement_Retirement4 CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement -RRAT_peek --> Retirement_Retirement +CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement +RRAT_peek --> Retirement_Retirement4 RRAT_peek --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement --> RegisterFile_free -TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free +Retirement_Retirement4 --> RegisterFile_free TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free -CSRRegister1_read --> Retirement_Retirement2 -Retirement_Retirement2 <--> ExceptionCauseRegister_clear +TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free +CSRRegister1_read --> Retirement_Retirement1 +Retirement_Retirement1 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -816,6 +816,45 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt +TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy2 +TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy2 +TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy2 +TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 +TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy +Serializer1_Serializer --> TransactionManager_accept_cond0_LSUDummy +BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy +BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 +WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy +WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 +Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy +Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 +TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy1 +LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy +LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement2 +TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement2 +TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write +TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write +TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write +TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write +TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry +TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry +TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 +TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read +TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer2 +TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write +TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write +TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request +TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request +TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 +Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond1 TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 TransactionManager_Retirement_cond0_Retirement --> RRAT_commit TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment @@ -824,48 +863,9 @@ CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement3 -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3 -TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister2_write -TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry -TransactionManager_Retirement_cond1_Retirement <--> InterruptController_entry -TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy1 -TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy1 -LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 -LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 -TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 -Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond1 -BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 -BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 -WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 -WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 -Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 -Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 -TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy -TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy -TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy -TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write -TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer2 -TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write -TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write -TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request -TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request -TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 -Serializer1_Serializer3 --> TransactionManager_LSUDummy_accept_cond0 -TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 -TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 -TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read -TransactionManager_LSUDummy_issue_cond1 --> Serializer1_Serializer1 -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 +TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 @@ -876,7 +876,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/components/icache.html b/components/icache.html index c44be0b31..c6ba4ad55 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index c1efeb535..b818efb48 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -129,7 +129,7 @@

Submodules
-serialize_addr(addr: Record) → Value
+serialize_addr(addr: View) → Value
@@ -241,7 +241,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index c965e7203..a93e1a3e1 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -368,7 +368,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/coreblocks.fu.html b/coreblocks.fu.html index 294d3b1e9..da98066af 100644 --- a/coreblocks.fu.html +++ b/coreblocks.fu.html @@ -236,7 +236,7 @@

Submodules
-coreblocks.fu.div_unit.get_input(arg: Record) → tuple[amaranth.hdl._ast.Value, amaranth.hdl._ast.Value]
+coreblocks.fu.div_unit.get_input(arg: View) → tuple[amaranth.hdl._ast.Value, amaranth.hdl._ast.Value]
@@ -286,7 +286,7 @@

SubmodulesAttributes
decode_fn: Signal
-
exec_fn: Record
+
exec_fn: View
@@ -965,7 +965,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/coreblocks.fu.unsigned_multiplication.html b/coreblocks.fu.unsigned_multiplication.html index 25447c615..c46c9b6e0 100644 --- a/coreblocks.fu.unsigned_multiplication.html +++ b/coreblocks.fu.unsigned_multiplication.html @@ -237,7 +237,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/coreblocks.html b/coreblocks.html index f59c8f5bc..1237650ed 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -234,7 +234,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/coreblocks.lsu.html b/coreblocks.lsu.html index c261c33c9..36d113c3c 100644 --- a/coreblocks.lsu.html +++ b/coreblocks.lsu.html @@ -166,7 +166,7 @@

Submodules
addrSignal

Memory address, for which PMAs are requested.

-
resultRecord

PMAs for given address.

+
resultView

PMAs for given address.

@@ -178,6 +178,17 @@

Submodules +
+class coreblocks.lsu.pma.PMALayout
+

Bases: StructLayout

+
+
+__init__()
+
+ +
+
class coreblocks.lsu.pma.PMARegion
@@ -236,7 +247,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/coreblocks.params.html b/coreblocks.params.html index c3ad994ad..a9ff75406 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -2314,17 +2314,6 @@

Submodules -
-class coreblocks.params.layouts.PMALayouts
-

Bases: object

-
-
-__init__(gen_params: GenParams)
-
- -

-
class coreblocks.params.layouts.RATLayouts
@@ -2701,7 +2690,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index d4e44e520..6acdc123f 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -744,7 +744,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index bac87e6f0..a71fac530 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/coreblocks.stages.html b/coreblocks.stages.html index 96d0ac310..4327f1258 100644 --- a/coreblocks.stages.html +++ b/coreblocks.stages.html @@ -263,7 +263,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/coreblocks.structs_common.html b/coreblocks.structs_common.html index e05bc67b4..318ceeb70 100644 --- a/coreblocks.structs_common.html +++ b/coreblocks.structs_common.html @@ -522,7 +522,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/coreblocks.utils.html b/coreblocks.utils.html index b64d42b2f..0059cb8e0 100644 --- a/coreblocks.utils.html +++ b/coreblocks.utils.html @@ -149,7 +149,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/current-graph.html b/current-graph.html index ae10765e5..32f5207c1 100644 --- a/current-graph.html +++ b/current-graph.html @@ -92,18 +92,18 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/development-environment.html b/development-environment.html index 730af3fa4..5a1c4b96e 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

diff --git a/genindex.html b/genindex.html index a9084ea4d..d1befd06c 100644 --- a/genindex.html +++ b/genindex.html @@ -185,6 +185,8 @@

_

  • (coreblocks.lsu.dummyLsu.LSUDummy method)
  • (coreblocks.lsu.pma.PMAChecker method) +
    • +
  • (coreblocks.lsu.pma.PMALayout method)
  • (coreblocks.lsu.pma.PMARegion method)
    • @@ -243,8 +245,6 @@

    _

  • (coreblocks.params.layouts.JumpBranchLayouts method)
  • (coreblocks.params.layouts.LSULayouts method) -
    • -
  • (coreblocks.params.layouts.PMALayouts method)
  • (coreblocks.params.layouts.RATLayouts method)
    • @@ -2731,7 +2731,7 @@

    P

  • PMAChecker (class in coreblocks.lsu.pma)
    • -
  • PMALayouts (class in coreblocks.params.layouts) +
  • PMALayout (class in coreblocks.lsu.pma)
  • PMARegion (class in coreblocks.lsu.pma)
    • @@ -3921,7 +3921,7 @@

    Z

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/home.html b/home.html index 799a2b754..471726678 100644 --- a/home.html +++ b/home.html @@ -129,7 +129,7 @@

    Documentation

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/index.html b/index.html index 9efbb6b44..16998b3e6 100644 --- a/index.html +++ b/index.html @@ -229,7 +229,7 @@

    Coreblocks

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html index 87e61df71..bc2c63032 100644 --- a/miscellany/exceptions-summary.html +++ b/miscellany/exceptions-summary.html @@ -271,7 +271,7 @@

    Summary

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/modules-coreblocks.html b/modules-coreblocks.html index c808e3308..8e160ae5f 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -203,7 +203,7 @@

    coreblocks

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/modules-transactron.html b/modules-transactron.html index 5d52139e9..2dc13be74 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -149,7 +149,7 @@

    transactron

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

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    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/py-modindex.html b/py-modindex.html index 72ce95f58..78cb0576a 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -618,7 +618,7 @@

    Python Module Index

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/scheduler/overview.html b/scheduler/overview.html index 5c4f9a5c3..9d10d5b0a 100644 --- a/scheduler/overview.html +++ b/scheduler/overview.html @@ -146,7 +146,7 @@

    More detailed description of each block

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/search.html b/search.html index 3deb2e593..1fb50efa2 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

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20, 27], "extens": [3, 10, 27], "introduc": [3, 20, 28], "16": [3, 10, 20, 29], "bit": [3, 5, 6, 7, 8, 10, 11, 14, 20, 25, 26, 28, 30, 32, 33], "relax": [3, 28], "unit": [3, 6, 7, 8, 10, 11, 12, 13, 14, 17, 24, 27], "handl": [3, 7, 14, 19, 28, 29], "case": [3, 11, 12, 13, 20, 23, 28, 29, 30, 32, 33], "fulli": [3, 9, 30], "pipelin": [3, 9, 11, 12, 14, 20, 25, 30], "process": [3, 14, 17, 19, 27, 30, 31], "order": [3, 10, 12, 14, 17, 18, 19, 27, 29, 30], "As": [3, 20, 28, 30], "can": [3, 9, 11, 13, 14, 17, 18, 20, 24, 25, 27, 28, 29, 30, 31, 32, 33], "invok": [3, 6, 12, 13, 20, 25, 31], "independ": [3, 28, 30], "accept_r": [3, 5], "If": [3, 6, 10, 11, 14, 20, 23, 25, 28, 29, 30, 32], "space": [3, 20], "anoth": [3, 5, 17, 28, 29, 30], "simpli": 3, "block": [3, 7, 8, 10, 11, 12, 13, 19, 20, 28, 29, 30], "latenc": [3, 20, 27, 30], "least": 3, "one": [3, 5, 7, 10, 11, 13, 14, 17, 20, 24, 25, 26, 28, 29, 30, 31, 32, 33], "cycl": [3, 7, 8, 11, 14, 17, 20, 24, 27, 28, 29, 30, 31], "miss": [3, 20], "occur": [3, 5], "arbitrarili": 3, "long": [3, 26, 27, 30], "ensur": [3, 27], "ani": [3, 6, 11, 12, 20, 23, 30, 31, 32, 33], "refetch": 3, "howev": [3, 30], "guarante": [3, 20], "have": [3, 9, 11, 13, 14, 17, 20, 23, 27, 28, 29, 30, 31, 32, 33], "alreadi": [3, 13, 20, 30, 32], "been": 3, "still": [3, 20, 26, 29], "wait": [3, 11, 13, 14, 17, 20, 25, 26, 29, 31], "accept": [3, 5, 7, 8, 14, 15, 27, 29, 30, 32], "inform": [3, 9, 12, 17, 29, 30, 32], "regard": 3, "error": [3, 5, 10, 11, 29, 30, 32], "mean": [3, 12, 17, 26, 29, 30], "dure": [3, 9, 19, 24, 30, 31], "line": [3, 5, 10, 17, 19], "subsequ": 3, "access": [3, 10, 11, 14, 20, 28, 30, 31, 32], "trigger": [3, 14], "which": [3, 5, 6, 7, 9, 10, 11, 12, 13, 17, 18, 20, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33], "most": [3, 20, 28, 29, 30], "like": [3, 6, 20, 28, 29, 30], "For": [3, 10, 17, 25, 26, 28, 29, 30, 32, 33], "32": [3, 7, 8, 10, 11, 20, 28, 30], "128": [3, 10], "set": [3, 5, 6, 7, 9, 10, 12, 13, 14, 19, 25, 27, 29, 30, 32, 33], "size": [3, 10, 11, 20, 28, 30, 32], "equal": [3, 14], "31": [3, 10], "15": [3, 10], "14": [3, 10], "13": [3, 10], "12": [3, 10], "11": [3, 10, 17, 27], "10": [3, 10, 20], "09": 3, "08": 3, "07": 3, "06": [3, 31], "05": 3, "04": 3, "03": 3, "02": 3, "01": 3, "00": 3, "tag": [3, 11, 20, 25, 26], "index": [3, 10, 29, 33], "offset": 3, "unsigned_multipl": [4, 7], "common": [4, 7, 11, 30, 32], "fast_recurs": [4, 7], "sequenc": [4, 7, 12, 30], "shift": [4, 7, 10], "class": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 28, 29, 30, 31, 32, 33], "base": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 20, 29, 30, 31, 32, 33], "elaborat": [4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 28, 29, 30, 31, 32], "__init__": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 28, 29, 30, 31, 32, 33], "gen_param": [4, 6, 7, 8, 9, 10, 12, 13, 14], "wb_instr_bu": 4, "wishboneinterfac": [4, 11], "wb_data_bu": 4, "cacheinterfac": [5, 6], "A": [5, 10, 11, 27, 28, 29, 30, 32], "simpl": [5, 6, 9, 12, 13, 29, 30, 32, 33], "associ": [5, 10, 30], "instruct": [5, 6, 7, 9, 10, 12, 13, 14, 19, 20, 24, 25, 27], "replac": [5, 8, 10, 25], "polici": 5, "pseudo": 5, "random": [5, 31], "scheme": 5, "everi": [5, 7, 11, 17, 27, 29, 30], "time": [5, 11, 14, 20, 29, 30], "trash": 5, "we": [5, 9, 11, 13, 20, 24, 25, 26, 27, 28, 31], "select": [5, 6, 7, 9, 11, 12, 13, 14, 15, 17], "next": [5, 6, 9, 12, 13, 14, 20, 29, 33], "wai": [5, 7, 11, 17, 20, 27, 28, 29, 30, 32], "keep": [5, 29], "global": [5, 14, 20], "counter": [5, 10, 14, 17, 30], "abstract": [5, 8, 10, 27, 30, 32], "awai": 5, "need": [5, 11, 17, 20, 25, 28, 29], "two": [5, 10, 14, 20, 23, 27, 28, 29, 30, 31, 32], "refiller_start": 5, "call": [5, 7, 12, 14, 17, 23, 25, 28, 29, 30, 31, 32], "whenev": 5, "refiller_accept": 5, "readi": [5, 9, 10, 11, 12, 13, 14, 19, 25, 29, 30], "word": [5, 10], "written": [5, 14, 26, 27, 30], "last": [5, 10, 12, 14, 29, 30], "when": [5, 11, 14, 17, 20, 23, 25, 26, 28, 29, 30, 31, 32, 33], "either": [5, 11, 28, 29, 30, 32, 33], "transfer": [5, 11, 29, 30], "over": [5, 14, 29, 30], "shouldn": [5, 27], "t": [5, 6, 9, 10, 17, 20, 23, 25, 27, 28, 29, 30, 31, 32], "until": [5, 20, 30], "start": [5, 7, 9, 10, 11, 20, 29, 30], "icachelayout": [5, 10], "icacheparamet": [5, 10], "cacherefillerinterfac": 5, "none": [5, 6, 7, 9, 10, 13, 14, 29, 30, 31, 32, 33], "paramet": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 28, 29, 30, 31, 32, 33], "instanc": [5, 6, 7, 9, 12, 13, 27, 29, 30, 31, 32], "us": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 19, 20, 23, 27, 28, 29, 30, 31, 32, 33], "creat": [5, 8, 11, 17, 27, 28, 29, 30, 31, 32, 33], "gener": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 18, 20, 23, 27, 29, 30, 31, 32], "input": [5, 6, 7, 11, 13, 14, 20, 25, 26, 28, 29, 30, 33], "start_refil": 5, "accept_refil": 5, "deserialize_addr": 5, "raw_addr": 5, "valu": [5, 6, 7, 9, 10, 11, 12, 13, 14, 19, 23, 25, 26, 29, 30, 31, 32, 33], "dict": [5, 11, 28, 29, 30, 31, 32, 33], "str": [5, 10, 11, 29, 30, 31, 32, 33], "amaranth": [5, 6, 7, 10, 11, 23, 27, 28, 29, 30, 31, 32, 33], "hdl": [5, 6, 7, 10, 29, 30, 31, 32, 33], "_ast": [5, 6, 7, 10, 29, 30, 31, 32, 33], "serialize_addr": 5, "addr": [5, 9, 10, 11, 30], "record": [5, 7, 9, 23, 28, 29, 30, 31, 32, 33], "icachebypass": 5, "bus_mast": 5, "busmasterinterfac": [5, 9, 10, 11], "haselabor": [5, 11, 15, 29, 30, 31, 33], "interfac": [5, 6, 8, 9, 11, 12, 13, 14, 19, 27, 28, 29, 30], "whole": [5, 18, 20, 30], "given": [5, 7, 9, 10, 17, 25, 28, 29, 30, 31, 32, 33], "simplecommonbuscacherefil": 5, "decodestag": 6, "decod": [6, 7, 10, 12, 29, 32], "transact": [6, 10, 11, 14, 17, 19, 25, 29, 30, 33], "instanti": [6, 29], "instrdecod": 6, "make": [6, 7, 17, 18, 20, 23, 27, 28, 29, 31], "actual": [6, 17, 19, 28], "combinatori": [6, 28], "manner": [6, 11], "get_raw": 6, "push_decod": 6, "raw": 6, "previou": [6, 11, 20, 30], "step": [6, 12, 17, 20, 27, 28], "e": [6, 10, 17, 20, 23, 28, 30, 32, 33], "g": [6, 10, 17, 20, 23, 28, 30, 32, 33], "fetchlayout": [6, 10], "send": [6, 10, 11, 12, 13], "It": [6, 7, 8, 9, 11, 12, 13, 17, 20, 24, 25, 27, 28, 29, 30, 31, 32, 33], "describ": [6, 10, 12, 13, 20, 27, 29, 30, 31], "decodelayout": [6, 10, 12], "pc": [6, 10, 14, 19], "insid": [6, 27, 28, 29, 30], "increment": [6, 14], "ilen_byt": 6, "cont": [6, 31], "unalignedfetch": 6, "work": [6, 12, 20, 23, 27, 28, 29], "unalign": 6, "perform": [6, 7, 8, 10, 12, 14, 17, 27, 28, 29, 30, 32, 33], "elementari": 6, "compon": [6, 10, 11, 18, 29, 30], "opcod": [6, 10, 25, 26], "funct3": [6, 7, 10], "etc": [6, 10, 28], "connect": [6, 11, 13, 14, 20, 28, 29, 30], "via": [6, 28, 29], "its": [6, 12, 13, 14, 20, 27, 28, 29, 30, 32, 33], "attribut": [6, 7, 8, 9, 10, 11, 13, 14, 29, 30, 32, 33], "signal": [6, 7, 9, 10, 11, 19, 23, 29, 30, 31, 32, 33], "ilen": [6, 10], "out": [6, 7, 8, 11, 13, 18, 19, 29, 30, 33], "identifi": [6, 10, 25, 30, 32], "funct3_v": 6, "1": [6, 7, 8, 10, 12, 14, 20, 25, 26, 27, 28, 29, 30, 31, 32, 33], "funct7": [6, 7, 10], "seven": 6, "funct7_v": 6, "funct12": [6, 10], "twelv": 6, "funct12_v": 6, "rd": [6, 10], "reg_cnt_log": 6, "address": [6, 9, 10, 11, 14, 19, 20], "regist": [6, 10, 12, 14, 20, 24, 30, 32], "rd_v": 6, "rs1": [6, 10], "hold": [6, 11, 14, 30], "first": [6, 7, 10, 12, 20, 25, 26, 27, 28, 30, 31, 32], "rs1_v": 6, "take": [6, 11, 13, 24, 25, 28, 29, 30, 31, 32], "form": [6, 10, 14, 20, 27, 30], "rs2": [6, 10], "second": [6, 7, 10, 12, 25, 26, 27, 30], "rs2_v": 6, "imm": [6, 10], "xlen": [6, 7, 10, 14, 32], "immedi": [6, 10, 11], "provid": [6, 7, 10, 12, 14, 27, 28, 30, 31, 32], "were": [6, 20, 28], "succ": 6, "fencetarget": [6, 10], "successor": 6, "fenc": [6, 10], "pred": 6, "predecessor": 6, "fm": 6, "fencefm": [6, 10], "mode": [6, 10, 17, 20], "csr_alen": [6, 10], "control": [6, 10, 11, 14, 27, 29, 30, 33], "sourc": [6, 10, 12, 17, 25, 29, 30, 32], "type": [6, 7, 10, 17, 29, 30, 31, 32], "defin": [6, 9, 14, 28, 29, 30, 32, 33], "kind": [6, 7, 12, 30, 32], "illeg": 6, "wa": [6, 10, 14, 17, 20, 28, 29, 30, 32], "success": [6, 11, 31], "do": [6, 10, 20, 23, 28, 29], "fit": 6, "support": [6, 9, 10, 12, 17, 19, 29, 30], "constructor": [6, 28, 29, 32], "encod": [6, 20, 29, 32, 33], "object": [6, 7, 9, 10, 11, 27, 28, 29, 30, 31, 32], "repres": [6, 14, 29, 30], "singl": [6, 7, 8, 10, 12, 13, 14, 28, 29, 30, 32], "option": [6, 7, 10, 14, 17, 28, 29, 30, 31, 32, 33], "exist": [6, 28, 32], "instr_type_overrid": 6, "instrtyp": [6, 10], "specifi": [6, 10, 11, 14, 26, 30, 31, 32], "determin": [6, 20, 27, 30, 32], "instrust": 6, "almost": 6, "correct": [6, 9, 20, 25, 26, 27], "rd_zero": 6, "bool": [6, 7, 9, 10, 14, 29, 30, 31, 32, 33], "field": [6, 9, 10, 14, 17, 25, 26, 28, 29, 30, 31, 32], "constant": 6, "zero": [6, 10, 14, 25, 30, 33], "other": [6, 14, 17, 19, 28, 29, 30, 33], "accordingli": 6, "default": [6, 11, 17, 28, 29, 30, 32, 33], "fals": [6, 7, 9, 10, 17, 28, 29, 30, 32, 33], "rs1_zero": 6, "instrdecompress": 6, "decompr_reg": 6, "rvc_reg": 6, "instr_mux": 6, "sel": [6, 11], "list": [6, 7, 10, 11, 14, 17, 19, 23, 27, 29, 30, 31, 32, 33], "int": [6, 7, 8, 9, 10, 11, 13, 14, 29, 30, 31, 32, 33], "enum": [6, 7, 10, 29, 30, 31, 32], "valuecast": [6, 10, 29, 30, 31, 32], "tupl": [6, 7, 10, 11, 12, 13, 14, 29, 30, 32], "is_instr_compress": 6, "alucompon": [7, 10], "functionalcomponentparam": [7, 10, 13], "zba_en": 7, "zbb_enabl": 7, "get_modul": [7, 9, 10, 13, 14], "funcunit": [7, 10, 13, 15], "get_optyp": [7, 9, 10, 13, 14], "alufuncunit": 7, "alu_fn": 7, "alufn": 7, "divcompon": 7, "ipc": [7, 27], "3": [7, 10, 14, 17, 29, 32], "div_fn": 7, "divfn": 7, "decodermanag": 7, "fn": 7, "intflag": [7, 10, 29], "div": [7, 10], "divu": [7, 10], "2": [7, 8, 10, 11, 14, 27, 29, 30, 32], "rem": [7, 10], "remu": [7, 10], "8": [7, 8, 10, 11, 29, 30], "__new__": [7, 10, 14, 29], "get_instruct": 7, "valid": [7, 10, 11, 12, 25, 30, 32, 33], "implement": [7, 9, 11, 18, 19, 20, 24, 30, 32, 33], "format": [7, 17, 27, 28, 29, 30, 32], "divunit": 7, "get_input": 7, "arg": [7, 11, 28, 29, 30, 31, 32, 33], "exceptionfuncunit": 7, "unit_fn": 7, "exceptionunitfn": 7, "exceptionunitcompon": [7, 10], "respons": [7, 11, 12, 17, 29, 30, 31], "decode_fn": 7, "exec_fn": [7, 10], "op": [7, 10], "check_optyp": 7, "manag": [7, 17, 19, 29, 30, 32], "enumer": 7, "get_decod": 7, "auto": 7, "pass": [7, 13, 14, 17, 19, 27, 29, 30, 31, 32], "contructor": 7, "get_funct": 7, "get_op_typ": 7, "jumpbranchfuncunit": 7, "jb_fn": 7, "jumpbranchfn": 7, "jumpcompon": [7, 10], "mulcompon": 7, "mul_unit_typ": 7, "multyp": 7, "dsp_width": [7, 8], "mul_fn": 7, "mulfn": 7, "hot": [7, 20, 33], "wire": [7, 32], "5": [7, 10, 24, 30, 31], "differ": [7, 11, 13, 17, 18, 20, 23, 27, 29, 30, 32], "mul": [7, 10], "mulh": [7, 10], "mulhsu": [7, 10], "mulhu": [7, 10], "intenum": [7, 10, 14], "recursive_mul": 7, "fastest": 7, "multipli": [7, 8], "onli": [7, 11, 14, 20, 27, 28, 29, 30, 31, 32], "costli": [7, 20], "term": 7, "resourc": [7, 14, 20, 27, 28], "sequence_mul": 7, "dsp": [7, 8], "balanc": 7, "between": [7, 17, 20, 28, 29, 30, 32, 33], "cost": [7, 19, 28], "shift_mul": 7, "cheapest": 7, "russian": [7, 8], "peasant": [7, 8], "algorithm": [7, 8], "mulunit": 7, "unsign": [7, 8], "integ": [7, 10, 32], "standard": [7, 14, 20, 27, 33], "funcunitlayout": [7, 10, 12, 13], "comput": [7, 8, 9, 14, 20, 30, 32], "mul_typ": 7, "privilegedfn": 7, "mret": [7, 10], "classmethod": [7, 29, 30, 32], "privilegedfuncunit": 7, "gp": [7, 10, 14], "privilegedunitcompon": [7, 10], "shiftfuncunit": 7, "shift_unit_fn": 7, "shiftunitfn": 7, "shiftunitcompon": [7, 10], "clmultipli": 7, "carri": [7, 10, 27], "less": [7, 10], "product": [7, 30], "i1": [7, 8], "n": [7, 8, 10], "factor": 7, "i2": [7, 8], "reset": [7, 14, 19, 29], "new": [7, 9, 11, 14, 19, 20, 29, 30, 32, 33], "busi": 7, "while": [7, 29, 31], "progress": 7, "bit_width": 7, "recursion_depth": 7, "width": [7, 8, 10, 11, 14, 30, 32, 33], "depth": [7, 11, 27, 30], "recurs": [7, 8, 27, 28, 29, 32], "parallel": 7, "assum": [7, 13, 20, 30, 32], "power": [7, 32], "iterative_modul": 7, "recursive_modul": 7, "zbccompon": 7, "zbc_fn": 7, "zbcfn": 7, "clmul": [7, 10], "clmulh": [7, 10], "clmulr": [7, 10], "zbcunit": 7, "execut": [7, 10, 11, 12, 13, 17, 19, 24, 26, 28, 29, 30, 31], "zbsfunction": 7, "in1": 7, "in2": 7, "zbscompon": 7, "bclr": [7, 10], "bext": [7, 10], "binv": [7, 10], "bset": [7, 10], "zbsunit": 7, "zbs_fn": 7, "dspmulunit": 8, "clock": [8, 24, 27, 28, 29, 30], "design": [8, 20, 28, 29], "synthesi": [8, 19], "tool": [8, 17, 27, 29], "o": [8, 20, 28, 29], "same": [8, 9, 17, 28, 29, 30, 32], "number": [8, 10, 11, 13, 17, 20, 27, 29, 30, 31, 32, 33], "mulbaseunsign": 8, "unsignedmulunitlayout": [8, 10], "recursiveunsignedmul": 8, "see": [8, 23, 27, 28, 30], "fast": 8, "within": [8, 17], "sequentialunsignedmul": 8, "sequenti": [8, 11], "classic": [8, 20], "shiftunsignedmul": 8, "cheap": 8, "multi": 8, "lsublockcompon": [9, 10], "blockcomponentparam": [9, 10, 13, 14], "funcblock": [9, 10, 12, 13, 14, 15], "get_rs_entry_count": [9, 10, 13, 14], "lsudummi": 9, "veri": [9, 20, 28], "serial": [9, 13, 30], "all": [9, 10, 11, 14, 17, 19, 20, 23, 28, 29, 30, 32, 33], "store": [9, 10, 13, 14, 20, 25, 26, 29, 30, 32], "load": [9, 10, 20, 30, 32], "isn": [9, 27, 29], "compliant": [9, 27], "riscv": [9, 27], "spec": 9, "doesn": [9, 20, 23, 28, 30], "check": [9, 17, 20, 23, 25, 26, 27, 29, 32], "rang": [9, 29, 30, 31, 32, 33], "reserv": [9, 10, 14, 19, 20], "place": [9, 11, 14, 20, 25, 27, 28, 29, 30], "intruct": 9, "insert": [9, 12, 13, 14, 15, 19, 20, 24, 25], "put": [9, 14, 25, 27, 30], "receiv": [9, 11, 14, 28, 29, 30], "calcul": [9, 30], "end": [9, 10, 13, 20, 30, 32], "further": [9, 17, 30], "get_result": [9, 13, 14, 15, 30], "To": [9, 17, 20, 27, 30, 32], "precommit": [9, 13, 17], "processor": [9, 18, 19, 24], "master": [9, 11, 27], "pmacheck": 9, "physic": [9, 10, 12, 20], "memori": [9, 10, 11, 20, 30], "checker": 9, "mai": [9, 17, 30, 31, 32], "part": [9, 14, 20, 24, 28, 29, 30], "combin": [9, 13, 19, 23, 29, 30, 32], "circuit": [9, 27, 28, 29, 30, 32], "pmaregion": [9, 10], "contigu": [9, 10], "region": [9, 20], "includ": [9, 27, 28, 29, 30, 32, 33], "both": [9, 25, 28, 29, 30, 32], "begin": [9, 20], "mmio": 9, "true": [9, 10, 11, 28, 29, 30, 31, 32, 33], "indic": [9, 20, 26, 29], "coreconfigur": 10, "func_units_config": 10, "collect": [10, 13, 14, 18, 27, 29, 30, 31, 32, 33], "station": [10, 19], "exampl": [10, 14, 17, 19, 25, 28, 29, 30, 33], "rsblockcompon": [10, 13], "rs_entri": [10, 13, 14], "compress": 10, "enabl": [10, 30, 31, 32], "embed": 10, "reduc": [10, 20, 29], "debug": [10, 17, 32], "hardwar": [10, 19, 24, 28, 30, 32], "disabl": [10, 29, 30, 31], "them": [10, 17, 20, 27, 28, 29, 30, 32], "synthes": [10, 27, 30], "phys_regs_bit": 10, "file": [10, 17, 20, 27, 32], "rob_entries_bit": 10, "reorder": [10, 20, 30], "buffer": [10, 11, 20, 25, 30], "start_pc": 10, "initi": [10, 11, 19, 30, 31], "program": [10, 20, 27, 28], "icache_en": 10, "bypass": 10, "directli": [10, 28, 29], "icache_wai": 10, "icache_sets_bit": 10, "log": [10, 20], "icache_block_size_bit": 10, "allow_partial_extens": 10, "allow": [10, 18, 20, 27, 28, 29, 30, 33], "partial": [10, 29, 30, 32], "_implied_extens": 10, "extenst": 10, "flag": 10, "intern": [10, 19, 28, 29, 30], "definit": [10, 19, 29], "per": [10, 27], "segment": 10, "abc": [10, 29, 30, 31, 32, 33], "func_unit": [10, 13], "csrblockcompon": [10, 14], "6": [10, 20], "7": 10, "factori": [10, 29, 30, 32], "kwarg": [10, 11, 29, 30, 31, 32, 33], "optypes_support": 10, "iter": [10, 13, 14, 29, 30, 31, 32, 33], "dependentcach": [10, 32], "cfg": 10, "addr_width": [10, 11], "length": [10, 20, 29, 32], "word_width": 10, "machin": [10, 14], "num_of_wai": 10, "num_of_sets_bit": 10, "block_size_bit": 10, "btypeinstr": 10, "riscvinstr": 10, "pack": 10, "ebreakinstr": 10, "itypeinstr": 10, "illegalinstr": 10, "jtypeinstr": 10, "rtypeinstr": 10, "stypeinstr": 10, "utypeinstr": 10, "exceptioncaus": 10, "breakpoint": 10, "environment_call_from_m": 10, "environment_call_from_": 10, "9": 10, "environment_call_from_u": 10, "illegal_instruct": 10, "instruction_access_fault": 10, "instruction_address_misalign": 10, "instruction_page_fault": 10, "load_access_fault": 10, "load_address_misalign": 10, "load_page_fault": 10, "store_access_fault": 10, "store_address_misalign": 10, "store_page_fault": 10, "avail": [10, 11, 12, 14, 17, 18, 27, 30], "atom": [10, 25, 28], "b": 10, "512": 10, "manipul": 10, "256": 10, "d": [10, 28, 29, 32], "doubl": [10, 14, 20], "precis": [10, 20, 27], "float": [10, 29, 30, 31, 32], "point": [10, 20, 23, 27], "64": [10, 11], "f": [10, 12, 17, 27, 31], "98366": 10, "contain": [10, 17, 27, 28, 29, 30, 32], "basic": [10, 19, 27, 30], "full": [10, 17, 19, 20, 27, 30], "j": 10, "1024": 10, "dynam": [10, 20, 33], "languag": [10, 28], "l": [10, 17], "decim": 10, "m": [10, 11, 14, 17, 20, 27, 28, 29, 30, 32, 33], "divis": 10, "16384": 10, "user": [10, 14, 20, 27, 30], "level": [10, 11, 18, 20, 27, 28], "interrupt": [10, 19], "p": [10, 17], "4096": 10, "simd": 10, "q": 10, "quad": 10, "2048": 10, "8192": 10, "vector": [10, 12, 19, 20], "xintmachinemod": 10, "8589934592": 10, "categor": 10, "privilieg": 10, "xintsupervisor": 10, "17179869184": 10, "supervisor": [10, 14], "zam": 10, "2097152": 10, "misalign": 10, "zba": 10, "268435456": 10, "extend": [10, 23, 29], "zbb": 10, "536870912": 10, "1073741824": 10, "2147483648": 10, "zdinx": 10, "33554432": 10, "zfh": 10, "4194304": 10, "half": 10, "zfhmin": 10, "8388608": 10, "minim": 10, "zfinx": 10, "16777216": 10, "zhinx": 10, "67108864": 10, "zicntr": 10, "524288": 10, "timer": [10, 14], "zicsr": 10, "32768": 10, "statu": [10, 14, 31], "zifencei": 10, "65536": 10, "zihintntl": 10, "262144": 10, "non": [10, 25, 29, 30], "tempor": 10, "local": [10, 14, 17], "hint": [10, 29], "zihintpaus": 10, "131072": 10, "paus": 10, "energi": 10, "zihpm": 10, "1048576": 10, "zmmul": 10, "134217728": 10, "ztso": 10, "4294967296": 10, "total": 10, "tso": 10, "dev_i": 10, "dev_o": 10, "mem_r": 10, "mem_w": 10, "clz": 10, "1536": 10, "cpop": 10, "1538": 10, "ctz": 10, "1537": 10, "ebreak": 10, "ecal": 10, "770": 10, "orcb": 10, "647": 10, "rev8_32": 10, "1688": 10, "rev8_64": 10, "1720": 10, "sextb": 10, "1540": 10, "sexth": 10, "1541": 10, "sret": 10, "258": 10, "wfi": 10, "261": 10, "zexth": 10, "add": [10, 28, 29, 30, 32], "AND": 10, "andn": 10, "beq": 10, "bge": 10, "bgeu": 10, "blt": 10, "bltu": 10, "bne": 10, "csrrc": 10, "csrrci": 10, "csrr": 10, "csrrsi": 10, "csrrw": 10, "csrrwi": 10, "divuw": 10, "divw": 10, "fencei": 10, "h": [10, 20], "hu": 10, "jalr": 10, "max": [10, 27], "maxu": 10, "min": [10, 30], "minu": 10, "mulw": 10, "OR": 10, "orn": 10, "remuw": 10, "remw": 10, "rev8": 10, "rol": 10, "ror": 10, "sh1add": 10, "sh2add": 10, "sh3add": 10, "sll": 10, "slt": 10, "sltu": 10, "sr": 10, "sub": 10, "w": [10, 20], "xnor": 10, "xor": 10, "36": 10, "52": 10, "20": 10, "48": 10, "muldiv": 10, "sa": 10, "sfencevma": 10, "sl": 10, "gather": 10, "numer": 10, "val": [10, 32], "correspond": [10, 25, 29, 33], "val_log": 10, "relev": [10, 29], "nativ": 10, "reg_cnt": 10, "maximum": [10, 27, 30], "bitwis": 10, "isa_str": 10, "string": 10, "pleas": [10, 17, 23, 28], "refer": [10, 29, 32], "gcc": 10, "": [10, 11, 20, 28, 29, 30, 32, 33], "arch": [10, 17, 27], "detail": [10, 14, 19], "u": [10, 20, 27, 30, 32], "auipc": 10, "branch": [10, 20, 27, 30], "24": 10, "jal": 10, "27": 10, "25": 10, "load_fp": 10, "lui": 10, "misc_mem": 10, "op32": 10, "op_imm": 10, "op_imm_32": 10, "store_fp": 10, "system": [10, 27, 28, 32], "28": [10, 20], "a0": 10, "a1": 10, "a2": 10, "a3": 10, "a4": 10, "a5": 10, "a6": 10, "a7": 10, "17": 10, "fp": [10, 29], "ra": 10, "s0": 10, "s1": 10, "s10": 10, "26": 10, "s11": 10, "s2": 10, "18": 10, "s3": 10, "19": 10, "s4": 10, "s5": 10, "21": 10, "s6": 10, "22": 10, "s7": 10, "23": 10, "s8": 10, "s9": 10, "sp": 10, "t0": 10, "t1": [10, 28], "t2": [10, 28], "t3": 10, "t4": 10, "29": 10, "t5": 10, "30": [10, 20], "t6": 10, "tp": [10, 32], "x1": 10, "x10": 10, "x11": 10, "x12": 10, "x13": 10, "x14": 10, "x15": 10, "x16": 10, "x17": 10, "x18": 10, "x19": 10, "x2": 10, "x20": 10, "x21": 10, "x22": 10, "x23": 10, "x24": 10, "x25": 10, "x26": 10, "x27": 10, "x28": 10, "x29": 10, "x3": 10, "x30": 10, "x31": 10, "x4": 10, "x5": 10, "x6": 10, "x7": 10, "x8": 10, "x9": 10, "asyncinterruptinsertsignalkei": 10, "simplekei": [10, 29, 30, 32], "branchverifykei": 10, "commonbusdatakei": 10, "exceptionreportkei": 10, "fetchresumekei": 10, "unifierkei": [10, 13, 30], "unifi": [10, 30], "alia": 10, "collector": [10, 30], "genericcsrregisterskei": 10, "genericcsrregist": [10, 14], "instructionprecommitkei": 10, "methodtryproduct": [10, 30], "mretkei": 10, "csrlayout": 10, "commonlayoutfield": 10, "commonli": 10, "layoutlistfield": 10, "caus": [10, 20, 30, 32], "piec": 10, "rais": [10, 20, 29, 30, 31, 32], "exec_fn_layout": 10, "op_typ": 10, "reg_id": 10, "id": [10, 12, 25, 26, 29], "reg_val": 10, "some": [10, 14, 20, 23, 28, 29, 30, 32], "regs_l": 10, "logic": [10, 20, 26, 27, 28], "manual": [10, 19, 28], "thei": [10, 11, 14, 17, 20, 24, 27, 28, 29, 30], "regs_p": 10, "rl_dst": 10, "destin": 10, "operand": [10, 20, 25, 26], "rl_s1": 10, "rl_s2": 10, "rob_id": 10, "entri": [10, 12, 13, 20, 24, 25, 26, 30, 32], "rp_dst": 10, "rp_s1": 10, "rp_s2": 10, "s1_val": 10, "s2_val": 10, "side_fx": 10, "side": [10, 14, 20, 25, 26], "effect": [10, 14, 20, 25, 26, 29, 30], "fetcher": 10, "access_fault": 10, "fail": [10, 20, 32], "produc": [10, 17], "jumpbranchlayout": 10, "verify_branch": 10, "predictor": 10, "about": [10, 17, 19, 29, 30, 32], "lsulayout": 10, "pmalayout": 10, "ratlayout": [10, 12], "tabl": [10, 19], "old_rp_dst": 10, "previous": [10, 11], "rrat": [10, 14], "rflayout": [10, 12], "roblayout": [10, 12], "done": [10, 20, 27, 28, 29, 30, 31], "yet": [10, 29], "latest": [10, 27, 30], "rob_data": 10, "earliest": [10, 14], "rsinterfacelayout": 10, "rs_entries_bit": 10, "data_layout": [10, 12, 30, 32], "shapelik": [10, 29, 30, 32], "layoutlist": [10, 29, 30, 32], "rslayout": [10, 12], "ready_list": 10, "bitmask": 10, "run": [10, 17, 27, 28, 29, 30, 31, 33], "retirementlayout": 10, "current": [10, 12, 14, 20, 29], "schedulerlayout": 10, "regs_l_rob_in": 10, "befor": [10, 11, 14, 17, 23, 24, 28, 30], "alloc": [10, 12, 24, 25, 26], "regs_p_alloc_out": 10, "rs_entry_id": 10, "rs_select": 10, "confus": 10, "address_gener": 10, "arithmet": 10, "bit_manipul": 10, "bit_rot": 10, "compar": [10, 19], "csr_imm": [10, 14], "csr_reg": [10, 14], "div_rem": 10, "34": 10, "33": 10, "single_bit_manipul": 10, "unary_bit_manipulation_1": 10, "unary_bit_manipulation_2": 10, "unary_bit_manipulation_3": 10, "unary_bit_manipulation_4": 10, "unary_bit_manipulation_5": 10, "unknown": [10, 17, 29, 30, 32], "optypes_required_by_extens": 10, "resolve_impl": 10, "ignore_unsupport": 10, "axiliteinterfac": 11, "abstractinterfac": 11, "abstractsignatur": 11, "read_address": 11, "axilitereadaddressinterfac": 11, "read_data": 11, "axilitereaddatainterfac": 11, "write_address": 11, "axilitewriteaddressinterfac": 11, "write_data": 11, "axilitewritedatainterfac": 11, "write_respons": 11, "axilitewriteresponseinterfac": 11, "axilitemast": 11, "axi": 11, "lite": 11, "axil_param": 11, "axiliteparamet": 11, "ra_request": 11, "channel": 11, "being": [11, 17, 30, 32, 33], "ra_request_layout": 11, "argument": [11, 12, 17, 19, 26, 27, 29, 30, 31, 32, 33], "rd_respons": 11, "availab": 11, "state": [11, 19, 20, 28, 29, 30, 31], "rd_response_layout": 11, "wa_request": 11, "wa_request_layout": 11, "wd_request": 11, "wd_request_layout": 11, "wr_respons": 11, "wr_response_layout": 11, "axil_mast": 11, "result_handl": 11, "tmodul": [11, 14, 28, 29, 30], "start_request_transact": 11, "is_address_channel": 11, "state_machine_request": 11, "request_sign": 11, "data_width": 11, "must": [11, 29, 30, 32], "axilitesignatur": 11, "signatur": 11, "patamet": 11, "axilitemasteradapt": 11, "where": [11, 12, 17, 20, 25, 26, 28, 29, 30, 31, 32], "expect": 11, "busparametersinterfac": 11, "method_layout": 11, "commonbusmastermethodlayout": 11, "request_read": 11, "underli": 11, "request_read_layout": 11, "request_writ": 11, "request_write_layout": 11, "get_read_respons": 11, "action": [11, 14, 29, 30, 32], "read_response_layout": 11, "get_write_respons": 11, "write_response_layout": 11, "prefer": [11, 28], "gain": 11, "simplifi": 11, "interchang": 11, "buse": 11, "sent": [11, 13, 31], "wishbonemasteradapt": 11, "wishbonemast": 11, "pipelinedwishbonemast": 11, "wb_param": 11, "wishboneparamet": 11, "max_req": 11, "limit": [11, 28, 30], "pend": 11, "wb": 11, "request_layout": 11, "complet": [11, 13, 20], "result_layout": 11, "requests_finish": 11, "generate_method_layout": 11, "wishbonearbit": 11, "arbit": 11, "slave": 11, "cyc": 11, "grant": [11, 28, 29, 30, 33], "round": [11, 29, 32, 33], "robin": [11, 29, 33], "num_slav": 11, "devic": 11, "slave_wb": 11, "intefac": 11, "num_mast": 11, "ack": 11, "adr": 11, "dat_r": 11, "dat_w": 11, "err": 11, "lock": [11, 17, 20, 28, 29, 30], "rst": 11, "rty": 11, "stall": [11, 14, 20], "stb": 11, "wb_master": 11, "becom": 11, "wishbonemastermethodlayout": 11, "wishbonememoryslav": 11, "underneath": 11, "keyword": [11, 28, 29, 30, 31, 32], "re": [11, 20, 23, 28, 29], "infer": [11, 29], "wishbonemux": 11, "muxer": 11, "multiplex": [11, 28], "ssel_tga": 11, "corespond": 11, "tga": 11, "so": [11, 13, 20, 27, 28, 29, 30], "note": [11, 14, 30], "stare": 11, "finish": [11, 13, 14, 30], "clear": [11, 25, 26, 30], "delai": [11, 28], "deassert": [11, 33], "master_wb": 11, "singal": 11, "granular": [11, 30], "smallest": 11, "port": [11, 30, 32, 33], "capabl": 11, "wishbonesignatur": 11, "path": [11, 29, 30, 32], "src_loc_at": [11, 32], "prepar": [12, 17, 20, 29], "In": [12, 17, 18, 19, 26, 27, 28, 29, 32], "renam": [12, 24], "without": [12, 13, 20, 30, 32], "stuck": 12, "get_instr": 12, "get_free_reg": 12, "rat_renam": 12, "rob_put": 12, "rf_read1": 12, "rf_read2": 12, "reservation_st": 12, "decoded_instr": 12, "free": [12, 19, 20, 26], "rat_rename_in": 12, "rat_rename_out": 12, "rf_read_out": 12, "rf_read_in": 12, "wakeupselect": 12, "wakeup": [12, 26], "firstli": 12, "get_readi": 12, "binari": [12, 27, 33], "th": [12, 30, 33], "posit": [12, 25, 26, 32], "row": [12, 17, 19], "taken": [12, 27, 29, 30], "take_row": 12, "get_ready_list_out": 12, "take_out": 12, "push": 12, "down": [12, 32], "resultannounc": 13, "mark": [13, 19, 20, 29], "also": [13, 17, 27, 28, 30, 31, 32], "more": [13, 17, 19, 20, 30, 32], "than": [13, 20, 30, 32], "manytooneconnecttran": [13, 30], "rob_mark_don": 13, "rs_updat": 13, "rf_write": 13, "funcblocksunifi": 13, "extra_methods_requir": 13, "get_extra_method": 13, "item": [13, 32, 33], "rob_peek": 13, "rob_retir": 13, "r_rat_commit": 13, "r_rat_peek": 13, "free_rf_put": 13, "rf_free": 13, "exception_cause_get": 13, "exception_cause_clear": 13, "frat_renam": 13, "fetch_continu": [13, 14], "instr_decr": 13, "trap_entri": 13, "rsfuncblock": 13, "With": 13, "csrlistkei": 14, "listkei": [14, 30, 32], "csrregist": 14, "dependencymanag": [14, 29, 30, 31, 32], "behaviour": [14, 27], "automat": [14, 17, 27, 32], "csrunit": 14, "bodi": [14, 28, 29, 30], "csr_val": 14, "els": [14, 20, 28, 29], "_fu_read": 14, "_fu_writ": 14, "ignor": 14, "prioriti": [14, 28, 29, 30], "csr_number": 14, "ro_bit": 14, "mask": [14, 30], "those": [14, 20, 29], "upper": 14, "0b11": 14, "discard": 14, "regitst": 14, "unitl": 14, "resum": 14, "privilegelevel": 14, "csr_access_privileg": 14, "csr_addr": 14, "csraddress": 14, "3072": 14, "cycleh": 14, "3200": 14, "instret": 14, "3074": 14, "instreth": 14, "3202": 14, "mcaus": 14, "834": 14, "mepc": 14, "833": 14, "mtvec": 14, "773": 14, "3073": 14, "timeh": 14, "3201": 14, "doublecountercsr": 14, "group": 14, "At": 14, "overflow": [14, 30], "low_addr": 14, "high_addr": 14, "lower": [14, 32], "higher": 14, "synthetis": 14, "machinemodecsrregist": 14, "exceptioncauseregist": 14, "reorderbuff": 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11, 20, 25, 26], "index": [3, 10, 29, 33], "offset": 3, "unsigned_multipl": [4, 7], "common": [4, 7, 11, 30, 32], "fast_recurs": [4, 7], "sequenc": [4, 7, 12, 30], "shift": [4, 7, 10], "class": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 28, 29, 30, 31, 32, 33], "base": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 20, 29, 30, 31, 32, 33], "elaborat": [4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 28, 29, 30, 31, 32], "__init__": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 28, 29, 30, 31, 32, 33], "gen_param": [4, 6, 7, 8, 9, 10, 12, 13, 14], "wb_instr_bu": 4, "wishboneinterfac": [4, 11], "wb_data_bu": 4, "cacheinterfac": [5, 6], "A": [5, 10, 11, 27, 28, 29, 30, 32], "simpl": [5, 6, 9, 12, 13, 29, 30, 32, 33], "associ": [5, 10, 30], "instruct": [5, 6, 7, 9, 10, 12, 13, 14, 19, 20, 24, 25, 27], "replac": [5, 8, 10, 25], "polici": 5, "pseudo": 5, "random": [5, 31], "scheme": 5, "everi": [5, 7, 11, 17, 27, 29, 30], "time": [5, 11, 14, 20, 29, 30], "trash": 5, "we": [5, 9, 11, 13, 20, 24, 25, 26, 27, 28, 31], "select": [5, 6, 7, 9, 11, 12, 13, 14, 15, 17], "next": [5, 6, 9, 12, 13, 14, 20, 29, 33], "wai": [5, 7, 11, 17, 20, 27, 28, 29, 30, 32], "keep": [5, 29], "global": [5, 14, 20], "counter": [5, 10, 14, 17, 30], "abstract": [5, 8, 10, 27, 30, 32], "awai": 5, "need": [5, 11, 17, 20, 25, 28, 29], "two": [5, 10, 14, 20, 23, 27, 28, 29, 30, 31, 32], "refiller_start": 5, "call": [5, 7, 12, 14, 17, 23, 25, 28, 29, 30, 31, 32], "whenev": 5, "refiller_accept": 5, "readi": [5, 9, 10, 11, 12, 13, 14, 19, 25, 29, 30], "word": [5, 10], "written": [5, 14, 26, 27, 30], "last": [5, 10, 12, 14, 29, 30], "when": [5, 11, 14, 17, 20, 23, 25, 26, 28, 29, 30, 31, 32, 33], "either": [5, 11, 28, 29, 30, 32, 33], "transfer": [5, 11, 29, 30], "over": [5, 14, 29, 30], "shouldn": [5, 27], "t": [5, 6, 9, 10, 17, 20, 23, 25, 27, 28, 29, 30, 31, 32], "until": [5, 20, 30], "start": [5, 7, 9, 10, 11, 20, 29, 30], "icachelayout": [5, 10], "icacheparamet": [5, 10], "cacherefillerinterfac": 5, "none": [5, 6, 7, 9, 10, 13, 14, 29, 30, 31, 32, 33], "paramet": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 28, 29, 30, 31, 32, 33], "instanc": [5, 6, 7, 9, 12, 13, 27, 29, 30, 31, 32], "us": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 19, 20, 23, 27, 28, 29, 30, 31, 32, 33], "creat": [5, 8, 11, 17, 27, 28, 29, 30, 31, 32, 33], "gener": [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 18, 20, 23, 27, 29, 30, 31, 32], "input": [5, 6, 7, 11, 13, 14, 20, 25, 26, 28, 29, 30, 33], "start_refil": 5, "accept_refil": 5, "deserialize_addr": 5, "raw_addr": 5, "valu": [5, 6, 7, 9, 10, 11, 12, 13, 14, 19, 23, 25, 26, 29, 30, 31, 32, 33], "dict": [5, 11, 28, 29, 30, 31, 32, 33], "str": [5, 10, 11, 29, 30, 31, 32, 33], "amaranth": [5, 6, 7, 10, 11, 23, 27, 28, 29, 30, 31, 32, 33], "hdl": [5, 6, 7, 10, 29, 30, 31, 32, 33], "_ast": [5, 6, 7, 10, 29, 30, 31, 32, 33], "serialize_addr": 5, "addr": [5, 9, 10, 11, 30], "view": [5, 7, 9, 29, 30, 31, 32, 33], "icachebypass": 5, "bus_mast": 5, "busmasterinterfac": [5, 9, 10, 11], "haselabor": [5, 11, 15, 29, 30, 31, 33], "interfac": [5, 6, 8, 9, 11, 12, 13, 14, 19, 27, 28, 29, 30], "whole": [5, 18, 20, 30], "given": [5, 7, 9, 10, 17, 25, 28, 29, 30, 31, 32, 33], "simplecommonbuscacherefil": 5, "decodestag": 6, "decod": [6, 7, 10, 12, 29, 32], "transact": [6, 10, 11, 14, 17, 19, 25, 29, 30, 33], "instanti": [6, 29], "instrdecod": 6, "make": [6, 7, 17, 18, 20, 23, 27, 28, 29, 31], "actual": [6, 17, 19, 28], "combinatori": [6, 28], "manner": [6, 11], "get_raw": 6, "push_decod": 6, "raw": 6, "previou": [6, 11, 20, 30], "step": [6, 12, 17, 20, 27, 28], "e": [6, 10, 17, 20, 23, 28, 30, 32, 33], "g": [6, 10, 17, 20, 23, 28, 30, 32, 33], "fetchlayout": [6, 10], "send": [6, 10, 11, 12, 13], "It": [6, 7, 8, 9, 11, 12, 13, 17, 20, 24, 25, 27, 28, 29, 30, 31, 32, 33], "describ": [6, 10, 12, 13, 20, 27, 29, 30, 31], "decodelayout": [6, 10, 12], "pc": [6, 10, 14, 19], "insid": [6, 27, 28, 29, 30], "increment": [6, 14], "ilen_byt": 6, "cont": [6, 31], "unalignedfetch": 6, "work": [6, 12, 20, 23, 27, 28, 29], "unalign": 6, "perform": [6, 7, 8, 10, 12, 14, 17, 27, 28, 29, 30, 32, 33], "elementari": 6, "compon": [6, 10, 11, 18, 29, 30], "opcod": [6, 10, 25, 26], "funct3": [6, 7, 10], "etc": [6, 10, 28], "connect": [6, 11, 13, 14, 20, 28, 29, 30], "via": [6, 28, 29], "its": [6, 12, 13, 14, 20, 27, 28, 29, 30, 32, 33], "attribut": [6, 7, 8, 9, 10, 11, 13, 14, 29, 30, 32, 33], "signal": [6, 7, 9, 10, 11, 19, 23, 29, 30, 31, 32, 33], "ilen": [6, 10], "out": [6, 7, 8, 11, 13, 18, 19, 29, 30, 33], "identifi": [6, 10, 25, 30, 32], "funct3_v": 6, "1": [6, 7, 8, 10, 12, 14, 20, 25, 26, 27, 28, 29, 30, 31, 32, 33], "funct7": [6, 7, 10], "seven": 6, "funct7_v": 6, "funct12": [6, 10], "twelv": 6, "funct12_v": 6, "rd": [6, 10], "reg_cnt_log": 6, "address": [6, 9, 10, 11, 14, 19, 20], "regist": [6, 10, 12, 14, 20, 24, 30, 32], "rd_v": 6, "rs1": [6, 10], "hold": [6, 11, 14, 30], "first": [6, 7, 10, 12, 20, 25, 26, 27, 28, 30, 31, 32], "rs1_v": 6, "take": [6, 11, 13, 24, 25, 28, 29, 30, 31, 32], "form": [6, 10, 14, 20, 27, 30], "rs2": [6, 10], "second": [6, 7, 10, 12, 25, 26, 27, 30], "rs2_v": 6, "imm": [6, 10], "xlen": [6, 7, 10, 14, 32], "immedi": [6, 10, 11], "provid": [6, 7, 10, 12, 14, 27, 28, 30, 31, 32], "were": [6, 20, 28], "succ": 6, "fencetarget": [6, 10], "successor": 6, "fenc": [6, 10], "pred": 6, "predecessor": 6, "fm": 6, "fencefm": [6, 10], "mode": [6, 10, 17, 20], "csr_alen": [6, 10], "control": [6, 10, 11, 14, 27, 29, 30, 33], "sourc": [6, 10, 12, 17, 25, 29, 30, 32], "type": [6, 7, 10, 17, 29, 30, 31, 32], "defin": [6, 9, 14, 28, 29, 30, 32, 33], "kind": [6, 7, 12, 30, 32], "illeg": 6, "wa": [6, 10, 14, 17, 20, 28, 29, 30, 32], "success": [6, 11, 31], "do": [6, 10, 20, 23, 28, 29], "fit": 6, "support": [6, 9, 10, 12, 17, 19, 29, 30], "constructor": [6, 28, 29, 32], "encod": [6, 20, 29, 32, 33], "object": [6, 7, 9, 10, 11, 27, 28, 29, 30, 31, 32], "repres": [6, 14, 29, 30], "singl": [6, 7, 8, 10, 12, 13, 14, 28, 29, 30, 32], "option": [6, 7, 10, 14, 17, 28, 29, 30, 31, 32, 33], "exist": [6, 28, 32], "instr_type_overrid": 6, "instrtyp": [6, 10], "specifi": [6, 10, 11, 14, 26, 30, 31, 32], "determin": [6, 20, 27, 30, 32], "instrust": 6, "almost": 6, "correct": [6, 9, 20, 25, 26, 27], "rd_zero": 6, "bool": [6, 7, 9, 10, 14, 29, 30, 31, 32, 33], "field": [6, 9, 10, 14, 17, 25, 26, 28, 29, 30, 31, 32], "constant": 6, "zero": [6, 10, 14, 25, 30, 33], "other": [6, 14, 17, 19, 28, 29, 30, 33], "accordingli": 6, "default": [6, 11, 17, 28, 29, 30, 32, 33], "fals": [6, 7, 9, 10, 17, 28, 29, 30, 32, 33], "rs1_zero": 6, "instrdecompress": 6, "decompr_reg": 6, "rvc_reg": 6, "instr_mux": 6, "sel": [6, 11], "list": [6, 7, 10, 11, 14, 17, 19, 23, 27, 29, 30, 31, 32, 33], "int": [6, 7, 8, 9, 10, 11, 13, 14, 29, 30, 31, 32, 33], "enum": [6, 7, 10, 29, 30, 31, 32], "valuecast": [6, 10, 29, 30, 31, 32], "tupl": [6, 7, 10, 11, 12, 13, 14, 29, 30, 32], "is_instr_compress": 6, "alucompon": [7, 10], "functionalcomponentparam": [7, 10, 13], "zba_en": 7, "zbb_enabl": 7, "get_modul": [7, 9, 10, 13, 14], "funcunit": [7, 10, 13, 15], "get_optyp": [7, 9, 10, 13, 14], "alufuncunit": 7, "alu_fn": 7, "alufn": 7, "divcompon": 7, "ipc": [7, 27], "3": [7, 10, 14, 17, 29, 32], "div_fn": 7, "divfn": 7, "decodermanag": 7, "fn": 7, "intflag": [7, 10, 29], "div": [7, 10], "divu": [7, 10], "2": [7, 8, 10, 11, 14, 27, 29, 30, 32], "rem": [7, 10], "remu": [7, 10], "8": [7, 8, 10, 11, 29, 30], "__new__": [7, 10, 14, 29], "get_instruct": 7, "valid": [7, 10, 11, 12, 25, 30, 32, 33], "implement": [7, 9, 11, 18, 19, 20, 24, 30, 32, 33], "format": [7, 17, 27, 28, 29, 30, 32], "divunit": 7, "get_input": 7, "arg": [7, 11, 28, 29, 30, 31, 32, 33], "exceptionfuncunit": 7, "unit_fn": 7, "exceptionunitfn": 7, "exceptionunitcompon": [7, 10], "respons": [7, 11, 12, 17, 29, 30, 31], "decode_fn": 7, "exec_fn": [7, 10], "op": [7, 10], "check_optyp": 7, "manag": [7, 17, 19, 29, 30, 32], "enumer": 7, "get_decod": 7, "auto": 7, "pass": [7, 13, 14, 17, 19, 27, 29, 30, 31, 32], "contructor": 7, "get_funct": 7, "get_op_typ": 7, "jumpbranchfuncunit": 7, "jb_fn": 7, "jumpbranchfn": 7, "jumpcompon": [7, 10], "mulcompon": 7, "mul_unit_typ": 7, "multyp": 7, "dsp_width": [7, 8], "mul_fn": 7, "mulfn": 7, "hot": [7, 20, 33], "wire": [7, 32], "5": [7, 10, 24, 30, 31], "differ": [7, 11, 13, 17, 18, 20, 23, 27, 29, 30, 32], "mul": [7, 10], "mulh": [7, 10], "mulhsu": [7, 10], "mulhu": [7, 10], "intenum": [7, 10, 14], "recursive_mul": 7, "fastest": 7, "multipli": [7, 8], "onli": [7, 11, 14, 20, 27, 28, 29, 30, 31, 32], "costli": [7, 20], "term": 7, "resourc": [7, 14, 20, 27, 28], "sequence_mul": 7, "dsp": [7, 8], "balanc": 7, "between": [7, 17, 20, 28, 29, 30, 32, 33], "cost": [7, 19, 28], "shift_mul": 7, "cheapest": 7, "russian": [7, 8], "peasant": [7, 8], "algorithm": [7, 8], "mulunit": 7, "unsign": [7, 8], "integ": [7, 10, 32], "standard": [7, 14, 20, 27, 33], "funcunitlayout": [7, 10, 12, 13], "comput": [7, 8, 9, 14, 20, 30, 32], "mul_typ": 7, "privilegedfn": 7, "mret": [7, 10], "classmethod": [7, 29, 30, 32], "privilegedfuncunit": 7, "gp": [7, 10, 14], "privilegedunitcompon": [7, 10], "shiftfuncunit": 7, "shift_unit_fn": 7, "shiftunitfn": 7, "shiftunitcompon": [7, 10], "clmultipli": 7, "carri": [7, 10, 27], "less": [7, 10], "product": [7, 30], "i1": [7, 8], "n": [7, 8, 10], "factor": 7, "i2": [7, 8], "reset": [7, 14, 19, 29], "new": [7, 9, 11, 14, 19, 20, 29, 30, 32, 33], "busi": 7, "while": [7, 29, 31], "progress": 7, "bit_width": 7, "recursion_depth": 7, "width": [7, 8, 10, 11, 14, 30, 32, 33], "depth": [7, 11, 27, 30], "recurs": [7, 8, 27, 28, 29, 32], "parallel": 7, "assum": [7, 13, 20, 30, 32], "power": [7, 32], "iterative_modul": 7, "recursive_modul": 7, "zbccompon": 7, "zbc_fn": 7, "zbcfn": 7, "clmul": [7, 10], "clmulh": [7, 10], "clmulr": [7, 10], "zbcunit": 7, "execut": [7, 10, 11, 12, 13, 17, 19, 24, 26, 28, 29, 30, 31], "zbsfunction": 7, "in1": 7, "in2": 7, "zbscompon": 7, "bclr": [7, 10], "bext": [7, 10], "binv": [7, 10], "bset": [7, 10], "zbsunit": 7, "zbs_fn": 7, "dspmulunit": 8, "clock": [8, 24, 27, 28, 29, 30], "design": [8, 20, 28, 29], "synthesi": [8, 19], "tool": [8, 17, 27, 29], "o": [8, 20, 28, 29], "same": [8, 9, 17, 28, 29, 30, 32], "number": [8, 10, 11, 13, 17, 20, 27, 29, 30, 31, 32, 33], "mulbaseunsign": 8, "unsignedmulunitlayout": [8, 10], "recursiveunsignedmul": 8, "see": [8, 23, 27, 28, 30], "fast": 8, "within": [8, 17], "sequentialunsignedmul": 8, "sequenti": [8, 11], "classic": [8, 20], "shiftunsignedmul": 8, "cheap": 8, "multi": 8, "lsublockcompon": [9, 10], "blockcomponentparam": [9, 10, 13, 14], "funcblock": [9, 10, 12, 13, 14, 15], "get_rs_entry_count": [9, 10, 13, 14], "lsudummi": 9, "veri": [9, 20, 28], "serial": [9, 13, 30], "all": [9, 10, 11, 14, 17, 19, 20, 23, 28, 29, 30, 32, 33], "store": [9, 10, 13, 14, 20, 25, 26, 29, 30, 32], "load": [9, 10, 20, 30, 32], "isn": [9, 27, 29], "compliant": [9, 27], "riscv": [9, 27], "spec": 9, "doesn": [9, 20, 23, 28, 30], "check": [9, 17, 20, 23, 25, 26, 27, 29, 32], "rang": [9, 29, 30, 31, 32, 33], "reserv": [9, 10, 14, 19, 20], "place": [9, 11, 14, 20, 25, 27, 28, 29, 30], "intruct": 9, "insert": [9, 12, 13, 14, 15, 19, 20, 24, 25], "put": [9, 14, 25, 27, 30], "receiv": [9, 11, 14, 28, 29, 30], "calcul": [9, 30], "end": [9, 10, 13, 20, 30, 32], "further": [9, 17, 30], "get_result": [9, 13, 14, 15, 30], "To": [9, 17, 20, 27, 30, 32], "precommit": [9, 13, 17], "processor": [9, 18, 19, 24], "master": [9, 11, 27], "pmacheck": 9, "physic": [9, 10, 12, 20], "memori": [9, 10, 11, 20, 30], "checker": 9, "mai": [9, 17, 30, 31, 32], "part": [9, 14, 20, 24, 28, 29, 30], "combin": [9, 13, 19, 23, 29, 30, 32], "circuit": [9, 27, 28, 29, 30, 32], "pmalayout": 9, "structlayout": [9, 29, 30, 32], "pmaregion": [9, 10], "contigu": [9, 10], "region": [9, 20], "includ": [9, 27, 28, 29, 30, 32, 33], "both": [9, 25, 28, 29, 30, 32], "begin": [9, 20], "mmio": 9, "true": [9, 10, 11, 28, 29, 30, 31, 32, 33], "indic": [9, 20, 26, 29], "coreconfigur": 10, "func_units_config": 10, "collect": [10, 13, 14, 18, 27, 29, 30, 31, 32, 33], "station": [10, 19], "exampl": [10, 14, 17, 19, 25, 28, 29, 30, 33], "rsblockcompon": [10, 13], "rs_entri": [10, 13, 14], "compress": 10, "enabl": [10, 30, 31, 32], "embed": 10, "reduc": [10, 20, 29], "debug": [10, 17, 32], "hardwar": [10, 19, 24, 28, 30, 32], "disabl": [10, 29, 30, 31], "them": [10, 17, 20, 27, 28, 29, 30, 32], "synthes": [10, 27, 30], "phys_regs_bit": 10, "file": [10, 17, 20, 27, 32], "rob_entries_bit": 10, "reorder": [10, 20, 30], "buffer": [10, 11, 20, 25, 30], "start_pc": 10, "initi": [10, 11, 19, 30, 31], "program": [10, 20, 27, 28], "icache_en": 10, "bypass": 10, "directli": [10, 28, 29], "icache_wai": 10, "icache_sets_bit": 10, "log": [10, 20], "icache_block_size_bit": 10, "allow_partial_extens": 10, "allow": [10, 18, 20, 27, 28, 29, 30, 33], "partial": [10, 29, 30, 32], "_implied_extens": 10, "extenst": 10, "flag": 10, "intern": [10, 19, 28, 29, 30], "definit": [10, 19, 29], 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32, "amaranth_ext": 33, "elaborat": 33}, "envversion": {"sphinx.domains.c": 2, "sphinx.domains.changeset": 1, "sphinx.domains.citation": 1, "sphinx.domains.cpp": 6, "sphinx.domains.index": 1, "sphinx.domains.javascript": 2, "sphinx.domains.math": 2, "sphinx.domains.python": 3, "sphinx.domains.rst": 2, "sphinx.domains.std": 2, "sphinx.ext.todo": 2, "sphinx": 56}}) \ No newline at end of file diff --git a/shared-structs/implementation/rs-impl.html b/shared-structs/implementation/rs-impl.html index 1725febff..ea8bbc9ed 100644 --- a/shared-structs/implementation/rs-impl.html +++ b/shared-structs/implementation/rs-impl.html @@ -252,7 +252,7 @@

    Read and clean row

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/shared-structs/rs.html b/shared-structs/rs.html index f4330cd58..c30ad4991 100644 --- a/shared-structs/rs.html +++ b/shared-structs/rs.html @@ -222,7 +222,7 @@

    External interface signals

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/synthesis/synthesis.html b/synthesis/synthesis.html index ceed6635e..da6d319e7 100644 --- a/synthesis/synthesis.html +++ b/synthesis/synthesis.html @@ -266,7 +266,7 @@

    Regression tests manual execution

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/transactions.html b/transactions.html index 872111e3f..5713da55f 100644 --- a/transactions.html +++ b/transactions.html @@ -409,7 +409,7 @@

    Transaction and method nesting

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/transactron.html b/transactron.html index 9ee5dd0da..b5115876e 100644 --- a/transactron.html +++ b/transactron.html @@ -1791,7 +1791,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/transactron.lib.html b/transactron.lib.html index 6ade3bc3b..a91fcfbd0 100644 --- a/transactron.lib.html +++ b/transactron.lib.html @@ -1269,7 +1269,7 @@

    Submodules
    -__init__(*, data_layout: amaranth.lib.data.StructLayout | collections.abc.Iterable[tuple[str, 'ShapeLike | LayoutList']], elem_count: int, granularity: Optional[int] = None, safe_writes: bool = True, src_loc: int | tuple[str, int] = 0)
    +__init__(*, data_layout: list[tuple[str, 'ShapeLike | LayoutList']], elem_count: int, granularity: Optional[int] = None, safe_writes: bool = True, src_loc: int | tuple[str, int] = 0)
    Parameters
    @@ -1643,7 +1643,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/transactron.testing.html b/transactron.testing.html index af4c4a868..4920ae592 100644 --- a/transactron.testing.html +++ b/transactron.testing.html @@ -399,7 +399,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/transactron.utils.amaranth_ext.html b/transactron.utils.amaranth_ext.html index 7162e1da8..ada0a00ca 100644 --- a/transactron.utils.amaranth_ext.html +++ b/transactron.utils.amaranth_ext.html @@ -293,7 +293,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.

    diff --git a/transactron.utils.html b/transactron.utils.html index c2b37bda6..1742510cf 100644 --- a/transactron.utils.html +++ b/transactron.utils.html @@ -183,7 +183,7 @@

    Submodulestransactron.utils.assign.assign(lhs: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg], rhs: amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | collections.abc.Mapping[str, AssignArg], *, fields: transactron.utils.assign.AssignType | collections.abc.Iterable[str] | collections.abc.Mapping[str, AssignFields] = AssignType.RHS, lhs_strict=False, rhs_strict=False) → Iterable[Assign]

    Safe structured assignment.

    This function recursively generates assignment statements for -field-containing structures. This includes: Amaranth Records, +field-containing structures. This includes: Amaranth Views using StructLayout, Python dicts. In case of mismatching fields or bit widths, error is raised.

    When both lhs and rhs are field-containing, assign generates @@ -192,16 +192,16 @@

    Submodules -

  • Any of lhs or rhs is a Record or View.

    • +

  • Any of lhs or rhs is a View.

  • Both lhs and rhs have an explicitly defined shape (e.g. are a -Signal, a field of a Record or a View).

    • +Signal, a field of a View).

    Parameters
    -
    lhsRecord or View or Value-castable or dict

    Record, signal or dict being assigned.

    +
    lhsView or Value-castable or dict

    View, signal or dict being assigned.

    -
    rhsRecord or View or Value-castable or dict

    Record, signal or dict containing assigned values.

    +
    rhsView or Value-castable or dict

    View, signal or dict containing assigned values.

    fieldsAssignType or Iterable or Mapping, optional

    Determines which fields will be assigned. Possible values:

    @@ -850,7 +850,7 @@

    Submodules

    © Copyright Kuźnia Rdzeni, 2024. - Last updated on 09:58 2024-03-13. + Last updated on 09:21 2024-03-14.