From 182c85a06a2e2370742cdc5104895823a55b0bb4 Mon Sep 17 00:00:00 2001
From: lekcyjna123 <34948061+lekcyjna123@users.noreply.github.com>
Date: Tue, 12 Mar 2024 23:19:51 +0100
Subject: [PATCH] Fix profiles on newer yosys version (#607)

---
 test/regression/cocotb.py | 7 +++----
 transactron/utils/gen.py  | 7 ++-----
 2 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/test/regression/cocotb.py b/test/regression/cocotb.py
index 87c043688..e68c6f9ca 100644
--- a/test/regression/cocotb.py
+++ b/test/regression/cocotb.py
@@ -157,10 +157,9 @@ def get_cocotb_handle(self, path_components: list[str]) -> ModifiableObject:
                 # function instead of 'getattr' - this is required by cocotb.
                 obj = obj._id(component, extended=False)
             except AttributeError:
-                if component[0] == "\\" and component[-1] == " ":
-                    # workaround for cocotb/verilator weirdness
-                    # for some escaped names lookup fails, but works when unescaped
-                    obj = obj._id(component[1:-1], extended=False)
+                # Try with escaped name
+                if component[0] != "\\" and component[-1] != " ":
+                    obj = obj._id("\\" + component + " ", extended=False)
                 else:
                     raise
 
diff --git a/transactron/utils/gen.py b/transactron/utils/gen.py
index 2ff40dec2..f87706750 100644
--- a/transactron/utils/gen.py
+++ b/transactron/utils/gen.py
@@ -149,7 +149,7 @@ def escape_verilog_identifier(identifier: str) -> str:
     # The standard says how to escape a identifier, but not when. So this is
     # a non-exhaustive list of characters that Yosys escapes (it is used
     # by Amaranth when generating Verilog code).
-    characters_to_escape = [".", "$"]
+    characters_to_escape = [".", "$", "-"]
 
     for char in characters_to_escape:
         if char in identifier:
@@ -160,10 +160,7 @@ def escape_verilog_identifier(identifier: str) -> str:
 
 def get_signal_location(signal: Signal, name_map: "SignalDict") -> list[str]:
     raw_location = name_map[signal]
-
-    # Amaranth escapes identifiers when generating Verilog code, but returns non-escaped identifiers
-    # in the name map, so we need to escape it manually.
-    return [escape_verilog_identifier(component) for component in raw_location]
+    return raw_location
 
 
 def collect_metric_locations(name_map: "SignalDict") -> dict[str, MetricLocation]: