diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index 7ed1f3446..bc17e2318 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index 29caa6977..391a370ae 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/coreblocks.doctree b/.doctrees/coreblocks.doctree index 68a27e4e0..dbd636dbd 100644 Binary files a/.doctrees/coreblocks.doctree and b/.doctrees/coreblocks.doctree differ diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree index 8e77bbe0d..72aecad3d 100644 Binary files a/.doctrees/current-graph.doctree and b/.doctrees/current-graph.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index e42a510ad..f7b1bda12 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index ca41387b2..d9ed6efdf 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -6,17 +6,17 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] + WishboneMaster_request["request"] WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_result["result"] - WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] - Forwarder_write["write"] Forwarder_read["read"] + Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] + WishboneMaster1_result["result"] WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] Forwarder1_write["write"] @@ -27,24 +27,24 @@ WishboneMasterAdapter_get_read_response["get_read_response"] WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] - Serializer_serialize_in0["serialize_in0"] Serializer_serialize_out0["serialize_out0"] + Serializer_serialize_in0["serialize_in0"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_write["write"] BasicFifo_read["read"] + BasicFifo_write["write"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] - WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_get_read_response["get_read_response"] + WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_request_read["request_read"] subgraph Serializer1["bus_serializer Serializer"] + Serializer1_serialize_out0["serialize_out0"] + Serializer1_serialize_in1["serialize_in1"] Serializer1_serialize_out1["serialize_out1"] Serializer1_serialize_in0["serialize_in0"] - Serializer1_serialize_in1["serialize_in1"] - Serializer1_serialize_out0["serialize_out0"] subgraph BasicFifo1["pending_requests BasicFifo"] BasicFifo1_write["write"] BasicFifo1_read["read"] @@ -57,27 +57,27 @@ CoreFrontend_target_pred_req["target_pred_req"] CoreFrontend_stall["stall"] subgraph BasicFifo2["instr_buffer BasicFifo"] - BasicFifo2_clear["clear"] - BasicFifo2_write["write"] BasicFifo2_read["read"] + BasicFifo2_write["write"] + BasicFifo2_clear["clear"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_read["read"] Forwarder2_write["write"] + Forwarder2_read["read"] end end subgraph ICache["icache ICache"] ICache_ICache["ICache"] - ICache_flush["flush"] - ICache_ICache1["ICache"] ICache_issue_req["issue_req"] - ICache_MemRead["MemRead"] ICache_accept_res["accept_res"] + ICache_MemRead["MemRead"] + ICache_ICache1["ICache"] + ICache_flush["flush"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -105,13 +105,13 @@ end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_write_results["write_results"] ArgumentsToResultsZipper_write_args["write_args"] - ArgumentsToResultsZipper_peek_arg["peek_arg"] ArgumentsToResultsZipper_read["read"] + ArgumentsToResultsZipper_write_results["write_results"] + ArgumentsToResultsZipper_peek_arg["peek_arg"] subgraph BasicFifo3["fifo BasicFifo"] - BasicFifo3_write["write"] BasicFifo3_peek["peek"] + BasicFifo3_write["write"] BasicFifo3_read["read"] end subgraph Forwarder3["forwarder Forwarder"] @@ -121,14 +121,14 @@ end end subgraph FetchUnit["fetch FetchUnit"] - FetchUnit_Fetch_Stage2["Fetch_Stage2"] FetchUnit_Fetch_Stage0["Fetch_Stage0"] - FetchUnit_resume_from_exception["resume_from_exception"] - FetchUnit_Fetch_Stage1["Fetch_Stage1"] + FetchUnit_Fetch_Stage2["Fetch_Stage2"] + FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] FetchUnit_resume_from_unsafe["resume_from_unsafe"] - FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] FetchUnit_stall_exception["stall_exception"] - FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] + FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] + FetchUnit_resume_from_exception["resume_from_exception"] + FetchUnit_Fetch_Stage1["Fetch_Stage1"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] end @@ -136,24 +136,24 @@ HwCounter5__incr["_incr"] end subgraph Serializer["serializer Serializer"] - Serializer_read["read"] - Serializer_write["write"] Serializer_clean["clean"] + Serializer_write["write"] + Serializer_read["read"] end subgraph ConnectTrans["serializer_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] end subgraph BasicFifo4["cache_requests BasicFifo"] - BasicFifo4_write["write"] BasicFifo4_read["read"] + BasicFifo4_write["write"] end subgraph Semaphore["req_counter Semaphore"] - Semaphore_acquire["acquire"] Semaphore_release["release"] + Semaphore_acquire["acquire"] end subgraph Pipe["s1_s2_pipe Pipe"] - Pipe_write["write"] Pipe_read["read"] + Pipe_write["write"] end subgraph Predecoder["predecoder_0 Predecoder"] Predecoder_predecode["predecode"] @@ -172,9 +172,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] + Pipe1_read["read"] Pipe1_write["write"] Pipe1_clean["clean"] - Pipe1_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -191,15 +191,15 @@ FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_peek["peek"] RRAT_commit["commit"] + RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] + RegisterFile_perf["perf"] RegisterFile_write["write"] - RegisterFile_read2["read2"] RegisterFile_free["free"] RegisterFile_read1["read1"] - RegisterFile_perf["perf"] + RegisterFile_read2["read2"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer__stop["_stop"] TaggedLatencyMeasurer__start["_start"] @@ -217,11 +217,11 @@ end subgraph ReorderBuffer["ROB ReorderBuffer"] ReorderBuffer_perf["perf"] - ReorderBuffer_retire["retire"] - ReorderBuffer_put["put"] + ReorderBuffer_peek["peek"] ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_peek["peek"] + ReorderBuffer_put["put"] + ReorderBuffer_retire["retire"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] FIFOLatencyMeasurer1__stop["_stop"] FIFOLatencyMeasurer1__start["_start"] @@ -242,8 +242,8 @@ ExceptionInformationRegister_clear["clear"] ExceptionInformationRegister_get["get"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] - BasicFifo6_write["write"] BasicFifo6_read["read"] + BasicFifo6_write["write"] end subgraph ConnectTrans1["report_connector ConnectTrans"] ConnectTrans1_ConnectTrans["ConnectTrans"] @@ -266,36 +266,39 @@ subgraph ConnectTrans4["ManyToOneConnectTrans_input_2 ConnectTrans"] ConnectTrans4_ConnectTrans["ConnectTrans"] end + subgraph ConnectTrans5["ManyToOneConnectTrans_input_3 ConnectTrans"] + ConnectTrans5_ConnectTrans["ConnectTrans"] + end end end subgraph MethodProduct["update_combiner MethodProduct"] MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] + RSFuncBlock_select["select"] RSFuncBlock_update["update"] - RSFuncBlock_get_result["get_result"] RSFuncBlock_insert["insert"] - RSFuncBlock_select["select"] + RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] - RS_insert["insert"] RS_RS["RS"] - RS_take["take"] RS_update["update"] + RS_take["take"] RS_RS1["RS"] RS_RS2["RS"] RS_RS3["RS"] + RS_insert["insert"] RS_RS4["RS"] RS_perf["perf"] RS_select["select"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__start["_start"] TaggedLatencyMeasurer1__stop["_stop"] + TaggedLatencyMeasurer1__start["_start"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_read0["read0"] AsyncMemoryBank1_write0["write0"] + AsyncMemoryBank1_read0["read0"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -303,22 +306,22 @@ end end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph TaggedCounter4["perf_instr TaggedCounter"] TaggedCounter4__incr["_incr"] end subgraph FIFO2["fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO3["fifo FIFO"] FIFO3_read["read"] FIFO3_write["write"] @@ -331,8 +334,8 @@ JumpBranchFuncUnit_issue["issue"] JumpBranchFuncUnit_accept["accept"] subgraph FIFO4["fifo_branch_resolved FIFO"] - FIFO4_write["write"] FIFO4_read["read"] + FIFO4_write["write"] end subgraph TaggedCounter5["perf_instr TaggedCounter"] TaggedCounter5__incr["_incr"] @@ -352,11 +355,11 @@ WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] + ExceptionFuncUnit_accept["accept"] subgraph FIFO5["fifo FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -365,11 +368,11 @@ subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] PrivilegedFuncUnit_accept["accept"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] BasicFifo8_read["read"] BasicFifo8_write["write"] @@ -388,39 +391,40 @@ Forwarder5_write["write"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] - subgraph ConnectTrans5["ManyToOneConnectTrans_input_0 ConnectTrans"] - ConnectTrans5_ConnectTrans["ConnectTrans"] - end - subgraph ConnectTrans6["ManyToOneConnectTrans_input_1 ConnectTrans"] + subgraph ConnectTrans6["ManyToOneConnectTrans_input_0 ConnectTrans"] ConnectTrans6_ConnectTrans["ConnectTrans"] end - subgraph ConnectTrans7["ManyToOneConnectTrans_input_2 ConnectTrans"] + subgraph ConnectTrans7["ManyToOneConnectTrans_input_1 ConnectTrans"] ConnectTrans7_ConnectTrans["ConnectTrans"] end - subgraph ConnectTrans8["ManyToOneConnectTrans_input_3 ConnectTrans"] + subgraph ConnectTrans8["ManyToOneConnectTrans_input_2 ConnectTrans"] ConnectTrans8_ConnectTrans["ConnectTrans"] end - subgraph ConnectTrans9["ManyToOneConnectTrans_input_4 ConnectTrans"] + subgraph ConnectTrans9["ManyToOneConnectTrans_input_3 ConnectTrans"] ConnectTrans9_ConnectTrans["ConnectTrans"] end + subgraph ConnectTrans10["ManyToOneConnectTrans_input_4 ConnectTrans"] + ConnectTrans10_ConnectTrans["ConnectTrans"] + end end end end subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] - RSFuncBlock1_select["select"] RSFuncBlock1_get_result["get_result"] - RSFuncBlock1_update["update"] RSFuncBlock1_insert["insert"] - subgraph FifoRS["rs FifoRS"] - FifoRS_FifoRS["FifoRS"] - FifoRS_take["take"] - FifoRS_perf["perf"] - FifoRS_update["update"] - FifoRS_select["select"] - FifoRS_insert["insert"] + RSFuncBlock1_select["select"] + RSFuncBlock1_update["update"] + subgraph RS1["rs RS"] + RS1_update["update"] + RS1_RS["RS"] + RS1_perf["perf"] + RS1_insert["insert"] + RS1_take["take"] + RS1_select["select"] + RS1_RS1["RS"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer2__start["_start"] TaggedLatencyMeasurer2__stop["_stop"] + TaggedLatencyMeasurer2__start["_start"] subgraph HwExpHistogram7["histogram HwExpHistogram"] HwExpHistogram7__add["_add"] end @@ -433,67 +437,156 @@ HwExpHistogram8__add["_add"] end end + subgraph MulUnit["func_unit_0 MulUnit"] + MulUnit_issue["issue"] + MulUnit_accept["accept"] + MulUnit_MulUnit["MulUnit"] + subgraph FIFO6["result_fifo FIFO"] + FIFO6_read["read"] + FIFO6_write["write"] + end + subgraph FIFO7["params_fifo FIFO"] + FIFO7_read["read"] + FIFO7_write["write"] + end + subgraph SequentialUnsignedMul["multiplier SequentialUnsignedMul"] + SequentialUnsignedMul_issue["issue"] + SequentialUnsignedMul_accept["accept"] + subgraph DSPMulUnit["dsp DSPMulUnit"] + DSPMulUnit_compute["compute"] + end + subgraph RecursiveWithSingleDSPMul["multiplier RecursiveWithSingleDSPMul"] + RecursiveWithSingleDSPMul_RecursiveWithSingleDSPMul["RecursiveWithSingleDSPMul"] + end + end + end + subgraph WakeupSelect5["wakeup_select_0 WakeupSelect"] + WakeupSelect5_WakeupSelect["WakeupSelect"] + end + subgraph DivUnit["func_unit_1 DivUnit"] + DivUnit_DivUnit["DivUnit"] + DivUnit_issue["issue"] + DivUnit_accept["accept"] + subgraph BasicFifo9["result_fifo BasicFifo"] + BasicFifo9_read["read"] + BasicFifo9_write["write"] + end + subgraph FIFO8["params_fifo FIFO"] + FIFO8_write["write"] + FIFO8_read["read"] + end + subgraph LongDivider["divider LongDivider"] + LongDivider_issue["issue"] + LongDivider_accept["accept"] + end + end + subgraph WakeupSelect6["wakeup_select_1 WakeupSelect"] + WakeupSelect6_WakeupSelect["WakeupSelect"] + end + subgraph Collector2["collector Collector"] + Collector2_method["method"] + subgraph Forwarder6["forwarder Forwarder"] + Forwarder6_read["read"] + Forwarder6_write["write"] + end + subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] + subgraph ConnectTrans11["ManyToOneConnectTrans_input_0 ConnectTrans"] + ConnectTrans11_ConnectTrans["ConnectTrans"] + end + subgraph ConnectTrans12["ManyToOneConnectTrans_input_1 ConnectTrans"] + ConnectTrans12_ConnectTrans["ConnectTrans"] + end + end + end + end + subgraph RSFuncBlock2["rs_block_2 RSFuncBlock"] + RSFuncBlock2_select["select"] + RSFuncBlock2_get_result["get_result"] + RSFuncBlock2_insert["insert"] + RSFuncBlock2_update["update"] + subgraph FifoRS["rs FifoRS"] + FifoRS_insert["insert"] + FifoRS_FifoRS["FifoRS"] + FifoRS_select["select"] + FifoRS_update["update"] + FifoRS_take["take"] + FifoRS_perf["perf"] + subgraph TaggedLatencyMeasurer3["perf_rs_wait_time TaggedLatencyMeasurer"] + TaggedLatencyMeasurer3__start["_start"] + TaggedLatencyMeasurer3__stop["_stop"] + subgraph HwExpHistogram9["histogram HwExpHistogram"] + HwExpHistogram9__add["_add"] + end + subgraph AsyncMemoryBank3["slots AsyncMemoryBank"] + AsyncMemoryBank3_write0["write0"] + AsyncMemoryBank3_read0["read0"] + end + end + subgraph HwExpHistogram10["perf_num_full HwExpHistogram"] + HwExpHistogram10__add["_add"] + end + end subgraph LSUDummy["func_unit_0 LSUDummy"] - LSUDummy_accept_cond1["accept_cond1"] - LSUDummy_accept["accept"] LSUDummy_LSUDummy["LSUDummy"] - LSUDummy_accept_cond0["accept_cond0"] LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_accept["accept"] + LSUDummy_issue["issue"] + LSUDummy_accept_cond1["accept_cond1"] + LSUDummy_accept_cond0["accept_cond0"] LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_LSUDummy3["LSUDummy"] - LSUDummy_issue["issue"] subgraph LSURequester["requester LSURequester"] - LSURequester_issue["issue"] - LSURequester_accept_cond1["accept_cond1"] LSURequester_issue_cond2["issue_cond2"] + LSURequester_issue["issue"] + LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept["accept"] LSURequester_issue_cond1["issue_cond1"] LSURequester_accept_cond0["accept_cond0"] - LSURequester_accept["accept"] - LSURequester_issue_cond0["issue_cond0"] - subgraph BasicFifo9["args_fifo BasicFifo"] - BasicFifo9_read["read"] - BasicFifo9_write["write"] + LSURequester_accept_cond1["accept_cond1"] + subgraph BasicFifo10["args_fifo BasicFifo"] + BasicFifo10_read["read"] + BasicFifo10_write["write"] end end - subgraph Forwarder6["requests Forwarder"] - Forwarder6_write["write"] - Forwarder6_read["read"] + subgraph Forwarder7["requests Forwarder"] + Forwarder7_read["read"] + Forwarder7_write["write"] end - subgraph FIFO6["results_noop FIFO"] - FIFO6_read["read"] - FIFO6_write["write"] + subgraph FIFO9["results_noop FIFO"] + FIFO9_read["read"] + FIFO9_write["write"] end - subgraph FIFO7["issued FIFO"] - FIFO7_read["read"] - FIFO7_write["write"] + subgraph FIFO10["issued FIFO"] + FIFO10_write["write"] + FIFO10_read["read"] end - subgraph FIFO8["issued_noop FIFO"] - FIFO8_write["write"] - FIFO8_read["read"] + subgraph FIFO11["issued_noop FIFO"] + FIFO11_write["write"] + FIFO11_read["read"] end end - subgraph WakeupSelect5["wakeup_select_0 WakeupSelect"] - WakeupSelect5_WakeupSelect["WakeupSelect"] + subgraph WakeupSelect7["wakeup_select_0 WakeupSelect"] + WakeupSelect7_WakeupSelect["WakeupSelect"] end - subgraph Collector2["collector Collector"] - Collector2_method["method"] - subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_read["read"] - Forwarder7_write["write"] + subgraph Collector3["collector Collector"] + Collector3_method["method"] + subgraph Forwarder8["forwarder Forwarder"] + Forwarder8_read["read"] + Forwarder8_write["write"] end - subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] - subgraph ConnectTrans10["ManyToOneConnectTrans_input_0 ConnectTrans"] - ConnectTrans10_ConnectTrans["ConnectTrans"] + subgraph ManyToOneConnectTrans3["connect ManyToOneConnectTrans"] + subgraph ConnectTrans13["ManyToOneConnectTrans_input_0 ConnectTrans"] + ConnectTrans13_ConnectTrans["ConnectTrans"] end end end end - subgraph CSRUnit["rs_block_2 CSRUnit"] + subgraph CSRUnit["rs_block_3 CSRUnit"] CSRUnit_get_result["get_result"] - CSRUnit_insert["insert"] - CSRUnit_CSRUnit["CSRUnit"] CSRUnit_select["select"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_update["update"] + CSRUnit_insert["insert"] CSRUnit_fetch_resume["fetch_resume"] end end @@ -528,8 +621,8 @@ end end subgraph CSRRegister4["mscratch CSRRegister"] - CSRRegister4__internal_fu_read["_internal_fu_read"] CSRRegister4__internal_fu_write["_internal_fu_write"] + CSRRegister4__internal_fu_read["_internal_fu_read"] subgraph MethodMap8["fu_write_map MethodMap"] MethodMap8_method["method"] end @@ -547,17 +640,17 @@ end end subgraph AliasedCSR["mstatus AliasedCSR"] - AliasedCSR__fu_read["_fu_read"] AliasedCSR__fu_write["_fu_write"] + AliasedCSR__fu_read["_fu_read"] end subgraph AliasedCSR1["mstatush AliasedCSR"] AliasedCSR1__fu_read["_fu_read"] AliasedCSR1__fu_write["_fu_write"] end subgraph CSRRegister6["mcause CSRRegister"] - CSRRegister6_write["write"] - CSRRegister6__internal_fu_read["_internal_fu_read"] CSRRegister6__internal_fu_write["_internal_fu_write"] + CSRRegister6__internal_fu_read["_internal_fu_read"] + CSRRegister6_write["write"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -569,8 +662,8 @@ end end subgraph CSRRegister7["mtvec CSRRegister"] - CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7_read["read"] + CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7__internal_fu_read["_internal_fu_read"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] @@ -585,8 +678,8 @@ subgraph CSRRegister8["mepc CSRRegister"] CSRRegister8__internal_fu_write["_internal_fu_write"] CSRRegister8_write["write"] - CSRRegister8__internal_fu_read["_internal_fu_read"] CSRRegister8_read["read"] + CSRRegister8__internal_fu_read["_internal_fu_read"] subgraph MethodMap16["fu_write_map MethodMap"] MethodMap16_method["method"] end @@ -598,8 +691,8 @@ end end subgraph CSRRegister9["mtval CSRRegister"] - CSRRegister9__internal_fu_write["_internal_fu_write"] CSRRegister9_write["write"] + CSRRegister9__internal_fu_write["_internal_fu_write"] CSRRegister9__internal_fu_read["_internal_fu_read"] subgraph MethodMap18["fu_write_map MethodMap"] MethodMap18_method["method"] @@ -625,13 +718,13 @@ end end subgraph CSRRegister11["priv_mode CSRRegister"] - CSRRegister11_read["read"] CSRRegister11_write["write"] + CSRRegister11_read["read"] end subgraph CSRRegister12["mstatus_mie CSRRegister"] CSRRegister12_write["write"] - CSRRegister12__internal_fu_write["_internal_fu_write"] CSRRegister12_read["read"] + CSRRegister12__internal_fu_write["_internal_fu_write"] CSRRegister12__internal_fu_read["_internal_fu_read"] subgraph MethodMap24["fu_write_map MethodMap"] MethodMap24_method["method"] @@ -644,10 +737,10 @@ end end subgraph CSRRegister13["mstatus_mpie CSRRegister"] + CSRRegister13_write["write"] CSRRegister13__internal_fu_write["_internal_fu_write"] CSRRegister13_read["read"] CSRRegister13__internal_fu_read["_internal_fu_read"] - CSRRegister13_write["write"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -674,9 +767,9 @@ end end subgraph CSRRegister15["mstatus_mprv CSRRegister"] - CSRRegister15__internal_fu_read["_internal_fu_read"] CSRRegister15_write["write"] CSRRegister15__internal_fu_write["_internal_fu_write"] + CSRRegister15__internal_fu_read["_internal_fu_read"] subgraph MethodMap30["fu_write_map MethodMap"] MethodMap30_method["method"] end @@ -688,8 +781,8 @@ end end subgraph CSRRegister16["mstatus_tw CSRRegister"] - CSRRegister16__internal_fu_read["_internal_fu_read"] CSRRegister16__internal_fu_write["_internal_fu_write"] + CSRRegister16__internal_fu_read["_internal_fu_read"] CSRRegister16_read["read"] subgraph MethodMap32["fu_write_map MethodMap"] MethodMap32_method["method"] @@ -713,9 +806,9 @@ end end subgraph CSRRegister18["register_high CSRRegister"] - CSRRegister18__internal_fu_read["_internal_fu_read"] CSRRegister18_read["read"] CSRRegister18_write["write"] + CSRRegister18__internal_fu_read["_internal_fu_read"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] end @@ -724,16 +817,16 @@ subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister19["register_low CSRRegister"] - CSRRegister19_read["read"] CSRRegister19__internal_fu_read["_internal_fu_read"] CSRRegister19_write["write"] + CSRRegister19_read["read"] subgraph MethodMap39["fu_read_map MethodMap"] MethodMap39_method["method"] end end subgraph CSRRegister20["register_high CSRRegister"] - CSRRegister20__internal_fu_read["_internal_fu_read"] CSRRegister20_read["read"] + CSRRegister20__internal_fu_read["_internal_fu_read"] CSRRegister20_write["write"] subgraph MethodMap41["fu_read_map MethodMap"] MethodMap41_method["method"] @@ -742,16 +835,16 @@ end end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] - InternalInterruptController_interrupt_cause["interrupt_cause"] + InternalInterruptController_entry["entry"] + InternalInterruptController_mret["mret"] InternalInterruptController_InternalInterruptController["InternalInterruptController"] + InternalInterruptController_interrupt_cause["interrupt_cause"] InternalInterruptController_InternalInterruptController1["InternalInterruptController"] - InternalInterruptController_mret["mret"] InternalInterruptController_InternalInterruptController2["InternalInterruptController"] - InternalInterruptController_entry["entry"] subgraph CSRRegister21["mie CSRRegister"] - CSRRegister21_read["read"] CSRRegister21__internal_fu_read["_internal_fu_read"] CSRRegister21__internal_fu_write["_internal_fu_write"] + CSRRegister21_read["read"] subgraph MethodMap42["fu_write_map MethodMap"] MethodMap42_method["method"] end @@ -763,11 +856,11 @@ end end subgraph CSRRegister22["mip CSRRegister"] - CSRRegister22__internal_fu_write["_internal_fu_write"] CSRRegister22_read_comb["read_comb"] CSRRegister22__internal_fu_read["_internal_fu_read"] - CSRRegister22_read["read"] CSRRegister22_write["write"] + CSRRegister22_read["read"] + CSRRegister22__internal_fu_write["_internal_fu_write"] subgraph MethodMap44["fu_write_map MethodMap"] MethodMap44_method["method"] end @@ -780,16 +873,16 @@ end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph MethodProduct1["get_instr MethodProduct"] MethodProduct1_method["method"] end subgraph Scheduler["scheduler Scheduler"] - subgraph FIFO9["alloc_rename_buf FIFO"] - FIFO9_write["write"] - FIFO9_read["read"] + subgraph FIFO12["alloc_rename_buf FIFO"] + FIFO12_read["read"] + FIFO12_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -801,69 +894,70 @@ subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] end - subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_write["write"] - FIFO10_read["read"] + subgraph FIFO13["reg_alloc_out_buf FIFO"] + FIFO13_read["read"] + FIFO13_write["write"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] end - subgraph FIFO11["rs_select_out_buf FIFO"] - FIFO11_read["read"] - FIFO11_write["write"] + subgraph FIFO14["rs_select_out_buf FIFO"] + FIFO14_write["write"] + FIFO14_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] RSSelection_RSSelection1["RSSelection"] RSSelection_RSSelection2["RSSelection"] + RSSelection_RSSelection3["RSSelection"] end subgraph RSInsertion["rs_insertion RSInsertion"] RSInsertion_RSInsertion["RSInsertion"] end end subgraph ModuleConnector["fetch_resume_unifiers ModuleConnector"] - subgraph Collector3["FetchResumeKey_unifier Collector"] - Collector3_method["method"] - subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_read["read"] - Forwarder8_write["write"] + subgraph Collector4["FetchResumeKey_unifier Collector"] + Collector4_method["method"] + subgraph Forwarder9["forwarder Forwarder"] + Forwarder9_write["write"] + Forwarder9_read["read"] end - subgraph ManyToOneConnectTrans3["connect ManyToOneConnectTrans"] - subgraph ConnectTrans11["ManyToOneConnectTrans_input_0 ConnectTrans"] - ConnectTrans11_ConnectTrans["ConnectTrans"] + subgraph ManyToOneConnectTrans4["connect ManyToOneConnectTrans"] + subgraph ConnectTrans14["ManyToOneConnectTrans_input_0 ConnectTrans"] + ConnectTrans14_ConnectTrans["ConnectTrans"] end - subgraph ConnectTrans12["ManyToOneConnectTrans_input_1 ConnectTrans"] - ConnectTrans12_ConnectTrans["ConnectTrans"] + subgraph ConnectTrans15["ManyToOneConnectTrans_input_1 ConnectTrans"] + ConnectTrans15_ConnectTrans["ConnectTrans"] end end end end - subgraph ConnectTrans13["fetch_resume_connector ConnectTrans"] - ConnectTrans13_ConnectTrans["ConnectTrans"] + subgraph ConnectTrans16["fetch_resume_connector ConnectTrans"] + ConnectTrans16_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement["Retirement"] + Retirement_Retirement1["Retirement"] Retirement_Retirement_cond1["Retirement_cond1"] Retirement_core_state["core_state"] - Retirement_precommit["precommit"] - Retirement_Retirement1["Retirement"] Retirement_Retirement2["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] + Retirement_precommit["precommit"] Retirement_Retirement3["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister23["register_low CSRRegister"] - CSRRegister23_read["read"] CSRRegister23__internal_fu_read["_internal_fu_read"] CSRRegister23_write["write"] + CSRRegister23_read["read"] subgraph MethodMap47["fu_read_map MethodMap"] MethodMap47_method["method"] end end subgraph CSRRegister24["register_high CSRRegister"] CSRRegister24_read["read"] - CSRRegister24_write["write"] CSRRegister24__internal_fu_read["_internal_fu_read"] + CSRRegister24_write["write"] subgraph MethodMap49["fu_read_map MethodMap"] MethodMap49_method["method"] end @@ -873,14 +967,14 @@ HwCounter9__incr["_incr"] end subgraph FIFOLatencyMeasurer2["perf_trap_latency FIFOLatencyMeasurer"] - FIFOLatencyMeasurer2__start["_start"] FIFOLatencyMeasurer2__stop["_stop"] - subgraph HwExpHistogram9["histogram HwExpHistogram"] - HwExpHistogram9__add["_add"] + FIFOLatencyMeasurer2__start["_start"] + subgraph HwExpHistogram11["histogram HwExpHistogram"] + HwExpHistogram11__add["_add"] end - subgraph FIFO12["fifo FIFO"] - FIFO12_write["write"] - FIFO12_read["read"] + subgraph FIFO15["fifo FIFO"] + FIFO15_read["read"] + FIFO15_write["write"] end end end @@ -888,39 +982,39 @@ end subgraph TransactionManager["transaction_manager TransactionManager"] TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit["PrivilegedFuncUnit_cond1_PrivilegedFuncUnit"] + TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] + TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit["PrivilegedFuncUnit_cond3_PrivilegedFuncUnit"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2["Fetch_Stage2_cond0_Fetch_Stage2"] - TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0["Fetch_Stage2_Fetch_Stage2_cond0"] + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1["Fetch_Stage2_Fetch_Stage2_cond1"] TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit["PrivilegedFuncUnit_cond0_PrivilegedFuncUnit"] - TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2["Fetch_Stage2_cond1_Fetch_Stage2"] - TransactionManager_accept_cond1_accept_cond0_ConnectTrans["accept_cond1_accept_cond0_ConnectTrans"] - TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit["PrivilegedFuncUnit_cond2_PrivilegedFuncUnit"] - TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] - TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] + TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"] + TransactionManager_accept_cond1_accept_cond0_ConnectTrans["accept_cond1_accept_cond0_ConnectTrans"] + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit["PrivilegedFuncUnit_cond3_PrivilegedFuncUnit"] end end Core_InitFreeRFFifo --> BasicFifo5_write - Retirement_Retirement3 --> BasicFifo5_write - TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write - TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write + Retirement_Retirement1 --> BasicFifo5_write + TransactionManager_Retirement_cond1_Retirement --> BasicFifo5_write + TransactionManager_Retirement_cond0_Retirement --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_serialize_in0 - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request - WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - Serializer_serialize_out0 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 - SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMasterAdapter_request_read + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Serializer_serialize_in0 + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> BasicFifo_write + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMaster_request + WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller + Serializer_serialize_out0 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller + BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller + WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller + Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller + SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Forwarder2_write ICache_ICache1 <--> HwCounter4__incr ArgumentsToResultsZipper_peek_arg --> ICache_MemRead BasicFifo3_peek --> ICache_MemRead @@ -991,31 +1085,39 @@ Pipe1_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation <--> CoreInstructionCounter_increment BasicFifo5_read --> RegAllocation_RegAllocation - RegAllocation_RegAllocation --> FIFO9_write - FIFO10_read --> RSSelection_RSSelection - FIFO10_read --> RSSelection_RSSelection1 - FIFO10_read --> RSSelection_RSSelection2 + RegAllocation_RegAllocation --> FIFO12_write + FIFO13_read --> RSSelection_RSSelection + FIFO13_read --> RSSelection_RSSelection3 + FIFO13_read --> RSSelection_RSSelection1 + FIFO13_read --> RSSelection_RSSelection2 RSFuncBlock_select --> RSSelection_RSSelection RS_select --> RSSelection_RSSelection - RSSelection_RSSelection --> FIFO11_write - RSSelection_RSSelection1 --> FIFO11_write - RSSelection_RSSelection2 --> FIFO11_write - RSFuncBlock1_select --> RSSelection_RSSelection1 + RSSelection_RSSelection --> FIFO14_write + RSSelection_RSSelection3 --> FIFO14_write + RSSelection_RSSelection1 --> FIFO14_write + RSSelection_RSSelection2 --> FIFO14_write + RSFuncBlock1_select --> RSSelection_RSSelection3 + RS1_select --> RSSelection_RSSelection3 + RSFuncBlock2_select --> RSSelection_RSSelection1 FifoRS_select --> RSSelection_RSSelection1 RSSelection_RSSelection2 <--> CSRUnit_select - FIFO11_read --> RSInsertion_RSInsertion + FIFO14_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion Retirement_core_state --> RSInsertion_RSInsertion - Retirement_core_state --> LSUDummy_LSUDummy2 + Retirement_core_state --> LSUDummy_LSUDummy RSInsertion_RSInsertion --> RSFuncBlock_insert RSInsertion_RSInsertion --> RS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer1__start RSInsertion_RSInsertion --> AsyncMemoryBank1_write0 RSInsertion_RSInsertion --> RSFuncBlock1_insert - RSInsertion_RSInsertion --> FifoRS_insert + RSInsertion_RSInsertion --> RS1_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer2__start RSInsertion_RSInsertion --> AsyncMemoryBank2_write0 + RSInsertion_RSInsertion --> RSFuncBlock2_insert + RSInsertion_RSInsertion --> FifoRS_insert + RSInsertion_RSInsertion --> TaggedLatencyMeasurer3__start + RSInsertion_RSInsertion --> AsyncMemoryBank3_write0 RSInsertion_RSInsertion --> CSRUnit_insert BasicFifo6_read --> ConnectTrans1_ConnectTrans ConnectTrans1_ConnectTrans --> ExceptionInformationRegister_report @@ -1025,13 +1127,13 @@ ConnectTrans1_ConnectTrans <--> Serializer_clean ConnectTrans1_ConnectTrans <--> BasicFifo2_clear ConnectTrans1_ConnectTrans <--> Pipe1_clean - ConnectTrans11_ConnectTrans --> Forwarder8_write - ConnectTrans12_ConnectTrans --> Forwarder8_write - BasicFifo8_read --> ConnectTrans11_ConnectTrans - CSRUnit_fetch_resume --> ConnectTrans12_ConnectTrans - Collector3_method --> ConnectTrans13_ConnectTrans - Forwarder8_read --> ConnectTrans13_ConnectTrans - ConnectTrans13_ConnectTrans --> FetchUnit_resume_from_unsafe + ConnectTrans14_ConnectTrans --> Forwarder9_write + ConnectTrans15_ConnectTrans --> Forwarder9_write + BasicFifo8_read --> ConnectTrans14_ConnectTrans + CSRUnit_fetch_resume --> ConnectTrans15_ConnectTrans + Collector4_method --> ConnectTrans16_ConnectTrans + Forwarder9_read --> ConnectTrans16_ConnectTrans + ConnectTrans16_ConnectTrans --> FetchUnit_resume_from_unsafe Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -1042,10 +1144,12 @@ ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> RSFuncBlock1_update + ResultAnnouncement_ResultAnnouncement --> RS1_update + ResultAnnouncement_ResultAnnouncement --> RSFuncBlock2_update ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add - RS_RS3 --> WakeupSelect_WakeupSelect + RS_RS2 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -1069,84 +1173,114 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter4__incr WakeupSelect_WakeupSelect --> FIFO2_write - RS_RS4 --> WakeupSelect1_WakeupSelect + RS_RS1 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write - RS_RS1 --> WakeupSelect2_WakeupSelect + RS_RS --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write WakeupSelect2_WakeupSelect --> TaggedCounter5__incr - RS_RS --> WakeupSelect3_WakeupSelect + RS_RS3 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> BasicFifo6_write - ConnectTrans7_ConnectTrans --> BasicFifo6_write - ConnectTrans9_ConnectTrans --> BasicFifo6_write - ConnectTrans4_ConnectTrans --> BasicFifo6_write + ConnectTrans8_ConnectTrans --> BasicFifo6_write + ConnectTrans10_ConnectTrans --> BasicFifo6_write + ConnectTrans5_ConnectTrans --> BasicFifo6_write + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo6_write TransactionManager_accept_cond1_ConnectTrans --> BasicFifo6_write TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> BasicFifo6_write - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write - RS_RS2 --> WakeupSelect4_WakeupSelect + RS_RS4 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue - ConnectTrans5_ConnectTrans --> Forwarder5_write ConnectTrans6_ConnectTrans --> Forwarder5_write ConnectTrans7_ConnectTrans --> Forwarder5_write ConnectTrans8_ConnectTrans --> Forwarder5_write ConnectTrans9_ConnectTrans --> Forwarder5_write - AluFuncUnit_accept --> ConnectTrans5_ConnectTrans - FIFO2_read --> ConnectTrans5_ConnectTrans - ShiftFuncUnit_accept --> ConnectTrans6_ConnectTrans - FIFO3_read --> ConnectTrans6_ConnectTrans - JumpBranchFuncUnit_accept --> ConnectTrans7_ConnectTrans - BasicFifo7_read --> ConnectTrans7_ConnectTrans - CoreFrontend_target_pred_resp --> ConnectTrans7_ConnectTrans - ConnectTrans7_ConnectTrans <--> HwCounter8__incr - ConnectTrans7_ConnectTrans <--> HwCounter7__incr - ConnectTrans7_ConnectTrans --> FIFO4_write - ExceptionFuncUnit_accept --> ConnectTrans8_ConnectTrans - FIFO5_read --> ConnectTrans8_ConnectTrans - PrivilegedFuncUnit_accept --> ConnectTrans9_ConnectTrans - CSRRegister8_read --> ConnectTrans9_ConnectTrans - ConnectTrans9_ConnectTrans --> BasicFifo8_write - FifoRS_perf --> HwExpHistogram8__add - Forwarder6_read --> LSUDummy_LSUDummy - Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 - Forwarder6_read --> TransactionManager_LSUDummy_issue_cond1 - Forwarder6_read --> TransactionManager_issue_cond0_LSUDummy - LSUDummy_LSUDummy --> FIFO6_write - WakeupSelect5_WakeupSelect --> FIFO6_write - TransactionManager_LSUDummy_issue_cond2 --> FIFO6_write - TransactionManager_LSUDummy_issue_cond1 --> FIFO6_write - TransactionManager_issue_cond0_LSUDummy --> FIFO6_write - LSUDummy_LSUDummy --> FIFO8_write - WakeupSelect5_WakeupSelect --> FIFO8_write - TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write - TransactionManager_LSUDummy_issue_cond1 --> FIFO8_write - TransactionManager_issue_cond0_LSUDummy --> FIFO8_write - LSUDummy_LSUDummy1 --> Retirement_precommit + ConnectTrans10_ConnectTrans --> Forwarder5_write + AluFuncUnit_accept --> ConnectTrans6_ConnectTrans + FIFO2_read --> ConnectTrans6_ConnectTrans + ShiftFuncUnit_accept --> ConnectTrans7_ConnectTrans + FIFO3_read --> ConnectTrans7_ConnectTrans + JumpBranchFuncUnit_accept --> ConnectTrans8_ConnectTrans + BasicFifo7_read --> ConnectTrans8_ConnectTrans + CoreFrontend_target_pred_resp --> ConnectTrans8_ConnectTrans + ConnectTrans8_ConnectTrans <--> HwCounter8__incr + ConnectTrans8_ConnectTrans <--> HwCounter7__incr + ConnectTrans8_ConnectTrans --> FIFO4_write + ExceptionFuncUnit_accept --> ConnectTrans9_ConnectTrans + FIFO5_read --> ConnectTrans9_ConnectTrans + PrivilegedFuncUnit_accept --> ConnectTrans10_ConnectTrans + CSRRegister8_read --> ConnectTrans10_ConnectTrans + ConnectTrans10_ConnectTrans --> BasicFifo8_write + RS1_perf --> HwExpHistogram8__add + SequentialUnsignedMul_accept --> MulUnit_MulUnit + FIFO7_read --> MulUnit_MulUnit + MulUnit_MulUnit --> FIFO6_write + RecursiveWithSingleDSPMul_RecursiveWithSingleDSPMul <--> DSPMulUnit_compute + RS1_RS --> WakeupSelect5_WakeupSelect + RS1_take --> WakeupSelect5_WakeupSelect + RS1_take --> WakeupSelect6_WakeupSelect + WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop + WakeupSelect6_WakeupSelect --> TaggedLatencyMeasurer2__stop + AsyncMemoryBank2_read0 --> WakeupSelect5_WakeupSelect + AsyncMemoryBank2_read0 --> WakeupSelect6_WakeupSelect + WakeupSelect5_WakeupSelect --> HwExpHistogram7__add + WakeupSelect6_WakeupSelect --> HwExpHistogram7__add + WakeupSelect5_WakeupSelect --> MulUnit_issue + WakeupSelect5_WakeupSelect --> FIFO7_write + WakeupSelect5_WakeupSelect --> SequentialUnsignedMul_issue + LongDivider_accept --> DivUnit_DivUnit + FIFO8_read --> DivUnit_DivUnit + DivUnit_DivUnit --> BasicFifo9_write + RS1_RS1 --> WakeupSelect6_WakeupSelect + WakeupSelect6_WakeupSelect --> DivUnit_issue + WakeupSelect6_WakeupSelect --> FIFO8_write + WakeupSelect6_WakeupSelect --> LongDivider_issue + ConnectTrans11_ConnectTrans --> Forwarder6_write + ConnectTrans12_ConnectTrans --> Forwarder6_write + MulUnit_accept --> ConnectTrans11_ConnectTrans + FIFO6_read --> ConnectTrans11_ConnectTrans + DivUnit_accept --> ConnectTrans12_ConnectTrans + BasicFifo9_read --> ConnectTrans12_ConnectTrans + FifoRS_perf --> HwExpHistogram10__add + Forwarder7_read --> LSUDummy_LSUDummy1 + Forwarder7_read --> TransactionManager_LSUDummy_issue_cond2 + Forwarder7_read --> TransactionManager_LSUDummy_issue_cond0 + Forwarder7_read --> TransactionManager_LSUDummy_issue_cond1 + LSUDummy_LSUDummy1 --> FIFO9_write + WakeupSelect7_WakeupSelect --> FIFO9_write + TransactionManager_LSUDummy_issue_cond2 --> FIFO9_write + TransactionManager_LSUDummy_issue_cond0 --> FIFO9_write + TransactionManager_LSUDummy_issue_cond1 --> FIFO9_write + LSUDummy_LSUDummy1 --> FIFO11_write + WakeupSelect7_WakeupSelect --> FIFO11_write + TransactionManager_LSUDummy_issue_cond2 --> FIFO11_write + TransactionManager_LSUDummy_issue_cond0 --> FIFO11_write + TransactionManager_LSUDummy_issue_cond1 --> FIFO11_write + LSUDummy_LSUDummy2 --> Retirement_precommit CSRUnit_CSRUnit --> Retirement_precommit TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> Retirement_precommit TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit --> Retirement_precommit TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit --> Retirement_precommit TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit --> Retirement_precommit - ReorderBuffer_peek --> LSUDummy_LSUDummy1 + ReorderBuffer_peek --> LSUDummy_LSUDummy2 ReorderBuffer_peek --> CSRUnit_CSRUnit - ReorderBuffer_peek --> Retirement_Retirement2 - ReorderBuffer_peek --> Retirement_Retirement3 + ReorderBuffer_peek --> Retirement_Retirement + ReorderBuffer_peek --> Retirement_Retirement1 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit + ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit - ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit - FifoRS_FifoRS --> WakeupSelect5_WakeupSelect - FifoRS_take --> WakeupSelect5_WakeupSelect - WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop - AsyncMemoryBank2_read0 --> WakeupSelect5_WakeupSelect - WakeupSelect5_WakeupSelect --> HwExpHistogram7__add - WakeupSelect5_WakeupSelect --> LSUDummy_issue - WakeupSelect5_WakeupSelect --> Forwarder6_write + ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + FifoRS_FifoRS --> WakeupSelect7_WakeupSelect + FifoRS_take --> WakeupSelect7_WakeupSelect + WakeupSelect7_WakeupSelect --> TaggedLatencyMeasurer3__stop + AsyncMemoryBank3_read0 --> WakeupSelect7_WakeupSelect + WakeupSelect7_WakeupSelect --> HwExpHistogram9__add + WakeupSelect7_WakeupSelect --> LSUDummy_issue + WakeupSelect7_WakeupSelect --> Forwarder7_write MethodMap1_method --> CSRUnit_CSRUnit CSRRegister__internal_fu_read --> CSRUnit_CSRUnit MethodMap3_method --> CSRUnit_CSRUnit @@ -1241,87 +1375,71 @@ ConnectTrans2_ConnectTrans --> Forwarder4_write ConnectTrans3_ConnectTrans --> Forwarder4_write ConnectTrans4_ConnectTrans --> Forwarder4_write + ConnectTrans5_ConnectTrans --> Forwarder4_write RSFuncBlock_get_result --> ConnectTrans2_ConnectTrans Collector1_method --> ConnectTrans2_ConnectTrans Forwarder5_read --> ConnectTrans2_ConnectTrans RSFuncBlock1_get_result --> ConnectTrans3_ConnectTrans Collector2_method --> ConnectTrans3_ConnectTrans - Forwarder7_read --> ConnectTrans3_ConnectTrans - CSRUnit_get_result --> ConnectTrans4_ConnectTrans - ExceptionInformationRegister_get --> Retirement_Retirement2 - ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond1 - ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement3 <--> ReorderBuffer_retire - TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire - TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire - Retirement_Retirement3 <--> FIFOLatencyMeasurer1__stop - TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop - TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop - FIFO1_read --> Retirement_Retirement3 - FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 - FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement3 --> HwExpHistogram3__add - TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add - TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add - CoreInstructionCounter_decrement --> Retirement_Retirement3 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 - RRAT_peek --> Retirement_Retirement3 - RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement3 --> RegisterFile_free - TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free - TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free - Retirement_Retirement3 --> TaggedLatencyMeasurer__stop - TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop - TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop - AsyncMemoryBank_read0 --> Retirement_Retirement3 - AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond1 - AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond0 - Retirement_Retirement3 --> HwExpHistogram1__add - TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add - TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add - Retirement_Retirement3 --> FRAT_rename - TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename + Forwarder6_read --> ConnectTrans3_ConnectTrans + RSFuncBlock2_get_result --> ConnectTrans4_ConnectTrans + Collector3_method --> ConnectTrans4_ConnectTrans + Forwarder8_read --> ConnectTrans4_ConnectTrans + CSRUnit_get_result --> ConnectTrans5_ConnectTrans + ExceptionInformationRegister_get --> Retirement_Retirement + ExceptionInformationRegister_get --> TransactionManager_Retirement_cond1_Retirement + ExceptionInformationRegister_get --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement1 <--> ReorderBuffer_retire + TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire + TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire + Retirement_Retirement1 <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer1__stop + FIFO1_read --> Retirement_Retirement1 + FIFO1_read --> TransactionManager_Retirement_cond1_Retirement + FIFO1_read --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement1 --> HwExpHistogram3__add + TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram3__add + TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram3__add + CoreInstructionCounter_decrement --> Retirement_Retirement1 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement + CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement + RRAT_peek --> Retirement_Retirement1 + RRAT_peek --> TransactionManager_Retirement_cond1_Retirement + Retirement_Retirement1 --> RegisterFile_free + TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free + TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free + Retirement_Retirement1 --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_cond1_Retirement --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_cond0_Retirement --> TaggedLatencyMeasurer__stop + AsyncMemoryBank_read0 --> Retirement_Retirement1 + AsyncMemoryBank_read0 --> TransactionManager_Retirement_cond1_Retirement + AsyncMemoryBank_read0 --> TransactionManager_Retirement_cond0_Retirement + Retirement_Retirement1 --> HwExpHistogram1__add + TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add + TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add + Retirement_Retirement1 --> FRAT_rename + TransactionManager_Retirement_cond1_Retirement --> FRAT_rename TransactionManager_Renaming_ROBAllocation --> FRAT_rename - Retirement_Retirement1 <--> FIFOLatencyMeasurer2__stop - FIFO12_read --> Retirement_Retirement1 - Retirement_Retirement1 --> HwExpHistogram9__add - CSRRegister7_read --> Retirement_Retirement1 - Retirement_Retirement1 --> FetchUnit_resume_from_exception - Retirement_Retirement1 <--> ExceptionInformationRegister_clear - TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 - FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans - FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans - TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> ConnectTrans10_ConnectTrans - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans - TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write - TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> Forwarder7_write - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write - LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans - LSUDummy_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans - LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond0 - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> HwCounter5__incr - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter__incr - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Serializer_write - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> Semaphore_release - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release - Pipe_read --> TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 - Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Predecoder_predecode - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> PredictionChecker_check - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter1__incr - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter2__incr - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter3__incr - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 + Retirement_Retirement3 <--> FIFOLatencyMeasurer2__stop + FIFO15_read --> Retirement_Retirement3 + Retirement_Retirement3 --> HwExpHistogram11__add + CSRRegister7_read --> Retirement_Retirement3 + Retirement_Retirement3 --> FetchUnit_resume_from_exception + Retirement_Retirement3 <--> ExceptionInformationRegister_clear + TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy3 + TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy3 + TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy3 + TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond2 --> BasicFifo10_write + TransactionManager_LSUDummy_issue_cond0 --> BasicFifo10_write + TransactionManager_LSUDummy_issue_cond1 --> BasicFifo10_write + TransactionManager_LSUDummy_issue_cond2 --> FIFO10_write + TransactionManager_LSUDummy_issue_cond0 --> FIFO10_write + TransactionManager_LSUDummy_issue_cond1 --> FIFO10_write + TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> ICache_flush TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit @@ -1336,84 +1454,104 @@ CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement - TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement - TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start - TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start - TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write - TransactionManager_Retirement_Retirement_cond0 --> FIFO12_write - InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 - InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister9_write - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister9_write - TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry - TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 - TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> InternalInterruptController_mret - TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans - Serializer1_serialize_out0 --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 + TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 + LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + LSURequester_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + BasicFifo10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + BasicFifo10_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + FIFO10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + FIFO10_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans13_ConnectTrans + TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans13_ConnectTrans + TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> ConnectTrans13_ConnectTrans + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder8_write + TransactionManager_accept_cond1_ConnectTrans --> Forwarder8_write + TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> Forwarder8_write + LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans + LSUDummy_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + Serializer1_serialize_out1 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 + BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 BasicFifo1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans - BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 WishboneMaster1_result --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans - WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 Forwarder1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans - Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 - LSURequester_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans - LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - BasicFifo9_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans - BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - FIFO7_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans - FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy3 - TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy3 - TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy3 - TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue - TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond2 --> BasicFifo9_write - TransactionManager_LSUDummy_issue_cond1 --> BasicFifo9_write - TransactionManager_issue_cond0_LSUDummy --> BasicFifo9_write - TransactionManager_LSUDummy_issue_cond2 --> FIFO7_write - TransactionManager_LSUDummy_issue_cond1 --> FIFO7_write - TransactionManager_issue_cond0_LSUDummy --> FIFO7_write - TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 - TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit - TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment - CSRRegister23_read --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister23_write - CSRRegister24_read --> TransactionManager_Retirement_Retirement_cond0 - TransactionManager_Retirement_Retirement_cond0 --> CSRRegister24_write - TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr - TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 - TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read - TransactionManager_LSUDummy_issue_cond1 --> Serializer1_serialize_in0 - TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write - TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request - TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request - TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 - TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write - TransactionManager_issue_cond0_LSUDummy --> Serializer1_serialize_in1 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 + TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement2 + TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement2 + TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer2__start + TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer2__start + TransactionManager_Retirement_cond1_Retirement --> FIFO15_write + TransactionManager_Retirement_cond0_Retirement --> FIFO15_write + InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond1_Retirement + InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond1_Retirement --> CSRRegister6_write + TransactionManager_Retirement_cond0_Retirement --> CSRRegister6_write + TransactionManager_Retirement_cond1_Retirement --> CSRRegister8_write + TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write + TransactionManager_Retirement_cond1_Retirement --> CSRRegister9_write + TransactionManager_Retirement_cond0_Retirement --> CSRRegister9_write + TransactionManager_Retirement_cond1_Retirement <--> InternalInterruptController_entry + TransactionManager_Retirement_cond0_Retirement <--> InternalInterruptController_entry TransactionManager_Renaming_ROBAllocation <--> Renaming_Renaming - FIFO9_read --> TransactionManager_Renaming_ROBAllocation + FIFO12_read --> TransactionManager_Renaming_ROBAllocation TransactionManager_Renaming_ROBAllocation --> Connect_write TransactionManager_Renaming_ROBAllocation <--> ROBAllocation_ROBAllocation Connect_read --> TransactionManager_Renaming_ROBAllocation TransactionManager_Renaming_ROBAllocation --> ReorderBuffer_put TransactionManager_Renaming_ROBAllocation <--> FIFOLatencyMeasurer1__start TransactionManager_Renaming_ROBAllocation --> FIFO1_write - TransactionManager_Renaming_ROBAllocation --> FIFO10_write - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - Serializer1_serialize_out1 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_Renaming_ROBAllocation --> FIFO13_write + TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> InternalInterruptController_mret + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2 + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> Semaphore_release + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> Semaphore_release + Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 + Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Predecoder_predecode + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> Predecoder_predecode + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> PredictionChecker_check + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> PredictionChecker_check + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter1__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter1__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter2__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter2__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter3__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write + TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 + FIFO9_read --> TransactionManager_accept_cond1_ConnectTrans + FIFO11_read --> TransactionManager_accept_cond1_ConnectTrans TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_cond0_Retirement --> RRAT_commit + TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment + CSRRegister23_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement --> CSRRegister23_write + CSRRegister24_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_cond0_Retirement --> CSRRegister24_write + TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2_cond1 + TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 + TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write + TransactionManager_LSUDummy_issue_cond0 --> Serializer1_serialize_in1 + TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write + TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write + TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request + TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request + TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + Serializer1_serialize_out0 --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans + TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 + TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read + TransactionManager_LSUDummy_issue_cond1 --> Serializer1_serialize_in0 diff --git a/api.html b/api.html index f2c90a4bd..9f9eeb998 100644 --- a/api.html +++ b/api.html @@ -192,7 +192,7 @@

coreblocks

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/assumptions.html b/assumptions.html index e980f089f..131269d44 100644 --- a/assumptions.html +++ b/assumptions.html @@ -103,7 +103,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/auto_graph.html b/auto_graph.html index c44a8261c..4a7315f3c 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -84,17 +84,17 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] + WishboneMaster_request["request"] WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_result["result"] - WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] - Forwarder_write["write"] Forwarder_read["read"] + Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_result["result"] WishboneMaster1_WishboneMaster["WishboneMaster"] + WishboneMaster1_result["result"] WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] Forwarder1_write["write"] @@ -105,24 +105,24 @@ WishboneMasterAdapter_get_read_response["get_read_response"] WishboneMasterAdapter_request_read["request_read"] subgraph Serializer["bus_serializer Serializer"] - Serializer_serialize_in0["serialize_in0"] Serializer_serialize_out0["serialize_out0"] + Serializer_serialize_in0["serialize_in0"] subgraph BasicFifo["pending_requests BasicFifo"] - BasicFifo_write["write"] BasicFifo_read["read"] + BasicFifo_write["write"] end end end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] - WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_get_read_response["get_read_response"] + WishboneMasterAdapter1_get_write_response["get_write_response"] WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_request_read["request_read"] subgraph Serializer1["bus_serializer Serializer"] + Serializer1_serialize_out0["serialize_out0"] + Serializer1_serialize_in1["serialize_in1"] Serializer1_serialize_out1["serialize_out1"] Serializer1_serialize_in0["serialize_in0"] - Serializer1_serialize_in1["serialize_in1"] - Serializer1_serialize_out0["serialize_out0"] subgraph BasicFifo1["pending_requests BasicFifo"] BasicFifo1_write["write"] BasicFifo1_read["read"] @@ -135,27 +135,27 @@ CoreFrontend_target_pred_req["target_pred_req"] CoreFrontend_stall["stall"] subgraph BasicFifo2["instr_buffer BasicFifo"] - BasicFifo2_clear["clear"] - BasicFifo2_write["write"] BasicFifo2_read["read"] + BasicFifo2_write["write"] + BasicFifo2_clear["clear"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] subgraph Forwarder2["resp_fwd Forwarder"] - Forwarder2_read["read"] Forwarder2_write["write"] + Forwarder2_read["read"] end end subgraph ICache["icache ICache"] ICache_ICache["ICache"] - ICache_flush["flush"] - ICache_ICache1["ICache"] ICache_issue_req["issue_req"] - ICache_MemRead["MemRead"] ICache_accept_res["accept_res"] + ICache_MemRead["MemRead"] + ICache_ICache1["ICache"] + ICache_flush["flush"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -183,13 +183,13 @@ end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_write_results["write_results"] ArgumentsToResultsZipper_write_args["write_args"] - ArgumentsToResultsZipper_peek_arg["peek_arg"] ArgumentsToResultsZipper_read["read"] + ArgumentsToResultsZipper_write_results["write_results"] + ArgumentsToResultsZipper_peek_arg["peek_arg"] subgraph BasicFifo3["fifo BasicFifo"] - BasicFifo3_write["write"] BasicFifo3_peek["peek"] + BasicFifo3_write["write"] BasicFifo3_read["read"] end subgraph Forwarder3["forwarder Forwarder"] @@ -199,14 +199,14 @@ end end subgraph FetchUnit["fetch FetchUnit"] - FetchUnit_Fetch_Stage2["Fetch_Stage2"] FetchUnit_Fetch_Stage0["Fetch_Stage0"] - FetchUnit_resume_from_exception["resume_from_exception"] - FetchUnit_Fetch_Stage1["Fetch_Stage1"] + FetchUnit_Fetch_Stage2["Fetch_Stage2"] + FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] FetchUnit_resume_from_unsafe["resume_from_unsafe"] - FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] FetchUnit_stall_exception["stall_exception"] - FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] + FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] + FetchUnit_resume_from_exception["resume_from_exception"] + FetchUnit_Fetch_Stage1["Fetch_Stage1"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] end @@ -214,24 +214,24 @@ HwCounter5__incr["_incr"] end subgraph Serializer["serializer Serializer"] - Serializer_read["read"] - Serializer_write["write"] Serializer_clean["clean"] + Serializer_write["write"] + Serializer_read["read"] end subgraph ConnectTrans["serializer_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] end subgraph BasicFifo4["cache_requests BasicFifo"] - BasicFifo4_write["write"] BasicFifo4_read["read"] + BasicFifo4_write["write"] end subgraph Semaphore["req_counter Semaphore"] - Semaphore_acquire["acquire"] Semaphore_release["release"] + Semaphore_acquire["acquire"] end subgraph Pipe["s1_s2_pipe Pipe"] - Pipe_write["write"] Pipe_read["read"] + Pipe_write["write"] end subgraph Predecoder["predecoder_0 Predecoder"] Predecoder_predecode["predecode"] @@ -250,9 +250,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] + Pipe1_read["read"] Pipe1_write["write"] Pipe1_clean["clean"] - Pipe1_read["read"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -269,15 +269,15 @@ FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_peek["peek"] RRAT_commit["commit"] + RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] + RegisterFile_perf["perf"] RegisterFile_write["write"] - RegisterFile_read2["read2"] RegisterFile_free["free"] RegisterFile_read1["read1"] - RegisterFile_perf["perf"] + RegisterFile_read2["read2"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer__stop["_stop"] TaggedLatencyMeasurer__start["_start"] @@ -295,11 +295,11 @@ end subgraph ReorderBuffer["ROB ReorderBuffer"] ReorderBuffer_perf["perf"] - ReorderBuffer_retire["retire"] - ReorderBuffer_put["put"] + ReorderBuffer_peek["peek"] ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_peek["peek"] + ReorderBuffer_put["put"] + ReorderBuffer_retire["retire"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] FIFOLatencyMeasurer1__stop["_stop"] FIFOLatencyMeasurer1__start["_start"] @@ -320,8 +320,8 @@ ExceptionInformationRegister_clear["clear"] ExceptionInformationRegister_get["get"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] - BasicFifo6_write["write"] BasicFifo6_read["read"] + BasicFifo6_write["write"] end subgraph ConnectTrans1["report_connector ConnectTrans"] ConnectTrans1_ConnectTrans["ConnectTrans"] @@ -344,36 +344,39 @@ subgraph ConnectTrans4["ManyToOneConnectTrans_input_2 ConnectTrans"] ConnectTrans4_ConnectTrans["ConnectTrans"] end + subgraph ConnectTrans5["ManyToOneConnectTrans_input_3 ConnectTrans"] + ConnectTrans5_ConnectTrans["ConnectTrans"] + end end end subgraph MethodProduct["update_combiner MethodProduct"] MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] + RSFuncBlock_select["select"] RSFuncBlock_update["update"] - RSFuncBlock_get_result["get_result"] RSFuncBlock_insert["insert"] - RSFuncBlock_select["select"] + RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] - RS_insert["insert"] RS_RS["RS"] - RS_take["take"] RS_update["update"] + RS_take["take"] RS_RS1["RS"] RS_RS2["RS"] RS_RS3["RS"] + RS_insert["insert"] RS_RS4["RS"] RS_perf["perf"] RS_select["select"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__start["_start"] TaggedLatencyMeasurer1__stop["_stop"] + TaggedLatencyMeasurer1__start["_start"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_read0["read0"] AsyncMemoryBank1_write0["write0"] + AsyncMemoryBank1_read0["read0"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -381,22 +384,22 @@ end end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph TaggedCounter4["perf_instr TaggedCounter"] TaggedCounter4__incr["_incr"] end subgraph FIFO2["fifo FIFO"] - FIFO2_read["read"] FIFO2_write["write"] + FIFO2_read["read"] end end subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] + ShiftFuncUnit_accept["accept"] subgraph FIFO3["fifo FIFO"] FIFO3_read["read"] FIFO3_write["write"] @@ -409,8 +412,8 @@ JumpBranchFuncUnit_issue["issue"] JumpBranchFuncUnit_accept["accept"] subgraph FIFO4["fifo_branch_resolved FIFO"] - FIFO4_write["write"] FIFO4_read["read"] + FIFO4_write["write"] end subgraph TaggedCounter5["perf_instr TaggedCounter"] TaggedCounter5__incr["_incr"] @@ -430,11 +433,11 @@ WakeupSelect2_WakeupSelect["WakeupSelect"] end subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] - ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] + ExceptionFuncUnit_accept["accept"] subgraph FIFO5["fifo FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -443,11 +446,11 @@ subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] PrivilegedFuncUnit_issue["issue"] PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] PrivilegedFuncUnit_accept["accept"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] BasicFifo8_read["read"] BasicFifo8_write["write"] @@ -466,39 +469,40 @@ Forwarder5_write["write"] end subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] - subgraph ConnectTrans5["ManyToOneConnectTrans_input_0 ConnectTrans"] - ConnectTrans5_ConnectTrans["ConnectTrans"] - end - subgraph ConnectTrans6["ManyToOneConnectTrans_input_1 ConnectTrans"] + subgraph ConnectTrans6["ManyToOneConnectTrans_input_0 ConnectTrans"] ConnectTrans6_ConnectTrans["ConnectTrans"] end - subgraph ConnectTrans7["ManyToOneConnectTrans_input_2 ConnectTrans"] + subgraph ConnectTrans7["ManyToOneConnectTrans_input_1 ConnectTrans"] ConnectTrans7_ConnectTrans["ConnectTrans"] end - subgraph ConnectTrans8["ManyToOneConnectTrans_input_3 ConnectTrans"] + subgraph ConnectTrans8["ManyToOneConnectTrans_input_2 ConnectTrans"] ConnectTrans8_ConnectTrans["ConnectTrans"] end - subgraph ConnectTrans9["ManyToOneConnectTrans_input_4 ConnectTrans"] + subgraph ConnectTrans9["ManyToOneConnectTrans_input_3 ConnectTrans"] ConnectTrans9_ConnectTrans["ConnectTrans"] end + subgraph ConnectTrans10["ManyToOneConnectTrans_input_4 ConnectTrans"] + ConnectTrans10_ConnectTrans["ConnectTrans"] + end end end end subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] - RSFuncBlock1_select["select"] RSFuncBlock1_get_result["get_result"] - RSFuncBlock1_update["update"] RSFuncBlock1_insert["insert"] - subgraph FifoRS["rs FifoRS"] - FifoRS_FifoRS["FifoRS"] - FifoRS_take["take"] - FifoRS_perf["perf"] - FifoRS_update["update"] - FifoRS_select["select"] - FifoRS_insert["insert"] + RSFuncBlock1_select["select"] + RSFuncBlock1_update["update"] + subgraph RS1["rs RS"] + RS1_update["update"] + RS1_RS["RS"] + RS1_perf["perf"] + RS1_insert["insert"] + RS1_take["take"] + RS1_select["select"] + RS1_RS1["RS"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer2__start["_start"] TaggedLatencyMeasurer2__stop["_stop"] + TaggedLatencyMeasurer2__start["_start"] subgraph HwExpHistogram7["histogram HwExpHistogram"] HwExpHistogram7__add["_add"] end @@ -511,67 +515,156 @@ HwExpHistogram8__add["_add"] end end + subgraph MulUnit["func_unit_0 MulUnit"] + MulUnit_issue["issue"] + MulUnit_accept["accept"] + MulUnit_MulUnit["MulUnit"] + subgraph FIFO6["result_fifo FIFO"] + FIFO6_read["read"] + FIFO6_write["write"] + end + subgraph FIFO7["params_fifo FIFO"] + FIFO7_read["read"] + FIFO7_write["write"] + end + subgraph SequentialUnsignedMul["multiplier SequentialUnsignedMul"] + SequentialUnsignedMul_issue["issue"] + SequentialUnsignedMul_accept["accept"] + subgraph DSPMulUnit["dsp DSPMulUnit"] + DSPMulUnit_compute["compute"] + end + subgraph RecursiveWithSingleDSPMul["multiplier RecursiveWithSingleDSPMul"] + RecursiveWithSingleDSPMul_RecursiveWithSingleDSPMul["RecursiveWithSingleDSPMul"] + end + end + end + subgraph WakeupSelect5["wakeup_select_0 WakeupSelect"] + WakeupSelect5_WakeupSelect["WakeupSelect"] + end + subgraph DivUnit["func_unit_1 DivUnit"] + DivUnit_DivUnit["DivUnit"] + DivUnit_issue["issue"] + DivUnit_accept["accept"] + subgraph BasicFifo9["result_fifo BasicFifo"] + BasicFifo9_read["read"] + BasicFifo9_write["write"] + end + subgraph FIFO8["params_fifo FIFO"] + FIFO8_write["write"] + FIFO8_read["read"] + end + subgraph LongDivider["divider LongDivider"] + LongDivider_issue["issue"] + LongDivider_accept["accept"] + end + end + subgraph WakeupSelect6["wakeup_select_1 WakeupSelect"] + WakeupSelect6_WakeupSelect["WakeupSelect"] + end + subgraph Collector2["collector Collector"] + Collector2_method["method"] + subgraph Forwarder6["forwarder Forwarder"] + Forwarder6_read["read"] + Forwarder6_write["write"] + end + subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] + subgraph ConnectTrans11["ManyToOneConnectTrans_input_0 ConnectTrans"] + ConnectTrans11_ConnectTrans["ConnectTrans"] + end + subgraph ConnectTrans12["ManyToOneConnectTrans_input_1 ConnectTrans"] + ConnectTrans12_ConnectTrans["ConnectTrans"] + end + end + end + end + subgraph RSFuncBlock2["rs_block_2 RSFuncBlock"] + RSFuncBlock2_select["select"] + RSFuncBlock2_get_result["get_result"] + RSFuncBlock2_insert["insert"] + RSFuncBlock2_update["update"] + subgraph FifoRS["rs FifoRS"] + FifoRS_insert["insert"] + FifoRS_FifoRS["FifoRS"] + FifoRS_select["select"] + FifoRS_update["update"] + FifoRS_take["take"] + FifoRS_perf["perf"] + subgraph TaggedLatencyMeasurer3["perf_rs_wait_time TaggedLatencyMeasurer"] + TaggedLatencyMeasurer3__start["_start"] + TaggedLatencyMeasurer3__stop["_stop"] + subgraph HwExpHistogram9["histogram HwExpHistogram"] + HwExpHistogram9__add["_add"] + end + subgraph AsyncMemoryBank3["slots AsyncMemoryBank"] + AsyncMemoryBank3_write0["write0"] + AsyncMemoryBank3_read0["read0"] + end + end + subgraph HwExpHistogram10["perf_num_full HwExpHistogram"] + HwExpHistogram10__add["_add"] + end + end subgraph LSUDummy["func_unit_0 LSUDummy"] - LSUDummy_accept_cond1["accept_cond1"] - LSUDummy_accept["accept"] LSUDummy_LSUDummy["LSUDummy"] - LSUDummy_accept_cond0["accept_cond0"] LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_accept["accept"] + LSUDummy_issue["issue"] + LSUDummy_accept_cond1["accept_cond1"] + LSUDummy_accept_cond0["accept_cond0"] LSUDummy_LSUDummy2["LSUDummy"] LSUDummy_LSUDummy3["LSUDummy"] - LSUDummy_issue["issue"] subgraph LSURequester["requester LSURequester"] - LSURequester_issue["issue"] - LSURequester_accept_cond1["accept_cond1"] LSURequester_issue_cond2["issue_cond2"] + LSURequester_issue["issue"] + LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept["accept"] LSURequester_issue_cond1["issue_cond1"] LSURequester_accept_cond0["accept_cond0"] - LSURequester_accept["accept"] - LSURequester_issue_cond0["issue_cond0"] - subgraph BasicFifo9["args_fifo BasicFifo"] - BasicFifo9_read["read"] - BasicFifo9_write["write"] + LSURequester_accept_cond1["accept_cond1"] + subgraph BasicFifo10["args_fifo BasicFifo"] + BasicFifo10_read["read"] + BasicFifo10_write["write"] end end - subgraph Forwarder6["requests Forwarder"] - Forwarder6_write["write"] - Forwarder6_read["read"] + subgraph Forwarder7["requests Forwarder"] + Forwarder7_read["read"] + Forwarder7_write["write"] end - subgraph FIFO6["results_noop FIFO"] - FIFO6_read["read"] - FIFO6_write["write"] + subgraph FIFO9["results_noop FIFO"] + FIFO9_read["read"] + FIFO9_write["write"] end - subgraph FIFO7["issued FIFO"] - FIFO7_read["read"] - FIFO7_write["write"] + subgraph FIFO10["issued FIFO"] + FIFO10_write["write"] + FIFO10_read["read"] end - subgraph FIFO8["issued_noop FIFO"] - FIFO8_write["write"] - FIFO8_read["read"] + subgraph FIFO11["issued_noop FIFO"] + FIFO11_write["write"] + FIFO11_read["read"] end end - subgraph WakeupSelect5["wakeup_select_0 WakeupSelect"] - WakeupSelect5_WakeupSelect["WakeupSelect"] + subgraph WakeupSelect7["wakeup_select_0 WakeupSelect"] + WakeupSelect7_WakeupSelect["WakeupSelect"] end - subgraph Collector2["collector Collector"] - Collector2_method["method"] - subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_read["read"] - Forwarder7_write["write"] + subgraph Collector3["collector Collector"] + Collector3_method["method"] + subgraph Forwarder8["forwarder Forwarder"] + Forwarder8_read["read"] + Forwarder8_write["write"] end - subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] - subgraph ConnectTrans10["ManyToOneConnectTrans_input_0 ConnectTrans"] - ConnectTrans10_ConnectTrans["ConnectTrans"] + subgraph ManyToOneConnectTrans3["connect ManyToOneConnectTrans"] + subgraph ConnectTrans13["ManyToOneConnectTrans_input_0 ConnectTrans"] + ConnectTrans13_ConnectTrans["ConnectTrans"] end end end end - subgraph CSRUnit["rs_block_2 CSRUnit"] + subgraph CSRUnit["rs_block_3 CSRUnit"] CSRUnit_get_result["get_result"] - CSRUnit_insert["insert"] - CSRUnit_CSRUnit["CSRUnit"] CSRUnit_select["select"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_update["update"] + CSRUnit_insert["insert"] CSRUnit_fetch_resume["fetch_resume"] end end @@ -606,8 +699,8 @@ end end subgraph CSRRegister4["mscratch CSRRegister"] - CSRRegister4__internal_fu_read["_internal_fu_read"] CSRRegister4__internal_fu_write["_internal_fu_write"] + CSRRegister4__internal_fu_read["_internal_fu_read"] subgraph MethodMap8["fu_write_map MethodMap"] MethodMap8_method["method"] end @@ -625,17 +718,17 @@ end end subgraph AliasedCSR["mstatus AliasedCSR"] - AliasedCSR__fu_read["_fu_read"] AliasedCSR__fu_write["_fu_write"] + AliasedCSR__fu_read["_fu_read"] end subgraph AliasedCSR1["mstatush AliasedCSR"] AliasedCSR1__fu_read["_fu_read"] AliasedCSR1__fu_write["_fu_write"] end subgraph CSRRegister6["mcause CSRRegister"] - CSRRegister6_write["write"] - CSRRegister6__internal_fu_read["_internal_fu_read"] CSRRegister6__internal_fu_write["_internal_fu_write"] + CSRRegister6__internal_fu_read["_internal_fu_read"] + CSRRegister6_write["write"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -647,8 +740,8 @@ end end subgraph CSRRegister7["mtvec CSRRegister"] - CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7_read["read"] + CSRRegister7__internal_fu_write["_internal_fu_write"] CSRRegister7__internal_fu_read["_internal_fu_read"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] @@ -663,8 +756,8 @@ subgraph CSRRegister8["mepc CSRRegister"] CSRRegister8__internal_fu_write["_internal_fu_write"] CSRRegister8_write["write"] - CSRRegister8__internal_fu_read["_internal_fu_read"] CSRRegister8_read["read"] + CSRRegister8__internal_fu_read["_internal_fu_read"] subgraph MethodMap16["fu_write_map MethodMap"] MethodMap16_method["method"] end @@ -676,8 +769,8 @@ end end subgraph CSRRegister9["mtval CSRRegister"] - CSRRegister9__internal_fu_write["_internal_fu_write"] CSRRegister9_write["write"] + CSRRegister9__internal_fu_write["_internal_fu_write"] CSRRegister9__internal_fu_read["_internal_fu_read"] subgraph MethodMap18["fu_write_map MethodMap"] MethodMap18_method["method"] @@ -703,13 +796,13 @@ end end subgraph CSRRegister11["priv_mode CSRRegister"] - CSRRegister11_read["read"] CSRRegister11_write["write"] + CSRRegister11_read["read"] end subgraph CSRRegister12["mstatus_mie CSRRegister"] CSRRegister12_write["write"] - CSRRegister12__internal_fu_write["_internal_fu_write"] CSRRegister12_read["read"] + CSRRegister12__internal_fu_write["_internal_fu_write"] CSRRegister12__internal_fu_read["_internal_fu_read"] subgraph MethodMap24["fu_write_map MethodMap"] MethodMap24_method["method"] @@ -722,10 +815,10 @@ end end subgraph CSRRegister13["mstatus_mpie CSRRegister"] + CSRRegister13_write["write"] CSRRegister13__internal_fu_write["_internal_fu_write"] CSRRegister13_read["read"] CSRRegister13__internal_fu_read["_internal_fu_read"] - CSRRegister13_write["write"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -752,9 +845,9 @@ end end subgraph CSRRegister15["mstatus_mprv CSRRegister"] - CSRRegister15__internal_fu_read["_internal_fu_read"] CSRRegister15_write["write"] CSRRegister15__internal_fu_write["_internal_fu_write"] + CSRRegister15__internal_fu_read["_internal_fu_read"] subgraph MethodMap30["fu_write_map MethodMap"] MethodMap30_method["method"] end @@ -766,8 +859,8 @@ end end subgraph CSRRegister16["mstatus_tw CSRRegister"] - CSRRegister16__internal_fu_read["_internal_fu_read"] CSRRegister16__internal_fu_write["_internal_fu_write"] + CSRRegister16__internal_fu_read["_internal_fu_read"] CSRRegister16_read["read"] subgraph MethodMap32["fu_write_map MethodMap"] MethodMap32_method["method"] @@ -791,9 +884,9 @@ end end subgraph CSRRegister18["register_high CSRRegister"] - CSRRegister18__internal_fu_read["_internal_fu_read"] CSRRegister18_read["read"] CSRRegister18_write["write"] + CSRRegister18__internal_fu_read["_internal_fu_read"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] end @@ -802,16 +895,16 @@ subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister19["register_low CSRRegister"] - CSRRegister19_read["read"] CSRRegister19__internal_fu_read["_internal_fu_read"] CSRRegister19_write["write"] + CSRRegister19_read["read"] subgraph MethodMap39["fu_read_map MethodMap"] MethodMap39_method["method"] end end subgraph CSRRegister20["register_high CSRRegister"] - CSRRegister20__internal_fu_read["_internal_fu_read"] CSRRegister20_read["read"] + CSRRegister20__internal_fu_read["_internal_fu_read"] CSRRegister20_write["write"] subgraph MethodMap41["fu_read_map MethodMap"] MethodMap41_method["method"] @@ -820,16 +913,16 @@ end end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] - InternalInterruptController_interrupt_cause["interrupt_cause"] + InternalInterruptController_entry["entry"] + InternalInterruptController_mret["mret"] InternalInterruptController_InternalInterruptController["InternalInterruptController"] + InternalInterruptController_interrupt_cause["interrupt_cause"] InternalInterruptController_InternalInterruptController1["InternalInterruptController"] - InternalInterruptController_mret["mret"] InternalInterruptController_InternalInterruptController2["InternalInterruptController"] - InternalInterruptController_entry["entry"] subgraph CSRRegister21["mie CSRRegister"] - CSRRegister21_read["read"] CSRRegister21__internal_fu_read["_internal_fu_read"] CSRRegister21__internal_fu_write["_internal_fu_write"] + CSRRegister21_read["read"] subgraph MethodMap42["fu_write_map MethodMap"] MethodMap42_method["method"] end @@ -841,11 +934,11 @@ end end subgraph CSRRegister22["mip CSRRegister"] - CSRRegister22__internal_fu_write["_internal_fu_write"] CSRRegister22_read_comb["read_comb"] CSRRegister22__internal_fu_read["_internal_fu_read"] - CSRRegister22_read["read"] CSRRegister22_write["write"] + CSRRegister22_read["read"] + CSRRegister22__internal_fu_write["_internal_fu_write"] subgraph MethodMap44["fu_write_map MethodMap"] MethodMap44_method["method"] end @@ -858,16 +951,16 @@ end end subgraph CoreInstructionCounter["core_counter CoreInstructionCounter"] - CoreInstructionCounter_increment["increment"] CoreInstructionCounter_decrement["decrement"] + CoreInstructionCounter_increment["increment"] end subgraph MethodProduct1["get_instr MethodProduct"] MethodProduct1_method["method"] end subgraph Scheduler["scheduler Scheduler"] - subgraph FIFO9["alloc_rename_buf FIFO"] - FIFO9_write["write"] - FIFO9_read["read"] + subgraph FIFO12["alloc_rename_buf FIFO"] + FIFO12_read["read"] + FIFO12_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -879,69 +972,70 @@ subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] end - subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_write["write"] - FIFO10_read["read"] + subgraph FIFO13["reg_alloc_out_buf FIFO"] + FIFO13_read["read"] + FIFO13_write["write"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] end - subgraph FIFO11["rs_select_out_buf FIFO"] - FIFO11_read["read"] - FIFO11_write["write"] + subgraph FIFO14["rs_select_out_buf FIFO"] + FIFO14_write["write"] + FIFO14_read["read"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] RSSelection_RSSelection1["RSSelection"] RSSelection_RSSelection2["RSSelection"] + RSSelection_RSSelection3["RSSelection"] end subgraph RSInsertion["rs_insertion RSInsertion"] RSInsertion_RSInsertion["RSInsertion"] end end subgraph ModuleConnector["fetch_resume_unifiers ModuleConnector"] - subgraph Collector3["FetchResumeKey_unifier Collector"] - Collector3_method["method"] - subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_read["read"] - Forwarder8_write["write"] + subgraph Collector4["FetchResumeKey_unifier Collector"] + Collector4_method["method"] + subgraph Forwarder9["forwarder Forwarder"] + Forwarder9_write["write"] + Forwarder9_read["read"] end - subgraph ManyToOneConnectTrans3["connect ManyToOneConnectTrans"] - subgraph ConnectTrans11["ManyToOneConnectTrans_input_0 ConnectTrans"] - ConnectTrans11_ConnectTrans["ConnectTrans"] + subgraph ManyToOneConnectTrans4["connect ManyToOneConnectTrans"] + subgraph ConnectTrans14["ManyToOneConnectTrans_input_0 ConnectTrans"] + ConnectTrans14_ConnectTrans["ConnectTrans"] end - subgraph ConnectTrans12["ManyToOneConnectTrans_input_1 ConnectTrans"] - ConnectTrans12_ConnectTrans["ConnectTrans"] + subgraph ConnectTrans15["ManyToOneConnectTrans_input_1 ConnectTrans"] + ConnectTrans15_ConnectTrans["ConnectTrans"] end end end end - subgraph ConnectTrans13["fetch_resume_connector ConnectTrans"] - ConnectTrans13_ConnectTrans["ConnectTrans"] + subgraph ConnectTrans16["fetch_resume_connector ConnectTrans"] + ConnectTrans16_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement["Retirement"] + Retirement_Retirement1["Retirement"] Retirement_Retirement_cond1["Retirement_cond1"] Retirement_core_state["core_state"] - Retirement_precommit["precommit"] - Retirement_Retirement1["Retirement"] Retirement_Retirement2["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] + Retirement_precommit["precommit"] Retirement_Retirement3["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister23["register_low CSRRegister"] - CSRRegister23_read["read"] CSRRegister23__internal_fu_read["_internal_fu_read"] CSRRegister23_write["write"] + CSRRegister23_read["read"] subgraph MethodMap47["fu_read_map MethodMap"] MethodMap47_method["method"] end end subgraph CSRRegister24["register_high CSRRegister"] CSRRegister24_read["read"] - CSRRegister24_write["write"] CSRRegister24__internal_fu_read["_internal_fu_read"] + CSRRegister24_write["write"] subgraph MethodMap49["fu_read_map MethodMap"] MethodMap49_method["method"] end @@ -951,14 +1045,14 @@ HwCounter9__incr["_incr"] end subgraph FIFOLatencyMeasurer2["perf_trap_latency FIFOLatencyMeasurer"] - FIFOLatencyMeasurer2__start["_start"] FIFOLatencyMeasurer2__stop["_stop"] - subgraph HwExpHistogram9["histogram HwExpHistogram"] - HwExpHistogram9__add["_add"] + FIFOLatencyMeasurer2__start["_start"] + subgraph HwExpHistogram11["histogram HwExpHistogram"] + HwExpHistogram11__add["_add"] end - subgraph FIFO12["fifo FIFO"] - FIFO12_write["write"] - FIFO12_read["read"] + subgraph FIFO15["fifo FIFO"] + FIFO15_read["read"] + FIFO15_write["write"] end end end @@ -966,39 +1060,39 @@ end subgraph TransactionManager["transaction_manager TransactionManager"] TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit["PrivilegedFuncUnit_cond1_PrivilegedFuncUnit"] + TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] + TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] TransactionManager_LSUDummy_issue_cond2["LSUDummy_issue_cond2"] - TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit["PrivilegedFuncUnit_cond3_PrivilegedFuncUnit"] - TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] - TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2["Fetch_Stage2_cond0_Fetch_Stage2"] - TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0["Fetch_Stage2_Fetch_Stage2_cond0"] + TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1["Fetch_Stage2_Fetch_Stage2_cond1"] TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit["PrivilegedFuncUnit_cond0_PrivilegedFuncUnit"] - TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2["Fetch_Stage2_cond1_Fetch_Stage2"] - TransactionManager_accept_cond1_accept_cond0_ConnectTrans["accept_cond1_accept_cond0_ConnectTrans"] - TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit["PrivilegedFuncUnit_cond2_PrivilegedFuncUnit"] - TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] - TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_LSUDummy_issue_cond1["LSUDummy_issue_cond1"] + TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] + TransactionManager_accept_cond0_ConnectTrans_accept_cond0["accept_cond0_ConnectTrans_accept_cond0"] + TransactionManager_accept_cond1_accept_cond0_ConnectTrans["accept_cond1_accept_cond0_ConnectTrans"] + TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit["PrivilegedFuncUnit_cond3_PrivilegedFuncUnit"] end end Core_InitFreeRFFifo --> BasicFifo5_write -Retirement_Retirement3 --> BasicFifo5_write -TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write -TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write +Retirement_Retirement1 --> BasicFifo5_write +TransactionManager_Retirement_cond1_Retirement --> BasicFifo5_write +TransactionManager_Retirement_cond0_Retirement --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMasterAdapter_request_read -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Serializer_serialize_in0 -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request -WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -Serializer_serialize_out0 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 -SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Forwarder2_write +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMasterAdapter_request_read +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> Serializer_serialize_in0 +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> BasicFifo_write +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1 --> WishboneMaster_request +WishboneMasterAdapter_get_read_response --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller +Serializer_serialize_out0 --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller +BasicFifo_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller +WishboneMaster_result --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller +Forwarder_read --> SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller +SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> Forwarder2_write ICache_ICache1 <--> HwCounter4__incr ArgumentsToResultsZipper_peek_arg --> ICache_MemRead BasicFifo3_peek --> ICache_MemRead @@ -1069,31 +1163,39 @@ Pipe1_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation <--> CoreInstructionCounter_increment BasicFifo5_read --> RegAllocation_RegAllocation -RegAllocation_RegAllocation --> FIFO9_write -FIFO10_read --> RSSelection_RSSelection -FIFO10_read --> RSSelection_RSSelection1 -FIFO10_read --> RSSelection_RSSelection2 +RegAllocation_RegAllocation --> FIFO12_write +FIFO13_read --> RSSelection_RSSelection +FIFO13_read --> RSSelection_RSSelection3 +FIFO13_read --> RSSelection_RSSelection1 +FIFO13_read --> RSSelection_RSSelection2 RSFuncBlock_select --> RSSelection_RSSelection RS_select --> RSSelection_RSSelection -RSSelection_RSSelection --> FIFO11_write -RSSelection_RSSelection1 --> FIFO11_write -RSSelection_RSSelection2 --> FIFO11_write -RSFuncBlock1_select --> RSSelection_RSSelection1 +RSSelection_RSSelection --> FIFO14_write +RSSelection_RSSelection3 --> FIFO14_write +RSSelection_RSSelection1 --> FIFO14_write +RSSelection_RSSelection2 --> FIFO14_write +RSFuncBlock1_select --> RSSelection_RSSelection3 +RS1_select --> RSSelection_RSSelection3 +RSFuncBlock2_select --> RSSelection_RSSelection1 FifoRS_select --> RSSelection_RSSelection1 RSSelection_RSSelection2 <--> CSRUnit_select -FIFO11_read --> RSInsertion_RSInsertion +FIFO14_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion Retirement_core_state --> RSInsertion_RSInsertion -Retirement_core_state --> LSUDummy_LSUDummy2 +Retirement_core_state --> LSUDummy_LSUDummy RSInsertion_RSInsertion --> RSFuncBlock_insert RSInsertion_RSInsertion --> RS_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer1__start RSInsertion_RSInsertion --> AsyncMemoryBank1_write0 RSInsertion_RSInsertion --> RSFuncBlock1_insert -RSInsertion_RSInsertion --> FifoRS_insert +RSInsertion_RSInsertion --> RS1_insert RSInsertion_RSInsertion --> TaggedLatencyMeasurer2__start RSInsertion_RSInsertion --> AsyncMemoryBank2_write0 +RSInsertion_RSInsertion --> RSFuncBlock2_insert +RSInsertion_RSInsertion --> FifoRS_insert +RSInsertion_RSInsertion --> TaggedLatencyMeasurer3__start +RSInsertion_RSInsertion --> AsyncMemoryBank3_write0 RSInsertion_RSInsertion --> CSRUnit_insert BasicFifo6_read --> ConnectTrans1_ConnectTrans ConnectTrans1_ConnectTrans --> ExceptionInformationRegister_report @@ -1103,13 +1205,13 @@ ConnectTrans1_ConnectTrans <--> Serializer_clean ConnectTrans1_ConnectTrans <--> BasicFifo2_clear ConnectTrans1_ConnectTrans <--> Pipe1_clean -ConnectTrans11_ConnectTrans --> Forwarder8_write -ConnectTrans12_ConnectTrans --> Forwarder8_write -BasicFifo8_read --> ConnectTrans11_ConnectTrans -CSRUnit_fetch_resume --> ConnectTrans12_ConnectTrans -Collector3_method --> ConnectTrans13_ConnectTrans -Forwarder8_read --> ConnectTrans13_ConnectTrans -ConnectTrans13_ConnectTrans --> FetchUnit_resume_from_unsafe +ConnectTrans14_ConnectTrans --> Forwarder9_write +ConnectTrans15_ConnectTrans --> Forwarder9_write +BasicFifo8_read --> ConnectTrans14_ConnectTrans +CSRUnit_fetch_resume --> ConnectTrans15_ConnectTrans +Collector4_method --> ConnectTrans16_ConnectTrans +Forwarder9_read --> ConnectTrans16_ConnectTrans +ConnectTrans16_ConnectTrans --> FetchUnit_resume_from_unsafe Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -1120,10 +1222,12 @@ ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> RSFuncBlock1_update +ResultAnnouncement_ResultAnnouncement --> RS1_update +ResultAnnouncement_ResultAnnouncement --> RSFuncBlock2_update ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add -RS_RS3 --> WakeupSelect_WakeupSelect +RS_RS2 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -1147,84 +1251,114 @@ WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> TaggedCounter4__incr WakeupSelect_WakeupSelect --> FIFO2_write -RS_RS4 --> WakeupSelect1_WakeupSelect +RS_RS1 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write -RS_RS1 --> WakeupSelect2_WakeupSelect +RS_RS --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write WakeupSelect2_WakeupSelect --> TaggedCounter5__incr -RS_RS --> WakeupSelect3_WakeupSelect +RS_RS3 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> BasicFifo6_write -ConnectTrans7_ConnectTrans --> BasicFifo6_write -ConnectTrans9_ConnectTrans --> BasicFifo6_write -ConnectTrans4_ConnectTrans --> BasicFifo6_write +ConnectTrans8_ConnectTrans --> BasicFifo6_write +ConnectTrans10_ConnectTrans --> BasicFifo6_write +ConnectTrans5_ConnectTrans --> BasicFifo6_write +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> BasicFifo6_write TransactionManager_accept_cond1_ConnectTrans --> BasicFifo6_write TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> BasicFifo6_write -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write -RS_RS2 --> WakeupSelect4_WakeupSelect +RS_RS4 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue -ConnectTrans5_ConnectTrans --> Forwarder5_write ConnectTrans6_ConnectTrans --> Forwarder5_write ConnectTrans7_ConnectTrans --> Forwarder5_write ConnectTrans8_ConnectTrans --> Forwarder5_write ConnectTrans9_ConnectTrans --> Forwarder5_write -AluFuncUnit_accept --> ConnectTrans5_ConnectTrans -FIFO2_read --> ConnectTrans5_ConnectTrans -ShiftFuncUnit_accept --> ConnectTrans6_ConnectTrans -FIFO3_read --> ConnectTrans6_ConnectTrans -JumpBranchFuncUnit_accept --> ConnectTrans7_ConnectTrans -BasicFifo7_read --> ConnectTrans7_ConnectTrans -CoreFrontend_target_pred_resp --> ConnectTrans7_ConnectTrans -ConnectTrans7_ConnectTrans <--> HwCounter8__incr -ConnectTrans7_ConnectTrans <--> HwCounter7__incr -ConnectTrans7_ConnectTrans --> FIFO4_write -ExceptionFuncUnit_accept --> ConnectTrans8_ConnectTrans -FIFO5_read --> ConnectTrans8_ConnectTrans -PrivilegedFuncUnit_accept --> ConnectTrans9_ConnectTrans -CSRRegister8_read --> ConnectTrans9_ConnectTrans -ConnectTrans9_ConnectTrans --> BasicFifo8_write -FifoRS_perf --> HwExpHistogram8__add -Forwarder6_read --> LSUDummy_LSUDummy -Forwarder6_read --> TransactionManager_LSUDummy_issue_cond2 -Forwarder6_read --> TransactionManager_LSUDummy_issue_cond1 -Forwarder6_read --> TransactionManager_issue_cond0_LSUDummy -LSUDummy_LSUDummy --> FIFO6_write -WakeupSelect5_WakeupSelect --> FIFO6_write -TransactionManager_LSUDummy_issue_cond2 --> FIFO6_write -TransactionManager_LSUDummy_issue_cond1 --> FIFO6_write -TransactionManager_issue_cond0_LSUDummy --> FIFO6_write -LSUDummy_LSUDummy --> FIFO8_write -WakeupSelect5_WakeupSelect --> FIFO8_write -TransactionManager_LSUDummy_issue_cond2 --> FIFO8_write -TransactionManager_LSUDummy_issue_cond1 --> FIFO8_write -TransactionManager_issue_cond0_LSUDummy --> FIFO8_write -LSUDummy_LSUDummy1 --> Retirement_precommit +ConnectTrans10_ConnectTrans --> Forwarder5_write +AluFuncUnit_accept --> ConnectTrans6_ConnectTrans +FIFO2_read --> ConnectTrans6_ConnectTrans +ShiftFuncUnit_accept --> ConnectTrans7_ConnectTrans +FIFO3_read --> ConnectTrans7_ConnectTrans +JumpBranchFuncUnit_accept --> ConnectTrans8_ConnectTrans +BasicFifo7_read --> ConnectTrans8_ConnectTrans +CoreFrontend_target_pred_resp --> ConnectTrans8_ConnectTrans +ConnectTrans8_ConnectTrans <--> HwCounter8__incr +ConnectTrans8_ConnectTrans <--> HwCounter7__incr +ConnectTrans8_ConnectTrans --> FIFO4_write +ExceptionFuncUnit_accept --> ConnectTrans9_ConnectTrans +FIFO5_read --> ConnectTrans9_ConnectTrans +PrivilegedFuncUnit_accept --> ConnectTrans10_ConnectTrans +CSRRegister8_read --> ConnectTrans10_ConnectTrans +ConnectTrans10_ConnectTrans --> BasicFifo8_write +RS1_perf --> HwExpHistogram8__add +SequentialUnsignedMul_accept --> MulUnit_MulUnit +FIFO7_read --> MulUnit_MulUnit +MulUnit_MulUnit --> FIFO6_write +RecursiveWithSingleDSPMul_RecursiveWithSingleDSPMul <--> DSPMulUnit_compute +RS1_RS --> WakeupSelect5_WakeupSelect +RS1_take --> WakeupSelect5_WakeupSelect +RS1_take --> WakeupSelect6_WakeupSelect +WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop +WakeupSelect6_WakeupSelect --> TaggedLatencyMeasurer2__stop +AsyncMemoryBank2_read0 --> WakeupSelect5_WakeupSelect +AsyncMemoryBank2_read0 --> WakeupSelect6_WakeupSelect +WakeupSelect5_WakeupSelect --> HwExpHistogram7__add +WakeupSelect6_WakeupSelect --> HwExpHistogram7__add +WakeupSelect5_WakeupSelect --> MulUnit_issue +WakeupSelect5_WakeupSelect --> FIFO7_write +WakeupSelect5_WakeupSelect --> SequentialUnsignedMul_issue +LongDivider_accept --> DivUnit_DivUnit +FIFO8_read --> DivUnit_DivUnit +DivUnit_DivUnit --> BasicFifo9_write +RS1_RS1 --> WakeupSelect6_WakeupSelect +WakeupSelect6_WakeupSelect --> DivUnit_issue +WakeupSelect6_WakeupSelect --> FIFO8_write +WakeupSelect6_WakeupSelect --> LongDivider_issue +ConnectTrans11_ConnectTrans --> Forwarder6_write +ConnectTrans12_ConnectTrans --> Forwarder6_write +MulUnit_accept --> ConnectTrans11_ConnectTrans +FIFO6_read --> ConnectTrans11_ConnectTrans +DivUnit_accept --> ConnectTrans12_ConnectTrans +BasicFifo9_read --> ConnectTrans12_ConnectTrans +FifoRS_perf --> HwExpHistogram10__add +Forwarder7_read --> LSUDummy_LSUDummy1 +Forwarder7_read --> TransactionManager_LSUDummy_issue_cond2 +Forwarder7_read --> TransactionManager_LSUDummy_issue_cond0 +Forwarder7_read --> TransactionManager_LSUDummy_issue_cond1 +LSUDummy_LSUDummy1 --> FIFO9_write +WakeupSelect7_WakeupSelect --> FIFO9_write +TransactionManager_LSUDummy_issue_cond2 --> FIFO9_write +TransactionManager_LSUDummy_issue_cond0 --> FIFO9_write +TransactionManager_LSUDummy_issue_cond1 --> FIFO9_write +LSUDummy_LSUDummy1 --> FIFO11_write +WakeupSelect7_WakeupSelect --> FIFO11_write +TransactionManager_LSUDummy_issue_cond2 --> FIFO11_write +TransactionManager_LSUDummy_issue_cond0 --> FIFO11_write +TransactionManager_LSUDummy_issue_cond1 --> FIFO11_write +LSUDummy_LSUDummy2 --> Retirement_precommit CSRUnit_CSRUnit --> Retirement_precommit TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit --> Retirement_precommit TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit --> Retirement_precommit TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit --> Retirement_precommit TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit --> Retirement_precommit -ReorderBuffer_peek --> LSUDummy_LSUDummy1 +ReorderBuffer_peek --> LSUDummy_LSUDummy2 ReorderBuffer_peek --> CSRUnit_CSRUnit -ReorderBuffer_peek --> Retirement_Retirement2 -ReorderBuffer_peek --> Retirement_Retirement3 +ReorderBuffer_peek --> Retirement_Retirement +ReorderBuffer_peek --> Retirement_Retirement1 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit +ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit -ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit -ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit -FifoRS_FifoRS --> WakeupSelect5_WakeupSelect -FifoRS_take --> WakeupSelect5_WakeupSelect -WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop -AsyncMemoryBank2_read0 --> WakeupSelect5_WakeupSelect -WakeupSelect5_WakeupSelect --> HwExpHistogram7__add -WakeupSelect5_WakeupSelect --> LSUDummy_issue -WakeupSelect5_WakeupSelect --> Forwarder6_write +ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement +FifoRS_FifoRS --> WakeupSelect7_WakeupSelect +FifoRS_take --> WakeupSelect7_WakeupSelect +WakeupSelect7_WakeupSelect --> TaggedLatencyMeasurer3__stop +AsyncMemoryBank3_read0 --> WakeupSelect7_WakeupSelect +WakeupSelect7_WakeupSelect --> HwExpHistogram9__add +WakeupSelect7_WakeupSelect --> LSUDummy_issue +WakeupSelect7_WakeupSelect --> Forwarder7_write MethodMap1_method --> CSRUnit_CSRUnit CSRRegister__internal_fu_read --> CSRUnit_CSRUnit MethodMap3_method --> CSRUnit_CSRUnit @@ -1319,87 +1453,71 @@ ConnectTrans2_ConnectTrans --> Forwarder4_write ConnectTrans3_ConnectTrans --> Forwarder4_write ConnectTrans4_ConnectTrans --> Forwarder4_write +ConnectTrans5_ConnectTrans --> Forwarder4_write RSFuncBlock_get_result --> ConnectTrans2_ConnectTrans Collector1_method --> ConnectTrans2_ConnectTrans Forwarder5_read --> ConnectTrans2_ConnectTrans RSFuncBlock1_get_result --> ConnectTrans3_ConnectTrans Collector2_method --> ConnectTrans3_ConnectTrans -Forwarder7_read --> ConnectTrans3_ConnectTrans -CSRUnit_get_result --> ConnectTrans4_ConnectTrans -ExceptionInformationRegister_get --> Retirement_Retirement2 -ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond1 -ExceptionInformationRegister_get --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement3 <--> ReorderBuffer_retire -TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire -TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire -Retirement_Retirement3 <--> FIFOLatencyMeasurer1__stop -TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop -TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop -FIFO1_read --> Retirement_Retirement3 -FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 -FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement3 --> HwExpHistogram3__add -TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add -TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add -CoreInstructionCounter_decrement --> Retirement_Retirement3 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 -RRAT_peek --> Retirement_Retirement3 -RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement3 --> RegisterFile_free -TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free -TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free -Retirement_Retirement3 --> TaggedLatencyMeasurer__stop -TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop -TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop -AsyncMemoryBank_read0 --> Retirement_Retirement3 -AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond1 -AsyncMemoryBank_read0 --> TransactionManager_Retirement_Retirement_cond0 -Retirement_Retirement3 --> HwExpHistogram1__add -TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add -TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add -Retirement_Retirement3 --> FRAT_rename -TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename +Forwarder6_read --> ConnectTrans3_ConnectTrans +RSFuncBlock2_get_result --> ConnectTrans4_ConnectTrans +Collector3_method --> ConnectTrans4_ConnectTrans +Forwarder8_read --> ConnectTrans4_ConnectTrans +CSRUnit_get_result --> ConnectTrans5_ConnectTrans +ExceptionInformationRegister_get --> Retirement_Retirement +ExceptionInformationRegister_get --> TransactionManager_Retirement_cond1_Retirement +ExceptionInformationRegister_get --> TransactionManager_Retirement_cond0_Retirement +Retirement_Retirement1 <--> ReorderBuffer_retire +TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire +TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire +Retirement_Retirement1 <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer1__stop +FIFO1_read --> Retirement_Retirement1 +FIFO1_read --> TransactionManager_Retirement_cond1_Retirement +FIFO1_read --> TransactionManager_Retirement_cond0_Retirement +Retirement_Retirement1 --> HwExpHistogram3__add +TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram3__add +TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram3__add +CoreInstructionCounter_decrement --> Retirement_Retirement1 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement +CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement +RRAT_peek --> Retirement_Retirement1 +RRAT_peek --> TransactionManager_Retirement_cond1_Retirement +Retirement_Retirement1 --> RegisterFile_free +TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free +TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free +Retirement_Retirement1 --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_cond1_Retirement --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_cond0_Retirement --> TaggedLatencyMeasurer__stop +AsyncMemoryBank_read0 --> Retirement_Retirement1 +AsyncMemoryBank_read0 --> TransactionManager_Retirement_cond1_Retirement +AsyncMemoryBank_read0 --> TransactionManager_Retirement_cond0_Retirement +Retirement_Retirement1 --> HwExpHistogram1__add +TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add +TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add +Retirement_Retirement1 --> FRAT_rename +TransactionManager_Retirement_cond1_Retirement --> FRAT_rename TransactionManager_Renaming_ROBAllocation --> FRAT_rename -Retirement_Retirement1 <--> FIFOLatencyMeasurer2__stop -FIFO12_read --> Retirement_Retirement1 -Retirement_Retirement1 --> HwExpHistogram9__add -CSRRegister7_read --> Retirement_Retirement1 -Retirement_Retirement1 --> FetchUnit_resume_from_exception -Retirement_Retirement1 <--> ExceptionInformationRegister_clear -TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 -FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans -FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans -TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans -TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> ConnectTrans10_ConnectTrans -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans -TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write -TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> Forwarder7_write -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write -LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans -LSUDummy_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans -LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond0 -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> HwCounter5__incr -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter__incr -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Serializer_write -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> Semaphore_release -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release -Pipe_read --> TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 -Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Predecoder_predecode -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> PredictionChecker_check -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter1__incr -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter2__incr -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter3__incr -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 +Retirement_Retirement3 <--> FIFOLatencyMeasurer2__stop +FIFO15_read --> Retirement_Retirement3 +Retirement_Retirement3 --> HwExpHistogram11__add +CSRRegister7_read --> Retirement_Retirement3 +Retirement_Retirement3 --> FetchUnit_resume_from_exception +Retirement_Retirement3 <--> ExceptionInformationRegister_clear +TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy3 +TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy3 +TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy3 +TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond2 --> BasicFifo10_write +TransactionManager_LSUDummy_issue_cond0 --> BasicFifo10_write +TransactionManager_LSUDummy_issue_cond1 --> BasicFifo10_write +TransactionManager_LSUDummy_issue_cond2 --> FIFO10_write +TransactionManager_LSUDummy_issue_cond0 --> FIFO10_write +TransactionManager_LSUDummy_issue_cond1 --> FIFO10_write +TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> ICache_flush TransactionManager_PrivilegedFuncUnit_cond1_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit @@ -1414,87 +1532,107 @@ CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit CSRRegister16_read --> TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement -TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement -TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start -TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start -TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write -TransactionManager_Retirement_Retirement_cond0 --> FIFO12_write -InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 -InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister9_write -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister9_write -TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry -TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 -TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> InternalInterruptController_mret -TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans -Serializer1_serialize_out0 --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSUDummy_accept_cond0 +TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 +LSURequester_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +LSURequester_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +BasicFifo10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +BasicFifo10_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +FIFO10_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +FIFO10_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> ConnectTrans13_ConnectTrans +TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans13_ConnectTrans +TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> ConnectTrans13_ConnectTrans +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 --> Forwarder8_write +TransactionManager_accept_cond1_ConnectTrans --> Forwarder8_write +TransactionManager_accept_cond1_accept_cond0_ConnectTrans --> Forwarder8_write +LSUDummy_accept --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans +LSUDummy_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +TransactionManager_accept_cond0_ConnectTrans_accept_cond0 <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +Serializer1_serialize_out1 --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 +BasicFifo1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 BasicFifo1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans -BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +WishboneMaster1_result --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 WishboneMaster1_result --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans -WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +Forwarder1_read --> TransactionManager_accept_cond0_ConnectTrans_accept_cond0 Forwarder1_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans -Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSUDummy_accept_cond0 -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 -LSURequester_accept --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans -LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -BasicFifo9_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans -BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -FIFO7_read --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans -FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -TransactionManager_LSUDummy_issue_cond2 <--> LSUDummy_LSUDummy3 -TransactionManager_LSUDummy_issue_cond1 <--> LSUDummy_LSUDummy3 -TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy3 -TransactionManager_LSUDummy_issue_cond2 --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond1 --> LSURequester_issue -TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond2 --> BasicFifo9_write -TransactionManager_LSUDummy_issue_cond1 --> BasicFifo9_write -TransactionManager_issue_cond0_LSUDummy --> BasicFifo9_write -TransactionManager_LSUDummy_issue_cond2 --> FIFO7_write -TransactionManager_LSUDummy_issue_cond1 --> FIFO7_write -TransactionManager_issue_cond0_LSUDummy --> FIFO7_write -TransactionManager_LSUDummy_issue_cond2 <--> LSURequester_issue_cond2 -TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit -TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment -CSRRegister23_read --> TransactionManager_Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister23_write -CSRRegister24_read --> TransactionManager_Retirement_Retirement_cond0 -TransactionManager_Retirement_Retirement_cond0 --> CSRRegister24_write -TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr -TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 -TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read -TransactionManager_LSUDummy_issue_cond1 --> Serializer1_serialize_in0 -TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write -TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write -TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request -TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request -TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 -TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write -TransactionManager_issue_cond0_LSUDummy --> Serializer1_serialize_in1 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 +TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement2 +TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement2 +TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer2__start +TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer2__start +TransactionManager_Retirement_cond1_Retirement --> FIFO15_write +TransactionManager_Retirement_cond0_Retirement --> FIFO15_write +InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond1_Retirement +InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond1_Retirement --> CSRRegister6_write +TransactionManager_Retirement_cond0_Retirement --> CSRRegister6_write +TransactionManager_Retirement_cond1_Retirement --> CSRRegister8_write +TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write +TransactionManager_Retirement_cond1_Retirement --> CSRRegister9_write +TransactionManager_Retirement_cond0_Retirement --> CSRRegister9_write +TransactionManager_Retirement_cond1_Retirement <--> InternalInterruptController_entry +TransactionManager_Retirement_cond0_Retirement <--> InternalInterruptController_entry TransactionManager_Renaming_ROBAllocation <--> Renaming_Renaming -FIFO9_read --> TransactionManager_Renaming_ROBAllocation +FIFO12_read --> TransactionManager_Renaming_ROBAllocation TransactionManager_Renaming_ROBAllocation --> Connect_write TransactionManager_Renaming_ROBAllocation <--> ROBAllocation_ROBAllocation Connect_read --> TransactionManager_Renaming_ROBAllocation TransactionManager_Renaming_ROBAllocation --> ReorderBuffer_put TransactionManager_Renaming_ROBAllocation <--> FIFOLatencyMeasurer1__start TransactionManager_Renaming_ROBAllocation --> FIFO1_write -TransactionManager_Renaming_ROBAllocation --> FIFO10_write -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -Serializer1_serialize_out1 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +TransactionManager_Renaming_ROBAllocation --> FIFO13_write +TransactionManager_PrivilegedFuncUnit_cond2_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +TransactionManager_PrivilegedFuncUnit_cond0_PrivilegedFuncUnit <--> InternalInterruptController_mret +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2 +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2 +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> Semaphore_release +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> Semaphore_release +Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 +Pipe_read --> TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Predecoder_predecode +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> Predecoder_predecode +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> PredictionChecker_check +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> PredictionChecker_check +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter1__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter1__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter2__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter2__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter3__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 --> TaggedCounter3__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> FetchUnit_Fetch_Stage2_cond0 +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 <--> HwCounter5__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> TaggedCounter__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond0 --> Serializer_write +TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 +FIFO9_read --> TransactionManager_accept_cond1_ConnectTrans +FIFO11_read --> TransactionManager_accept_cond1_ConnectTrans TransactionManager_PrivilegedFuncUnit_cond3_PrivilegedFuncUnit <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_cond0_Retirement --> RRAT_commit +TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment +CSRRegister23_read --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond0_Retirement --> CSRRegister23_write +CSRRegister24_read --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_cond0_Retirement --> CSRRegister24_write +TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr +TransactionManager_Fetch_Stage2_Fetch_Stage2_cond1 <--> FetchUnit_Fetch_Stage2_cond1 +TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 +TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write +TransactionManager_LSUDummy_issue_cond0 --> Serializer1_serialize_in1 +TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write +TransactionManager_LSUDummy_issue_cond1 --> BasicFifo1_write +TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request +TransactionManager_LSUDummy_issue_cond1 --> WishboneMaster1_request +TransactionManager_accept_cond1_accept_cond0_ConnectTrans <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +Serializer1_serialize_out0 --> TransactionManager_accept_cond1_accept_cond0_ConnectTrans +TransactionManager_LSUDummy_issue_cond1 <--> LSURequester_issue_cond1 +TransactionManager_LSUDummy_issue_cond1 --> WishboneMasterAdapter1_request_read +TransactionManager_LSUDummy_issue_cond1 --> Serializer1_serialize_in0 @@ -1505,7 +1643,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/components/icache.html b/components/icache.html index 69446afc1..12cdb7029 100644 --- a/components/icache.html +++ b/components/icache.html @@ -130,7 +130,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.arch.html b/coreblocks.arch.html index 095899b30..6c705611d 100644 --- a/coreblocks.arch.html +++ b/coreblocks.arch.html @@ -3922,7 +3922,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.backend.html b/coreblocks.backend.html index 49dc411cd..c765cda1c 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -164,7 +164,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index 9e19fd75c..7b57acd45 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -240,7 +240,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index a9cd039d1..2c4a4de34 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -156,7 +156,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index f7ff41c9f..b3227f395 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -312,7 +312,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index 4e4a88415..16beffd53 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -209,7 +209,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 617088b61..1348fa00e 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -186,7 +186,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.func_blocks.fu.fpu.html b/coreblocks.func_blocks.fu.fpu.html index 63b54852d..5a97433c2 100644 --- a/coreblocks.func_blocks.fu.fpu.html +++ b/coreblocks.func_blocks.fu.fpu.html @@ -302,7 +302,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index 5a870be6c..cf9335208 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -893,7 +893,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.func_blocks.fu.lsu.html b/coreblocks.func_blocks.fu.lsu.html index 7e1f90142..361fc09c5 100644 --- a/coreblocks.func_blocks.fu.lsu.html +++ b/coreblocks.func_blocks.fu.lsu.html @@ -289,7 +289,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index 6df061f4a..722ee3243 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -259,7 +259,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index 3e75912ba..22e5805b6 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -157,7 +157,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index 4959c233d..2fa1bbf56 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -163,7 +163,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.html b/coreblocks.html index 220265b8c..9d3aecd10 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -237,6 +237,11 @@

Submodules__init__(*, gen_params: GenParams)
+
+
+interrupts: Signal
+
+
wb_data: WishboneInterface
@@ -267,7 +272,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:48 2024-11-25. + Last updated on 15:14 2024-11-25.

diff --git a/coreblocks.params.html b/coreblocks.params.html index f7fc26867..ed1deecf5 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -831,7 +831,7 @@

Submodules

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diff --git a/coreblocks.priv.html b/coreblocks.priv.html index 478697bc7..9b8afe97f 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -123,7 +123,7 @@

Subpackages

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diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index d1f9ba33e..1568a5295 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -204,7 +204,7 @@

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diff --git a/current-graph.html b/current-graph.html index 4abc7a697..2d61a0b42 100644 --- a/current-graph.html +++ b/current-graph.html @@ -90,17 +90,17 @@

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diff --git a/genindex.html b/genindex.html index b3b1c73a5..59909b863 100644 --- a/genindex.html +++ b/genindex.html @@ -1723,6 +1723,8 @@

I

  • InternalInterruptController (class in coreblocks.priv.traps.interrupt_controller)
  • InterruptCauseNumber (class in coreblocks.arch.isa_consts) +
    • +
  • interrupts (coreblocks.core.Core attribute)
  • INVALID (coreblocks.arch.optypes.CfiType attribute)
    • @@ -3416,7 +3418,7 @@

    Z

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    diff --git a/scheduler/overview.html b/scheduler/overview.html index 72208ab67..eca7f3963 100644 --- a/scheduler/overview.html +++ b/scheduler/overview.html @@ -145,7 +145,7 @@

    More detailed description of each block

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    diff --git a/search.html b/search.html index 7a056ff9f..5151c90a7 100644 --- a/search.html +++ b/search.html @@ -100,7 +100,7 @@

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21, 23, 28, 30], "prefer": [5, 19], "us": [5, 6, 7, 10, 11, 13, 15, 16, 18, 19, 21, 22, 23, 27, 28, 30, 34], "cfi": [5, 11], "static": [5, 18], "is_branch": 5, "amaranth": [5, 7, 9, 10, 11, 13, 18, 19, 21, 30, 34], "hdl": [5, 7, 9, 10, 13, 18, 21], "_ast": [5, 7, 9, 10, 13, 18, 21], "valuecast": [5, 9, 10, 18, 21], "is_jal": 5, "is_jalr": 5, "valid": [5, 13, 19, 23, 32], "do": [5, 10, 28, 30], "confus": 5, "address_gener": 5, "arithmet": [5, 14], "bit_manipul": 5, "bit_rot": 5, "compar": [5, 27], "csr_imm": 5, "csr_reg": 5, "div_rem": 5, "caus": [5, 18, 22, 28], "befor": [5, 15, 19, 22, 25, 30, 31], "execut": [5, 6, 13, 19, 23, 25, 27, 31, 33], "logic": [5, 15, 28, 33, 34], "33": 5, "single_bit_manipul": 5, "unary_bit_manipulation_1": 5, "unary_bit_manipulation_2": 5, "unary_bit_manipulation_3": 5, "unary_bit_manipulation_4": 5, "unary_bit_manipulation_5": 5, "unknown": [5, 25], "resultannounc": 6, "elaborat": [6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 19, 21, 22, 23], "simpl": [6, 7, 10, 15, 21, 23], "It": [6, 10, 11, 13, 15, 16, 18, 19, 21, 23, 25, 28, 31, 32, 34], "take": [6, 10, 14, 19, 31, 32], "its": [6, 10, 18, 21, 23, 28, 34], "mark": [6, 27, 28], "complet": [6, 19, 21, 28], "also": [6, 11, 18, 25, 34], "sent": [6, 19], "get_result": [6, 17], "serial": [6, 11, 15], "so": [6, 18, 19, 28, 34], "we": [6, 7, 19, 28, 31, 32, 33, 34], "more": [6, 21, 25, 27, 28], "than": [6, 28], "connect": [6, 10, 19, 21, 28], "manytooneconnecttran": 6, "fifo": [6, 28], "rob_mark_don": 6, "rs_updat": 6, "rf_write": 6, "instanc": [6, 7, 10, 11, 15, 18, 23, 34], "next": [6, 7, 10, 11, 23, 28], "readi": [6, 7, 19, 21, 23, 27, 32], "assum": [6, 13, 28], "differ": [6, 13, 19, 25, 26, 28, 30, 34], "end": [6, 15, 28], "without": [6, 23, 28], "pass": [6, 25, 34], "finish": [6, 19, 22], "debug_sign": 6, "rob_peek": 6, "rob_retir": 6, "r_rat_commit": 6, "r_rat_peek": 6, "free_rf_put": 6, "rf_free": 6, "exception_cause_get": 6, "exception_cause_clear": 6, "frat_renam": 6, "fetch_continu": 6, "instr_decr": 6, "trap_entri": 6, "async_interrupt_caus": 6, "cacheinterfac": [7, 11], "associ": [7, 18], "replac": [7, 16, 18, 21, 32], "polici": 7, "pseudo": 7, "random": 7, "scheme": 7, "everi": [7, 13, 19, 25, 34], "trash": 7, "select": [7, 10, 13, 17, 19, 23, 25], "keep": 7, "global": [7, 28], "abstract": [7, 16, 18, 34], "awai": 7, "need": [7, 11, 18, 19, 25, 28, 32], "refiller_start": 7, "whenev": [7, 18], "refiller_accept": 7, "written": [7, 21, 33, 34], "last": [7, 22, 23], "when": [7, 15, 18, 19, 22, 25, 28, 30, 32, 33], "either": [7, 18, 19, 22], "transfer": [7, 19], "over": [7, 21], "shouldn": [7, 34], "until": [7, 11, 28], "start": [7, 13, 15, 19, 22, 28], "layout": [7, 10, 11, 14, 19, 23, 25, 30], "icachelayout": 7, "icacheparamet": [7, 18], "cacherefillerinterfac": 7, "creat": [7, 16, 18, 19, 25, 34], "input": [7, 10, 13, 14, 19, 21, 22, 28, 32, 33], "start_refil": 7, "accept_refil": 7, "deserialize_addr": 7, "raw_addr": 7, "dict": [7, 19], "serialize_addr": 7, "addr": [7, 15, 19], "view": [7, 13, 15], "icachebypass": 7, "bus_mast": 7, "busmasterinterfac": [7, 9, 15, 19], "haselabor": [7, 17, 19], "protocol": [7, 17, 19], "whole": [7, 26, 28], "given": [7, 9, 15, 18, 21, 25, 32], "simplecommonbuscacherefil": 7, "frat": 8, "rrat": 8, "registerfil": 8, "reorderbuff": [8, 22], "corefrontend": 9, "consume_instr": 9, "consum": [9, 11], "resume_from_except": 9, "resum": 9, "pc": [9, 27], "resume_from_unsaf": 9, "unsaf": 9, "stall": [9, 19, 28], "instr_bu": 9, "frontendparam": 9, "fb_addr": 9, "fb_instr_idx": 9, "pc_from_fb": 9, "decodestag": 10, "instanti": 10, "instrdecod": 10, "make": [10, 13, 25, 26, 28, 30, 34], "actual": [10, 25, 27], "combinatori": 10, "manner": [10, 19], "get_raw": 10, "push_decod": 10, "raw": 10, "previou": [10, 11, 14, 19, 28], "step": [10, 11, 23, 25, 28, 34], "fetchlayout": [10, 11], "describ": [10, 11, 15, 23, 28, 34], "decodelayout": [10, 23], "elementari": 10, "etc": 10, "via": [10, 22], "signal": [10, 13, 15, 19, 21, 22, 27, 30], "gen": [10, 13, 16], "out": [10, 13, 16, 19, 22, 26, 27], "funct3_v": 10, "seven": 10, "funct7_v": 10, "twelv": 10, "funct12_v": 10, "rd": [10, 18], "reg_cnt_log": 10, "rd_v": 10, "rs1": [10, 18], "hold": [10, 18, 19], "first": [10, 13, 15, 21, 23, 28, 32, 33, 34], "rs1_v": 10, "rs2": [10, 18], "second": [10, 13, 21, 23, 32, 33, 34], "rs2_v": 10, "imm": [10, 18], "immedi": [10, 18, 19], "were": [10, 28], "succ": 10, "successor": 10, "pred": 10, "predecessor": 10, "fm": 10, "sourc": [10, 21, 23, 25, 32], "defin": [10, 15, 21], "kind": [10, 13, 23], "illeg": [10, 18], "success": [10, 19], "fit": 10, "constructor": 10, "repres": [10, 21], "exist": 10, "instr_type_overrid": 10, "specifi": [10, 19, 21, 33], "determin": [10, 11, 28, 34], "instrust": 10, "almost": 10, "correct": [10, 11, 15, 28, 32, 33, 34], "rd_zero": 10, "bool": [10, 15, 18, 21], "constant": 10, "other": [10, 18, 21, 25, 27], "accordingli": 10, "default": [10, 19, 21, 25], "fals": [10, 13, 15, 25], "rs1_zero": 10, "instrdecompress": 10, "decompr_reg": 10, "rvc_reg": 10, "instr_mux": 10, "sel": [10, 19], "list": [10, 13, 18, 19, 25, 27, 30, 34], "tupl": [10, 11, 13, 19, 21, 23], "is_instr_compress": 10, "fetchunit": 11, "superscalar": 11, "respons": [11, 13, 15, 19, 23, 25], "retriev": [11, 15], "them": [11, 25, 28, 34], "work": [11, 23, 28, 30, 34], "chunk": 11, "fetch_block_byt": 11, "relat": [11, 28], "how": [11, 18, 21, 25, 28, 32, 34], "mani": [11, 18, 21, 25, 28, 34], "onc": [11, 34], "vari": 11, "deal": 11, "expand": 11, "manag": [11, 13, 25, 27], "aren": [11, 28], "boundari": [11, 28], "cont": 11, "predecod": 11, "analysi": [11, 27], "jump": [11, 18, 28], "find": [11, 25, 28], "target": [11, 34], "Its": [11, 14, 15, 31], "role": 11, "give": 11, "quick": 11, "feedback": 11, "potenti": [11, 31], "predictor": 11, "help": [11, 25, 28], "redirect": 11, "promptli": 11, "predictioncheck": 11, "predict": 11, "checker": [11, 15], "look": [11, 28], "taken": [11, 21, 23, 34], "mistak": [11, 30], "ones": 11, "wrong": [11, 28], "element": [11, 28], "dispatch": [11, 28, 31, 32, 33], "new": [11, 13, 15, 19, 22, 27, 28], "batch": 11, "onli": [11, 13, 18, 19, 21, 22, 28, 34], "temporari": [11, 21], "workaround": 11, "buffer": [11, 19, 28, 32], "rest": 11, "becom": [11, 19], "elem_layout": 11, "lib": [11, 21], "structlayout": [11, 15], "collect": [11, 26, 34], "abc": [11, 18], "iter": [11, 17, 18], "shapelik": 11, "layoutlist": 11, "fpu": [12, 13], "fpu_common": [12, 13], "fpu_error_modul": [12, 13], "fpu_rounding_modul": [12, 13], "lsu": [12, 13], "dummylsu": [12, 13], "lsu_request": [12, 13], "pma": [12, 13], "unsigned_multipl": [12, 13], "common": [12, 13, 19], "fast_recurs": [12, 13], "sequenc": [12, 13, 23], "alucompon": 13, "functionalcomponentparam": [13, 15, 18], "zba_en": 13, "zbb_enabl": 13, "get_modul": [13, 15, 18], "funcunit": [13, 15, 17, 18], "get_optyp": [13, 15, 18], "alufuncunit": 13, "alu_fn": 13, "alufn": 13, "divcompon": 13, "ipc": [13, 34], "div_fn": 13, "divfn": 13, "decodermanag": 13, "fn": 13, "get_instruct": 13, "implement": [13, 15, 19, 21, 26, 27, 28, 31], "format": [13, 25, 34], "divunit": 13, "get_input": 13, "arg": [13, 19], "exceptionfuncunit": 13, "unit_fn": 13, "exceptionunitfn": 13, "exceptionunitcompon": 13, "jumpbranchfuncunit": 13, "jb_fn": 13, "jumpbranchfn": 13, "jumpcompon": 13, "mulcompon": 13, "mul_unit_typ": 13, "multyp": 13, "dsp_width": [13, 16], "mul_fn": 13, "mulfn": 13, "hot": [13, 28], "wire": 13, "recursive_mul": 13, "fastest": 13, "multipli": [13, 16], "costli": [13, 28], "term": 13, "resourc": [13, 22, 28, 34], "sequence_mul": 13, "dsp": [13, 16], "balanc": 13, "between": [13, 15, 25, 28], "cost": [13, 27], "shift_mul": 13, "cheapest": 13, "russian": [13, 16], "peasant": [13, 16], "algorithm": [13, 16], "mulunit": 13, "unsign": [13, 16], "standard": [13, 22, 28, 34], "funcunitlayout": [13, 23], "comput": [13, 16, 18, 22, 28], "mul_typ": 13, "privilegedfn": 13, "classmethod": 13, "privilegedfuncunit": 13, "privilegedunitcompon": 13, "shiftfuncunit": 13, "shift_unit_fn": 13, "shiftunitfn": 13, "shiftunitcompon": 13, "clmultipli": 13, "product": 13, "i1": [13, 16], "factor": 13, "i2": [13, 16], "reset": [13, 21, 27], "busi": 13, "while": 13, "progress": 13, "bit_width": [13, 21], "recursion_depth": 13, "depth": [13, 15, 19, 34], "recurs": [13, 16, 34], "parallel": 13, "power": 13, "iterative_modul": 13, "recursive_modul": 13, "zbccompon": 13, "zbc_fn": 13, "zbcfn": 13, "zbcunit": 13, "zbsfunction": 13, "in1": 13, "in2": 13, "zbscompon": 13, "zbsunit": 13, "zbs_fn": 13, "division_by_zero": 14, "inexact": 14, "invalid_oper": 14, "overflow": [14, 21], "underflow": 14, "fpuparam": 14, "sig_width": 14, "significand": 14, "includ": [14, 15, 34], "implicit": 14, "exp_width": 14, "expon": 14, "roundingmod": 14, "round_down": 14, "round_nearest_awai": 14, "round_nearest_even": 14, "round_up": 14, "round_zero": 14, "fpuerrormethodlayout": 14, "fpu_param": 14, "input_inf": 14, "flag": 14, "come": 14, "purpos": [14, 28], "indic": [14, 15, 28, 33], "infin": 14, "fpuerrormodul": 14, "round": [14, 19], "error_checking_request": 14, "initi": [14, 19, 27], "error_in_layout": 14, "argument": [14, 19, 23, 25, 33, 34], "final": 14, "error_out_layout": 14, "fpuroudningmethodlayout": 14, "fpuround": 14, "rounding_request": 14, "rounding_in_layout": 14, "rounding_out_layout": 14, "lsucompon": 15, "lsudummi": 15, "veri": [15, 28], "isn": [15, 34], "compliant": [15, 34], "riscv": [15, 18, 34], "spec": [15, 22], "doesn": [15, 28, 30], "rang": 15, "processor": [15, 26, 27, 31], "master": [15, 19, 34], "lsurequest": 15, "job": [15, 28], "resili": 15, "check_align": 15, "tmodul": [15, 19, 21, 22], "postprocess_load_data": 15, "modulelik": 15, "raw_data": 15, "prepare_bytes_mask": 15, "prepare_data_to_sav": 15, "pmacheck": 15, "physic": [15, 23, 28], "mai": [15, 18, 25], "part": [15, 18, 21, 22, 28, 31], "combin": [15, 30], "circuit": [15, 34], "pmalayout": 15, "pmaregion": 15, "contigu": 15, "region": [15, 28], "both": [15, 21, 32], "begin": [15, 28], "mmio": 15, "true": [15, 18, 19, 21], "dspmulunit": 16, "clock": [16, 31, 34], "design": [16, 28], "synthesi": [16, 27], "tool": [16, 25, 34], "o": [16, 28], "same": [16, 18, 21, 25], "mulbaseunsign": 16, "unsignedmulunitlayout": 16, "recursiveunsignedmul": 16, "see": [16, 22, 30, 34], "fast": 16, "within": [16, 25], "pipelinedunsignedmul": 16, "dsp_number": 16, "sequentialunsignedmul": 16, "sequenti": [16, 19], "classic": [16, 28], "shiftunsignedmul": 16, "cheap": 16, "multi": 16, "funcblocksunifi": 17, "blockcomponentparam": [17, 18], "funcblock": [17, 18, 23], "insert": [17, 22, 23, 27, 28, 31, 32], "coreconfigur": 18, "_coreconfigurationdataclass": 18, "kwarg": [18, 19], "self": 18, "get_rs_entry_count": 18, "optypes_support": 18, "dependentcach": 18, "cfg": 18, "addr_width": [18, 19], "word_width": 18, "word": 18, "num_of_wai": 18, "num_of_sets_bit": 18, "log": [18, 19, 28], "line_bytes_log": 18, "disabl": 18, "bypass": 18, "fetch_block_bytes_log": 18, "python": [18, 25], "model": 18, "stefan": 18, "wallentowitz": 18, "http": [18, 34], "github": [18, 26, 34], "com": [18, 34], "wallento": 18, "btypeinstr": 18, "instructionfunct3typ": 18, "posit": [18, 23, 32, 33], "where": [18, 19, 23, 25, 28, 32, 33], "would": [18, 25, 28], "map": [18, 21, 27, 28], "sign": 18, "whether": [18, 34], "skip": 18, "exampl": [18, 21, 25, 27, 32], "signific": 18, "affect": [18, 34], "procedur": [18, 28], "extern": [18, 27, 34], "static_valu": 18, "ebreakinstr": 18, "itypeinstr": 18, "illegalinstr": 18, "riscvinstr": 18, "cat": [18, 34], "const": 18, "d1": 18, "jtypeinstr": 18, "as_valu": 18, "convert": 18, "concret": 18, "usual": [18, 28], "deleg": 18, "must": [18, 19], "idempot": 18, "twice": 18, "exactli": 18, "code": [18, 25, 26, 28, 30, 34], "recogn": 18, "cast": 18, "rais": [18, 28], "convers": 18, "cannot": 18, "done": [18, 28, 34], "propag": 18, "caller": [18, 25], "directli": 18, "recommend": 18, "shape": 18, "itself": [18, 28], "discov": 18, "castabl": 18, "subclass": 18, "richer": 18, "represent": 18, "shapecast": 18, "condit": [18, 25], "rtypeinstr": 18, "instructionfunct7typ": 18, "stypeinstr": 18, "utypeinstr": 18, "axiliteinterfac": 19, "abstractinterfac": 19, "abstractsignatur": 19, "read_address": 19, "axilitereadaddressinterfac": 19, "read_data": 19, "axilitereaddatainterfac": 19, "write_address": 19, "axilitewriteaddressinterfac": 19, "write_data": 19, "axilitewritedatainterfac": 19, "write_respons": 19, "axilitewriteresponseinterfac": 19, "axilitemast": 19, "axi": 19, "lite": 19, "axil_param": 19, "axiliteparamet": 19, "ra_request": 19, "channel": 19, "being": [19, 25], "ra_request_layout": 19, "rd_respons": 19, "availab": 19, "state": [19, 22, 27, 28], "rd_response_layout": 19, "wa_request": 19, "wa_request_layout": 19, "wd_request": 19, "wd_request_layout": 19, "wr_respons": 19, "wr_response_layout": 19, "axil_mast": 19, "result_handl": 19, "start_request_transact": 19, "is_address_channel": 19, "state_machine_request": 19, "request_sign": 19, "data_width": 19, "axilitesignatur": 19, "signatur": 19, "patamet": 19, "axilitemasteradapt": 19, "adapt": 19, "place": [19, 28, 32, 34], "expect": 19, "busparametersinterfac": 19, "method_layout": 19, "commonbusmastermethodlayout": 19, "request_read": 19, "underli": 19, "request_read_layout": 19, "request_writ": 19, "request_write_layout": 19, "get_read_respons": 19, "action": [19, 21], "read_response_layout": 19, "get_write_respons": 19, "write_response_layout": 19, "gain": 19, "simplifi": 19, "interchang": 19, "buse": 19, "receiv": 19, "previous": 19, "wishbonemasteradapt": 19, "wishbonemast": 19, "pipelinedwishbonemast": 19, "wb_param": 19, "wishboneparamet": 19, "max_req": 19, "limit": 19, "pend": [19, 22], "wb": 19, "request_layout": 19, "result_layout": 19, "requests_finish": 19, "generate_method_layout": 19, "wishbonearbit": 19, "arbit": 19, "slave": 19, "assert": 19, "cyc": 19, "grant": 19, "robin": 19, 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"regard": 3, "error": [3, 7, 11, 14, 19], "mean": [3, 23, 25, 33], "dure": [3, 15, 27, 31], "line": [3, 7, 18, 25, 27], "subsequ": 3, "access": [3, 5, 19, 21, 28], "trigger": [3, 21, 22], "which": [3, 6, 7, 10, 11, 13, 15, 19, 23, 25, 26, 28, 31, 32, 33, 34], "most": [3, 22, 28], "like": [3, 10, 18, 28], "For": [3, 5, 9, 18, 25, 32, 33], "32": [3, 5, 13, 16, 19, 28], "128": [3, 5], "set": [3, 7, 10, 13, 15, 18, 21, 22, 23, 27, 32, 34], "size": [3, 11, 18, 19, 28], "equal": [3, 22], "31": [3, 5], "15": [3, 5, 22], "14": [3, 5], "13": [3, 5], "12": [3, 5], "11": [3, 5, 25, 34], "10": [3, 5, 28], "09": 3, "08": 3, "07": 3, "06": 3, "05": 3, "04": 3, "03": 3, "02": 3, "01": 3, "00": 3, "tag": [3, 19, 28, 32, 33], "index": [3, 9], "offset": [3, 18], "decod": [4, 9, 11, 13, 23], "decode_stag": [4, 9], "instr_decod": [4, 9], "instr_descript": [4, 9], "rvc": [4, 9], "alu": [4, 12], "div_unit": [4, 12], "except": [4, 5, 6, 9, 12, 18, 20, 27, 30], "jumpbranch": [4, 12], "mul_unit": [4, 12], "shift_unit": [4, 12], "zbc": [4, 5, 12], "zb": [4, 5, 12], "interfac": [4, 7, 10, 12, 15, 16, 19, 22, 23, 27, 34], "func_blocks_unifi": [4, 12], "func_protocol": [4, 12, 23], "csr": [4, 5, 10, 20, 22], "alias": [4, 20], "csr_instanc": [4, 20], "csr_regist": [4, 20], "trap": [4, 20], "instr_count": [4, 20], "interrupt_control": [4, 20], "class": [4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 25], "base": [4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 25, 28], "compon": [4, 10, 18, 19, 22, 26], "__init__": [4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23], "gen_param": [4, 6, 8, 9, 10, 11, 13, 15, 16, 17, 18, 21, 22, 23], "interrupt": [4, 5, 22, 27], "signal": [4, 10, 13, 15, 19, 21, 22, 27, 30], "wb_data": 4, "wishboneinterfac": [4, 19], "wb_instr": 4, "csraddress": [5, 21], "intenum": [5, 13], "coreblocks_test_csr": 5, "2047": 5, "coreblocks_test_priv_mod": 5, "2303": 5, "3072": 5, "cycleh": 5, "3200": 5, "dcsr": 5, "1968": 5, "dpc": 5, "1969": 5, "dscratch0": 5, "1970": 5, "dscratch1": 5, "1971": 5, "fcsr": 5, "3": [5, 13, 14, 25], "fflag": 5, "1": [5, 10, 13, 14, 16, 18, 21, 22, 23, 28, 32, 33, 34], "frm": 5, "2": [5, 13, 14, 16, 19, 21, 34], "hcontext": 5, "1704": 5, "hcounteren": 5, "1542": 5, "hedeleg": 5, "1538": 5, "hedelegh": 5, "1554": 5, "henvcfg": 5, "1546": 5, "henvcfgh": 5, "1562": 5, "hgatp": 5, "1664": 5, "hgeie": 5, "1543": 5, "hgeip": 5, "3602": 5, "hideleg": 5, "1539": 5, "hie": 5, "1540": 5, "hip": 5, "1604": 5, "hpmcounter10": 5, "3082": 5, "hpmcounter10h": 5, "3210": 5, "hpmcounter11": 5, "3083": 5, "hpmcounter11h": 5, "3211": 5, "hpmcounter12": 5, "3084": 5, "hpmcounter12h": 5, "3212": 5, "hpmcounter13": 5, "3085": 5, "hpmcounter13h": 5, "3213": 5, "hpmcounter14": 5, "3086": 5, "hpmcounter14h": 5, "3214": 5, "hpmcounter15": 5, "3087": 5, "hpmcounter15h": 5, "3215": 5, "hpmcounter16": 5, "3088": 5, "hpmcounter16h": 5, "3216": 5, "hpmcounter17": 5, "3089": 5, "hpmcounter17h": 5, "3217": 5, "hpmcounter18": 5, "3090": 5, "hpmcounter18h": 5, "3218": 5, "hpmcounter19": 5, "3091": 5, "hpmcounter19h": 5, "3219": 5, "hpmcounter20": 5, "3092": 5, "hpmcounter20h": 5, "3220": 5, "hpmcounter21": 5, "3093": 5, "hpmcounter21h": 5, "3221": 5, "hpmcounter22": 5, "3094": 5, "hpmcounter22h": 5, "3222": 5, "hpmcounter23": 5, "3095": 5, "hpmcounter23h": 5, "3223": 5, "hpmcounter24": 5, "3096": 5, "hpmcounter24h": 5, "3224": 5, "hpmcounter25": 5, "3097": 5, "hpmcounter25h": 5, "3225": 5, "hpmcounter26": 5, "3098": 5, "hpmcounter26h": 5, "3226": 5, "hpmcounter27": 5, "3099": 5, "hpmcounter27h": 5, "3227": 5, "hpmcounter28": 5, "3100": 5, "hpmcounter28h": 5, "3228": 5, "hpmcounter29": 5, "3101": 5, "hpmcounter29h": 5, "3229": 5, "hpmcounter3": 5, "3075": 5, "hpmcounter30": 5, "3102": 5, "hpmcounter30h": 5, "3230": 5, "hpmcounter31": 5, "3103": 5, "hpmcounter31h": 5, "3231": 5, "hpmcounter3h": 5, "3203": 5, "hpmcounter4": 5, "3076": 5, "hpmcounter4h": 5, "3204": 5, "hpmcounter5": 5, "3077": 5, "hpmcounter5h": 5, "3205": 5, "hpmcounter6": 5, "3078": 5, "hpmcounter6h": 5, "3206": 5, "hpmcounter7": 5, "3079": 5, "hpmcounter7h": 5, "3207": 5, "hpmcounter8": 5, "3080": 5, "hpmcounter8h": 5, "3208": 5, "hpmcounter9": 5, "3081": 5, "hpmcounter9h": 5, "3209": 5, "hstateen0": 5, "1548": 5, "hstateen0h": 5, "1564": 5, "hstateen1": 5, "1549": 5, "hstateen1h": 5, "1565": 5, "hstateen2": 5, "1550": 5, "hstateen2h": 5, "1566": 5, "hstateen3": 5, "1551": 5, "hstateen3h": 5, "1567": 5, "hstatu": 5, "1536": 5, "htimedelta": 5, "1541": 5, "htimedeltah": 5, "1557": 5, "htinst": 5, "1610": 5, "htval": 5, "1603": 5, "hvip": 5, "1605": 5, "instret": 5, "3074": 5, "instreth": 5, "3202": 5, "marchid": 5, "3858": 5, "mcaus": 5, "834": 5, "mconfigptr": 5, "3861": 5, "mcontext": 5, "1960": 5, "mcounteren": 5, "774": 5, "mcountinhibit": 5, "800": 5, "mcycl": 5, "2816": 5, "mcycleh": 5, "2944": 5, "medeleg": 5, "770": 5, "medelegh": 5, "786": 5, "menvcfg": 5, "778": 5, "menvcfgh": 5, "794": 5, "mepc": 5, "833": 5, "mhartid": 5, "3860": 5, "mhpmcounter10": 5, "2826": 5, "mhpmcounter10h": 5, "2954": 5, "mhpmcounter11": 5, "2827": 5, "mhpmcounter11h": 5, "2955": 5, "mhpmcounter12": 5, "2828": 5, "mhpmcounter12h": 5, "2956": 5, "mhpmcounter13": 5, "2829": 5, "mhpmcounter13h": 5, "2957": 5, "mhpmcounter14": 5, "2830": 5, "mhpmcounter14h": 5, "2958": 5, "mhpmcounter15": 5, "2831": 5, "mhpmcounter15h": 5, "2959": 5, "mhpmcounter16": 5, "2832": 5, "mhpmcounter16h": 5, "2960": 5, "mhpmcounter17": 5, "2833": 5, "mhpmcounter17h": 5, "2961": 5, "mhpmcounter18": 5, "2834": 5, "mhpmcounter18h": 5, "2962": 5, "mhpmcounter19": 5, "2835": 5, "mhpmcounter19h": 5, "2963": 5, "mhpmcounter20": 5, "2836": 5, "mhpmcounter20h": 5, "2964": 5, "mhpmcounter21": 5, "2837": 5, "mhpmcounter21h": 5, "2965": 5, "mhpmcounter22": 5, "2838": 5, "mhpmcounter22h": 5, "2966": 5, "mhpmcounter23": 5, "2839": 5, "mhpmcounter23h": 5, "2967": 5, "mhpmcounter24": 5, "2840": 5, "mhpmcounter24h": 5, "2968": 5, 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5, "812": 5, "mhpmevent12h": 5, "1836": 5, "mhpmevent13": 5, "813": 5, "mhpmevent13h": 5, "1837": 5, "mhpmevent14": 5, "814": 5, "mhpmevent14h": 5, "1838": 5, "mhpmevent15": 5, "815": 5, "mhpmevent15h": 5, "1839": 5, "mhpmevent16": 5, "816": 5, "mhpmevent16h": 5, "1840": 5, "mhpmevent17": 5, "817": 5, "mhpmevent17h": 5, "1841": 5, "mhpmevent18": 5, "818": 5, "mhpmevent18h": 5, "1842": 5, "mhpmevent19": 5, "819": 5, "mhpmevent19h": 5, "1843": 5, "mhpmevent20": 5, "820": 5, "mhpmevent20h": 5, "1844": 5, "mhpmevent21": 5, "821": 5, "mhpmevent21h": 5, "1845": 5, "mhpmevent22": 5, "822": 5, "mhpmevent22h": 5, "1846": 5, "mhpmevent23": 5, "823": 5, "mhpmevent23h": 5, "1847": 5, "mhpmevent24": 5, "824": 5, "mhpmevent24h": 5, "1848": 5, "mhpmevent25": 5, "825": 5, "mhpmevent25h": 5, "1849": 5, "mhpmevent26": 5, "826": 5, "mhpmevent26h": 5, "1850": 5, "mhpmevent27": 5, "827": 5, "mhpmevent27h": 5, "1851": 5, "mhpmevent28": 5, "828": 5, "mhpmevent28h": 5, "1852": 5, "mhpmevent29": 5, "829": 5, "mhpmevent29h": 5, "1853": 5, "mhpmevent3": 5, "803": 5, "mhpmevent30": 5, "830": 5, "mhpmevent30h": 5, "1854": 5, "mhpmevent31": 5, "831": 5, "mhpmevent31h": 5, "1855": 5, "mhpmevent3h": 5, "1827": 5, "mhpmevent4": 5, "804": 5, "mhpmevent4h": 5, "1828": 5, "mhpmevent5": 5, "805": 5, "mhpmevent5h": 5, "1829": 5, "mhpmevent6": 5, "806": 5, "mhpmevent6h": 5, "1830": 5, "mhpmevent7": 5, "807": 5, "mhpmevent7h": 5, "1831": 5, "mhpmevent8": 5, "808": 5, "mhpmevent8h": 5, "1832": 5, "mhpmevent9": 5, "809": 5, "mhpmevent9h": 5, "1833": 5, "mideleg": 5, "771": 5, "mie": 5, "772": 5, "mimpid": 5, "3859": 5, "minstret": 5, "2818": 5, "minstreth": 5, "2946": 5, "mip": [5, 28], "836": 5, "misa": 5, "769": 5, "mncaus": 5, "1858": 5, "mnepc": 5, "1857": 5, "mnscratch": 5, "1856": 5, "mnstatu": 5, "1860": 5, "mscratch": 5, "832": 5, "mseccfg": 5, "1863": 5, "mseccfgh": 5, "1879": 5, "mstateen0": 5, "780": 5, "mstateen0h": 5, "796": 5, "mstateen1": 5, "781": 5, "mstateen1h": 5, "797": 5, "mstateen2": 5, "782": 5, "mstateen2h": 5, "798": 5, "mstateen3": 5, "783": 5, "mstateen3h": 5, "799": 5, "mstatu": 5, "768": 5, "mstatush": 5, "784": 5, "mtinst": 5, "842": 5, "mtval": 5, "835": 5, "mtval2": 5, "843": 5, "mtvec": 5, "773": 5, "mvendorid": 5, "3857": 5, "pmpaddr0": 5, "944": 5, "pmpaddr1": 5, "945": 5, "pmpaddr10": 5, "954": 5, "pmpaddr11": 5, "955": 5, "pmpaddr12": 5, "956": 5, "pmpaddr13": 5, "957": 5, "pmpaddr14": 5, "958": 5, "pmpaddr15": 5, "959": 5, "pmpaddr16": 5, "960": 5, "pmpaddr17": 5, "961": 5, "pmpaddr18": 5, "962": 5, "pmpaddr19": 5, "963": 5, "pmpaddr2": 5, "946": 5, "pmpaddr20": 5, "964": 5, "pmpaddr21": 5, "965": 5, "pmpaddr22": 5, "966": 5, "pmpaddr23": 5, "967": 5, "pmpaddr24": 5, "968": 5, "pmpaddr25": 5, "969": 5, "pmpaddr26": 5, "970": 5, "pmpaddr27": 5, "971": 5, "pmpaddr28": 5, "972": 5, "pmpaddr29": 5, "973": 5, "pmpaddr3": 5, "947": 5, "pmpaddr30": 5, "974": 5, "pmpaddr31": 5, "975": 5, "pmpaddr32": 5, "976": 5, "pmpaddr33": 5, "977": 5, "pmpaddr34": 5, "978": 5, "pmpaddr35": 5, "979": 5, "pmpaddr36": 5, "980": 5, "pmpaddr37": 5, "981": 5, "pmpaddr38": 5, "982": 5, "pmpaddr39": 5, "983": 5, "pmpaddr4": 5, "948": 5, "pmpaddr40": 5, "984": 5, "pmpaddr41": 5, "985": 5, "pmpaddr42": 5, "986": 5, "pmpaddr43": 5, "987": 5, "pmpaddr44": 5, "988": 5, "pmpaddr45": 5, "989": 5, "pmpaddr46": 5, "990": 5, "pmpaddr47": 5, "991": 5, "pmpaddr48": 5, "992": 5, "pmpaddr49": 5, "993": 5, "pmpaddr5": 5, "949": 5, "pmpaddr50": 5, "994": 5, "pmpaddr51": 5, "995": 5, "pmpaddr52": 5, "996": 5, "pmpaddr53": 5, "997": 5, "pmpaddr54": 5, "998": 5, "pmpaddr55": 5, "999": 5, "pmpaddr56": 5, "1000": 5, "pmpaddr57": 5, "1001": 5, "pmpaddr58": 5, "1002": 5, "pmpaddr59": 5, "1003": 5, "pmpaddr6": 5, "950": 5, "pmpaddr60": 5, "1004": 5, "pmpaddr61": 5, "1005": 5, "pmpaddr62": 5, "1006": 5, "pmpaddr63": 5, "1007": 5, "pmpaddr7": 5, "951": 5, "pmpaddr8": 5, "952": 5, "pmpaddr9": 5, "953": 5, "pmpcfg0": 5, "928": 5, "pmpcfg1": 5, "929": 5, "pmpcfg10": 5, "938": 5, "pmpcfg11": 5, "939": 5, "pmpcfg12": 5, "940": 5, "pmpcfg13": 5, "941": 5, "pmpcfg14": 5, "942": 5, "pmpcfg15": 5, "943": 5, "pmpcfg2": 5, "930": 5, "pmpcfg3": 5, "931": 5, "pmpcfg4": 5, "932": 5, "pmpcfg5": 5, "933": 5, "pmpcfg6": 5, "934": 5, "pmpcfg7": 5, "935": 5, "pmpcfg8": 5, "936": 5, "pmpcfg9": 5, "937": 5, "satp": 5, "384": 5, "scaus": 5, "322": 5, "scontext": 5, "1448": 5, "scounteren": 5, "262": 5, "scountinhibit": 5, "288": 5, "scountovf": 5, "3488": 5, "senvcfg": 5, "266": 5, "sepc": 5, "321": 5, "sie": 5, "260": 5, "sip": 5, "324": 5, "sscratch": 5, "320": 5, "ssp": 5, "17": 5, "sstateen0": 5, "268": 5, "sstateen1": 5, "269": 5, "sstateen2": 5, "270": 5, "sstateen3": 5, "271": 5, "sstatu": 5, "256": 5, "stval": 5, "323": 5, "stvec": 5, "261": 5, "tdata1": 5, "1953": 5, "tdata2": 5, "1954": 5, "tdata3": 5, "1955": 5, "time": [5, 7, 11, 19, 28], "3073": 5, "timeh": 5, "3201": 5, "tselect": 5, "1952": 5, "vsatp": 5, "640": 5, "vscaus": 5, "578": 5, "vsepc": 5, "577": 5, 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    Read and clean row

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    diff --git a/shared-structs/rs.html b/shared-structs/rs.html index 640cfe239..9d336b674 100644 --- a/shared-structs/rs.html +++ b/shared-structs/rs.html @@ -221,7 +221,7 @@

    External interface signals

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    Regression tests manual execution

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