diff --git a/coreblocks/func_blocks/fu/common/rs.py b/coreblocks/func_blocks/fu/common/rs.py index 16afaf9c2..f3a6a38cd 100644 --- a/coreblocks/func_blocks/fu/common/rs.py +++ b/coreblocks/func_blocks/fu/common/rs.py @@ -7,8 +7,9 @@ from coreblocks.params import GenParams from coreblocks.arch import OpType from coreblocks.interface.layouts import RSLayouts +from coreblocks.interface.keys import InstructionPrecommitKey from transactron.lib.metrics import HwExpHistogram, TaggedLatencyMeasurer -from transactron.utils import RecordDict +from transactron.utils import DependencyContext, RecordDict from transactron.utils import assign from transactron.utils.assign import AssignType from transactron.utils.amaranth_ext.functions import popcount @@ -44,6 +45,8 @@ def __init__( self.ready_for = [list(op_list) for op_list in ready_for] self.get_ready_list = [Method(o=self.layouts.get_ready_list_out, nonexclusive=True) for _ in self.ready_for] + self.dependency_manager = DependencyContext.get() + self.data = Array(Signal(self.internal_layout) for _ in range(self.rs_entries)) self.data_ready = Signal(self.rs_entries) @@ -67,10 +70,14 @@ def elaborate(self, platform) -> TModule: def _elaborate(self, m: TModule, selected_id: Value, select_possible: Value, take_vector: Value): m.submodules += [self.perf_rs_wait_time, self.perf_num_full] - for i, record in enumerate(self.data): - m.d.comb += self.data_ready[i].eq( - ~record.rs_data.rp_s1.bool() & ~record.rs_data.rp_s2.bool() & record.rec_full.bool() - ) + with Transaction(name="readiness").body(m): + precommit = self.dependency_manager.get_dependency(InstructionPrecommitKey()) + info = precommit(m) + for i, record in enumerate(self.data): + m.d.comb += self.data_ready[i].eq( + (~record.rs_data.rp_s1.bool() & ~record.rs_data.rp_s2.bool() & record.rec_full.bool()) + | ~info.side_fx + ) ready_lists: list[Value] = [] for op_list in self.ready_for: diff --git a/transactron/core/tmodule.py b/transactron/core/tmodule.py index d4276dce7..c870dbfa3 100644 --- a/transactron/core/tmodule.py +++ b/transactron/core/tmodule.py @@ -25,6 +25,10 @@ def __iadd__(self, assigns: StatementLike) -> Self: class _AvoidingModuleBuilderDomains: _m: "TModule" + comb: _AvoidingModuleBuilderDomain + av_comb: _AvoidingModuleBuilderDomain + top_comb: _AvoidingModuleBuilderDomain + sync: _AvoidingModuleBuilderDomain def __init__(self, m: "TModule"): object.__setattr__(self, "_m", m)