diff --git a/coreblocks/fu/__init__.py b/coreblocks/backend/__init__.py similarity index 100% rename from coreblocks/fu/__init__.py rename to coreblocks/backend/__init__.py diff --git a/coreblocks/stages/backend.py b/coreblocks/backend/annoucement.py similarity index 100% rename from coreblocks/stages/backend.py rename to coreblocks/backend/annoucement.py diff --git a/coreblocks/stages/retirement.py b/coreblocks/backend/retirement.py similarity index 97% rename from coreblocks/stages/retirement.py rename to coreblocks/backend/retirement.py index 1225e7e57..cd1ac4696 100644 --- a/coreblocks/stages/retirement.py +++ b/coreblocks/backend/retirement.py @@ -1,5 +1,5 @@ from amaranth import * -from coreblocks.params.layouts import RetirementLayouts +from coreblocks.interface.layouts import RetirementLayouts from transactron.core import Method, Transaction, TModule, def_method from transactron.lib.simultaneous import condition @@ -7,9 +7,9 @@ from transactron.lib.metrics import * from coreblocks.params.genparams import GenParams -from coreblocks.params.isa import ExceptionCause -from coreblocks.params.keys import CoreStateKey, GenericCSRRegistersKey -from coreblocks.structs_common.csr_generic import CSRAddress, DoubleCounterCSR +from coreblocks.frontend.decoder.isa import ExceptionCause +from coreblocks.interface.keys import CoreStateKey, GenericCSRRegistersKey +from coreblocks.priv.csr.csr_instances import CSRAddress, DoubleCounterCSR class Retirement(Elaboratable): diff --git a/coreblocks/cache/icache.py b/coreblocks/cache/icache.py index 09899afb6..f94c6e07c 100644 --- a/coreblocks/cache/icache.py +++ b/coreblocks/cache/icache.py @@ -7,7 +7,8 @@ from transactron.core import def_method, Priority, TModule from transactron import Method, Transaction -from coreblocks.params import ICacheLayouts, ICacheParameters +from coreblocks.params import ICacheParameters +from coreblocks.interface.layouts import ICacheLayouts from transactron.utils import assign, OneHotSwitchDynamic from transactron.lib import * from coreblocks.peripherals.bus_adapter import BusMasterInterface diff --git a/coreblocks/cache/refiller.py b/coreblocks/cache/refiller.py index e8a261e26..311764852 100644 --- a/coreblocks/cache/refiller.py +++ b/coreblocks/cache/refiller.py @@ -1,6 +1,7 @@ from amaranth import * from coreblocks.cache.icache import CacheRefillerInterface -from coreblocks.params import ICacheLayouts, ICacheParameters +from coreblocks.params import ICacheParameters +from coreblocks.interface.layouts import ICacheLayouts from coreblocks.peripherals.bus_adapter import BusMasterInterface from transactron.core import Transaction from transactron.lib import Forwarder, Method, TModule, def_method diff --git a/coreblocks/core.py b/coreblocks/core.py index a91b2e827..145abf653 100644 --- a/coreblocks/core.py +++ b/coreblocks/core.py @@ -2,13 +2,13 @@ from amaranth.lib.wiring import flipped, connect from transactron.utils.dependencies import DependencyManager, DependencyContext -from coreblocks.stages.func_blocks_unifier import FuncBlocksUnifier -from coreblocks.structs_common.instr_counter import CoreInstructionCounter -from coreblocks.structs_common.interrupt_controller import InterruptController +from coreblocks.func_blocks.interface.func_blocks_unifier import FuncBlocksUnifier +from coreblocks.priv.traps.instr_counter import CoreInstructionCounter +from coreblocks.priv.traps.interrupt_controller import InterruptController from transactron.core import Transaction, TModule from transactron.lib import FIFO, ConnectTrans -from coreblocks.params.layouts import * -from coreblocks.params.keys import ( +from coreblocks.interface.layouts import * +from coreblocks.interface.keys import ( BranchVerifyKey, FetchResumeKey, GenericCSRRegistersKey, @@ -16,21 +16,21 @@ CommonBusDataKey, ) from coreblocks.params.genparams import GenParams -from coreblocks.params.isa import Extension -from coreblocks.frontend.decode_stage import DecodeStage -from coreblocks.structs_common.rat import FRAT, RRAT -from coreblocks.structs_common.rob import ReorderBuffer -from coreblocks.structs_common.rf import RegisterFile -from coreblocks.structs_common.csr_generic import GenericCSRRegisters -from coreblocks.structs_common.exception import ExceptionCauseRegister +from coreblocks.params.isa_params import Extension +from coreblocks.frontend.decoder.decode_stage import DecodeStage +from coreblocks.core_structs.rat import FRAT, RRAT +from coreblocks.core_structs.rob import ReorderBuffer +from coreblocks.core_structs.rf import RegisterFile +from coreblocks.priv.csr.csr_instances import GenericCSRRegisters +from coreblocks.priv.traps.exception import ExceptionCauseRegister from coreblocks.scheduler.scheduler import Scheduler -from coreblocks.stages.backend import ResultAnnouncement -from coreblocks.stages.retirement import Retirement +from coreblocks.backend.annoucement import ResultAnnouncement +from coreblocks.backend.retirement import Retirement from coreblocks.cache.icache import ICache, ICacheBypass from coreblocks.peripherals.bus_adapter import WishboneMasterAdapter from coreblocks.peripherals.wishbone import WishboneMaster, WishboneInterface from coreblocks.cache.refiller import SimpleCommonBusCacheRefiller -from coreblocks.frontend.fetch import Fetch, UnalignedFetch +from coreblocks.frontend.fetch.fetch import Fetch, UnalignedFetch from transactron.lib.transformers import MethodMap, MethodProduct from transactron.lib import BasicFifo from transactron.lib.metrics import HwMetricsEnabledKey diff --git a/coreblocks/fu/unsigned_multiplication/__init__.py b/coreblocks/core_structs/__init__.py similarity index 100% rename from coreblocks/fu/unsigned_multiplication/__init__.py rename to coreblocks/core_structs/__init__.py diff --git a/coreblocks/structs_common/rat.py b/coreblocks/core_structs/rat.py similarity index 94% rename from coreblocks/structs_common/rat.py rename to coreblocks/core_structs/rat.py index 9a823688c..10ee248af 100644 --- a/coreblocks/structs_common/rat.py +++ b/coreblocks/core_structs/rat.py @@ -1,6 +1,7 @@ from amaranth import * from transactron import Method, def_method, TModule -from coreblocks.params import RATLayouts, GenParams +from coreblocks.interface.layouts import RATLayouts +from coreblocks.params import GenParams __all__ = ["FRAT", "RRAT"] diff --git a/coreblocks/structs_common/rf.py b/coreblocks/core_structs/rf.py similarity index 96% rename from coreblocks/structs_common/rf.py rename to coreblocks/core_structs/rf.py index 899e99593..f7a9b8a7f 100644 --- a/coreblocks/structs_common/rf.py +++ b/coreblocks/core_structs/rf.py @@ -1,6 +1,7 @@ from amaranth import * from transactron import Method, def_method, TModule -from coreblocks.params import RFLayouts, GenParams +from coreblocks.interface.layouts import RFLayouts +from coreblocks.params import GenParams from transactron.utils.transactron_helpers import make_layout __all__ = ["RegisterFile"] diff --git a/coreblocks/structs_common/rob.py b/coreblocks/core_structs/rob.py similarity index 96% rename from coreblocks/structs_common/rob.py rename to coreblocks/core_structs/rob.py index b2b74f9ae..1f3806d46 100644 --- a/coreblocks/structs_common/rob.py +++ b/coreblocks/core_structs/rob.py @@ -1,7 +1,8 @@ from amaranth import * from transactron import Method, def_method, TModule from transactron.lib.metrics import * -from ..params import GenParams, ROBLayouts +from coreblocks.interface.layouts import ROBLayouts +from coreblocks.params import GenParams __all__ = ["ReorderBuffer"] diff --git a/coreblocks/frontend/decoder/__init__.py b/coreblocks/frontend/decoder/__init__.py new file mode 100644 index 000000000..0a4dc5f63 --- /dev/null +++ b/coreblocks/frontend/decoder/__init__.py @@ -0,0 +1,2 @@ +from .isa import * # noqa: F401 +from .optypes import * # noqa: F401 diff --git a/coreblocks/frontend/decode_stage.py b/coreblocks/frontend/decoder/decode_stage.py similarity index 96% rename from coreblocks/frontend/decode_stage.py rename to coreblocks/frontend/decoder/decode_stage.py index 6ba649db7..77807fb47 100644 --- a/coreblocks/frontend/decode_stage.py +++ b/coreblocks/frontend/decoder/decode_stage.py @@ -1,10 +1,10 @@ from amaranth import * -from coreblocks.params.isa import Funct3 -from coreblocks.params.optypes import OpType +from coreblocks.frontend.decoder.isa import Funct3 +from coreblocks.frontend.decoder.optypes import OpType from transactron.lib.metrics import * from transactron import Method, Transaction, TModule -from ..params import GenParams +from coreblocks.params import GenParams from .instr_decoder import InstrDecoder from coreblocks.params import * diff --git a/coreblocks/frontend/instr_decoder.py b/coreblocks/frontend/decoder/instr_decoder.py similarity index 99% rename from coreblocks/frontend/instr_decoder.py rename to coreblocks/frontend/decoder/instr_decoder.py index fff818b7a..fdb71a4c8 100644 --- a/coreblocks/frontend/instr_decoder.py +++ b/coreblocks/frontend/decoder/instr_decoder.py @@ -4,6 +4,8 @@ from amaranth import * from coreblocks.params import * +from coreblocks.frontend.decoder.optypes import * +from coreblocks.frontend.decoder.isa import * from .instr_description import instructions_by_optype, Encoding __all__ = ["InstrDecoder"] diff --git a/coreblocks/frontend/instr_description.py b/coreblocks/frontend/decoder/instr_description.py similarity index 99% rename from coreblocks/frontend/instr_description.py rename to coreblocks/frontend/decoder/instr_description.py index 632d436cc..d59309aff 100644 --- a/coreblocks/frontend/instr_description.py +++ b/coreblocks/frontend/decoder/instr_description.py @@ -2,6 +2,8 @@ from typing import Optional from coreblocks.params import * +from .isa import * +from .optypes import * @dataclass(frozen=True) diff --git a/coreblocks/frontend/decoder/isa.py b/coreblocks/frontend/decoder/isa.py new file mode 100644 index 000000000..229d65c9b --- /dev/null +++ b/coreblocks/frontend/decoder/isa.py @@ -0,0 +1,154 @@ +from amaranth.lib.enum import unique, Enum, IntEnum, IntFlag + +__all__ = [ + "InstrType", + "Opcode", + "Funct3", + "Funct7", + "Funct12", + "ExceptionCause", + "FenceTarget", + "FenceFm", + "Registers", +] + + +@unique +class InstrType(Enum): + R = 0 + I = 1 # noqa: E741 + S = 2 + B = 3 + U = 4 + J = 5 + + +@unique +class Opcode(IntEnum, shape=5): + LOAD = 0b00000 + LOAD_FP = 0b00001 + MISC_MEM = 0b00011 + OP_IMM = 0b00100 + AUIPC = 0b00101 + OP_IMM_32 = 0b00110 + STORE = 0b01000 + STORE_FP = 0b01001 + OP = 0b01100 + LUI = 0b01101 + OP32 = 0b01110 + BRANCH = 0b11000 + JALR = 0b11001 + JAL = 0b11011 + SYSTEM = 0b11100 + + +class Funct3(IntEnum, shape=3): + JALR = BEQ = B = ADD = SUB = FENCE = PRIV = MUL = MULW = _EINSTRACCESSFAULT = 0b000 + BNE = H = SLL = FENCEI = CSRRW = MULH = BCLR = BINV = BSET = CLZ = CPOP = CTZ = ROL \ + = SEXTB = SEXTH = CLMUL = _EILLEGALINSTR = 0b001 # fmt: skip + W = SLT = CSRRS = MULHSU = SH1ADD = CLMULR = _EBREAKPOINT = 0b010 + D = SLTU = CSRRC = MULHU = CLMULH = _EINSTRPAGEFAULT = 0b011 + BLT = BU = XOR = DIV = DIVW = SH2ADD = MIN = XNOR = ZEXTH = 0b100 + BGE = HU = SR = CSRRWI = DIVU = DIVUW = BEXT = ORCB = REV8 = ROR = MINU = 0b101 + BLTU = OR = CSRRSI = REM = REMW = SH3ADD = MAX = ORN = 0b110 + BGEU = AND = CSRRCI = REMU = REMUW = ANDN = MAXU = 0b111 + + +class Funct7(IntEnum, shape=7): + SL = SLT = ADD = XOR = OR = AND = 0b0000000 + SA = SUB = ANDN = ORN = XNOR = 0b0100000 + MULDIV = 0b0000001 + SH1ADD = SH2ADD = SH3ADD = 0b0010000 + BCLR = BEXT = 0b0100100 + BINV = REV8 = 0b0110100 + BSET = ORCB = 0b0010100 + MAX = MIN = CLMUL = 0b0000101 + ROL = ROR = SEXTB = SEXTH = CPOP = CLZ = CTZ = 0b0110000 + ZEXTH = 0b0000100 + SFENCEVMA = 0b0001001 + + +class Funct12(IntEnum, shape=12): + ECALL = 0b000000000000 + EBREAK = 0b000000000001 + SRET = 0b000100000010 + MRET = 0b001100000010 + WFI = 0b000100000101 + CPOP = 0b011000000010 + CLZ = 0b011000000000 + CTZ = 0b011000000001 + ORCB = 0b001010000111 + REV8_32 = 0b011010011000 + REV8_64 = 0b011010111000 + SEXTB = 0b011000000100 + SEXTH = 0b011000000101 + ZEXTH = 0b000010000000 + + +class Registers(IntEnum, shape=5): + X0 = ZERO = 0b00000 # hardwired zero + X1 = RA = 0b00001 # return address + X2 = SP = 0b00010 # stack pointer + X3 = GP = 0b00011 # global pointer + X4 = TP = 0b00100 # thread pointer + X5 = T0 = 0b00101 # temporary register 0 + X6 = T1 = 0b00110 # temporary register 1 + X7 = T2 = 0b00111 # temporary register 2 + X8 = S0 = FP = 0b01000 # saved register 0 / frame pointer + X9 = S1 = 0b01001 # saved register 1 + X10 = A0 = 0b01010 # function argument 0 / return value 0 + X11 = A1 = 0b01011 # function argument 1 / return value 1 + X12 = A2 = 0b01100 # function argument 2 + X13 = A3 = 0b01101 # function argument 3 + X14 = A4 = 0b01110 # function argument 4 + X15 = A5 = 0b01111 # function argument 5 + X16 = A6 = 0b10000 # function argument 6 + X17 = A7 = 0b10001 # function argument 7 + X18 = S2 = 0b10010 # saved register 2 + X19 = S3 = 0b10011 # saved register 3 + X20 = S4 = 0b10100 # saved register 4 + X21 = S5 = 0b10101 # saved register 5 + X22 = S6 = 0b10110 # saved register 6 + X23 = S7 = 0b10111 # saved register 7 + X24 = S8 = 0b11000 # saved register 8 + X25 = S9 = 0b11001 # saved register 9 + X26 = S10 = 0b11010 # saved register 10 + X27 = S11 = 0b11011 # saved register 11 + X28 = T3 = 0b11100 # temporary register 3 + X29 = T4 = 0b11101 # temporary register 4 + X30 = T5 = 0b11110 # temporary register 5 + X31 = T6 = 0b11111 # temporary register 6 + + +@unique +class FenceTarget(IntFlag, shape=4): + MEM_W = 0b0001 + MEM_R = 0b0010 + DEV_O = 0b0100 + DEV_I = 0b1000 + + +@unique +class FenceFm(IntEnum, shape=4): + NONE = 0b0000 + TSO = 0b1000 + + +@unique +class ExceptionCause(IntEnum, shape=5): + INSTRUCTION_ADDRESS_MISALIGNED = 0 + INSTRUCTION_ACCESS_FAULT = 1 + ILLEGAL_INSTRUCTION = 2 + BREAKPOINT = 3 + LOAD_ADDRESS_MISALIGNED = 4 + LOAD_ACCESS_FAULT = 5 + STORE_ADDRESS_MISALIGNED = 6 + STORE_ACCESS_FAULT = 7 + ENVIRONMENT_CALL_FROM_U = 8 + ENVIRONMENT_CALL_FROM_S = 9 + ENVIRONMENT_CALL_FROM_M = 11 + INSTRUCTION_PAGE_FAULT = 12 + LOAD_PAGE_FAULT = 13 + STORE_PAGE_FAULT = 15 + _COREBLOCKS_ASYNC_INTERRUPT = 16 + _COREBLOCKS_MISPREDICTION = 17 diff --git a/coreblocks/params/optypes.py b/coreblocks/frontend/decoder/optypes.py similarity index 97% rename from coreblocks/params/optypes.py rename to coreblocks/frontend/decoder/optypes.py index 60fd52c19..fe60c62e2 100644 --- a/coreblocks/params/optypes.py +++ b/coreblocks/frontend/decoder/optypes.py @@ -1,7 +1,7 @@ from enum import IntEnum, auto, unique from coreblocks.params import Extension -from coreblocks.params.isa import extension_implications, extension_only_implies +from coreblocks.params.isa_params import extension_implications, extension_only_implies @unique diff --git a/coreblocks/frontend/rvc.py b/coreblocks/frontend/decoder/rvc.py similarity index 99% rename from coreblocks/frontend/rvc.py rename to coreblocks/frontend/decoder/rvc.py index bd01255fd..4ff48c07d 100644 --- a/coreblocks/frontend/rvc.py +++ b/coreblocks/frontend/decoder/rvc.py @@ -2,6 +2,7 @@ from transactron import TModule from coreblocks.params import * +from coreblocks.frontend.decoder.isa import * from transactron.utils import ValueLike diff --git a/coreblocks/lsu/__init__.py b/coreblocks/frontend/fetch/__init__.py similarity index 100% rename from coreblocks/lsu/__init__.py rename to coreblocks/frontend/fetch/__init__.py diff --git a/coreblocks/frontend/fetch.py b/coreblocks/frontend/fetch/fetch.py similarity index 97% rename from coreblocks/frontend/fetch.py rename to coreblocks/frontend/fetch/fetch.py index 33a1a2129..add09c6c1 100644 --- a/coreblocks/frontend/fetch.py +++ b/coreblocks/frontend/fetch/fetch.py @@ -3,9 +3,11 @@ from transactron.lib import BasicFifo, Semaphore from transactron.lib.metrics import * from coreblocks.cache.iface import CacheInterface -from coreblocks.frontend.rvc import InstrDecompress, is_instr_compressed +from coreblocks.frontend.decoder.rvc import InstrDecompress, is_instr_compressed from transactron import def_method, Method, Transaction, TModule -from ..params import * +from coreblocks.params import * +from coreblocks.interface.layouts import * +from coreblocks.frontend.decoder.isa import * class Fetch(Elaboratable): diff --git a/coreblocks/stages/__init__.py b/coreblocks/func_blocks/__init__.py similarity index 100% rename from coreblocks/stages/__init__.py rename to coreblocks/func_blocks/__init__.py diff --git a/coreblocks/structs_common/csr.py b/coreblocks/func_blocks/csr/csr.py similarity index 64% rename from coreblocks/structs_common/csr.py rename to coreblocks/func_blocks/csr/csr.py index a01a028fa..43ddfe957 100644 --- a/coreblocks/structs_common/csr.py +++ b/coreblocks/func_blocks/csr/csr.py @@ -1,163 +1,21 @@ from amaranth import * from amaranth.lib.data import StructLayout -from amaranth.lib.enum import IntEnum -from dataclasses import dataclass from transactron import Method, def_method, Transaction, TModule -from transactron.utils import assign, bits_from_int +from transactron.utils import assign from coreblocks.params.genparams import GenParams -from transactron.utils.dependencies import DependencyManager, ListKey +from transactron.utils.dependencies import DependencyManager from coreblocks.params.fu_params import BlockComponentParams -from coreblocks.params.layouts import FetchLayouts, FuncUnitLayouts, CSRLayouts -from coreblocks.params.isa import Funct3, ExceptionCause -from coreblocks.params.keys import ( - AsyncInterruptInsertSignalKey, +from coreblocks.interface.layouts import FetchLayouts, FuncUnitLayouts, CSRLayouts +from coreblocks.frontend.decoder import Funct3, ExceptionCause, OpType +from coreblocks.func_blocks.interface.func_protocols import FuncBlock +from coreblocks.priv.csr.csr_register import * +from coreblocks.interface.keys import ( FetchResumeKey, - ExceptionReportKey, InstructionPrecommitKey, + ExceptionReportKey, + AsyncInterruptInsertSignalKey, ) -from coreblocks.params.optypes import OpType -from coreblocks.utils.protocols import FuncBlock -from transactron.utils.transactron_helpers import from_method_layout - - -class PrivilegeLevel(IntEnum, shape=2): - USER = 0b00 - SUPERVISOR = 0b01 - MACHINE = 0b11 - - -def csr_access_privilege(csr_addr: int) -> tuple[PrivilegeLevel, bool]: - read_only = bits_from_int(csr_addr, 10, 2) == 0b11 - - match bits_from_int(csr_addr, 8, 2): - case 0b00: - return (PrivilegeLevel.USER, read_only) - case 0b01: - return (PrivilegeLevel.SUPERVISOR, read_only) - case 0b10: # Hypervisior CSRs - accessible with VS mode (S with extension) - return (PrivilegeLevel.SUPERVISOR, read_only) - case _: - return (PrivilegeLevel.MACHINE, read_only) - - -@dataclass(frozen=True) -class CSRListKey(ListKey["CSRRegister"]): - """DependencyManager key collecting CSR registers globally as a list.""" - - # This key is defined here, because it is only used internally by CSRRegister and CSRUnit - pass - - -class CSRRegister(Elaboratable): - """CSR Register - Used to define a CSR register and specify its behaviour. - `CSRRegisters` are automatically assigned to `CSRListKey` dependency key, to be accessed from `CSRUnits`. - - Attributes - ---------- - read: Method - Reads register value and side effect status. - Side effect fields `read` and `written` are set if register was accessed by _fu_read or _fu_write - methods (by CSR instruction) in a current cycle; they can be used to trigger other actions. - Always ready. - write: Method - Updates register value. - Always ready. If _fu_write is called simultaneously, this call is ignored. - _fu_read: Method - Method connected automatically by `CSRUnit`. Reads register value. - _fu_write: Method - Method connected automatically by `CSRUnit`. Updates register value. - Always ready. Has priority over `write` method. - - Examples - -------- - .. highlight:: python - .. code-block:: python - - # Timer register that increments on each cycle and resets if read by CSR instruction - csr = CSRRegister(1, gen_params) - with Transaction.body(m): - csr_val = csr.read() - with m.If(csr_val.read): - csr.write(0) - with m.Else(): - csr.write(csr_val.data + 1) - """ - - def __init__(self, csr_number: int, gen_params: GenParams, *, ro_bits: int = 0): - """ - Parameters - ---------- - csr_number: int - Address of this CSR Register. - gen_params: GenParams - Core generation parameters. - ro_bits: int - Bit mask of read-only bits in register. - Writes from _fu_write (instructions) to those bits are ignored. - Note that this parameter is only required if there are some read-only - bits in read-write register. Writes to read-only registers specified - by upper 2 bits of CSR address set to `0b11` are discarded by `CSRUnit`. - """ - self.gen_params = gen_params - self.csr_number = csr_number - self.ro_bits = ro_bits - - csr_layouts = gen_params.get(CSRLayouts) - - self.read = Method(o=csr_layouts.read) - self.write = Method(i=csr_layouts.write) - - # Methods connected automatically by CSRUnit - self._fu_read = Method(o=csr_layouts._fu_read) - self._fu_write = Method(i=csr_layouts._fu_write) - - self.value = Signal(gen_params.isa.xlen) - self.side_effects = Signal(StructLayout({"read": 1, "write": 1})) - - # append to global CSR list - dm = gen_params.get(DependencyManager) - dm.add_dependency(CSRListKey(), self) - - def elaborate(self, platform): - m = TModule() - - internal_method_layout = from_method_layout([("data", self.gen_params.isa.xlen), ("active", 1)]) - write_internal = Signal(internal_method_layout) - fu_write_internal = Signal(internal_method_layout) - - m.d.sync += self.side_effects.eq(0) - - @def_method(m, self.write) - def _(data): - m.d.comb += write_internal.data.eq(data) - m.d.comb += write_internal.active.eq(1) - - @def_method(m, self._fu_write) - def _(data): - m.d.comb += fu_write_internal.data.eq(data) - m.d.comb += fu_write_internal.active.eq(1) - m.d.sync += self.side_effects.write.eq(1) - - @def_method(m, self.read) - def _(): - return {"data": self.value, "read": self.side_effects.read, "written": self.side_effects.write} - - @def_method(m, self._fu_read) - def _(): - m.d.sync += self.side_effects.read.eq(1) - return self.value - - # Writes from instructions have priority - with m.If(fu_write_internal.active & write_internal.active): - m.d.sync += self.value.eq((fu_write_internal.data & ~self.ro_bits) | (write_internal.data & self.ro_bits)) - with m.Elif(fu_write_internal.active): - m.d.sync += self.value.eq((fu_write_internal.data & ~self.ro_bits) | (self.value & self.ro_bits)) - with m.Elif(write_internal.active): - m.d.sync += self.value.eq(write_internal.data) - - return m class CSRUnit(FuncBlock, Elaboratable): diff --git a/coreblocks/structs_common/__init__.py b/coreblocks/func_blocks/fu/__init__.py similarity index 100% rename from coreblocks/structs_common/__init__.py rename to coreblocks/func_blocks/fu/__init__.py diff --git a/coreblocks/fu/alu.py b/coreblocks/func_blocks/fu/alu.py similarity index 96% rename from coreblocks/fu/alu.py rename to coreblocks/func_blocks/fu/alu.py index 114e367ce..adfcc6a3f 100644 --- a/coreblocks/fu/alu.py +++ b/coreblocks/func_blocks/fu/alu.py @@ -4,13 +4,16 @@ from transactron import * from transactron.lib import FIFO -from coreblocks.params import OpType, Funct3, Funct7, GenParams, FuncUnitLayouts, FunctionalComponentParams +from coreblocks.frontend.decoder.isa import Funct3, Funct7 +from coreblocks.frontend.decoder.optypes import OpType +from coreblocks.interface.layouts import FuncUnitLayouts +from coreblocks.params import GenParams, FunctionalComponentParams from transactron.utils import HasElaborate, OneHotSwitch -from coreblocks.fu.fu_decoder import DecoderManager +from coreblocks.func_blocks.fu.common.fu_decoder import DecoderManager from enum import IntFlag, auto -from coreblocks.utils.protocols import FuncUnit +from coreblocks.func_blocks.interface.func_protocols import FuncUnit from transactron.utils import popcount, count_leading_zeros diff --git a/coreblocks/fu/fu_decoder.py b/coreblocks/func_blocks/fu/common/fu_decoder.py similarity index 94% rename from coreblocks/fu/fu_decoder.py rename to coreblocks/func_blocks/fu/common/fu_decoder.py index eeaae8bf1..2324b9f24 100644 --- a/coreblocks/fu/fu_decoder.py +++ b/coreblocks/func_blocks/fu/common/fu_decoder.py @@ -1,11 +1,12 @@ from typing import Sequence, Type from amaranth import * -from coreblocks.params import GenParams, CommonLayoutFields +from coreblocks.params import GenParams +from coreblocks.interface.layouts import CommonLayoutFields from enum import IntFlag -from coreblocks.params.optypes import OpType +from coreblocks.frontend.decoder.optypes import OpType class Decoder(Elaboratable): diff --git a/coreblocks/structs_common/rs.py b/coreblocks/func_blocks/fu/common/rs.py similarity index 96% rename from coreblocks/structs_common/rs.py rename to coreblocks/func_blocks/fu/common/rs.py index 6af0b5e2a..56287df27 100644 --- a/coreblocks/structs_common/rs.py +++ b/coreblocks/func_blocks/fu/common/rs.py @@ -3,7 +3,9 @@ from amaranth import * from amaranth.lib.coding import PriorityEncoder from transactron import Method, def_method, TModule -from coreblocks.params import RSLayouts, GenParams, OpType +from coreblocks.params import GenParams +from coreblocks.frontend.decoder import OpType +from coreblocks.interface.layouts import RSLayouts from transactron.utils import RecordDict from transactron.utils.transactron_helpers import make_layout diff --git a/coreblocks/stages/rs_func_block.py b/coreblocks/func_blocks/fu/common/rs_func_block.py similarity index 94% rename from coreblocks/stages/rs_func_block.py rename to coreblocks/func_blocks/fu/common/rs_func_block.py index 9b3a45c4b..66fed3d0e 100644 --- a/coreblocks/stages/rs_func_block.py +++ b/coreblocks/func_blocks/fu/common/rs_func_block.py @@ -2,11 +2,13 @@ from amaranth import * from dataclasses import dataclass from coreblocks.params import * -from coreblocks.structs_common.rs import RS +from .rs import RS from coreblocks.scheduler.wakeup_select import WakeupSelect from transactron import Method, TModule -from coreblocks.utils.protocols import FuncUnit, FuncBlock +from coreblocks.func_blocks.interface.func_protocols import FuncUnit, FuncBlock from transactron.lib import Collector +from coreblocks.frontend.decoder import OpType +from coreblocks.interface.layouts import RSLayouts, FuncUnitLayouts __all__ = ["RSFuncBlock", "RSBlockComponent"] diff --git a/coreblocks/fu/div_unit.py b/coreblocks/func_blocks/fu/div_unit.py similarity index 93% rename from coreblocks/fu/div_unit.py rename to coreblocks/func_blocks/fu/div_unit.py index 9e3f3dfc6..bc4938624 100644 --- a/coreblocks/fu/div_unit.py +++ b/coreblocks/func_blocks/fu/div_unit.py @@ -6,16 +6,18 @@ from amaranth.lib import data from coreblocks.params.fu_params import FunctionalComponentParams -from coreblocks.params import Funct3, GenParams, FuncUnitLayouts, OpType +from coreblocks.params import GenParams +from coreblocks.frontend.decoder import Funct3, OpType +from coreblocks.interface.layouts import FuncUnitLayouts from transactron import * from transactron.core import def_method from transactron.lib import * -from coreblocks.fu.fu_decoder import DecoderManager +from coreblocks.func_blocks.fu.common.fu_decoder import DecoderManager from transactron.utils import OneHotSwitch -from coreblocks.utils.protocols import FuncUnit -from coreblocks.fu.division.long_division import LongDivider +from coreblocks.func_blocks.interface.func_protocols import FuncUnit +from coreblocks.func_blocks.fu.division.long_division import LongDivider class DivFn(DecoderManager): diff --git a/coreblocks/fu/division/common.py b/coreblocks/func_blocks/fu/division/common.py similarity index 87% rename from coreblocks/fu/division/common.py rename to coreblocks/func_blocks/fu/division/common.py index a48175086..c253090f1 100644 --- a/coreblocks/fu/division/common.py +++ b/coreblocks/func_blocks/fu/division/common.py @@ -1,6 +1,6 @@ from amaranth import * from coreblocks.params import GenParams -from coreblocks.params.layouts import DivUnitLayouts +from coreblocks.interface.layouts import DivUnitLayouts from transactron.core import Method diff --git a/coreblocks/fu/division/long_division.py b/coreblocks/func_blocks/fu/division/long_division.py similarity index 99% rename from coreblocks/fu/division/long_division.py rename to coreblocks/func_blocks/fu/division/long_division.py index c74958340..efa140430 100644 --- a/coreblocks/fu/division/long_division.py +++ b/coreblocks/func_blocks/fu/division/long_division.py @@ -3,7 +3,7 @@ from coreblocks.params import GenParams from transactron import * from transactron.core import def_method -from coreblocks.fu.division.common import DividerBase +from coreblocks.func_blocks.fu.division.common import DividerBase """ Algorithm - multi-cycle array divider diff --git a/coreblocks/fu/exception.py b/coreblocks/func_blocks/fu/exception.py similarity index 90% rename from coreblocks/fu/exception.py rename to coreblocks/func_blocks/fu/exception.py index 2927c0399..a944276fd 100644 --- a/coreblocks/fu/exception.py +++ b/coreblocks/func_blocks/fu/exception.py @@ -1,19 +1,20 @@ from typing import Sequence from amaranth import * from transactron.utils.dependencies import DependencyManager -from coreblocks.params.isa import Funct3, ExceptionCause from transactron import * from transactron.lib import FIFO -from coreblocks.params import OpType, GenParams, FuncUnitLayouts, FunctionalComponentParams +from coreblocks.params import GenParams, FunctionalComponentParams +from coreblocks.frontend.decoder import Funct3, OpType, ExceptionCause +from coreblocks.interface.layouts import FuncUnitLayouts from transactron.utils import OneHotSwitch -from coreblocks.params.keys import ExceptionReportKey +from coreblocks.interface.keys import ExceptionReportKey -from coreblocks.fu.fu_decoder import DecoderManager +from coreblocks.func_blocks.fu.common.fu_decoder import DecoderManager from enum import IntFlag, auto -from coreblocks.utils.protocols import FuncUnit +from coreblocks.func_blocks.interface.func_protocols import FuncUnit __all__ = ["ExceptionFuncUnit", "ExceptionUnitComponent"] diff --git a/coreblocks/fu/jumpbranch.py b/coreblocks/func_blocks/fu/jumpbranch.py similarity index 95% rename from coreblocks/fu/jumpbranch.py rename to coreblocks/func_blocks/fu/jumpbranch.py index 8b4ba52c9..aeb6fed22 100644 --- a/coreblocks/fu/jumpbranch.py +++ b/coreblocks/func_blocks/fu/jumpbranch.py @@ -9,12 +9,13 @@ from transactron.lib import * from transactron.lib import logging from transactron.utils import DependencyManager -from coreblocks.params import * -from coreblocks.params.keys import AsyncInterruptInsertSignalKey, BranchVerifyKey +from coreblocks.params import GenParams, FunctionalComponentParams, Extension +from coreblocks.frontend.decoder import Funct3, OpType, ExceptionCause +from coreblocks.interface.layouts import FuncUnitLayouts, JumpBranchLayouts +from coreblocks.interface.keys import AsyncInterruptInsertSignalKey, BranchVerifyKey, ExceptionReportKey from transactron.utils import OneHotSwitch -from coreblocks.utils.protocols import FuncUnit - -from coreblocks.fu.fu_decoder import DecoderManager +from coreblocks.func_blocks.interface.func_protocols import FuncUnit +from coreblocks.func_blocks.fu.common.fu_decoder import DecoderManager __all__ = ["JumpBranchFuncUnit", "JumpComponent"] diff --git a/coreblocks/fu/mul_unit.py b/coreblocks/func_blocks/fu/mul_unit.py similarity index 93% rename from coreblocks/fu/mul_unit.py rename to coreblocks/func_blocks/fu/mul_unit.py index 0deba543a..60b0b53a6 100644 --- a/coreblocks/fu/mul_unit.py +++ b/coreblocks/func_blocks/fu/mul_unit.py @@ -4,22 +4,23 @@ from amaranth import * -from coreblocks.fu.unsigned_multiplication.fast_recursive import RecursiveUnsignedMul -from coreblocks.fu.unsigned_multiplication.sequence import SequentialUnsignedMul -from coreblocks.fu.unsigned_multiplication.shift import ShiftUnsignedMul -from coreblocks.params.fu_params import FunctionalComponentParams -from coreblocks.params import Funct3, GenParams, FuncUnitLayouts, OpType +from coreblocks.func_blocks.fu.unsigned_multiplication.fast_recursive import RecursiveUnsignedMul +from coreblocks.func_blocks.fu.unsigned_multiplication.sequence import SequentialUnsignedMul +from coreblocks.func_blocks.fu.unsigned_multiplication.shift import ShiftUnsignedMul +from coreblocks.params import GenParams, FunctionalComponentParams +from coreblocks.frontend.decoder import Funct3, OpType +from coreblocks.interface.layouts import FuncUnitLayouts from transactron import * from transactron.core import def_method from transactron.lib import * -from coreblocks.fu.fu_decoder import DecoderManager +from coreblocks.func_blocks.fu.common.fu_decoder import DecoderManager __all__ = ["MulUnit", "MulFn", "MulComponent", "MulType"] from transactron.utils import OneHotSwitch -from coreblocks.utils.protocols import FuncUnit +from coreblocks.func_blocks.interface.func_protocols import FuncUnit class MulFn(DecoderManager): diff --git a/coreblocks/fu/priv.py b/coreblocks/func_blocks/fu/priv.py similarity index 86% rename from coreblocks/fu/priv.py rename to coreblocks/func_blocks/fu/priv.py index 1e7d599d5..d153df540 100644 --- a/coreblocks/fu/priv.py +++ b/coreblocks/func_blocks/fu/priv.py @@ -1,6 +1,6 @@ from amaranth import * -from enum import IntFlag, auto +from enum import IntFlag, auto, unique from typing import Sequence @@ -9,10 +9,20 @@ from transactron.utils import DependencyManager from coreblocks.params import * -from coreblocks.params.keys import MretKey -from coreblocks.utils.protocols import FuncUnit - -from coreblocks.fu.fu_decoder import DecoderManager +from coreblocks.params import GenParams, FunctionalComponentParams +from coreblocks.frontend.decoder import OpType, ExceptionCause +from coreblocks.interface.layouts import FuncUnitLayouts, RetirementLayouts, FetchLayouts +from coreblocks.interface.keys import ( + MretKey, + AsyncInterruptInsertSignalKey, + ExceptionReportKey, + GenericCSRRegistersKey, + InstructionPrecommitKey, + FetchResumeKey, +) +from coreblocks.func_blocks.interface.func_protocols import FuncUnit + +from coreblocks.func_blocks.fu.common.fu_decoder import DecoderManager class PrivilegedFn(DecoderManager): diff --git a/coreblocks/fu/shift_unit.py b/coreblocks/func_blocks/fu/shift_unit.py similarity index 92% rename from coreblocks/fu/shift_unit.py rename to coreblocks/func_blocks/fu/shift_unit.py index 0df08b73c..1c27c78a3 100644 --- a/coreblocks/fu/shift_unit.py +++ b/coreblocks/func_blocks/fu/shift_unit.py @@ -4,13 +4,15 @@ from transactron import * from transactron.lib import FIFO -from coreblocks.params import OpType, Funct3, Funct7, GenParams, FuncUnitLayouts, FunctionalComponentParams +from coreblocks.params import GenParams, FunctionalComponentParams +from coreblocks.frontend.decoder import Funct3, OpType, Funct7 +from coreblocks.interface.layouts import FuncUnitLayouts from transactron.utils import OneHotSwitch -from coreblocks.fu.fu_decoder import DecoderManager +from coreblocks.func_blocks.fu.common.fu_decoder import DecoderManager from enum import IntFlag, auto -from coreblocks.utils.protocols import FuncUnit +from coreblocks.func_blocks.interface.func_protocols import FuncUnit __all__ = ["ShiftFuncUnit", "ShiftUnitComponent"] diff --git a/coreblocks/utils/__init__.py b/coreblocks/func_blocks/fu/unsigned_multiplication/__init__.py similarity index 100% rename from coreblocks/utils/__init__.py rename to coreblocks/func_blocks/fu/unsigned_multiplication/__init__.py diff --git a/coreblocks/fu/unsigned_multiplication/common.py b/coreblocks/func_blocks/fu/unsigned_multiplication/common.py similarity index 94% rename from coreblocks/fu/unsigned_multiplication/common.py rename to coreblocks/func_blocks/fu/unsigned_multiplication/common.py index aa9d11924..28c2cf977 100644 --- a/coreblocks/fu/unsigned_multiplication/common.py +++ b/coreblocks/func_blocks/fu/unsigned_multiplication/common.py @@ -1,6 +1,7 @@ from amaranth import * -from coreblocks.params import GenParams, UnsignedMulUnitLayouts +from coreblocks.params import GenParams +from coreblocks.interface.layouts import UnsignedMulUnitLayouts from transactron import * from transactron.core import def_method diff --git a/coreblocks/fu/unsigned_multiplication/fast_recursive.py b/coreblocks/func_blocks/fu/unsigned_multiplication/fast_recursive.py similarity index 97% rename from coreblocks/fu/unsigned_multiplication/fast_recursive.py rename to coreblocks/func_blocks/fu/unsigned_multiplication/fast_recursive.py index b5b189b91..fdb294907 100644 --- a/coreblocks/fu/unsigned_multiplication/fast_recursive.py +++ b/coreblocks/func_blocks/fu/unsigned_multiplication/fast_recursive.py @@ -1,6 +1,6 @@ from amaranth import * -from coreblocks.fu.unsigned_multiplication.common import MulBaseUnsigned, DSPMulUnit +from coreblocks.func_blocks.fu.unsigned_multiplication.common import MulBaseUnsigned, DSPMulUnit from coreblocks.params import GenParams from transactron import * from transactron.core import def_method diff --git a/coreblocks/fu/unsigned_multiplication/sequence.py b/coreblocks/func_blocks/fu/unsigned_multiplication/sequence.py similarity index 98% rename from coreblocks/fu/unsigned_multiplication/sequence.py rename to coreblocks/func_blocks/fu/unsigned_multiplication/sequence.py index 549c125e0..41733027b 100644 --- a/coreblocks/fu/unsigned_multiplication/sequence.py +++ b/coreblocks/func_blocks/fu/unsigned_multiplication/sequence.py @@ -1,6 +1,6 @@ from amaranth import * -from coreblocks.fu.unsigned_multiplication.common import DSPMulUnit, MulBaseUnsigned +from coreblocks.func_blocks.fu.unsigned_multiplication.common import DSPMulUnit, MulBaseUnsigned from coreblocks.params import GenParams from transactron import * from transactron.core import def_method diff --git a/coreblocks/fu/unsigned_multiplication/shift.py b/coreblocks/func_blocks/fu/unsigned_multiplication/shift.py similarity index 93% rename from coreblocks/fu/unsigned_multiplication/shift.py rename to coreblocks/func_blocks/fu/unsigned_multiplication/shift.py index 9bdd8c336..77dbb19b2 100644 --- a/coreblocks/fu/unsigned_multiplication/shift.py +++ b/coreblocks/func_blocks/fu/unsigned_multiplication/shift.py @@ -1,6 +1,6 @@ from amaranth import * -from coreblocks.fu.unsigned_multiplication.common import MulBaseUnsigned +from coreblocks.func_blocks.fu.unsigned_multiplication.common import MulBaseUnsigned from coreblocks.params import GenParams from transactron.core import def_method, TModule diff --git a/coreblocks/fu/zbc.py b/coreblocks/func_blocks/fu/zbc.py similarity index 96% rename from coreblocks/fu/zbc.py rename to coreblocks/func_blocks/fu/zbc.py index 8834d40fe..6d7158011 100644 --- a/coreblocks/fu/zbc.py +++ b/coreblocks/func_blocks/fu/zbc.py @@ -4,18 +4,14 @@ from amaranth import * -from coreblocks.fu.fu_decoder import DecoderManager -from coreblocks.params import ( - Funct3, - OpType, - GenParams, - FuncUnitLayouts, - FunctionalComponentParams, -) +from coreblocks.func_blocks.fu.common.fu_decoder import DecoderManager +from coreblocks.params import GenParams, FunctionalComponentParams +from coreblocks.frontend.decoder import Funct3, OpType +from coreblocks.interface.layouts import FuncUnitLayouts from transactron import Method, def_method, TModule from transactron.lib import FIFO from transactron.utils import OneHotSwitch -from coreblocks.utils.protocols import FuncUnit +from coreblocks.func_blocks.interface.func_protocols import FuncUnit class ZbcFn(DecoderManager): diff --git a/coreblocks/fu/zbs.py b/coreblocks/func_blocks/fu/zbs.py similarity index 92% rename from coreblocks/fu/zbs.py rename to coreblocks/func_blocks/fu/zbs.py index d135c5e75..7fca4253e 100644 --- a/coreblocks/fu/zbs.py +++ b/coreblocks/func_blocks/fu/zbs.py @@ -2,13 +2,15 @@ from typing import Sequence from amaranth import * -from coreblocks.params import Funct3, GenParams, FuncUnitLayouts, OpType, Funct7, FunctionalComponentParams +from coreblocks.params import GenParams, FunctionalComponentParams +from coreblocks.frontend.decoder import Funct3, OpType, Funct7 +from coreblocks.interface.layouts import FuncUnitLayouts from transactron import Method, TModule, def_method from transactron.lib import FIFO from transactron.utils import OneHotSwitch -from coreblocks.utils.protocols import FuncUnit +from coreblocks.func_blocks.interface.func_protocols import FuncUnit -from coreblocks.fu.fu_decoder import DecoderManager +from coreblocks.func_blocks.fu.common.fu_decoder import DecoderManager class ZbsFunction(DecoderManager): diff --git a/coreblocks/func_blocks/interface/__init__.py b/coreblocks/func_blocks/interface/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/coreblocks/stages/func_blocks_unifier.py b/coreblocks/func_blocks/interface/func_blocks_unifier.py similarity index 100% rename from coreblocks/stages/func_blocks_unifier.py rename to coreblocks/func_blocks/interface/func_blocks_unifier.py diff --git a/coreblocks/utils/protocols.py b/coreblocks/func_blocks/interface/func_protocols.py similarity index 100% rename from coreblocks/utils/protocols.py rename to coreblocks/func_blocks/interface/func_protocols.py diff --git a/coreblocks/func_blocks/lsu/__init__.py b/coreblocks/func_blocks/lsu/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/coreblocks/lsu/dummyLsu.py b/coreblocks/func_blocks/lsu/dummyLsu.py similarity index 97% rename from coreblocks/lsu/dummyLsu.py rename to coreblocks/func_blocks/lsu/dummyLsu.py index 3b8edd4a4..ccda62e32 100644 --- a/coreblocks/lsu/dummyLsu.py +++ b/coreblocks/func_blocks/lsu/dummyLsu.py @@ -6,10 +6,13 @@ from coreblocks.peripherals.bus_adapter import BusMasterInterface from transactron.lib.connectors import Forwarder from transactron.utils import assign, ModuleLike, DependencyManager -from coreblocks.utils.protocols import FuncBlock +from coreblocks.func_blocks.interface.func_protocols import FuncBlock from transactron.lib.simultaneous import condition -from coreblocks.lsu.pma import PMAChecker +from coreblocks.frontend.decoder import * +from coreblocks.interface.layouts import LSULayouts, FuncUnitLayouts +from coreblocks.func_blocks.lsu.pma import PMAChecker +from coreblocks.interface.keys import ExceptionReportKey, CommonBusDataKey, InstructionPrecommitKey __all__ = ["LSUDummy", "LSUBlockComponent"] diff --git a/coreblocks/lsu/pma.py b/coreblocks/func_blocks/lsu/pma.py similarity index 100% rename from coreblocks/lsu/pma.py rename to coreblocks/func_blocks/lsu/pma.py diff --git a/coreblocks/params/keys.py b/coreblocks/interface/keys.py similarity index 93% rename from coreblocks/params/keys.py rename to coreblocks/interface/keys.py index eab1b3985..9f863c614 100644 --- a/coreblocks/params/keys.py +++ b/coreblocks/interface/keys.py @@ -8,7 +8,7 @@ from amaranth import Signal if TYPE_CHECKING: - from coreblocks.structs_common.csr_generic import GenericCSRRegisters # noqa: F401 + from coreblocks.priv.csr.csr_instances import GenericCSRRegisters # noqa: F401 __all__ = [ "CommonBusDataKey", diff --git a/coreblocks/params/layouts.py b/coreblocks/interface/layouts.py similarity index 99% rename from coreblocks/params/layouts.py rename to coreblocks/interface/layouts.py index 98f69344c..5db15302e 100644 --- a/coreblocks/params/layouts.py +++ b/coreblocks/interface/layouts.py @@ -1,6 +1,6 @@ from amaranth.lib.data import StructLayout -from coreblocks.params import GenParams, OpType, Funct7, Funct3 -from coreblocks.params.isa import ExceptionCause +from coreblocks.params import GenParams +from coreblocks.frontend.decoder import ExceptionCause, OpType, Funct7, Funct3 from transactron.utils import LayoutList, LayoutListField, layout_subset from transactron.utils.transactron_helpers import from_method_layout, make_layout diff --git a/coreblocks/params/__init__.py b/coreblocks/params/__init__.py index 8e5e6dfc1..60379a5ab 100644 --- a/coreblocks/params/__init__.py +++ b/coreblocks/params/__init__.py @@ -1,8 +1,5 @@ -from .isa import * # noqa: F401 -from .optypes import * # noqa: F401 +from .isa_params import * # noqa: F401 from .genparams import * # noqa: F401 -from .layouts import * # noqa: F401 from .fu_params import * # noqa: F401 -from .keys import * # noqa: F401 from .icache_params import * # noqa: F401 from .instr import * # noqa: F401 diff --git a/coreblocks/params/configurations.py b/coreblocks/params/configurations.py index 6d69cd8f9..a9dee4931 100644 --- a/coreblocks/params/configurations.py +++ b/coreblocks/params/configurations.py @@ -2,23 +2,23 @@ import dataclasses from dataclasses import dataclass, field -from coreblocks.lsu.pma import PMARegion +from coreblocks.func_blocks.lsu.pma import PMARegion -from coreblocks.params.isa import Extension +from coreblocks.params.isa_params import Extension from coreblocks.params.fu_params import BlockComponentParams -from coreblocks.stages.rs_func_block import RSBlockComponent - -from coreblocks.fu.alu import ALUComponent -from coreblocks.fu.shift_unit import ShiftUnitComponent -from coreblocks.fu.jumpbranch import JumpComponent -from coreblocks.fu.mul_unit import MulComponent, MulType -from coreblocks.fu.div_unit import DivComponent -from coreblocks.fu.zbc import ZbcComponent -from coreblocks.fu.zbs import ZbsComponent -from coreblocks.fu.exception import ExceptionUnitComponent -from coreblocks.fu.priv import PrivilegedUnitComponent -from coreblocks.lsu.dummyLsu import LSUBlockComponent -from coreblocks.structs_common.csr import CSRBlockComponent +from coreblocks.func_blocks.fu.common.rs_func_block import RSBlockComponent + +from coreblocks.func_blocks.fu.alu import ALUComponent +from coreblocks.func_blocks.fu.shift_unit import ShiftUnitComponent +from coreblocks.func_blocks.fu.jumpbranch import JumpComponent +from coreblocks.func_blocks.fu.mul_unit import MulComponent, MulType +from coreblocks.func_blocks.fu.div_unit import DivComponent +from coreblocks.func_blocks.fu.zbc import ZbcComponent +from coreblocks.func_blocks.fu.zbs import ZbsComponent +from coreblocks.func_blocks.fu.exception import ExceptionUnitComponent +from coreblocks.func_blocks.fu.priv import PrivilegedUnitComponent +from coreblocks.func_blocks.lsu.dummyLsu import LSUBlockComponent +from coreblocks.func_blocks.csr.csr import CSRBlockComponent __all__ = ["CoreConfiguration", "basic_core_config", "tiny_core_config", "full_core_config", "test_core_config"] diff --git a/coreblocks/params/fu_params.py b/coreblocks/params/fu_params.py index e5962a1a9..297e9e9fc 100644 --- a/coreblocks/params/fu_params.py +++ b/coreblocks/params/fu_params.py @@ -1,16 +1,16 @@ from abc import abstractmethod, ABC from collections.abc import Collection, Iterable -from coreblocks.utils.protocols import FuncBlock, FuncUnit -from coreblocks.params.isa import Extension, extension_implications -from coreblocks.params.optypes import optypes_required_by_extensions +from coreblocks.func_blocks.interface.func_protocols import FuncBlock, FuncUnit +from coreblocks.params.isa_params import Extension, extension_implications +from coreblocks.frontend.decoder import optypes_required_by_extensions from typing import TYPE_CHECKING if TYPE_CHECKING: from coreblocks.params.genparams import GenParams - from coreblocks.params.optypes import OpType + from coreblocks.frontend.decoder.optypes import OpType __all__ = [ diff --git a/coreblocks/params/genparams.py b/coreblocks/params/genparams.py index 3691d02ca..5b6fe0ce2 100644 --- a/coreblocks/params/genparams.py +++ b/coreblocks/params/genparams.py @@ -2,7 +2,7 @@ from amaranth.utils import exact_log2 -from .isa import ISA, gen_isa_string +from .isa_params import ISA, gen_isa_string from .icache_params import ICacheParameters from .fu_params import extensions_supported from ..peripherals.wishbone import WishboneParameters diff --git a/coreblocks/params/instr.py b/coreblocks/params/instr.py index efaab82cb..8f14d6b11 100644 --- a/coreblocks/params/instr.py +++ b/coreblocks/params/instr.py @@ -4,7 +4,8 @@ from amaranth import * from transactron.utils import ValueLike -from coreblocks.params.isa import * +from coreblocks.params.isa_params import * +from coreblocks.frontend.decoder.isa import * __all__ = [ diff --git a/coreblocks/params/isa.py b/coreblocks/params/isa_params.py similarity index 63% rename from coreblocks/params/isa.py rename to coreblocks/params/isa_params.py index dde829023..39ce1abfa 100644 --- a/coreblocks/params/isa.py +++ b/coreblocks/params/isa_params.py @@ -1,164 +1,14 @@ from itertools import takewhile -from amaranth.lib.enum import unique, Enum, IntEnum, IntFlag, auto +from amaranth.lib.enum import unique, auto import enum __all__ = [ - "InstrType", - "Opcode", - "Funct3", - "Funct7", - "Funct12", - "ExceptionCause", "Extension", - "FenceTarget", - "FenceFm", "ISA", - "Registers", ] -@unique -class InstrType(Enum): - R = 0 - I = 1 # noqa: E741 - S = 2 - B = 3 - U = 4 - J = 5 - - -@unique -class Opcode(IntEnum, shape=5): - LOAD = 0b00000 - LOAD_FP = 0b00001 - MISC_MEM = 0b00011 - OP_IMM = 0b00100 - AUIPC = 0b00101 - OP_IMM_32 = 0b00110 - STORE = 0b01000 - STORE_FP = 0b01001 - OP = 0b01100 - LUI = 0b01101 - OP32 = 0b01110 - BRANCH = 0b11000 - JALR = 0b11001 - JAL = 0b11011 - SYSTEM = 0b11100 - - -class Funct3(IntEnum, shape=3): - JALR = BEQ = B = ADD = SUB = FENCE = PRIV = MUL = MULW = _EINSTRACCESSFAULT = 0b000 - BNE = H = SLL = FENCEI = CSRRW = MULH = BCLR = BINV = BSET = CLZ = CPOP = CTZ = ROL \ - = SEXTB = SEXTH = CLMUL = _EILLEGALINSTR = 0b001 # fmt: skip - W = SLT = CSRRS = MULHSU = SH1ADD = CLMULR = _EBREAKPOINT = 0b010 - D = SLTU = CSRRC = MULHU = CLMULH = _EINSTRPAGEFAULT = 0b011 - BLT = BU = XOR = DIV = DIVW = SH2ADD = MIN = XNOR = ZEXTH = 0b100 - BGE = HU = SR = CSRRWI = DIVU = DIVUW = BEXT = ORCB = REV8 = ROR = MINU = 0b101 - BLTU = OR = CSRRSI = REM = REMW = SH3ADD = MAX = ORN = 0b110 - BGEU = AND = CSRRCI = REMU = REMUW = ANDN = MAXU = 0b111 - - -class Funct7(IntEnum, shape=7): - SL = SLT = ADD = XOR = OR = AND = 0b0000000 - SA = SUB = ANDN = ORN = XNOR = 0b0100000 - MULDIV = 0b0000001 - SH1ADD = SH2ADD = SH3ADD = 0b0010000 - BCLR = BEXT = 0b0100100 - BINV = REV8 = 0b0110100 - BSET = ORCB = 0b0010100 - MAX = MIN = CLMUL = 0b0000101 - ROL = ROR = SEXTB = SEXTH = CPOP = CLZ = CTZ = 0b0110000 - ZEXTH = 0b0000100 - SFENCEVMA = 0b0001001 - - -class Funct12(IntEnum, shape=12): - ECALL = 0b000000000000 - EBREAK = 0b000000000001 - SRET = 0b000100000010 - MRET = 0b001100000010 - WFI = 0b000100000101 - CPOP = 0b011000000010 - CLZ = 0b011000000000 - CTZ = 0b011000000001 - ORCB = 0b001010000111 - REV8_32 = 0b011010011000 - REV8_64 = 0b011010111000 - SEXTB = 0b011000000100 - SEXTH = 0b011000000101 - ZEXTH = 0b000010000000 - - -class Registers(IntEnum, shape=5): - X0 = ZERO = 0b00000 # hardwired zero - X1 = RA = 0b00001 # return address - X2 = SP = 0b00010 # stack pointer - X3 = GP = 0b00011 # global pointer - X4 = TP = 0b00100 # thread pointer - X5 = T0 = 0b00101 # temporary register 0 - X6 = T1 = 0b00110 # temporary register 1 - X7 = T2 = 0b00111 # temporary register 2 - X8 = S0 = FP = 0b01000 # saved register 0 / frame pointer - X9 = S1 = 0b01001 # saved register 1 - X10 = A0 = 0b01010 # function argument 0 / return value 0 - X11 = A1 = 0b01011 # function argument 1 / return value 1 - X12 = A2 = 0b01100 # function argument 2 - X13 = A3 = 0b01101 # function argument 3 - X14 = A4 = 0b01110 # function argument 4 - X15 = A5 = 0b01111 # function argument 5 - X16 = A6 = 0b10000 # function argument 6 - X17 = A7 = 0b10001 # function argument 7 - X18 = S2 = 0b10010 # saved register 2 - X19 = S3 = 0b10011 # saved register 3 - X20 = S4 = 0b10100 # saved register 4 - X21 = S5 = 0b10101 # saved register 5 - X22 = S6 = 0b10110 # saved register 6 - X23 = S7 = 0b10111 # saved register 7 - X24 = S8 = 0b11000 # saved register 8 - X25 = S9 = 0b11001 # saved register 9 - X26 = S10 = 0b11010 # saved register 10 - X27 = S11 = 0b11011 # saved register 11 - X28 = T3 = 0b11100 # temporary register 3 - X29 = T4 = 0b11101 # temporary register 4 - X30 = T5 = 0b11110 # temporary register 5 - X31 = T6 = 0b11111 # temporary register 6 - - -@unique -class FenceTarget(IntFlag, shape=4): - MEM_W = 0b0001 - MEM_R = 0b0010 - DEV_O = 0b0100 - DEV_I = 0b1000 - - -@unique -class FenceFm(IntEnum, shape=4): - NONE = 0b0000 - TSO = 0b1000 - - -@unique -class ExceptionCause(IntEnum, shape=5): - INSTRUCTION_ADDRESS_MISALIGNED = 0 - INSTRUCTION_ACCESS_FAULT = 1 - ILLEGAL_INSTRUCTION = 2 - BREAKPOINT = 3 - LOAD_ADDRESS_MISALIGNED = 4 - LOAD_ACCESS_FAULT = 5 - STORE_ADDRESS_MISALIGNED = 6 - STORE_ACCESS_FAULT = 7 - ENVIRONMENT_CALL_FROM_U = 8 - ENVIRONMENT_CALL_FROM_S = 9 - ENVIRONMENT_CALL_FROM_M = 11 - INSTRUCTION_PAGE_FAULT = 12 - LOAD_PAGE_FAULT = 13 - STORE_PAGE_FAULT = 15 - _COREBLOCKS_ASYNC_INTERRUPT = 16 - _COREBLOCKS_MISPREDICTION = 17 - - @unique class Extension(enum.IntFlag): """ diff --git a/coreblocks/priv/__init__.py b/coreblocks/priv/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/coreblocks/priv/csr/__init__.py b/coreblocks/priv/csr/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/coreblocks/structs_common/csr_generic.py b/coreblocks/priv/csr/csr_instances.py similarity index 98% rename from coreblocks/structs_common/csr_generic.py rename to coreblocks/priv/csr/csr_instances.py index 6f9150d81..58b033472 100644 --- a/coreblocks/structs_common/csr_generic.py +++ b/coreblocks/priv/csr/csr_instances.py @@ -4,7 +4,7 @@ from typing import Optional from coreblocks.params.genparams import GenParams -from coreblocks.structs_common.csr import CSRRegister +from coreblocks.priv.csr.csr_register import CSRRegister from transactron.core import Method, Transaction, def_method, TModule diff --git a/coreblocks/priv/csr/csr_register.py b/coreblocks/priv/csr/csr_register.py new file mode 100644 index 000000000..8018463fd --- /dev/null +++ b/coreblocks/priv/csr/csr_register.py @@ -0,0 +1,150 @@ +from amaranth import * +from amaranth.lib.data import StructLayout +from amaranth.lib.enum import IntEnum +from dataclasses import dataclass + +from transactron import Method, def_method, TModule +from transactron.utils import bits_from_int +from coreblocks.params.genparams import GenParams +from transactron.utils.dependencies import DependencyManager, ListKey +from coreblocks.interface.layouts import CSRLayouts +from transactron.utils.transactron_helpers import from_method_layout + + +class PrivilegeLevel(IntEnum, shape=2): + USER = 0b00 + SUPERVISOR = 0b01 + MACHINE = 0b11 + + +def csr_access_privilege(csr_addr: int) -> tuple[PrivilegeLevel, bool]: + read_only = bits_from_int(csr_addr, 10, 2) == 0b11 + + match bits_from_int(csr_addr, 8, 2): + case 0b00: + return (PrivilegeLevel.USER, read_only) + case 0b01: + return (PrivilegeLevel.SUPERVISOR, read_only) + case 0b10: # Hypervisior CSRs - accessible with VS mode (S with extension) + return (PrivilegeLevel.SUPERVISOR, read_only) + case _: + return (PrivilegeLevel.MACHINE, read_only) + + +@dataclass(frozen=True) +class CSRListKey(ListKey["CSRRegister"]): + """DependencyManager key collecting CSR registers globally as a list.""" + + # This key is defined here, because it is only used internally by CSRRegister and CSRUnit + pass + + +class CSRRegister(Elaboratable): + """CSR Register + Used to define a CSR register and specify its behaviour. + `CSRRegisters` are automatically assigned to `CSRListKey` dependency key, to be accessed from `CSRUnits`. + + Attributes + ---------- + read: Method + Reads register value and side effect status. + Side effect fields `read` and `written` are set if register was accessed by _fu_read or _fu_write + methods (by CSR instruction) in a current cycle; they can be used to trigger other actions. + Always ready. + write: Method + Updates register value. + Always ready. If _fu_write is called simultaneously, this call is ignored. + _fu_read: Method + Method connected automatically by `CSRUnit`. Reads register value. + _fu_write: Method + Method connected automatically by `CSRUnit`. Updates register value. + Always ready. Has priority over `write` method. + + Examples + -------- + .. highlight:: python + .. code-block:: python + + # Timer register that increments on each cycle and resets if read by CSR instruction + csr = CSRRegister(1, gen_params) + with Transaction.body(m): + csr_val = csr.read() + with m.If(csr_val.read): + csr.write(0) + with m.Else(): + csr.write(csr_val.data + 1) + """ + + def __init__(self, csr_number: int, gen_params: GenParams, *, ro_bits: int = 0): + """ + Parameters + ---------- + csr_number: int + Address of this CSR Register. + gen_params: GenParams + Core generation parameters. + ro_bits: int + Bit mask of read-only bits in register. + Writes from _fu_write (instructions) to those bits are ignored. + Note that this parameter is only required if there are some read-only + bits in read-write register. Writes to read-only registers specified + by upper 2 bits of CSR address set to `0b11` are discarded by `CSRUnit`. + """ + self.gen_params = gen_params + self.csr_number = csr_number + self.ro_bits = ro_bits + + csr_layouts = gen_params.get(CSRLayouts) + + self.read = Method(o=csr_layouts.read) + self.write = Method(i=csr_layouts.write) + + # Methods connected automatically by CSRUnit + self._fu_read = Method(o=csr_layouts._fu_read) + self._fu_write = Method(i=csr_layouts._fu_write) + + self.value = Signal(gen_params.isa.xlen) + self.side_effects = Signal(StructLayout({"read": 1, "write": 1})) + + # append to global CSR list + dm = gen_params.get(DependencyManager) + dm.add_dependency(CSRListKey(), self) + + def elaborate(self, platform): + m = TModule() + + internal_method_layout = from_method_layout([("data", self.gen_params.isa.xlen), ("active", 1)]) + write_internal = Signal(internal_method_layout) + fu_write_internal = Signal(internal_method_layout) + + m.d.sync += self.side_effects.eq(0) + + @def_method(m, self.write) + def _(data): + m.d.comb += write_internal.data.eq(data) + m.d.comb += write_internal.active.eq(1) + + @def_method(m, self._fu_write) + def _(data): + m.d.comb += fu_write_internal.data.eq(data) + m.d.comb += fu_write_internal.active.eq(1) + m.d.sync += self.side_effects.write.eq(1) + + @def_method(m, self.read) + def _(): + return {"data": self.value, "read": self.side_effects.read, "written": self.side_effects.write} + + @def_method(m, self._fu_read) + def _(): + m.d.sync += self.side_effects.read.eq(1) + return self.value + + # Writes from instructions have priority + with m.If(fu_write_internal.active & write_internal.active): + m.d.sync += self.value.eq((fu_write_internal.data & ~self.ro_bits) | (write_internal.data & self.ro_bits)) + with m.Elif(fu_write_internal.active): + m.d.sync += self.value.eq((fu_write_internal.data & ~self.ro_bits) | (self.value & self.ro_bits)) + with m.Elif(write_internal.active): + m.d.sync += self.value.eq(write_internal.data) + + return m diff --git a/coreblocks/priv/traps/__init__.py b/coreblocks/priv/traps/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/coreblocks/structs_common/exception.py b/coreblocks/priv/traps/exception.py similarity index 96% rename from coreblocks/structs_common/exception.py rename to coreblocks/priv/traps/exception.py index 4385b12f6..fea3cafaf 100644 --- a/coreblocks/structs_common/exception.py +++ b/coreblocks/priv/traps/exception.py @@ -2,9 +2,9 @@ from transactron.utils.dependencies import DependencyManager from coreblocks.params.genparams import GenParams -from coreblocks.params.isa import ExceptionCause -from coreblocks.params.layouts import ExceptionRegisterLayouts -from coreblocks.params.keys import ExceptionReportKey +from coreblocks.frontend.decoder.isa import ExceptionCause +from coreblocks.interface.layouts import ExceptionRegisterLayouts +from coreblocks.interface.keys import ExceptionReportKey from transactron.core import TModule, def_method, Method from transactron.lib.connectors import ConnectTrans from transactron.lib.fifo import BasicFifo diff --git a/coreblocks/structs_common/instr_counter.py b/coreblocks/priv/traps/instr_counter.py similarity index 95% rename from coreblocks/structs_common/instr_counter.py rename to coreblocks/priv/traps/instr_counter.py index 73b30eb7a..b30790aa9 100644 --- a/coreblocks/structs_common/instr_counter.py +++ b/coreblocks/priv/traps/instr_counter.py @@ -1,6 +1,6 @@ from amaranth import * from coreblocks.params.genparams import GenParams -from coreblocks.params.layouts import CoreInstructionCounterLayouts +from coreblocks.interface.layouts import CoreInstructionCounterLayouts from transactron.core import Method, TModule, def_method diff --git a/coreblocks/structs_common/interrupt_controller.py b/coreblocks/priv/traps/interrupt_controller.py similarity index 94% rename from coreblocks/structs_common/interrupt_controller.py rename to coreblocks/priv/traps/interrupt_controller.py index 3b98f8a53..d79ac18bd 100644 --- a/coreblocks/structs_common/interrupt_controller.py +++ b/coreblocks/priv/traps/interrupt_controller.py @@ -1,7 +1,7 @@ from amaranth import * from transactron.utils.dependencies import DependencyManager from coreblocks.params.genparams import GenParams -from coreblocks.params.keys import AsyncInterruptInsertSignalKey, MretKey +from coreblocks.interface.keys import AsyncInterruptInsertSignalKey, MretKey from transactron.core import Method, TModule, def_method diff --git a/coreblocks/scheduler/scheduler.py b/coreblocks/scheduler/scheduler.py index 6e7e152bd..f9758fac7 100644 --- a/coreblocks/scheduler/scheduler.py +++ b/coreblocks/scheduler/scheduler.py @@ -4,11 +4,13 @@ from transactron import Method, Transaction, TModule from transactron.lib import FIFO, Forwarder -from coreblocks.params import SchedulerLayouts, GenParams, OpType +from coreblocks.interface.layouts import SchedulerLayouts +from coreblocks.params import GenParams +from coreblocks.frontend.decoder.optypes import OpType from transactron.utils import assign, AssignType from transactron.utils.dependencies import DependencyManager -from coreblocks.params.keys import CoreStateKey -from coreblocks.utils.protocols import FuncBlock +from coreblocks.interface.keys import CoreStateKey +from coreblocks.func_blocks.interface.func_protocols import FuncBlock __all__ = ["Scheduler"] diff --git a/coreblocks/scheduler/wakeup_select.py b/coreblocks/scheduler/wakeup_select.py index 724d6ffe7..a9eaaf302 100644 --- a/coreblocks/scheduler/wakeup_select.py +++ b/coreblocks/scheduler/wakeup_select.py @@ -1,6 +1,7 @@ from amaranth import * -from coreblocks.params import GenParams, FuncUnitLayouts +from coreblocks.params import GenParams +from coreblocks.interface.layouts import FuncUnitLayouts from transactron.utils import assign, AssignType from transactron.core import * diff --git a/scripts/synthesize.py b/scripts/synthesize.py index 6c5c2f7eb..71c3574c2 100755 --- a/scripts/synthesize.py +++ b/scripts/synthesize.py @@ -19,12 +19,12 @@ from coreblocks.params.genparams import GenParams from coreblocks.params.fu_params import FunctionalComponentParams from coreblocks.core import Core -from coreblocks.fu.alu import ALUComponent -from coreblocks.fu.div_unit import DivComponent -from coreblocks.fu.mul_unit import MulComponent, MulType -from coreblocks.fu.shift_unit import ShiftUnitComponent -from coreblocks.fu.zbc import ZbcComponent -from coreblocks.fu.zbs import ZbsComponent +from coreblocks.func_blocks.fu.alu import ALUComponent +from coreblocks.func_blocks.fu.div_unit import DivComponent +from coreblocks.func_blocks.fu.mul_unit import MulComponent, MulType +from coreblocks.func_blocks.fu.shift_unit import ShiftUnitComponent +from coreblocks.func_blocks.fu.zbc import ZbcComponent +from coreblocks.func_blocks.fu.zbs import ZbsComponent from transactron import TransactionModule from transactron.lib import AdapterBase, AdapterTrans from coreblocks.peripherals.wishbone import WishboneArbiter, WishboneInterface diff --git a/test/cache/test_icache.py b/test/cache/test_icache.py index 2afeff6db..3bd198c43 100644 --- a/test/cache/test_icache.py +++ b/test/cache/test_icache.py @@ -8,7 +8,8 @@ from transactron.lib import AdapterTrans, Adapter from coreblocks.cache.icache import ICache, ICacheBypass, CacheRefillerInterface -from coreblocks.params import GenParams, ICacheLayouts +from coreblocks.params import GenParams +from coreblocks.interface.layouts import ICacheLayouts from coreblocks.peripherals.wishbone import WishboneMaster, WishboneParameters from coreblocks.peripherals.bus_adapter import WishboneMasterAdapter from coreblocks.params.configurations import test_core_config diff --git a/test/frontend/test_decode_stage.py b/test/frontend/test_decode_stage.py index c9c80251a..c3bc6338e 100644 --- a/test/frontend/test_decode_stage.py +++ b/test/frontend/test_decode_stage.py @@ -2,8 +2,10 @@ from transactron.testing import TestCaseWithSimulator, TestbenchIO, SimpleTestCircuit, ModuleConnector -from coreblocks.frontend.decode_stage import DecodeStage -from coreblocks.params import GenParams, FetchLayouts, DecodeLayouts, OpType, Funct3, Funct7 +from coreblocks.frontend.decoder.decode_stage import DecodeStage +from coreblocks.params import GenParams +from coreblocks.frontend.decoder import OpType, Funct3, Funct7 +from coreblocks.interface.layouts import FetchLayouts, DecodeLayouts from coreblocks.params.configurations import test_core_config diff --git a/test/frontend/test_fetch.py b/test/frontend/test_fetch.py index e57392485..b9ff1388c 100644 --- a/test/frontend/test_fetch.py +++ b/test/frontend/test_fetch.py @@ -7,10 +7,11 @@ from transactron.core import Method from transactron.lib import AdapterTrans, FIFO, Adapter -from coreblocks.frontend.fetch import Fetch, UnalignedFetch +from coreblocks.frontend.fetch.fetch import Fetch, UnalignedFetch from coreblocks.cache.iface import CacheInterface from coreblocks.params import * from coreblocks.params.configurations import test_core_config +from coreblocks.interface.layouts import ICacheLayouts, FetchLayouts from transactron.utils import ModuleConnector from transactron.testing import TestCaseWithSimulator, TestbenchIO, def_method_mock, SimpleTestCircuit diff --git a/test/frontend/test_instr_decoder.py b/test/frontend/test_instr_decoder.py index 4c0a0b4b6..2fea2e77f 100644 --- a/test/frontend/test_instr_decoder.py +++ b/test/frontend/test_instr_decoder.py @@ -4,7 +4,8 @@ from coreblocks.params import * from coreblocks.params.configurations import test_core_config -from coreblocks.frontend.instr_decoder import InstrDecoder, Encoding, instructions_by_optype +from coreblocks.frontend.decoder.instr_decoder import InstrDecoder, Encoding, instructions_by_optype +from coreblocks.frontend.decoder import * from unittest import TestCase from typing import Optional diff --git a/test/frontend/test_rvc.py b/test/frontend/test_rvc.py index d31d21e63..0b099f751 100644 --- a/test/frontend/test_rvc.py +++ b/test/frontend/test_rvc.py @@ -3,7 +3,8 @@ from amaranth.sim import Settle from amaranth import * -from coreblocks.frontend.rvc import InstrDecompress +from coreblocks.frontend.decoder.rvc import InstrDecompress +from coreblocks.frontend.decoder import * from coreblocks.params import * from coreblocks.params.configurations import test_core_config from transactron.utils import ValueLike diff --git a/test/fu/functional_common.py b/test/fu/functional_common.py index 7d21682cb..51e8713ef 100644 --- a/test/fu/functional_common.py +++ b/test/fu/functional_common.py @@ -11,10 +11,10 @@ from coreblocks.params.configurations import test_core_config from transactron.utils.dependencies import DependencyManager from coreblocks.params.fu_params import FunctionalComponentParams -from coreblocks.params.isa import Funct3, Funct7 -from coreblocks.params.keys import AsyncInterruptInsertSignalKey, ExceptionReportKey -from coreblocks.params.layouts import ExceptionRegisterLayouts -from coreblocks.params.optypes import OpType +from coreblocks.frontend.decoder.isa import Funct3, Funct7 +from coreblocks.interface.keys import AsyncInterruptInsertSignalKey, ExceptionReportKey +from coreblocks.interface.layouts import ExceptionRegisterLayouts +from coreblocks.frontend.decoder.optypes import OpType from transactron.lib import Adapter from transactron.testing import RecordIntDict, RecordIntDictRet, TestbenchIO, TestCaseWithSimulator, SimpleTestCircuit from transactron.utils import ModuleConnector diff --git a/test/fu/test_alu.py b/test/fu/test_alu.py index 7e973fc92..3fb67072d 100644 --- a/test/fu/test_alu.py +++ b/test/fu/test_alu.py @@ -1,5 +1,5 @@ -from coreblocks.params import Funct3, Funct7, OpType -from coreblocks.fu.alu import AluFn, ALUComponent +from coreblocks.frontend.decoder import Funct3, Funct7, OpType +from coreblocks.func_blocks.fu.alu import AluFn, ALUComponent from test.fu.functional_common import ExecFn, FunctionalUnitTestCase diff --git a/test/fu/test_div_unit.py b/test/fu/test_div_unit.py index c8c3e9b4c..0b792825c 100644 --- a/test/fu/test_div_unit.py +++ b/test/fu/test_div_unit.py @@ -1,7 +1,7 @@ from parameterized import parameterized_class -from coreblocks.params import Funct3, Funct7, OpType -from coreblocks.fu.div_unit import DivFn, DivComponent +from coreblocks.frontend.decoder import Funct3, Funct7, OpType +from coreblocks.func_blocks.fu.div_unit import DivFn, DivComponent from test.fu.functional_common import ExecFn, FunctionalUnitTestCase diff --git a/test/fu/test_exception_unit.py b/test/fu/test_exception_unit.py index a1484b074..35adb71b6 100644 --- a/test/fu/test_exception_unit.py +++ b/test/fu/test_exception_unit.py @@ -1,8 +1,6 @@ -from amaranth import * - -from coreblocks.params import * -from coreblocks.fu.exception import ExceptionUnitFn, ExceptionUnitComponent -from coreblocks.params.isa import ExceptionCause +from coreblocks.func_blocks.fu.exception import ExceptionUnitFn, ExceptionUnitComponent +from coreblocks.frontend.decoder.isa import ExceptionCause +from coreblocks.frontend.decoder import OpType, Funct3 from test.fu.functional_common import ExecFn, FunctionalUnitTestCase diff --git a/test/fu/test_fu_decoder.py b/test/fu/test_fu_decoder.py index 965e07e40..1674af001 100644 --- a/test/fu/test_fu_decoder.py +++ b/test/fu/test_fu_decoder.py @@ -5,8 +5,9 @@ from transactron.testing import SimpleTestCircuit, TestCaseWithSimulator -from coreblocks.fu.fu_decoder import DecoderManager, Decoder -from coreblocks.params import OpType, Funct3, Funct7, GenParams +from coreblocks.func_blocks.fu.common.fu_decoder import DecoderManager, Decoder +from coreblocks.frontend.decoder import OpType, Funct3, Funct7 +from coreblocks.params import GenParams from coreblocks.params.configurations import test_core_config from enum import IntFlag, auto diff --git a/test/fu/test_jb_unit.py b/test/fu/test_jb_unit.py index 559062989..5a6ba2ce7 100644 --- a/test/fu/test_jb_unit.py +++ b/test/fu/test_jb_unit.py @@ -3,10 +3,11 @@ from parameterized import parameterized_class from coreblocks.params import * -from coreblocks.fu.jumpbranch import JumpBranchFuncUnit, JumpBranchFn, JumpComponent +from coreblocks.func_blocks.fu.jumpbranch import JumpBranchFuncUnit, JumpBranchFn, JumpComponent from transactron import Method, def_method, TModule -from coreblocks.params.layouts import FuncUnitLayouts -from coreblocks.utils.protocols import FuncUnit +from coreblocks.interface.layouts import FuncUnitLayouts, JumpBranchLayouts +from coreblocks.func_blocks.interface.func_protocols import FuncUnit +from coreblocks.frontend.decoder import Funct3, OpType, ExceptionCause from transactron.utils import signed_to_int diff --git a/test/fu/test_mul_unit.py b/test/fu/test_mul_unit.py index 34f87e7a8..201ddd98b 100644 --- a/test/fu/test_mul_unit.py +++ b/test/fu/test_mul_unit.py @@ -1,7 +1,7 @@ from parameterized import parameterized_class -from coreblocks.params import * -from coreblocks.fu.mul_unit import MulFn, MulComponent, MulType +from coreblocks.frontend.decoder import Funct3, Funct7, OpType +from coreblocks.func_blocks.fu.mul_unit import MulFn, MulComponent, MulType from transactron.utils import signed_to_int, int_to_signed diff --git a/test/fu/test_shift_unit.py b/test/fu/test_shift_unit.py index 20eed6d55..f004bccac 100644 --- a/test/fu/test_shift_unit.py +++ b/test/fu/test_shift_unit.py @@ -1,5 +1,5 @@ -from coreblocks.params import Funct3, Funct7, OpType -from coreblocks.fu.shift_unit import ShiftUnitFn, ShiftUnitComponent +from coreblocks.frontend.decoder import Funct3, Funct7, OpType +from coreblocks.func_blocks.fu.shift_unit import ShiftUnitFn, ShiftUnitComponent from test.fu.functional_common import ExecFn, FunctionalUnitTestCase diff --git a/test/fu/test_unsigned_mul_unit.py b/test/fu/test_unsigned_mul_unit.py index 56b3657e6..42e5fc624 100644 --- a/test/fu/test_unsigned_mul_unit.py +++ b/test/fu/test_unsigned_mul_unit.py @@ -5,10 +5,10 @@ from amaranth.sim import Settle from parameterized import parameterized_class -from coreblocks.fu.unsigned_multiplication.common import MulBaseUnsigned -from coreblocks.fu.unsigned_multiplication.fast_recursive import RecursiveUnsignedMul -from coreblocks.fu.unsigned_multiplication.sequence import SequentialUnsignedMul -from coreblocks.fu.unsigned_multiplication.shift import ShiftUnsignedMul +from coreblocks.func_blocks.fu.unsigned_multiplication.common import MulBaseUnsigned +from coreblocks.func_blocks.fu.unsigned_multiplication.fast_recursive import RecursiveUnsignedMul +from coreblocks.func_blocks.fu.unsigned_multiplication.sequence import SequentialUnsignedMul +from coreblocks.func_blocks.fu.unsigned_multiplication.shift import ShiftUnsignedMul from transactron.testing import TestCaseWithSimulator, SimpleTestCircuit diff --git a/test/fu/test_zbc.py b/test/fu/test_zbc.py index c4c63041d..e26ae379b 100644 --- a/test/fu/test_zbc.py +++ b/test/fu/test_zbc.py @@ -1,7 +1,7 @@ from parameterized import parameterized_class -from coreblocks.fu.zbc import ZbcFn, ZbcComponent -from coreblocks.params import * +from coreblocks.func_blocks.fu.zbc import ZbcFn, ZbcComponent +from coreblocks.frontend.decoder import Funct3, Funct7, OpType from coreblocks.params.configurations import test_core_config from test.fu.functional_common import ExecFn, FunctionalUnitTestCase diff --git a/test/fu/test_zbs.py b/test/fu/test_zbs.py index a629dd3b5..790bc58a2 100644 --- a/test/fu/test_zbs.py +++ b/test/fu/test_zbs.py @@ -1,6 +1,5 @@ -from coreblocks.params import Funct3, Funct7 -from coreblocks.fu.zbs import ZbsFunction, ZbsComponent -from coreblocks.params.optypes import OpType +from coreblocks.frontend.decoder import Funct3, Funct7, OpType +from coreblocks.func_blocks.fu.zbs import ZbsFunction, ZbsComponent from test.fu.functional_common import ExecFn, FunctionalUnitTestCase diff --git a/test/lsu/test_dummylsu.py b/test/lsu/test_dummylsu.py index 61e9a3f29..4211720a6 100644 --- a/test/lsu/test_dummylsu.py +++ b/test/lsu/test_dummylsu.py @@ -6,13 +6,13 @@ from transactron.lib import Adapter from transactron.utils import int_to_signed, signed_to_int -from coreblocks.params import OpType, GenParams -from coreblocks.lsu.dummyLsu import LSUDummy +from coreblocks.params import GenParams +from coreblocks.func_blocks.lsu.dummyLsu import LSUDummy from coreblocks.params.configurations import test_core_config -from coreblocks.params.isa import * -from coreblocks.params.keys import ExceptionReportKey +from coreblocks.frontend.decoder import * +from coreblocks.interface.keys import ExceptionReportKey from transactron.utils.dependencies import DependencyManager -from coreblocks.params.layouts import ExceptionRegisterLayouts +from coreblocks.interface.layouts import ExceptionRegisterLayouts from coreblocks.peripherals.wishbone import * from transactron.testing import TestbenchIO, TestCaseWithSimulator, def_method_mock from coreblocks.peripherals.bus_adapter import WishboneMasterAdapter diff --git a/test/lsu/test_pma.py b/test/lsu/test_pma.py index 07c36652d..aa19b4005 100644 --- a/test/lsu/test_pma.py +++ b/test/lsu/test_pma.py @@ -1,14 +1,14 @@ from amaranth.sim import Settle -from coreblocks.lsu.pma import PMAChecker, PMARegion +from coreblocks.func_blocks.lsu.pma import PMAChecker, PMARegion from transactron.lib import Adapter -from coreblocks.params import OpType, GenParams -from coreblocks.lsu.dummyLsu import LSUDummy +from coreblocks.params import GenParams +from coreblocks.func_blocks.lsu.dummyLsu import LSUDummy from coreblocks.params.configurations import test_core_config -from coreblocks.params.isa import * -from coreblocks.params.keys import ExceptionReportKey +from coreblocks.frontend.decoder import * +from coreblocks.interface.keys import ExceptionReportKey from transactron.utils.dependencies import DependencyManager -from coreblocks.params.layouts import ExceptionRegisterLayouts +from coreblocks.interface.layouts import ExceptionRegisterLayouts from coreblocks.peripherals.wishbone import * from transactron.testing import TestbenchIO, TestCaseWithSimulator, def_method_mock from coreblocks.peripherals.bus_adapter import WishboneMasterAdapter diff --git a/test/params/test_configurations.py b/test/params/test_configurations.py index 786dbad93..f15171966 100644 --- a/test/params/test_configurations.py +++ b/test/params/test_configurations.py @@ -3,7 +3,7 @@ from coreblocks.params.genparams import GenParams from coreblocks.params.configurations import * -from coreblocks.params.isa import gen_isa_string +from coreblocks.params.isa_params import gen_isa_string from coreblocks.params.fu_params import extensions_supported diff --git a/test/params/test_isa.py b/test/params/test_isa.py index ef77c8c7a..5b3295f38 100644 --- a/test/params/test_isa.py +++ b/test/params/test_isa.py @@ -1,6 +1,6 @@ import unittest -from coreblocks.params.isa import Extension, ISA +from coreblocks.params.isa_params import Extension, ISA class TestISA(unittest.TestCase): diff --git a/test/scheduler/test_rs_selection.py b/test/scheduler/test_rs_selection.py index 322323fb2..58dea22c3 100644 --- a/test/scheduler/test_rs_selection.py +++ b/test/scheduler/test_rs_selection.py @@ -4,7 +4,9 @@ from amaranth import * from amaranth.sim import Settle, Passive -from coreblocks.params import GenParams, RSLayouts, SchedulerLayouts, OpType, Funct3, Funct7 +from coreblocks.params import GenParams +from coreblocks.interface.layouts import RSLayouts, SchedulerLayouts +from coreblocks.frontend.decoder import OpType, Funct3, Funct7 from coreblocks.params.configurations import test_core_config from coreblocks.scheduler.scheduler import RSSelection from transactron.lib import FIFO, Adapter, AdapterTrans diff --git a/test/scheduler/test_scheduler.py b/test/scheduler/test_scheduler.py index a25979c49..3c50efab6 100644 --- a/test/scheduler/test_scheduler.py +++ b/test/scheduler/test_scheduler.py @@ -5,20 +5,22 @@ from amaranth import * from amaranth.sim import Settle from parameterized import parameterized_class -from coreblocks.params.keys import CoreStateKey -from coreblocks.params.layouts import RetirementLayouts -from coreblocks.stages.rs_func_block import RSBlockComponent +from coreblocks.interface.keys import CoreStateKey +from coreblocks.interface.layouts import RetirementLayouts +from coreblocks.func_blocks.fu.common.rs_func_block import RSBlockComponent from transactron.core import Method from transactron.lib import FIFO, AdapterTrans, Adapter from transactron.utils.dependencies import DependencyManager from coreblocks.scheduler.scheduler import Scheduler -from coreblocks.structs_common.rf import RegisterFile -from coreblocks.structs_common.rat import FRAT -from coreblocks.params import RSLayouts, DecodeLayouts, SchedulerLayouts, GenParams, OpType, Funct3, Funct7 +from coreblocks.core_structs.rf import RegisterFile +from coreblocks.core_structs.rat import FRAT +from coreblocks.params import GenParams +from coreblocks.interface.layouts import RSLayouts, DecodeLayouts, SchedulerLayouts +from coreblocks.frontend.decoder import OpType, Funct3, Funct7 from coreblocks.params.configurations import test_core_config -from coreblocks.structs_common.rob import ReorderBuffer -from coreblocks.utils.protocols import FuncBlock +from coreblocks.core_structs.rob import ReorderBuffer +from coreblocks.func_blocks.interface.func_protocols import FuncBlock from transactron.testing import RecordIntDict, TestCaseWithSimulator, TestGen, TestbenchIO, def_method_mock diff --git a/test/scheduler/test_wakeup_select.py b/test/scheduler/test_wakeup_select.py index ec0cb158c..4ff298da9 100644 --- a/test/scheduler/test_wakeup_select.py +++ b/test/scheduler/test_wakeup_select.py @@ -8,9 +8,10 @@ from inspect import isclass import random -from coreblocks.params import GenParams, RSLayouts +from coreblocks.params import GenParams +from coreblocks.interface.layouts import RSLayouts from coreblocks.params.configurations import test_core_config -from coreblocks.stages.rs_func_block import RSBlockComponent +from coreblocks.func_blocks.fu.common.rs_func_block import RSBlockComponent from transactron import * from transactron.lib import Adapter from coreblocks.scheduler.wakeup_select import * diff --git a/test/stages/test_backend.py b/test/stages/test_backend.py index 2dc1695f8..780ff1d20 100644 --- a/test/stages/test_backend.py +++ b/test/stages/test_backend.py @@ -4,8 +4,8 @@ from amaranth import * from transactron.lib import FIFO, AdapterTrans, Adapter, ManyToOneConnectTrans -from coreblocks.stages.backend import ResultAnnouncement -from coreblocks.params.layouts import * +from coreblocks.backend.annoucement import ResultAnnouncement +from coreblocks.interface.layouts import * from coreblocks.params import GenParams from coreblocks.params.configurations import test_core_config from transactron.testing import TestCaseWithSimulator, TestbenchIO diff --git a/test/stages/test_retirement.py b/test/stages/test_retirement.py index 1502eb0b9..c544baa3c 100644 --- a/test/stages/test_retirement.py +++ b/test/stages/test_retirement.py @@ -1,10 +1,11 @@ -from coreblocks.params.layouts import CoreInstructionCounterLayouts, ExceptionRegisterLayouts, FetchLayouts -from coreblocks.stages.retirement import * -from coreblocks.structs_common.csr_generic import GenericCSRRegisters +from coreblocks.interface.layouts import CoreInstructionCounterLayouts, ExceptionRegisterLayouts, FetchLayouts +from coreblocks.backend.retirement import * +from coreblocks.priv.csr.csr_instances import GenericCSRRegisters from transactron.lib import FIFO, Adapter -from coreblocks.structs_common.rat import FRAT, RRAT -from coreblocks.params import ROBLayouts, RFLayouts, GenParams, LSULayouts, SchedulerLayouts +from coreblocks.core_structs.rat import FRAT, RRAT +from coreblocks.params import GenParams +from coreblocks.interface.layouts import ROBLayouts, RFLayouts, LSULayouts, SchedulerLayouts from coreblocks.params.configurations import test_core_config from transactron.testing import * diff --git a/test/structs_common/test_csr.py b/test/structs_common/test_csr.py index 4df317ba8..62ec75bbe 100644 --- a/test/structs_common/test_csr.py +++ b/test/structs_common/test_csr.py @@ -1,14 +1,14 @@ from amaranth import * from transactron.lib import Adapter -from coreblocks.structs_common.csr import CSRUnit, CSRRegister +from coreblocks.func_blocks.csr.csr import CSRUnit +from coreblocks.priv.csr.csr_register import CSRRegister from coreblocks.params import GenParams -from coreblocks.params.isa import Funct3, ExceptionCause +from coreblocks.frontend.decoder import Funct3, ExceptionCause, OpType from coreblocks.params.configurations import test_core_config -from coreblocks.params.layouts import ExceptionRegisterLayouts -from coreblocks.params.keys import AsyncInterruptInsertSignalKey, ExceptionReportKey +from coreblocks.interface.layouts import ExceptionRegisterLayouts +from coreblocks.interface.keys import AsyncInterruptInsertSignalKey, ExceptionReportKey from transactron.utils.dependencies import DependencyManager -from coreblocks.params.optypes import OpType from transactron.testing import * diff --git a/test/structs_common/test_exception.py b/test/structs_common/test_exception.py index 1988f5ad3..4cd99cb48 100644 --- a/test/structs_common/test_exception.py +++ b/test/structs_common/test_exception.py @@ -1,9 +1,9 @@ from amaranth import * -from coreblocks.params.layouts import ROBLayouts +from coreblocks.interface.layouts import ROBLayouts -from coreblocks.structs_common.exception import ExceptionCauseRegister +from coreblocks.priv.traps.exception import ExceptionCauseRegister from coreblocks.params import GenParams -from coreblocks.params.isa import ExceptionCause +from coreblocks.frontend.decoder import ExceptionCause from coreblocks.params.configurations import test_core_config from transactron.lib import Adapter from transactron.utils import ModuleConnector diff --git a/test/structs_common/test_rat.py b/test/structs_common/test_rat.py index 6fb281761..56ccbe6c4 100644 --- a/test/structs_common/test_rat.py +++ b/test/structs_common/test_rat.py @@ -1,6 +1,6 @@ from transactron.testing import TestCaseWithSimulator, SimpleTestCircuit -from coreblocks.structs_common.rat import FRAT, RRAT +from coreblocks.core_structs.rat import FRAT, RRAT from coreblocks.params import GenParams from coreblocks.params.configurations import test_core_config diff --git a/test/structs_common/test_reorder_buffer.py b/test/structs_common/test_reorder_buffer.py index 26731e635..e29bcf385 100644 --- a/test/structs_common/test_reorder_buffer.py +++ b/test/structs_common/test_reorder_buffer.py @@ -2,7 +2,7 @@ from transactron.testing import TestCaseWithSimulator, SimpleTestCircuit -from coreblocks.structs_common.rob import ReorderBuffer +from coreblocks.core_structs.rob import ReorderBuffer from coreblocks.params import GenParams from coreblocks.params.configurations import test_core_config diff --git a/test/structs_common/test_rs.py b/test/structs_common/test_rs.py index d5b9b4741..4e86a46de 100644 --- a/test/structs_common/test_rs.py +++ b/test/structs_common/test_rs.py @@ -2,9 +2,10 @@ from transactron.testing import TestCaseWithSimulator, get_outputs, SimpleTestCircuit -from coreblocks.structs_common.rs import RS +from coreblocks.func_blocks.fu.common.rs import RS from coreblocks.params import * from coreblocks.params.configurations import test_core_config +from coreblocks.frontend.decoder import OpType def create_check_list(rs_entries_bits: int, insert_list: list[dict]) -> list[dict]: diff --git a/test/transactions/test_transaction_lib.py b/test/transactions/test_transaction_lib.py index dd3899964..c8e758ce7 100644 --- a/test/transactions/test_transaction_lib.py +++ b/test/transactions/test_transaction_lib.py @@ -11,7 +11,6 @@ from amaranth import * from transactron import * from transactron.lib import * -from coreblocks.utils import * from transactron.utils._typing import ModuleLike, MethodStruct, RecordDict from transactron.utils import ModuleConnector from transactron.testing import (