From 05c48c2cd99cd5b7b19405aa09cb90f868f18353 Mon Sep 17 00:00:00 2001 From: tilk Date: Wed, 22 Nov 2023 23:47:38 +0000 Subject: [PATCH] Transaction graph and docs cleanup (#521) --- .doctrees/api.doctree | Bin 34284 -> 20945 bytes .doctrees/assumptions.doctree | Bin 0 -> 5029 bytes .doctrees/auto_graph.doctree | Bin 24894 -> 24896 bytes .doctrees/current-graph.doctree | Bin 0 -> 26117 bytes .doctrees/development-environment.doctree | Bin 0 -> 22994 bytes .doctrees/environment.pickle | Bin 330814 -> 331107 bytes .doctrees/home.doctree | Bin 0 -> 5853 bytes .doctrees/index.doctree | Bin 3293 -> 3294 bytes .../miscellany/exceptions-summary.doctree | Bin 0 -> 36919 bytes .doctrees/problem-checklist.doctree | Bin 0 -> 6578 bytes .doctrees/scheduler/overview.doctree | Bin 0 -> 8260 bytes .../implementation/rs-impl.doctree | Bin 0 -> 30568 bytes .doctrees/shared-structs/rs.doctree | Bin 0 -> 20610 bytes .doctrees/synthesis/synthesis.doctree | Bin 0 -> 11720 bytes .doctrees/transactions.doctree | Bin 0 -> 56692 bytes _sources/assumptions.md.txt | 8 + _sources/auto_graph.rst.txt | 90 +-- _sources/current-graph.md.txt | 12 + _sources/development-environment.md.txt | 78 +++ _sources/home.md.txt | 36 ++ _sources/index.md.txt | 22 +- _sources/miscellany/exceptions-summary.md.txt | 153 +++++ _sources/problem-checklist.md.txt | 15 + _sources/scheduler/overview.md.txt | 46 ++ .../implementation/rs-impl.md.txt | 110 ++++ _sources/shared-structs/rs.md.txt | 91 +++ _sources/synthesis/synthesis.md.txt | 49 ++ _sources/transactions.md.txt | 336 ++++++++++ api.html | 28 +- assumptions.html | 125 ++++ auto_graph.html | 114 ++-- components/icache.html | 32 +- coreblocks.frontend.html | 24 +- coreblocks.fu.html | 24 +- coreblocks.fu.unsigned_multiplication.html | 24 +- coreblocks.html | 24 +- coreblocks.params.html | 24 +- coreblocks.peripherals.html | 24 +- coreblocks.scheduler.html | 24 +- coreblocks.stages.html | 24 +- coreblocks.structs_common.html | 24 +- coreblocks.utils.html | 24 +- current-graph.html | 581 ++++++++++++++++++ development-environment.html | 199 ++++++ genindex.html | 24 +- home.html | 150 +++++ index.html | 172 +++--- miscellany/exceptions-summary.html | 292 +++++++++ modules-coreblocks.html | 24 +- modules-transactron.html | 24 +- objects.inv | Bin 8112 -> 8084 bytes problem-checklist.html | 126 ++++ py-modindex.html | 24 +- scheduler/overview.html | 167 +++++ search.html | 24 +- searchindex.js | 2 +- shared-structs/implementation/rs-impl.html | 273 ++++++++ shared-structs/rs.html | 243 ++++++++ synthesis/synthesis.html | 172 ++++++ transactions.html | 430 +++++++++++++ transactron.html | 24 +- transactron.lib.html | 24 +- transactron.utils.html | 24 +- 63 files changed, 4138 insertions(+), 446 deletions(-) create mode 100644 .doctrees/assumptions.doctree create mode 100644 .doctrees/current-graph.doctree create mode 100644 .doctrees/development-environment.doctree create mode 100644 .doctrees/home.doctree create mode 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zn*f`8@O<%&Z+bJ(vA?rcak{4`y8HXNd&rtk9CtP7EQLX`CdPo&9{8b1+ zHL3N^?@5n>rJAKoy0QtB;x-ZZ6X_8F7tUP6<}0{HrJzMvs)CjGcKqwvSBTz0d3j^0 z7OvMC_y_gNu;ef6ok^1Ws>8$KQbRXmG9YO0_Z>77M z?vZ*VAO(032OHs13viq~++J|ZApi-UN}x{BCzf>L-iLd0=>Z(aRINnaRkA^8jEV>R%_<@g5k9)%1`Ctr@nu zM9lg(@bmmf2=dylblY1P0Q_Z-{uhHr&*^l)_}%n&3lA+677oB!{SPr*F1&wEa1e3U z_;qm^K?p>D821a%L;3ey{TiCqWBPa};+#4KJM~ZEu-ke{ACF=mYyDyRxUmBtUHT~P z#K%w4$1Av;w*E4Ge3w4HO&?8M!Bel($KRz6{tkV75=XGrQ~GGqKy~_$a(Z_!JVK04D>BGlIH=QPE={f{~1p)7hfOSQ{xgua(5%8@D*j5BwD*~n!0ndtn z1?>R>o}k+mG5(4edqs@9BF0?l);v&IAfz@cuu)r(sG!RRBr3}Emq5ibVMd_hLxdTD ziV9&ypn@(GmZ+d>FeNJJ<^+ifI=ED#f_z7b3fhq^Q9%V#5*3sO5~vW-X*bM=pj zeH9hbk?xdF$l7o_DTn40*$(;~+N`-6H8RyGn%?0&%vw)dJx=qe;-%ZI{^2-u67p2; wbo)}j+?MWvEzFwjM|=nq0#2vv8Dxi<$+I5s%^nM#gR7w6%_@T>ox-L64`5cyhX4Qo literal 0 HcmV?d00001 diff --git a/_sources/assumptions.md.txt b/_sources/assumptions.md.txt new file mode 100644 index 000000000..0213502e3 --- /dev/null +++ b/_sources/assumptions.md.txt @@ -0,0 +1,8 @@ +# List of assumptions made during development + +- RF has data forwarding from the Tomasulo announcement bus +- read of `x0`/`RF0` returns 0 +- write to `x0`/`RF0` is a noop +- separate RS for each FU +- the writeback stage saves data to the RF and the ROB (after getting output data from FUs) +- the commit stage updates the R-RAT diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index ba5e34071..8120dbad2 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -6,18 +6,18 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] - WishboneMaster_WishboneMaster["WishboneMaster"] - WishboneMaster_request["request"] WishboneMaster_result["result"] + WishboneMaster_request["request"] + WishboneMaster_WishboneMaster["WishboneMaster"] subgraph Forwarder["result Forwarder"] Forwarder_read["read"] Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_result["result"] WishboneMaster1_request["request"] WishboneMaster1_WishboneMaster["WishboneMaster"] + WishboneMaster1_result["result"] subgraph Forwarder1["result Forwarder"] Forwarder1_read["read"] Forwarder1_write["write"] @@ -32,19 +32,19 @@ BasicFifo_read["read"] end subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"] - SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] SimpleWBCacheRefiller_start_refill["start_refill"] SimpleWBCacheRefiller_accept_refill["accept_refill"] + SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] subgraph Forwarder2["address_fwd Forwarder"] Forwarder2_write["write"] Forwarder2_read["read"] end end subgraph ICache["icache ICache"] - ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] ICache_ICache["ICache"] ICache_ICache1["ICache"] + ICache_accept_res["accept_res"] + ICache_issue_req["issue_req"] ICache_ICache2["ICache"] subgraph FIFO1["req_fifo FIFO"] FIFO1_read["read"] @@ -56,8 +56,8 @@ end end subgraph Fetch["fetch Fetch"] - Fetch_Fetch["Fetch"] Fetch_verify_branch["verify_branch"] + Fetch_Fetch["Fetch"] Fetch_Fetch1["Fetch"] subgraph BasicFifo1["fetch_target_queue BasicFifo"] BasicFifo1_write["write"] @@ -71,21 +71,21 @@ RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] - RegisterFile_free["free"] RegisterFile_read2["read2"] + RegisterFile_free["free"] RegisterFile_write["write"] + RegisterFile_read1["read1"] end subgraph ReorderBuffer["ROB ReorderBuffer"] ReorderBuffer_mark_done["mark_done"] ReorderBuffer_peek["peek"] + ReorderBuffer_retire["retire"] ReorderBuffer_get_indices["get_indices"] ReorderBuffer_put["put"] - ReorderBuffer_retire["retire"] end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_report["report"] end subgraph FuncBlocksUnifier["func_blocks_unifier FuncBlocksUnifier"] subgraph Collector["result_collector Collector"] @@ -107,23 +107,23 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] + RSFuncBlock_insert["insert"] RSFuncBlock_update["update"] RSFuncBlock_select["select"] RSFuncBlock_get_result["get_result"] - RSFuncBlock_insert["insert"] subgraph RS["rs RS"] RS_update["update"] + RS_take["take"] RS_RS["RS"] RS_RS1["RS"] - RS_take["take"] - RS_insert["insert"] - RS_select["select"] RS_RS2["RS"] + RS_insert["insert"] RS_RS3["RS"] + RS_select["select"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] - AluFuncUnit_accept["accept"] AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] subgraph FIFO2["fifo FIFO"] FIFO2_read["read"] FIFO2_write["write"] @@ -133,11 +133,11 @@ WakeupSelect_WakeupSelect["WakeupSelect"] end subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] - ShiftFuncUnit_issue["issue"] ShiftFuncUnit_accept["accept"] + ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] - FIFO3_read["read"] FIFO3_write["write"] + FIFO3_read["read"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] @@ -148,8 +148,8 @@ JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] subgraph FIFO4["fifo_res FIFO"] - FIFO4_write["write"] FIFO4_read["read"] + FIFO4_write["write"] end subgraph FIFO5["fifo_branch FIFO"] FIFO5_read["read"] @@ -163,8 +163,8 @@ ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] subgraph FIFO6["fifo FIFO"] - FIFO6_write["write"] FIFO6_read["read"] + FIFO6_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] @@ -193,21 +193,21 @@ end end subgraph LSUDummy["rs_block_1 LSUDummy"] - LSUDummy_update["update"] - LSUDummy_get_result["get_result"] LSUDummy_insert["insert"] LSUDummy_LSUDummy["LSUDummy"] - LSUDummy_precommit["precommit"] + LSUDummy_get_result["get_result"] LSUDummy_select["select"] LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_precommit["precommit"] LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_update["update"] subgraph Forwarder6["forwarder Forwarder"] Forwarder6_write["write"] Forwarder6_read["read"] end subgraph LSURequesterWB["requester LSURequesterWB"] - LSURequesterWB_accept["accept"] LSURequesterWB_issue["issue"] + LSURequesterWB_accept["accept"] end end end @@ -243,8 +243,8 @@ end end subgraph FIFO7["fifo_decode FIFO"] - FIFO7_write["write"] FIFO7_read["read"] + FIFO7_write["write"] end subgraph Decode["decode Decode"] Decode_Decode["Decode"] @@ -258,8 +258,8 @@ RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO9["rename_out_buf FIFO"] - FIFO9_read["read"] FIFO9_write["write"] + FIFO9_read["read"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] @@ -298,8 +298,8 @@ subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister5["register_low CSRRegister"] - CSRRegister5_write["write"] CSRRegister5_read["read"] + CSRRegister5_write["write"] end subgraph CSRRegister6["register_high CSRRegister"] CSRRegister6_read["read"] @@ -330,9 +330,9 @@ WishboneMaster1_WishboneMaster --> Forwarder1_write Forwarder2_read --> SimpleWBCacheRefiller_SimpleWBCacheRefiller SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request - ICache_ICache1 --> Forwarder3_write - ICache_ICache2 --> SimpleWBCacheRefiller_start_refill - ICache_ICache2 --> Forwarder2_write + ICache_ICache2 --> Forwarder3_write + ICache_ICache1 --> SimpleWBCacheRefiller_start_refill + ICache_ICache1 --> Forwarder2_write ICache_ICache --> Forwarder2_write SimpleWBCacheRefiller_accept_refill --> ICache_ICache WishboneMaster_result --> ICache_ICache @@ -358,15 +358,15 @@ FIFO9_read --> ROBAllocation_ROBAllocation ROBAllocation_ROBAllocation --> ReorderBuffer_put ROBAllocation_ROBAllocation --> FIFO10_write - FIFO10_read --> RSSelection_RSSelection1 - RSSelection_RSSelection1 --> Forwarder7_write + FIFO10_read --> RSSelection_RSSelection2 + RSSelection_RSSelection2 --> Forwarder7_write Forwarder7_read --> RSSelection_RSSelection - Forwarder7_read --> RSSelection_RSSelection2 + Forwarder7_read --> RSSelection_RSSelection1 RSFuncBlock_select --> RSSelection_RSSelection RS_select --> RSSelection_RSSelection RSSelection_RSSelection --> FIFO11_write - RSSelection_RSSelection2 --> FIFO11_write - RSSelection_RSSelection2 <--> LSUDummy_select + RSSelection_RSSelection1 --> FIFO11_write + RSSelection_RSSelection1 <--> LSUDummy_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -385,17 +385,17 @@ ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update - RS_RS1 --> WakeupSelect_WakeupSelect + RS_RS3 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect RS_take --> WakeupSelect3_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO2_write - RS_RS --> WakeupSelect1_WakeupSelect + RS_RS2 --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO3_write - RS_RS3 --> WakeupSelect2_WakeupSelect + RS_RS1 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect --> ExceptionCauseRegister_report WakeupSelect3_WakeupSelect --> ExceptionCauseRegister_report @@ -405,7 +405,7 @@ ReorderBuffer_get_indices --> ConnectTrans1_ConnectTrans WakeupSelect2_WakeupSelect --> FIFO4_write WakeupSelect2_WakeupSelect --> FIFO5_write - RS_RS2 --> WakeupSelect3_WakeupSelect + RS_RS --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO6_write ConnectTrans2_ConnectTrans --> Forwarder5_write @@ -420,14 +420,14 @@ FIFO4_read --> ConnectTrans4_ConnectTrans ExceptionFuncUnit_accept --> ConnectTrans5_ConnectTrans FIFO6_read --> ConnectTrans5_ConnectTrans - LSUDummy_LSUDummy --> LSURequesterWB_issue - LSUDummy_LSUDummy --> WishboneMaster1_request + LSUDummy_LSUDummy2 --> LSURequesterWB_issue + LSUDummy_LSUDummy2 --> WishboneMaster1_request + LSUDummy_LSUDummy2 --> Forwarder6_write LSUDummy_LSUDummy --> Forwarder6_write LSUDummy_LSUDummy1 --> Forwarder6_write - LSUDummy_LSUDummy2 --> Forwarder6_write - LSURequesterWB_accept --> LSUDummy_LSUDummy2 - WishboneMaster1_result --> LSUDummy_LSUDummy2 - Forwarder1_read --> LSUDummy_LSUDummy2 + LSURequesterWB_accept --> LSUDummy_LSUDummy1 + WishboneMaster1_result --> LSUDummy_LSUDummy1 + Forwarder1_read --> LSUDummy_LSUDummy1 ConnectTrans_ConnectTrans --> Forwarder4_write ConnectTrans1_ConnectTrans --> Forwarder4_write RSFuncBlock_get_result --> ConnectTrans_ConnectTrans diff --git a/_sources/current-graph.md.txt b/_sources/current-graph.md.txt new file mode 100644 index 000000000..c176682f2 --- /dev/null +++ b/_sources/current-graph.md.txt @@ -0,0 +1,12 @@ +# Full transaction-method graph + +
+
+ + ```{eval-rst} + .. include:: auto_graph.rst + + ``` + +
+
diff --git a/_sources/development-environment.md.txt b/_sources/development-environment.md.txt new file mode 100644 index 000000000..cfdb58cad --- /dev/null +++ b/_sources/development-environment.md.txt @@ -0,0 +1,78 @@ +# Development environment + +## Setting up + +In order to prepare the development environment, please follow the steps below: + +1. Install the Python 3.11 interpreter and pip package manager. + * Optionally create a Python virtual environment with `python3 -m venv venv` in the project directory and activate it using generated script: `. venv/bin/activate`. +2. Install all required libraries with `pip3 install -r requirements-dev.txt`. +3. Install `riscv64-unknown-elf` binutils using your favourite package manager. On Debian-based distros the package is called `binutils-riscv64-unknown-elf`, on Arch-based - `riscv64-unknown-elf-binutils`. +4. Optionally, install all precommit hooks with `pre-commit install`. This will automatically run the linter before commits. + +## Using scripts + +The development environment contains a number of scripts which are run in CI, but are also intended for local use. They are: + +### run\_tests.py + +Runs the unit tests. By default, every available test is run. Tests from a specific file can be run using the following call (`test_transactions` is used as an example): + +``` +scripts/run_tests.py test_transactions +``` + +One can even run a specific test class from a file: + +``` +scripts/run_tests.py test_transactions.TestScheduler +``` + +Or a specific test method: + +``` +scripts/run_tests.py test_transactions.TestScheduler.test_single +``` + +The argument to `run_tests.py` is actually used to search within the full names of tests. The script runs all the tests which match the query. Thanks to this, if a given test class name is unique, just the class name can be used as an argument. + +The `run_tests.py` script has the following options: + +* `-l`, `--list` -- lists available tests. This option is helpful, e.g., to find a name of a test generated using the `parameterized` package. +* `-t`, `--trace` -- generates waveforms in the `vcd` format and `gtkw` files for the `gtkwave` tool. The files are saved in the `test/__traces__/` directory. Useful for debugging and test-driven development. +* `-v`, `--verbose` -- makes the test runner more verbose. It will, for example, print the names of all the tests being run. + +### lint.sh + +Checks the code formatting and typing. It should be run as follows: + +``` +scripts/lint.sh subcommand [filename...] +``` + +The following main subcommands are available: + +* `format` -- reformats the code using `black`. +* `check_format` -- verifies code formatting using `black` and `flake8`. +* `check_types` -- verifies typing using `pyright`. +* `verify` -- runs all checks. The same set of checks is run in CI. + +When confronted with `would reformat [filename]` message from `black` you may run: + +``` +black --diff [filename] +``` +This way you may display the changes `black` would apply to `[filename]` if you chose the `format` option for `lint.sh` script. This may help you locate the formatting issues. + +### core\_graph.py + +Visualizes the core architecture as a graph. The script outputs a file in one of supported graph formats, which need to be passed to an appropriate tool to get a graph. + +The `core_graph.py` script has the following options: + +* `-p`, `--prune` -- removes disconnected nodes from the output graph. +* `-f FORMAT`, `--format FORMAT` -- selects the output format. Supported formats are `elk` (for [Eclipse Layout Kernel](https://www.eclipse.org/elk/)), `dot` (for [Graphviz](https://graphviz.org/)), `mermaid` (for [Mermaid](https://mermaid.js.org/)). + +### build\_docs.sh + +Generates local documentation using [Sphinx](https://www.sphinx-doc.org/). The generated HTML files are located in `build/html`. diff --git a/_sources/home.md.txt b/_sources/home.md.txt new file mode 100644 index 000000000..79c4df96a --- /dev/null +++ b/_sources/home.md.txt @@ -0,0 +1,36 @@ +# Introduction + +CoreBlocks is going to be an out-of-order processor which will implement a RISC-V microarchitecture. +The project will focus on flexibility, which should allow to easily make experiments with different +component implementations. + +## Documentation + +Documentation located in the `docs/` directory collects description of the whole processor. +In `Overview` a high level overview of CoreBlocks can be found. + +Html versions of these pages and API documentation generated from code are available at [kuznia-rdzeni.github.io/coreblocks/](https://kuznia-rdzeni.github.io/coreblocks/) + + +```{mermaid} +graph + F[FRONTEND
-get instruction
-decode] + F -->|FIFO| S + S[SCHEDULER
-allocate register
-rename
-allocate ROB
-send to RS] + S --RS--> E + E[EXEC
-listen to incoming operands
-select instruction to execute
-send to FU
-deallocate RS] + E --FU--> B + B[BACKEND
-listen for results from FU
-announce results to RF and RS
-mark done in ROB] + B --> R + R[RETIREMENT
-check rediness of instruction from the end of ROB
-update RAT
-deallocate old register
-deallocate ROB] + + ROB((ROB)) + RF((RF)) + FREE_RF((FREE RF)) + RAT((RAT)) + + R --> FREE_RF --> S + S & R & B <--> ROB + B --> RF --> S + S <--> RAT <--> R +``` diff --git a/_sources/index.md.txt b/_sources/index.md.txt index 85d7b3e2c..0e16a25ec 100644 --- a/_sources/index.md.txt +++ b/_sources/index.md.txt @@ -5,17 +5,17 @@ maxdepth: 3 --- -Home.md -Assumptions.md -Development_environment.md -Transactions.md -scheduler/Overview.md -shared_structs/Implementation/RS_impl.md -shared_structs/RS.md -Current_graph.md -Problem-checklist.md -synthesis/Synthesis.md +home.md +assumptions.md +development-environment.md +transactions.md +scheduler/overview.md +shared-structs/implementation/rs-impl.md +shared-structs/rs.md +current-graph.md +problem-checklist.md +synthesis/synthesis.md components/icache.md -miscellany/exceptionsSummary.md +miscellany/exceptions-summary.md api.md ``` diff --git a/_sources/miscellany/exceptions-summary.md.txt b/_sources/miscellany/exceptions-summary.md.txt new file mode 100644 index 000000000..cde39753d --- /dev/null +++ b/_sources/miscellany/exceptions-summary.md.txt @@ -0,0 +1,153 @@ +# Summary of papers about interrupts + +## Introduction + +This summary is a result of analysis of journal articles which I made as a preparation to implement support for +interrupts, exceptions and speculation to core blocks. It looks like the choice of primary interrupts related to +structure determines the interrupt handling procedure. We have chosen a ROB, so there is a one classical implementation +of the ROB interrupt handling procedure. This procedure is used as a basis for the improvements, but most of the papers +are pretty old (1993-2001). Currently there is no much research going on about CPU interrupt handling and it is +considered that this problem is solved. Instead of that, there are some works, which try to implement precise interrupts +on GPUs, but due to different characteristics of the CPU and GPU, this research can not be applied in an easy way to our +project. + +When I have prepared this overview, I have decided to look at articles from different times to check on what people were +working at that time. So there is probably a lot of other works which can be worth checking out. Specifically: +- W. Walker and H. G. Cragon. “Interrupt processing in concurrent processors.” IEEE Computer, vol. 28, no. 6, June 1995 +- M. Moudgill and S. Vassiliadis. “Precise interrupts.” IEEE Micro, vol. 16, no. 1, pp. 58–67, February 1996 +These two works present a survey of the topic of interrupts as a time of writing. + +## Interrupt handling in old PCs + +- CDC 6600 - interrupt handling is done by inserting a jump instruction into the interrupt handler +- IBM360 - stop fetching and wait for all fetched instructions to be committed, then jump to interrupt handler +- CRAY-1 - similar to IBM360, but here latency can be even bigger due to vector instructions + +## Interrupt Handling for Out-of-Order Execution Processors + +> Interrupt Handling for Out-of-Order Execution Processors +> H. C. Torng and Martin Day, 1993 + +This article describes one of the first probes for the implementation of exceptions in out-of-order processes. In that +time, ROB was a very new idea. The authors of this paper introduced Instruction Window (IW) as their proposition for the +implementation of interrupts in out-of-order processors. IW will store all dispatched instructions, which didn't +complete. In the case of an interrupt it will be a part of the context and will be copied to memory by the interrupt handler. +After restoring the context, all instructions from IW will be restarted so that the state of the CPU will be precise. + +The idea of IW is similar to that of ROB, but there are few differences: +- ROB is not a part of the context +- ROB removes instructions in-order, IW allows to remove instructions out-of-order +- Tags in IW are one-hot-encoded, which will in current implementation cause big overhead. + +So in its original form, IW is unfeasible for our processor, because it would require to double a job. Additionally, +this context of the ROB size will have to be stored on each entry to the interrupt handler, which can be costly +operations. But: +- maybe it is possible to reduce cost of IW saving by cooperation of CPU and OS? +- maybe cost of restoring IW is smaller than cost of re-fetching and scheduling one more time for old instructions? + +Some interesting ideas from the paper: +- they propose NRP (No Return Point) implementation - a point in the pipeline after which an instruction can be removed, + it should allow instructions which are ending to save its results and remove itself from IW, to don't waste cycles on + context restore for executing this instruction one more time, NRP can be implemented for different interrupts and + instructions in different places to allow different interrupt latency +- for vector instructions IW remember how many elements are left to be processed, so after this context restore allows + to restore vector operation in the middle of the vector + + +## In-Line Interrupt Handling for Software-Managed TLBs + +> In-Line Interrupt Handling for Software-Managed TLBs +> Aamer Jaleel and Bruce Jacob, 2001 + +In that time, ROB was already a standard, so there was "classic" interrupt handling procedure. But in that time +there is still a lot of software managed TLBs, which cause an interrupt on each page miss. This of course causes a big +context switch overhead, so the authors of this paper try to reduce this penalty. As a base architecture they use Alpha and MIPS. They +concentrate on improving TLB miss efficiency and this has a property that interrupt handlers are very short (10-30 +instructions). + +The main idea is to not flush the whole pipeline on an interrupt, but instead to inline a handler code between +instructions of the user space program. They observed that the most important problem is that there can not be enough +resources to execute the interrupt handler without flushing the pipeline (e.g. in case when ROB is full there can be +live-lock). +- they assume that interrupt handler has known length +- they check if ROB, RS and RF have enough free resources to inline handler +- if the handler can be inlined, they do that, else they flush the pipeline +- in fly instruction return instruction is swapped to NOP and excepted instruction is reexecuted +- each executed instruction has one connected bit indicating the privilege level + +They use some properties of the Alpha and MIPS architectures where they have interrupts vectors so the OS can insert +short, specific, handlers to correct the interrupt vector addresses. In contrast to that in current design it is a +tendency to have one interrupt handler in OS, which next decides which handling functions should be invoked. This makes +the handler longer, so it can be hard to make inlining (e.g. for risk V in Linux the first step is to save +each of general purpose registers, so on the start we have already 32 instructions in handler) + +Ideas from the paper: +- Pipelines don't have to be flushed +- Additional HW resources reserved for only privileged mode can allow to execute privileged instruction without boring + with stopping user space program +- Interrupts and exceptions can be treated as branches and can be speculated + + +## Hardware/software cost analysis of interrupt processing strategies: + +> Hardware/software cost analysis of interrupt processing strategies +> Mansur H. Samadzadeh, Loai E. Garalnabi, 2001 + +Present overview for all main structures to handle exceptions, so: +- Instruction Window +- Checkpoint repair +- History file +- Reorder buffer +- Future file + +## iGPU: Exception Support and Speculative Execution on GPUs + +> iGPU: Exception Support and Speculative Execution on GPUs Jaikrishnan Menon, Marc de Kruijf, Karthikeyan +> Sankaralingam, 2012 + +They try to introduce exceptions to GPU. To do that, they observe that: +- it is possible to find points where it is low number of live registers (e.g., boundaries of kernels) +- GPU execution has no side effects, so it can be safely rewritten +- GPU program can be recompiled in runtime + +They introduce to the GPU program regions and subregions. Regions are parts of code which start at the beginning and end +with a small number of live registers. Subregion is a part of a region which has short length (not more than 32 +instructions). In each subregion there is no instruction which overrides the output of the instruction from the previous +subregion. Each subregion end is an instruction barrier. + +Exceptions and interrupts are handled by restarting execution of warp from the beginning of region. Wrong speculation is +handled by restarting execution of current subregion. In case when there are two exceptions in region, code is +dynamically recompiled and split into two regions to prevent live-locks. + + +## Efficient Exception Handling Support for GPUs + +> Efficient Exception Handling Support for GPUs +> Ivan Tanasic, Isaac Gelado, Marc Jorda, Eduard Ayguade, Nacho Navarro, 2017 + +One more time it is analysed the problem of precise interrupts for GPU. They observe that the only problematic +instructions are those related to memory access. All other instructions are guaranteed to end successfully or they kill +the program. This time there is more hardware modification and there are presented three propositions: +- stall warp until previous global load is solved - on GPU it is not so problematic because usually there is a lot of + other warp which wait to be executed. +- save instructions which can fail (global loads) to next reply them, input registers are not allowed to be + modified until this instruction don't claim that it doesn't fail +- operand logging - replay queue + storing operations + + +## Others + +> Reducing Exception Management Overhead with Software Restart Markers +> Mark Jerome Hampton, 2008 + +Mention a paper of Alli and Bailey [AB04] where there is no ROB. Instead of that in RAT there are FIFO-s which store +mapping between physical and logical registers and the age of instruction. If there is a need to raise an exception it +is checked if all younger instruction have already ended if not an exception wait for some cycles and repeat the check. + + +## Summary + +GPU research don't help us much, because the main assumption is that operations don't cause side effects +except of communication with main memory by load/store instructions. From research about CPUs, it looks like, +there is a "canonical" implementation of ROB that can be eventually introduced some small improvements, but +there aren't any very different procedures. diff --git a/_sources/problem-checklist.md.txt b/_sources/problem-checklist.md.txt new file mode 100644 index 000000000..122632544 --- /dev/null +++ b/_sources/problem-checklist.md.txt @@ -0,0 +1,15 @@ +# Problem checklist + +If something doesn't work and you're puzzled as to why - go through this checklist to see if any of these points apply in your case: + +1. Make sure that you use `yield from` when calling generator functions in tests - e.g. `TestbenchIO` functions (notable exception: `yield Settle()` instead of `yield from Settle()`) + +2. If a signal has an unexpected value in tests try adding `yield Settle()` right before you read it. + +3. Make sure you don't do `.eq` on two records with different layouts. Use `assign` from `coreblocks.utils` instead. + +4. Make sure all amaranth statements are added to some domain. + +5. Check if your code doesn't have any combinational loops - especially if your simulation hangs. + +Please extend this list if you spot yourself doing an easy-to-fix mistake. diff --git a/_sources/scheduler/overview.md.txt b/_sources/scheduler/overview.md.txt new file mode 100644 index 000000000..10e587547 --- /dev/null +++ b/_sources/scheduler/overview.md.txt @@ -0,0 +1,46 @@ +# Scheduler overview + +## Description + +The scheduler is the middle part of our processor. +It is located after the frontend and before execution units. +Its main tasks are: + +- register allocation +- renaming +- ROB entry allocation +- dispatching instructions to RSs + + +## Schema + +```{mermaid} +graph + Reg; + Reg[REGISTER ALLOCATION
-get free register from FREE RF list] + Reg --> Rename; + Rename[RENAMING
-rename source registers using F-RAT
-save mapping to allocated output register in F-RAT] + Rename --> AlocRob; + AlocRob[ROB ALLOCATION
-get ID of free entry in ROB
-save instruction in ROB entry] + AlocRob --> Select; + Select[RS SELECTION
-choose RS to which instruction should be send
-reserve entry in that RS] + Select --> Insert; + Insert[RS INSERTION
-insert instruction to selected RS
-get operands from RF
-save them in RS field of new instruction] +``` + +## Structure + +We decided to split the scheduler into 5 phases: +- register allocation +- renaming +- ROB entry allocation +- choosing the RS to which instruction should be dispatched +- inserting instruction to RS + +Each phase can potentially take one clock cycle, but they can be merged as a potential future optimization. +During implementation each phase should be treated as a separate hardware block for future flexibility. + + +## More detailed description of each block + +TODO diff --git a/_sources/shared-structs/implementation/rs-impl.md.txt b/_sources/shared-structs/implementation/rs-impl.md.txt new file mode 100644 index 000000000..80e29b0e6 --- /dev/null +++ b/_sources/shared-structs/implementation/rs-impl.md.txt @@ -0,0 +1,110 @@ +# Proposition of Reservation Station implementation + +Here is an example proposition how to implement RS using transaction framework for internal communication. If you want +you can follow this proposition, if you don't, feel free to change anything you want. + + +## Internal data + +### Actual Reservation Station + +This is a buffer which has `R` rows. Each row has the following structure: + +|v|opcode|`id_out`|`id_ROB`|`id_rs1`|`val_rs1`|`id_rs2`|`val_rs2`| +|-|------|--------|--------|--------|---------|--------|---------| + +- `v` - "valid" - it is 1 if entry is a correct instruction which waits to be filled with operands/dispatched +- `id_rsX` - is 0 when the source value is ready (and is stored in the appropriate `val_rsX`) or not needed. It is + non-zero when we wait for an operand to be ready. +- When the operand is ready we insert it to the appropriate `val_rsX` field and we put zero to `id_rsX` +- The instruction is ready to be dispatched if `v` is `1` and both `id_rs1`, `id_rs2` are `0` + +### Used slots table + +It is a table with `R` one-bit fields. Each field is `1` if this slot is used or is reserved to be used in the near +future (there is instruction in pipeline which will be saved to this slot). + +When an entry in the RS is released, the corresponding entry in this table is switched from `1` to `0`. + + +## Internal methods + +### Compare and substitute + +Input: +- `tag` - identifier of field in RF which should be compared with `id_rsX` to check if there is need to store `value` +- `value` - value which should be stored in RS field if tag matches +- `position` - position in RS on which comparison and replacement should take place + +Output: +- *null* + +Side effects: +- When `tag` matches one of `id_rsX` saved in RS on `position` then `id_rsX` is cleared (set to 0) and `value` is saved + in `val_rsX` + +### Read row + +Input: +- `position` - which RS row should be read + +Output: +- `opcode` - instruction opcode for FU +- `val_rs1` - value of first operand +- `val_rs2` - value of second operand +- `id_out` - id of RF field where instruction output should be stored +- `id_ROB` - id of ROB entry which is allocated for this instruction + +Side effects: +- *null* + +### Clean row + +Input: +- `position` - RS row which should be cleaned + +Output: +- *null* + +Side effects: +- `v` bit for entry on `position` set to `0` + +### Get free slot + +Input: +- *null* + +Output: +- `position` - of the free slot in the RS + +Side effects: +- *null* + +### Mark slot as used + +Input: +- `position` - of slot which should be marked as used + +Output: +- *null* + +Side effects: +- `position` slot in RS marked as used + + + +## Proposition of implementation of external interfaces + +### Get slot and mark as used + +["Get free slot"](#get-free-slot) position and call ["Mark slot as used"](#mark-slot-as-used) with it. + + +### Compare and substitute all + +Invokes ["Compare and substitute"](#compare-and-substitute) for each row of RS. + + +### Read and clean row + +For given row `r` atomically ["Read row"](#read-row) and ["Clean row"](#clean-row) diff --git a/_sources/shared-structs/rs.md.txt b/_sources/shared-structs/rs.md.txt new file mode 100644 index 000000000..e264a962b --- /dev/null +++ b/_sources/shared-structs/rs.md.txt @@ -0,0 +1,91 @@ +# Reservation Station + +## Overview + +The reservation station is used to store instructions which wait for their operands to be ready. When the instruction +is ready it should be woken up by wakeup logic and dispatched to the correct FU. + +### Reset / Initial state + +In initial state all rows are marked as invalid. + + +## External interface methods + +### Get slot and mark as used + +Input: +- *null* + +Output: +- `position` - of a free slot in RS + +Side effects: +- Slot on `position` marked as used + + +### Insert new instruction + +Input: +- `opcode` - instruction opcode for FU +- `id_rs1` - id of RF field where `src1` should be stored +- `id_rs2` - id of RF field where `src2` should be stored +- `id_out` - id of RF field where instruction output should be stored +- `id_ROB` - id of ROB entry which is allocated for this instruction +- `position` - in the RS to which we should write this entry + +Output: +- *null* + +Side effects: +- Save data from input to the slot in RS specified by the `position` argument + +---- + +### Get ready vector + +Input: +- *null* + +Output: +- `inst_ready` - bit vector as long as RS, where bit on `position` mean: + - 0 - instruction is still waiting for arguments + - 1 - instruction is ready for execute + +Side effects: +- *null* + +### Read and clean row + +Input: +- `position` - of RS row which should be read and cleared + +Output: +- `opcode` - instruction opcode for FU +- `val_rs1` - value of first operand +- `val_rs2` - value of second operand +- `id_out` - id of RF field where instruction output should be stored +- `id_ROB` - id of ROB entry which is allocated for this instruction + +Side effects: +- RS row on `position` marked as invalid + +---- + +### Compare and substitute all + +Input: +- `tag` - from RF for which RS should be checked for +- `value` - value which should be written to fields of RS with matching tag + +Output: +- *null* + +Side effects: +- For each row of RS if in this row are fields tagged with `tag` store + `value` in these fields. + + +## External interface signals + +- `free`: one-bit signal indicating if there is a free slot in the RS diff --git a/_sources/synthesis/synthesis.md.txt b/_sources/synthesis/synthesis.md.txt new file mode 100644 index 000000000..7f3112be1 --- /dev/null +++ b/_sources/synthesis/synthesis.md.txt @@ -0,0 +1,49 @@ +# Synthesis + +CoreBlocks synthesizes `Core` circuit to test how many resources it consumes as the project +grows and more functionalities are added. + +## Documentation + +### Requirements + +In order to perform synthesis you will need to install following tools: + * [yosys](https://github.com/YosysHQ/yosys) + * [prjtrellis](https://github.com/YosysHQ/prjtrellis) + * [nextpnr-ecp5](https://github.com/YosysHQ/nextpnr.git) + +These tools may need manual compilation from git repository, that can take some time. + +You can use docker images that have installed all required tools to perform synthesis: + * [vuush/amaranth-synth:ecp5](https://hub.docker.com/r/vuush/amaranth-synth/tags) + +To build the `AmaranthSynthECP5.Dockerfile` yourself use following command: +``` +docker build --platform linux/amd64 -t "amaranth-synth:ecp5" -f ./docker/AmaranthSynthECP5.Dockerfile . +``` + +### Usage + +Script named `synthesize.py` is used to perform the `Core` synthesis. + +Example usage: +``` +./scripts/synthesize.py --help +./scripts/synthesize.py --platform ecp5 --verbose +``` + +To collect synthesis information we use script named `parse_benchmark_info.py`. + +This script parses the output of the synthesis tool and extracts the +following information: + - Max clock frequency + - Number of logic cells used + - Number of carry cells used + - Number of RAM cells used + - Number of DFF cells used + +## Benchmarks + +For each commit on `master` branch, CI runs the synthesis and saves the parameters collected by `parse_benchmark_info` script. + +Graphs generated from this information are available on a dedicated [subpage](https://kuznia-rdzeni.github.io/coreblocks/dev/benchmark/). diff --git a/_sources/transactions.md.txt b/_sources/transactions.md.txt new file mode 100644 index 000000000..41b5d5528 --- /dev/null +++ b/_sources/transactions.md.txt @@ -0,0 +1,336 @@ +# Documentation for Coreblocks transaction framework + +## Introduction + +Coreblocks utilizes a transaction framework for modularizing the design. +It is inspired by the [Bluespec](http://bluespec.com/) programming language (see: [Bluespec wiki](http://wiki.bluespec.com/), [Bluespec compiler](https://github.com/B-Lang-org/bsc)). + +The basic idea is to interface hardware modules using _transactions_ and _methods_. +A transaction is a state-changing operation performed by the hardware in a single clock cycle. +Transactions are atomic: in a given clock cycle, a transaction either executes in its entriety, or not at all. +A transaction is executed only if it is ready for execution and it does not _conflict_ with another transaction scheduled for execution in the same clock cycle. + +A transaction defined in a given hardware module can depend on other hardware modules via the use of methods. +A method can be _called_ by a transaction or by other methods. +Execution of methods is directly linked to the execution of transactions: a method only executes if some transaction which calls the method (directly or indirectly, via other methods) is executed. +If multiple transactions try to call the same method in the same clock cycle, the transactions conflict, and only one of them is executed. +In this way, access to methods is coordinated via the transaction system to avoid conflicts. + +Methods can communicate with their callers in both directions: from caller to method and back. +The communication is structured using Amaranth records. + +## Basic usage + +### Implementing transactions + +The simplest way to implement a transaction as a part of Amaranth `Elaboratable` is by using a `with` block: + +```python +class MyThing(Elaboratable): + ... + + def elaborate(self, platform): + m = TModule() + + ... + + with Transaction().body(m): + # Operations conditioned on the transaction executing. + # Including Amaranth assignments, like: + + m.d.comb += sig1.eq(expr1) + m.d.sync += sig2.eq(expr2) + + # Method calls can also be used, like: + + result = self.method(m, arg_expr) + + ... + + return m +``` + +The transaction body `with` block works analogously to Amaranth's `with m.If():` blocks: the Amaranth assignments and method calls only "work" in clock cycles when the transaction is executed. +This is implemented in hardware via multiplexers. +Please remember that this is not a Python `if` statement -- the *Python code* inside the `with` block is always executed once. + +### Implementing methods + +As methods are used as a way to communicate with other `Elaboratable`s, they are typically declared in the `Elaboratable`'s constructor, and then defined in the `elaborate` method: + +```python +class MyOtherThing(Elaboratable): + def __init__(self): + ... + + # Declaration of the method. + # The i/o parameters pass the format of method argument/result as Amaranth layouts. + # Both parameters are optional. + + self.my_method = Method(i=input_layout, o=output_layout) + + ... + + def elaborate(self, platform): + # A TModule needs to be used instead of an Amaranth module + + m = TModule() + + ... + + @def_method(m, self.my_method) + def _(arg): + # Operations conditioned on the method executing. + # Including Amaranth assignments, like: + + m.d.comb += sig1.eq(expr1) + m.d.sync += sig2.eq(expr2) + + # Method calls can also be used, like: + + result = self.other_method(m, arg_expr) + + # Method result should be returned: + + return ret_expr + + ... + + return m +``` + +The `def_method` technique presented above is a convenience syntax, but it works just like other Amaranth `with` blocks. +In particular, the *Python code* inside the unnamed `def` function is always executed once. + +A method defined in one `Elaboratable` is usually passed to other `Elaboratable`s via constructor parameters. +For example, the `MyThing` constructor could be defined as follows. +Only methods should be passed around, not entire `Elaboratable`s! + +```python +class MyThing(Elaboratable): + def __init__(self, method: Method): + self.method = method + + ... + + ... +``` + +### Method or transaction? + +Sometimes, there might be two alternative ways to implement some functionality: + +* Using a transaction, which calls methods on other `Elaboratable`s. +* Using a method, which is called from other `Elaboratable`s. + +Deciding on a best method is not always easy. +An important question to ask yourself is -- is this functionality something that runs independently from other things (not in lock-step)? +If so, maybe it should be a transaction. +Or is it something that is dependent on some external condition? +If so, maybe it should be a method. + +If in doubt, methods are preferred. +This is because if a functionality is implemented as a method, and a transaction is needed, one can use a transaction which calls this method and does nothing else. +Such a transaction is included in the library -- it's named `AdapterTrans`. + +### Method argument passing conventions + +Even though method arguments are Amaranth records, their use can be avoided in many cases, which results in cleaner code. +Suppose we have the following layout, which is an input layout for a method called `method`: + +```python +layout = [("foo", 1), ("bar", 32)] +method = Method(input_layout=layout) +``` + +The method can be called in multiple ways. +The cleanest and recommended way is to pass each record field using a keyword argument: + +```python +method(m, foo=foo_expr, bar=bar_expr) +``` + +Another way is to pass the arguments using a `dict`: + +```python +method(m, {'foo': foo_expr, 'bar': bar_expr}) +``` + +Finally, one can directly pass an Amaranth record: + +```python +rec = Record(layout) +m.d.comb += rec.foo.eq(foo_expr) +m.d.comb += rec.bar.eq(bar_expr) +method(m, rec) +``` + +The `dict` convention can be used recursively when layouts are nested. +Take the following definitions: + +```python +layout2 = [("foobar", layout), ("baz", 42)] +method2 = Method(input_layout=layout2) +``` + +One can then pass the arguments using `dict`s in following ways: + +```python +# the preferred way +method2(m, foobar={'foo': foo_expr, 'bar': bar_expr}, baz=baz_expr) + +# the alternative way +method2(m, {'foobar': {'foo': foo_expr, 'bar': bar_expr}, 'baz': baz_expr}) +``` + +### Method definition conventions + +When defining methods, two conventions can be used. +The cleanest and recommended way is to create an argument for each record field: + +```python +@def_method(m, method) +def _(foo: Value, bar: Value): + ... +``` + +The other is to receive the argument record directly. The `arg` name is required: + +```python +def_method(m, method) +def _(arg: Record): + ... +``` + +### Method return value conventions + +The `dict` syntax can be used for returning values from methods. +Take the following method declaration: + +```python +method3 = Method(input_layout=layout, output_layout=layout2) +``` + +One can then define this method as follows: + +```python +@def_method(m, method3) +def _(foo: Value, bar: Value): + return {{'foo': foo, 'bar': foo + bar}, 'baz': foo - bar} +``` + +### Readiness signals + +If a transaction is not always ready for execution (for example, because of the dependence on some resource), a `request` parameter should be used. +An Amaranth single-bit expression should be passed. +When the `request` parameter is not passed, the transaction is always requesting execution. + +```python + with Transaction().body(m, request=expr): +``` + +Methods have a similar mechanism, which uses the `ready` parameter on `def_method`: + +```python + @def_method(m, self.my_method, ready=expr) + def _(arg): + ... +``` + +The `request` signal typically should only depend on the internal state of an `Elaboratable`. +Other dependencies risk introducing combinational loops. +In certain occasions, it is possible to relax this requirement; see e.g. [Scheduling order](#scheduling-order). + +## The library + +The transaction framework is designed to facilitate code re-use. +It includes a library, which contains `Elaboratable`s providing useful methods and transactions. +The most useful ones are: + +* `ConnectTrans`, for connecting two methods together with a transaction. +* `FIFO`, for queues accessed with two methods, `read` and `write`. +* `Adapter` and `AdapterTrans`, for communicating with transactions and methods from plain Amaranth code. + These are very useful in testbenches. + +## Advanced concepts + +### Special combinational domains + +Transactron defines its own variant of Amaranth modules, called `TModule`. +Its role is to allow to improve circuit performance by omitting unneeded multiplexers in combinational circuits. +This is done by adding two additional, special combinatorial domains, `av_comb` and `top_comb`. + +Statements added to the `av_comb` domain (the "avoiding" domain) are not executed when under a false `m.If`, but are executed when under a false `m.AvoidedIf`. +Transaction and method bodies are internally guarded by an `m.AvoidedIf` with the transaction `grant` or method `run` signal. +Therefore combinational assignments added to `av_comb` work even if the transaction or method definition containing the assignments are not running. +Because combinational signals usually don't induce state changes, this is often safe to do and improves performance. + +Statements added to the `top_comb` domain are always executed, even if the statement is under false conditions (including `m.If`, `m.Switch` etc.). +This allows for cleaner code, as combinational assignments which logically belong to some case, but aren't actually required to be there, can be as performant as if they were manually moved to the top level. + +An important caveat of the special domains is that, just like with normal domains, a signal assigned in one of them cannot be assigned in others. + +### Scheduling order + +When writing multiple methods and transactions in the same `Elaboratable`, sometimes some dependency between them needs to exist. +For example, in the `Forwarder` module in the library, forwarding can take place only if both `read` and `write` are executed simultaneously. +This requirement is handled by making the the `read` method's readiness depend on the execution of the `write` method. +If the `read` method was considered for execution before `write`, this would introduce a combinational loop into the circuit. +In order to avoid such issues, one can require a certain scheduling order between methods and transactions. + +`Method` and `Transaction` objects include a `schedule_before` method. +Its only argument is another `Method` or `Transaction`, which will be scheduled after the first one: + +```python +first_t_or_m.schedule_before(other_t_or_m) +``` + +Internally, scheduling orders exist only on transactions. +If a scheduling order is added to a `Method`, it is lifted to the transaction level. +For example, if `first_m` is scheduled before `other_t`, and is called by `t1` and `t2`, the added scheduling orderings will be the same as if the following calls were made: + +```python +t1.schedule_before(other_t) +t2.schedule_before(other_t) +``` + +### Conflicts + +In some situations it might be useful to make some methods or transactions mutually exclusive with others. +Two conflicting transactions or methods can't execute simultaneously: only one or the other runs in a given clock cycle. + +Conflicts are defined similarly to scheduling orders: + +```python +first_t_or_m.add_conflict(other_t_or_m) +``` + +Conflicts are lifted to the transaction level, just like scheduling orders. + +The `add_conflict` method has an optional argument `priority`, which allows to define a scheduling order between conflicting transactions or methods. +Possible values are `Priority.LEFT`, `Priority.RIGHT` and `Priority.UNDEFINED` (the default). +For example, the following code adds a conflict with a scheduling order, where `first_m` is scheduled before `other_m`: + +```python +first_m.add_conflict(other_m, priority = Priority.LEFT) +``` + +Scheduling conflicts come with a possible cost. +The conflicting transactions have a dependency in the transaction scheduler, which can increase the size and combinational delay of the scheduling circuit. +Therefore, use of this feature requires consideration. + +### Transaction and method nesting + +Transaction and method bodies can be nested. For example: + +```python +with Transaction().body(m): + # Transaction body. + + with Transaction().body(m): + # Nested transaction body. +``` + +Nested transactions and methods can only run if the parent also runs. +The converse is not true: it is possible that only the parent runs, but the nested transaction or method doesn't (because of other limitations). +Nesting implies scheduling order: the nested transaction or method is considered for execution after the parent. diff --git a/api.html b/api.html index 56e87f9a2..296615a53 100644 --- a/api.html +++ b/api.html @@ -21,7 +21,7 @@ - + @@ -41,18 +41,18 @@ @@ -240,7 +240,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 18:08 2023-11-20. + Last updated on 23:47 2023-11-22.

diff --git a/assumptions.html b/assumptions.html new file mode 100644 index 000000000..a4da8e92b --- /dev/null +++ b/assumptions.html @@ -0,0 +1,125 @@ + + + + + + List of assumptions made during development — Coreblocks documentation + + + + + + + + + + + + + + + + + + + +
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List of assumptions made during development

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  • RF has data forwarding from the Tomasulo announcement bus

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  • read of x0/RF0 returns 0

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  • write to x0/RF0 is a noop

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  • separate RS for each FU

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  • the writeback stage saves data to the RF and the ROB (after getting output data from FUs)

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  • the commit stage updates the R-RAT

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© Copyright Kuźnia Rdzeni, 2023. + Last updated on 23:47 2023-11-22. +

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+ + + + \ No newline at end of file diff --git a/auto_graph.html b/auto_graph.html index 022b659e8..04e75ed13 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -39,18 +39,18 @@

© Copyright Kuźnia Rdzeni, 2023. - Last updated on 18:08 2023-11-20. + Last updated on 23:47 2023-11-22.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 60da9728a..7d0cd18a0 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -41,18 +41,18 @@ diff --git a/coreblocks.fu.html b/coreblocks.fu.html index 8aac060c0..b135fe7b2 100644 --- a/coreblocks.fu.html +++ b/coreblocks.fu.html @@ -41,18 +41,18 @@ diff --git a/coreblocks.fu.unsigned_multiplication.html b/coreblocks.fu.unsigned_multiplication.html index f6fd23ec7..9cbda1a97 100644 --- a/coreblocks.fu.unsigned_multiplication.html +++ b/coreblocks.fu.unsigned_multiplication.html @@ -41,18 +41,18 @@ diff --git a/coreblocks.html b/coreblocks.html index e7d592b2d..059943597 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -41,18 +41,18 @@ diff --git a/coreblocks.params.html b/coreblocks.params.html index 6b22a2534..113183d81 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -41,18 +41,18 @@ diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index bab4bf049..338006510 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -41,18 +41,18 @@ diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index f770359d7..f8324a0e2 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -41,18 +41,18 @@ diff --git a/coreblocks.stages.html b/coreblocks.stages.html index 0b880e3de..4c0c0dffa 100644 --- a/coreblocks.stages.html +++ b/coreblocks.stages.html @@ -41,18 +41,18 @@ diff --git a/coreblocks.structs_common.html b/coreblocks.structs_common.html index 1a7a15bcc..beebc695c 100644 --- a/coreblocks.structs_common.html +++ b/coreblocks.structs_common.html @@ -41,18 +41,18 @@ diff --git a/coreblocks.utils.html b/coreblocks.utils.html index a56017589..abfe6f911 100644 --- a/coreblocks.utils.html +++ b/coreblocks.utils.html @@ -41,18 +41,18 @@ diff --git a/current-graph.html b/current-graph.html new file mode 100644 index 000000000..c8d0cf492 --- /dev/null +++ b/current-graph.html @@ -0,0 +1,581 @@ + + + + + + Full transaction-method graph — Coreblocks documentation + + + + + + + + + + + + + + + + + + + +
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Full transaction-method graph

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+ flowchart TB + subgraph TransactionModule["TransactionModule"] + subgraph TestElaboratable["elaboratable TestElaboratable"] + subgraph Core["core Core"] + Core_InitFreeRFFifo["InitFreeRFFifo"] + subgraph WishboneMaster["wb_master_instr WishboneMaster"] + WishboneMaster_result["result"] + WishboneMaster_request["request"] + WishboneMaster_WishboneMaster["WishboneMaster"] + subgraph Forwarder["result Forwarder"] + Forwarder_read["read"] + Forwarder_write["write"] + end + end + subgraph WishboneMaster1["wb_master_data WishboneMaster"] + WishboneMaster1_request["request"] + WishboneMaster1_WishboneMaster["WishboneMaster"] + WishboneMaster1_result["result"] + subgraph Forwarder1["result Forwarder"] + Forwarder1_read["read"] + Forwarder1_write["write"] + end + end + subgraph FIFO["fifo_fetch FIFO"] + FIFO_read["read"] + FIFO_write["write"] + end + subgraph BasicFifo["free_rf_fifo BasicFifo"] + BasicFifo_write["write"] + BasicFifo_read["read"] + end + subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"] + SimpleWBCacheRefiller_start_refill["start_refill"] + SimpleWBCacheRefiller_accept_refill["accept_refill"] + SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"] + subgraph Forwarder2["address_fwd Forwarder"] + Forwarder2_write["write"] + Forwarder2_read["read"] + end + end + subgraph ICache["icache ICache"] + ICache_ICache["ICache"] + ICache_ICache1["ICache"] + ICache_accept_res["accept_res"] + ICache_issue_req["issue_req"] + ICache_ICache2["ICache"] + subgraph FIFO1["req_fifo FIFO"] + FIFO1_read["read"] + FIFO1_write["write"] + end + subgraph Forwarder3["res_fwd Forwarder"] + Forwarder3_write["write"] + Forwarder3_read["read"] + end + end + subgraph Fetch["fetch Fetch"] + Fetch_verify_branch["verify_branch"] + Fetch_Fetch["Fetch"] + Fetch_Fetch1["Fetch"] + subgraph BasicFifo1["fetch_target_queue BasicFifo"] + BasicFifo1_write["write"] + BasicFifo1_read["read"] + end + end + subgraph FRAT["FRAT FRAT"] + FRAT_rename["rename"] + end + subgraph RRAT["RRAT RRAT"] + RRAT_commit["commit"] + end + subgraph RegisterFile["RF RegisterFile"] + RegisterFile_read2["read2"] + RegisterFile_free["free"] + RegisterFile_write["write"] + RegisterFile_read1["read1"] + end + subgraph ReorderBuffer["ROB ReorderBuffer"] + ReorderBuffer_mark_done["mark_done"] + ReorderBuffer_peek["peek"] + ReorderBuffer_retire["retire"] + ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_put["put"] + end + subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] + ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_report["report"] + end + subgraph FuncBlocksUnifier["func_blocks_unifier FuncBlocksUnifier"] + subgraph Collector["result_collector Collector"] + Collector_method["method"] + subgraph Forwarder4["forwarder Forwarder"] + Forwarder4_read["read"] + Forwarder4_write["write"] + end + subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] + subgraph ConnectTrans["ManyToOneConnectTrans_input_0 ConnectTrans"] + ConnectTrans_ConnectTrans["ConnectTrans"] + end + subgraph ConnectTrans1["ManyToOneConnectTrans_input_1 ConnectTrans"] + ConnectTrans1_ConnectTrans["ConnectTrans"] + end + end + end + subgraph MethodProduct["update_combiner MethodProduct"] + MethodProduct_method["method"] + end + subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] + RSFuncBlock_insert["insert"] + RSFuncBlock_update["update"] + RSFuncBlock_select["select"] + RSFuncBlock_get_result["get_result"] + subgraph RS["rs RS"] + RS_update["update"] + RS_take["take"] + RS_RS["RS"] + RS_RS1["RS"] + RS_RS2["RS"] + RS_insert["insert"] + RS_RS3["RS"] + RS_select["select"] + end + subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] + AluFuncUnit_issue["issue"] + AluFuncUnit_accept["accept"] + subgraph FIFO2["fifo FIFO"] + FIFO2_read["read"] + FIFO2_write["write"] + end + end + subgraph WakeupSelect["wakeup_select_0 WakeupSelect"] + WakeupSelect_WakeupSelect["WakeupSelect"] + end + subgraph ShiftFuncUnit["func_unit_1 ShiftFuncUnit"] + ShiftFuncUnit_accept["accept"] + ShiftFuncUnit_issue["issue"] + subgraph FIFO3["fifo FIFO"] + FIFO3_write["write"] + FIFO3_read["read"] + end + end + subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] + WakeupSelect1_WakeupSelect["WakeupSelect"] + end + subgraph JumpBranchFuncUnit["func_unit_2 JumpBranchFuncUnit"] + JumpBranchFuncUnit_branch_result["branch_result"] + JumpBranchFuncUnit_accept["accept"] + JumpBranchFuncUnit_issue["issue"] + subgraph FIFO4["fifo_res FIFO"] + FIFO4_read["read"] + FIFO4_write["write"] + end + subgraph FIFO5["fifo_branch FIFO"] + FIFO5_read["read"] + FIFO5_write["write"] + end + end + subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] + WakeupSelect2_WakeupSelect["WakeupSelect"] + end + subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"] + ExceptionFuncUnit_issue["issue"] + ExceptionFuncUnit_accept["accept"] + subgraph FIFO6["fifo FIFO"] + FIFO6_read["read"] + FIFO6_write["write"] + end + end + subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] + WakeupSelect3_WakeupSelect["WakeupSelect"] + end + subgraph Collector1["collector Collector"] + Collector1_method["method"] + subgraph Forwarder5["forwarder Forwarder"] + Forwarder5_write["write"] + Forwarder5_read["read"] + end + subgraph ManyToOneConnectTrans1["connect ManyToOneConnectTrans"] + subgraph ConnectTrans2["ManyToOneConnectTrans_input_0 ConnectTrans"] + ConnectTrans2_ConnectTrans["ConnectTrans"] + end + subgraph ConnectTrans3["ManyToOneConnectTrans_input_1 ConnectTrans"] + ConnectTrans3_ConnectTrans["ConnectTrans"] + end + subgraph ConnectTrans4["ManyToOneConnectTrans_input_2 ConnectTrans"] + ConnectTrans4_ConnectTrans["ConnectTrans"] + end + subgraph ConnectTrans5["ManyToOneConnectTrans_input_3 ConnectTrans"] + ConnectTrans5_ConnectTrans["ConnectTrans"] + end + end + end + end + subgraph LSUDummy["rs_block_1 LSUDummy"] + LSUDummy_insert["insert"] + LSUDummy_LSUDummy["LSUDummy"] + LSUDummy_get_result["get_result"] + LSUDummy_select["select"] + LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_precommit["precommit"] + LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_update["update"] + subgraph Forwarder6["forwarder Forwarder"] + Forwarder6_write["write"] + Forwarder6_read["read"] + end + subgraph LSURequesterWB["requester LSURequesterWB"] + LSURequesterWB_issue["issue"] + LSURequesterWB_accept["accept"] + end + end + end + subgraph ResultAnnouncement["announcement ResultAnnouncement"] + ResultAnnouncement_ResultAnnouncement["ResultAnnouncement"] + end + subgraph GenericCSRRegisters["csr_generic GenericCSRRegisters"] + GenericCSRRegisters_GenericCSRRegisters["GenericCSRRegisters"] + subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] + DoubleCounterCSR_increment["increment"] + subgraph CSRRegister["register_low CSRRegister"] + CSRRegister_read["read"] + CSRRegister_write["write"] + end + subgraph CSRRegister1["register_high CSRRegister"] + CSRRegister1_read["read"] + CSRRegister1_write["write"] + end + end + subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] + DoubleCounterCSR1_increment["increment"] + subgraph CSRRegister2["register_low CSRRegister"] + CSRRegister2_write["write"] + CSRRegister2_read["read"] + end + subgraph CSRRegister3["register_high CSRRegister"] + CSRRegister3_write["write"] + CSRRegister3_read["read"] + end + end + subgraph CSRRegister4["mcause CSRRegister"] + CSRRegister4_write["write"] + end + end + subgraph FIFO7["fifo_decode FIFO"] + FIFO7_read["read"] + FIFO7_write["write"] + end + subgraph Decode["decode Decode"] + Decode_Decode["Decode"] + end + subgraph Scheduler["scheduler Scheduler"] + subgraph FIFO8["alloc_rename_buf FIFO"] + FIFO8_write["write"] + FIFO8_read["read"] + end + subgraph RegAllocation["reg_alloc RegAllocation"] + RegAllocation_RegAllocation["RegAllocation"] + end + subgraph FIFO9["rename_out_buf FIFO"] + FIFO9_write["write"] + FIFO9_read["read"] + end + subgraph Renaming["renaming Renaming"] + Renaming_Renaming["Renaming"] + end + subgraph FIFO10["reg_alloc_out_buf FIFO"] + FIFO10_write["write"] + FIFO10_read["read"] + end + subgraph ROBAllocation["rob_alloc ROBAllocation"] + ROBAllocation_ROBAllocation["ROBAllocation"] + end + subgraph FIFO11["rs_select_out_buf FIFO"] + FIFO11_read["read"] + FIFO11_write["write"] + end + subgraph RSSelection["rs_selector RSSelection"] + RSSelection_RSSelection["RSSelection"] + RSSelection_RSSelection1["RSSelection"] + RSSelection_RSSelection2["RSSelection"] + subgraph Forwarder7["forwarder Forwarder"] + Forwarder7_write["write"] + Forwarder7_read["read"] + end + end + subgraph RSInsertion["rs_insertion RSInsertion"] + RSInsertion_RSInsertion["RSInsertion"] + end + end + subgraph ConnectTrans6["verify_branch ConnectTrans"] + ConnectTrans6_ConnectTrans["ConnectTrans"] + end + subgraph Retirement["retirement Retirement"] + Retirement_Retirement["Retirement"] + Retirement_Retirement1["Retirement"] + Retirement_Retirement2["Retirement"] + subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] + DoubleCounterCSR2_increment["increment"] + subgraph CSRRegister5["register_low CSRRegister"] + CSRRegister5_read["read"] + CSRRegister5_write["write"] + end + subgraph CSRRegister6["register_high CSRRegister"] + CSRRegister6_read["read"] + CSRRegister6_write["write"] + end + end + subgraph Forwarder8["frat_fix Forwarder"] + Forwarder8_write["write"] + Forwarder8_read["read"] + end + end + end + subgraph TestbenchIO["io_in TestbenchIO"] + subgraph AdapterTrans["adapter AdapterTrans"] + AdapterTrans_AdapterTrans_write["AdapterTrans_write"] + end + end + subgraph TestbenchIO1["rf_write TestbenchIO"] + subgraph AdapterTrans1["adapter AdapterTrans"] + AdapterTrans1_AdapterTrans_write["AdapterTrans_write"] + end + end + end + end +Core_InitFreeRFFifo --> BasicFifo_write +Retirement_Retirement --> BasicFifo_write +WishboneMaster_WishboneMaster --> Forwarder_write +WishboneMaster1_WishboneMaster --> Forwarder1_write +Forwarder2_read --> SimpleWBCacheRefiller_SimpleWBCacheRefiller +SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request +ICache_ICache2 --> Forwarder3_write +ICache_ICache1 --> SimpleWBCacheRefiller_start_refill +ICache_ICache1 --> Forwarder2_write +ICache_ICache --> Forwarder2_write +SimpleWBCacheRefiller_accept_refill --> ICache_ICache +WishboneMaster_result --> ICache_ICache +Forwarder_read --> ICache_ICache +Fetch_Fetch1 --> ICache_issue_req +Fetch_Fetch1 --> FIFO1_write +Fetch_Fetch1 --> BasicFifo1_write +BasicFifo1_read --> Fetch_Fetch +ICache_accept_res --> Fetch_Fetch +FIFO1_read --> Fetch_Fetch +Forwarder3_read --> Fetch_Fetch +Fetch_Fetch --> FIFO_write +AdapterTrans_AdapterTrans_write --> FIFO_write +FIFO_read --> Decode_Decode +Decode_Decode --> FIFO7_write +FIFO7_read --> RegAllocation_RegAllocation +BasicFifo_read --> RegAllocation_RegAllocation +RegAllocation_RegAllocation --> FIFO8_write +FIFO8_read --> Renaming_Renaming +Renaming_Renaming --> FRAT_rename +Retirement_Retirement2 --> FRAT_rename +Renaming_Renaming --> FIFO9_write +FIFO9_read --> ROBAllocation_ROBAllocation +ROBAllocation_ROBAllocation --> ReorderBuffer_put +ROBAllocation_ROBAllocation --> FIFO10_write +FIFO10_read --> RSSelection_RSSelection2 +RSSelection_RSSelection2 --> Forwarder7_write +Forwarder7_read --> RSSelection_RSSelection +Forwarder7_read --> RSSelection_RSSelection1 +RSFuncBlock_select --> RSSelection_RSSelection +RS_select --> RSSelection_RSSelection +RSSelection_RSSelection --> FIFO11_write +RSSelection_RSSelection1 --> FIFO11_write +RSSelection_RSSelection1 <--> LSUDummy_select +FIFO11_read --> RSInsertion_RSInsertion +RegisterFile_read1 --> RSInsertion_RSInsertion +RegisterFile_read2 --> RSInsertion_RSInsertion +RSInsertion_RSInsertion --> RSFuncBlock_insert +RSInsertion_RSInsertion --> RS_insert +RSInsertion_RSInsertion --> LSUDummy_insert +JumpBranchFuncUnit_branch_result --> ConnectTrans6_ConnectTrans +FIFO5_read --> ConnectTrans6_ConnectTrans +ConnectTrans6_ConnectTrans --> Fetch_verify_branch +Collector_method --> ResultAnnouncement_ResultAnnouncement +Forwarder4_read --> ResultAnnouncement_ResultAnnouncement +ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done +ResultAnnouncement_ResultAnnouncement --> RegisterFile_write +AdapterTrans1_AdapterTrans_write --> RegisterFile_write +ResultAnnouncement_ResultAnnouncement --> MethodProduct_method +ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update +ResultAnnouncement_ResultAnnouncement --> RS_update +ResultAnnouncement_ResultAnnouncement --> LSUDummy_update +RS_RS3 --> WakeupSelect_WakeupSelect +RS_take --> WakeupSelect_WakeupSelect +RS_take --> WakeupSelect1_WakeupSelect +RS_take --> WakeupSelect2_WakeupSelect +RS_take --> WakeupSelect3_WakeupSelect +WakeupSelect_WakeupSelect --> AluFuncUnit_issue +WakeupSelect_WakeupSelect --> FIFO2_write +RS_RS2 --> WakeupSelect1_WakeupSelect +WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue +WakeupSelect1_WakeupSelect --> FIFO3_write +RS_RS1 --> WakeupSelect2_WakeupSelect +WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue +WakeupSelect2_WakeupSelect --> ExceptionCauseRegister_report +WakeupSelect3_WakeupSelect --> ExceptionCauseRegister_report +ConnectTrans1_ConnectTrans --> ExceptionCauseRegister_report +ReorderBuffer_get_indices --> WakeupSelect2_WakeupSelect +ReorderBuffer_get_indices --> WakeupSelect3_WakeupSelect +ReorderBuffer_get_indices --> ConnectTrans1_ConnectTrans +WakeupSelect2_WakeupSelect --> FIFO4_write +WakeupSelect2_WakeupSelect --> FIFO5_write +RS_RS --> WakeupSelect3_WakeupSelect +WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue +WakeupSelect3_WakeupSelect --> FIFO6_write +ConnectTrans2_ConnectTrans --> Forwarder5_write +ConnectTrans3_ConnectTrans --> Forwarder5_write +ConnectTrans4_ConnectTrans --> Forwarder5_write +ConnectTrans5_ConnectTrans --> Forwarder5_write +AluFuncUnit_accept --> ConnectTrans2_ConnectTrans +FIFO2_read --> ConnectTrans2_ConnectTrans +ShiftFuncUnit_accept --> ConnectTrans3_ConnectTrans +FIFO3_read --> ConnectTrans3_ConnectTrans +JumpBranchFuncUnit_accept --> ConnectTrans4_ConnectTrans +FIFO4_read --> ConnectTrans4_ConnectTrans +ExceptionFuncUnit_accept --> ConnectTrans5_ConnectTrans +FIFO6_read --> ConnectTrans5_ConnectTrans +LSUDummy_LSUDummy2 --> LSURequesterWB_issue +LSUDummy_LSUDummy2 --> WishboneMaster1_request +LSUDummy_LSUDummy2 --> Forwarder6_write +LSUDummy_LSUDummy --> Forwarder6_write +LSUDummy_LSUDummy1 --> Forwarder6_write +LSURequesterWB_accept --> LSUDummy_LSUDummy1 +WishboneMaster1_result --> LSUDummy_LSUDummy1 +Forwarder1_read --> LSUDummy_LSUDummy1 +ConnectTrans_ConnectTrans --> Forwarder4_write +ConnectTrans1_ConnectTrans --> Forwarder4_write +RSFuncBlock_get_result --> ConnectTrans_ConnectTrans +Collector1_method --> ConnectTrans_ConnectTrans +Forwarder5_read --> ConnectTrans_ConnectTrans +LSUDummy_get_result --> ConnectTrans1_ConnectTrans +Forwarder6_read --> ConnectTrans1_ConnectTrans +ReorderBuffer_peek --> Retirement_Retirement1 +Retirement_Retirement1 --> LSUDummy_precommit +ReorderBuffer_retire --> Retirement_Retirement +ExceptionCauseRegister_get --> Retirement_Retirement +Retirement_Retirement --> CSRRegister4_write +Retirement_Retirement --> RRAT_commit +Retirement_Retirement <--> DoubleCounterCSR2_increment +CSRRegister5_read --> Retirement_Retirement +Retirement_Retirement --> CSRRegister5_write +CSRRegister6_read --> Retirement_Retirement +Retirement_Retirement --> CSRRegister6_write +Retirement_Retirement --> Forwarder8_write +Retirement_Retirement --> RegisterFile_free +Forwarder8_read --> Retirement_Retirement2 +GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment +CSRRegister_read --> GenericCSRRegisters_GenericCSRRegisters +GenericCSRRegisters_GenericCSRRegisters --> CSRRegister_write +CSRRegister1_read --> GenericCSRRegisters_GenericCSRRegisters +GenericCSRRegisters_GenericCSRRegisters --> CSRRegister1_write +GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR1_increment +CSRRegister2_read --> GenericCSRRegisters_GenericCSRRegisters +GenericCSRRegisters_GenericCSRRegisters --> CSRRegister2_write +CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters +GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write +
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© Copyright Kuźnia Rdzeni, 2023. + Last updated on 23:47 2023-11-22. +

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Development environment

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Setting up

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In order to prepare the development environment, please follow the steps below:

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  1. Install the Python 3.11 interpreter and pip package manager.

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    • Optionally create a Python virtual environment with python3 -m venv venv in the project directory and activate it using generated script: . venv/bin/activate.

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  2. Install all required libraries with pip3 install -r requirements-dev.txt.

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  3. Install riscv64-unknown-elf binutils using your favourite package manager. On Debian-based distros the package is called binutils-riscv64-unknown-elf, on Arch-based - riscv64-unknown-elf-binutils.

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  4. Optionally, install all precommit hooks with pre-commit install. This will automatically run the linter before commits.

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Using scripts

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The development environment contains a number of scripts which are run in CI, but are also intended for local use. They are:

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run_tests.py

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Runs the unit tests. By default, every available test is run. Tests from a specific file can be run using the following call (test_transactions is used as an example):

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scripts/run_tests.py test_transactions
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One can even run a specific test class from a file:

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scripts/run_tests.py test_transactions.TestScheduler
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Or a specific test method:

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scripts/run_tests.py test_transactions.TestScheduler.test_single
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The argument to run_tests.py is actually used to search within the full names of tests. The script runs all the tests which match the query. Thanks to this, if a given test class name is unique, just the class name can be used as an argument.

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The run_tests.py script has the following options:

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  • -l, --list – lists available tests. This option is helpful, e.g., to find a name of a test generated using the parameterized package.

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  • -t, --trace – generates waveforms in the vcd format and gtkw files for the gtkwave tool. The files are saved in the test/__traces__/ directory. Useful for debugging and test-driven development.

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  • -v, --verbose – makes the test runner more verbose. It will, for example, print the names of all the tests being run.

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lint.sh

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Checks the code formatting and typing. It should be run as follows:

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scripts/lint.sh subcommand [filename...]
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The following main subcommands are available:

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  • format – reformats the code using black.

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  • check_format – verifies code formatting using black and flake8.

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  • check_types – verifies typing using pyright.

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  • verify – runs all checks. The same set of checks is run in CI.

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When confronted with would reformat [filename] message from black you may run:

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black --diff [filename]
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This way you may display the changes black would apply to [filename] if you chose the format option for lint.sh script. This may help you locate the formatting issues.

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core_graph.py

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Visualizes the core architecture as a graph. The script outputs a file in one of supported graph formats, which need to be passed to an appropriate tool to get a graph.

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The core_graph.py script has the following options:

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  • -p, --prune – removes disconnected nodes from the output graph.

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  • -f FORMAT, --format FORMAT – selects the output format. Supported formats are elk (for Eclipse Layout Kernel), dot (for Graphviz), mermaid (for Mermaid).

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build_docs.sh

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Generates local documentation using Sphinx. The generated HTML files are located in build/html.

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© Copyright Kuźnia Rdzeni, 2023. + Last updated on 23:47 2023-11-22. +

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zJ*BM*y0)0MsPW04k>!)*m}fsN6_H)(k2W1aCGOW16zQ+#LBlS~R&0{?5O1)&T;yxs tSJ1K)*tG + + + + + Problem checklist — Coreblocks documentation + + + + + + + + + + + + + + + + + + + +
+ + +
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+ +
+

Problem checklist

+

If something doesn’t work and you’re puzzled as to why - go through this checklist to see if any of these points apply in your case:

+
    +

  1. Make sure that you use yield from when calling generator functions in tests - e.g. TestbenchIO functions (notable exception: yield Settle() instead of yield from Settle())

    2. +

  2. If a signal has an unexpected value in tests try adding yield Settle() right before you read it.

    3. +

  3. Make sure you don’t do .eq on two records with different layouts. Use assign from coreblocks.utils instead.

    4. +

  4. Make sure all amaranth statements are added to some domain.

    5. +

  5. Check if your code doesn’t have any combinational loops - especially if your simulation hangs.

    6. +
+

Please extend this list if you spot yourself doing an easy-to-fix mistake.

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+ + +
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+ +
+ +
+

© Copyright Kuźnia Rdzeni, 2023. + Last updated on 23:47 2023-11-22. +

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+ + + + \ No newline at end of file diff --git a/py-modindex.html b/py-modindex.html index a1bca4a57..7353c746e 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -42,18 +42,18 @@ diff --git a/transactron.lib.html b/transactron.lib.html index 920792a22..8141a2d98 100644 --- a/transactron.lib.html +++ b/transactron.lib.html @@ -41,18 +41,18 @@ diff --git a/transactron.utils.html b/transactron.utils.html index 669175af5..a1659d6c6 100644 --- a/transactron.utils.html +++ b/transactron.utils.html @@ -40,18 +40,18 @@