diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index c2186514e..223e434cd 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index bf39cd7f1..406a5c8fa 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree index b0e6cb0c2..9c1fd0fb5 100644 Binary files a/.doctrees/current-graph.doctree and b/.doctrees/current-graph.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index 12ed0f57b..55aa34e22 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 23126380c..ecd50e847 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -11,17 +11,17 @@ WishboneMaster_result["result"] WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] - Forwarder_write["write"] Forwarder_read["read"] + Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_WishboneMaster["WishboneMaster"] - WishboneMaster1_request["request"] WishboneMaster1_result["result"] + WishboneMaster1_request["request"] + WishboneMaster1_WishboneMaster["WishboneMaster"] subgraph Forwarder1["result Forwarder"] - Forwarder1_read["read"] Forwarder1_write["write"] + Forwarder1_read["read"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] @@ -47,8 +47,8 @@ Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_write["write"] BasicFifo1_read["read"] + BasicFifo1_write["write"] end end end @@ -57,8 +57,8 @@ CoreInstructionCounter_decrement["decrement"] end subgraph FIFO["fifo_fetch FIFO"] - FIFO_read["read"] FIFO_write["write"] + FIFO_read["read"] end subgraph MethodMap["core_counter_increment_discard_map MethodMap"] MethodMap_method["method"] @@ -71,9 +71,9 @@ BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] subgraph Forwarder2["address_fwd Forwarder"] Forwarder2_read["read"] Forwarder2_write["write"] @@ -81,10 +81,10 @@ end subgraph ICache["icache ICache"] ICache_ICache["ICache"] - ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] + ICache_accept_res["accept_res"] + ICache_issue_req["issue_req"] ICache_ICache3["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] @@ -102,8 +102,8 @@ HwCounter4__incr["_incr"] end subgraph LatencyMeasurer["req_latency LatencyMeasurer"] - LatencyMeasurer__stop["_stop"] LatencyMeasurer__start["_start"] + LatencyMeasurer__stop["_stop"] subgraph HwExpHistogram["histogram HwExpHistogram"] HwExpHistogram__add["_add"] end @@ -117,8 +117,8 @@ FIFO2_write["write"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end subgraph FRAT["FRAT FRAT"] @@ -129,20 +129,20 @@ RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] RegisterFile_write["write"] - RegisterFile_free["free"] RegisterFile_read2["read2"] + RegisterFile_read1["read1"] + RegisterFile_free["free"] end subgraph ReorderBuffer["ROB ReorderBuffer"] + ReorderBuffer_put["put"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_peek["peek"] ReorderBuffer_retire["retire"] - ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_put["put"] + ReorderBuffer_peek["peek"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] - LatencyMeasurer1__stop["_stop"] LatencyMeasurer1__start["_start"] + LatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram1["histogram HwExpHistogram"] HwExpHistogram1__add["_add"] end @@ -153,9 +153,9 @@ end end subgraph Fetch["fetch Fetch"] + Fetch_resume["resume"] Fetch_Fetch["Fetch"] Fetch_stall_exception["stall_exception"] - Fetch_resume["resume"] Fetch_Fetch1["Fetch"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] BasicFifo3_read["read"] @@ -164,8 +164,8 @@ end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] ExceptionCauseRegister_report["report"] - ExceptionCauseRegister_get["get"] ExceptionCauseRegister_clear["clear"] + ExceptionCauseRegister_get["get"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] BasicFifo4_write["write"] BasicFifo4_read["read"] @@ -178,8 +178,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_write["write"] Forwarder4_read["read"] + Forwarder4_write["write"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -197,20 +197,20 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_get_result["get_result"] - RSFuncBlock_select["select"] - RSFuncBlock_insert["insert"] RSFuncBlock_update["update"] + RSFuncBlock_insert["insert"] + RSFuncBlock_select["select"] + RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] + RS_update["update"] RS_RS["RS"] - RS_take["take"] RS_RS1["RS"] + RS_select["select"] + RS_take["take"] RS_RS2["RS"] - RS_insert["insert"] RS_RS3["RS"] - RS_update["update"] RS_RS4["RS"] - RS_select["select"] + RS_insert["insert"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] AluFuncUnit_accept["accept"] @@ -227,8 +227,8 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] @@ -251,8 +251,8 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -262,16 +262,16 @@ ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] subgraph FIFO8["fifo FIFO"] - FIFO8_write["write"] FIFO8_read["read"] + FIFO8_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] - PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_issue["issue"] + PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_precommit["precommit"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] BasicFifo5_write["write"] @@ -308,41 +308,41 @@ end subgraph LSUDummy["rs_block_1 LSUDummy"] LSUDummy_select["select"] - LSUDummy_precommit["precommit"] LSUDummy_get_result["get_result"] LSUDummy_LSUDummy["LSUDummy"] LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_LSUDummy2["LSUDummy"] - LSUDummy_insert["insert"] LSUDummy_update["update"] + LSUDummy_insert["insert"] + LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_precommit["precommit"] subgraph Forwarder6["forwarder Forwarder"] - Forwarder6_read["read"] Forwarder6_write["write"] + Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_accept_cond0["accept_cond0"] - LSURequester_issue["issue"] LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept_cond1["accept_cond1"] + LSURequester_issue_cond1["issue_cond1"] LSURequester_accept["accept"] LSURequester_issue_cond2["issue_cond2"] - LSURequester_issue_cond1["issue_cond1"] - LSURequester_accept_cond1["accept_cond1"] + LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue["issue"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_select["select"] - CSRUnit_update["update"] - CSRUnit_precommit["precommit"] CSRUnit_get_result["get_result"] - CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_precommit["precommit"] CSRUnit_insert["insert"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_select["select"] + CSRUnit_update["update"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] MethodTryProduct_MethodTryProduct1["MethodTryProduct"] - MethodTryProduct_MethodTryProduct2["MethodTryProduct"] MethodTryProduct_method["method"] + MethodTryProduct_MethodTryProduct2["MethodTryProduct"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] @@ -377,23 +377,23 @@ CSRRegister_write["write"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_write["_fu_write"] - CSRRegister1_read["read"] CSRRegister1__fu_read["_fu_read"] + CSRRegister1_read["read"] + CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] CSRRegister2_write["write"] - CSRRegister2__fu_read["_fu_read"] - CSRRegister2_read["read"] CSRRegister2__fu_write["_fu_write"] + CSRRegister2_read["read"] + CSRRegister2__fu_read["_fu_read"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] CSRRegister3_write["write"] - CSRRegister3__fu_read["_fu_read"] CSRRegister3_read["read"] + CSRRegister3__fu_read["_fu_read"] end subgraph CSRRegister4["register_high CSRRegister"] CSRRegister4_read["read"] @@ -427,29 +427,29 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO10["alloc_rename_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO11["rename_out_buf FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] end subgraph FIFO12["reg_alloc_out_buf FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO13["rs_select_out_buf FIFO"] - FIFO13_write["write"] FIFO13_read["read"] + FIFO13_write["write"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -457,8 +457,8 @@ RSSelection_RSSelection2["RSSelection"] RSSelection_RSSelection3["RSSelection"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_read["read"] Forwarder8_write["write"] + Forwarder8_read["read"] end end subgraph RSInsertion["rs_insertion RSInsertion"] @@ -469,25 +469,25 @@ ConnectTrans11_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] + Retirement_core_state["core_state"] Retirement_Retirement1["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement2["Retirement"] Retirement_Retirement_cond0["Retirement_cond0"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement3["Retirement"] Retirement_Retirement4["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] CSRRegister7__fu_read["_fu_read"] - CSRRegister7_write["write"] CSRRegister7_read["read"] + CSRRegister7_write["write"] end subgraph CSRRegister8["register_high CSRRegister"] + CSRRegister8__fu_read["_fu_read"] CSRRegister8_read["read"] CSRRegister8_write["write"] - CSRRegister8__fu_read["_fu_read"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -507,19 +507,19 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] - TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] end end Core_InitFreeRFFifo --> BasicFifo2_write - Retirement_Retirement1 --> BasicFifo2_write - TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write + Retirement_Retirement3 --> BasicFifo2_write TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write + TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write @@ -529,19 +529,19 @@ SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request ICache_ICache <--> HwCounter4__incr - ICache_ICache2 <--> HwCounter3__incr - ICache_ICache2 <--> HwCounter2__incr - ICache_ICache2 <--> HwCounter1__incr - ICache_ICache2 --> Forwarder3_write + ICache_ICache3 <--> HwCounter3__incr + ICache_ICache3 <--> HwCounter2__incr + ICache_ICache3 <--> HwCounter1__incr + ICache_ICache3 --> Forwarder3_write ICache_ICache1 --> SimpleCommonBusCacheRefiller_start_refill ICache_ICache1 --> Forwarder2_write - ICache_ICache3 --> Forwarder2_write - SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3 - WishboneMasterAdapter_get_read_response --> ICache_ICache3 - Serializer_Serializer --> ICache_ICache3 - BasicFifo_read --> ICache_ICache3 - WishboneMaster_result --> ICache_ICache3 - Forwarder_read --> ICache_ICache3 + ICache_ICache2 --> Forwarder2_write + SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache2 + WishboneMasterAdapter_get_read_response --> ICache_ICache2 + Serializer_Serializer --> ICache_ICache2 + BasicFifo_read --> ICache_ICache2 + WishboneMaster_result --> ICache_ICache2 + Forwarder_read --> ICache_ICache2 Fetch_Fetch --> ICache_issue_req Fetch_Fetch <--> HwCounter__incr Fetch_Fetch <--> LatencyMeasurer__start @@ -571,7 +571,7 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename - Retirement_Retirement1 --> FRAT_rename + Retirement_Retirement3 --> FRAT_rename TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation @@ -579,18 +579,18 @@ ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write - FIFO12_read --> RSSelection_RSSelection2 - RSSelection_RSSelection2 --> Forwarder8_write - Forwarder8_read --> RSSelection_RSSelection1 - Forwarder8_read --> RSSelection_RSSelection + FIFO12_read --> RSSelection_RSSelection + RSSelection_RSSelection --> Forwarder8_write + Forwarder8_read --> RSSelection_RSSelection2 Forwarder8_read --> RSSelection_RSSelection3 - RSFuncBlock_select --> RSSelection_RSSelection1 - RS_select --> RSSelection_RSSelection1 - RSSelection_RSSelection1 --> FIFO13_write - RSSelection_RSSelection --> FIFO13_write + Forwarder8_read --> RSSelection_RSSelection1 + RSFuncBlock_select --> RSSelection_RSSelection2 + RS_select --> RSSelection_RSSelection2 + RSSelection_RSSelection2 --> FIFO13_write RSSelection_RSSelection3 --> FIFO13_write - RSSelection_RSSelection <--> LSUDummy_select - RSSelection_RSSelection3 <--> CSRUnit_select + RSSelection_RSSelection1 --> FIFO13_write + RSSelection_RSSelection3 <--> LSUDummy_select + RSSelection_RSSelection1 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -606,7 +606,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume - Retirement_Retirement3 --> Fetch_resume + Retirement_Retirement1 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -616,7 +616,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update - RS_RS --> WakeupSelect_WakeupSelect + RS_RS2 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -624,10 +624,10 @@ RS_take --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO4_write - RS_RS4 --> WakeupSelect1_WakeupSelect + RS_RS --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write - RS_RS3 --> WakeupSelect2_WakeupSelect + RS_RS4 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -639,10 +639,10 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write - RS_RS2 --> WakeupSelect3_WakeupSelect + RS_RS1 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write - RS_RS1 --> WakeupSelect4_WakeupSelect + RS_RS3 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -660,11 +660,11 @@ PrivilegedFuncUnit_accept --> ConnectTrans8_ConnectTrans CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write - LSUDummy_LSUDummy1 --> Forwarder6_write - TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write - TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write - TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write + LSUDummy_LSUDummy --> Forwarder6_write + TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write + TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write + TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write @@ -695,37 +695,37 @@ ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans - ReorderBuffer_peek --> Retirement_Retirement2 + ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> Retirement_Retirement - ReorderBuffer_peek --> Retirement_Retirement1 - ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + ReorderBuffer_peek --> Retirement_Retirement3 ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement2 --> MethodTryProduct_method + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement4 --> MethodTryProduct_method ExceptionCauseRegister_get --> Retirement_Retirement - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement1 <--> ReorderBuffer_retire - TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire + ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement3 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire - Retirement_Retirement1 <--> LatencyMeasurer1__stop - TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire + Retirement_Retirement3 <--> LatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop - FIFO3_read --> Retirement_Retirement1 - FIFO3_read --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop + FIFO3_read --> Retirement_Retirement3 FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement1 --> HwExpHistogram1__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add + FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 + Retirement_Retirement3 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add - CoreInstructionCounter_decrement --> Retirement_Retirement1 - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add + CoreInstructionCounter_decrement --> Retirement_Retirement3 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 - RRAT_peek --> Retirement_Retirement1 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 + RRAT_peek --> Retirement_Retirement3 RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 - Retirement_Retirement1 --> RegisterFile_free - TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free + Retirement_Retirement3 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free - CSRRegister1_read --> Retirement_Retirement3 - Retirement_Retirement3 <--> ExceptionCauseRegister_clear + TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free + CSRRegister1_read --> Retirement_Retirement1 + Retirement_Retirement1 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -737,45 +737,19 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_cond0_Retirement --> RRAT_commit - TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment - CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write - CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write - TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement4 - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement4 - TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write - TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write - TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry - TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry - TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2 - TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy2 - LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 - LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 - TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 - Serializer1_Serializer2 --> TransactionManager_LSUDummy_accept_cond0 - BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 - BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 - WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 - WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 - Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 - Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 - TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 - Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond1 - TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 - TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy - TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy - TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy - TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue - TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue + TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy + Serializer1_Serializer1 --> TransactionManager_accept_cond0_LSUDummy + BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy + BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy + WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy + WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy + Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy + Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy + TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy2 + TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy2 + LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy + LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3 @@ -783,7 +757,33 @@ TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request + TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 + TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy1 + TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue + TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement2 + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2 + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write + TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 + TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy + Serializer1_Serializer2 --> TransactionManager_accept_cond1_LSUDummy + TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit + TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment + CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write + CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 - TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 + TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer diff --git a/api.html b/api.html index 2a1f6c1ba..f86a2c32a 100644 --- a/api.html +++ b/api.html @@ -259,7 +259,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/assumptions.html b/assumptions.html index e0196f2db..d5bb64ee3 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/auto_graph.html b/auto_graph.html index 24d2393e3..534a12154 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -90,17 +90,17 @@ WishboneMaster_result["result"] WishboneMaster_request["request"] subgraph Forwarder["result Forwarder"] - Forwarder_write["write"] Forwarder_read["read"] + Forwarder_write["write"] end end subgraph WishboneMaster1["wb_master_data WishboneMaster"] - WishboneMaster1_WishboneMaster["WishboneMaster"] - WishboneMaster1_request["request"] WishboneMaster1_result["result"] + WishboneMaster1_request["request"] + WishboneMaster1_WishboneMaster["WishboneMaster"] subgraph Forwarder1["result Forwarder"] - Forwarder1_read["read"] Forwarder1_write["write"] + Forwarder1_read["read"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] @@ -126,8 +126,8 @@ Serializer1_Serializer2["Serializer"] Serializer1_Serializer3["Serializer"] subgraph BasicFifo1["pending_requests BasicFifo"] - BasicFifo1_write["write"] BasicFifo1_read["read"] + BasicFifo1_write["write"] end end end @@ -136,8 +136,8 @@ CoreInstructionCounter_decrement["decrement"] end subgraph FIFO["fifo_fetch FIFO"] - FIFO_read["read"] FIFO_write["write"] + FIFO_read["read"] end subgraph MethodMap["core_counter_increment_discard_map MethodMap"] MethodMap_method["method"] @@ -150,9 +150,9 @@ BasicFifo2_read["read"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] subgraph Forwarder2["address_fwd Forwarder"] Forwarder2_read["read"] Forwarder2_write["write"] @@ -160,10 +160,10 @@ end subgraph ICache["icache ICache"] ICache_ICache["ICache"] - ICache_accept_res["accept_res"] - ICache_issue_req["issue_req"] ICache_ICache1["ICache"] ICache_ICache2["ICache"] + ICache_accept_res["accept_res"] + ICache_issue_req["issue_req"] ICache_ICache3["ICache"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] @@ -181,8 +181,8 @@ HwCounter4__incr["_incr"] end subgraph LatencyMeasurer["req_latency LatencyMeasurer"] - LatencyMeasurer__stop["_stop"] LatencyMeasurer__start["_start"] + LatencyMeasurer__stop["_stop"] subgraph HwExpHistogram["histogram HwExpHistogram"] HwExpHistogram__add["_add"] end @@ -196,8 +196,8 @@ FIFO2_write["write"] end subgraph Forwarder3["res_fwd Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end subgraph FRAT["FRAT FRAT"] @@ -208,20 +208,20 @@ RRAT_peek["peek"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] RegisterFile_write["write"] - RegisterFile_free["free"] RegisterFile_read2["read2"] + RegisterFile_read1["read1"] + RegisterFile_free["free"] end subgraph ReorderBuffer["ROB ReorderBuffer"] + ReorderBuffer_put["put"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_peek["peek"] ReorderBuffer_retire["retire"] - ReorderBuffer_get_indices["get_indices"] - ReorderBuffer_put["put"] + ReorderBuffer_peek["peek"] subgraph LatencyMeasurer1["perf_rob_wait_time LatencyMeasurer"] - LatencyMeasurer1__stop["_stop"] LatencyMeasurer1__start["_start"] + LatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram1["histogram HwExpHistogram"] HwExpHistogram1__add["_add"] end @@ -232,9 +232,9 @@ end end subgraph Fetch["fetch Fetch"] + Fetch_resume["resume"] Fetch_Fetch["Fetch"] Fetch_stall_exception["stall_exception"] - Fetch_resume["resume"] Fetch_Fetch1["Fetch"] subgraph BasicFifo3["fetch_target_queue BasicFifo"] BasicFifo3_read["read"] @@ -243,8 +243,8 @@ end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] ExceptionCauseRegister_report["report"] - ExceptionCauseRegister_get["get"] ExceptionCauseRegister_clear["clear"] + ExceptionCauseRegister_get["get"] subgraph BasicFifo4["fu_report_fifo BasicFifo"] BasicFifo4_write["write"] BasicFifo4_read["read"] @@ -257,8 +257,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_write["write"] Forwarder4_read["read"] + Forwarder4_write["write"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans1["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -276,20 +276,20 @@ MethodProduct1_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_get_result["get_result"] - RSFuncBlock_select["select"] - RSFuncBlock_insert["insert"] RSFuncBlock_update["update"] + RSFuncBlock_insert["insert"] + RSFuncBlock_select["select"] + RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] + RS_update["update"] RS_RS["RS"] - RS_take["take"] RS_RS1["RS"] + RS_select["select"] + RS_take["take"] RS_RS2["RS"] - RS_insert["insert"] RS_RS3["RS"] - RS_update["update"] RS_RS4["RS"] - RS_select["select"] + RS_insert["insert"] end subgraph AluFuncUnit["func_unit_0 AluFuncUnit"] AluFuncUnit_accept["accept"] @@ -306,8 +306,8 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO5["fifo FIFO"] - FIFO5_read["read"] FIFO5_write["write"] + FIFO5_read["read"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] @@ -330,8 +330,8 @@ HwCounter7__incr["_incr"] end subgraph FIFO7["fifo_res FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -341,16 +341,16 @@ ExceptionFuncUnit_accept["accept"] ExceptionFuncUnit_issue["issue"] subgraph FIFO8["fifo FIFO"] - FIFO8_write["write"] FIFO8_read["read"] + FIFO8_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] - PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_issue["issue"] + PrivilegedFuncUnit_accept["accept"] PrivilegedFuncUnit_precommit["precommit"] subgraph BasicFifo5["fetch_resume_fifo BasicFifo"] BasicFifo5_write["write"] @@ -387,41 +387,41 @@ end subgraph LSUDummy["rs_block_1 LSUDummy"] LSUDummy_select["select"] - LSUDummy_precommit["precommit"] LSUDummy_get_result["get_result"] LSUDummy_LSUDummy["LSUDummy"] LSUDummy_LSUDummy1["LSUDummy"] - LSUDummy_LSUDummy2["LSUDummy"] - LSUDummy_insert["insert"] LSUDummy_update["update"] + LSUDummy_insert["insert"] + LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_precommit["precommit"] subgraph Forwarder6["forwarder Forwarder"] - Forwarder6_read["read"] Forwarder6_write["write"] + Forwarder6_read["read"] end subgraph LSURequester["requester LSURequester"] - LSURequester_accept_cond0["accept_cond0"] - LSURequester_issue["issue"] LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept_cond1["accept_cond1"] + LSURequester_issue_cond1["issue_cond1"] LSURequester_accept["accept"] LSURequester_issue_cond2["issue_cond2"] - LSURequester_issue_cond1["issue_cond1"] - LSURequester_accept_cond1["accept_cond1"] + LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue["issue"] end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_select["select"] - CSRUnit_update["update"] - CSRUnit_precommit["precommit"] CSRUnit_get_result["get_result"] - CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_precommit["precommit"] CSRUnit_insert["insert"] + CSRUnit_CSRUnit["CSRUnit"] CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_select["select"] + CSRUnit_update["update"] end subgraph MethodTryProduct["InstructionPrecommitKey_unifier MethodTryProduct"] MethodTryProduct_MethodTryProduct["MethodTryProduct"] MethodTryProduct_MethodTryProduct1["MethodTryProduct"] - MethodTryProduct_MethodTryProduct2["MethodTryProduct"] MethodTryProduct_method["method"] + MethodTryProduct_MethodTryProduct2["MethodTryProduct"] end subgraph Collector2["FetchResumeKey_unifier Collector"] Collector2_method["method"] @@ -456,23 +456,23 @@ CSRRegister_write["write"] end subgraph CSRRegister1["mtvec CSRRegister"] - CSRRegister1__fu_write["_fu_write"] - CSRRegister1_read["read"] CSRRegister1__fu_read["_fu_read"] + CSRRegister1_read["read"] + CSRRegister1__fu_write["_fu_write"] end subgraph CSRRegister2["mepc CSRRegister"] CSRRegister2_write["write"] - CSRRegister2__fu_read["_fu_read"] - CSRRegister2_read["read"] CSRRegister2__fu_write["_fu_write"] + CSRRegister2_read["read"] + CSRRegister2__fu_read["_fu_read"] end end subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister3["register_low CSRRegister"] CSRRegister3_write["write"] - CSRRegister3__fu_read["_fu_read"] CSRRegister3_read["read"] + CSRRegister3__fu_read["_fu_read"] end subgraph CSRRegister4["register_high CSRRegister"] CSRRegister4_read["read"] @@ -506,29 +506,29 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO10["alloc_rename_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] end subgraph FIFO11["rename_out_buf FIFO"] - FIFO11_write["write"] FIFO11_read["read"] + FIFO11_write["write"] end subgraph Renaming["renaming Renaming"] Renaming_Renaming["Renaming"] end subgraph FIFO12["reg_alloc_out_buf FIFO"] - FIFO12_read["read"] FIFO12_write["write"] + FIFO12_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] end subgraph FIFO13["rs_select_out_buf FIFO"] - FIFO13_write["write"] FIFO13_read["read"] + FIFO13_write["write"] end subgraph RSSelection["rs_selector RSSelection"] RSSelection_RSSelection["RSSelection"] @@ -536,8 +536,8 @@ RSSelection_RSSelection2["RSSelection"] RSSelection_RSSelection3["RSSelection"] subgraph Forwarder8["forwarder Forwarder"] - Forwarder8_read["read"] Forwarder8_write["write"] + Forwarder8_read["read"] end end subgraph RSInsertion["rs_insertion RSInsertion"] @@ -548,25 +548,25 @@ ConnectTrans11_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] - Retirement_core_state["core_state"] Retirement_Retirement["Retirement"] + Retirement_core_state["core_state"] Retirement_Retirement1["Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement2["Retirement"] Retirement_Retirement_cond0["Retirement_cond0"] - Retirement_Retirement_cond1["Retirement_cond1"] Retirement_Retirement3["Retirement"] Retirement_Retirement4["Retirement"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister7["register_low CSRRegister"] CSRRegister7__fu_read["_fu_read"] - CSRRegister7_write["write"] CSRRegister7_read["read"] + CSRRegister7_write["write"] end subgraph CSRRegister8["register_high CSRRegister"] + CSRRegister8__fu_read["_fu_read"] CSRRegister8_read["read"] CSRRegister8_write["write"] - CSRRegister8__fu_read["_fu_read"] end end subgraph HwCounter9["perf_instr_ret HwCounter"] @@ -586,19 +586,19 @@ end end subgraph TransactionManager["transactionManager TransactionManager"] - TransactionManager_LSUDummy_accept_cond0["LSUDummy_accept_cond0"] TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] - TransactionManager_LSUDummy_accept_cond1["LSUDummy_accept_cond1"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_accept_cond1_LSUDummy["accept_cond1_LSUDummy"] TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_accept_cond0_LSUDummy["accept_cond0_LSUDummy"] TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] end end Core_InitFreeRFFifo --> BasicFifo2_write -Retirement_Retirement1 --> BasicFifo2_write -TransactionManager_Retirement_cond0_Retirement --> BasicFifo2_write +Retirement_Retirement3 --> BasicFifo2_write TransactionManager_Retirement_Retirement_cond1 --> BasicFifo2_write +TransactionManager_Retirement_Retirement_cond0 --> BasicFifo2_write FIFO6_read --> Core_DiscardBranchVerify WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write @@ -608,19 +608,19 @@ SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> BasicFifo_write SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller --> WishboneMaster_request ICache_ICache <--> HwCounter4__incr -ICache_ICache2 <--> HwCounter3__incr -ICache_ICache2 <--> HwCounter2__incr -ICache_ICache2 <--> HwCounter1__incr -ICache_ICache2 --> Forwarder3_write +ICache_ICache3 <--> HwCounter3__incr +ICache_ICache3 <--> HwCounter2__incr +ICache_ICache3 <--> HwCounter1__incr +ICache_ICache3 --> Forwarder3_write ICache_ICache1 --> SimpleCommonBusCacheRefiller_start_refill ICache_ICache1 --> Forwarder2_write -ICache_ICache3 --> Forwarder2_write -SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache3 -WishboneMasterAdapter_get_read_response --> ICache_ICache3 -Serializer_Serializer --> ICache_ICache3 -BasicFifo_read --> ICache_ICache3 -WishboneMaster_result --> ICache_ICache3 -Forwarder_read --> ICache_ICache3 +ICache_ICache2 --> Forwarder2_write +SimpleCommonBusCacheRefiller_accept_refill --> ICache_ICache2 +WishboneMasterAdapter_get_read_response --> ICache_ICache2 +Serializer_Serializer --> ICache_ICache2 +BasicFifo_read --> ICache_ICache2 +WishboneMaster_result --> ICache_ICache2 +Forwarder_read --> ICache_ICache2 Fetch_Fetch --> ICache_issue_req Fetch_Fetch <--> HwCounter__incr Fetch_Fetch <--> LatencyMeasurer__start @@ -650,7 +650,7 @@ RegAllocation_RegAllocation --> FIFO10_write FIFO10_read --> Renaming_Renaming Renaming_Renaming --> FRAT_rename -Retirement_Retirement1 --> FRAT_rename +Retirement_Retirement3 --> FRAT_rename TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename Renaming_Renaming --> FIFO11_write FIFO11_read --> ROBAllocation_ROBAllocation @@ -658,18 +658,18 @@ ROBAllocation_ROBAllocation <--> LatencyMeasurer1__start ROBAllocation_ROBAllocation --> FIFO3_write ROBAllocation_ROBAllocation --> FIFO12_write -FIFO12_read --> RSSelection_RSSelection2 -RSSelection_RSSelection2 --> Forwarder8_write -Forwarder8_read --> RSSelection_RSSelection1 -Forwarder8_read --> RSSelection_RSSelection +FIFO12_read --> RSSelection_RSSelection +RSSelection_RSSelection --> Forwarder8_write +Forwarder8_read --> RSSelection_RSSelection2 Forwarder8_read --> RSSelection_RSSelection3 -RSFuncBlock_select --> RSSelection_RSSelection1 -RS_select --> RSSelection_RSSelection1 -RSSelection_RSSelection1 --> FIFO13_write -RSSelection_RSSelection --> FIFO13_write +Forwarder8_read --> RSSelection_RSSelection1 +RSFuncBlock_select --> RSSelection_RSSelection2 +RS_select --> RSSelection_RSSelection2 +RSSelection_RSSelection2 --> FIFO13_write RSSelection_RSSelection3 --> FIFO13_write -RSSelection_RSSelection <--> LSUDummy_select -RSSelection_RSSelection3 <--> CSRUnit_select +RSSelection_RSSelection1 --> FIFO13_write +RSSelection_RSSelection3 <--> LSUDummy_select +RSSelection_RSSelection1 <--> CSRUnit_select FIFO13_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -685,7 +685,7 @@ Collector2_method --> ConnectTrans11_ConnectTrans Forwarder7_read --> ConnectTrans11_ConnectTrans ConnectTrans11_ConnectTrans --> Fetch_resume -Retirement_Retirement3 --> Fetch_resume +Retirement_Retirement1 --> Fetch_resume Collector_method --> ResultAnnouncement_ResultAnnouncement Forwarder4_read --> ResultAnnouncement_ResultAnnouncement ResultAnnouncement_ResultAnnouncement --> ReorderBuffer_mark_done @@ -695,7 +695,7 @@ ResultAnnouncement_ResultAnnouncement --> RS_update ResultAnnouncement_ResultAnnouncement --> LSUDummy_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update -RS_RS --> WakeupSelect_WakeupSelect +RS_RS2 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -703,10 +703,10 @@ RS_take --> WakeupSelect4_WakeupSelect WakeupSelect_WakeupSelect --> AluFuncUnit_issue WakeupSelect_WakeupSelect --> FIFO4_write -RS_RS4 --> WakeupSelect1_WakeupSelect +RS_RS --> WakeupSelect1_WakeupSelect WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue WakeupSelect1_WakeupSelect --> FIFO5_write -RS_RS3 --> WakeupSelect2_WakeupSelect +RS_RS4 --> WakeupSelect2_WakeupSelect WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue WakeupSelect2_WakeupSelect <--> HwCounter5__incr WakeupSelect2_WakeupSelect <--> HwCounter6__incr @@ -718,10 +718,10 @@ ConnectTrans3_ConnectTrans --> BasicFifo4_write WakeupSelect2_WakeupSelect --> FIFO7_write WakeupSelect2_WakeupSelect --> FIFO6_write -RS_RS2 --> WakeupSelect3_WakeupSelect +RS_RS1 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> FIFO8_write -RS_RS1 --> WakeupSelect4_WakeupSelect +RS_RS3 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans4_ConnectTrans --> Forwarder5_write ConnectTrans5_ConnectTrans --> Forwarder5_write @@ -739,11 +739,11 @@ PrivilegedFuncUnit_accept --> ConnectTrans8_ConnectTrans CSRRegister2_read --> ConnectTrans8_ConnectTrans ConnectTrans8_ConnectTrans --> BasicFifo5_write -LSUDummy_LSUDummy1 --> Forwarder6_write -TransactionManager_LSUDummy_accept_cond0 --> Forwarder6_write -TransactionManager_LSUDummy_accept_cond1 --> Forwarder6_write -TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write +LSUDummy_LSUDummy --> Forwarder6_write +TransactionManager_accept_cond0_LSUDummy --> Forwarder6_write TransactionManager_issue_cond1_LSUDummy --> Forwarder6_write +TransactionManager_accept_cond1_LSUDummy --> Forwarder6_write +TransactionManager_issue_cond2_LSUDummy --> Forwarder6_write TransactionManager_LSUDummy_issue_cond0 --> Forwarder6_write CSRRegister__fu_read --> CSRUnit_CSRUnit CSRUnit_CSRUnit --> CSRRegister__fu_write @@ -774,37 +774,37 @@ ConnectTrans10_ConnectTrans --> Forwarder7_write BasicFifo5_read --> ConnectTrans9_ConnectTrans CSRUnit_fetch_resume --> ConnectTrans10_ConnectTrans -ReorderBuffer_peek --> Retirement_Retirement2 +ReorderBuffer_peek --> Retirement_Retirement4 ReorderBuffer_peek --> Retirement_Retirement -ReorderBuffer_peek --> Retirement_Retirement1 -ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement +ReorderBuffer_peek --> Retirement_Retirement3 ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement2 --> MethodTryProduct_method +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement4 --> MethodTryProduct_method ExceptionCauseRegister_get --> Retirement_Retirement -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement1 <--> ReorderBuffer_retire -TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire +ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement3 <--> ReorderBuffer_retire TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire -Retirement_Retirement1 <--> LatencyMeasurer1__stop -TransactionManager_Retirement_cond0_Retirement <--> LatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire +Retirement_Retirement3 <--> LatencyMeasurer1__stop TransactionManager_Retirement_Retirement_cond1 <--> LatencyMeasurer1__stop -FIFO3_read --> Retirement_Retirement1 -FIFO3_read --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_Retirement_cond0 <--> LatencyMeasurer1__stop +FIFO3_read --> Retirement_Retirement3 FIFO3_read --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement1 --> HwExpHistogram1__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add +FIFO3_read --> TransactionManager_Retirement_Retirement_cond0 +Retirement_Retirement3 --> HwExpHistogram1__add TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add -CoreInstructionCounter_decrement --> Retirement_Retirement1 -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add +CoreInstructionCounter_decrement --> Retirement_Retirement3 CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 -RRAT_peek --> Retirement_Retirement1 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 +RRAT_peek --> Retirement_Retirement3 RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 -Retirement_Retirement1 --> RegisterFile_free -TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free +Retirement_Retirement3 --> RegisterFile_free TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free -CSRRegister1_read --> Retirement_Retirement3 -Retirement_Retirement3 <--> ExceptionCauseRegister_clear +TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free +CSRRegister1_read --> Retirement_Retirement1 +Retirement_Retirement1 <--> ExceptionCauseRegister_clear GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment CSRRegister3_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister3_write @@ -816,45 +816,19 @@ CSRRegister6_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister6_write AdapterTrans1_AdapterTrans_report_interrupt <--> InterruptController_report_interrupt -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_cond0_Retirement --> RRAT_commit -TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment -CSRRegister7_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister7_write -CSRRegister8_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write -TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement4 -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement4 -TransactionManager_Retirement_cond0_Retirement --> CSRRegister_write -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister2_write -TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write -TransactionManager_Retirement_cond0_Retirement <--> InterruptController_entry -TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry -TransactionManager_LSUDummy_accept_cond0 <--> LSUDummy_LSUDummy2 -TransactionManager_LSUDummy_accept_cond1 <--> LSUDummy_LSUDummy2 -LSURequester_accept --> TransactionManager_LSUDummy_accept_cond0 -LSURequester_accept --> TransactionManager_LSUDummy_accept_cond1 -TransactionManager_LSUDummy_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_LSUDummy_accept_cond0 -Serializer1_Serializer2 --> TransactionManager_LSUDummy_accept_cond0 -BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond0 -BasicFifo1_read --> TransactionManager_LSUDummy_accept_cond1 -WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond0 -WishboneMaster1_result --> TransactionManager_LSUDummy_accept_cond1 -Forwarder1_read --> TransactionManager_LSUDummy_accept_cond0 -Forwarder1_read --> TransactionManager_LSUDummy_accept_cond1 -TransactionManager_LSUDummy_accept_cond1 <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_LSUDummy_accept_cond1 -Serializer1_Serializer --> TransactionManager_LSUDummy_accept_cond1 -TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 -TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy -TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy -TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy -TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue -TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue +TransactionManager_accept_cond0_LSUDummy <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_accept_cond0_LSUDummy +Serializer1_Serializer1 --> TransactionManager_accept_cond0_LSUDummy +BasicFifo1_read --> TransactionManager_accept_cond0_LSUDummy +BasicFifo1_read --> TransactionManager_accept_cond1_LSUDummy +WishboneMaster1_result --> TransactionManager_accept_cond0_LSUDummy +WishboneMaster1_result --> TransactionManager_accept_cond1_LSUDummy +Forwarder1_read --> TransactionManager_accept_cond0_LSUDummy +Forwarder1_read --> TransactionManager_accept_cond1_LSUDummy +TransactionManager_accept_cond0_LSUDummy <--> LSUDummy_LSUDummy2 +TransactionManager_accept_cond1_LSUDummy <--> LSUDummy_LSUDummy2 +LSURequester_accept --> TransactionManager_accept_cond0_LSUDummy +LSURequester_accept --> TransactionManager_accept_cond1_LSUDummy TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer3 @@ -862,10 +836,36 @@ TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request +TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy1 +TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy1 +TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue +TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement2 +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement2 +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister_write +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister2_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister2_write +TransactionManager_Retirement_Retirement_cond1 <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond0 <--> InterruptController_entry +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 +TransactionManager_accept_cond1_LSUDummy <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_accept_cond1_LSUDummy +Serializer1_Serializer2 --> TransactionManager_accept_cond1_LSUDummy +TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit +TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment +CSRRegister7_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister7_write +CSRRegister8_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write -TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 -TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 +TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer @@ -876,7 +876,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/components/icache.html b/components/icache.html index 2248aee2b..03fa589fb 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.backend.html b/coreblocks.backend.html index b69f84a3c..94151eb8b 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -165,7 +165,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.cache.html b/coreblocks.cache.html index cc1ff1124..a35b67546 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -241,7 +241,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index 41fe2d121..aba25cb8a 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -157,7 +157,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index fcf62dde7..188a69710 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -1721,7 +1721,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index 459a6273b..7e36c306f 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -161,7 +161,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index 202e2cda4..65b0d6179 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -125,7 +125,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index e40e71896..ce7f0dfb6 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -867,7 +867,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index 338f960f5..2d377b5e6 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -238,7 +238,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index a82c857d3..d4c1990ee 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -148,7 +148,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index cd0cae79c..cdb218165 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -169,7 +169,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.func_blocks.lsu.html b/coreblocks.func_blocks.lsu.html index 81caf5183..53f867cc7 100644 --- a/coreblocks.func_blocks.lsu.html +++ b/coreblocks.func_blocks.lsu.html @@ -248,7 +248,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.html b/coreblocks.html index 8c96322b1..3ed06075c 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -255,7 +255,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.params.html b/coreblocks.params.html index d1b472c46..7da248309 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -719,7 +719,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index 73a818f34..79516d2d8 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -746,7 +746,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html index 70936b4a7..4d06e931e 100644 --- a/coreblocks.priv.csr.html +++ b/coreblocks.priv.csr.html @@ -327,7 +327,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.priv.html b/coreblocks.priv.html index 1a1eeeb85..a65b28cff 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -123,7 +123,7 @@

Subpackages

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index 37dfbddb6..5bf1c440c 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -171,7 +171,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 1898975c2..446bb2f88 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/current-graph.html b/current-graph.html index 44e71de75..817549ce1 100644 --- a/current-graph.html +++ b/current-graph.html @@ -96,17 +96,17 @@

Full transaction-method graph

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/development-environment.html b/development-environment.html index b5f4f3e33..9a0f58734 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/genindex.html b/genindex.html index fbab25555..499a975c7 100644 --- a/genindex.html +++ b/genindex.html @@ -3737,7 +3737,7 @@

Z

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/home.html b/home.html index 5d846c2a2..82d0d0b4a 100644 --- a/home.html +++ b/home.html @@ -129,7 +129,7 @@

Documentation

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/index.html b/index.html index 98e8d47e7..9284b5274 100644 --- a/index.html +++ b/index.html @@ -229,7 +229,7 @@

Coreblocks

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html index a12c4c811..20e76037e 100644 --- a/miscellany/exceptions-summary.html +++ b/miscellany/exceptions-summary.html @@ -271,7 +271,7 @@

Summary

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/modules-coreblocks.html b/modules-coreblocks.html index 78ab3c4b6..c884c409f 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -168,7 +168,7 @@

coreblocks

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/modules-transactron.html b/modules-transactron.html index ede59e378..4577eff58 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -161,7 +161,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/problem-checklist.html b/problem-checklist.html index 7c237202f..9e7486d28 100644 --- a/problem-checklist.html +++ b/problem-checklist.html @@ -105,7 +105,7 @@

Problem checklist

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/py-modindex.html b/py-modindex.html index 61db9fad1..eacb84315 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -668,7 +668,7 @@

Python Module Index

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/scheduler/overview.html b/scheduler/overview.html index f7a06ff02..6142305e4 100644 --- a/scheduler/overview.html +++ b/scheduler/overview.html @@ -146,7 +146,7 @@

More detailed description of each block

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/search.html b/search.html index 27e69d91a..d5e8abb99 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/shared-structs/implementation/rs-impl.html b/shared-structs/implementation/rs-impl.html index b6aec2c9e..dba7f425a 100644 --- a/shared-structs/implementation/rs-impl.html +++ b/shared-structs/implementation/rs-impl.html @@ -252,7 +252,7 @@

Read and clean row

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/shared-structs/rs.html b/shared-structs/rs.html index 64fbf6da6..0806582c1 100644 --- a/shared-structs/rs.html +++ b/shared-structs/rs.html @@ -222,7 +222,7 @@

External interface signals

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/synthesis/synthesis.html b/synthesis/synthesis.html index 334e45d90..65003bd5d 100644 --- a/synthesis/synthesis.html +++ b/synthesis/synthesis.html @@ -266,7 +266,7 @@

Regression tests manual execution

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/transactions.html b/transactions.html index 726effd83..50c7f12bc 100644 --- a/transactions.html +++ b/transactions.html @@ -409,7 +409,7 @@

Transaction and method nesting

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/transactron.core.html b/transactron.core.html index c90842b8d..5d59ab655 100644 --- a/transactron.core.html +++ b/transactron.core.html @@ -860,7 +860,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/transactron.html b/transactron.html index 3ccfc7e37..8dc26143d 100644 --- a/transactron.html +++ b/transactron.html @@ -751,7 +751,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/transactron.lib.html b/transactron.lib.html index 3cd620f7c..978e25638 100644 --- a/transactron.lib.html +++ b/transactron.lib.html @@ -1916,7 +1916,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/transactron.testing.html b/transactron.testing.html index e92c5ba96..1eb9eb292 100644 --- a/transactron.testing.html +++ b/transactron.testing.html @@ -408,7 +408,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/transactron.utils.amaranth_ext.html b/transactron.utils.amaranth_ext.html index 92dd90f00..24fe7d4b6 100644 --- a/transactron.utils.amaranth_ext.html +++ b/transactron.utils.amaranth_ext.html @@ -293,7 +293,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.

diff --git a/transactron.utils.html b/transactron.utils.html index d9e700395..23e8d8adc 100644 --- a/transactron.utils.html +++ b/transactron.utils.html @@ -792,7 +792,7 @@

Submodules

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:58 2024-03-21. + Last updated on 21:57 2024-03-21.