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hruby_simulator.vcd
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hruby_simulator.vcd
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$date
02 01 2021 02:06
$end
$version
Generated from HDLRuby simulator
$end
$comment
Is it an easter egg?
$end
$timescale 1ps $end
$scope module __$T0 $end
$var wire 1 __$T0$__$T$clk clk $end
$var wire 1 __$T0$__$T$rst rst $end
$var wire 1 __$T0$__$T$req req $end
$var wire 1 __$T0$__$T$fill fill $end
$var wire 1 __$T0$__$T$ack_fill ack_fill $end
$var wire 1 __$T0$__$T$ack_network ack_network $end
$scope module neural_network $end
$var wire 1 neural_network$T0$clk clk $end
$var wire 1 neural_network$T0$rst rst $end
$var wire 1 neural_network$T0$req req $end
$var wire 1 neural_network$T0$fill fill $end
$var wire 8 neural_network$T0$$10 $10 $end
$var wire 1 neural_network$T0$ack_fill ack_fill $end
$var wire 1 neural_network$T0$ack_network ack_network $end
$var wire 1 neural_network$T0$$8 $8 $end
$var wire 1 neural_network$T0$$9 $9 $end
$var wire 1 neural_network$T0$$32 $32 $end
$var wire 1 neural_network$T0$$33 $33 $end
$var wire 8 neural_network$T0$$34 $34 $end
$var wire 1 neural_network$T0$neural_network$T$ack_0 ack_0 $end
$var wire 1 neural_network$T0$neural_network$T$ack_1 ack_1 $end
$var wire 1 neural_network$T0$neural_network$T$fill_inputs fill_inputs $end
$var wire 8 neural_network$T0$neural_network$T$value_inputs value_inputs $end
$var wire 2 neural_network$T0$neural_network$T$address_inputs address_inputs $end
$var wire 1 neural_network$T0$neural_network$T$flag_inputs flag_inputs $end
$var wire 1 neural_network$T0$neural_network$T$ack_inputs ack_inputs $end
$var wire 1 neural_network$T0$neural_network$T$$61 $61 $end
$var wire 1 neural_network$T0$neural_network$T$$62 $62 $end
$var wire 8 neural_network$T0$neural_network$T$$63 $63 $end
$var wire 1 neural_network$T0$neural_network$T$fill_outputs fill_outputs $end
$var wire 8 neural_network$T0$neural_network$T$value_outputs value_outputs $end
$var wire 1 neural_network$T0$neural_network$T$address_outputs address_outputs $end
$var wire 1 neural_network$T0$neural_network$T$flag_outputs flag_outputs $end
$var wire 8 neural_network$T0$neural_network$T$$84 $84 $end
$var wire 1 neural_network$T0$neural_network$T$$85 $85 $end
$scope module layer0 $end
$var wire 1 layer0$T0$clk clk $end
$var wire 1 layer0$T0$rst rst $end
$var wire 1 layer0$T0$req req $end
$var wire 8 layer0$T0$$59 $59 $end
$var wire 1 layer0$T0$ack_layer ack_layer $end
$var wire 1 layer0$T0$$57 $57 $end
$var wire 1 layer0$T0$$58 $58 $end
$var wire 8 layer0$T0$$99 $99 $end
$var wire 8 layer0$T0$$100 $100 $end
$var wire 1 layer0$T0$layer0$T$req_mac req_mac $end
$var wire 1 layer0$T0$layer0$T$ack ack $end
$var wire 1 layer0$T0$layer0$T$ack_mac ack_mac $end
$var wire 1 layer0$T0$layer0$T$ack_add ack_add $end
$var wire 8 layer0$T0$layer0$T$$136 $136 $end
$var wire 1 layer0$T0$layer0$T$$134 $134 $end
$var wire 1 layer0$T0$layer0$T$$135 $135 $end
$var wire 8 layer0$T0$layer0$T$$159 $159 $end
$var wire 8 layer0$T0$layer0$T$$160 $160 $end
$var wire 8 layer0$T0$layer0$T$$151 $151 $end
$var wire 1 layer0$T0$layer0$T$$149 $149 $end
$var wire 1 layer0$T0$layer0$T$$150 $150 $end
$var wire 8 layer0$T0$layer0$T$$200 $200 $end
$var wire 1 layer0$T0$layer0$T$$201 $201 $end
$var wire 1 layer0$T0$layer0$T$$198 $198 $end
$var wire 1 layer0$T0$layer0$T$$199 $199 $end
$var wire 8 layer0$T0$layer0$T$$228 $228 $end
$var wire 8 layer0$T0$layer0$T$$229 $229 $end
$var wire 8 layer0$T0$layer0$T$$215 $215 $end
$var wire 1 layer0$T0$layer0$T$$216 $216 $end
$var wire 1 layer0$T0$layer0$T$$213 $213 $end
$var wire 1 layer0$T0$layer0$T$$214 $214 $end
$var wire 8 layer0$T0$layer0$T$value_z0 value_z0 $end
$var wire 8 layer0$T0$layer0$T$value_z1 value_z1 $end
$var wire 8 layer0$T0$layer0$T$value_a0 value_a0 $end
$var wire 8 layer0$T0$layer0$T$value_a1 value_a1 $end
$var wire 1 layer0$T0$layer0$T$flag_z0 flag_z0 $end
$var wire 1 layer0$T0$layer0$T$flag_z1 flag_z1 $end
$var wire 1 layer0$T0$layer0$T$ack_a0 ack_a0 $end
$var wire 1 layer0$T0$layer0$T$ack_a1 ack_a1 $end
$scope module counter $end
$var wire 1 counter$T1$clk clk $end
$var wire 1 counter$T1$ack ack $end
$var wire 1 counter$T1$rst rst $end
$var wire 1 counter$T1$ack_mac ack_mac $end
$var wire 2 counter$T1$counter$T$q q $end
$upscope $end
$scope module func0 $end
$var wire 8 func0$T1$z_value z_value $end
$var wire 8 func0$T1$a a $end
$var wire 8 func0$T1$func0$T$base base $end
$var wire 8 func0$T1$func0$T$next_data next_data $end
$var wire 4 func0$T1$func0$T$address address $end
$var wire 8 func0$T1$func0$T$remaining remaining $end
$var wire 8 func0$T1$func0$T$change change $end
$scope module my_lut $end
$var wire 4 my_lut$T2$address address $end
$var wire 8 my_lut$T2$base base $end
$var wire 8 my_lut$T2$next_data next_data $end
$var wire 128 my_lut$T2$my_lut$T$lut lut $end
$upscope $end
$scope module my_interpolator $end
$var wire 8 my_interpolator$T2$base base $end
$var wire 8 my_interpolator$T2$next_data next_data $end
$var wire 8 my_interpolator$T2$remaining remaining $end
$var wire 8 my_interpolator$T2$interpolated_value interpolated_value $end
$upscope $end
$upscope $end
$scope module func1 $end
$var wire 8 func1$T0$z_value z_value $end
$var wire 8 func1$T0$a a $end
$var wire 8 func1$T0$func1$T$base base $end
$var wire 8 func1$T0$func1$T$next_data next_data $end
$var wire 4 func1$T0$func1$T$address address $end
$var wire 8 func1$T0$func1$T$remaining remaining $end
$var wire 8 func1$T0$func1$T$change change $end
$scope module my_lut $end
$var wire 4 my_lut$T00$address address $end
$var wire 8 my_lut$T00$base base $end
$var wire 8 my_lut$T00$next_data next_data $end
$var wire 128 my_lut$T00$my_lut$T0$lut lut $end
$upscope $end
$scope module my_interpolator $end
$var wire 8 my_interpolator$T00$base base $end
$var wire 8 my_interpolator$T00$next_data next_data $end
$var wire 8 my_interpolator$T00$remaining remaining $end
$var wire 8 my_interpolator$T00$interpolated_value interpolated_value $end
$upscope $end
$upscope $end
$scope module channel_w0$127 $end
$var wire 1 layer0$T0$layer0$T$channel_w0$127$trig_r trig_r $end
$var wire 8 layer0$T0$layer0$T$channel_w0$127$dbus_r dbus_r $end
$var wire 1 layer0$T0$layer0$T$channel_w0$127$abus_r abus_r $end
$var wire 16 layer0$T0$layer0$T$channel_w0$127$mem mem $end
$upscope $end
$scope module channel_w1$142 $end
$var wire 1 layer0$T0$layer0$T$channel_w1$142$trig_r trig_r $end
$var wire 8 layer0$T0$layer0$T$channel_w1$142$dbus_r dbus_r $end
$var wire 1 layer0$T0$layer0$T$channel_w1$142$abus_r abus_r $end
$var wire 16 layer0$T0$layer0$T$channel_w1$142$mem mem $end
$upscope $end
$scope module channel_accum$157 $end
$var wire 8 layer0$T0$layer0$T$channel_accum$157$reg_0 reg_0 $end
$var wire 8 layer0$T0$layer0$T$channel_accum$157$reg_1 reg_1 $end
$scope module rinc$169 $end
$var wire 1 layer0$T0$layer0$T$channel_accum$157$rinc$169$abus_r abus_r $end
$upscope $end
$scope module winc$174 $end
$var wire 1 layer0$T0$layer0$T$channel_accum$157$winc$174$abus_w abus_w $end
$upscope $end
$scope module rdec$179 $end
$var wire 1 layer0$T0$layer0$T$channel_accum$157$rdec$179$abus_r abus_r $end
$upscope $end
$scope module wdec$184 $end
$var wire 1 layer0$T0$layer0$T$channel_accum$157$wdec$184$abus_w abus_w $end
$upscope $end
$upscope $end
$scope module mac_n1$189 $end
$var wire 8 layer0$T0$layer0$T$mac_n1$189$lv0 lv0 $end
$var wire 8 layer0$T0$layer0$T$mac_n1$189$lv1 lv1 $end
$var wire 8 layer0$T0$layer0$T$mac_n1$189$av0 av0 $end
$var wire 8 layer0$T0$layer0$T$mac_n1$189$av1 av1 $end
$var wire 8 layer0$T0$layer0$T$mac_n1$189$rv rv $end
$var wire 1 layer0$T0$layer0$T$mac_n1$189$lvok0 lvok0 $end
$var wire 1 layer0$T0$layer0$T$mac_n1$189$lvok1 lvok1 $end
$var wire 1 layer0$T0$layer0$T$mac_n1$189$rvok rvok $end
$var wire 1 layer0$T0$layer0$T$mac_n1$189$wok0 wok0 $end
$var wire 1 layer0$T0$layer0$T$mac_n1$189$wok1 wok1 $end
$var wire 1 layer0$T0$layer0$T$mac_n1$189$run run $end
$upscope $end
$scope module channel_b0$196 $end
$var wire 1 layer0$T0$layer0$T$channel_b0$196$trig_r trig_r $end
$var wire 8 layer0$T0$layer0$T$channel_b0$196$dbus_r dbus_r $end
$var wire 1 layer0$T0$layer0$T$channel_b0$196$abus_r abus_r $end
$var wire 8 layer0$T0$layer0$T$channel_b0$196$mem mem $end
$upscope $end
$scope module channel_b1$211 $end
$var wire 1 layer0$T0$layer0$T$channel_b1$211$trig_r trig_r $end
$var wire 8 layer0$T0$layer0$T$channel_b1$211$dbus_r dbus_r $end
$var wire 1 layer0$T0$layer0$T$channel_b1$211$abus_r abus_r $end
$var wire 8 layer0$T0$layer0$T$channel_b1$211$mem mem $end
$upscope $end
$scope module channel_z$226 $end
$var wire 8 layer0$T0$layer0$T$channel_z$226$reg_0 reg_0 $end
$var wire 8 layer0$T0$layer0$T$channel_z$226$reg_1 reg_1 $end
$scope module rinc$238 $end
$var wire 1 layer0$T0$layer0$T$channel_z$226$rinc$238$abus_r abus_r $end
$upscope $end
$scope module winc$242 $end
$var wire 1 layer0$T0$layer0$T$channel_z$226$winc$242$abus_w abus_w $end
$upscope $end
$scope module rdec$246 $end
$var wire 1 layer0$T0$layer0$T$channel_z$226$rdec$246$abus_r abus_r $end
$upscope $end
$scope module wdec$251 $end
$var wire 1 layer0$T0$layer0$T$channel_z$226$wdec$251$abus_w abus_w $end
$upscope $end
$upscope $end
$scope module add_n$256 $end
$var wire 8 layer0$T0$layer0$T$add_n$256$lv0 lv0 $end
$var wire 8 layer0$T0$layer0$T$add_n$256$lv1 lv1 $end
$var wire 8 layer0$T0$layer0$T$add_n$256$rv0 rv0 $end
$var wire 8 layer0$T0$layer0$T$add_n$256$rv1 rv1 $end
$var wire 1 layer0$T0$layer0$T$add_n$256$lvok0 lvok0 $end
$var wire 1 layer0$T0$layer0$T$add_n$256$lvok1 lvok1 $end
$var wire 1 layer0$T0$layer0$T$add_n$256$rvok0 rvok0 $end
$var wire 1 layer0$T0$layer0$T$add_n$256$rvok1 rvok1 $end
$var wire 1 layer0$T0$layer0$T$add_n$256$run run $end
$upscope $end
$upscope $end
$scope module layer1 $end
$var wire 1 layer1$T0$clk clk $end
$var wire 1 layer1$T0$rst rst $end
$var wire 1 layer1$T0$req req $end
$var wire 8 layer1$T0$$110 $110 $end
$var wire 8 layer1$T0$$111 $111 $end
$var wire 1 layer1$T0$ack_layer ack_layer $end
$var wire 1 layer1$T0$$112 $112 $end
$var wire 8 layer1$T0$$76 $76 $end
$var wire 1 layer1$T0$layer1$T$req_mac req_mac $end
$var wire 1 layer1$T0$layer1$T$ack ack $end
$var wire 1 layer1$T0$layer1$T$ack_mac ack_mac $end
$var wire 1 layer1$T0$layer1$T$ack_add ack_add $end
$var wire 8 layer1$T0$layer1$T$$276 $276 $end
$var wire 1 layer1$T0$layer1$T$$274 $274 $end
$var wire 1 layer1$T0$layer1$T$$275 $275 $end
$var wire 8 layer1$T0$layer1$T$$284 $284 $end
$var wire 8 layer1$T0$layer1$T$$316 $316 $end
$var wire 1 layer1$T0$layer1$T$$317 $317 $end
$var wire 1 layer1$T0$layer1$T$$314 $314 $end
$var wire 1 layer1$T0$layer1$T$$315 $315 $end
$var wire 8 layer1$T0$layer1$T$$329 $329 $end
$var wire 8 layer1$T0$layer1$T$value_z0 value_z0 $end
$var wire 8 layer1$T0$layer1$T$value_a0 value_a0 $end
$var wire 1 layer1$T0$layer1$T$flag_z0 flag_z0 $end
$var wire 1 layer1$T0$layer1$T$ack_a0 ack_a0 $end
$scope module counter $end
$var wire 1 counter$T00$clk clk $end
$var wire 1 counter$T00$ack ack $end
$var wire 1 counter$T00$rst rst $end
$var wire 1 counter$T00$ack_mac ack_mac $end
$var wire 2 counter$T00$counter$T0$q q $end
$upscope $end
$scope module func0 $end
$var wire 8 func0$T00$z_value z_value $end
$var wire 8 func0$T00$a a $end
$var wire 8 func0$T00$func0$T0$base base $end
$var wire 8 func0$T00$func0$T0$next_data next_data $end
$var wire 4 func0$T00$func0$T0$address address $end
$var wire 8 func0$T00$func0$T0$remaining remaining $end
$var wire 8 func0$T00$func0$T0$change change $end
$scope module my_lut $end
$var wire 4 my_lut$T10$address address $end
$var wire 8 my_lut$T10$base base $end
$var wire 8 my_lut$T10$next_data next_data $end
$var wire 128 my_lut$T10$my_lut$T1$lut lut $end
$upscope $end
$scope module my_interpolator $end
$var wire 8 my_interpolator$T10$base base $end
$var wire 8 my_interpolator$T10$next_data next_data $end
$var wire 8 my_interpolator$T10$remaining remaining $end
$var wire 8 my_interpolator$T10$interpolated_value interpolated_value $end
$upscope $end
$upscope $end
$scope module channel_w0$267 $end
$var wire 1 layer1$T0$layer1$T$channel_w0$267$trig_r trig_r $end
$var wire 8 layer1$T0$layer1$T$channel_w0$267$dbus_r dbus_r $end
$var wire 1 layer1$T0$layer1$T$channel_w0$267$abus_r abus_r $end
$var wire 16 layer1$T0$layer1$T$channel_w0$267$mem mem $end
$upscope $end
$scope module channel_accum$282 $end
$var wire 8 layer1$T0$layer1$T$channel_accum$282$reg_0 reg_0 $end
$scope module rinc$291 $end
$var wire 1 layer1$T0$layer1$T$channel_accum$282$rinc$291$abus_r abus_r $end
$upscope $end
$scope module winc$295 $end
$var wire 1 layer1$T0$layer1$T$channel_accum$282$winc$295$abus_w abus_w $end
$upscope $end
$scope module rdec$299 $end
$var wire 1 layer1$T0$layer1$T$channel_accum$282$rdec$299$abus_r abus_r $end
$upscope $end
$scope module wdec$303 $end
$var wire 1 layer1$T0$layer1$T$channel_accum$282$wdec$303$abus_w abus_w $end
$upscope $end
$upscope $end
$scope module mac_n1$307 $end
$var wire 8 layer1$T0$layer1$T$mac_n1$307$lv0 lv0 $end
$var wire 8 layer1$T0$layer1$T$mac_n1$307$av0 av0 $end
$var wire 8 layer1$T0$layer1$T$mac_n1$307$rv rv $end
$var wire 1 layer1$T0$layer1$T$mac_n1$307$lvok0 lvok0 $end
$var wire 1 layer1$T0$layer1$T$mac_n1$307$rvok rvok $end
$var wire 1 layer1$T0$layer1$T$mac_n1$307$wok0 wok0 $end
$var wire 1 layer1$T0$layer1$T$mac_n1$307$run run $end
$upscope $end
$scope module channel_b0$312 $end
$var wire 1 layer1$T0$layer1$T$channel_b0$312$trig_r trig_r $end
$var wire 8 layer1$T0$layer1$T$channel_b0$312$dbus_r dbus_r $end
$var wire 1 layer1$T0$layer1$T$channel_b0$312$abus_r abus_r $end
$var wire 8 layer1$T0$layer1$T$channel_b0$312$mem mem $end
$upscope $end
$scope module channel_z$327 $end
$var wire 8 layer1$T0$layer1$T$channel_z$327$reg_0 reg_0 $end
$scope module rinc$336 $end
$var wire 1 layer1$T0$layer1$T$channel_z$327$rinc$336$abus_r abus_r $end
$upscope $end
$scope module winc$339 $end
$var wire 1 layer1$T0$layer1$T$channel_z$327$winc$339$abus_w abus_w $end
$upscope $end
$scope module rdec$342 $end
$var wire 1 layer1$T0$layer1$T$channel_z$327$rdec$342$abus_r abus_r $end
$upscope $end
$scope module wdec$346 $end
$var wire 1 layer1$T0$layer1$T$channel_z$327$wdec$346$abus_w abus_w $end
$upscope $end
$upscope $end
$scope module add_n$350 $end
$var wire 8 layer1$T0$layer1$T$add_n$350$lv0 lv0 $end
$var wire 8 layer1$T0$layer1$T$add_n$350$rv0 rv0 $end
$var wire 1 layer1$T0$layer1$T$add_n$350$lvok0 lvok0 $end
$var wire 1 layer1$T0$layer1$T$add_n$350$rvok0 rvok0 $end
$var wire 1 layer1$T0$layer1$T$add_n$350$run run $end
$upscope $end
$upscope $end
$scope module channel_inputs$45 $end
$var wire 1 neural_network$T0$neural_network$T$channel_inputs$45$trig_r trig_r $end
$var wire 1 neural_network$T0$neural_network$T$channel_inputs$45$trig_w trig_w $end
$var wire 8 neural_network$T0$neural_network$T$channel_inputs$45$dbus_r dbus_r $end
$var wire 8 neural_network$T0$neural_network$T$channel_inputs$45$dbus_w dbus_w $end
$var wire 1 neural_network$T0$neural_network$T$channel_inputs$45$abus_r abus_r $end
$var wire 1 neural_network$T0$neural_network$T$channel_inputs$45$abus_w abus_w $end
$var wire 16 neural_network$T0$neural_network$T$channel_inputs$45$mem mem $end
$scope module rinc$56 $end
$upscope $end
$upscope $end
$scope module channel_outputs$74 $end
$var wire 8 neural_network$T0$neural_network$T$channel_outputs$74$reg_0 reg_0 $end
$scope module anum$75 $end
$upscope $end
$scope module rinc$83 $end
$var wire 1 neural_network$T0$neural_network$T$channel_outputs$74$rinc$83$abus_r abus_r $end
$upscope $end
$scope module winc$86 $end
$var wire 1 neural_network$T0$neural_network$T$channel_outputs$74$winc$86$abus_w abus_w $end
$upscope $end
$scope module rdec$89 $end
$var wire 1 neural_network$T0$neural_network$T$channel_outputs$74$rdec$89$abus_r abus_r $end
$upscope $end
$scope module wdec$93 $end
$var wire 1 neural_network$T0$neural_network$T$channel_outputs$74$wdec$93$abus_w abus_w $end
$upscope $end
$upscope $end
$scope module channel_a0$97 $end
$var wire 8 neural_network$T0$neural_network$T$channel_a0$97$reg_0 reg_0 $end
$var wire 8 neural_network$T0$neural_network$T$channel_a0$97$reg_1 reg_1 $end
$scope module anum$98 $end
$upscope $end
$scope module rinc$109 $end
$var wire 1 neural_network$T0$neural_network$T$channel_a0$97$rinc$109$abus_r abus_r $end
$upscope $end
$scope module winc$113 $end
$var wire 1 neural_network$T0$neural_network$T$channel_a0$97$winc$113$abus_w abus_w $end
$upscope $end
$scope module rdec$117 $end
$var wire 1 neural_network$T0$neural_network$T$channel_a0$97$rdec$117$abus_r abus_r $end
$upscope $end
$scope module wdec$122 $end
$var wire 1 neural_network$T0$neural_network$T$channel_a0$97$wdec$122$abus_w abus_w $end
$upscope $end
$upscope $end
$upscope $end
$scope module rom_inputs$1 $end
$var wire 1 __$T0$__$T$rom_inputs$1$trig_r trig_r $end
$var wire 8 __$T0$__$T$rom_inputs$1$dbus_r dbus_r $end
$var wire 1 __$T0$__$T$rom_inputs$1$abus_r abus_r $end
$var wire 16 __$T0$__$T$rom_inputs$1$mem mem $end
$scope module rinc$7 $end
$upscope $end
$upscope $end
$scope module ram_outputs$16 $end
$var wire 1 __$T0$__$T$ram_outputs$16$trig_r trig_r $end
$var wire 1 __$T0$__$T$ram_outputs$16$trig_w trig_w $end
$var wire 8 __$T0$__$T$ram_outputs$16$dbus_r dbus_r $end
$var wire 8 __$T0$__$T$ram_outputs$16$dbus_w dbus_w $end
$var wire 1 __$T0$__$T$ram_outputs$16$abus_r abus_r $end
$var wire 1 __$T0$__$T$ram_outputs$16$abus_w abus_w $end
$var wire 8 __$T0$__$T$ram_outputs$16$mem mem $end
$scope module winc$31 $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
bxxxxxxxx my_interpolator$T10$base
bxxxxxxxx my_interpolator$T10$next_data
bxxxxxxxx my_interpolator$T10$remaining
bxxxxxxxx my_interpolator$T10$interpolated_value
bxxxx my_lut$T10$address
bxxxxxxxx my_lut$T10$base
bxxxxxxxx my_lut$T10$next_data
b11110000111000001101000011000000101100001010000010010000100000000111000001100000010100000100000000110000001000000001000000000000 my_lut$T10$my_lut$T1$lut
bxxxxxxxx func0$T00$z_value
bxxxxxxxx func0$T00$a
bxxxxxxxx func0$T00$func0$T0$base
bxxxxxxxx func0$T00$func0$T0$next_data
bxxxx func0$T00$func0$T0$address
bxxxxxxxx func0$T00$func0$T0$remaining
bxxxxxxxx func0$T00$func0$T0$change
bx counter$T00$clk
bx counter$T00$ack
bx counter$T00$rst
bx counter$T00$ack_mac
bxx counter$T00$counter$T0$q
bx layer1$T0$clk
bx layer1$T0$rst
bx layer1$T0$req
bxxxxxxxx layer1$T0$$110
bxxxxxxxx layer1$T0$$111
bx layer1$T0$ack_layer
bx layer1$T0$$112
bxxxxxxxx layer1$T0$$76
bx layer1$T0$layer1$T$req_mac
bx layer1$T0$layer1$T$ack
bx layer1$T0$layer1$T$ack_mac
bx layer1$T0$layer1$T$ack_add
bxxxxxxxx layer1$T0$layer1$T$$276
bx layer1$T0$layer1$T$$274
bx layer1$T0$layer1$T$$275
bxxxxxxxx layer1$T0$layer1$T$$284
bxxxxxxxx layer1$T0$layer1$T$$316
bx layer1$T0$layer1$T$$317
bx layer1$T0$layer1$T$$314
bx layer1$T0$layer1$T$$315
bxxxxxxxx layer1$T0$layer1$T$$329
bxxxxxxxx layer1$T0$layer1$T$value_z0
bxxxxxxxx layer1$T0$layer1$T$value_a0
bx layer1$T0$layer1$T$flag_z0
bx layer1$T0$layer1$T$ack_a0
bx layer1$T0$layer1$T$channel_w0$267$trig_r
bxxxxxxxx layer1$T0$layer1$T$channel_w0$267$dbus_r
bx layer1$T0$layer1$T$channel_w0$267$abus_r
b0000110100010100 layer1$T0$layer1$T$channel_w0$267$mem
bxxxxxxxx layer1$T0$layer1$T$channel_accum$282$reg_0
bx layer1$T0$layer1$T$channel_accum$282$rinc$291$abus_r
bx layer1$T0$layer1$T$channel_accum$282$winc$295$abus_w
bx layer1$T0$layer1$T$channel_accum$282$rdec$299$abus_r
bx layer1$T0$layer1$T$channel_accum$282$wdec$303$abus_w
bxxxxxxxx layer1$T0$layer1$T$mac_n1$307$lv0
bxxxxxxxx layer1$T0$layer1$T$mac_n1$307$av0
bxxxxxxxx layer1$T0$layer1$T$mac_n1$307$rv
bx layer1$T0$layer1$T$mac_n1$307$lvok0
bx layer1$T0$layer1$T$mac_n1$307$rvok
bx layer1$T0$layer1$T$mac_n1$307$wok0
bx layer1$T0$layer1$T$mac_n1$307$run
bx layer1$T0$layer1$T$channel_b0$312$trig_r
bxxxxxxxx layer1$T0$layer1$T$channel_b0$312$dbus_r
bx layer1$T0$layer1$T$channel_b0$312$abus_r
b11111110 layer1$T0$layer1$T$channel_b0$312$mem
bxxxxxxxx layer1$T0$layer1$T$channel_z$327$reg_0
bx layer1$T0$layer1$T$channel_z$327$rinc$336$abus_r
bx layer1$T0$layer1$T$channel_z$327$winc$339$abus_w
bx layer1$T0$layer1$T$channel_z$327$rdec$342$abus_r
bx layer1$T0$layer1$T$channel_z$327$wdec$346$abus_w
bxxxxxxxx layer1$T0$layer1$T$add_n$350$lv0
bxxxxxxxx layer1$T0$layer1$T$add_n$350$rv0
bx layer1$T0$layer1$T$add_n$350$lvok0
bx layer1$T0$layer1$T$add_n$350$rvok0
bx layer1$T0$layer1$T$add_n$350$run
bxxxxxxxx my_interpolator$T00$base
bxxxxxxxx my_interpolator$T00$next_data
bxxxxxxxx my_interpolator$T00$remaining
bxxxxxxxx my_interpolator$T00$interpolated_value
bxxxx my_lut$T00$address
bxxxxxxxx my_lut$T00$base
bxxxxxxxx my_lut$T00$next_data
b00000000000000000000000000000000000000000000000000000000000000000111000001100000010100000100000000110000001000000001000000000000 my_lut$T00$my_lut$T0$lut
bxxxxxxxx func1$T0$z_value
bxxxxxxxx func1$T0$a
bxxxxxxxx func1$T0$func1$T$base
bxxxxxxxx func1$T0$func1$T$next_data
bxxxx func1$T0$func1$T$address
bxxxxxxxx func1$T0$func1$T$remaining
bxxxxxxxx func1$T0$func1$T$change
bxxxxxxxx my_interpolator$T2$base
bxxxxxxxx my_interpolator$T2$next_data
bxxxxxxxx my_interpolator$T2$remaining
bxxxxxxxx my_interpolator$T2$interpolated_value
bxxxx my_lut$T2$address
bxxxxxxxx my_lut$T2$base
bxxxxxxxx my_lut$T2$next_data
b00000000000000000000000000000000000000000000000000000000000000000111000001100000010100000100000000110000001000000001000000000000 my_lut$T2$my_lut$T$lut
bxxxxxxxx func0$T1$z_value
bxxxxxxxx func0$T1$a
bxxxxxxxx func0$T1$func0$T$base
bxxxxxxxx func0$T1$func0$T$next_data
bxxxx func0$T1$func0$T$address
bxxxxxxxx func0$T1$func0$T$remaining
bxxxxxxxx func0$T1$func0$T$change
bx counter$T1$clk
bx counter$T1$ack
bx counter$T1$rst
bx counter$T1$ack_mac
bxx counter$T1$counter$T$q
bx layer0$T0$clk
bx layer0$T0$rst
bx layer0$T0$req
bxxxxxxxx layer0$T0$$59
bx layer0$T0$ack_layer
bx layer0$T0$$57
bx layer0$T0$$58
bxxxxxxxx layer0$T0$$99
bxxxxxxxx layer0$T0$$100
bx layer0$T0$layer0$T$req_mac
bx layer0$T0$layer0$T$ack
bx layer0$T0$layer0$T$ack_mac
bx layer0$T0$layer0$T$ack_add
bxxxxxxxx layer0$T0$layer0$T$$136
bx layer0$T0$layer0$T$$134
bx layer0$T0$layer0$T$$135
bxxxxxxxx layer0$T0$layer0$T$$159
bxxxxxxxx layer0$T0$layer0$T$$160
bxxxxxxxx layer0$T0$layer0$T$$151
bx layer0$T0$layer0$T$$149
bx layer0$T0$layer0$T$$150
bxxxxxxxx layer0$T0$layer0$T$$200
bx layer0$T0$layer0$T$$201
bx layer0$T0$layer0$T$$198
bx layer0$T0$layer0$T$$199
bxxxxxxxx layer0$T0$layer0$T$$228
bxxxxxxxx layer0$T0$layer0$T$$229
bxxxxxxxx layer0$T0$layer0$T$$215
bx layer0$T0$layer0$T$$216
bx layer0$T0$layer0$T$$213
bx layer0$T0$layer0$T$$214
bxxxxxxxx layer0$T0$layer0$T$value_z0
bxxxxxxxx layer0$T0$layer0$T$value_z1
bxxxxxxxx layer0$T0$layer0$T$value_a0
bxxxxxxxx layer0$T0$layer0$T$value_a1
bx layer0$T0$layer0$T$flag_z0
bx layer0$T0$layer0$T$flag_z1
bx layer0$T0$layer0$T$ack_a0
bx layer0$T0$layer0$T$ack_a1
bx layer0$T0$layer0$T$channel_w0$127$trig_r
bxxxxxxxx layer0$T0$layer0$T$channel_w0$127$dbus_r
bx layer0$T0$layer0$T$channel_w0$127$abus_r
b1111001000001100 layer0$T0$layer0$T$channel_w0$127$mem
bx layer0$T0$layer0$T$channel_w1$142$trig_r
bxxxxxxxx layer0$T0$layer0$T$channel_w1$142$dbus_r
bx layer0$T0$layer0$T$channel_w1$142$abus_r
b0001100011101111 layer0$T0$layer0$T$channel_w1$142$mem
bxxxxxxxx layer0$T0$layer0$T$channel_accum$157$reg_0
bxxxxxxxx layer0$T0$layer0$T$channel_accum$157$reg_1
bx layer0$T0$layer0$T$channel_accum$157$rinc$169$abus_r
bx layer0$T0$layer0$T$channel_accum$157$winc$174$abus_w
bx layer0$T0$layer0$T$channel_accum$157$rdec$179$abus_r
bx layer0$T0$layer0$T$channel_accum$157$wdec$184$abus_w
bxxxxxxxx layer0$T0$layer0$T$mac_n1$189$lv0
bxxxxxxxx layer0$T0$layer0$T$mac_n1$189$lv1
bxxxxxxxx layer0$T0$layer0$T$mac_n1$189$av0
bxxxxxxxx layer0$T0$layer0$T$mac_n1$189$av1
bxxxxxxxx layer0$T0$layer0$T$mac_n1$189$rv
bx layer0$T0$layer0$T$mac_n1$189$lvok0
bx layer0$T0$layer0$T$mac_n1$189$lvok1
bx layer0$T0$layer0$T$mac_n1$189$rvok
bx layer0$T0$layer0$T$mac_n1$189$wok0
bx layer0$T0$layer0$T$mac_n1$189$wok1
bx layer0$T0$layer0$T$mac_n1$189$run
bx layer0$T0$layer0$T$channel_b0$196$trig_r
bxxxxxxxx layer0$T0$layer0$T$channel_b0$196$dbus_r
bx layer0$T0$layer0$T$channel_b0$196$abus_r
b00000001 layer0$T0$layer0$T$channel_b0$196$mem
bx layer0$T0$layer0$T$channel_b1$211$trig_r
bxxxxxxxx layer0$T0$layer0$T$channel_b1$211$dbus_r
bx layer0$T0$layer0$T$channel_b1$211$abus_r
b11111101 layer0$T0$layer0$T$channel_b1$211$mem
bxxxxxxxx layer0$T0$layer0$T$channel_z$226$reg_0
bxxxxxxxx layer0$T0$layer0$T$channel_z$226$reg_1
bx layer0$T0$layer0$T$channel_z$226$rinc$238$abus_r
bx layer0$T0$layer0$T$channel_z$226$winc$242$abus_w
bx layer0$T0$layer0$T$channel_z$226$rdec$246$abus_r
bx layer0$T0$layer0$T$channel_z$226$wdec$251$abus_w
bxxxxxxxx layer0$T0$layer0$T$add_n$256$lv0
bxxxxxxxx layer0$T0$layer0$T$add_n$256$lv1
bxxxxxxxx layer0$T0$layer0$T$add_n$256$rv0
bxxxxxxxx layer0$T0$layer0$T$add_n$256$rv1
bx layer0$T0$layer0$T$add_n$256$lvok0
bx layer0$T0$layer0$T$add_n$256$lvok1
bx layer0$T0$layer0$T$add_n$256$rvok0
bx layer0$T0$layer0$T$add_n$256$rvok1
bx layer0$T0$layer0$T$add_n$256$run
bx neural_network$T0$clk
bx neural_network$T0$rst
bx neural_network$T0$req
bx neural_network$T0$fill
bxxxxxxxx neural_network$T0$$10
bx neural_network$T0$ack_fill
bx neural_network$T0$ack_network
bx neural_network$T0$$8
bx neural_network$T0$$9
bx neural_network$T0$$32
bx neural_network$T0$$33
bxxxxxxxx neural_network$T0$$34
bx neural_network$T0$neural_network$T$ack_0
bx neural_network$T0$neural_network$T$ack_1
bx neural_network$T0$neural_network$T$fill_inputs
bxxxxxxxx neural_network$T0$neural_network$T$value_inputs
bxx neural_network$T0$neural_network$T$address_inputs
bx neural_network$T0$neural_network$T$flag_inputs
bx neural_network$T0$neural_network$T$ack_inputs
bx neural_network$T0$neural_network$T$$61
bx neural_network$T0$neural_network$T$$62
bxxxxxxxx neural_network$T0$neural_network$T$$63
bx neural_network$T0$neural_network$T$fill_outputs
bxxxxxxxx neural_network$T0$neural_network$T$value_outputs
bx neural_network$T0$neural_network$T$address_outputs
bx neural_network$T0$neural_network$T$flag_outputs
bxxxxxxxx neural_network$T0$neural_network$T$$84
bx neural_network$T0$neural_network$T$$85
bx neural_network$T0$neural_network$T$channel_inputs$45$trig_r
bx neural_network$T0$neural_network$T$channel_inputs$45$trig_w
bxxxxxxxx neural_network$T0$neural_network$T$channel_inputs$45$dbus_r
bxxxxxxxx neural_network$T0$neural_network$T$channel_inputs$45$dbus_w
bx neural_network$T0$neural_network$T$channel_inputs$45$abus_r
bx neural_network$T0$neural_network$T$channel_inputs$45$abus_w
bxxxxxxxxxxxxxxxx neural_network$T0$neural_network$T$channel_inputs$45$mem
bxxxxxxxx neural_network$T0$neural_network$T$channel_outputs$74$reg_0
bx neural_network$T0$neural_network$T$channel_outputs$74$rinc$83$abus_r
bx neural_network$T0$neural_network$T$channel_outputs$74$winc$86$abus_w
bx neural_network$T0$neural_network$T$channel_outputs$74$rdec$89$abus_r
bx neural_network$T0$neural_network$T$channel_outputs$74$wdec$93$abus_w
bxxxxxxxx neural_network$T0$neural_network$T$channel_a0$97$reg_0
bxxxxxxxx neural_network$T0$neural_network$T$channel_a0$97$reg_1
bx neural_network$T0$neural_network$T$channel_a0$97$rinc$109$abus_r
bx neural_network$T0$neural_network$T$channel_a0$97$winc$113$abus_w
bx neural_network$T0$neural_network$T$channel_a0$97$rdec$117$abus_r
bx neural_network$T0$neural_network$T$channel_a0$97$wdec$122$abus_w
bx __$T0$__$T$clk
bx __$T0$__$T$rst
bx __$T0$__$T$req
bx __$T0$__$T$fill
bx __$T0$__$T$ack_fill
bx __$T0$__$T$ack_network
bx __$T0$__$T$rom_inputs$1$trig_r
bxxxxxxxx __$T0$__$T$rom_inputs$1$dbus_r
bx __$T0$__$T$rom_inputs$1$abus_r
b0001000000000000 __$T0$__$T$rom_inputs$1$mem
bx __$T0$__$T$ram_outputs$16$trig_r
bx __$T0$__$T$ram_outputs$16$trig_w
bxxxxxxxx __$T0$__$T$ram_outputs$16$dbus_r
bxxxxxxxx __$T0$__$T$ram_outputs$16$dbus_w
bx __$T0$__$T$ram_outputs$16$abus_r
bx __$T0$__$T$ram_outputs$16$abus_w
bxxxxxxxx __$T0$__$T$ram_outputs$16$mem
$end
#0
b0 __$T0$__$T$clk
b0 __$T0$__$T$rst
b0 __$T0$__$T$req
b0 __$T0$__$T$fill
b0 neural_network$T0$clk
b0 neural_network$T0$rst
b0 neural_network$T0$req
b0 neural_network$T0$fill
b00000000 __$T0$__$T$rom_inputs$1$dbus_r
b0 layer0$T0$clk
b0 layer0$T0$rst
b0 layer0$T0$req
b0 layer1$T0$clk
b0 layer1$T0$rst
b0 neural_network$T0$neural_network$T$fill_inputs
b00000000 neural_network$T0$$10
b0 counter$T1$clk
b0 counter$T1$rst
b00001100 layer0$T0$layer0$T$channel_w0$127$dbus_r
b11101111 layer0$T0$layer0$T$channel_w1$142$dbus_r
b00000001 layer0$T0$layer0$T$channel_b0$196$dbus_r
b11111101 layer0$T0$layer0$T$channel_b1$211$dbus_r
b0 layer0$T0$layer0$T$$201
b0 layer0$T0$layer0$T$$216
b0 layer0$T0$layer0$T$req_mac
b0 counter$T00$clk
b0 counter$T00$rst
b00010100 layer1$T0$layer1$T$channel_w0$267$dbus_r
b11111110 layer1$T0$layer1$T$channel_b0$312$dbus_r
b0 layer1$T0$layer1$T$$317
b00001100 layer0$T0$layer0$T$$136
b11101111 layer0$T0$layer0$T$$151
b00000001 layer0$T0$layer0$T$$200
b11111101 layer0$T0$layer0$T$$215
b00010100 layer1$T0$layer1$T$$276
b11111110 layer1$T0$layer1$T$$316
#10
#10
b1 __$T0$__$T$rst
b1 neural_network$T0$rst
b1 layer0$T0$rst
b1 layer1$T0$rst
b1 counter$T1$rst
b1 layer0$T0$layer0$T$$201
b1 layer0$T0$layer0$T$$216
b1 counter$T00$rst
b1 layer1$T0$layer1$T$$317
#20
b1 __$T0$__$T$clk
b1 neural_network$T0$clk
b1 layer0$T0$clk
b1 layer1$T0$clk
b0 neural_network$T0$neural_network$T$ack_0
b0 neural_network$T0$neural_network$T$ack_1
b1 neural_network$T0$neural_network$T$$62
b0 neural_network$T0$neural_network$T$$61
b1 neural_network$T0$$9
b0 neural_network$T0$$8
b00 neural_network$T0$neural_network$T$address_inputs
b0 neural_network$T0$neural_network$T$flag_inputs
b0 neural_network$T0$neural_network$T$ack_inputs
b1 neural_network$T0$$33
b0 neural_network$T0$$32
b0 neural_network$T0$neural_network$T$$85
b0 neural_network$T0$neural_network$T$address_outputs
b0 neural_network$T0$neural_network$T$flag_outputs
b0 neural_network$T0$ack_network
b1 counter$T1$clk
b1 layer0$T0$layer0$T$$150
b0 layer0$T0$layer0$T$$149
b1 layer0$T0$layer0$T$$135
b0 layer0$T0$layer0$T$$134
b1 layer0$T0$$58
b0 layer0$T0$$57
b0 layer0$T0$layer0$T$ack
b0 layer0$T0$layer0$T$mac_n1$189$run
b0 layer0$T0$layer0$T$$213
b0 layer0$T0$layer0$T$$198
b0 layer0$T0$layer0$T$ack_add
b0 layer0$T0$layer0$T$add_n$256$run
b0 layer0$T0$layer0$T$ack_mac
b0 layer0$T0$layer0$T$ack_a0
b0 layer0$T0$layer0$T$ack_a1
b1 counter$T00$clk
b1 layer1$T0$layer1$T$$275
b0 layer1$T0$layer1$T$$274
b0 layer1$T0$$112
b0 layer1$T0$layer1$T$ack
b0 layer1$T0$layer1$T$mac_n1$307$run
b0 layer1$T0$layer1$T$$314
b0 layer1$T0$layer1$T$ack_add
b0 layer1$T0$layer1$T$add_n$350$run
b0 layer1$T0$layer1$T$ack_mac
b0 layer1$T0$layer1$T$ack_a0
b0 layer1$T0$req
b0 neural_network$T0$ack_fill
b0 neural_network$T0$neural_network$T$fill_outputs
b1 neural_network$T0$neural_network$T$channel_inputs$45$abus_w
b0 neural_network$T0$neural_network$T$channel_inputs$45$trig_w
b0 __$T0$__$T$rom_inputs$1$trig_r
b1 __$T0$__$T$rom_inputs$1$abus_r
b0 neural_network$T0$neural_network$T$fill_inputs
b0 __$T0$__$T$ram_outputs$16$trig_w
b1 __$T0$__$T$ram_outputs$16$abus_w
b0 neural_network$T0$neural_network$T$channel_outputs$74$rinc$83$abus_r
b0 __$T0$__$T$ack_network
b1 layer0$T0$layer0$T$channel_w1$142$abus_r
b0 layer0$T0$layer0$T$channel_w1$142$trig_r
b1 layer0$T0$layer0$T$channel_w0$127$abus_r
b0 layer0$T0$layer0$T$channel_w0$127$trig_r
b0 neural_network$T0$neural_network$T$channel_inputs$45$trig_r
b1 neural_network$T0$neural_network$T$channel_inputs$45$abus_r
b0 counter$T1$ack
b0 layer0$T0$ack_layer
b0 layer0$T0$layer0$T$channel_b1$211$trig_r
b0 layer0$T0$layer0$T$channel_b0$196$trig_r
b0 layer0$T0$layer0$T$req_mac
b1 layer1$T0$layer1$T$channel_w0$267$abus_r
b0 layer1$T0$layer1$T$channel_w0$267$trig_r
b0 neural_network$T0$neural_network$T$channel_a0$97$rinc$109$abus_r
b0 counter$T00$ack
b0 layer1$T0$ack_layer
b0 layer1$T0$layer1$T$channel_b0$312$trig_r
b0 layer1$T0$layer1$T$req_mac
b0 __$T0$__$T$ack_fill
#30
b0 __$T0$__$T$clk
b0 neural_network$T0$clk
b00010000 __$T0$__$T$rom_inputs$1$dbus_r
b0 layer0$T0$clk
b0 layer1$T0$clk
b00010000 neural_network$T0$$10
b0 counter$T1$clk
b11110010 layer0$T0$layer0$T$channel_w0$127$dbus_r
b00011000 layer0$T0$layer0$T$channel_w1$142$dbus_r
b0 counter$T00$clk
b00001101 layer1$T0$layer1$T$channel_w0$267$dbus_r
b00 counter$T1$counter$T$q
b0 counter$T1$ack_mac
b11110010 layer0$T0$layer0$T$$136
b00011000 layer0$T0$layer0$T$$151
b00 counter$T00$counter$T0$q
b0 counter$T00$ack_mac
b00001101 layer1$T0$layer1$T$$276
#40
b1 __$T0$__$T$clk
b1 neural_network$T0$clk
b1 layer0$T0$clk
b1 layer1$T0$clk
b1 counter$T1$clk
b0 layer0$T0$layer0$T$mac_n1$189$rvok
b0 layer0$T0$layer0$T$mac_n1$189$lvok0
b0 layer0$T0$layer0$T$mac_n1$189$wok0
b0 layer0$T0$layer0$T$mac_n1$189$lvok1
b0 layer0$T0$layer0$T$mac_n1$189$wok1
b00000000 layer0$T0$layer0$T$mac_n1$189$av0
b00000000 layer0$T0$layer0$T$mac_n1$189$av1
b0 layer0$T0$layer0$T$add_n$256$lvok0
b0 layer0$T0$layer0$T$add_n$256$rvok0
b0 layer0$T0$layer0$T$add_n$256$lvok1
b0 layer0$T0$layer0$T$add_n$256$rvok1
b0 layer0$T0$layer0$T$flag_z0
b0 layer0$T0$layer0$T$flag_z1
b1 counter$T00$clk
b0 layer1$T0$layer1$T$mac_n1$307$rvok
b0 layer1$T0$layer1$T$mac_n1$307$lvok0
b0 layer1$T0$layer1$T$mac_n1$307$wok0
b00000000 layer1$T0$layer1$T$mac_n1$307$av0
b0 layer1$T0$layer1$T$add_n$350$lvok0
b0 layer1$T0$layer1$T$add_n$350$rvok0
b0 layer1$T0$layer1$T$flag_z0
#50
b0 __$T0$__$T$clk
b0 __$T0$__$T$rst
b1 __$T0$__$T$fill
b0 neural_network$T0$clk
b0 neural_network$T0$rst
b1 neural_network$T0$fill
b0 layer0$T0$clk
b0 layer0$T0$rst
b0 layer1$T0$clk
b0 layer1$T0$rst
b1 neural_network$T0$neural_network$T$fill_inputs
b0 counter$T1$clk
b0 counter$T1$rst
b0 layer0$T0$layer0$T$$201
b0 layer0$T0$layer0$T$$216
b0 counter$T00$clk
b0 counter$T00$rst
b0 layer1$T0$layer1$T$$317
#60
b1 __$T0$__$T$clk
b1 neural_network$T0$clk
b1 layer0$T0$clk
b1 layer1$T0$clk
b0 neural_network$T0$$9
b1 neural_network$T0$$8
b1 counter$T1$clk
b1 counter$T00$clk
b1 __$T0$__$T$rom_inputs$1$trig_r
b0 __$T0$__$T$rom_inputs$1$abus_r
#70
b0 __$T0$__$T$clk
b0 neural_network$T0$clk
b00000000 __$T0$__$T$rom_inputs$1$dbus_r
b0 layer0$T0$clk
b0 layer1$T0$clk
b00000000 neural_network$T0$$10
b0 counter$T1$clk
b0 counter$T00$clk
#80
b1 __$T0$__$T$clk
b1 neural_network$T0$clk
b1 layer0$T0$clk
b1 layer1$T0$clk
b0 neural_network$T0$$8
b00000000 neural_network$T0$neural_network$T$value_inputs
b1 neural_network$T0$neural_network$T$flag_inputs
b1 counter$T1$clk
b1 counter$T00$clk
b0 __$T0$__$T$rom_inputs$1$trig_r
b0 neural_network$T0$neural_network$T$fill_inputs
#90
b0 __$T0$__$T$clk
b0 neural_network$T0$clk
b0 layer0$T0$clk
b0 layer1$T0$clk
b0 counter$T1$clk
b0 counter$T00$clk
#100
b1 __$T0$__$T$clk
b1 neural_network$T0$clk
b1 layer0$T0$clk
b1 layer1$T0$clk
b1 neural_network$T0$neural_network$T$$61
b0 neural_network$T0$neural_network$T$$62
b00000000 neural_network$T0$neural_network$T$$63
b01 neural_network$T0$neural_network$T$address_inputs
b0 neural_network$T0$neural_network$T$flag_inputs
b1 counter$T1$clk
b1 counter$T00$clk
b1 neural_network$T0$neural_network$T$channel_inputs$45$trig_w
b0 neural_network$T0$neural_network$T$channel_inputs$45$abus_w
b00000000 neural_network$T0$neural_network$T$channel_inputs$45$dbus_w
b1 neural_network$T0$neural_network$T$fill_inputs
#110
b0 __$T0$__$T$clk
b0 neural_network$T0$clk
b0 layer0$T0$clk
b0 layer1$T0$clk
bxxxxxxxx00000000 neural_network$T0$neural_network$T$channel_inputs$45$mem
b0 counter$T1$clk
b0 counter$T00$clk
#120
b1 __$T0$__$T$clk
b1 neural_network$T0$clk
b1 layer0$T0$clk
b1 layer1$T0$clk
b0 neural_network$T0$neural_network$T$$61
b1 neural_network$T0$$9
b1 neural_network$T0$$8
b1 counter$T1$clk
b1 counter$T00$clk
b0 neural_network$T0$neural_network$T$channel_inputs$45$trig_w
b1 __$T0$__$T$rom_inputs$1$trig_r
b1 __$T0$__$T$rom_inputs$1$abus_r
#130
b0 __$T0$__$T$clk
b0 neural_network$T0$clk
b00010000 __$T0$__$T$rom_inputs$1$dbus_r
b0 layer0$T0$clk
b0 layer1$T0$clk
b00010000 neural_network$T0$$10
b0 counter$T1$clk
b0 counter$T00$clk
#140
b1 __$T0$__$T$clk
b1 neural_network$T0$clk
b1 layer0$T0$clk
b1 layer1$T0$clk
b0 neural_network$T0$$8
b00010000 neural_network$T0$neural_network$T$value_inputs
b1 neural_network$T0$neural_network$T$flag_inputs
b1 counter$T1$clk
b1 counter$T00$clk
b0 __$T0$__$T$rom_inputs$1$trig_r
b0 neural_network$T0$neural_network$T$fill_inputs
#150
b0 __$T0$__$T$clk
b0 neural_network$T0$clk
b0 layer0$T0$clk
b0 layer1$T0$clk
b0 counter$T1$clk
b0 counter$T00$clk
#160
b1 __$T0$__$T$clk
b1 neural_network$T0$clk
b1 layer0$T0$clk
b1 layer1$T0$clk
b1 neural_network$T0$neural_network$T$$61
b1 neural_network$T0$neural_network$T$$62
b00010000 neural_network$T0$neural_network$T$$63
b10 neural_network$T0$neural_network$T$address_inputs
b0 neural_network$T0$neural_network$T$flag_inputs
b1 neural_network$T0$neural_network$T$ack_inputs
b1 counter$T1$clk
b1 counter$T00$clk
b1 neural_network$T0$neural_network$T$channel_inputs$45$trig_w
b1 neural_network$T0$neural_network$T$channel_inputs$45$abus_w
b00010000 neural_network$T0$neural_network$T$channel_inputs$45$dbus_w
b1 neural_network$T0$ack_fill
b1 __$T0$__$T$ack_fill
#170
b0 __$T0$__$T$clk
b0 neural_network$T0$clk
b0 layer0$T0$clk
b0 layer1$T0$clk
b0001000000000000 neural_network$T0$neural_network$T$channel_inputs$45$mem
b0 counter$T1$clk
b0 counter$T00$clk
#180
b1 __$T0$__$T$clk
b1 neural_network$T0$clk
b1 layer0$T0$clk
b1 layer1$T0$clk
b0 neural_network$T0$neural_network$T$$61
b1 counter$T1$clk
b1 counter$T00$clk
b0 neural_network$T0$neural_network$T$channel_inputs$45$trig_w
#190
b0 __$T0$__$T$clk
b0 neural_network$T0$clk
b0 layer0$T0$clk
b0 layer1$T0$clk
b00010000 neural_network$T0$neural_network$T$channel_inputs$45$dbus_r
b0 counter$T1$clk
b0 counter$T00$clk
b00010000 layer0$T0$$59
#200
b1 __$T0$__$T$clk