From 09b8f75b452d738194e78d1f8110f39ff393d42d Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Mon, 17 Dec 2018 18:11:37 -0500 Subject: [PATCH 01/14] Add support for MSP430 --- .gitignore | 3 + README.md | 2 +- bindings/Makefile | 4 + debian/control | 4 +- docs/COMPILE-NIX.md | 2 +- docs/COMPILE-WINDOWS.md | 2 +- include/keystone/keystone.h | 2 + include/keystone/msp430.h | 23 + kstool/kstool.cpp | 8 + kstool/test-all.sh | 5 + llvm/CMakeLists.txt | 1 + llvm/include/llvm/MC/MCParser/MCAsmParser.h | 6 + .../llvm/MC/MCParser/MCTargetAsmParser.h | 11 +- llvm/include/llvm/Object/ELFObjectFile.h | 4 + llvm/include/llvm/Support/Endian.h | 11 + llvm/include/llvm/Support/EndianStream.h | 6 + llvm/keystone/CMakeLists.txt | 1 + llvm/keystone/ks.cpp | 18 + llvm/keystone/ks_priv.h | 1 + llvm/lib/MC/MCParser/MCAsmParser.cpp | 37 + llvm/lib/Target/LLVMBuild.txt | 1 + .../Target/MSP430/AsmParser/CMakeLists.txt | 5 + .../lib/Target/MSP430/AsmParser/LLVMBuild.txt | 23 + .../MSP430/AsmParser/MSP430AsmParser.cpp | 575 +++++++++ llvm/lib/Target/MSP430/CMakeLists.txt | 0 llvm/lib/Target/MSP430/LLVMBuild.txt | 22 + .../Target/MSP430/MCTargetDesc/CMakeLists.txt | 7 + .../Target/MSP430/MCTargetDesc/LLVMBuild.txt | 23 + .../MSP430/MCTargetDesc/MSP430AsmBackend.cpp | 152 +++ .../MSP430/MCTargetDesc/MSP430ELFBackport.h | 28 + .../MCTargetDesc/MSP430ELFObjectWriter.cpp | 59 + .../MSP430/MCTargetDesc/MSP430ELFStreamer.cpp | 74 ++ .../MSP430/MCTargetDesc/MSP430FixupKinds.h | 53 + .../MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp | 24 + .../MSP430/MCTargetDesc/MSP430MCAsmInfo.h | 30 + .../MCTargetDesc/MSP430MCCodeEmitter.cpp | 211 +++ .../MCTargetDesc/MSP430MCTargetDesc.cpp | 73 ++ .../MSP430/MCTargetDesc/MSP430MCTargetDesc.h | 63 + llvm/lib/Target/MSP430/MSP430.h | 84 ++ .../lib/Target/MSP430/MSP430GenAsmMatcher.inc | 1109 ++++++++++++++++ llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc | 1147 +++++++++++++++++ .../Target/MSP430/MSP430GenMCCodeEmitter.inc | 838 ++++++++++++ .../Target/MSP430/MSP430GenRegisterInfo.inc | 631 +++++++++ .../Target/MSP430/MSP430GenSubtargetInfo.inc | 163 +++ .../Target/MSP430/TargetInfo/CMakeLists.txt | 3 + .../Target/MSP430/TargetInfo/LLVMBuild.txt | 23 + .../MSP430/TargetInfo/MSP430TargetInfo.cpp | 20 + samples/sample.c | 3 + suite/fuzz/fuzz_asm_msp430.c | 66 + suite/fuzz/gentargets.sh | 2 + suite/test-all.sh | 5 + 51 files changed, 5662 insertions(+), 6 deletions(-) create mode 100644 include/keystone/msp430.h create mode 100644 llvm/lib/Target/MSP430/AsmParser/CMakeLists.txt create mode 100644 llvm/lib/Target/MSP430/AsmParser/LLVMBuild.txt create mode 100644 llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp create mode 100644 llvm/lib/Target/MSP430/CMakeLists.txt create mode 100644 llvm/lib/Target/MSP430/LLVMBuild.txt create mode 100755 llvm/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt create mode 100755 llvm/lib/Target/MSP430/MCTargetDesc/LLVMBuild.txt create mode 100755 llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp create mode 100644 llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFBackport.h create mode 100755 llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFObjectWriter.cpp create mode 100644 llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp create mode 100755 llvm/lib/Target/MSP430/MCTargetDesc/MSP430FixupKinds.h create mode 100755 llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp create mode 100755 llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h create mode 100755 llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp create mode 100755 llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp create mode 100755 llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h create mode 100644 llvm/lib/Target/MSP430/MSP430.h create mode 100644 llvm/lib/Target/MSP430/MSP430GenAsmMatcher.inc create mode 100644 llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc create mode 100644 llvm/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc create mode 100644 llvm/lib/Target/MSP430/MSP430GenRegisterInfo.inc create mode 100644 llvm/lib/Target/MSP430/MSP430GenSubtargetInfo.inc create mode 100644 llvm/lib/Target/MSP430/TargetInfo/CMakeLists.txt create mode 100644 llvm/lib/Target/MSP430/TargetInfo/LLVMBuild.txt create mode 100644 llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp create mode 100644 suite/fuzz/fuzz_asm_msp430.c mode change 100644 => 100755 suite/fuzz/gentargets.sh diff --git a/.gitignore b/.gitignore index 54885d84..144e6e02 100644 --- a/.gitignore +++ b/.gitignore @@ -18,6 +18,9 @@ *.github.io _*.diff +.idea/ +cmake-build-debug + build*/ samples/sample _sample*.txt diff --git a/README.md b/README.md index c97c8b42..17cb3aa2 100644 --- a/README.md +++ b/README.md @@ -8,7 +8,7 @@ Keystone Engine Keystone is a lightweight multi-platform, multi-architecture assembler framework. It offers some unparalleled features: -- Multi-architecture, with support for Arm, Arm64 (AArch64/Armv8), Ethereum Virtual Machine, Hexagon, Mips, PowerPC, Sparc, SystemZ & X86 (include 16/32/64bit). +- Multi-architecture, with support for Arm, Arm64 (AArch64/Armv8), Ethereum Virtual Machine, Hexagon, Mips, MSP430, PowerPC, Sparc, SystemZ & X86 (include 16/32/64bit). - Clean/simple/lightweight/intuitive architecture-neutral API. - Implemented in C/C++ languages, with bindings for Java, Masm, C#, PowerShell, Perl, Python, NodeJS, Ruby, Go, Rust, Haskell, VB6 & OCaml available. - Native support for Windows & \*nix (with Mac OSX, Linux, \*BSD & Solaris confirmed). diff --git a/bindings/Makefile b/bindings/Makefile index 85799b6a..f082bce5 100644 --- a/bindings/Makefile +++ b/bindings/Makefile @@ -7,6 +7,7 @@ DIFF = diff -u -w SAMPLE_ARM = $(TMPDIR)/sample_arm SAMPLE_ARM64 = $(TMPDIR)/sample_arm64 SAMPLE_MIPS = $(TMPDIR)/sample_mips +SAMPLE_MSP430 = $(TMPDIR)/sample_msp430 SAMPLE_M68K = $(TMPDIR)/sample_m68k SAMPLE_SPARC = $(TMPDIR)/sample_sparc SAMPLE_X86 = $(TMPDIR)/sample_x86 @@ -31,6 +32,7 @@ expected: ../samples/sample_arm > $(SAMPLE_ARM)_e ../samples/sample_arm64 > $(SAMPLE_ARM64)_e ../samples/sample_mips > $(SAMPLE_MIPS)_e + ../samples/sample_msp430 > $(SAMPLE_MSP430)_e ../samples/sample_sparc > $(SAMPLE_SPARC)_e ../samples/sample_m68k > $(SAMPLE_M68K)_e ../samples/sample_x86 > $(SAMPLE_X86)_e @@ -40,6 +42,7 @@ python: FORCE python python/sample_arm.py > $(SAMPLE_ARM)_o python python/sample_arm64.py > $(SAMPLE_ARM64)_o python python/sample_mips.py > $(SAMPLE_MIPS)_o + python python/sample_msp430.py > $(SAMPLE_MSP430)_o python python/sample_sparc.py > $(SAMPLE_SPARC)_o python python/sample_m68k.py > $(SAMPLE_M68K)_o python python/sample_x86.py > $(SAMPLE_X86)_o @@ -64,6 +67,7 @@ sample_diff: FORCE $(DIFF) $(SAMPLE_ARM)_e $(SAMPLE_ARM)_o $(DIFF) $(SAMPLE_ARM64)_e $(SAMPLE_ARM64)_o $(DIFF) $(SAMPLE_MIPS)_e $(SAMPLE_MIPS)_o + $(DIFF) $(SAMPLE_MSP430)_e $(SAMPLE_MSP430)_o $(DIFF) $(SAMPLE_SPARC)_e $(SAMPLE_SPARC)_o $(DIFF) $(SAMPLE_M68K)_e $(SAMPLE_M68K)_o $(DIFF) $(SAMPLE_X86)_e $(SAMPLE_X86)_o diff --git a/debian/control b/debian/control index 0964097c..c0510bef 100644 --- a/debian/control +++ b/debian/control @@ -14,11 +14,11 @@ Architecture: any Depends: keystone-engine1 (= ${binary:Version}), ${misc:Depends} Description: A lightweight multi-architecture assembler framework. Multi-architecture, with support for Arm, Arm64 (AArch64/Armv8), - Hexagon, Mips, PowerPC, Sparc, SystemZ, & X86 (include 16/32/64bit). + Hexagon, Mips, MSP430, PowerPC, Sparc, SystemZ, & X86 (include 16/32/64bit). Package: keystone-engine1 Architecture: any Depends: ${shlibs:Depends}, ${misc:Depends} Description: A lightweight multi-architecture assembler framework. Multi-architecture, with support for Arm, Arm64 (AArch64/Armv8), - Hexagon, Mips, PowerPC, Sparc, SystemZ, & X86 (include 16/32/64bit). + Hexagon, Mips, MSP430, PowerPC, Sparc, SystemZ, & X86 (include 16/32/64bit). diff --git a/docs/COMPILE-NIX.md b/docs/COMPILE-NIX.md index 182bb9f3..7b0a7b0c 100644 --- a/docs/COMPILE-NIX.md +++ b/docs/COMPILE-NIX.md @@ -34,7 +34,7 @@ For Windows, see [COMPILE-WINDOWS.md](COMPILE-WINDOWS.md) $ ../make-share.sh lib64 By default, this builds all architectures, which is: AArch64, ARM, Hexagon, - Mips, PowerPC, Sparc, SystemZ & X86. To compile just some selected ones, + Mips, MSP430, PowerPC, Sparc, SystemZ & X86. To compile just some selected ones, pass a semicolon-separated list of targets to LLVM_TARGETS_TO_BUILD, like follows if we only want AArch64 & X86. diff --git a/docs/COMPILE-WINDOWS.md b/docs/COMPILE-WINDOWS.md index b8ecac36..7808fa3a 100644 --- a/docs/COMPILE-WINDOWS.md +++ b/docs/COMPILE-WINDOWS.md @@ -25,7 +25,7 @@ For *nix OS, see [COMPILE-NIX.md](COMPILE-NIX.md) $ ..\nmake-dll.bat By default, this builds all architectures, which is: AArch64, ARM, Hexagon, - Mips, PowerPC, Sparc, SystemZ & X86. To compile just some selected ones, + Mips, MSP430, PowerPC, Sparc, SystemZ & X86. To compile just some selected ones, pass a semicolon-separated list of targets to LLVM_TARGETS_TO_BUILD, like follows if we only want AArch64 & X86. diff --git a/include/keystone/keystone.h b/include/keystone/keystone.h index 5dd51ee5..87305c97 100644 --- a/include/keystone/keystone.h +++ b/include/keystone/keystone.h @@ -56,6 +56,7 @@ typedef enum ks_arch { KS_ARCH_SYSTEMZ, // SystemZ architecture (S390X) KS_ARCH_HEXAGON, // Hexagon architecture KS_ARCH_EVM, // Ethereum Virtual Machine architecture + KS_ARCH_MSP430, // MSP430 architecture KS_ARCH_MAX, } ks_arch; @@ -180,6 +181,7 @@ typedef enum ks_opt_value { #include "evm.h" #include "hexagon.h" #include "mips.h" +#include "msp430.h" #include "ppc.h" #include "sparc.h" #include "systemz.h" diff --git a/include/keystone/msp430.h b/include/keystone/msp430.h new file mode 100644 index 00000000..2ae14778 --- /dev/null +++ b/include/keystone/msp430.h @@ -0,0 +1,23 @@ +/* Keystone Assembler Engine */ +/* By Nguyen Anh Quynh, 2016 */ + +#ifndef KEYSTONE_MSP430_H +#define KEYSTONE_MSP430_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "keystone.h" + +typedef enum ks_err_asm_msp430 { + KS_ERR_ASM_MSP430_INVALIDOPERAND = KS_ERR_ASM_ARCH, + KS_ERR_ASM_MSP430_MISSINGFEATURE, + KS_ERR_ASM_MSP430_MNEMONICFAIL, +} ks_err_asm_msp430; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/kstool/kstool.cpp b/kstool/kstool.cpp index 0ae73aab..7bf57a63 100644 --- a/kstool/kstool.cpp +++ b/kstool/kstool.cpp @@ -59,6 +59,10 @@ static void usage(char *prog) printf(" mips64be: Mips64 - big endian\n"); } + if (ks_arch_supported(KS_ARCH_MSP430)) { + printf(" msp430: MSP430\n"); + } + if (ks_arch_supported(KS_ARCH_PPC)) { printf(" ppc32be: PowerPC32 - big endian\n"); printf(" ppc64: PowerPC64 - little endian\n"); @@ -240,6 +244,10 @@ int main(int argc, char **argv) err = ks_open(KS_ARCH_MIPS, KS_MODE_MIPS32+KS_MODE_LITTLE_ENDIAN, &ks); } + if (!strcmp(mode, "msp430")) { + err = ks_open(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, &ks); + } + if (!strcmp(mode, "mipsbe")) { err = ks_open(KS_ARCH_MIPS, KS_MODE_MIPS32+KS_MODE_BIG_ENDIAN, &ks); } diff --git a/kstool/test-all.sh b/kstool/test-all.sh index 7b955371..efbead76 100755 --- a/kstool/test-all.sh +++ b/kstool/test-all.sh @@ -75,6 +75,11 @@ kstool mips64be "and \$9, \$6, \$7" #encoding: [0x00,0xc7,0x48,0x24] echo +echo "::MSP430" +kstool msp430 "and r12, r13" +#encoding: [0x0d,0xfc] +echo + echo "::SystemZ" kstool systemz "a %r0, 4095(%r15,%r1)" #encoding: [0x5a,0x0f,0x1f,0xff] diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index e324ef39..15d7b9c8 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -174,6 +174,7 @@ set(LLVM_ALL_TARGETS ARM Hexagon Mips + MSP430 PowerPC Sparc SystemZ diff --git a/llvm/include/llvm/MC/MCParser/MCAsmParser.h b/llvm/include/llvm/MC/MCParser/MCAsmParser.h index bac580fd..b572caff 100644 --- a/llvm/include/llvm/MC/MCParser/MCAsmParser.h +++ b/llvm/include/llvm/MC/MCParser/MCAsmParser.h @@ -11,6 +11,7 @@ #define LLVM_MC_MCPARSER_MCASMPARSER_H #include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/MC/MCParser/AsmLexer.h" #include "llvm/Support/DataTypes.h" @@ -80,6 +81,11 @@ class MCAsmParser { // save Keystone error unsigned int KsError; + bool parseMany(function_ref parseOne, bool hasComma = true); + bool parseOptionalToken(AsmToken::TokenKind T); + bool parseToken(AsmToken::TokenKind T, const Twine &Msg); + bool parseEOL(const Twine &Msg); + virtual ~MCAsmParser(); virtual void addDirectiveHandler(StringRef Directive, diff --git a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h index 4daab8e2..4d4690ef 100644 --- a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h +++ b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h @@ -13,12 +13,12 @@ #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCParser/MCAsmParserExtension.h" #include "llvm/MC/MCTargetOptions.h" +#include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include namespace llvm_ks { class AsmToken; class MCInst; -class MCParsedAsmOperand; class MCStreamer; class MCSubtargetInfo; class SMLoc; @@ -136,6 +136,15 @@ class MCTargetAsmParser : public MCAsmParserExtension { SemaCallback = Callback; } + /// Returns whether two registers are equal and is used by the tied-operands + /// checks in the AsmMatcher. This method can be overridden allow e.g. a + /// sub- or super-register as the tied operand. + virtual bool regsEqual(const MCParsedAsmOperand &Op1, + const MCParsedAsmOperand &Op2) const { + assert(Op1.isReg() && Op2.isReg() && "Operands not all regs"); + return Op1.getReg() == Op2.getReg(); + } + virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc, unsigned int &ErrorCode) = 0; diff --git a/llvm/include/llvm/Object/ELFObjectFile.h b/llvm/include/llvm/Object/ELFObjectFile.h index 26836d63..71b0f1da 100644 --- a/llvm/include/llvm/Object/ELFObjectFile.h +++ b/llvm/include/llvm/Object/ELFObjectFile.h @@ -837,6 +837,8 @@ StringRef ELFObjectFile::getFileFormatName() const { return "ELF32-hexagon"; case ELF::EM_MIPS: return "ELF32-mips"; + case ELF::EM_MSP430: + return "ELF32-msp430"; case ELF::EM_PPC: return "ELF32-ppc"; case ELF::EM_SPARC: @@ -900,6 +902,8 @@ unsigned ELFObjectFile::getArch() const { default: report_fatal_error("Invalid ELFCLASS!"); } + case ELF::EM_MSP430: + return Triple::msp430; case ELF::EM_PPC: return Triple::ppc; case ELF::EM_PPC64: diff --git a/llvm/include/llvm/Support/Endian.h b/llvm/include/llvm/Support/Endian.h index 59c59b44..079c69f9 100644 --- a/llvm/include/llvm/Support/Endian.h +++ b/llvm/include/llvm/Support/Endian.h @@ -78,6 +78,17 @@ inline void write(void *memory, value_type value) { sizeof(value_type)); } +constexpr endianness system_endianness() { + return sys::IsBigEndianHost ? big : little; +} + +template +inline value_type byte_swap(value_type value, endianness endian) { + if ((endian != native) && (endian != system_endianness())) + sys::swapByteOrder(value); + return value; +} + template using make_unsigned_t = typename std::make_unsigned::type; diff --git a/llvm/include/llvm/Support/EndianStream.h b/llvm/include/llvm/Support/EndianStream.h index 35200c1b..a2f2714a 100644 --- a/llvm/include/llvm/Support/EndianStream.h +++ b/llvm/include/llvm/Support/EndianStream.h @@ -61,6 +61,12 @@ inline void Writer::write(double Val) { write(DoubleToBits(Val)); } +template +inline void write(raw_ostream &os, value_type value, endianness endian) { + value = byte_swap(value, endian); + os.write((const char *)&value, sizeof(value_type)); +} + } // end namespace endian } // end namespace support diff --git a/llvm/keystone/CMakeLists.txt b/llvm/keystone/CMakeLists.txt index 572d0f4e..f7f3d846 100644 --- a/llvm/keystone/CMakeLists.txt +++ b/llvm/keystone/CMakeLists.txt @@ -14,6 +14,7 @@ file(GLOB_RECURSE src_AArch64 "../lib/Target/AArch64/*.cpp") file(GLOB_RECURSE src_ARM "../lib/Target/ARM/*.cpp") file(GLOB_RECURSE src_Hexagon "../lib/Target/Hexagon/*.cpp") file(GLOB_RECURSE src_Mips "../lib/Target/Mips/*.cpp") +file(GLOB_RECURSE src_MSP430 "../lib/Target/MSP430/*.cpp") file(GLOB_RECURSE src_PowerPC "../lib/Target/PowerPC/*.cpp") file(GLOB_RECURSE src_Sparc "../lib/Target/Sparc/*.cpp") file(GLOB_RECURSE src_SystemZ "../lib/Target/SystemZ/*.cpp") diff --git a/llvm/keystone/ks.cpp b/llvm/keystone/ks.cpp index bfb0f6a8..63de0d89 100644 --- a/llvm/keystone/ks.cpp +++ b/llvm/keystone/ks.cpp @@ -161,6 +161,9 @@ bool ks_arch_supported(ks_arch arch) #ifdef LLVM_ENABLE_ARCH_Mips case KS_ARCH_MIPS: return true; #endif +#ifdef LLVM_ENABLE_ARCH_MSP430 + case KS_ARCH_MSP430: return true; +#endif #ifdef LLVM_ENABLE_ARCH_PowerPC case KS_ARCH_PPC: return true; #endif @@ -410,6 +413,21 @@ ks_err ks_open(ks_arch arch, int mode, ks_engine **result) break; #endif +#ifdef LLVM_ENABLE_ARCH_MSP430 + case KS_ARCH_MSP430: + if (mode & ~KS_MODE_MSP430_MASK) { + delete ks; + return KS_ERR_MODE; + } + + TripleName = "msp430"; + + InitKs(arch, ks, TripleName); + + //ks->init_arch = arm_ks_init; + break; +#endif + #ifdef LLVM_ENABLE_ARCH_PowerPC case KS_ARCH_PPC: if ((mode & ~KS_MODE_PPC_MASK) || diff --git a/llvm/keystone/ks_priv.h b/llvm/keystone/ks_priv.h index aa1446ae..1a2b3c1e 100644 --- a/llvm/keystone/ks_priv.h +++ b/llvm/keystone/ks_priv.h @@ -26,6 +26,7 @@ #define KS_MODE_PPC_MASK (KS_MODE_PPC32|KS_MODE_PPC64|KS_MODE_LITTLE_ENDIAN|KS_MODE_BIG_ENDIAN) #define KS_MODE_SPARC_MASK (KS_MODE_V9|KS_MODE_SPARC32|KS_MODE_SPARC64|KS_MODE_LITTLE_ENDIAN|KS_MODE_BIG_ENDIAN) #define KS_MODE_HEXAGON_MASK (KS_MODE_BIG_ENDIAN) +#define KS_MODE_MSP430_MASK (KS_MODE_LITTLE_ENDIAN) #define KS_MODE_SYSTEMZ_MASK (KS_MODE_BIG_ENDIAN) #define KS_MODE_ARM64_MASK (KS_MODE_LITTLE_ENDIAN) #define KS_MODE_M68K_MASK (KS_MODE_BIG_ENDIAN) diff --git a/llvm/lib/MC/MCParser/MCAsmParser.cpp b/llvm/lib/MC/MCParser/MCAsmParser.cpp index dcd1638c..a8ef3688 100644 --- a/llvm/lib/MC/MCParser/MCAsmParser.cpp +++ b/llvm/lib/MC/MCParser/MCAsmParser.cpp @@ -43,5 +43,42 @@ bool MCAsmParser::parseExpression(const MCExpr *&Res) { return parseExpression(Res, L); } +bool MCAsmParser::parseEOL(const Twine &Msg) { + if (getTok().getKind() != AsmToken::EndOfStatement) + return Error(getTok().getLoc(), Msg); + Lex(); + return false; +} + +bool MCAsmParser::parseToken(AsmToken::TokenKind T, const Twine &Msg = "unexpected token") { + if (T == AsmToken::EndOfStatement) + return parseEOL(Msg); + if (getTok().getKind() != T) + return Error(getTok().getLoc(), Msg); + Lex(); + return false; +} + +bool MCAsmParser::parseOptionalToken(AsmToken::TokenKind T) { + bool Present = (getTok().getKind() == T); + if (Present) + parseToken(T); + return Present; +} + +bool MCAsmParser::parseMany(function_ref parseOne, bool hasComma) { + if (parseOptionalToken(AsmToken::EndOfStatement)) + return false; + while (true) { + if (parseOne()) + return true; + if (parseOptionalToken(AsmToken::EndOfStatement)) + return false; + if (hasComma && parseToken(AsmToken::Comma)) + return true; + } + return false; +} + LLVM_DUMP_METHOD void MCParsedAsmOperand::dump() const { } diff --git a/llvm/lib/Target/LLVMBuild.txt b/llvm/lib/Target/LLVMBuild.txt index b9278afb..f6b48ca3 100644 --- a/llvm/lib/Target/LLVMBuild.txt +++ b/llvm/lib/Target/LLVMBuild.txt @@ -23,6 +23,7 @@ subdirectories = AArch64 Hexagon Mips + MSP430 PowerPC Sparc SystemZ diff --git a/llvm/lib/Target/MSP430/AsmParser/CMakeLists.txt b/llvm/lib/Target/MSP430/AsmParser/CMakeLists.txt new file mode 100644 index 00000000..1b22f4eb --- /dev/null +++ b/llvm/lib/Target/MSP430/AsmParser/CMakeLists.txt @@ -0,0 +1,5 @@ +include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) + +add_llvm_library(LLVMMSP430AsmParser + MSP430AsmParser.cpp +) diff --git a/llvm/lib/Target/MSP430/AsmParser/LLVMBuild.txt b/llvm/lib/Target/MSP430/AsmParser/LLVMBuild.txt new file mode 100644 index 00000000..58f67c07 --- /dev/null +++ b/llvm/lib/Target/MSP430/AsmParser/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===- lib/Target/MSP430/AsmParser/LLVMBuild.txt ----------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = MSP430AsmParser +parent = MSP430 +required_libraries = MC MCParser MSP430Desc MSP430Info Support +add_to_library_groups = MSP430 diff --git a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp new file mode 100644 index 00000000..267d0ec9 --- /dev/null +++ b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp @@ -0,0 +1,575 @@ +//===- MSP430AsmParser.cpp - Parse MSP430 assembly to MCInst instructions -===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "../MSP430.h" +#include "../MCTargetDesc/MSP430MCTargetDesc.h" + +#include "llvm/ADT/APInt.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringSwitch.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstBuilder.h" +#include "llvm/MC/MCParser/MCAsmLexer.h" +#include "llvm/MC/MCParser/MCParsedAsmOperand.h" +#include "llvm/MC/MCParser/MCTargetAsmParser.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCValue.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Support/TargetRegistry.h" + +#define DEBUG_TYPE "msp430-asm-parser" + +using namespace llvm_ks; + +namespace { + +/// Parses MSP430 assembly from a stream. +class MSP430AsmParser : public MCTargetAsmParser { + const MCSubtargetInfo &STI; + MCAsmParser &Parser; + const MCRegisterInfo *MRI; + + bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, + OperandVector &Operands, MCStreamer &Out, + uint64_t &ErrorInfo, + bool MatchingInlineAsm, unsigned int &ErrorCode, uint64_t &Address) override; + + bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc, unsigned int &ErrorCode) override; + + bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, + SMLoc NameLoc, OperandVector &Operands, unsigned int &ErrorCode) override; + + bool ParseDirective(AsmToken DirectiveID) override; + bool ParseDirectiveRefSym(AsmToken DirectiveID); + + unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, + unsigned Kind) override; + + bool parseJccInstruction(ParseInstructionInfo &Info, StringRef Name, + SMLoc NameLoc, OperandVector &Operands); + + bool ParseOperand(OperandVector &Operands, unsigned int &ErrorCode); + + bool ParseLiteralValues(unsigned Size, SMLoc L); + + MCAsmParser &getParser() const { return Parser; } + MCAsmLexer &getLexer() const { return Parser.getLexer(); } + + /// @name Auto-generated Matcher Functions + /// { + +#define GET_ASSEMBLER_HEADER +#include "../MSP430GenAsmMatcher.inc" + + /// } + +public: + MSP430AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, + const MCInstrInfo &MII, const MCTargetOptions &Options) + : MCTargetAsmParser(Options, STI), STI(STI), Parser(Parser) { + MCAsmParserExtension::Initialize(Parser); + MRI = getContext().getRegisterInfo(); + + setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); + } +}; + +/// A parsed MSP430 assembly operand. +class MSP430Operand : public MCParsedAsmOperand { + typedef MCParsedAsmOperand Base; + + enum KindTy { + k_Imm, + k_Reg, + k_Tok, + k_Mem, + k_IndReg, + k_PostIndReg + } Kind; + + struct Memory { + unsigned Reg; + const MCExpr *Offset; + }; + union { + const MCExpr *Imm; + unsigned Reg; + StringRef Tok; + Memory Mem; + }; + + SMLoc Start, End; + +public: + MSP430Operand(StringRef Tok, SMLoc const &S) + : Base(), Kind(k_Tok), Tok(Tok), Start(S), End(S) {} + MSP430Operand(KindTy Kind, unsigned Reg, SMLoc const &S, SMLoc const &E) + : Base(), Kind(Kind), Reg(Reg), Start(S), End(E) {} + MSP430Operand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E) + : Base(), Kind(k_Imm), Imm(Imm), Start(S), End(E) {} + MSP430Operand(unsigned Reg, MCExpr const *Expr, SMLoc const &S, SMLoc const &E) + : Base(), Kind(k_Mem), Mem({Reg, Expr}), Start(S), End(E) {} + + void addRegOperands(MCInst &Inst, unsigned N) const { + assert((Kind == k_Reg || Kind == k_IndReg || Kind == k_PostIndReg) && + "Unexpected operand kind"); + assert(N == 1 && "Invalid number of operands!"); + + Inst.addOperand(MCOperand::createReg(Reg)); + } + + void addExprOperand(MCInst &Inst, const MCExpr *Expr) const { + // Add as immediate when possible + if (!Expr) + Inst.addOperand(MCOperand::createImm(0)); + else if (const MCConstantExpr *CE = dyn_cast(Expr)) + Inst.addOperand(MCOperand::createImm(CE->getValue())); + else + Inst.addOperand(MCOperand::createExpr(Expr)); + } + + void addImmOperands(MCInst &Inst, unsigned N) const { + assert(Kind == k_Imm && "Unexpected operand kind"); + assert(N == 1 && "Invalid number of operands!"); + + addExprOperand(Inst, Imm); + } + + void addMemOperands(MCInst &Inst, unsigned N) const { + assert(Kind == k_Mem && "Unexpected operand kind"); + assert(N == 2 && "Invalid number of operands"); + + Inst.addOperand(MCOperand::createReg(Mem.Reg)); + addExprOperand(Inst, Mem.Offset); + } + + bool isReg() const { return Kind == k_Reg; } + bool isImm() const { return Kind == k_Imm; } + bool isToken() const { return Kind == k_Tok; } + bool isMem() const { return Kind == k_Mem; } + bool isIndReg() const { return Kind == k_IndReg; } + bool isPostIndReg() const { return Kind == k_PostIndReg; } + + bool isCGImm() const { + if (Kind != k_Imm) + return false; + + int64_t Val; + if (!Imm->evaluateAsAbsolute(Val)) + return false; + + if (Val == 0 || Val == 1 || Val == 2 || Val == 4 || Val == 8 || Val == -1) + return true; + + return false; + } + + StringRef getToken() const { + assert(Kind == k_Tok && "Invalid access!"); + return Tok; + } + + unsigned getReg() const { + assert(Kind == k_Reg && "Invalid access!"); + return Reg; + } + + void setReg(unsigned RegNo) { + assert(Kind == k_Reg && "Invalid access!"); + Reg = RegNo; + } + + static std::unique_ptr CreateToken(StringRef Str, SMLoc S) { + return make_unique(Str, S); + } + + static std::unique_ptr CreateReg(unsigned RegNum, SMLoc S, + SMLoc E) { + return make_unique(k_Reg, RegNum, S, E); + } + + static std::unique_ptr CreateImm(const MCExpr *Val, SMLoc S, + SMLoc E) { + return make_unique(Val, S, E); + } + + static std::unique_ptr CreateMem(unsigned RegNum, + const MCExpr *Val, + SMLoc S, SMLoc E) { + return make_unique(RegNum, Val, S, E); + } + + static std::unique_ptr CreateIndReg(unsigned RegNum, SMLoc S, + SMLoc E) { + return make_unique(k_IndReg, RegNum, S, E); + } + + static std::unique_ptr CreatePostIndReg(unsigned RegNum, SMLoc S, + SMLoc E) { + return make_unique(k_PostIndReg, RegNum, S, E); + } + + SMLoc getStartLoc() const { return Start; } + SMLoc getEndLoc() const { return End; } + + virtual void print(raw_ostream &O) const { + switch (Kind) { + case k_Tok: + O << "Token " << Tok; + break; + case k_Reg: + O << "Register " << Reg; + break; + case k_Imm: + O << "Immediate " << *Imm; + break; + case k_Mem: + O << "Memory "; + O << *Mem.Offset << "(" << Reg << ")"; + break; + case k_IndReg: + O << "RegInd " << Reg; + break; + case k_PostIndReg: + O << "PostInc " << Reg; + break; + } + } +}; +} // end anonymous namespace + +bool MSP430AsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode, + OperandVector &Operands, + MCStreamer &Out, + uint64_t &ErrorInfo, + bool MatchingInlineAsm, unsigned int &ErrorCode, uint64_t &Address) { + MCInst Inst; + unsigned MatchResult = + MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm); + + switch (MatchResult) { + case Match_Success: + Inst.setLoc(Loc); + Out.EmitInstruction(Inst, STI, ErrorCode); + return false; + case Match_MnemonicFail: + return Error(Loc, "invalid instruction mnemonic"); + case Match_InvalidOperand: { + SMLoc ErrorLoc = Loc; + if (ErrorInfo != ~0U) { + if (ErrorInfo >= Operands.size()) + return Error(ErrorLoc, "too few operands for instruction"); + + ErrorLoc = ((MSP430Operand &)*Operands[ErrorInfo]).getStartLoc(); + if (ErrorLoc == SMLoc()) + ErrorLoc = Loc; + } + return Error(ErrorLoc, "invalid operand for instruction"); + } + default: + return true; + } +} + +// Auto-generated by TableGen +static unsigned MatchRegisterName(StringRef Name); + +bool MSP430AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc, unsigned int &ErrorCode) { + if (getLexer().getKind() == AsmToken::Identifier) { + auto Name = getLexer().getTok().getIdentifier().lower(); + RegNo = MatchRegisterName(Name); + if (RegNo == MSP430::NoRegister) { +// RegNo = MatchRegisterAltName(Name); +// if (RegNo == MSP430::NoRegister) + return true; + } + + AsmToken const &T = getParser().getTok(); + StartLoc = T.getLoc(); + EndLoc = T.getEndLoc(); + getLexer().Lex(); // eat register token + + return false; + } + + return Error(StartLoc, "invalid register name"); +} + +bool MSP430AsmParser::parseJccInstruction(ParseInstructionInfo &Info, + StringRef Name, SMLoc NameLoc, + OperandVector &Operands) { + if (!Name.startswith_lower("j")) + return true; + + auto CC = Name.drop_front().lower(); + unsigned CondCode; + if (CC == "ne" || CC == "nz") + CondCode = MSP430CC::COND_NE; + else if (CC == "eq" || CC == "z") + CondCode = MSP430CC::COND_E; + else if (CC == "lo" || CC == "nc") + CondCode = MSP430CC::COND_LO; + else if (CC == "hs" || CC == "c") + CondCode = MSP430CC::COND_HS; + else if (CC == "n") + CondCode = MSP430CC::COND_N; + else if (CC == "ge") + CondCode = MSP430CC::COND_GE; + else if (CC == "l") + CondCode = MSP430CC::COND_L; + else if (CC == "mp") + CondCode = MSP430CC::COND_NONE; + else + return Error(NameLoc, "unknown instruction"); + + if (CondCode == (unsigned)MSP430CC::COND_NONE) + Operands.push_back(MSP430Operand::CreateToken("jmp", NameLoc)); + else { + Operands.push_back(MSP430Operand::CreateToken("j", NameLoc)); + const MCExpr *CCode = MCConstantExpr::create(CondCode, getContext()); + Operands.push_back(MSP430Operand::CreateImm(CCode, SMLoc(), SMLoc())); + } + + // Skip optional '$' sign. + if (getLexer().getKind() == AsmToken::Dollar) + getLexer().Lex(); // Eat '$' + + const MCExpr *Val; + SMLoc ExprLoc = getLexer().getLoc(); + if (getParser().parseExpression(Val)) + return Error(ExprLoc, "expected expression operand"); + + int64_t Res; + if (Val->evaluateAsAbsolute(Res)) + if (Res < -512 || Res > 511) + return Error(ExprLoc, "invalid jump offset"); + + Operands.push_back(MSP430Operand::CreateImm(Val, ExprLoc, + getLexer().getLoc())); + + if (getLexer().isNot(AsmToken::EndOfStatement)) { + SMLoc Loc = getLexer().getLoc(); + getParser().eatToEndOfStatement(); + return Error(Loc, "unexpected token"); + } + + getParser().Lex(); // Consume the EndOfStatement. + return false; +} + +bool MSP430AsmParser::ParseInstruction(ParseInstructionInfo &Info, + StringRef Name, SMLoc NameLoc, + OperandVector &Operands, unsigned int &ErrorCode) { + // Drop .w suffix + if (Name.endswith_lower(".w")) + Name = Name.drop_back(2); + + if (!parseJccInstruction(Info, Name, NameLoc, Operands)) + return false; + + // First operand is instruction mnemonic + Operands.push_back(MSP430Operand::CreateToken(Name, NameLoc)); + + // If there are no more operands, then finish + if (getLexer().is(AsmToken::EndOfStatement)) + return false; + + // Parse first operand + if (ParseOperand(Operands, ErrorCode)) + return true; + + // Parse second operand if any + if (getLexer().is(AsmToken::Comma)) { + getLexer().Lex(); // Eat ',' + if (ParseOperand(Operands, ErrorCode)) + return true; + } + + if (getLexer().isNot(AsmToken::EndOfStatement)) { + SMLoc Loc = getLexer().getLoc(); + getParser().eatToEndOfStatement(); + return Error(Loc, "unexpected token"); + } + + getParser().Lex(); // Consume the EndOfStatement. + return false; +} + +bool MSP430AsmParser::ParseDirectiveRefSym(AsmToken DirectiveID) { + StringRef Name; + if (getParser().parseIdentifier(Name)) + return TokError("expected identifier in directive"); + + MCSymbol *Sym = getContext().getOrCreateSymbol(Name); + getStreamer().EmitSymbolAttribute(Sym, MCSA_Global); + return false; +} + +bool MSP430AsmParser::ParseDirective(AsmToken DirectiveID) { + StringRef IDVal = DirectiveID.getIdentifier(); + if (IDVal.lower() == ".long") { + ParseLiteralValues(4, DirectiveID.getLoc()); + } else if (IDVal.lower() == ".word" || IDVal.lower() == ".short") { + ParseLiteralValues(2, DirectiveID.getLoc()); + } else if (IDVal.lower() == ".byte") { + ParseLiteralValues(1, DirectiveID.getLoc()); + } else if (IDVal.lower() == ".refsym") { + return ParseDirectiveRefSym(DirectiveID); + } + return true; +} + +bool MSP430AsmParser::ParseOperand(OperandVector &Operands, unsigned int &ErrorCode) { + switch (getLexer().getKind()) { + default: return true; + case AsmToken::Identifier: { + // try rN + unsigned RegNo; + SMLoc StartLoc, EndLoc; + if (!ParseRegister(RegNo, StartLoc, EndLoc, ErrorCode)) { + Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc)); + return false; + } + } + case AsmToken::Integer: + case AsmToken::Plus: + case AsmToken::Minus: { + SMLoc StartLoc = getParser().getTok().getLoc(); + const MCExpr *Val; + // Try constexpr[(rN)] + if (!getParser().parseExpression(Val)) { + unsigned RegNo = MSP430::PC; + SMLoc EndLoc = getParser().getTok().getLoc(); + // Try (rN) + if (getLexer().getKind() == AsmToken::LParen) { + getLexer().Lex(); // Eat '(' + SMLoc RegStartLoc; + if (ParseRegister(RegNo, RegStartLoc, EndLoc, ErrorCode)) + return true; + if (getLexer().getKind() != AsmToken::RParen) + return true; + EndLoc = getParser().getTok().getEndLoc(); + getLexer().Lex(); // Eat ')' + } + Operands.push_back(MSP430Operand::CreateMem(RegNo, Val, StartLoc, + EndLoc)); + return false; + } + return true; + } + case AsmToken::Amp: { + // Try &constexpr + SMLoc StartLoc = getParser().getTok().getLoc(); + getLexer().Lex(); // Eat '&' + const MCExpr *Val; + if (!getParser().parseExpression(Val)) { + SMLoc EndLoc = getParser().getTok().getLoc(); + Operands.push_back(MSP430Operand::CreateMem(MSP430::SR, Val, StartLoc, + EndLoc)); + return false; + } + return true; + } + case AsmToken::At: { + // Try @rN[+] + SMLoc StartLoc = getParser().getTok().getLoc(); + getLexer().Lex(); // Eat '@' + unsigned RegNo; + SMLoc RegStartLoc, EndLoc; + if (ParseRegister(RegNo, RegStartLoc, EndLoc, ErrorCode)) + return true; + if (getLexer().getKind() == AsmToken::Plus) { + Operands.push_back(MSP430Operand::CreatePostIndReg(RegNo, StartLoc, EndLoc)); + getLexer().Lex(); // Eat '+' + return false; + } + Operands.push_back(MSP430Operand::CreateIndReg(RegNo, StartLoc, EndLoc)); + return false; + } + case AsmToken::Hash: + // Try #constexpr + SMLoc StartLoc = getParser().getTok().getLoc(); + getLexer().Lex(); // Eat '#' + const MCExpr *Val; + if (!getParser().parseExpression(Val)) { + SMLoc EndLoc = getParser().getTok().getLoc(); + Operands.push_back(MSP430Operand::CreateImm(Val, StartLoc, EndLoc)); + return false; + } + return true; + } +} + +bool MSP430AsmParser::ParseLiteralValues(unsigned Size, SMLoc L) { + auto parseOne = [&]() -> bool { + const MCExpr *Value; + if (getParser().parseExpression(Value)) + return true; + getParser().getStreamer().EmitValue(Value, Size, L); + return false; + }; + return (getParser().parseMany(parseOne)); +} + +extern "C" void LLVMInitializeMSP430AsmParser() { + RegisterMCAsmParser X(llvm_ks::TheMSP430Target); +} + +#define GET_REGISTER_MATCHER +#define GET_MATCHER_IMPLEMENTATION +#include "../MSP430GenAsmMatcher.inc" + +static unsigned convertGR16ToGR8(unsigned Reg) { + switch (Reg) { + default: + llvm_unreachable("Unknown GR16 register"); + case MSP430::PC: return MSP430::PCB; + case MSP430::SP: return MSP430::SPB; + case MSP430::SR: return MSP430::SRB; + case MSP430::CG: return MSP430::CGB; + case MSP430::FP: return MSP430::FPB; + case MSP430::R5: return MSP430::R5B; + case MSP430::R6: return MSP430::R6B; + case MSP430::R7: return MSP430::R7B; + case MSP430::R8: return MSP430::R8B; + case MSP430::R9: return MSP430::R9B; + case MSP430::R10: return MSP430::R10B; + case MSP430::R11: return MSP430::R11B; + case MSP430::R12: return MSP430::R12B; + case MSP430::R13: return MSP430::R13B; + case MSP430::R14: return MSP430::R14B; + case MSP430::R15: return MSP430::R15B; + } +} + +unsigned MSP430AsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, + unsigned Kind) { + MSP430Operand &Op = static_cast(AsmOp); + + if (!Op.isReg()) + return Match_InvalidOperand; + + unsigned Reg = Op.getReg(); + bool isGR16 = + MSP430MCRegisterClasses[MSP430::GR16RegClassID].contains(Reg); + + if (isGR16 && (Kind == MCK_GR8)) { + Op.setReg(convertGR16ToGR8(Reg)); + return Match_Success; + } + + return Match_InvalidOperand; +} diff --git a/llvm/lib/Target/MSP430/CMakeLists.txt b/llvm/lib/Target/MSP430/CMakeLists.txt new file mode 100644 index 00000000..e69de29b diff --git a/llvm/lib/Target/MSP430/LLVMBuild.txt b/llvm/lib/Target/MSP430/LLVMBuild.txt new file mode 100644 index 00000000..201e9f9d --- /dev/null +++ b/llvm/lib/Target/MSP430/LLVMBuild.txt @@ -0,0 +1,22 @@ +;===- ./lib/Target/MSP430/LLVMBuild.txt ------------------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = TargetGroup +name = MSP430 +parent = Target +has_asmparser = 1 \ No newline at end of file diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt new file mode 100755 index 00000000..4e85f5b5 --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt @@ -0,0 +1,7 @@ +add_llvm_library(LLVMMSP430Desc + MSP430AsmBackend.cpp + MSP430ELFObjectWriter.cpp + MSP430MCAsmInfo.cpp + MSP430MCCodeEmitter.cpp + MSP430MCTargetDesc.cpp + ) diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/LLVMBuild.txt b/llvm/lib/Target/MSP430/MCTargetDesc/LLVMBuild.txt new file mode 100755 index 00000000..a305b2db --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===- ./lib/Target/MSP430/MCTargetDesc/LLVMBuild.txt -----------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = MSP430Desc +parent = MSP430 +required_libraries = MC MSP430AsmPrinter MSP430Info Support +add_to_library_groups = MSP430 diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp new file mode 100755 index 00000000..3f60963c --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp @@ -0,0 +1,152 @@ +//===-- MSP430AsmBackend.cpp - MSP430 Assembler Backend -------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MSP430FixupKinds.h" +#include "MSP430MCTargetDesc.h" +#include "llvm/ADT/APInt.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/MC/MCAsmBackend.h" +#include "llvm/MC/MCAssembler.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDirectives.h" +#include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCFixupKindInfo.h" +#include "llvm/MC/MCObjectWriter.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCTargetOptions.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm_ks; + +namespace { +class MSP430AsmBackend : public MCAsmBackend { + uint8_t OSABI; +public: + MSP430AsmBackend(uint8_t osABI) + : OSABI(osABI) {} + + // Override MCAsmBackend + unsigned getNumFixupKinds() const override { + return MSP430::NumTargetFixupKinds; + } + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { + const static MCFixupKindInfo Infos[MSP430::NumTargetFixupKinds] = { + // This table must be in the same order of enum in MSP430FixupKinds.h. + // + // name offset bits flags + {"fixup_32", 0, 32, 0}, + {"fixup_10_pcrel", 0, 10, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_16", 0, 16, 0}, + {"fixup_16_pcrel", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_16_byte", 0, 16, 0}, + {"fixup_16_pcrel_byte", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_2x_pcrel", 0, 10, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_rl_pcrel", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_8", 0, 8, 0}, + {"fixup_sym_diff", 0, 32, 0}, + }; + static_assert((array_lengthof(Infos)) == MSP430::NumTargetFixupKinds, + "Not all fixup kinds added to Infos array"); + + if (Kind < FirstTargetFixupKind) + return MCAsmBackend::getFixupKindInfo(Kind); + + return Infos[Kind - FirstTargetFixupKind]; + } + void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, + uint64_t Value, bool IsPCRel, unsigned int &KsError) const override; + bool mayNeedRelaxation(const MCInst &Inst) const override { + return false; + } + bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, + const MCRelaxableFragment *Fragment, + const MCAsmLayout &Layout, unsigned &KsError) const override { + return false; + } + void relaxInstruction(const MCInst &Inst, MCInst &Res) const override { + llvm_unreachable("MSP430 does do not have assembler relaxation"); + } + bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override { + if ((Count % 2) != 0) + return false; + + // The canonical nop on MSP430 is mov #0, r3 + uint64_t NopCount = Count / 2; + while (NopCount--) + OW->write16(0x0343); + + return true; + } + + MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { + return createMSP430ObjectWriter(OS, OSABI); + } + + uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, unsigned int &KsError) const { + unsigned Kind = Fixup.getKind(); + switch (Kind) { + case MSP430::fixup_10_pcrel: { + if (Value & 0x1) KsError = KS_ERR_ASM; + + // Offset is signed + int16_t Offset = Value; + // Jumps are in words + Offset >>= 1; + // PC points to the next instruction so decrement by one + --Offset; + + if (Offset < -512 || Offset > 511) KsError = KS_ERR_ASM; + + // Mask 10 bits + Offset &= 0x3ff; + + return Offset; + } + default: + return Value; + } + }; +}; + +void MSP430AsmBackend::applyFixup(const MCFixup &Fixup, + char *Data, + unsigned DataSize, + uint64_t Value, bool IsPCRel, + unsigned int &KsError) const { + Value = adjustFixupValue(Fixup, Value, KsError); + MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind()); + if (!Value) + return; // Doesn't change encoding. + + // Shift the value into position. + Value <<= Info.TargetOffset; + + unsigned Offset = Fixup.getOffset(); + unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8; + + assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); + + // For each byte of the fragment that the fixup touches, mask in the + // bits from the fixup value. + for (unsigned i = 0; i != NumBytes; ++i) { + Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); + } +} + +} // end anonymous namespace + +MCAsmBackend *llvm_ks::createMSP430MCAsmBackend(const Target &T, + const MCRegisterInfo &MRI, + const Triple &TT, + StringRef CPU) { + return new MSP430AsmBackend(ELF::ELFOSABI_STANDALONE); +} diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFBackport.h b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFBackport.h new file mode 100644 index 00000000..19368876 --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFBackport.h @@ -0,0 +1,28 @@ +#ifndef LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430ELFBACKPORT_H +#define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430ELFBACKPORT_H + +#define ELF_RELOC(name, value) name = value, + +namespace llvm_ks { + +const unsigned SHT_MSP430_ATTRIBUTES = 0x70000003U; + +enum { + ELF_RELOC(R_MSP430_NONE, 0) + ELF_RELOC(R_MSP430_32, 1) + ELF_RELOC(R_MSP430_10_PCREL, 2) + ELF_RELOC(R_MSP430_16, 3) + ELF_RELOC(R_MSP430_16_PCREL, 4) + ELF_RELOC(R_MSP430_16_BYTE, 5) + ELF_RELOC(R_MSP430_16_PCREL_BYTE, 6) + ELF_RELOC(R_MSP430_2X_PCREL, 7) + ELF_RELOC(R_MSP430_RL_PCREL, 8) + ELF_RELOC(R_MSP430_8, 9) + ELF_RELOC(R_MSP430_SYM_DIFF, 10) +}; + +} + +#undef ELF_RELOC + +#endif //LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430ELFBACKPORT_H diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFObjectWriter.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFObjectWriter.cpp new file mode 100755 index 00000000..8467384e --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFObjectWriter.cpp @@ -0,0 +1,59 @@ +//===-- MSP430ELFObjectWriter.cpp - MSP430 ELF Writer ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MSP430ELFBackport.h" +#include "MSP430FixupKinds.h" +#include "MSP430MCTargetDesc.h" +#include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/MC/MCFixup.h" +#include "llvm/MC/MCObjectWriter.h" +#include "llvm/MC/MCValue.h" +#include "llvm/Support/ErrorHandling.h" + +using namespace llvm_ks; + +namespace { +class MSP430ELFObjectWriter : public MCELFObjectTargetWriter { +public: + MSP430ELFObjectWriter(uint8_t OSABI) + : MCELFObjectTargetWriter(false, OSABI, ELF::EM_MSP430, + /*HasRelocationAddend*/ true) {} + + ~MSP430ELFObjectWriter() override {} + +protected: + unsigned getRelocType(MCContext &Ctx, const MCValue &Target, + const MCFixup &Fixup, bool IsPCRel) const override { + // Translate fixup kind to ELF relocation type. + switch ((unsigned)Fixup.getKind()) { + case FK_Data_1: return R_MSP430_8; + case FK_Data_2: return R_MSP430_16_BYTE; + case FK_Data_4: return R_MSP430_32; + case MSP430::fixup_32: return R_MSP430_32; + case MSP430::fixup_10_pcrel: return R_MSP430_10_PCREL; + case MSP430::fixup_16: return R_MSP430_16; + case MSP430::fixup_16_pcrel: return R_MSP430_16_PCREL; + case MSP430::fixup_16_byte: return R_MSP430_16_BYTE; + case MSP430::fixup_16_pcrel_byte: return R_MSP430_16_PCREL_BYTE; + case MSP430::fixup_2x_pcrel: return R_MSP430_2X_PCREL; + case MSP430::fixup_rl_pcrel: return R_MSP430_RL_PCREL; + case MSP430::fixup_8: return R_MSP430_8; + case MSP430::fixup_sym_diff: return R_MSP430_SYM_DIFF; + default: + llvm_unreachable("Invalid fixup kind"); + } + } +}; +} // end of anonymous namespace + +MCObjectWriter *llvm_ks::createMSP430ObjectWriter(raw_pwrite_stream &OS, + uint8_t OSABI) { + MCELFObjectTargetWriter *MOTW = new MSP430ELFObjectWriter(OSABI); + return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/false); +} \ No newline at end of file diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp new file mode 100644 index 00000000..acf042fe --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp @@ -0,0 +1,74 @@ +//===-- MSP430ELFStreamer.cpp - MSP430 ELF Target Streamer Methods --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides MSP430 specific target streamer methods. +// +//===----------------------------------------------------------------------===// + +#include "MSP430ELFBackport.h" +#include "MSP430MCTargetDesc.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCELFStreamer.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSubtargetInfo.h" + +using namespace llvm_ks; + +namespace llvm_ks { + +class MSP430TargetELFStreamer : public MCTargetStreamer { +public: + MCELFStreamer &getStreamer(); + MSP430TargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI); +}; + +// This part is for ELF object output. +MSP430TargetELFStreamer::MSP430TargetELFStreamer(MCStreamer &S, + const MCSubtargetInfo &STI) + : MCTargetStreamer(S) { + MCAssembler &MCA = getStreamer().getAssembler(); + unsigned EFlags = MCA.getELFHeaderEFlags(); + MCA.setELFHeaderEFlags(EFlags); + + // Emit build attributes section according to + // MSP430 EABI (slaa534.pdf, part 13). + MCSection *AttributeSection = getStreamer().getContext().getELFSection( + ".MSP430.attributes", SHT_MSP430_ATTRIBUTES, 0); + Streamer.SwitchSection(AttributeSection); + + bool Error; + // Format version. + Streamer.EmitIntValue(0x41, 1, Error); + // Subsection length. + Streamer.EmitIntValue(22, 4, Error); + // Vendor name string, zero-terminated. + Streamer.EmitBytes("mspabi"); + Streamer.EmitIntValue(0, 1, Error); + + // Attribute vector scope tag. 1 stands for the entire file. + Streamer.EmitIntValue(1, 1, Error); + // Attribute vector length. + Streamer.EmitIntValue(11, 4, Error); + // OFBA_MSPABI_Tag_ISA(4) = 1, MSP430 + Streamer.EmitIntValue(4, 1, Error); + Streamer.EmitIntValue(1, 1, Error); + // OFBA_MSPABI_Tag_Code_Model(6) = 1, Small + Streamer.EmitIntValue(6, 1, Error); + Streamer.EmitIntValue(1, 1, Error); + // OFBA_MSPABI_Tag_Data_Model(8) = 1, Small + Streamer.EmitIntValue(8, 1, Error); + Streamer.EmitIntValue(1, 1, Error); +} + +MCELFStreamer &MSP430TargetELFStreamer::getStreamer() { + return static_cast(Streamer); +} + +} // namespace llvm diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430FixupKinds.h b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430FixupKinds.h new file mode 100755 index 00000000..3f2340a4 --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430FixupKinds.h @@ -0,0 +1,53 @@ +//===-- MSP430FixupKinds.h - MSP430 Specific Fixup Entries ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430FIXUPKINDS_H +#define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430FIXUPKINDS_H + +#include "llvm/MC/MCFixup.h" + +#undef MSP430 + +namespace llvm_ks { +namespace MSP430 { + +// This table must be in the same order of +// MCFixupKindInfo Infos[MSP430::NumTargetFixupKinds] +// in MSP430AsmBackend.cpp. +// +enum Fixups { + // A 32 bit absolute fixup. + fixup_32 = FirstTargetFixupKind, + // A 10 bit PC relative fixup. + fixup_10_pcrel, + // A 16 bit absolute fixup. + fixup_16, + // A 16 bit PC relative fixup. + fixup_16_pcrel, + // A 16 bit absolute fixup for byte operations. + fixup_16_byte, + // A 16 bit PC relative fixup for command address. + fixup_16_pcrel_byte, + // A 10 bit PC relative fixup for complicated polymorphs. + fixup_2x_pcrel, + // A 16 bit relaxable fixup. + fixup_rl_pcrel, + // A 8 bit absolute fixup. + fixup_8, + // A 32 bit symbol difference fixup. + fixup_sym_diff, + + // Marker + LastTargetFixupKind, + NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind +}; +} // end namespace MSP430 +} // end namespace llvm + +#endif diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp new file mode 100755 index 00000000..87e5c9ff --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp @@ -0,0 +1,24 @@ +//===-- MSP430MCAsmInfo.cpp - MSP430 asm properties -----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declarations of the MSP430MCAsmInfo properties. +// +//===----------------------------------------------------------------------===// + +#include "MSP430MCAsmInfo.h" +using namespace llvm_ks; + +MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT) { + CalleeSaveStackSlotSize = 2; + + CommentString = ";"; + + AlignmentIsInBytes = false; + UsesELFSectionDirectiveForBSS = true; +} diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h new file mode 100755 index 00000000..47fd5427 --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h @@ -0,0 +1,30 @@ +//===-- MSP430MCAsmInfo.h - MSP430 asm properties --------------*- C++ -*--===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of the MSP430MCAsmInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCASMINFO_H +#define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCASMINFO_H + +#include "llvm/MC/MCAsmInfoELF.h" + +namespace llvm_ks { +class Triple; + +class MSP430MCAsmInfo : public MCAsmInfoELF { + +public: + explicit MSP430MCAsmInfo(const Triple &TT); +}; + +} // namespace llvm + +#endif diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp new file mode 100755 index 00000000..0d665098 --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp @@ -0,0 +1,211 @@ +//===-- MSP430MCCodeEmitter.cpp - Convert MSP430 code to machine code -----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the MSP430MCCodeEmitter class. +// +//===----------------------------------------------------------------------===// + +#include "../MSP430.h" +#include "MSP430MCTargetDesc.h" +#include "MSP430FixupKinds.h" + +#include "llvm/ADT/APFloat.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCFixup.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/Endian.h" +#include "llvm/Support/EndianStream.h" +#include "llvm/Support/raw_ostream.h" + +#define DEBUG_TYPE "mccodeemitter" + +namespace llvm_ks { + +class MSP430MCCodeEmitter : public MCCodeEmitter { + MCContext &Ctx; + MCInstrInfo const &MCII; + + // Offset keeps track of current word number being emitted + // inside a particular instruction. + mutable unsigned Offset; + + /// TableGen'erated function for getting the binary encoding for an + /// instruction. + uint64_t getBinaryCodeForInstr(const MCInst &MI, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + /// Returns the binary encoding of operands. + /// + /// If an operand requires relocation, the relocation is recorded + /// and zero is returned. + unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + unsigned getMemOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + unsigned getPCRelImmOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + unsigned getCGImmOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + unsigned getCCOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + +public: + MSP430MCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) + : Ctx(ctx), MCII(MCII) {} + + void encodeInstruction(MCInst &MI, raw_ostream &OS, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI, unsigned int &KsError) const override; +}; + +void MSP430MCCodeEmitter::encodeInstruction(MCInst &MI, raw_ostream &OS, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI, unsigned int &KsError) const { + const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); + // Get byte count of instruction. + unsigned Size = Desc.getSize(); + + // Initialize fixup offset + Offset = 2; + + uint64_t BinaryOpCode = getBinaryCodeForInstr(MI, Fixups, STI); + size_t WordCount = Size / 2; + + while (WordCount--) { + support::endian::write(OS, (uint16_t)BinaryOpCode, support::little); + BinaryOpCode >>= 16; + } +} + +unsigned MSP430MCCodeEmitter::getMachineOpValue(const MCInst &MI, + const MCOperand &MO, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + if (MO.isReg()) + return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); + + if (MO.isImm()) { + Offset += 2; + return MO.getImm(); + } + + assert(MO.isExpr() && "Expected expr operand"); + Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), + static_cast(MSP430::fixup_16_byte), MI.getLoc())); + Offset += 2; + return 0; +} + +unsigned MSP430MCCodeEmitter::getMemOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO1 = MI.getOperand(Op); + assert(MO1.isReg() && "Register operand expected"); + unsigned Reg = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg()); + + const MCOperand &MO2 = MI.getOperand(Op + 1); + if (MO2.isImm()) { + Offset += 2; + return (MO2.getImm() << 4) | Reg; + } + + assert(MO2.isExpr() && "Expr operand expected"); + MSP430::Fixups FixupKind; + switch (Reg) { + case 0: + FixupKind = MSP430::fixup_16_pcrel_byte; + break; + case 2: + FixupKind = MSP430::fixup_16_byte; + break; + default: + FixupKind = MSP430::fixup_16_byte; + break; + } + Fixups.push_back(MCFixup::create(Offset, MO2.getExpr(), + static_cast(FixupKind), MI.getLoc())); + Offset += 2; + return Reg; +} + +unsigned MSP430MCCodeEmitter::getPCRelImmOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(Op); + if (MO.isImm()) + return MO.getImm(); + + assert(MO.isExpr() && "Expr operand expected"); + Fixups.push_back(MCFixup::create(0, MO.getExpr(), + static_cast(MSP430::fixup_10_pcrel), MI.getLoc())); + return 0; +} + +unsigned MSP430MCCodeEmitter::getCGImmOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(Op); + assert(MO.isImm() && "Expr operand expected"); + + int64_t Imm = MO.getImm(); + switch (Imm) { + default: + llvm_unreachable("Invalid immediate value"); + case 4: return 0x22; + case 8: return 0x32; + case 0: return 0x03; + case 1: return 0x13; + case 2: return 0x23; + case -1: return 0x33; + } +} + +unsigned MSP430MCCodeEmitter::getCCOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(Op); + assert(MO.isImm() && "Immediate operand expected"); + switch (MO.getImm()) { + case MSP430CC::COND_NE: return 0; + case MSP430CC::COND_E: return 1; + case MSP430CC::COND_LO: return 2; + case MSP430CC::COND_HS: return 3; + case MSP430CC::COND_N: return 4; + case MSP430CC::COND_GE: return 5; + case MSP430CC::COND_L: return 6; + default: + llvm_unreachable("Unknown condition code"); + } +} + +MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII, + const MCRegisterInfo &MRI, + MCContext &Ctx) { + return new MSP430MCCodeEmitter(Ctx, MCII); +} + +#include "../MSP430GenMCCodeEmitter.inc" + +} // end of namespace llvm diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp new file mode 100755 index 00000000..91072155 --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -0,0 +1,73 @@ +//===-- MSP430MCTargetDesc.cpp - MSP430 Target Descriptions ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides MSP430 specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "MSP430MCTargetDesc.h" +#include "MSP430MCAsmInfo.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm_ks; + +#define GET_INSTRINFO_MC_DESC +#include "../MSP430GenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "../MSP430GenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "../MSP430GenRegisterInfo.inc" +#include "../MSP430.h" + +static MCAsmInfo *createMSP430MCAsmInfo(const MCRegisterInfo &MRI, + const Triple &TT) { + return new MSP430MCAsmInfo(TT); +} + +static MCInstrInfo *createMSP430MCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitMSP430MCInstrInfo(X); + return X; +} + +static MCRegisterInfo *createMSP430MCRegisterInfo(const Triple &TT) { + MCRegisterInfo *X = new MCRegisterInfo(); + InitMSP430MCRegisterInfo(X, MSP430::PC); + return X; +} + +static MCSubtargetInfo * +createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { + return createMSP430MCSubtargetInfoImpl(TT, CPU, FS); +} + +extern "C" void LLVMInitializeMSP430TargetMC() { + TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, + createMSP430MCInstrInfo); + + TargetRegistry::RegisterMCRegInfo(TheMSP430Target, + createMSP430MCRegisterInfo); + + TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target, + createMSP430MCSubtargetInfo); + + TargetRegistry::RegisterMCCodeEmitter(TheMSP430Target, + createMSP430MCCodeEmitter); + + TargetRegistry::RegisterMCAsmBackend(TheMSP430Target, + createMSP430MCAsmBackend); + + TargetRegistry::RegisterMCAsmInfo(TheMSP430Target, + createMSP430MCAsmInfo); +} diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h new file mode 100755 index 00000000..5ad7f4a3 --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h @@ -0,0 +1,63 @@ +//===-- MSP430MCTargetDesc.h - MSP430 Target Descriptions -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides MSP430 specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCTARGETDESC_H +#define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCTARGETDESC_H + +#include +#include "llvm/ADT/StringRef.h" +#include "llvm/MC/MCObjectWriter.h" +#include "llvm/Support/DataTypes.h" + +namespace llvm_ks { +class Target; +class Triple; +class MCAsmBackend; +class MCCodeEmitter; +class MCInstrInfo; +class MCSubtargetInfo; +class MCRegisterInfo; +class MCContext; +class MCTargetOptions; +class MCStreamer; +class MCTargetStreamer; + +extern Target TheMSP430Target; + +/// Creates a machine code emitter for MSP430. +MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII, + const MCRegisterInfo &MRI, + MCContext &Ctx); + +MCAsmBackend *createMSP430MCAsmBackend(const Target &T, + const MCRegisterInfo &MRI, + const Triple &TT, + StringRef CPU); + +MCObjectWriter *createMSP430ObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI); + +} // End llvm namespace + +// Defines symbolic names for MSP430 registers. +// This defines a mapping from register name to register number. +#define GET_REGINFO_ENUM +#include "../MSP430GenRegisterInfo.inc" + +// Defines symbolic names for the MSP430 instructions. +#define GET_INSTRINFO_ENUM +#include "../MSP430GenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "../MSP430GenSubtargetInfo.inc" + +#endif diff --git a/llvm/lib/Target/MSP430/MSP430.h b/llvm/lib/Target/MSP430/MSP430.h new file mode 100644 index 00000000..e23547bf --- /dev/null +++ b/llvm/lib/Target/MSP430/MSP430.h @@ -0,0 +1,84 @@ +//==-- MSP430.h - Top-level interface for MSP430 representation --*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the entry points for global functions defined in +// the LLVM MSP430 backend. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MSP430_H +#define LLVM_LIB_TARGET_MSP430_MSP430_H + +#include "MCTargetDesc/MSP430MCTargetDesc.h" +#include "llvm/Support/TargetRegistry.h" + +namespace MSP430CC { + // MSP430 specific condition code. + enum CondCodes { + COND_E = 0, // aka COND_Z + COND_NE = 1, // aka COND_NZ + COND_HS = 2, // aka COND_C + COND_LO = 3, // aka COND_NC + COND_GE = 4, + COND_L = 5, + COND_N = 6, // jump if negative + COND_NONE, // unconditional + + COND_INVALID = -1 + }; +} + +enum class DiagnosticPredicateTy { + Match, + NearMatch, + NoMatch, +}; + +// When an operand is parsed, the assembler will try to iterate through a set of +// possible operand classes that the operand might match and call the +// corresponding PredicateMethod to determine that. +// +// If there are two AsmOperands that would give a specific diagnostic if there +// is no match, there is currently no mechanism to distinguish which operand is +// a closer match. The DiagnosticPredicate distinguishes between 'completely +// no match' and 'near match', so the assembler can decide whether to give a +// specific diagnostic, or use 'InvalidOperand' and continue to find a +// 'better matching' diagnostic. +// +// For example: +// opcode opnd0, onpd1, opnd2 +// +// where: +// opnd2 could be an 'immediate of range [-8, 7]' +// opnd2 could be a 'register + shift/extend'. +// +// If opnd2 is a valid register, but with a wrong shift/extend suffix, it makes +// little sense to give a diagnostic that the operand should be an immediate +// in range [-8, 7]. +// +// This is a light-weight alternative to the 'NearMissInfo' approach +// below which collects *all* possible diagnostics. This alternative +// is optional and fully backward compatible with existing +// PredicateMethods that return a 'bool' (match or no match). +struct DiagnosticPredicate { + DiagnosticPredicateTy Type; + + explicit DiagnosticPredicate(bool Match) + : Type(Match ? DiagnosticPredicateTy::Match + : DiagnosticPredicateTy::NearMatch) {} + DiagnosticPredicate(DiagnosticPredicateTy T) : Type(T) {} + DiagnosticPredicate(const DiagnosticPredicate &) = default; + + operator bool() const { return Type == DiagnosticPredicateTy::Match; } + bool isMatch() const { return Type == DiagnosticPredicateTy::Match; } + bool isNearMatch() const { return Type == DiagnosticPredicateTy::NearMatch; } + bool isNoMatch() const { return Type == DiagnosticPredicateTy::NoMatch; } +}; + +#endif diff --git a/llvm/lib/Target/MSP430/MSP430GenAsmMatcher.inc b/llvm/lib/Target/MSP430/MSP430GenAsmMatcher.inc new file mode 100644 index 00000000..6e16e7a8 --- /dev/null +++ b/llvm/lib/Target/MSP430/MSP430GenAsmMatcher.inc @@ -0,0 +1,1109 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Assembly Matcher Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_ASSEMBLER_HEADER +#undef GET_ASSEMBLER_HEADER + // This should be included into the middle of the declaration of + // your subclasses implementation of MCTargetAsmParser. + uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const; + void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, + const OperandVector &Operands); + void convertToMapAndConstraints(unsigned Kind, + const OperandVector &Operands) override; + bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID); + unsigned MatchInstructionImpl(const OperandVector &Operands, + MCInst &Inst, + uint64_t &ErrorInfo, bool matchingInlineAsm, + unsigned VariantID = 0); +#endif // GET_ASSEMBLER_HEADER_INFO + + +#ifdef GET_OPERAND_DIAGNOSTIC_TYPES +#undef GET_OPERAND_DIAGNOSTIC_TYPES + +#endif // GET_OPERAND_DIAGNOSTIC_TYPES + + +#ifdef GET_REGISTER_MATCHER +#undef GET_REGISTER_MATCHER + +// Flags for subtarget features that participate in instruction matching. +enum SubtargetFeatureFlag : uint8_t { + Feature_None = 0 +}; + +static unsigned MatchRegisterName(StringRef Name) { + switch (Name.size()) { + default: break; + case 2: // 10 strings to match. + if (Name[0] != 'r') + break; + switch (Name[1]) { + default: break; + case '0': // 1 string to match. + return 5; // "r0" + case '1': // 1 string to match. + return 7; // "r1" + case '2': // 1 string to match. + return 9; // "r2" + case '3': // 1 string to match. + return 1; // "r3" + case '4': // 1 string to match. + return 3; // "r4" + case '5': // 1 string to match. + return 11; // "r5" + case '6': // 1 string to match. + return 12; // "r6" + case '7': // 1 string to match. + return 13; // "r7" + case '8': // 1 string to match. + return 14; // "r8" + case '9': // 1 string to match. + return 15; // "r9" + } + break; + case 3: // 16 strings to match. + if (Name[0] != 'r') + break; + switch (Name[1]) { + default: break; + case '0': // 1 string to match. + if (Name[2] != 'b') + break; + return 6; // "r0b" + case '1': // 7 strings to match. + switch (Name[2]) { + default: break; + case '0': // 1 string to match. + return 16; // "r10" + case '1': // 1 string to match. + return 17; // "r11" + case '2': // 1 string to match. + return 18; // "r12" + case '3': // 1 string to match. + return 19; // "r13" + case '4': // 1 string to match. + return 20; // "r14" + case '5': // 1 string to match. + return 21; // "r15" + case 'b': // 1 string to match. + return 8; // "r1b" + } + break; + case '2': // 1 string to match. + if (Name[2] != 'b') + break; + return 10; // "r2b" + case '3': // 1 string to match. + if (Name[2] != 'b') + break; + return 2; // "r3b" + case '4': // 1 string to match. + if (Name[2] != 'b') + break; + return 4; // "r4b" + case '5': // 1 string to match. + if (Name[2] != 'b') + break; + return 22; // "r5b" + case '6': // 1 string to match. + if (Name[2] != 'b') + break; + return 23; // "r6b" + case '7': // 1 string to match. + if (Name[2] != 'b') + break; + return 24; // "r7b" + case '8': // 1 string to match. + if (Name[2] != 'b') + break; + return 25; // "r8b" + case '9': // 1 string to match. + if (Name[2] != 'b') + break; + return 26; // "r9b" + } + break; + case 4: // 6 strings to match. + if (memcmp(Name.data()+0, "r1", 2)) + break; + switch (Name[2]) { + default: break; + case '0': // 1 string to match. + if (Name[3] != 'b') + break; + return 27; // "r10b" + case '1': // 1 string to match. + if (Name[3] != 'b') + break; + return 28; // "r11b" + case '2': // 1 string to match. + if (Name[3] != 'b') + break; + return 29; // "r12b" + case '3': // 1 string to match. + if (Name[3] != 'b') + break; + return 30; // "r13b" + case '4': // 1 string to match. + if (Name[3] != 'b') + break; + return 31; // "r14b" + case '5': // 1 string to match. + if (Name[3] != 'b') + break; + return 32; // "r15b" + } + break; + } + return 0; +} + +#endif // GET_REGISTER_MATCHER + + +#ifdef GET_SUBTARGET_FEATURE_NAME +#undef GET_SUBTARGET_FEATURE_NAME + +// User-level names for subtarget features that participate in +// instruction matching. +static const char *getSubtargetFeatureName(uint64_t Val) { + return "(unknown)"; +} + +#endif // GET_SUBTARGET_FEATURE_NAME + + +#ifdef GET_MATCHER_IMPLEMENTATION +#undef GET_MATCHER_IMPLEMENTATION + +namespace { +enum OperatorConversionKind { + CVT_Done, + CVT_Reg, + CVT_Tied, + CVT_95_Reg, + CVT_imm_95_0, + CVT_95_addMemOperands, + CVT_95_addImmOperands, + CVT_95_addRegOperands, + CVT_imm_95_1, + CVT_imm_95_2, + CVT_regSR, + CVT_imm_95_8, + CVT_imm_95__MINUS_1, + CVT_regCG, + CVT_imm_95_4, + CVT_NUM_CONVERTERS +}; + +enum InstructionConversionKind { + Convert__Reg1_0__Tie0__imm_95_0, + Convert__Mem2_0__imm_95_0, + Convert__Reg1_1__Tie0__Reg1_0, + Convert__Mem2_1__Reg1_0, + Convert__Reg1_1__Tie0__CGImm1_0, + Convert__Mem2_1__CGImm1_0, + Convert__Reg1_1__Tie0__Imm1_0, + Convert__Mem2_1__Imm1_0, + Convert__Reg1_1__Tie0__IndReg1_0, + Convert__Mem2_1__IndReg1_0, + Convert__Reg1_1__Tie0__Mem2_0, + Convert__Mem2_1__Mem2_0, + Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, + Convert__Mem2_1__PostIndReg1_0, + Convert__Reg1_1__imm_95_0__Reg1_0, + Convert__Reg1_1__imm_95_0__Mem2_0, + Convert__Reg1_1__Reg1_0, + Convert__Reg1_1__CGImm1_0, + Convert__Reg1_1__Imm1_0, + Convert__Reg1_1__Mem2_0, + Convert__Reg1_0, + Convert__Imm1_0, + Convert__Mem2_0, + Convert__Reg1_0__imm_95_0, + Convert__Reg1_0__Tie0__imm_95_1, + Convert__Mem2_0__imm_95_1, + Convert__Reg1_0__Tie0__imm_95_2, + Convert__Mem2_0__imm_95_2, + Convert__regSR__Tie0__imm_95_8, + Convert__Reg1_0__Tie0__imm_95__MINUS_1, + Convert__Mem2_0__imm_95__MINUS_1, + Convert__Imm1_1__Imm1_0, + Convert__Reg1_1__IndReg1_0, + Convert__Reg1_1__PostIndReg1_0__Tie1, + Convert__regCG__imm_95_0, + Convert__CGImm1_0, + Convert_NoOperands, + Convert__Reg1_0__Tie0__Reg1_0, + Convert__Mem2_0__Mem2_0, + Convert__Reg1_0__Tie0, + Convert__regSR__Tie0__imm_95_1, + Convert__regSR__Tie0__imm_95_4, + Convert__regSR__Tie0__imm_95_2, + CVT_NUM_SIGNATURES +}; + +} // end anonymous namespace + +static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = { + // Convert__Reg1_0__Tie0__imm_95_0 + { CVT_95_Reg, 1, CVT_Tied, 0, CVT_imm_95_0, 0, CVT_Done }, + // Convert__Mem2_0__imm_95_0 + { CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done }, + // Convert__Reg1_1__Tie0__Reg1_0 + { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_Done }, + // Convert__Mem2_1__Reg1_0 + { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done }, + // Convert__Reg1_1__Tie0__CGImm1_0 + { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done }, + // Convert__Mem2_1__CGImm1_0 + { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done }, + // Convert__Reg1_1__Tie0__Imm1_0 + { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done }, + // Convert__Mem2_1__Imm1_0 + { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done }, + // Convert__Reg1_1__Tie0__IndReg1_0 + { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addRegOperands, 1, CVT_Done }, + // Convert__Mem2_1__IndReg1_0 + { CVT_95_addMemOperands, 2, CVT_95_addRegOperands, 1, CVT_Done }, + // Convert__Reg1_1__Tie0__Mem2_0 + { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addMemOperands, 1, CVT_Done }, + // Convert__Mem2_1__Mem2_0 + { CVT_95_addMemOperands, 2, CVT_95_addMemOperands, 1, CVT_Done }, + // Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1 + { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Tied, 0, CVT_Tied, 1, CVT_Done }, + // Convert__Mem2_1__PostIndReg1_0 + { CVT_95_addMemOperands, 2, CVT_95_addRegOperands, 1, CVT_Done }, + // Convert__Reg1_1__imm_95_0__Reg1_0 + { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_Reg, 1, CVT_Done }, + // Convert__Reg1_1__imm_95_0__Mem2_0 + { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemOperands, 1, CVT_Done }, + // Convert__Reg1_1__Reg1_0 + { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done }, + // Convert__Reg1_1__CGImm1_0 + { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done }, + // Convert__Reg1_1__Imm1_0 + { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done }, + // Convert__Reg1_1__Mem2_0 + { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done }, + // Convert__Reg1_0 + { CVT_95_Reg, 1, CVT_Done }, + // Convert__Imm1_0 + { CVT_95_addImmOperands, 1, CVT_Done }, + // Convert__Mem2_0 + { CVT_95_addMemOperands, 1, CVT_Done }, + // Convert__Reg1_0__imm_95_0 + { CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done }, + // Convert__Reg1_0__Tie0__imm_95_1 + { CVT_95_Reg, 1, CVT_Tied, 0, CVT_imm_95_1, 0, CVT_Done }, + // Convert__Mem2_0__imm_95_1 + { CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done }, + // Convert__Reg1_0__Tie0__imm_95_2 + { CVT_95_Reg, 1, CVT_Tied, 0, CVT_imm_95_2, 0, CVT_Done }, + // Convert__Mem2_0__imm_95_2 + { CVT_95_addMemOperands, 1, CVT_imm_95_2, 0, CVT_Done }, + // Convert__regSR__Tie0__imm_95_8 + { CVT_regSR, 0, CVT_Tied, 0, CVT_imm_95_8, 0, CVT_Done }, + // Convert__Reg1_0__Tie0__imm_95__MINUS_1 + { CVT_95_Reg, 1, CVT_Tied, 0, CVT_imm_95__MINUS_1, 0, CVT_Done }, + // Convert__Mem2_0__imm_95__MINUS_1 + { CVT_95_addMemOperands, 1, CVT_imm_95__MINUS_1, 0, CVT_Done }, + // Convert__Imm1_1__Imm1_0 + { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done }, + // Convert__Reg1_1__IndReg1_0 + { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Done }, + // Convert__Reg1_1__PostIndReg1_0__Tie1 + { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Tied, 1, CVT_Done }, + // Convert__regCG__imm_95_0 + { CVT_regCG, 0, CVT_imm_95_0, 0, CVT_Done }, + // Convert__CGImm1_0 + { CVT_95_addImmOperands, 1, CVT_Done }, + // Convert_NoOperands + { CVT_Done }, + // Convert__Reg1_0__Tie0__Reg1_0 + { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 1, CVT_Done }, + // Convert__Mem2_0__Mem2_0 + { CVT_95_addMemOperands, 1, CVT_95_addMemOperands, 1, CVT_Done }, + // Convert__Reg1_0__Tie0 + { CVT_95_Reg, 1, CVT_Tied, 0, CVT_Done }, + // Convert__regSR__Tie0__imm_95_1 + { CVT_regSR, 0, CVT_Tied, 0, CVT_imm_95_1, 0, CVT_Done }, + // Convert__regSR__Tie0__imm_95_4 + { CVT_regSR, 0, CVT_Tied, 0, CVT_imm_95_4, 0, CVT_Done }, + // Convert__regSR__Tie0__imm_95_2 + { CVT_regSR, 0, CVT_Tied, 0, CVT_imm_95_2, 0, CVT_Done }, +}; + +void MSP430AsmParser:: +convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, + const OperandVector &Operands) { + assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); + const uint8_t *Converter = ConversionTable[Kind]; + unsigned OpIdx; + Inst.setOpcode(Opcode); + for (const uint8_t *p = Converter; *p; p+= 2) { + OpIdx = *(p + 1); + switch (*p) { + default: llvm_unreachable("invalid conversion entry!"); + case CVT_Reg: + static_cast(*Operands[OpIdx]).addRegOperands(Inst, 1); + break; + case CVT_Tied: + Inst.addOperand(Inst.getOperand(OpIdx)); + break; + case CVT_95_Reg: + static_cast(*Operands[OpIdx]).addRegOperands(Inst, 1); + break; + case CVT_imm_95_0: + Inst.addOperand(MCOperand::createImm(0)); + break; + case CVT_95_addMemOperands: + static_cast(*Operands[OpIdx]).addMemOperands(Inst, 2); + break; + case CVT_95_addImmOperands: + static_cast(*Operands[OpIdx]).addImmOperands(Inst, 1); + break; + case CVT_95_addRegOperands: + static_cast(*Operands[OpIdx]).addRegOperands(Inst, 1); + break; + case CVT_imm_95_1: + Inst.addOperand(MCOperand::createImm(1)); + break; + case CVT_imm_95_2: + Inst.addOperand(MCOperand::createImm(2)); + break; + case CVT_regSR: + Inst.addOperand(MCOperand::createReg(MSP430::SR)); + break; + case CVT_imm_95_8: + Inst.addOperand(MCOperand::createImm(8)); + break; + case CVT_imm_95__MINUS_1: + Inst.addOperand(MCOperand::createImm(-1)); + break; + case CVT_regCG: + Inst.addOperand(MCOperand::createReg(MSP430::CG)); + break; + case CVT_imm_95_4: + Inst.addOperand(MCOperand::createImm(4)); + break; + } + } +} + +void MSP430AsmParser:: +convertToMapAndConstraints(unsigned Kind, + const OperandVector &Operands) { + assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); + unsigned NumMCOperands = 0; + const uint8_t *Converter = ConversionTable[Kind]; + for (const uint8_t *p = Converter; *p; p+= 2) { + switch (*p) { + default: llvm_unreachable("invalid conversion entry!"); + case CVT_Reg: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint("r"); + ++NumMCOperands; + break; + case CVT_Tied: + ++NumMCOperands; + break; + case CVT_95_Reg: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint("r"); + NumMCOperands += 1; + break; + case CVT_imm_95_0: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint(""); + ++NumMCOperands; + break; + case CVT_95_addMemOperands: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint("m"); + NumMCOperands += 2; + break; + case CVT_95_addImmOperands: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint("m"); + NumMCOperands += 1; + break; + case CVT_95_addRegOperands: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint("m"); + NumMCOperands += 1; + break; + case CVT_imm_95_1: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint(""); + ++NumMCOperands; + break; + case CVT_imm_95_2: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint(""); + ++NumMCOperands; + break; + case CVT_regSR: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint("m"); + ++NumMCOperands; + break; + case CVT_imm_95_8: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint(""); + ++NumMCOperands; + break; + case CVT_imm_95__MINUS_1: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint(""); + ++NumMCOperands; + break; + case CVT_regCG: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint("m"); + ++NumMCOperands; + break; + case CVT_imm_95_4: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint(""); + ++NumMCOperands; + break; + } + } +} + +namespace { + +/// MatchClassKind - The kinds of classes which participate in +/// instruction matching. +enum MatchClassKind { + InvalidMatchClass = 0, + OptionalMatchClass = 1, + MCK_GR16, // register class 'GR16' + MCK_GR8, // register class 'GR8' + MCK_CGImm, // user defined class 'CGImmAsmOperand' + MCK_Imm, // user defined class 'ImmAsmOperand' + MCK_IndReg, // user defined class 'IndRegAsmOperand' + MCK_Mem, // user defined class 'MemAsmOperand' + MCK_PostIndReg, // user defined class 'PostIndRegAsmOperand' + NumMatchClassKinds +}; + +} + +static MatchClassKind matchTokenString(StringRef Name) { + return InvalidMatchClass; +} + +/// isSubclass - Compute whether \p A is a subclass of \p B. +static bool isSubclass(MatchClassKind A, MatchClassKind B) { + if (A == B) + return true; + + return false; +} + +static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) { + MSP430Operand &Operand = (MSP430Operand&)GOp; + if (Kind == InvalidMatchClass) + return MCTargetAsmParser::Match_InvalidOperand; + + if (Operand.isToken()) + return isSubclass(matchTokenString(Operand.getToken()), Kind) ? + MCTargetAsmParser::Match_Success : + MCTargetAsmParser::Match_InvalidOperand; + + switch (Kind) { + default: break; + // 'CGImm' class + case MCK_CGImm: + if (Operand.isCGImm()) + return MCTargetAsmParser::Match_Success; + break; + // 'Imm' class + case MCK_Imm: + if (Operand.isImm()) + return MCTargetAsmParser::Match_Success; + break; + // 'IndReg' class + case MCK_IndReg: + if (Operand.isIndReg()) + return MCTargetAsmParser::Match_Success; + break; + // 'Mem' class + case MCK_Mem: + if (Operand.isMem()) + return MCTargetAsmParser::Match_Success; + break; + // 'PostIndReg' class + case MCK_PostIndReg: + if (Operand.isPostIndReg()) + return MCTargetAsmParser::Match_Success; + break; + } // end switch (Kind) + + if (Operand.isReg()) { + MatchClassKind OpKind; + switch (Operand.getReg()) { + default: OpKind = InvalidMatchClass; break; + case MSP430::PCB: OpKind = MCK_GR8; break; + case MSP430::SPB: OpKind = MCK_GR8; break; + case MSP430::SRB: OpKind = MCK_GR8; break; + case MSP430::CGB: OpKind = MCK_GR8; break; + case MSP430::FPB: OpKind = MCK_GR8; break; + case MSP430::R5B: OpKind = MCK_GR8; break; + case MSP430::R6B: OpKind = MCK_GR8; break; + case MSP430::R7B: OpKind = MCK_GR8; break; + case MSP430::R8B: OpKind = MCK_GR8; break; + case MSP430::R9B: OpKind = MCK_GR8; break; + case MSP430::R10B: OpKind = MCK_GR8; break; + case MSP430::R11B: OpKind = MCK_GR8; break; + case MSP430::R12B: OpKind = MCK_GR8; break; + case MSP430::R13B: OpKind = MCK_GR8; break; + case MSP430::R14B: OpKind = MCK_GR8; break; + case MSP430::R15B: OpKind = MCK_GR8; break; + case MSP430::PC: OpKind = MCK_GR16; break; + case MSP430::SP: OpKind = MCK_GR16; break; + case MSP430::SR: OpKind = MCK_GR16; break; + case MSP430::CG: OpKind = MCK_GR16; break; + case MSP430::FP: OpKind = MCK_GR16; break; + case MSP430::R5: OpKind = MCK_GR16; break; + case MSP430::R6: OpKind = MCK_GR16; break; + case MSP430::R7: OpKind = MCK_GR16; break; + case MSP430::R8: OpKind = MCK_GR16; break; + case MSP430::R9: OpKind = MCK_GR16; break; + case MSP430::R10: OpKind = MCK_GR16; break; + case MSP430::R11: OpKind = MCK_GR16; break; + case MSP430::R12: OpKind = MCK_GR16; break; + case MSP430::R13: OpKind = MCK_GR16; break; + case MSP430::R14: OpKind = MCK_GR16; break; + case MSP430::R15: OpKind = MCK_GR16; break; + } + return isSubclass(OpKind, Kind) ? MCTargetAsmParser::Match_Success : + MCTargetAsmParser::Match_InvalidOperand; + } + + return MCTargetAsmParser::Match_InvalidOperand; +} + +uint64_t MSP430AsmParser:: +ComputeAvailableFeatures(const FeatureBitset& FB) const { + uint64_t Features = 0; + return Features; +} + +static const char *const MnemonicTable = + "\003adc\005adc.b\003add\005add.b\004addc\006addc.b\003and\005and.b\005b" + "ic.b\005bic.w\003bis\005bis.b\003bit\005bit.b\002br\004call\003clr\005c" + "lr.b\003cmp\005cmp.b\004dadc\006dadc.b\004dadd\006dadd.b\003dec\005dec." + "b\004decd\006decd.b\004eint\003inc\005inc.b\004incd\006incd.b\003inv\005" + "inv.b\001j\003jmp\003mov\005mov.b\003nop\003pop\004push\006push.b\003re" + "t\004reti\003rla\005rla.b\003rlc\005rlc.b\003rra\005rra.b\003rrc\005rrc" + ".b\003sbc\005sbc.b\004setc\004setn\004setz\003sub\005sub.b\004subc\006s" + "ubc.b\004swpb\003sxt\003tst\005tst.b\003xor\005xor.b"; + +namespace { + struct MatchEntry { + uint16_t Mnemonic; + uint16_t Opcode; + uint16_t ConvertFn; + uint8_t RequiredFeatures; + uint8_t Classes[2]; + StringRef getMnemonic() const { + return StringRef(MnemonicTable + Mnemonic + 1, + MnemonicTable[Mnemonic]); + } + }; + + // Predicate for searching for an opcode. + struct LessOpcode { + bool operator()(const MatchEntry &LHS, StringRef RHS) { + return LHS.getMnemonic() < RHS; + } + bool operator()(StringRef LHS, const MatchEntry &RHS) { + return LHS < RHS.getMnemonic(); + } + bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) { + return LHS.getMnemonic() < RHS.getMnemonic(); + } + }; +} // end anonymous namespace. + +static const MatchEntry MatchTable0[] = { + { 0 /* adc */, MSP430::ADDC16rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR16 }, }, + { 0 /* adc */, MSP430::ADDC16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 4 /* adc.b */, MSP430::ADDC8rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR8 }, }, + { 4 /* adc.b */, MSP430::ADDC8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 10 /* add */, MSP430::ADD16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 10 /* add */, MSP430::ADD16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 10 /* add */, MSP430::ADD16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 10 /* add */, MSP430::ADD16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 10 /* add */, MSP430::ADD16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 10 /* add */, MSP430::ADD16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 10 /* add */, MSP430::ADD16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 10 /* add */, MSP430::ADD16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 10 /* add */, MSP430::ADD16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 10 /* add */, MSP430::ADD16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 10 /* add */, MSP430::ADD16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 10 /* add */, MSP430::ADD16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 14 /* add.b */, MSP430::ADD8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 14 /* add.b */, MSP430::ADD8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 14 /* add.b */, MSP430::ADD8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 14 /* add.b */, MSP430::ADD8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 14 /* add.b */, MSP430::ADD8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 14 /* add.b */, MSP430::ADD8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 14 /* add.b */, MSP430::ADD8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 14 /* add.b */, MSP430::ADD8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 14 /* add.b */, MSP430::ADD8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 14 /* add.b */, MSP430::ADD8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 14 /* add.b */, MSP430::ADD8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 14 /* add.b */, MSP430::ADD8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 20 /* addc */, MSP430::ADDC16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 20 /* addc */, MSP430::ADDC16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 20 /* addc */, MSP430::ADDC16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 20 /* addc */, MSP430::ADDC16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 20 /* addc */, MSP430::ADDC16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 20 /* addc */, MSP430::ADDC16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 20 /* addc */, MSP430::ADDC16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 20 /* addc */, MSP430::ADDC16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 20 /* addc */, MSP430::ADDC16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 20 /* addc */, MSP430::ADDC16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 20 /* addc */, MSP430::ADDC16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 20 /* addc */, MSP430::ADDC16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 25 /* addc.b */, MSP430::ADDC8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 25 /* addc.b */, MSP430::ADDC8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 25 /* addc.b */, MSP430::ADDC8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 25 /* addc.b */, MSP430::ADDC8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 25 /* addc.b */, MSP430::ADDC8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 25 /* addc.b */, MSP430::ADDC8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 25 /* addc.b */, MSP430::ADDC8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 25 /* addc.b */, MSP430::ADDC8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 25 /* addc.b */, MSP430::ADDC8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 25 /* addc.b */, MSP430::ADDC8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 25 /* addc.b */, MSP430::ADDC8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 25 /* addc.b */, MSP430::ADDC8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 32 /* and */, MSP430::AND16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 32 /* and */, MSP430::AND16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 32 /* and */, MSP430::AND16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 32 /* and */, MSP430::AND16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 32 /* and */, MSP430::AND16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 32 /* and */, MSP430::AND16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 32 /* and */, MSP430::AND16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 32 /* and */, MSP430::AND16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 32 /* and */, MSP430::AND16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 32 /* and */, MSP430::AND16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 32 /* and */, MSP430::AND16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 32 /* and */, MSP430::AND16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 36 /* and.b */, MSP430::AND8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 36 /* and.b */, MSP430::AND8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 36 /* and.b */, MSP430::AND8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 36 /* and.b */, MSP430::AND8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 36 /* and.b */, MSP430::AND8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 36 /* and.b */, MSP430::AND8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 36 /* and.b */, MSP430::AND8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 36 /* and.b */, MSP430::AND8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 36 /* and.b */, MSP430::AND8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 36 /* and.b */, MSP430::AND8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 36 /* and.b */, MSP430::AND8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 36 /* and.b */, MSP430::AND8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 42 /* bic.b */, MSP430::BIC8rr, Convert__Reg1_1__imm_95_0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 42 /* bic.b */, MSP430::BIC8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 42 /* bic.b */, MSP430::BIC8rm, Convert__Reg1_1__imm_95_0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 42 /* bic.b */, MSP430::BIC8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 48 /* bic.w */, MSP430::BIC16rr, Convert__Reg1_1__imm_95_0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 48 /* bic.w */, MSP430::BIC16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 48 /* bic.w */, MSP430::BIC16rm, Convert__Reg1_1__imm_95_0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 48 /* bic.w */, MSP430::BIC16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 54 /* bis */, MSP430::BIS16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 54 /* bis */, MSP430::BIS16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 54 /* bis */, MSP430::BIS16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 54 /* bis */, MSP430::BIS16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 54 /* bis */, MSP430::BIS16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 54 /* bis */, MSP430::BIS16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 54 /* bis */, MSP430::BIS16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 54 /* bis */, MSP430::BIS16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 54 /* bis */, MSP430::BIS16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 54 /* bis */, MSP430::BIS16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 54 /* bis */, MSP430::BIS16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 54 /* bis */, MSP430::BIS16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 58 /* bis.b */, MSP430::BIS8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 58 /* bis.b */, MSP430::BIS8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 58 /* bis.b */, MSP430::BIS8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 58 /* bis.b */, MSP430::BIS8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 58 /* bis.b */, MSP430::BIS8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 58 /* bis.b */, MSP430::BIS8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 58 /* bis.b */, MSP430::BIS8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 58 /* bis.b */, MSP430::BIS8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 58 /* bis.b */, MSP430::BIS8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 58 /* bis.b */, MSP430::BIS8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 58 /* bis.b */, MSP430::BIS8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 58 /* bis.b */, MSP430::BIS8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 64 /* bit */, MSP430::BIT16rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 64 /* bit */, MSP430::BIT16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 64 /* bit */, MSP430::BIT16rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 64 /* bit */, MSP430::BIT16ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 64 /* bit */, MSP430::BIT16mc, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 64 /* bit */, MSP430::BIT16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 64 /* bit */, MSP430::BIT16rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 64 /* bit */, MSP430::BIT16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 68 /* bit.b */, MSP430::BIT8rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 68 /* bit.b */, MSP430::BIT8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 68 /* bit.b */, MSP430::BIT8rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 68 /* bit.b */, MSP430::BIT8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 68 /* bit.b */, MSP430::BIT8ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 68 /* bit.b */, MSP430::BIT8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 68 /* bit.b */, MSP430::BIT8rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 68 /* bit.b */, MSP430::BIT8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 74 /* br */, MSP430::Br, Convert__Reg1_0, 0, { MCK_GR16 }, }, + { 74 /* br */, MSP430::Bi, Convert__Imm1_0, 0, { MCK_Imm }, }, + { 74 /* br */, MSP430::Bm, Convert__Mem2_0, 0, { MCK_Mem }, }, + { 77 /* call */, MSP430::CALLr, Convert__Reg1_0, 0, { MCK_GR16 }, }, + { 77 /* call */, MSP430::CALLi, Convert__Imm1_0, 0, { MCK_Imm }, }, + { 77 /* call */, MSP430::CALLm, Convert__Mem2_0, 0, { MCK_Mem }, }, + { 82 /* clr */, MSP430::MOV16rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR16 }, }, + { 82 /* clr */, MSP430::MOV16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 86 /* clr.b */, MSP430::MOV8rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR8 }, }, + { 86 /* clr.b */, MSP430::MOV8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 92 /* cmp */, MSP430::CMP16rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 92 /* cmp */, MSP430::CMP16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 92 /* cmp */, MSP430::CMP16rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 92 /* cmp */, MSP430::CMP16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 92 /* cmp */, MSP430::CMP16ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 92 /* cmp */, MSP430::CMP16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 92 /* cmp */, MSP430::CMP16rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 96 /* cmp.b */, MSP430::CMP8rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 96 /* cmp.b */, MSP430::CMP8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 96 /* cmp.b */, MSP430::CMP8rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 96 /* cmp.b */, MSP430::CMP8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 96 /* cmp.b */, MSP430::CMP8ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 96 /* cmp.b */, MSP430::CMP8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 96 /* cmp.b */, MSP430::CMP8rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 102 /* dadc */, MSP430::DADD16rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR16 }, }, + { 102 /* dadc */, MSP430::DADD16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 107 /* dadc.b */, MSP430::DADD8rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR8 }, }, + { 107 /* dadc.b */, MSP430::DADD8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 114 /* dadd */, MSP430::DADD16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 114 /* dadd */, MSP430::DADD16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 114 /* dadd */, MSP430::DADD16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 114 /* dadd */, MSP430::DADD16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 114 /* dadd */, MSP430::DADD16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 114 /* dadd */, MSP430::DADD16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 114 /* dadd */, MSP430::DADD16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 114 /* dadd */, MSP430::DADD16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 114 /* dadd */, MSP430::DADD16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 114 /* dadd */, MSP430::DADD16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 114 /* dadd */, MSP430::DADD16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 114 /* dadd */, MSP430::DADD16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 119 /* dadd.b */, MSP430::DADD8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 119 /* dadd.b */, MSP430::DADD8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 119 /* dadd.b */, MSP430::DADD8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 119 /* dadd.b */, MSP430::DADD8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 119 /* dadd.b */, MSP430::DADD8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 119 /* dadd.b */, MSP430::DADD8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 119 /* dadd.b */, MSP430::DADD8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 119 /* dadd.b */, MSP430::DADD8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 119 /* dadd.b */, MSP430::DADD8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 119 /* dadd.b */, MSP430::DADD8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 119 /* dadd.b */, MSP430::DADD8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 119 /* dadd.b */, MSP430::DADD8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 126 /* dec */, MSP430::SUB16rc, Convert__Reg1_0__Tie0__imm_95_1, 0, { MCK_GR16 }, }, + { 126 /* dec */, MSP430::SUB16mc, Convert__Mem2_0__imm_95_1, 0, { MCK_Mem }, }, + { 130 /* dec.b */, MSP430::SUB8rc, Convert__Reg1_0__Tie0__imm_95_1, 0, { MCK_GR8 }, }, + { 130 /* dec.b */, MSP430::SUB8mc, Convert__Mem2_0__imm_95_1, 0, { MCK_Mem }, }, + { 136 /* decd */, MSP430::SUB16rc, Convert__Reg1_0__Tie0__imm_95_2, 0, { MCK_GR16 }, }, + { 136 /* decd */, MSP430::SUB16mc, Convert__Mem2_0__imm_95_2, 0, { MCK_Mem }, }, + { 141 /* decd.b */, MSP430::SUB8rc, Convert__Reg1_0__Tie0__imm_95_2, 0, { MCK_GR8 }, }, + { 141 /* decd.b */, MSP430::SUB8mc, Convert__Mem2_0__imm_95_2, 0, { MCK_Mem }, }, + { 148 /* eint */, MSP430::BIS16rc, Convert__regSR__Tie0__imm_95_8, 0, { }, }, + { 153 /* inc */, MSP430::ADD16rc, Convert__Reg1_0__Tie0__imm_95_1, 0, { MCK_GR16 }, }, + { 153 /* inc */, MSP430::ADD16mc, Convert__Mem2_0__imm_95_1, 0, { MCK_Mem }, }, + { 157 /* inc.b */, MSP430::ADD8rc, Convert__Reg1_0__Tie0__imm_95_1, 0, { MCK_GR8 }, }, + { 157 /* inc.b */, MSP430::ADD8mc, Convert__Mem2_0__imm_95_1, 0, { MCK_Mem }, }, + { 163 /* incd */, MSP430::ADD16rc, Convert__Reg1_0__Tie0__imm_95_2, 0, { MCK_GR16 }, }, + { 163 /* incd */, MSP430::ADD16mc, Convert__Mem2_0__imm_95_2, 0, { MCK_Mem }, }, + { 168 /* incd.b */, MSP430::ADD8rc, Convert__Reg1_0__Tie0__imm_95_2, 0, { MCK_GR8 }, }, + { 168 /* incd.b */, MSP430::ADD8mc, Convert__Mem2_0__imm_95_2, 0, { MCK_Mem }, }, + { 175 /* inv */, MSP430::XOR16rc, Convert__Reg1_0__Tie0__imm_95__MINUS_1, 0, { MCK_GR16 }, }, + { 175 /* inv */, MSP430::XOR16mc, Convert__Mem2_0__imm_95__MINUS_1, 0, { MCK_Mem }, }, + { 179 /* inv.b */, MSP430::XOR8rc, Convert__Reg1_0__Tie0__imm_95__MINUS_1, 0, { MCK_GR8 }, }, + { 179 /* inv.b */, MSP430::XOR8mc, Convert__Mem2_0__imm_95__MINUS_1, 0, { MCK_Mem }, }, + { 185 /* j */, MSP430::JCC, Convert__Imm1_1__Imm1_0, 0, { MCK_Imm, MCK_Imm }, }, + { 187 /* jmp */, MSP430::JMP, Convert__Imm1_0, 0, { MCK_Imm }, }, + { 191 /* mov */, MSP430::MOV16rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 191 /* mov */, MSP430::MOV16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 191 /* mov */, MSP430::MOV16rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 191 /* mov */, MSP430::MOV16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 191 /* mov */, MSP430::MOV16ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 191 /* mov */, MSP430::MOV16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 191 /* mov */, MSP430::MOV16rn, Convert__Reg1_1__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 191 /* mov */, MSP430::MOV16rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 191 /* mov */, MSP430::MOV16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 191 /* mov */, MSP430::MOV16rp, Convert__Reg1_1__PostIndReg1_0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 195 /* mov.b */, MSP430::MOV8rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 195 /* mov.b */, MSP430::MOV8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 195 /* mov.b */, MSP430::MOV8rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 195 /* mov.b */, MSP430::MOV8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 195 /* mov.b */, MSP430::MOV8ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 195 /* mov.b */, MSP430::MOV8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 195 /* mov.b */, MSP430::MOV8rn, Convert__Reg1_1__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 195 /* mov.b */, MSP430::MOV8rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 195 /* mov.b */, MSP430::MOV8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 195 /* mov.b */, MSP430::MOV8rp, Convert__Reg1_1__PostIndReg1_0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 201 /* nop */, MSP430::MOV16rc, Convert__regCG__imm_95_0, 0, { }, }, + { 205 /* pop */, MSP430::POP16r, Convert__Reg1_0, 0, { MCK_GR16 }, }, + { 209 /* push */, MSP430::PUSH16r, Convert__Reg1_0, 0, { MCK_GR16 }, }, + { 209 /* push */, MSP430::PUSH16c, Convert__CGImm1_0, 0, { MCK_CGImm }, }, + { 209 /* push */, MSP430::PUSH16i, Convert__Imm1_0, 0, { MCK_Imm }, }, + { 214 /* push.b */, MSP430::PUSH8r, Convert__Reg1_0, 0, { MCK_GR8 }, }, + { 221 /* ret */, MSP430::RET, Convert_NoOperands, 0, { }, }, + { 225 /* reti */, MSP430::RETI, Convert_NoOperands, 0, { }, }, + { 230 /* rla */, MSP430::ADD16rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR16 }, }, + { 230 /* rla */, MSP430::ADD16mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, + { 234 /* rla.b */, MSP430::ADD8rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR8 }, }, + { 234 /* rla.b */, MSP430::ADD8mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, + { 240 /* rlc */, MSP430::ADDC16rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR16 }, }, + { 240 /* rlc */, MSP430::ADDC16mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, + { 244 /* rlc.b */, MSP430::ADDC8rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR8 }, }, + { 244 /* rlc.b */, MSP430::ADDC8mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, + { 250 /* rra */, MSP430::RRA16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, + { 254 /* rra.b */, MSP430::RRA8r, Convert__Reg1_0__Tie0, 0, { MCK_GR8 }, }, + { 260 /* rrc */, MSP430::RRC16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, + { 264 /* rrc.b */, MSP430::RRC8r, Convert__Reg1_0__Tie0, 0, { MCK_GR8 }, }, + { 270 /* sbc */, MSP430::SUBC16rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR16 }, }, + { 270 /* sbc */, MSP430::SUBC16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 274 /* sbc.b */, MSP430::SUBC8rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR8 }, }, + { 274 /* sbc.b */, MSP430::SUBC8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 280 /* setc */, MSP430::BIS16rc, Convert__regSR__Tie0__imm_95_1, 0, { }, }, + { 285 /* setn */, MSP430::BIS16rc, Convert__regSR__Tie0__imm_95_4, 0, { }, }, + { 290 /* setz */, MSP430::BIS16rc, Convert__regSR__Tie0__imm_95_2, 0, { }, }, + { 295 /* sub */, MSP430::SUB16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 295 /* sub */, MSP430::SUB16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 295 /* sub */, MSP430::SUB16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 295 /* sub */, MSP430::SUB16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 295 /* sub */, MSP430::SUB16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 295 /* sub */, MSP430::SUB16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 295 /* sub */, MSP430::SUB16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 295 /* sub */, MSP430::SUB16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 295 /* sub */, MSP430::SUB16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 295 /* sub */, MSP430::SUB16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 295 /* sub */, MSP430::SUB16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 295 /* sub */, MSP430::SUB16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 299 /* sub.b */, MSP430::SUB8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 299 /* sub.b */, MSP430::SUB8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 299 /* sub.b */, MSP430::SUB8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 299 /* sub.b */, MSP430::SUB8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 299 /* sub.b */, MSP430::SUB8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 299 /* sub.b */, MSP430::SUB8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 299 /* sub.b */, MSP430::SUB8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 299 /* sub.b */, MSP430::SUB8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 299 /* sub.b */, MSP430::SUB8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 299 /* sub.b */, MSP430::SUB8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 299 /* sub.b */, MSP430::SUB8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 299 /* sub.b */, MSP430::SUB8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 305 /* subc */, MSP430::SUBC16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 305 /* subc */, MSP430::SUBC16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 305 /* subc */, MSP430::SUBC16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 305 /* subc */, MSP430::SUBC16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 305 /* subc */, MSP430::SUBC16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 305 /* subc */, MSP430::SUBC16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 305 /* subc */, MSP430::SUBC16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 305 /* subc */, MSP430::SUBC16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 305 /* subc */, MSP430::SUBC16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 305 /* subc */, MSP430::SUBC16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 305 /* subc */, MSP430::SUBC16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 305 /* subc */, MSP430::SUBC16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 310 /* subc.b */, MSP430::SUBC8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 310 /* subc.b */, MSP430::SUBC8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 310 /* subc.b */, MSP430::SUBC8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 310 /* subc.b */, MSP430::SUBC8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 310 /* subc.b */, MSP430::SUBC8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 310 /* subc.b */, MSP430::SUBC8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 310 /* subc.b */, MSP430::SUBC8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 310 /* subc.b */, MSP430::SUBC8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 310 /* subc.b */, MSP430::SUBC8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 310 /* subc.b */, MSP430::SUBC8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 310 /* subc.b */, MSP430::SUBC8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 310 /* subc.b */, MSP430::SUBC8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 317 /* swpb */, MSP430::SWPB16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, + { 322 /* sxt */, MSP430::SEXT16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, + { 326 /* tst */, MSP430::CMP16rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR16 }, }, + { 326 /* tst */, MSP430::CMP16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 330 /* tst.b */, MSP430::CMP8rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR8 }, }, + { 330 /* tst.b */, MSP430::CMP8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 336 /* xor */, MSP430::XOR16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 336 /* xor */, MSP430::XOR16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 336 /* xor */, MSP430::XOR16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 336 /* xor */, MSP430::XOR16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 336 /* xor */, MSP430::XOR16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 336 /* xor */, MSP430::XOR16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 336 /* xor */, MSP430::XOR16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 336 /* xor */, MSP430::XOR16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 336 /* xor */, MSP430::XOR16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 336 /* xor */, MSP430::XOR16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 336 /* xor */, MSP430::XOR16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 336 /* xor */, MSP430::XOR16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 340 /* xor.b */, MSP430::XOR8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 340 /* xor.b */, MSP430::XOR8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 340 /* xor.b */, MSP430::XOR8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 340 /* xor.b */, MSP430::XOR8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 340 /* xor.b */, MSP430::XOR8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 340 /* xor.b */, MSP430::XOR8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 340 /* xor.b */, MSP430::XOR8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 340 /* xor.b */, MSP430::XOR8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 340 /* xor.b */, MSP430::XOR8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 340 /* xor.b */, MSP430::XOR8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 340 /* xor.b */, MSP430::XOR8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 340 /* xor.b */, MSP430::XOR8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, +}; + +bool MSP430AsmParser:: +mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) { + // Find the appropriate table for this asm variant. + const MatchEntry *Start, *End; + switch (VariantID) { + default: llvm_unreachable("invalid variant!"); + case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; + } + // Search the table. + auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); + return MnemonicRange.first != MnemonicRange.second; +} + +unsigned MSP430AsmParser:: +MatchInstructionImpl(const OperandVector &Operands, + MCInst &Inst, uint64_t &ErrorInfo, + bool matchingInlineAsm, unsigned VariantID) { + // Eliminate obvious mismatches. + if (Operands.size() > 3) { + ErrorInfo = 3; + return Match_InvalidOperand; + } + + // Get the current feature set. + uint64_t AvailableFeatures = getAvailableFeatures(); + + // Get the instruction mnemonic, which is the first token. + StringRef Mnemonic = ((MSP430Operand&)*Operands[0]).getToken(); + + // Some state to try to produce better error messages. + bool HadMatchOtherThanFeatures = false; + bool HadMatchOtherThanPredicate = false; + unsigned RetCode = Match_InvalidOperand; + uint64_t MissingFeatures = ~0ULL; + // Set ErrorInfo to the operand that mismatches if it is + // wrong for all instances of the instruction. + ErrorInfo = ~0ULL; + // Find the appropriate table for this asm variant. + const MatchEntry *Start, *End; + switch (VariantID) { + default: llvm_unreachable("invalid variant!"); + case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; + } + // Search the table. + auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); + + // Return a more specific error code if no mnemonics match. + if (MnemonicRange.first == MnemonicRange.second) + return Match_MnemonicFail; + + for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; + it != ie; ++it) { + // equal_range guarantees that instruction mnemonic matches. + assert(Mnemonic == it->getMnemonic()); + bool OperandsValid = true; + for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 2; ++FormalIdx) { + auto Formal = static_cast(it->Classes[FormalIdx]); + if (ActualIdx >= Operands.size()) { + OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass); + if (!OperandsValid) ErrorInfo = ActualIdx; + break; + } + MCParsedAsmOperand &Actual = *Operands[ActualIdx]; + unsigned Diag = validateOperandClass(Actual, Formal); + if (Diag == Match_Success) { + ++ActualIdx; + continue; + } + // If the generic handler indicates an invalid operand + // failure, check for a special case. + if (Diag == Match_InvalidOperand) { + Diag = validateTargetOperandClass(Actual, Formal); + if (Diag == Match_Success) { + ++ActualIdx; + continue; + } + } + // If current formal operand wasn't matched and it is optional + // then try to match next formal operand + if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) { + continue; + } + // If this operand is broken for all of the instances of this + // mnemonic, keep track of it so we can report loc info. + // If we already had a match that only failed due to a + // target predicate, that diagnostic is preferred. + if (!HadMatchOtherThanPredicate && + (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) { + ErrorInfo = ActualIdx; + // InvalidOperand is the default. Prefer specificity. + if (Diag != Match_InvalidOperand) + RetCode = Diag; + } + // Otherwise, just reject this instance of the mnemonic. + OperandsValid = false; + break; + } + + if (!OperandsValid) continue; + if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) { + HadMatchOtherThanFeatures = true; + uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures; + if (countPopulation(NewMissingFeatures) <= + countPopulation(MissingFeatures)) + MissingFeatures = NewMissingFeatures; + continue; + } + + Inst.clear(); + + if (matchingInlineAsm) { + Inst.setOpcode(it->Opcode); + convertToMapAndConstraints(it->ConvertFn, Operands); + return Match_Success; + } + + // We have selected a definite instruction, convert the parsed + // operands into the appropriate MCInst. + convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands); + + // We have a potential match. Check the target predicate to + // handle any context sensitive constraints. + unsigned MatchResult; + if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { + Inst.clear(); + RetCode = MatchResult; + HadMatchOtherThanPredicate = true; + continue; + } + + return Match_Success; + } + + // Okay, we had no match. Try to return a useful error code. + if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures) + return RetCode; + + // Missing feature matches return which features were missing + ErrorInfo = MissingFeatures; + return Match_MissingFeature; +} + +#endif // GET_MATCHER_IMPLEMENTATION + diff --git a/llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc b/llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc new file mode 100644 index 00000000..aa8733a6 --- /dev/null +++ b/llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc @@ -0,0 +1,1147 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Target Instruction Enum Values and Descriptors *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM +namespace llvm_ks { + +namespace MSP430 { + enum { + PHI = 0, + INLINEASM = 1, + CFI_INSTRUCTION = 2, + EH_LABEL = 3, + GC_LABEL = 4, + KILL = 5, + EXTRACT_SUBREG = 6, + INSERT_SUBREG = 7, + IMPLICIT_DEF = 8, + SUBREG_TO_REG = 9, + COPY_TO_REGCLASS = 10, + DBG_VALUE = 11, + REG_SEQUENCE = 12, + COPY = 13, + BUNDLE = 14, + LIFETIME_START = 15, + LIFETIME_END = 16, + STACKMAP = 17, + PATCHPOINT = 18, + LOAD_STACK_GUARD = 19, + STATEPOINT = 20, + LOCAL_ESCAPE = 21, + FAULTING_LOAD_OP = 22, + PATCHABLE_OP = 23, + PATCHABLE_FUNCTION_ENTER = 24, + PATCHABLE_RET = 25, + G_ADD = 26, + G_OR = 27, + G_BR = 28, + ADD16mc = 29, + ADD16mi = 30, + ADD16mm = 31, + ADD16mn = 32, + ADD16mp = 33, + ADD16mr = 34, + ADD16rc = 35, + ADD16ri = 36, + ADD16rm = 37, + ADD16rn = 38, + ADD16rp = 39, + ADD16rr = 40, + ADD8mc = 41, + ADD8mi = 42, + ADD8mm = 43, + ADD8mn = 44, + ADD8mp = 45, + ADD8mr = 46, + ADD8rc = 47, + ADD8ri = 48, + ADD8rm = 49, + ADD8rn = 50, + ADD8rp = 51, + ADD8rr = 52, + ADDC16mc = 53, + ADDC16mi = 54, + ADDC16mm = 55, + ADDC16mn = 56, + ADDC16mp = 57, + ADDC16mr = 58, + ADDC16rc = 59, + ADDC16ri = 60, + ADDC16rm = 61, + ADDC16rn = 62, + ADDC16rp = 63, + ADDC16rr = 64, + ADDC8mc = 65, + ADDC8mi = 66, + ADDC8mm = 67, + ADDC8mn = 68, + ADDC8mp = 69, + ADDC8mr = 70, + ADDC8rc = 71, + ADDC8ri = 72, + ADDC8rm = 73, + ADDC8rn = 74, + ADDC8rp = 75, + ADDC8rr = 76, + ADDframe = 77, + ADJCALLSTACKDOWN = 78, + ADJCALLSTACKUP = 79, + AND16mc = 80, + AND16mi = 81, + AND16mm = 82, + AND16mn = 83, + AND16mp = 84, + AND16mr = 85, + AND16rc = 86, + AND16ri = 87, + AND16rm = 88, + AND16rn = 89, + AND16rp = 90, + AND16rr = 91, + AND8mc = 92, + AND8mi = 93, + AND8mm = 94, + AND8mn = 95, + AND8mp = 96, + AND8mr = 97, + AND8rc = 98, + AND8ri = 99, + AND8rm = 100, + AND8rn = 101, + AND8rp = 102, + AND8rr = 103, + BIC16mm = 104, + BIC16mr = 105, + BIC16rm = 106, + BIC16rr = 107, + BIC8mm = 108, + BIC8mr = 109, + BIC8rm = 110, + BIC8rr = 111, + BIS16mc = 112, + BIS16mi = 113, + BIS16mm = 114, + BIS16mn = 115, + BIS16mp = 116, + BIS16mr = 117, + BIS16rc = 118, + BIS16ri = 119, + BIS16rm = 120, + BIS16rn = 121, + BIS16rp = 122, + BIS16rr = 123, + BIS8mc = 124, + BIS8mi = 125, + BIS8mm = 126, + BIS8mn = 127, + BIS8mp = 128, + BIS8mr = 129, + BIS8rc = 130, + BIS8ri = 131, + BIS8rm = 132, + BIS8rn = 133, + BIS8rp = 134, + BIS8rr = 135, + BIT16mc = 136, + BIT16mi = 137, + BIT16mm = 138, + BIT16mr = 139, + BIT16rc = 140, + BIT16ri = 141, + BIT16rm = 142, + BIT16rr = 143, + BIT8mc = 144, + BIT8mi = 145, + BIT8mm = 146, + BIT8mr = 147, + BIT8rc = 148, + BIT8ri = 149, + BIT8rm = 150, + BIT8rr = 151, + Bi = 152, + Bm = 153, + Br = 154, + CALLi = 155, + CALLm = 156, + CALLr = 157, + CMP16mc = 158, + CMP16mi = 159, + CMP16mr = 160, + CMP16rc = 161, + CMP16ri = 162, + CMP16rm = 163, + CMP16rr = 164, + CMP8mc = 165, + CMP8mi = 166, + CMP8mr = 167, + CMP8rc = 168, + CMP8ri = 169, + CMP8rm = 170, + CMP8rr = 171, + DADD16mc = 172, + DADD16mi = 173, + DADD16mm = 174, + DADD16mn = 175, + DADD16mp = 176, + DADD16mr = 177, + DADD16rc = 178, + DADD16ri = 179, + DADD16rm = 180, + DADD16rn = 181, + DADD16rp = 182, + DADD16rr = 183, + DADD8mc = 184, + DADD8mi = 185, + DADD8mm = 186, + DADD8mn = 187, + DADD8mp = 188, + DADD8mr = 189, + DADD8rc = 190, + DADD8ri = 191, + DADD8rm = 192, + DADD8rn = 193, + DADD8rp = 194, + DADD8rr = 195, + JCC = 196, + JMP = 197, + MOV16mc = 198, + MOV16mi = 199, + MOV16mm = 200, + MOV16mr = 201, + MOV16rc = 202, + MOV16ri = 203, + MOV16rm = 204, + MOV16rn = 205, + MOV16rp = 206, + MOV16rr = 207, + MOV8mc = 208, + MOV8mi = 209, + MOV8mm = 210, + MOV8mr = 211, + MOV8rc = 212, + MOV8ri = 213, + MOV8rm = 214, + MOV8rn = 215, + MOV8rp = 216, + MOV8rr = 217, + MOVZX16rm8 = 218, + MOVZX16rr8 = 219, + POP16r = 220, + PUSH16c = 221, + PUSH16i = 222, + PUSH16r = 223, + PUSH8r = 224, + RET = 225, + RETI = 226, + RRA16r = 227, + RRA8r = 228, + RRC16r = 229, + RRC8r = 230, + Rrcl16 = 231, + Rrcl8 = 232, + SEXT16r = 233, + SUB16mc = 234, + SUB16mi = 235, + SUB16mm = 236, + SUB16mn = 237, + SUB16mp = 238, + SUB16mr = 239, + SUB16rc = 240, + SUB16ri = 241, + SUB16rm = 242, + SUB16rn = 243, + SUB16rp = 244, + SUB16rr = 245, + SUB8mc = 246, + SUB8mi = 247, + SUB8mm = 248, + SUB8mn = 249, + SUB8mp = 250, + SUB8mr = 251, + SUB8rc = 252, + SUB8ri = 253, + SUB8rm = 254, + SUB8rn = 255, + SUB8rp = 256, + SUB8rr = 257, + SUBC16mc = 258, + SUBC16mi = 259, + SUBC16mm = 260, + SUBC16mn = 261, + SUBC16mp = 262, + SUBC16mr = 263, + SUBC16rc = 264, + SUBC16ri = 265, + SUBC16rm = 266, + SUBC16rn = 267, + SUBC16rp = 268, + SUBC16rr = 269, + SUBC8mc = 270, + SUBC8mi = 271, + SUBC8mm = 272, + SUBC8mn = 273, + SUBC8mp = 274, + SUBC8mr = 275, + SUBC8rc = 276, + SUBC8ri = 277, + SUBC8rm = 278, + SUBC8rn = 279, + SUBC8rp = 280, + SUBC8rr = 281, + SWPB16r = 282, + Select16 = 283, + Select8 = 284, + Shl16 = 285, + Shl8 = 286, + Sra16 = 287, + Sra8 = 288, + Srl16 = 289, + Srl8 = 290, + XOR16mc = 291, + XOR16mi = 292, + XOR16mm = 293, + XOR16mn = 294, + XOR16mp = 295, + XOR16mr = 296, + XOR16rc = 297, + XOR16ri = 298, + XOR16rm = 299, + XOR16rn = 300, + XOR16rp = 301, + XOR16rr = 302, + XOR8mc = 303, + XOR8mi = 304, + XOR8mm = 305, + XOR8mn = 306, + XOR8mp = 307, + XOR8mr = 308, + XOR8rc = 309, + XOR8ri = 310, + XOR8rm = 311, + XOR8rn = 312, + XOR8rp = 313, + XOR8rr = 314, + ZEXT16r = 315, + INSTRUCTION_LIST_END = 316 + }; + +namespace Sched { + enum { + NoInstrModel = 0, + SCHED_LIST_END = 1 + }; +} // end Sched namespace +} // end MSP430 namespace +} // end llvm namespace +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC +namespace llvm_ks { + +static const MCPhysReg ImplicitList1[] = { MSP430::SR, 0 }; +static const MCPhysReg ImplicitList2[] = { MSP430::SP, 0 }; +static const MCPhysReg ImplicitList3[] = { MSP430::SP, MSP430::SR, 0 }; +static const MCPhysReg ImplicitList4[] = { MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR, 0 }; + +static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 316); +} + +} // end llvm namespace +#endif // GET_INSTRINFO_MC_DESC + +#ifdef GET_INSTRINFO_HEADER +#undef GET_INSTRINFO_HEADER +namespace llvm_ks { +struct MSP430GenInstrInfo : public TargetInstrInfo { + explicit MSP430GenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1); + ~MSP430GenInstrInfo() override {} +}; +} // end llvm namespace +#endif // GET_INSTRINFO_HEADER + +#ifdef GET_INSTRINFO_CTOR_DTOR +#undef GET_INSTRINFO_CTOR_DTOR +namespace llvm_ks { +extern const MCInstrDesc MSP430Insts[]; +extern const unsigned MSP430InstrNameIndices[]; +extern const char MSP430InstrNameData[]; +MSP430GenInstrInfo::MSP430GenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode) + : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { + InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 316); +} +} // end llvm namespace +#endif // GET_INSTRINFO_CTOR_DTOR + +#ifdef GET_INSTRINFO_OPERAND_ENUM +#undef GET_INSTRINFO_OPERAND_ENUM +namespace llvm_ks { +namespace MSP430 { +namespace OpName { +enum { +OPERAND_LAST +}; +} // end namespace OpName +} // end namespace MSP430 +} // end namespace llvm +#endif //GET_INSTRINFO_OPERAND_ENUM + +#ifdef GET_INSTRINFO_NAMED_OPS +#undef GET_INSTRINFO_NAMED_OPS +namespace llvm_ks { +namespace MSP430 { +LLVM_READONLY +int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { + return -1; +} +} // end namespace MSP430 +} // end namespace llvm +#endif //GET_INSTRINFO_NAMED_OPS + +#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM +#undef GET_INSTRINFO_OPERAND_TYPES_ENUM +namespace llvm_ks { +namespace MSP430 { +namespace OpTypes { +enum OperandType { + cc = 0, + cg16imm = 1, + cg8imm = 2, + f32imm = 3, + f64imm = 4, + i16imm = 5, + i1imm = 6, + i32imm = 7, + i64imm = 8, + i8imm = 9, + indreg = 10, + jmptarget = 11, + memdst = 12, + memsrc = 13, + postreg = 14, + OPERAND_TYPE_LIST_END +}; +} // end namespace OpTypes +} // end namespace MSP430 +} // end namespace llvm +#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM + diff --git a/llvm/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc b/llvm/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc new file mode 100644 index 00000000..a9b093c3 --- /dev/null +++ b/llvm/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc @@ -0,0 +1,838 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Machine Code Emitter *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + static const uint64_t InstBits[] = { + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(0), + UINT64_C(20608), // ADD16mc + UINT64_C(20656), // ADD16mi + UINT64_C(20624), // ADD16mm + UINT64_C(20640), // ADD16mn + UINT64_C(20656), // ADD16mp + UINT64_C(20608), // ADD16mr + UINT64_C(20480), // ADD16rc + UINT64_C(20528), // ADD16ri + UINT64_C(20496), // ADD16rm + UINT64_C(20512), // ADD16rn + UINT64_C(20528), // ADD16rp + UINT64_C(20480), // ADD16rr + UINT64_C(20672), // ADD8mc + UINT64_C(20720), // ADD8mi + UINT64_C(20688), // ADD8mm + UINT64_C(20704), // ADD8mn + UINT64_C(20720), // ADD8mp + UINT64_C(20672), // ADD8mr + UINT64_C(20544), // ADD8rc + UINT64_C(20592), // ADD8ri + UINT64_C(20560), // ADD8rm + UINT64_C(20576), // ADD8rn + UINT64_C(20592), // ADD8rp + UINT64_C(20544), // ADD8rr + UINT64_C(24704), // ADDC16mc + UINT64_C(24752), // ADDC16mi + UINT64_C(24720), // ADDC16mm + UINT64_C(24736), // ADDC16mn + UINT64_C(24752), // ADDC16mp + UINT64_C(24704), // ADDC16mr + UINT64_C(24576), // ADDC16rc + UINT64_C(24624), // ADDC16ri + UINT64_C(24592), // ADDC16rm + UINT64_C(24608), // ADDC16rn + UINT64_C(24624), // ADDC16rp + UINT64_C(24576), // ADDC16rr + UINT64_C(24768), // ADDC8mc + UINT64_C(24816), // ADDC8mi + UINT64_C(24784), // ADDC8mm + UINT64_C(24800), // ADDC8mn + UINT64_C(24816), // ADDC8mp + UINT64_C(24768), // ADDC8mr + UINT64_C(24640), // ADDC8rc + UINT64_C(24688), // ADDC8ri + UINT64_C(24656), // ADDC8rm + UINT64_C(24672), // ADDC8rn + UINT64_C(24688), // ADDC8rp + UINT64_C(24640), // ADDC8rr + UINT64_C(0), // ADDframe + UINT64_C(0), // ADJCALLSTACKDOWN + UINT64_C(0), // ADJCALLSTACKUP + UINT64_C(61568), // AND16mc + UINT64_C(61616), // AND16mi + UINT64_C(61584), // AND16mm + UINT64_C(61600), // AND16mn + UINT64_C(61616), // AND16mp + UINT64_C(61568), // AND16mr + UINT64_C(61440), // AND16rc + UINT64_C(61488), // AND16ri + UINT64_C(61456), // AND16rm + UINT64_C(61472), // AND16rn + UINT64_C(61488), // AND16rp + UINT64_C(61440), // AND16rr + UINT64_C(61632), // AND8mc + UINT64_C(61680), // AND8mi + UINT64_C(61648), // AND8mm + UINT64_C(61664), // AND8mn + UINT64_C(61680), // AND8mp + UINT64_C(61632), // AND8mr + UINT64_C(61504), // AND8rc + UINT64_C(61552), // AND8ri + UINT64_C(61520), // AND8rm + UINT64_C(61536), // AND8rn + UINT64_C(61552), // AND8rp + UINT64_C(61504), // AND8rr + UINT64_C(144), // BIC16mm + UINT64_C(128), // BIC16mr + UINT64_C(16), // BIC16rm + UINT64_C(0), // BIC16rr + UINT64_C(208), // BIC8mm + UINT64_C(192), // BIC8mr + UINT64_C(80), // BIC8rm + UINT64_C(64), // BIC8rr + UINT64_C(53376), // BIS16mc + UINT64_C(53424), // BIS16mi + UINT64_C(53392), // BIS16mm + UINT64_C(53408), // BIS16mn + UINT64_C(53424), // BIS16mp + UINT64_C(53376), // BIS16mr + UINT64_C(53248), // BIS16rc + UINT64_C(53296), // BIS16ri + UINT64_C(53264), // BIS16rm + UINT64_C(53280), // BIS16rn + UINT64_C(53296), // BIS16rp + UINT64_C(53248), // BIS16rr + UINT64_C(53440), // BIS8mc + UINT64_C(53488), // BIS8mi + UINT64_C(53456), // BIS8mm + UINT64_C(53472), // BIS8mn + UINT64_C(53488), // BIS8mp + UINT64_C(53440), // BIS8mr + UINT64_C(53312), // BIS8rc + UINT64_C(53360), // BIS8ri + UINT64_C(53328), // BIS8rm + UINT64_C(53344), // BIS8rn + UINT64_C(53360), // BIS8rp + UINT64_C(53312), // BIS8rr + UINT64_C(45184), // BIT16mc + UINT64_C(45232), // BIT16mi + UINT64_C(45200), // BIT16mm + UINT64_C(45184), // BIT16mr + UINT64_C(45056), // BIT16rc + UINT64_C(45104), // BIT16ri + UINT64_C(45072), // BIT16rm + UINT64_C(45056), // BIT16rr + UINT64_C(45248), // BIT8mc + UINT64_C(45296), // BIT8mi + UINT64_C(45264), // BIT8mm + UINT64_C(45248), // BIT8mr + UINT64_C(45120), // BIT8rc + UINT64_C(45168), // BIT8ri + UINT64_C(45136), // BIT8rm + UINT64_C(45120), // BIT8rr + UINT64_C(16432), // Bi + UINT64_C(16400), // Bm + UINT64_C(16384), // Br + UINT64_C(4784), // CALLi + UINT64_C(4752), // CALLm + UINT64_C(4736), // CALLr + UINT64_C(36992), // CMP16mc + UINT64_C(37040), // CMP16mi + UINT64_C(36992), // CMP16mr + UINT64_C(36864), // CMP16rc + UINT64_C(36912), // CMP16ri + UINT64_C(36880), // CMP16rm + UINT64_C(36864), // CMP16rr + UINT64_C(37056), // CMP8mc + UINT64_C(37104), // CMP8mi + UINT64_C(37056), // CMP8mr + UINT64_C(36928), // CMP8rc + UINT64_C(36976), // CMP8ri + UINT64_C(36944), // CMP8rm + UINT64_C(36928), // CMP8rr + UINT64_C(41088), // DADD16mc + UINT64_C(41136), // DADD16mi + UINT64_C(41104), // DADD16mm + UINT64_C(41120), // DADD16mn + UINT64_C(41136), // DADD16mp + UINT64_C(41088), // DADD16mr + UINT64_C(40960), // DADD16rc + UINT64_C(41008), // DADD16ri + UINT64_C(40976), // DADD16rm + UINT64_C(40992), // DADD16rn + UINT64_C(41008), // DADD16rp + UINT64_C(40960), // DADD16rr + UINT64_C(41152), // DADD8mc + UINT64_C(41200), // DADD8mi + UINT64_C(41168), // DADD8mm + UINT64_C(41184), // DADD8mn + UINT64_C(41200), // DADD8mp + UINT64_C(41152), // DADD8mr + UINT64_C(41024), // DADD8rc + UINT64_C(41072), // DADD8ri + UINT64_C(41040), // DADD8rm + UINT64_C(41056), // DADD8rn + UINT64_C(41072), // DADD8rp + UINT64_C(41024), // DADD8rr + UINT64_C(8192), // JCC + UINT64_C(15360), // JMP + UINT64_C(16512), // MOV16mc + UINT64_C(16560), // MOV16mi + UINT64_C(16528), // MOV16mm + UINT64_C(16512), // MOV16mr + UINT64_C(16384), // MOV16rc + UINT64_C(16432), // MOV16ri + UINT64_C(16400), // MOV16rm + UINT64_C(16416), // MOV16rn + UINT64_C(16432), // MOV16rp + UINT64_C(16384), // MOV16rr + UINT64_C(16576), // MOV8mc + UINT64_C(16624), // MOV8mi + UINT64_C(16592), // MOV8mm + UINT64_C(16576), // MOV8mr + UINT64_C(16448), // MOV8rc + UINT64_C(16496), // MOV8ri + UINT64_C(16464), // MOV8rm + UINT64_C(16480), // MOV8rn + UINT64_C(16496), // MOV8rp + UINT64_C(16448), // MOV8rr + UINT64_C(16464), // MOVZX16rm8 + UINT64_C(16448), // MOVZX16rr8 + UINT64_C(16688), // POP16r + UINT64_C(4608), // PUSH16c + UINT64_C(4656), // PUSH16i + UINT64_C(4608), // PUSH16r + UINT64_C(4672), // PUSH8r + UINT64_C(16688), // RET + UINT64_C(4864), // RETI + UINT64_C(4352), // RRA16r + UINT64_C(4416), // RRA8r + UINT64_C(4096), // RRC16r + UINT64_C(4160), // RRC8r + UINT64_C(0), // Rrcl16 + UINT64_C(0), // Rrcl8 + UINT64_C(4480), // SEXT16r + UINT64_C(32896), // SUB16mc + UINT64_C(32944), // SUB16mi + UINT64_C(32912), // SUB16mm + UINT64_C(32928), // SUB16mn + UINT64_C(32944), // SUB16mp + UINT64_C(32896), // SUB16mr + UINT64_C(32768), // SUB16rc + UINT64_C(32816), // SUB16ri + UINT64_C(32784), // SUB16rm + UINT64_C(32800), // SUB16rn + UINT64_C(32816), // SUB16rp + UINT64_C(32768), // SUB16rr + UINT64_C(32960), // SUB8mc + UINT64_C(33008), // SUB8mi + UINT64_C(32976), // SUB8mm + UINT64_C(32992), // SUB8mn + UINT64_C(33008), // SUB8mp + UINT64_C(32960), // SUB8mr + UINT64_C(32832), // SUB8rc + UINT64_C(32880), // SUB8ri + UINT64_C(32848), // SUB8rm + UINT64_C(32864), // SUB8rn + UINT64_C(32880), // SUB8rp + UINT64_C(32832), // SUB8rr + UINT64_C(28800), // SUBC16mc + UINT64_C(28848), // SUBC16mi + UINT64_C(28816), // SUBC16mm + UINT64_C(28832), // SUBC16mn + UINT64_C(28848), // SUBC16mp + UINT64_C(28800), // SUBC16mr + UINT64_C(28672), // SUBC16rc + UINT64_C(28720), // SUBC16ri + UINT64_C(28688), // SUBC16rm + UINT64_C(28704), // SUBC16rn + UINT64_C(28720), // SUBC16rp + UINT64_C(28672), // SUBC16rr + UINT64_C(28864), // SUBC8mc + UINT64_C(28912), // SUBC8mi + UINT64_C(28880), // SUBC8mm + UINT64_C(28896), // SUBC8mn + UINT64_C(28912), // SUBC8mp + UINT64_C(28864), // SUBC8mr + UINT64_C(28736), // SUBC8rc + UINT64_C(28784), // SUBC8ri + UINT64_C(28752), // SUBC8rm + UINT64_C(28768), // SUBC8rn + UINT64_C(28784), // SUBC8rp + UINT64_C(28736), // SUBC8rr + UINT64_C(4224), // SWPB16r + UINT64_C(0), // Select16 + UINT64_C(0), // Select8 + UINT64_C(0), // Shl16 + UINT64_C(0), // Shl8 + UINT64_C(0), // Sra16 + UINT64_C(0), // Sra8 + UINT64_C(0), // Srl16 + UINT64_C(0), // Srl8 + UINT64_C(57472), // XOR16mc + UINT64_C(57520), // XOR16mi + UINT64_C(57488), // XOR16mm + UINT64_C(57504), // XOR16mn + UINT64_C(57520), // XOR16mp + UINT64_C(57472), // XOR16mr + UINT64_C(57344), // XOR16rc + UINT64_C(57392), // XOR16ri + UINT64_C(57360), // XOR16rm + UINT64_C(57376), // XOR16rn + UINT64_C(57392), // XOR16rp + UINT64_C(57344), // XOR16rr + UINT64_C(57536), // XOR8mc + UINT64_C(57584), // XOR8mi + UINT64_C(57552), // XOR8mm + UINT64_C(57568), // XOR8mn + UINT64_C(57584), // XOR8mp + UINT64_C(57536), // XOR8mr + UINT64_C(57408), // XOR8rc + UINT64_C(57456), // XOR8ri + UINT64_C(57424), // XOR8rm + UINT64_C(57440), // XOR8rn + UINT64_C(57456), // XOR8rp + UINT64_C(57408), // XOR8rr + UINT64_C(16448), // ZEXT16r + UINT64_C(0) + }; + const unsigned opcode = MI.getOpcode(); + uint64_t Value = InstBits[opcode]; + uint64_t op = 0; + (void)op; // suppress warning + switch (opcode) { + case MSP430::ADDframe: + case MSP430::ADJCALLSTACKDOWN: + case MSP430::ADJCALLSTACKUP: + case MSP430::RET: + case MSP430::RETI: + case MSP430::Rrcl16: + case MSP430::Rrcl8: + case MSP430::Select16: + case MSP430::Select8: + case MSP430::Shl16: + case MSP430::Shl8: + case MSP430::Sra16: + case MSP430::Sra8: + case MSP430::Srl16: + case MSP430::Srl8: { + break; + } + case MSP430::JCC: { + // op: cond + op = getCCOpValue(MI, 1, Fixups, STI); + Value |= (op & UINT64_C(7)) << 10; + // op: dst + op = getPCRelImmOpValue(MI, 0, Fixups, STI); + Value |= op & UINT64_C(1023); + break; + } + case MSP430::JMP: { + // op: dst + op = getPCRelImmOpValue(MI, 0, Fixups, STI); + Value |= op & UINT64_C(1023); + break; + } + case MSP430::PUSH16c: { + // op: imm + op = getCGImmOpValue(MI, 0, Fixups, STI); + Value |= op & UINT64_C(63); + break; + } + case MSP430::BIT16rc: + case MSP430::BIT8rc: + case MSP430::CMP16rc: + case MSP430::CMP8rc: + case MSP430::MOV16rc: + case MSP430::MOV8rc: { + // op: imm + op = getCGImmOpValue(MI, 1, Fixups, STI); + Value |= (op & UINT64_C(15)) << 8; + Value |= op & UINT64_C(48); + // op: rd + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= op & UINT64_C(15); + break; + } + case MSP430::ADD16mc: + case MSP430::ADD8mc: + case MSP430::ADDC16mc: + case MSP430::ADDC8mc: + case MSP430::AND16mc: + case MSP430::AND8mc: + case MSP430::BIS16mc: + case MSP430::BIS8mc: + case MSP430::BIT8mc: + case MSP430::CMP16mc: + case MSP430::CMP8mc: + case MSP430::DADD16mc: + case MSP430::DADD8mc: + case MSP430::MOV16mc: + case MSP430::MOV8mc: + case MSP430::SUB16mc: + case MSP430::SUB8mc: + case MSP430::SUBC16mc: + case MSP430::SUBC8mc: + case MSP430::XOR16mc: + case MSP430::XOR8mc: { + // op: imm + op = getCGImmOpValue(MI, 2, Fixups, STI); + Value |= (op & UINT64_C(15)) << 8; + Value |= op & UINT64_C(48); + // op: dst + op = getMemOpValue(MI, 0, Fixups, STI); + Value |= (op & UINT64_C(1048560)) << 12; + Value |= op & UINT64_C(15); + break; + } + case MSP430::ADD16rc: + case MSP430::ADD8rc: + case MSP430::ADDC16rc: + case MSP430::ADDC8rc: + case MSP430::AND16rc: + case MSP430::AND8rc: + case MSP430::BIS16rc: + case MSP430::BIS8rc: + case MSP430::DADD16rc: + case MSP430::DADD8rc: + case MSP430::SUB16rc: + case MSP430::SUB8rc: + case MSP430::SUBC16rc: + case MSP430::SUBC8rc: + case MSP430::XOR16rc: + case MSP430::XOR8rc: { + // op: imm + op = getCGImmOpValue(MI, 2, Fixups, STI); + Value |= (op & UINT64_C(15)) << 8; + Value |= op & UINT64_C(48); + // op: rd + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= op & UINT64_C(15); + break; + } + case MSP430::Bi: + case MSP430::CALLi: + case MSP430::PUSH16i: { + // op: imm + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= (op & UINT64_C(65535)) << 16; + break; + } + case MSP430::BIT16mc: { + // op: imm + op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); + Value |= (op & UINT64_C(15)) << 8; + Value |= op & UINT64_C(48); + // op: dst + op = getMemOpValue(MI, 0, Fixups, STI); + Value |= (op & UINT64_C(1048560)) << 12; + Value |= op & UINT64_C(15); + break; + } + case MSP430::ADD16mi: + case MSP430::ADD8mi: + case MSP430::ADDC16mi: + case MSP430::ADDC8mi: + case MSP430::AND16mi: + case MSP430::AND8mi: + case MSP430::BIS16mi: + case MSP430::BIS8mi: + case MSP430::BIT16mi: + case MSP430::BIT8mi: + case MSP430::CMP16mi: + case MSP430::CMP8mi: + case MSP430::DADD16mi: + case MSP430::DADD8mi: + case MSP430::MOV16mi: + case MSP430::MOV8mi: + case MSP430::SUB16mi: + case MSP430::SUB8mi: + case MSP430::SUBC16mi: + case MSP430::SUBC8mi: + case MSP430::XOR16mi: + case MSP430::XOR8mi: { + // op: imm + op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); + Value |= (op & UINT64_C(65535)) << 16; + // op: dst + op = getMemOpValue(MI, 0, Fixups, STI); + Value |= (op & UINT64_C(1048560)) << 28; + Value |= op & UINT64_C(15); + break; + } + case MSP430::POP16r: { + // op: rd + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= op & UINT64_C(15); + break; + } + case MSP430::BIT16ri: + case MSP430::BIT8ri: + case MSP430::CMP16ri: + case MSP430::CMP8ri: + case MSP430::MOV16ri: + case MSP430::MOV8ri: { + // op: rd + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= op & UINT64_C(15); + // op: imm + op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); + Value |= (op & UINT64_C(65535)) << 16; + break; + } + case MSP430::ADD16ri: + case MSP430::ADD8ri: + case MSP430::ADDC16ri: + case MSP430::ADDC8ri: + case MSP430::AND16ri: + case MSP430::AND8ri: + case MSP430::BIS16ri: + case MSP430::BIS8ri: + case MSP430::DADD16ri: + case MSP430::DADD8ri: + case MSP430::SUB16ri: + case MSP430::SUB8ri: + case MSP430::SUBC16ri: + case MSP430::SUBC8ri: + case MSP430::XOR16ri: + case MSP430::XOR8ri: { + // op: rd + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= op & UINT64_C(15); + // op: imm + op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); + Value |= (op & UINT64_C(65535)) << 16; + break; + } + case MSP430::BIC16rm: + case MSP430::BIC8rm: { + // op: rd + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= op & UINT64_C(15); + // op: src + op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); + Value |= (op & UINT64_C(1048560)) << 12; + Value |= (op & UINT64_C(15)) << 8; + break; + } + case MSP430::BIT16rm: + case MSP430::BIT8rm: + case MSP430::CMP16rm: + case MSP430::CMP8rm: + case MSP430::MOV16rm: + case MSP430::MOV8rm: + case MSP430::MOVZX16rm8: { + // op: rd + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= op & UINT64_C(15); + // op: src + op = getMemOpValue(MI, 1, Fixups, STI); + Value |= (op & UINT64_C(1048560)) << 12; + Value |= (op & UINT64_C(15)) << 8; + break; + } + case MSP430::ADD16rm: + case MSP430::ADD8rm: + case MSP430::ADDC16rm: + case MSP430::ADDC8rm: + case MSP430::AND16rm: + case MSP430::AND8rm: + case MSP430::BIS16rm: + case MSP430::BIS8rm: + case MSP430::DADD16rm: + case MSP430::DADD8rm: + case MSP430::SUB16rm: + case MSP430::SUB8rm: + case MSP430::SUBC16rm: + case MSP430::SUBC8rm: + case MSP430::XOR16rm: + case MSP430::XOR8rm: { + // op: rd + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= op & UINT64_C(15); + // op: src + op = getMemOpValue(MI, 2, Fixups, STI); + Value |= (op & UINT64_C(1048560)) << 12; + Value |= (op & UINT64_C(15)) << 8; + break; + } + case MSP430::Br: { + // op: rs + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= (op & UINT64_C(15)) << 8; + break; + } + case MSP430::BIC16rr: + case MSP430::BIC8rr: { + // op: rs + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= (op & UINT64_C(15)) << 8; + // op: rd + op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); + Value |= op & UINT64_C(15); + break; + } + case MSP430::CALLr: + case MSP430::PUSH16r: + case MSP430::PUSH8r: { + // op: rs + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= op & UINT64_C(15); + break; + } + case MSP430::BIT16rr: + case MSP430::BIT8rr: + case MSP430::CMP16rr: + case MSP430::CMP8rr: + case MSP430::MOV16rn: + case MSP430::MOV16rr: + case MSP430::MOV8rn: + case MSP430::MOV8rr: + case MSP430::MOVZX16rr8: + case MSP430::ZEXT16r: { + // op: rs + op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); + Value |= (op & UINT64_C(15)) << 8; + // op: rd + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= op & UINT64_C(15); + break; + } + case MSP430::RRA16r: + case MSP430::RRA8r: + case MSP430::RRC16r: + case MSP430::RRC8r: + case MSP430::SEXT16r: + case MSP430::SWPB16r: { + // op: rs + op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); + Value |= op & UINT64_C(15); + break; + } + case MSP430::ADD16mn: + case MSP430::ADD16mp: + case MSP430::ADD16mr: + case MSP430::ADD8mn: + case MSP430::ADD8mp: + case MSP430::ADD8mr: + case MSP430::ADDC16mn: + case MSP430::ADDC16mp: + case MSP430::ADDC16mr: + case MSP430::ADDC8mn: + case MSP430::ADDC8mp: + case MSP430::ADDC8mr: + case MSP430::AND16mn: + case MSP430::AND16mp: + case MSP430::AND16mr: + case MSP430::AND8mn: + case MSP430::AND8mp: + case MSP430::AND8mr: + case MSP430::BIS16mn: + case MSP430::BIS16mp: + case MSP430::BIS16mr: + case MSP430::BIS8mn: + case MSP430::BIS8mp: + case MSP430::BIS8mr: + case MSP430::BIT16mr: + case MSP430::BIT8mr: + case MSP430::CMP16mr: + case MSP430::CMP8mr: + case MSP430::DADD16mn: + case MSP430::DADD16mp: + case MSP430::DADD16mr: + case MSP430::DADD8mn: + case MSP430::DADD8mp: + case MSP430::DADD8mr: + case MSP430::MOV16mr: + case MSP430::MOV8mr: + case MSP430::SUB16mn: + case MSP430::SUB16mp: + case MSP430::SUB16mr: + case MSP430::SUB8mn: + case MSP430::SUB8mp: + case MSP430::SUB8mr: + case MSP430::SUBC16mn: + case MSP430::SUBC16mp: + case MSP430::SUBC16mr: + case MSP430::SUBC8mn: + case MSP430::SUBC8mp: + case MSP430::SUBC8mr: + case MSP430::XOR16mn: + case MSP430::XOR16mp: + case MSP430::XOR16mr: + case MSP430::XOR8mn: + case MSP430::XOR8mp: + case MSP430::XOR8mr: { + // op: rs + op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); + Value |= (op & UINT64_C(15)) << 8; + // op: dst + op = getMemOpValue(MI, 0, Fixups, STI); + Value |= (op & UINT64_C(1048560)) << 12; + Value |= op & UINT64_C(15); + break; + } + case MSP430::ADD16rn: + case MSP430::ADD16rr: + case MSP430::ADD8rn: + case MSP430::ADD8rr: + case MSP430::ADDC16rn: + case MSP430::ADDC16rr: + case MSP430::ADDC8rn: + case MSP430::ADDC8rr: + case MSP430::AND16rn: + case MSP430::AND16rr: + case MSP430::AND8rn: + case MSP430::AND8rr: + case MSP430::BIS16rn: + case MSP430::BIS16rr: + case MSP430::BIS8rn: + case MSP430::BIS8rr: + case MSP430::DADD16rn: + case MSP430::DADD16rr: + case MSP430::DADD8rn: + case MSP430::DADD8rr: + case MSP430::MOV16rp: + case MSP430::MOV8rp: + case MSP430::SUB16rn: + case MSP430::SUB16rr: + case MSP430::SUB8rn: + case MSP430::SUB8rr: + case MSP430::SUBC16rn: + case MSP430::SUBC16rr: + case MSP430::SUBC8rn: + case MSP430::SUBC8rr: + case MSP430::XOR16rn: + case MSP430::XOR16rr: + case MSP430::XOR8rn: + case MSP430::XOR8rr: { + // op: rs + op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); + Value |= (op & UINT64_C(15)) << 8; + // op: rd + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= op & UINT64_C(15); + break; + } + case MSP430::ADD16rp: + case MSP430::ADD8rp: + case MSP430::ADDC16rp: + case MSP430::ADDC8rp: + case MSP430::AND16rp: + case MSP430::AND8rp: + case MSP430::BIS16rp: + case MSP430::BIS8rp: + case MSP430::DADD16rp: + case MSP430::DADD8rp: + case MSP430::SUB16rp: + case MSP430::SUB8rp: + case MSP430::SUBC16rp: + case MSP430::SUBC8rp: + case MSP430::XOR16rp: + case MSP430::XOR8rp: { + // op: rs + op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); + Value |= (op & UINT64_C(15)) << 8; + // op: rd + op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); + Value |= op & UINT64_C(15); + break; + } + case MSP430::BIC16mr: + case MSP430::BIC8mr: { + // op: rs + op = getMemOpValue(MI, 0, Fixups, STI); + Value |= (op & UINT64_C(15)) << 8; + // op: dst + op = getMemOpValue(MI, 0, Fixups, STI); + Value |= (op & UINT64_C(1048560)) << 12; + Value |= op & UINT64_C(15); + break; + } + case MSP430::Bm: { + // op: src + op = getMemOpValue(MI, 0, Fixups, STI); + Value |= (op & UINT64_C(1048560)) << 12; + Value |= (op & UINT64_C(15)) << 8; + break; + } + case MSP430::CALLm: { + // op: src + op = getMemOpValue(MI, 0, Fixups, STI); + Value |= (op & UINT64_C(1048560)) << 12; + Value |= op & UINT64_C(15); + break; + } + case MSP430::ADD16mm: + case MSP430::ADD8mm: + case MSP430::ADDC16mm: + case MSP430::ADDC8mm: + case MSP430::AND16mm: + case MSP430::AND8mm: + case MSP430::BIC16mm: + case MSP430::BIC8mm: + case MSP430::BIS16mm: + case MSP430::BIS8mm: + case MSP430::BIT16mm: + case MSP430::BIT8mm: + case MSP430::DADD16mm: + case MSP430::DADD8mm: + case MSP430::MOV16mm: + case MSP430::MOV8mm: + case MSP430::SUB16mm: + case MSP430::SUB8mm: + case MSP430::SUBC16mm: + case MSP430::SUBC8mm: + case MSP430::XOR16mm: + case MSP430::XOR8mm: { + // op: src + op = getMemOpValue(MI, 2, Fixups, STI); + Value |= (op & UINT64_C(1048560)) << 12; + Value |= (op & UINT64_C(15)) << 8; + // op: dst + op = getMemOpValue(MI, 0, Fixups, STI); + Value |= (op & UINT64_C(1048560)) << 28; + Value |= op & UINT64_C(15); + break; + } + default: + std::string msg; + raw_string_ostream Msg(msg); + Msg << "Not supported instr: " << MI; + report_fatal_error(Msg.str()); + } + return Value; +} + diff --git a/llvm/lib/Target/MSP430/MSP430GenRegisterInfo.inc b/llvm/lib/Target/MSP430/MSP430GenRegisterInfo.inc new file mode 100644 index 00000000..33a60e98 --- /dev/null +++ b/llvm/lib/Target/MSP430/MSP430GenRegisterInfo.inc @@ -0,0 +1,631 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Target Register Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +namespace llvm_ks { + +class MCRegisterClass; +extern const MCRegisterClass MSP430MCRegisterClasses[]; + +namespace MSP430 { +enum { + NoRegister, + CG = 1, + CGB = 2, + FP = 3, + FPB = 4, + PC = 5, + PCB = 6, + SP = 7, + SPB = 8, + SR = 9, + SRB = 10, + R5 = 11, + R6 = 12, + R7 = 13, + R8 = 14, + R9 = 15, + R10 = 16, + R11 = 17, + R12 = 18, + R13 = 19, + R14 = 20, + R15 = 21, + R5B = 22, + R6B = 23, + R7B = 24, + R8B = 25, + R9B = 26, + R10B = 27, + R11B = 28, + R12B = 29, + R13B = 30, + R14B = 31, + R15B = 32, + NUM_TARGET_REGS // 33 +}; +} // end namespace MSP430 + +// Register classes + +namespace MSP430 { +enum { + GR8RegClassID = 0, + GR16RegClassID = 1, + + }; +} // end namespace MSP430 + + +// Subregister indices + +namespace MSP430 { +enum { + NoSubRegister, + subreg_8bit, // 1 + NUM_TARGET_SUBREGS +}; +} // end namespace MSP430 + +} // end namespace llvm + +#endif // GET_REGINFO_ENUM + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* MC Register Information *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +namespace llvm_ks { + +extern const MCPhysReg MSP430RegDiffLists[] = { + /* 0 */ 0, 0, + /* 2 */ 1, 0, + /* 4 */ 2, 0, + /* 6 */ 3, 0, + /* 8 */ 4, 0, + /* 10 */ 11, 0, + /* 12 */ 65519, 0, + /* 14 */ 65525, 0, + /* 16 */ 65530, 0, + /* 18 */ 65535, 0, +}; + +extern const unsigned MSP430LaneMaskLists[] = { + /* 0 */ 0x00000000, ~0u, + /* 2 */ 0x00000001, ~0u, +}; + +extern const uint16_t MSP430SubRegIdxLists[] = { + /* 0 */ 1, 0, +}; + +extern const MCRegisterInfo::SubRegCoveredBits MSP430SubRegIdxRanges[] = { + { 65535, 65535 }, + { 0, 8 }, // subreg_8bit +}; + +extern const char MSP430RegStrings[] = { + /* 0 */ 'R', '1', '0', 0, + /* 4 */ 'R', '1', '1', 0, + /* 8 */ 'R', '1', '2', 0, + /* 12 */ 'R', '1', '3', 0, + /* 16 */ 'R', '1', '4', 0, + /* 20 */ 'R', '1', '5', 0, + /* 24 */ 'R', '5', 0, + /* 27 */ 'R', '6', 0, + /* 30 */ 'R', '7', 0, + /* 33 */ 'R', '8', 0, + /* 36 */ 'R', '9', 0, + /* 39 */ 'R', '1', '0', 'B', 0, + /* 44 */ 'R', '1', '1', 'B', 0, + /* 49 */ 'R', '1', '2', 'B', 0, + /* 54 */ 'R', '1', '3', 'B', 0, + /* 59 */ 'R', '1', '4', 'B', 0, + /* 64 */ 'R', '1', '5', 'B', 0, + /* 69 */ 'R', '5', 'B', 0, + /* 73 */ 'R', '6', 'B', 0, + /* 77 */ 'R', '7', 'B', 0, + /* 81 */ 'R', '8', 'B', 0, + /* 85 */ 'R', '9', 'B', 0, + /* 89 */ 'P', 'C', 'B', 0, + /* 93 */ 'C', 'G', 'B', 0, + /* 97 */ 'F', 'P', 'B', 0, + /* 101 */ 'S', 'P', 'B', 0, + /* 105 */ 'S', 'R', 'B', 0, + /* 109 */ 'P', 'C', 0, + /* 112 */ 'C', 'G', 0, + /* 115 */ 'F', 'P', 0, + /* 118 */ 'S', 'P', 0, + /* 121 */ 'S', 'R', 0, +}; + +extern const MCRegisterDesc MSP430RegDesc[] = { // Descriptors + { 3, 0, 0, 0, 0, 0 }, + { 112, 2, 1, 0, 0, 2 }, + { 93, 1, 18, 1, 0, 0 }, + { 115, 2, 1, 0, 32, 2 }, + { 97, 1, 18, 1, 32, 0 }, + { 109, 2, 1, 0, 64, 2 }, + { 89, 1, 18, 1, 64, 0 }, + { 118, 2, 1, 0, 96, 2 }, + { 101, 1, 18, 1, 96, 0 }, + { 121, 2, 1, 0, 128, 2 }, + { 105, 1, 18, 1, 128, 0 }, + { 24, 10, 1, 0, 257, 2 }, + { 27, 10, 1, 0, 257, 2 }, + { 30, 10, 1, 0, 257, 2 }, + { 33, 10, 1, 0, 257, 2 }, + { 36, 10, 1, 0, 257, 2 }, + { 0, 10, 1, 0, 257, 2 }, + { 4, 10, 1, 0, 257, 2 }, + { 8, 10, 1, 0, 257, 2 }, + { 12, 10, 1, 0, 257, 2 }, + { 16, 10, 1, 0, 257, 2 }, + { 20, 10, 1, 0, 257, 2 }, + { 69, 1, 14, 1, 193, 0 }, + { 73, 1, 14, 1, 193, 0 }, + { 77, 1, 14, 1, 193, 0 }, + { 81, 1, 14, 1, 193, 0 }, + { 85, 1, 14, 1, 193, 0 }, + { 39, 1, 14, 1, 193, 0 }, + { 44, 1, 14, 1, 193, 0 }, + { 49, 1, 14, 1, 193, 0 }, + { 54, 1, 14, 1, 193, 0 }, + { 59, 1, 14, 1, 193, 0 }, + { 64, 1, 14, 1, 193, 0 }, +}; + +extern const MCPhysReg MSP430RegUnitRoots[][2] = { + { MSP430::CGB }, + { MSP430::FPB }, + { MSP430::PCB }, + { MSP430::SPB }, + { MSP430::SRB }, + { MSP430::R5B }, + { MSP430::R6B }, + { MSP430::R7B }, + { MSP430::R8B }, + { MSP430::R9B }, + { MSP430::R10B }, + { MSP430::R11B }, + { MSP430::R12B }, + { MSP430::R13B }, + { MSP430::R14B }, + { MSP430::R15B }, +}; + +namespace { // Register classes... + // GR8 Register Class... + const MCPhysReg GR8[] = { + MSP430::R12B, MSP430::R13B, MSP430::R14B, MSP430::R15B, MSP430::R11B, MSP430::R10B, MSP430::R9B, MSP430::R8B, MSP430::R7B, MSP430::R6B, MSP430::R5B, MSP430::FPB, MSP430::PCB, MSP430::SPB, MSP430::SRB, MSP430::CGB, + }; + + // GR8 Bit set. + const uint8_t GR8Bits[] = { + 0x54, 0x05, 0xc0, 0xff, 0x01, + }; + + // GR16 Register Class... + const MCPhysReg GR16[] = { + MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::R11, MSP430::R10, MSP430::R9, MSP430::R8, MSP430::R7, MSP430::R6, MSP430::R5, MSP430::FP, MSP430::PC, MSP430::SP, MSP430::SR, MSP430::CG, + }; + + // GR16 Bit set. + const uint8_t GR16Bits[] = { + 0xaa, 0xfa, 0x3f, + }; + +} // end anonymous namespace + +extern const char MSP430RegClassStrings[] = { + /* 0 */ 'G', 'R', '1', '6', 0, + /* 5 */ 'G', 'R', '8', 0, +}; + +extern const MCRegisterClass MSP430MCRegisterClasses[] = { + { GR8, GR8Bits, 5, 16, sizeof(GR8Bits), MSP430::GR8RegClassID, 1, 1, 1, true }, + { GR16, GR16Bits, 0, 16, sizeof(GR16Bits), MSP430::GR16RegClassID, 2, 2, 1, true }, +}; + +extern const uint16_t MSP430RegEncodingTable[] = { + 0, + 3, + 3, + 4, + 4, + 0, + 0, + 1, + 1, + 2, + 2, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, +}; +static inline void InitMSP430MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { + RI->InitMCRegisterInfo(MSP430RegDesc, 33, RA, PC, MSP430MCRegisterClasses, 2, MSP430RegUnitRoots, 16, MSP430RegDiffLists, MSP430LaneMaskLists, MSP430RegStrings, MSP430RegClassStrings, MSP430SubRegIdxLists, 2, +MSP430SubRegIdxRanges, MSP430RegEncodingTable); + +} + +} // end namespace llvm + +#endif // GET_REGINFO_MC_DESC + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Register Information Header Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_REGINFO_HEADER +#undef GET_REGINFO_HEADER + +#include "llvm/Target/TargetRegisterInfo.h" + +namespace llvm_ks { + +class MSP430FrameLowering; + +struct MSP430GenRegisterInfo : public TargetRegisterInfo { + explicit MSP430GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0); + unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; + LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; + LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; + const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override; + const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; + unsigned getRegUnitWeight(unsigned RegUnit) const override; + unsigned getNumRegPressureSets() const override; + const char *getRegPressureSetName(unsigned Idx) const override; + unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; + const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; + const int *getRegUnitPressureSets(unsigned RegUnit) const override; + ArrayRef getRegMaskNames() const override; + ArrayRef getRegMasks() const override; + /// Devirtualized TargetFrameLowering. + static const MSP430FrameLowering *getFrameLowering( + const MachineFunction &MF); +}; + +namespace MSP430 { // Register classes + extern const TargetRegisterClass GR8RegClass; + extern const TargetRegisterClass GR16RegClass; +} // end namespace MSP430 + +} // end namespace llvm + +#endif // GET_REGINFO_HEADER + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Target Register and Register Classes Information *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_REGINFO_TARGET_DESC +#undef GET_REGINFO_TARGET_DESC + +namespace llvm_ks { + +extern const MCRegisterClass MSP430MCRegisterClasses[]; + +static const MVT::SimpleValueType VTLists[] = { + /* 0 */ MVT::i8, MVT::Other, + /* 2 */ MVT::i16, MVT::Other, +}; + +static const char *const SubRegIndexNameTable[] = { "subreg_8bit", "" }; + + +static const unsigned SubRegIndexLaneMaskTable[] = { + ~0u, + 0x00000001, // subreg_8bit + }; + + + +static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; + +static const uint32_t GR8SubClassMask[] = { + 0x00000001, + 0x00000002, // subreg_8bit +}; + +static const uint32_t GR16SubClassMask[] = { + 0x00000002, +}; + +static const uint16_t SuperRegIdxSeqs[] = { + /* 0 */ 1, 0, +}; + + +namespace MSP430 { // Register class instances + extern const TargetRegisterClass GR8RegClass = { + &MSP430MCRegisterClasses[GR8RegClassID], + VTLists + 0, + GR8SubClassMask, + SuperRegIdxSeqs + 0, + 0x00000001, + 0, + false, /* HasDisjunctSubRegs */ + false, /* CoveredBySubRegs */ + NullRegClasses, + nullptr + }; + + extern const TargetRegisterClass GR16RegClass = { + &MSP430MCRegisterClasses[GR16RegClassID], + VTLists + 2, + GR16SubClassMask, + SuperRegIdxSeqs + 1, + 0x00000001, + 0, + false, /* HasDisjunctSubRegs */ + false, /* CoveredBySubRegs */ + NullRegClasses, + nullptr + }; + +} // end namespace MSP430 + +namespace { + const TargetRegisterClass* const RegisterClasses[] = { + &MSP430::GR8RegClass, + &MSP430::GR16RegClass, + }; +} // end anonymous namespace + +static const TargetRegisterInfoDesc MSP430RegInfoDesc[] = { // Extra Descriptors + { 0, false }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, + { 0, true }, +}; +unsigned MSP430GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { + static const uint8_t Rows[1][1] = { + { 0, }, + }; + + --IdxA; assert(IdxA < 1); + --IdxB; assert(IdxB < 1); + return Rows[0][IdxB]; +} + + struct MaskRolOp { + unsigned Mask; + uint8_t RotateLeft; + }; + static const MaskRolOp LaneMaskComposeSequences[] = { + { 0xFFFFFFFF, 0 }, { 0, 0 } // Sequence 0 + }; + static const MaskRolOp *const CompositeSequences[] = { + &LaneMaskComposeSequences[0] // to subreg_8bit + }; + +LaneBitmask MSP430GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { + --IdxA; assert(IdxA < 1 && "Subregister index out of bounds"); + LaneBitmask Result = 0; + for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops) { + LaneBitmask Masked = LaneMask & Ops->Mask; + Result |= (Masked << Ops->RotateLeft) & 0xFFFFFFFF; + Result |= (Masked >> ((32 - Ops->RotateLeft) & 0x1F)); + } + return Result; +} + +LaneBitmask MSP430GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { + LaneMask &= getSubRegIndexLaneMask(IdxA); + --IdxA; assert(IdxA < 1 && "Subregister index out of bounds"); + LaneBitmask Result = 0; + for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops) { + LaneBitmask Rotated = (LaneMask >> Ops->RotateLeft) | + ((LaneMask << ((32 - Ops->RotateLeft) & 0x1F)) & 0xFFFFFFFF); + Result |= Rotated & Ops->Mask; + } + return Result; +} + +const TargetRegisterClass *MSP430GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { + static const uint8_t Table[2][1] = { + { // GR8 + 0, // subreg_8bit + }, + { // GR16 + 2, // subreg_8bit -> GR16 + }, + }; + assert(RC && "Missing regclass"); + if (!Idx) return RC; + --Idx; + assert(Idx < 1 && "Bad subreg"); + unsigned TV = Table[RC->getID()][Idx]; + return TV ? getRegClass(TV - 1) : nullptr; +} + +/// Get the weight in units of pressure for this register class. +const RegClassWeight &MSP430GenRegisterInfo:: +getRegClassWeight(const TargetRegisterClass *RC) const { + static const RegClassWeight RCWeightTable[] = { + {1, 16}, // GR8 + {1, 16}, // GR16 + }; + return RCWeightTable[RC->getID()]; +} + +/// Get the weight in units of pressure for this register unit. +unsigned MSP430GenRegisterInfo:: +getRegUnitWeight(unsigned RegUnit) const { + assert(RegUnit < 16 && "invalid register unit"); + // All register units have unit weight. + return 1; +} + + +// Get the number of dimensions of register pressure. +unsigned MSP430GenRegisterInfo::getNumRegPressureSets() const { + return 1; +} + +// Get the name of this register unit pressure set. +const char *MSP430GenRegisterInfo:: +getRegPressureSetName(unsigned Idx) const { + static const char *const PressureNameTable[] = { + "GR8", + }; + return PressureNameTable[Idx]; +} + +// Get the register unit pressure limit for this dimension. +// This limit must be adjusted dynamically for reserved registers. +unsigned MSP430GenRegisterInfo:: +getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { + static const uint8_t PressureLimitTable[] = { + 16, // 0: GR8 + }; + return PressureLimitTable[Idx]; +} + +/// Table of pressure sets per register class or unit. +static const int RCSetsTable[] = { + /* 0 */ 0, -1, +}; + +/// Get the dimensions of register pressure impacted by this register class. +/// Returns a -1 terminated array of pressure set IDs +const int* MSP430GenRegisterInfo:: +getRegClassPressureSets(const TargetRegisterClass *RC) const { + static const uint8_t RCSetStartTable[] = { + 0,0,}; + return &RCSetsTable[RCSetStartTable[RC->getID()]]; +} + +/// Get the dimensions of register pressure impacted by this register unit. +/// Returns a -1 terminated array of pressure set IDs +const int* MSP430GenRegisterInfo:: +getRegUnitPressureSets(unsigned RegUnit) const { + assert(RegUnit < 16 && "invalid register unit"); + static const uint8_t RUSetStartTable[] = { + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,}; + return &RCSetsTable[RUSetStartTable[RegUnit]]; +} + +extern const MCRegisterDesc MSP430RegDesc[]; +extern const MCPhysReg MSP430RegDiffLists[]; +extern const unsigned MSP430LaneMaskLists[]; +extern const char MSP430RegStrings[]; +extern const char MSP430RegClassStrings[]; +extern const MCPhysReg MSP430RegUnitRoots[][2]; +extern const uint16_t MSP430SubRegIdxLists[]; +extern const MCRegisterInfo::SubRegCoveredBits MSP430SubRegIdxRanges[]; +extern const uint16_t MSP430RegEncodingTable[]; +MSP430GenRegisterInfo:: +MSP430GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC) + : TargetRegisterInfo(MSP430RegInfoDesc, RegisterClasses, RegisterClasses+2, + SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0xfffffffe) { + InitMCRegisterInfo(MSP430RegDesc, 33, RA, PC, + MSP430MCRegisterClasses, 2, + MSP430RegUnitRoots, + 16, + MSP430RegDiffLists, + MSP430LaneMaskLists, + MSP430RegStrings, + MSP430RegClassStrings, + MSP430SubRegIdxLists, + 2, + MSP430SubRegIdxRanges, + MSP430RegEncodingTable); + +} + + + +ArrayRef MSP430GenRegisterInfo::getRegMasks() const { + return None; +} + +ArrayRef MSP430GenRegisterInfo::getRegMaskNames() const { + return None; +} + +const MSP430FrameLowering * +MSP430GenRegisterInfo::getFrameLowering(const MachineFunction &MF) { + return static_cast( + MF.getSubtarget().getFrameLowering()); +} + +} // end namespace llvm + +#endif // GET_REGINFO_TARGET_DESC + diff --git a/llvm/lib/Target/MSP430/MSP430GenSubtargetInfo.inc b/llvm/lib/Target/MSP430/MSP430GenSubtargetInfo.inc new file mode 100644 index 00000000..fe346f86 --- /dev/null +++ b/llvm/lib/Target/MSP430/MSP430GenSubtargetInfo.inc @@ -0,0 +1,163 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Subtarget Enumeration Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_SUBTARGETINFO_ENUM +#undef GET_SUBTARGETINFO_ENUM + +namespace llvm_ks { +namespace MSP430 { +enum { + FeatureHWMult16 = 0, + FeatureHWMult32 = 1, + FeatureHWMultF5 = 2, + FeatureX = 3 +}; +} // end namespace MSP430 +} // end namespace llvm + +#endif // GET_SUBTARGETINFO_ENUM + + +#ifdef GET_SUBTARGETINFO_MC_DESC +#undef GET_SUBTARGETINFO_MC_DESC + +namespace llvm_ks { +// Sorted (by key) array of values for CPU features. +extern const llvm_ks::SubtargetFeatureKV MSP430FeatureKV[] = { + { "ext", "Enable MSP430-X extensions", { MSP430::FeatureX }, { } }, + { "hwmult16", "Enable 16-bit hardware multiplier", { MSP430::FeatureHWMult16 }, { } }, + { "hwmult32", "Enable 32-bit hardware multiplier", { MSP430::FeatureHWMult32 }, { } }, + { "hwmultf5", "Enable F5 series hardware multiplier", { MSP430::FeatureHWMultF5 }, { } } +}; + +// Sorted (by key) array of values for CPU subtype. +extern const llvm_ks::SubtargetFeatureKV MSP430SubTypeKV[] = { + { "generic", "Select the generic processor", { }, { } }, + { "msp430", "Select the msp430 processor", { }, { } }, + { "msp430x", "Select the msp430x processor", { MSP430::FeatureX }, { } } +}; + +#ifdef DBGFIELD +#error "GenSubtargetInfo.inc requires a DBGFIELD macro" +#endif +#ifndef NDEBUG +#define DBGFIELD(x) x, +#else +#define DBGFIELD(x) +#endif + +// =============================================================== +// Data tables for the new per-operand machine model. + +// {ProcResourceIdx, Cycles} +extern const llvm_ks::MCWriteProcResEntry MSP430WriteProcResTable[] = { + { 0, 0}, // Invalid +}; // MSP430WriteProcResTable + +// {Cycles, WriteResourceID} +extern const llvm_ks::MCWriteLatencyEntry MSP430WriteLatencyTable[] = { + { 0, 0}, // Invalid +}; // MSP430WriteLatencyTable + +// {UseIdx, WriteResourceID, Cycles} +extern const llvm_ks::MCReadAdvanceEntry MSP430ReadAdvanceTable[] = { + {0, 0, 0}, // Invalid +}; // MSP430ReadAdvanceTable + +static const llvm_ks::MCSchedModel NoSchedModel = { + MCSchedModel::DefaultIssueWidth, + MCSchedModel::DefaultMicroOpBufferSize, + MCSchedModel::DefaultLoopMicroOpBufferSize, + MCSchedModel::DefaultLoadLatency, + MCSchedModel::DefaultHighLatency, + MCSchedModel::DefaultMispredictPenalty, + false, // PostRAScheduler + false, // CompleteModel + 0, // Processor ID + nullptr, nullptr, 0, 0, // No instruction-level machine model. + nullptr}; // No Itinerary + +// Sorted (by key) array of itineraries for CPU subtype. +extern const llvm_ks::SubtargetInfoKV MSP430ProcSchedKV[] = { + { "generic", (const void *)&NoSchedModel }, + { "msp430", (const void *)&NoSchedModel }, + { "msp430x", (const void *)&NoSchedModel } +}; +#undef DBGFIELD +static inline MCSubtargetInfo *createMSP430MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) { + return new MCSubtargetInfo(TT, CPU, FS, MSP430FeatureKV, MSP430SubTypeKV, NULL); +} + +} // end namespace llvm + +#endif // GET_SUBTARGETINFO_MC_DESC + + +#ifdef GET_SUBTARGETINFO_TARGET_DESC +#undef GET_SUBTARGETINFO_TARGET_DESC + +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + +// ParseSubtargetFeatures - Parses features string setting specified +// subtarget options. +void llvm_ks::MSP430Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) { + DEBUG(dbgs() << "\nFeatures:" << FS); + DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n"); + InitMCProcessorInfo(CPU, FS); + const FeatureBitset& Bits = getFeatureBits(); + if (Bits[MSP430::FeatureHWMult16] && HWMultMode < HWMult16) HWMultMode = HWMult16; + if (Bits[MSP430::FeatureHWMult32] && HWMultMode < HWMult32) HWMultMode = HWMult32; + if (Bits[MSP430::FeatureHWMultF5] && HWMultMode < HWMultF5) HWMultMode = HWMultF5; + if (Bits[MSP430::FeatureX]) ExtendedInsts = true; +} +#endif // GET_SUBTARGETINFO_TARGET_DESC + + +#ifdef GET_SUBTARGETINFO_HEADER +#undef GET_SUBTARGETINFO_HEADER + +namespace llvm_ks { +class DFAPacketizer; +struct MSP430GenSubtargetInfo : public TargetSubtargetInfo { + explicit MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS); +public: + unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override; + DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const; +}; +} // end namespace llvm + +#endif // GET_SUBTARGETINFO_HEADER + + +#ifdef GET_SUBTARGETINFO_CTOR +#undef GET_SUBTARGETINFO_CTOR + +#include "llvm/CodeGen/TargetSchedule.h" + +namespace llvm_ks { +extern const llvm_ks::SubtargetFeatureKV MSP430FeatureKV[]; +extern const llvm_ks::SubtargetFeatureKV MSP430SubTypeKV[]; +extern const llvm_ks::SubtargetInfoKV MSP430ProcSchedKV[]; +extern const llvm_ks::MCWriteProcResEntry MSP430WriteProcResTable[]; +extern const llvm_ks::MCWriteLatencyEntry MSP430WriteLatencyTable[]; +extern const llvm_ks::MCReadAdvanceEntry MSP430ReadAdvanceTable[]; +MSP430GenSubtargetInfo::MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) + : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(MSP430FeatureKV, 4), makeArrayRef(MSP430SubTypeKV, 3), + MSP430ProcSchedKV, MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable, + 0, 0, 0) {} + +unsigned MSP430GenSubtargetInfo +::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const { + report_fatal_error("Expected a variant SchedClass"); +} // MSP430GenSubtargetInfo::resolveSchedClass +} // end namespace llvm + +#endif // GET_SUBTARGETINFO_CTOR + diff --git a/llvm/lib/Target/MSP430/TargetInfo/CMakeLists.txt b/llvm/lib/Target/MSP430/TargetInfo/CMakeLists.txt new file mode 100644 index 00000000..fee5f434 --- /dev/null +++ b/llvm/lib/Target/MSP430/TargetInfo/CMakeLists.txt @@ -0,0 +1,3 @@ +add_llvm_library(LLVMMSP430Info + MSP430TargetInfo.cpp + ) diff --git a/llvm/lib/Target/MSP430/TargetInfo/LLVMBuild.txt b/llvm/lib/Target/MSP430/TargetInfo/LLVMBuild.txt new file mode 100644 index 00000000..ee41ae46 --- /dev/null +++ b/llvm/lib/Target/MSP430/TargetInfo/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===- ./lib/Target/MSP430/TargetInfo/LLVMBuild.txt -------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = MSP430Info +parent = MSP430 +required_libraries = Support +add_to_library_groups = MSP430 diff --git a/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp b/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp new file mode 100644 index 00000000..0b281574 --- /dev/null +++ b/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp @@ -0,0 +1,20 @@ +//===-- MSP430TargetInfo.cpp - MSP430 Target Implementation ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "../MCTargetDesc/MSP430MCTargetDesc.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm_ks; + +Target llvm_ks::TheMSP430Target; + +extern "C" void LLVMInitializeMSP430TargetInfo() { + RegisterTarget + X(TheMSP430Target, "msp430", "MSP430"); +} diff --git a/samples/sample.c b/samples/sample.c index bf48dbce..e75e181e 100644 --- a/samples/sample.c +++ b/samples/sample.c @@ -137,6 +137,9 @@ int main(int argc, char **argv) test_ks(KS_ARCH_MIPS, KS_MODE_MIPS64, "and $9, $6, $7", 0); test_ks(KS_ARCH_MIPS, KS_MODE_MIPS64 + KS_MODE_BIG_ENDIAN, "and $9, $6, $7", 0); + // MSP430 + test_ks(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, "and r12, r13", 0); + // PowerPC test_ks(KS_ARCH_PPC, KS_MODE_PPC32 + KS_MODE_BIG_ENDIAN, "add 1, 2, 3", 0); test_ks(KS_ARCH_PPC, KS_MODE_PPC64, "add 1, 2, 3", 0); diff --git a/suite/fuzz/fuzz_asm_msp430.c b/suite/fuzz/fuzz_asm_msp430.c new file mode 100644 index 00000000..400bc348 --- /dev/null +++ b/suite/fuzz/fuzz_asm_msp430.c @@ -0,0 +1,66 @@ +#include + +#include + +FILE * outfile = NULL; + + +int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) { + ks_engine *ks; + ks_err err; + size_t count; + unsigned char *encode = NULL; + size_t size; + char * assembler; + + if (outfile == NULL) { + // we compute the output + outfile = fopen("/dev/null", "w"); + if (outfile == NULL) { + printf("failed opening /dev/null\n"); + abort(); + } + } + + if (Size < 1) { + return 0; + } + + err = ks_open(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, &ks); + if (err != KS_ERR_OK) { + printf("ERROR: failed on ks_open(), quit error = %u\n", err); + abort(); + } + + ks_option(ks, KS_OPT_SYNTAX, Data[Size-1]); + + assembler = malloc(Size); + memcpy(assembler, Data, Size-1); + //null terminate string + assembler[Size-1] = 0; + + if (ks_asm(ks, assembler, 0, &encode, &size, &count) != KS_ERR_OK) { + fprintf(outfile, "ERROR: ks_asm() failed & count = %lu, error = %u\n", + count, ks_errno(ks)); + } else { + size_t i; + + fprintf(outfile, "%s = ", assembler); + for (i = 0; i < size; i++) { + fprintf(outfile, "%02x ", encode[i]); + } + fprintf(outfile, "\n"); + fprintf(outfile, "Compiled: %lu bytes, statements: %lu\n", size, count); + } + + free(assembler); + // NOTE: free encode after usage to avoid leaking memory + if (encode != NULL) { + ks_free(encode); + } + + // close Keystone instance when done + ks_close(ks); + + return 0; +} diff --git a/suite/fuzz/gentargets.sh b/suite/fuzz/gentargets.sh old mode 100644 new mode 100755 index 0b08032a..5f8bdec9 --- a/suite/fuzz/gentargets.sh +++ b/suite/fuzz/gentargets.sh @@ -33,4 +33,6 @@ sed 's/KS_ARCH_X86/KS_ARCH_SPARC/' fuzz_asm_x86_32.c | sed 's/KS_MODE_32/KS_MODE sed 's/KS_ARCH_X86/KS_ARCH_SYSTEMZ/' fuzz_asm_x86_32.c | sed 's/KS_MODE_32/KS_MODE_BIG_ENDIAN/' > fuzz_asm_systemz.c +sed 's/KS_ARCH_X86/KS_ARCH_MSP430/' fuzz_asm_x86_32.c | sed 's/KS_MODE_32/KS_MODE_LITTLE_ENDIAN/' > fuzz_asm_msp430.c + sed 's/KS_ARCH_X86/KS_ARCH_EVM/' fuzz_asm_x86_32.c | sed 's/KS_MODE_32/0/' > fuzz_asm_evm.c diff --git a/suite/test-all.sh b/suite/test-all.sh index 7b955371..965a5ea4 100755 --- a/suite/test-all.sh +++ b/suite/test-all.sh @@ -75,6 +75,11 @@ kstool mips64be "and \$9, \$6, \$7" #encoding: [0x00,0xc7,0x48,0x24] echo +echo "::MSP430" +kstool msp430 "and \$9, \$6, \$7" +#encoding: [0x00,0xc7,0x48,0x24] +echo + echo "::SystemZ" kstool systemz "a %r0, 4095(%r15,%r1)" #encoding: [0x5a,0x0f,0x1f,0xff] From a7968a26f2de04880d502b571a681aa9ec2291fe Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Wed, 19 Dec 2018 17:43:16 -0500 Subject: [PATCH 02/14] Fix test-all.sh --- suite/test-all.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/suite/test-all.sh b/suite/test-all.sh index 965a5ea4..efbead76 100755 --- a/suite/test-all.sh +++ b/suite/test-all.sh @@ -76,8 +76,8 @@ kstool mips64be "and \$9, \$6, \$7" echo echo "::MSP430" -kstool msp430 "and \$9, \$6, \$7" -#encoding: [0x00,0xc7,0x48,0x24] +kstool msp430 "and r12, r13" +#encoding: [0x0d,0xfc] echo echo "::SystemZ" From f8dba9c51bf8ff16042ec1fb8a856b88e5e758b4 Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Wed, 19 Dec 2018 18:43:31 -0500 Subject: [PATCH 03/14] Use corrected TableGen output files --- .../lib/Target/MSP430/MSP430GenAsmMatcher.inc | 589 +++---- llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc | 1507 +++++++++-------- .../Target/MSP430/MSP430GenMCCodeEmitter.inc | 86 +- 3 files changed, 1125 insertions(+), 1057 deletions(-) diff --git a/llvm/lib/Target/MSP430/MSP430GenAsmMatcher.inc b/llvm/lib/Target/MSP430/MSP430GenAsmMatcher.inc index 6e16e7a8..154c8934 100644 --- a/llvm/lib/Target/MSP430/MSP430GenAsmMatcher.inc +++ b/llvm/lib/Target/MSP430/MSP430GenAsmMatcher.inc @@ -193,13 +193,13 @@ enum OperatorConversionKind { CVT_95_addMemOperands, CVT_95_addImmOperands, CVT_95_addRegOperands, + CVT_regSR, CVT_imm_95_1, + CVT_imm_95_4, CVT_imm_95_2, - CVT_regSR, CVT_imm_95_8, CVT_imm_95__MINUS_1, CVT_regCG, - CVT_imm_95_4, CVT_NUM_CONVERTERS }; @@ -218,8 +218,6 @@ enum InstructionConversionKind { Convert__Mem2_1__Mem2_0, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, Convert__Mem2_1__PostIndReg1_0, - Convert__Reg1_1__imm_95_0__Reg1_0, - Convert__Reg1_1__imm_95_0__Mem2_0, Convert__Reg1_1__Reg1_0, Convert__Reg1_1__CGImm1_0, Convert__Reg1_1__Imm1_0, @@ -228,6 +226,9 @@ enum InstructionConversionKind { Convert__Imm1_0, Convert__Mem2_0, Convert__Reg1_0__imm_95_0, + Convert__regSR__Tie0__imm_95_1, + Convert__regSR__Tie0__imm_95_4, + Convert__regSR__Tie0__imm_95_2, Convert__Reg1_0__Tie0__imm_95_1, Convert__Mem2_0__imm_95_1, Convert__Reg1_0__Tie0__imm_95_2, @@ -244,9 +245,6 @@ enum InstructionConversionKind { Convert__Reg1_0__Tie0__Reg1_0, Convert__Mem2_0__Mem2_0, Convert__Reg1_0__Tie0, - Convert__regSR__Tie0__imm_95_1, - Convert__regSR__Tie0__imm_95_4, - Convert__regSR__Tie0__imm_95_2, CVT_NUM_SIGNATURES }; @@ -281,10 +279,6 @@ static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = { { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Tied, 0, CVT_Tied, 1, CVT_Done }, // Convert__Mem2_1__PostIndReg1_0 { CVT_95_addMemOperands, 2, CVT_95_addRegOperands, 1, CVT_Done }, - // Convert__Reg1_1__imm_95_0__Reg1_0 - { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_Reg, 1, CVT_Done }, - // Convert__Reg1_1__imm_95_0__Mem2_0 - { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemOperands, 1, CVT_Done }, // Convert__Reg1_1__Reg1_0 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done }, // Convert__Reg1_1__CGImm1_0 @@ -301,6 +295,12 @@ static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = { { CVT_95_addMemOperands, 1, CVT_Done }, // Convert__Reg1_0__imm_95_0 { CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done }, + // Convert__regSR__Tie0__imm_95_1 + { CVT_regSR, 0, CVT_Tied, 0, CVT_imm_95_1, 0, CVT_Done }, + // Convert__regSR__Tie0__imm_95_4 + { CVT_regSR, 0, CVT_Tied, 0, CVT_imm_95_4, 0, CVT_Done }, + // Convert__regSR__Tie0__imm_95_2 + { CVT_regSR, 0, CVT_Tied, 0, CVT_imm_95_2, 0, CVT_Done }, // Convert__Reg1_0__Tie0__imm_95_1 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_imm_95_1, 0, CVT_Done }, // Convert__Mem2_0__imm_95_1 @@ -333,12 +333,6 @@ static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = { { CVT_95_addMemOperands, 1, CVT_95_addMemOperands, 1, CVT_Done }, // Convert__Reg1_0__Tie0 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_Done }, - // Convert__regSR__Tie0__imm_95_1 - { CVT_regSR, 0, CVT_Tied, 0, CVT_imm_95_1, 0, CVT_Done }, - // Convert__regSR__Tie0__imm_95_4 - { CVT_regSR, 0, CVT_Tied, 0, CVT_imm_95_4, 0, CVT_Done }, - // Convert__regSR__Tie0__imm_95_2 - { CVT_regSR, 0, CVT_Tied, 0, CVT_imm_95_2, 0, CVT_Done }, }; void MSP430AsmParser:: @@ -373,15 +367,18 @@ convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, case CVT_95_addRegOperands: static_cast(*Operands[OpIdx]).addRegOperands(Inst, 1); break; + case CVT_regSR: + Inst.addOperand(MCOperand::createReg(MSP430::SR)); + break; case CVT_imm_95_1: Inst.addOperand(MCOperand::createImm(1)); break; + case CVT_imm_95_4: + Inst.addOperand(MCOperand::createImm(4)); + break; case CVT_imm_95_2: Inst.addOperand(MCOperand::createImm(2)); break; - case CVT_regSR: - Inst.addOperand(MCOperand::createReg(MSP430::SR)); - break; case CVT_imm_95_8: Inst.addOperand(MCOperand::createImm(8)); break; @@ -391,9 +388,6 @@ convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, case CVT_regCG: Inst.addOperand(MCOperand::createReg(MSP430::CG)); break; - case CVT_imm_95_4: - Inst.addOperand(MCOperand::createImm(4)); - break; } } } @@ -440,19 +434,24 @@ convertToMapAndConstraints(unsigned Kind, Operands[*(p + 1)]->setConstraint("m"); NumMCOperands += 1; break; + case CVT_regSR: + Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); + Operands[*(p + 1)]->setConstraint("m"); + ++NumMCOperands; + break; case CVT_imm_95_1: Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); Operands[*(p + 1)]->setConstraint(""); ++NumMCOperands; break; - case CVT_imm_95_2: + case CVT_imm_95_4: Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); Operands[*(p + 1)]->setConstraint(""); ++NumMCOperands; break; - case CVT_regSR: + case CVT_imm_95_2: Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); - Operands[*(p + 1)]->setConstraint("m"); + Operands[*(p + 1)]->setConstraint(""); ++NumMCOperands; break; case CVT_imm_95_8: @@ -470,11 +469,6 @@ convertToMapAndConstraints(unsigned Kind, Operands[*(p + 1)]->setConstraint("m"); ++NumMCOperands; break; - case CVT_imm_95_4: - Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); - Operands[*(p + 1)]->setConstraint(""); - ++NumMCOperands; - break; } } } @@ -600,14 +594,15 @@ ComputeAvailableFeatures(const FeatureBitset& FB) const { } static const char *const MnemonicTable = - "\003adc\005adc.b\003add\005add.b\004addc\006addc.b\003and\005and.b\005b" - "ic.b\005bic.w\003bis\005bis.b\003bit\005bit.b\002br\004call\003clr\005c" - "lr.b\003cmp\005cmp.b\004dadc\006dadc.b\004dadd\006dadd.b\003dec\005dec." - "b\004decd\006decd.b\004eint\003inc\005inc.b\004incd\006incd.b\003inv\005" - "inv.b\001j\003jmp\003mov\005mov.b\003nop\003pop\004push\006push.b\003re" - "t\004reti\003rla\005rla.b\003rlc\005rlc.b\003rra\005rra.b\003rrc\005rrc" - ".b\003sbc\005sbc.b\004setc\004setn\004setz\003sub\005sub.b\004subc\006s" - "ubc.b\004swpb\003sxt\003tst\005tst.b\003xor\005xor.b"; + "\003adc\005adc.b\003add\005add.b\004addc\006addc.b\003and\005and.b\003b" + "ic\005bic.b\003bis\005bis.b\003bit\005bit.b\002br\004call\003clr\005clr" + ".b\004clrc\004clrn\004clrz\003cmp\005cmp.b\004dadc\006dadc.b\004dadd\006" + "dadd.b\003dec\005dec.b\004decd\006decd.b\004dint\004eint\003inc\005inc." + "b\004incd\006incd.b\003inv\005inv.b\001j\003jmp\003mov\005mov.b\003nop\003" + "pop\004push\006push.b\003ret\004reti\003rla\005rla.b\003rlc\005rlc.b\003" + "rra\005rra.b\003rrc\005rrc.b\003sbc\005sbc.b\004setc\004setn\004setz\003" + "sub\005sub.b\004subc\006subc.b\004swpb\003sxt\003tst\005tst.b\003xor\005" + "xor.b"; namespace { struct MatchEntry { @@ -713,254 +708,274 @@ static const MatchEntry MatchTable0[] = { { 36 /* and.b */, MSP430::AND8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, { 36 /* and.b */, MSP430::AND8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, { 36 /* and.b */, MSP430::AND8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, - { 42 /* bic.b */, MSP430::BIC8rr, Convert__Reg1_1__imm_95_0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, - { 42 /* bic.b */, MSP430::BIC8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, - { 42 /* bic.b */, MSP430::BIC8rm, Convert__Reg1_1__imm_95_0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, - { 42 /* bic.b */, MSP430::BIC8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 48 /* bic.w */, MSP430::BIC16rr, Convert__Reg1_1__imm_95_0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, - { 48 /* bic.w */, MSP430::BIC16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, - { 48 /* bic.w */, MSP430::BIC16rm, Convert__Reg1_1__imm_95_0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, - { 48 /* bic.w */, MSP430::BIC16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 54 /* bis */, MSP430::BIS16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, - { 54 /* bis */, MSP430::BIS16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, - { 54 /* bis */, MSP430::BIS16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, - { 54 /* bis */, MSP430::BIS16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 54 /* bis */, MSP430::BIS16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, - { 54 /* bis */, MSP430::BIS16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 54 /* bis */, MSP430::BIS16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, - { 54 /* bis */, MSP430::BIS16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, - { 54 /* bis */, MSP430::BIS16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, - { 54 /* bis */, MSP430::BIS16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 54 /* bis */, MSP430::BIS16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, - { 54 /* bis */, MSP430::BIS16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, - { 58 /* bis.b */, MSP430::BIS8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, - { 58 /* bis.b */, MSP430::BIS8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, - { 58 /* bis.b */, MSP430::BIS8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, - { 58 /* bis.b */, MSP430::BIS8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 58 /* bis.b */, MSP430::BIS8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, - { 58 /* bis.b */, MSP430::BIS8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 58 /* bis.b */, MSP430::BIS8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, - { 58 /* bis.b */, MSP430::BIS8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, - { 58 /* bis.b */, MSP430::BIS8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, - { 58 /* bis.b */, MSP430::BIS8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 58 /* bis.b */, MSP430::BIS8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, - { 58 /* bis.b */, MSP430::BIS8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, - { 64 /* bit */, MSP430::BIT16rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, - { 64 /* bit */, MSP430::BIT16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, - { 64 /* bit */, MSP430::BIT16rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, - { 64 /* bit */, MSP430::BIT16ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, - { 64 /* bit */, MSP430::BIT16mc, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 64 /* bit */, MSP430::BIT16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 64 /* bit */, MSP430::BIT16rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, - { 64 /* bit */, MSP430::BIT16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 68 /* bit.b */, MSP430::BIT8rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, - { 68 /* bit.b */, MSP430::BIT8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, - { 68 /* bit.b */, MSP430::BIT8rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, - { 68 /* bit.b */, MSP430::BIT8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 68 /* bit.b */, MSP430::BIT8ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, - { 68 /* bit.b */, MSP430::BIT8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 68 /* bit.b */, MSP430::BIT8rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, - { 68 /* bit.b */, MSP430::BIT8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 74 /* br */, MSP430::Br, Convert__Reg1_0, 0, { MCK_GR16 }, }, - { 74 /* br */, MSP430::Bi, Convert__Imm1_0, 0, { MCK_Imm }, }, - { 74 /* br */, MSP430::Bm, Convert__Mem2_0, 0, { MCK_Mem }, }, - { 77 /* call */, MSP430::CALLr, Convert__Reg1_0, 0, { MCK_GR16 }, }, - { 77 /* call */, MSP430::CALLi, Convert__Imm1_0, 0, { MCK_Imm }, }, - { 77 /* call */, MSP430::CALLm, Convert__Mem2_0, 0, { MCK_Mem }, }, - { 82 /* clr */, MSP430::MOV16rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR16 }, }, - { 82 /* clr */, MSP430::MOV16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, - { 86 /* clr.b */, MSP430::MOV8rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR8 }, }, - { 86 /* clr.b */, MSP430::MOV8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, - { 92 /* cmp */, MSP430::CMP16rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, - { 92 /* cmp */, MSP430::CMP16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, - { 92 /* cmp */, MSP430::CMP16rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, - { 92 /* cmp */, MSP430::CMP16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 92 /* cmp */, MSP430::CMP16ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, - { 92 /* cmp */, MSP430::CMP16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 92 /* cmp */, MSP430::CMP16rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, - { 96 /* cmp.b */, MSP430::CMP8rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, - { 96 /* cmp.b */, MSP430::CMP8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, - { 96 /* cmp.b */, MSP430::CMP8rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, - { 96 /* cmp.b */, MSP430::CMP8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 96 /* cmp.b */, MSP430::CMP8ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, - { 96 /* cmp.b */, MSP430::CMP8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 96 /* cmp.b */, MSP430::CMP8rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, - { 102 /* dadc */, MSP430::DADD16rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR16 }, }, - { 102 /* dadc */, MSP430::DADD16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, - { 107 /* dadc.b */, MSP430::DADD8rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR8 }, }, - { 107 /* dadc.b */, MSP430::DADD8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, - { 114 /* dadd */, MSP430::DADD16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, - { 114 /* dadd */, MSP430::DADD16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, - { 114 /* dadd */, MSP430::DADD16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, - { 114 /* dadd */, MSP430::DADD16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 114 /* dadd */, MSP430::DADD16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, - { 114 /* dadd */, MSP430::DADD16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 114 /* dadd */, MSP430::DADD16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, - { 114 /* dadd */, MSP430::DADD16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, - { 114 /* dadd */, MSP430::DADD16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, - { 114 /* dadd */, MSP430::DADD16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 114 /* dadd */, MSP430::DADD16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, - { 114 /* dadd */, MSP430::DADD16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, - { 119 /* dadd.b */, MSP430::DADD8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, - { 119 /* dadd.b */, MSP430::DADD8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, - { 119 /* dadd.b */, MSP430::DADD8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, - { 119 /* dadd.b */, MSP430::DADD8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 119 /* dadd.b */, MSP430::DADD8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, - { 119 /* dadd.b */, MSP430::DADD8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 119 /* dadd.b */, MSP430::DADD8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, - { 119 /* dadd.b */, MSP430::DADD8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, - { 119 /* dadd.b */, MSP430::DADD8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, - { 119 /* dadd.b */, MSP430::DADD8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 119 /* dadd.b */, MSP430::DADD8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, - { 119 /* dadd.b */, MSP430::DADD8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, - { 126 /* dec */, MSP430::SUB16rc, Convert__Reg1_0__Tie0__imm_95_1, 0, { MCK_GR16 }, }, - { 126 /* dec */, MSP430::SUB16mc, Convert__Mem2_0__imm_95_1, 0, { MCK_Mem }, }, - { 130 /* dec.b */, MSP430::SUB8rc, Convert__Reg1_0__Tie0__imm_95_1, 0, { MCK_GR8 }, }, - { 130 /* dec.b */, MSP430::SUB8mc, Convert__Mem2_0__imm_95_1, 0, { MCK_Mem }, }, - { 136 /* decd */, MSP430::SUB16rc, Convert__Reg1_0__Tie0__imm_95_2, 0, { MCK_GR16 }, }, - { 136 /* decd */, MSP430::SUB16mc, Convert__Mem2_0__imm_95_2, 0, { MCK_Mem }, }, - { 141 /* decd.b */, MSP430::SUB8rc, Convert__Reg1_0__Tie0__imm_95_2, 0, { MCK_GR8 }, }, - { 141 /* decd.b */, MSP430::SUB8mc, Convert__Mem2_0__imm_95_2, 0, { MCK_Mem }, }, - { 148 /* eint */, MSP430::BIS16rc, Convert__regSR__Tie0__imm_95_8, 0, { }, }, - { 153 /* inc */, MSP430::ADD16rc, Convert__Reg1_0__Tie0__imm_95_1, 0, { MCK_GR16 }, }, - { 153 /* inc */, MSP430::ADD16mc, Convert__Mem2_0__imm_95_1, 0, { MCK_Mem }, }, - { 157 /* inc.b */, MSP430::ADD8rc, Convert__Reg1_0__Tie0__imm_95_1, 0, { MCK_GR8 }, }, - { 157 /* inc.b */, MSP430::ADD8mc, Convert__Mem2_0__imm_95_1, 0, { MCK_Mem }, }, - { 163 /* incd */, MSP430::ADD16rc, Convert__Reg1_0__Tie0__imm_95_2, 0, { MCK_GR16 }, }, - { 163 /* incd */, MSP430::ADD16mc, Convert__Mem2_0__imm_95_2, 0, { MCK_Mem }, }, - { 168 /* incd.b */, MSP430::ADD8rc, Convert__Reg1_0__Tie0__imm_95_2, 0, { MCK_GR8 }, }, - { 168 /* incd.b */, MSP430::ADD8mc, Convert__Mem2_0__imm_95_2, 0, { MCK_Mem }, }, - { 175 /* inv */, MSP430::XOR16rc, Convert__Reg1_0__Tie0__imm_95__MINUS_1, 0, { MCK_GR16 }, }, - { 175 /* inv */, MSP430::XOR16mc, Convert__Mem2_0__imm_95__MINUS_1, 0, { MCK_Mem }, }, - { 179 /* inv.b */, MSP430::XOR8rc, Convert__Reg1_0__Tie0__imm_95__MINUS_1, 0, { MCK_GR8 }, }, - { 179 /* inv.b */, MSP430::XOR8mc, Convert__Mem2_0__imm_95__MINUS_1, 0, { MCK_Mem }, }, - { 185 /* j */, MSP430::JCC, Convert__Imm1_1__Imm1_0, 0, { MCK_Imm, MCK_Imm }, }, - { 187 /* jmp */, MSP430::JMP, Convert__Imm1_0, 0, { MCK_Imm }, }, - { 191 /* mov */, MSP430::MOV16rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, - { 191 /* mov */, MSP430::MOV16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, - { 191 /* mov */, MSP430::MOV16rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, - { 191 /* mov */, MSP430::MOV16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 191 /* mov */, MSP430::MOV16ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, - { 191 /* mov */, MSP430::MOV16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 191 /* mov */, MSP430::MOV16rn, Convert__Reg1_1__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, - { 191 /* mov */, MSP430::MOV16rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, - { 191 /* mov */, MSP430::MOV16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 191 /* mov */, MSP430::MOV16rp, Convert__Reg1_1__PostIndReg1_0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, - { 195 /* mov.b */, MSP430::MOV8rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, - { 195 /* mov.b */, MSP430::MOV8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, - { 195 /* mov.b */, MSP430::MOV8rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, - { 195 /* mov.b */, MSP430::MOV8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 195 /* mov.b */, MSP430::MOV8ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, - { 195 /* mov.b */, MSP430::MOV8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 195 /* mov.b */, MSP430::MOV8rn, Convert__Reg1_1__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, - { 195 /* mov.b */, MSP430::MOV8rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, - { 195 /* mov.b */, MSP430::MOV8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 195 /* mov.b */, MSP430::MOV8rp, Convert__Reg1_1__PostIndReg1_0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, - { 201 /* nop */, MSP430::MOV16rc, Convert__regCG__imm_95_0, 0, { }, }, - { 205 /* pop */, MSP430::POP16r, Convert__Reg1_0, 0, { MCK_GR16 }, }, - { 209 /* push */, MSP430::PUSH16r, Convert__Reg1_0, 0, { MCK_GR16 }, }, - { 209 /* push */, MSP430::PUSH16c, Convert__CGImm1_0, 0, { MCK_CGImm }, }, - { 209 /* push */, MSP430::PUSH16i, Convert__Imm1_0, 0, { MCK_Imm }, }, - { 214 /* push.b */, MSP430::PUSH8r, Convert__Reg1_0, 0, { MCK_GR8 }, }, - { 221 /* ret */, MSP430::RET, Convert_NoOperands, 0, { }, }, - { 225 /* reti */, MSP430::RETI, Convert_NoOperands, 0, { }, }, - { 230 /* rla */, MSP430::ADD16rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR16 }, }, - { 230 /* rla */, MSP430::ADD16mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, - { 234 /* rla.b */, MSP430::ADD8rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR8 }, }, - { 234 /* rla.b */, MSP430::ADD8mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, - { 240 /* rlc */, MSP430::ADDC16rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR16 }, }, - { 240 /* rlc */, MSP430::ADDC16mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, - { 244 /* rlc.b */, MSP430::ADDC8rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR8 }, }, - { 244 /* rlc.b */, MSP430::ADDC8mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, - { 250 /* rra */, MSP430::RRA16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, - { 254 /* rra.b */, MSP430::RRA8r, Convert__Reg1_0__Tie0, 0, { MCK_GR8 }, }, - { 260 /* rrc */, MSP430::RRC16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, - { 264 /* rrc.b */, MSP430::RRC8r, Convert__Reg1_0__Tie0, 0, { MCK_GR8 }, }, - { 270 /* sbc */, MSP430::SUBC16rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR16 }, }, - { 270 /* sbc */, MSP430::SUBC16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, - { 274 /* sbc.b */, MSP430::SUBC8rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR8 }, }, - { 274 /* sbc.b */, MSP430::SUBC8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, - { 280 /* setc */, MSP430::BIS16rc, Convert__regSR__Tie0__imm_95_1, 0, { }, }, - { 285 /* setn */, MSP430::BIS16rc, Convert__regSR__Tie0__imm_95_4, 0, { }, }, - { 290 /* setz */, MSP430::BIS16rc, Convert__regSR__Tie0__imm_95_2, 0, { }, }, - { 295 /* sub */, MSP430::SUB16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, - { 295 /* sub */, MSP430::SUB16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, - { 295 /* sub */, MSP430::SUB16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, - { 295 /* sub */, MSP430::SUB16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 295 /* sub */, MSP430::SUB16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, - { 295 /* sub */, MSP430::SUB16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 295 /* sub */, MSP430::SUB16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, - { 295 /* sub */, MSP430::SUB16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, - { 295 /* sub */, MSP430::SUB16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, - { 295 /* sub */, MSP430::SUB16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 295 /* sub */, MSP430::SUB16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, - { 295 /* sub */, MSP430::SUB16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, - { 299 /* sub.b */, MSP430::SUB8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, - { 299 /* sub.b */, MSP430::SUB8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, - { 299 /* sub.b */, MSP430::SUB8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, - { 299 /* sub.b */, MSP430::SUB8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 299 /* sub.b */, MSP430::SUB8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, - { 299 /* sub.b */, MSP430::SUB8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 299 /* sub.b */, MSP430::SUB8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, - { 299 /* sub.b */, MSP430::SUB8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, - { 299 /* sub.b */, MSP430::SUB8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, - { 299 /* sub.b */, MSP430::SUB8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 299 /* sub.b */, MSP430::SUB8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, - { 299 /* sub.b */, MSP430::SUB8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, - { 305 /* subc */, MSP430::SUBC16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, - { 305 /* subc */, MSP430::SUBC16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, - { 305 /* subc */, MSP430::SUBC16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, - { 305 /* subc */, MSP430::SUBC16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 305 /* subc */, MSP430::SUBC16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, - { 305 /* subc */, MSP430::SUBC16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 305 /* subc */, MSP430::SUBC16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, - { 305 /* subc */, MSP430::SUBC16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, - { 305 /* subc */, MSP430::SUBC16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, - { 305 /* subc */, MSP430::SUBC16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 305 /* subc */, MSP430::SUBC16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, - { 305 /* subc */, MSP430::SUBC16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, - { 310 /* subc.b */, MSP430::SUBC8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, - { 310 /* subc.b */, MSP430::SUBC8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, - { 310 /* subc.b */, MSP430::SUBC8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, - { 310 /* subc.b */, MSP430::SUBC8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 310 /* subc.b */, MSP430::SUBC8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, - { 310 /* subc.b */, MSP430::SUBC8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 310 /* subc.b */, MSP430::SUBC8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, - { 310 /* subc.b */, MSP430::SUBC8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, - { 310 /* subc.b */, MSP430::SUBC8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, - { 310 /* subc.b */, MSP430::SUBC8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 310 /* subc.b */, MSP430::SUBC8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, - { 310 /* subc.b */, MSP430::SUBC8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, - { 317 /* swpb */, MSP430::SWPB16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, - { 322 /* sxt */, MSP430::SEXT16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, - { 326 /* tst */, MSP430::CMP16rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR16 }, }, - { 326 /* tst */, MSP430::CMP16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, - { 330 /* tst.b */, MSP430::CMP8rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR8 }, }, - { 330 /* tst.b */, MSP430::CMP8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, - { 336 /* xor */, MSP430::XOR16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, - { 336 /* xor */, MSP430::XOR16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, - { 336 /* xor */, MSP430::XOR16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, - { 336 /* xor */, MSP430::XOR16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 336 /* xor */, MSP430::XOR16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, - { 336 /* xor */, MSP430::XOR16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 336 /* xor */, MSP430::XOR16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, - { 336 /* xor */, MSP430::XOR16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, - { 336 /* xor */, MSP430::XOR16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, - { 336 /* xor */, MSP430::XOR16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 336 /* xor */, MSP430::XOR16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, - { 336 /* xor */, MSP430::XOR16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, - { 340 /* xor.b */, MSP430::XOR8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, - { 340 /* xor.b */, MSP430::XOR8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, - { 340 /* xor.b */, MSP430::XOR8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, - { 340 /* xor.b */, MSP430::XOR8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, - { 340 /* xor.b */, MSP430::XOR8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, - { 340 /* xor.b */, MSP430::XOR8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, - { 340 /* xor.b */, MSP430::XOR8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, - { 340 /* xor.b */, MSP430::XOR8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, - { 340 /* xor.b */, MSP430::XOR8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, - { 340 /* xor.b */, MSP430::XOR8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, - { 340 /* xor.b */, MSP430::XOR8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, - { 340 /* xor.b */, MSP430::XOR8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 42 /* bic */, MSP430::BIC16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 42 /* bic */, MSP430::BIC16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 42 /* bic */, MSP430::BIC16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 42 /* bic */, MSP430::BIC16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 42 /* bic */, MSP430::BIC16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 42 /* bic */, MSP430::BIC16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 42 /* bic */, MSP430::BIC16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 42 /* bic */, MSP430::BIC16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 42 /* bic */, MSP430::BIC16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 42 /* bic */, MSP430::BIC16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 42 /* bic */, MSP430::BIC16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 42 /* bic */, MSP430::BIC16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 46 /* bic.b */, MSP430::BIC8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 46 /* bic.b */, MSP430::BIC8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 46 /* bic.b */, MSP430::BIC8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 46 /* bic.b */, MSP430::BIC8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 46 /* bic.b */, MSP430::BIC8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 46 /* bic.b */, MSP430::BIC8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 46 /* bic.b */, MSP430::BIC8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 46 /* bic.b */, MSP430::BIC8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 46 /* bic.b */, MSP430::BIC8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 46 /* bic.b */, MSP430::BIC8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 46 /* bic.b */, MSP430::BIC8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 46 /* bic.b */, MSP430::BIC8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 52 /* bis */, MSP430::BIS16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 52 /* bis */, MSP430::BIS16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 52 /* bis */, MSP430::BIS16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 52 /* bis */, MSP430::BIS16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 52 /* bis */, MSP430::BIS16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 52 /* bis */, MSP430::BIS16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 52 /* bis */, MSP430::BIS16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 52 /* bis */, MSP430::BIS16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 52 /* bis */, MSP430::BIS16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 52 /* bis */, MSP430::BIS16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 52 /* bis */, MSP430::BIS16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 52 /* bis */, MSP430::BIS16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 56 /* bis.b */, MSP430::BIS8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 56 /* bis.b */, MSP430::BIS8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 56 /* bis.b */, MSP430::BIS8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 56 /* bis.b */, MSP430::BIS8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 56 /* bis.b */, MSP430::BIS8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 56 /* bis.b */, MSP430::BIS8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 56 /* bis.b */, MSP430::BIS8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 56 /* bis.b */, MSP430::BIS8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 56 /* bis.b */, MSP430::BIS8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 56 /* bis.b */, MSP430::BIS8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 56 /* bis.b */, MSP430::BIS8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 56 /* bis.b */, MSP430::BIS8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 62 /* bit */, MSP430::BIT16rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 62 /* bit */, MSP430::BIT16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 62 /* bit */, MSP430::BIT16rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 62 /* bit */, MSP430::BIT16ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 62 /* bit */, MSP430::BIT16mc, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 62 /* bit */, MSP430::BIT16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 62 /* bit */, MSP430::BIT16rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 62 /* bit */, MSP430::BIT16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 66 /* bit.b */, MSP430::BIT8rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 66 /* bit.b */, MSP430::BIT8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 66 /* bit.b */, MSP430::BIT8rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 66 /* bit.b */, MSP430::BIT8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 66 /* bit.b */, MSP430::BIT8ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 66 /* bit.b */, MSP430::BIT8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 66 /* bit.b */, MSP430::BIT8rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 66 /* bit.b */, MSP430::BIT8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 72 /* br */, MSP430::Br, Convert__Reg1_0, 0, { MCK_GR16 }, }, + { 72 /* br */, MSP430::Bi, Convert__Imm1_0, 0, { MCK_Imm }, }, + { 72 /* br */, MSP430::Bm, Convert__Mem2_0, 0, { MCK_Mem }, }, + { 75 /* call */, MSP430::CALLr, Convert__Reg1_0, 0, { MCK_GR16 }, }, + { 75 /* call */, MSP430::CALLi, Convert__Imm1_0, 0, { MCK_Imm }, }, + { 75 /* call */, MSP430::CALLm, Convert__Mem2_0, 0, { MCK_Mem }, }, + { 80 /* clr */, MSP430::MOV16rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR16 }, }, + { 80 /* clr */, MSP430::MOV16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 84 /* clr.b */, MSP430::MOV8rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR8 }, }, + { 84 /* clr.b */, MSP430::MOV8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 90 /* clrc */, MSP430::BIC16rc, Convert__regSR__Tie0__imm_95_1, 0, { }, }, + { 95 /* clrn */, MSP430::BIC16rc, Convert__regSR__Tie0__imm_95_4, 0, { }, }, + { 100 /* clrz */, MSP430::BIC16rc, Convert__regSR__Tie0__imm_95_2, 0, { }, }, + { 105 /* cmp */, MSP430::CMP16rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 105 /* cmp */, MSP430::CMP16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 105 /* cmp */, MSP430::CMP16rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 105 /* cmp */, MSP430::CMP16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 105 /* cmp */, MSP430::CMP16ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 105 /* cmp */, MSP430::CMP16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 105 /* cmp */, MSP430::CMP16rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 109 /* cmp.b */, MSP430::CMP8rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 109 /* cmp.b */, MSP430::CMP8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 109 /* cmp.b */, MSP430::CMP8rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 109 /* cmp.b */, MSP430::CMP8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 109 /* cmp.b */, MSP430::CMP8ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 109 /* cmp.b */, MSP430::CMP8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 109 /* cmp.b */, MSP430::CMP8rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 115 /* dadc */, MSP430::DADD16rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR16 }, }, + { 115 /* dadc */, MSP430::DADD16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 120 /* dadc.b */, MSP430::DADD8rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR8 }, }, + { 120 /* dadc.b */, MSP430::DADD8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 127 /* dadd */, MSP430::DADD16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 127 /* dadd */, MSP430::DADD16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 127 /* dadd */, MSP430::DADD16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 127 /* dadd */, MSP430::DADD16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 127 /* dadd */, MSP430::DADD16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 127 /* dadd */, MSP430::DADD16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 127 /* dadd */, MSP430::DADD16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 127 /* dadd */, MSP430::DADD16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 127 /* dadd */, MSP430::DADD16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 127 /* dadd */, MSP430::DADD16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 127 /* dadd */, MSP430::DADD16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 127 /* dadd */, MSP430::DADD16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 132 /* dadd.b */, MSP430::DADD8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 132 /* dadd.b */, MSP430::DADD8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 132 /* dadd.b */, MSP430::DADD8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 132 /* dadd.b */, MSP430::DADD8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 132 /* dadd.b */, MSP430::DADD8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 132 /* dadd.b */, MSP430::DADD8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 132 /* dadd.b */, MSP430::DADD8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 132 /* dadd.b */, MSP430::DADD8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 132 /* dadd.b */, MSP430::DADD8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 132 /* dadd.b */, MSP430::DADD8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 132 /* dadd.b */, MSP430::DADD8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 132 /* dadd.b */, MSP430::DADD8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 139 /* dec */, MSP430::SUB16rc, Convert__Reg1_0__Tie0__imm_95_1, 0, { MCK_GR16 }, }, + { 139 /* dec */, MSP430::SUB16mc, Convert__Mem2_0__imm_95_1, 0, { MCK_Mem }, }, + { 143 /* dec.b */, MSP430::SUB8rc, Convert__Reg1_0__Tie0__imm_95_1, 0, { MCK_GR8 }, }, + { 143 /* dec.b */, MSP430::SUB8mc, Convert__Mem2_0__imm_95_1, 0, { MCK_Mem }, }, + { 149 /* decd */, MSP430::SUB16rc, Convert__Reg1_0__Tie0__imm_95_2, 0, { MCK_GR16 }, }, + { 149 /* decd */, MSP430::SUB16mc, Convert__Mem2_0__imm_95_2, 0, { MCK_Mem }, }, + { 154 /* decd.b */, MSP430::SUB8rc, Convert__Reg1_0__Tie0__imm_95_2, 0, { MCK_GR8 }, }, + { 154 /* decd.b */, MSP430::SUB8mc, Convert__Mem2_0__imm_95_2, 0, { MCK_Mem }, }, + { 161 /* dint */, MSP430::BIC16rc, Convert__regSR__Tie0__imm_95_8, 0, { }, }, + { 166 /* eint */, MSP430::BIS16rc, Convert__regSR__Tie0__imm_95_8, 0, { }, }, + { 171 /* inc */, MSP430::ADD16rc, Convert__Reg1_0__Tie0__imm_95_1, 0, { MCK_GR16 }, }, + { 171 /* inc */, MSP430::ADD16mc, Convert__Mem2_0__imm_95_1, 0, { MCK_Mem }, }, + { 175 /* inc.b */, MSP430::ADD8rc, Convert__Reg1_0__Tie0__imm_95_1, 0, { MCK_GR8 }, }, + { 175 /* inc.b */, MSP430::ADD8mc, Convert__Mem2_0__imm_95_1, 0, { MCK_Mem }, }, + { 181 /* incd */, MSP430::ADD16rc, Convert__Reg1_0__Tie0__imm_95_2, 0, { MCK_GR16 }, }, + { 181 /* incd */, MSP430::ADD16mc, Convert__Mem2_0__imm_95_2, 0, { MCK_Mem }, }, + { 186 /* incd.b */, MSP430::ADD8rc, Convert__Reg1_0__Tie0__imm_95_2, 0, { MCK_GR8 }, }, + { 186 /* incd.b */, MSP430::ADD8mc, Convert__Mem2_0__imm_95_2, 0, { MCK_Mem }, }, + { 193 /* inv */, MSP430::XOR16rc, Convert__Reg1_0__Tie0__imm_95__MINUS_1, 0, { MCK_GR16 }, }, + { 193 /* inv */, MSP430::XOR16mc, Convert__Mem2_0__imm_95__MINUS_1, 0, { MCK_Mem }, }, + { 197 /* inv.b */, MSP430::XOR8rc, Convert__Reg1_0__Tie0__imm_95__MINUS_1, 0, { MCK_GR8 }, }, + { 197 /* inv.b */, MSP430::XOR8mc, Convert__Mem2_0__imm_95__MINUS_1, 0, { MCK_Mem }, }, + { 203 /* j */, MSP430::JCC, Convert__Imm1_1__Imm1_0, 0, { MCK_Imm, MCK_Imm }, }, + { 205 /* jmp */, MSP430::JMP, Convert__Imm1_0, 0, { MCK_Imm }, }, + { 209 /* mov */, MSP430::MOV16rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 209 /* mov */, MSP430::MOV16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 209 /* mov */, MSP430::MOV16rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 209 /* mov */, MSP430::MOV16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 209 /* mov */, MSP430::MOV16ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 209 /* mov */, MSP430::MOV16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 209 /* mov */, MSP430::MOV16rn, Convert__Reg1_1__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 209 /* mov */, MSP430::MOV16rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 209 /* mov */, MSP430::MOV16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 209 /* mov */, MSP430::MOV16rp, Convert__Reg1_1__PostIndReg1_0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 213 /* mov.b */, MSP430::MOV8rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 213 /* mov.b */, MSP430::MOV8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 213 /* mov.b */, MSP430::MOV8rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 213 /* mov.b */, MSP430::MOV8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 213 /* mov.b */, MSP430::MOV8ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 213 /* mov.b */, MSP430::MOV8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 213 /* mov.b */, MSP430::MOV8rn, Convert__Reg1_1__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 213 /* mov.b */, MSP430::MOV8rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 213 /* mov.b */, MSP430::MOV8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 213 /* mov.b */, MSP430::MOV8rp, Convert__Reg1_1__PostIndReg1_0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 219 /* nop */, MSP430::MOV16rc, Convert__regCG__imm_95_0, 0, { }, }, + { 223 /* pop */, MSP430::POP16r, Convert__Reg1_0, 0, { MCK_GR16 }, }, + { 227 /* push */, MSP430::PUSH16r, Convert__Reg1_0, 0, { MCK_GR16 }, }, + { 227 /* push */, MSP430::PUSH16c, Convert__CGImm1_0, 0, { MCK_CGImm }, }, + { 227 /* push */, MSP430::PUSH16i, Convert__Imm1_0, 0, { MCK_Imm }, }, + { 232 /* push.b */, MSP430::PUSH8r, Convert__Reg1_0, 0, { MCK_GR8 }, }, + { 239 /* ret */, MSP430::RET, Convert_NoOperands, 0, { }, }, + { 243 /* reti */, MSP430::RETI, Convert_NoOperands, 0, { }, }, + { 248 /* rla */, MSP430::ADD16rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR16 }, }, + { 248 /* rla */, MSP430::ADD16mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, + { 252 /* rla.b */, MSP430::ADD8rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR8 }, }, + { 252 /* rla.b */, MSP430::ADD8mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, + { 258 /* rlc */, MSP430::ADDC16rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR16 }, }, + { 258 /* rlc */, MSP430::ADDC16mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, + { 262 /* rlc.b */, MSP430::ADDC8rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR8 }, }, + { 262 /* rlc.b */, MSP430::ADDC8mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, + { 268 /* rra */, MSP430::RRA16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, + { 272 /* rra.b */, MSP430::RRA8r, Convert__Reg1_0__Tie0, 0, { MCK_GR8 }, }, + { 278 /* rrc */, MSP430::RRC16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, + { 282 /* rrc.b */, MSP430::RRC8r, Convert__Reg1_0__Tie0, 0, { MCK_GR8 }, }, + { 288 /* sbc */, MSP430::SUBC16rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR16 }, }, + { 288 /* sbc */, MSP430::SUBC16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 292 /* sbc.b */, MSP430::SUBC8rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR8 }, }, + { 292 /* sbc.b */, MSP430::SUBC8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 298 /* setc */, MSP430::BIS16rc, Convert__regSR__Tie0__imm_95_1, 0, { }, }, + { 303 /* setn */, MSP430::BIS16rc, Convert__regSR__Tie0__imm_95_4, 0, { }, }, + { 308 /* setz */, MSP430::BIS16rc, Convert__regSR__Tie0__imm_95_2, 0, { }, }, + { 313 /* sub */, MSP430::SUB16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 313 /* sub */, MSP430::SUB16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 313 /* sub */, MSP430::SUB16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 313 /* sub */, MSP430::SUB16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 313 /* sub */, MSP430::SUB16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 313 /* sub */, MSP430::SUB16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 313 /* sub */, MSP430::SUB16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 313 /* sub */, MSP430::SUB16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 313 /* sub */, MSP430::SUB16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 313 /* sub */, MSP430::SUB16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 313 /* sub */, MSP430::SUB16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 313 /* sub */, MSP430::SUB16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 317 /* sub.b */, MSP430::SUB8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 317 /* sub.b */, MSP430::SUB8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 317 /* sub.b */, MSP430::SUB8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 317 /* sub.b */, MSP430::SUB8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 317 /* sub.b */, MSP430::SUB8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 317 /* sub.b */, MSP430::SUB8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 317 /* sub.b */, MSP430::SUB8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 317 /* sub.b */, MSP430::SUB8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 317 /* sub.b */, MSP430::SUB8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 317 /* sub.b */, MSP430::SUB8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 317 /* sub.b */, MSP430::SUB8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 317 /* sub.b */, MSP430::SUB8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 323 /* subc */, MSP430::SUBC16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 323 /* subc */, MSP430::SUBC16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 323 /* subc */, MSP430::SUBC16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 323 /* subc */, MSP430::SUBC16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 323 /* subc */, MSP430::SUBC16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 323 /* subc */, MSP430::SUBC16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 323 /* subc */, MSP430::SUBC16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 323 /* subc */, MSP430::SUBC16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 323 /* subc */, MSP430::SUBC16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 323 /* subc */, MSP430::SUBC16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 323 /* subc */, MSP430::SUBC16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 323 /* subc */, MSP430::SUBC16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 328 /* subc.b */, MSP430::SUBC8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 328 /* subc.b */, MSP430::SUBC8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 328 /* subc.b */, MSP430::SUBC8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 328 /* subc.b */, MSP430::SUBC8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 328 /* subc.b */, MSP430::SUBC8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 328 /* subc.b */, MSP430::SUBC8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 328 /* subc.b */, MSP430::SUBC8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 328 /* subc.b */, MSP430::SUBC8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 328 /* subc.b */, MSP430::SUBC8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 328 /* subc.b */, MSP430::SUBC8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 328 /* subc.b */, MSP430::SUBC8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 328 /* subc.b */, MSP430::SUBC8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 335 /* swpb */, MSP430::SWPB16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, + { 340 /* sxt */, MSP430::SEXT16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, + { 344 /* tst */, MSP430::CMP16rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR16 }, }, + { 344 /* tst */, MSP430::CMP16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 348 /* tst.b */, MSP430::CMP8rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR8 }, }, + { 348 /* tst.b */, MSP430::CMP8mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, + { 354 /* xor */, MSP430::XOR16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, }, + { 354 /* xor */, MSP430::XOR16mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR16, MCK_Mem }, }, + { 354 /* xor */, MSP430::XOR16rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR16 }, }, + { 354 /* xor */, MSP430::XOR16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 354 /* xor */, MSP430::XOR16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, + { 354 /* xor */, MSP430::XOR16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 354 /* xor */, MSP430::XOR16rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 354 /* xor */, MSP430::XOR16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 354 /* xor */, MSP430::XOR16rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 354 /* xor */, MSP430::XOR16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 354 /* xor */, MSP430::XOR16rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 354 /* xor */, MSP430::XOR16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 358 /* xor.b */, MSP430::XOR8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, + { 358 /* xor.b */, MSP430::XOR8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, + { 358 /* xor.b */, MSP430::XOR8rc, Convert__Reg1_1__Tie0__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, + { 358 /* xor.b */, MSP430::XOR8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, + { 358 /* xor.b */, MSP430::XOR8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, + { 358 /* xor.b */, MSP430::XOR8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 358 /* xor.b */, MSP430::XOR8rn, Convert__Reg1_1__Tie0__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 358 /* xor.b */, MSP430::XOR8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, + { 358 /* xor.b */, MSP430::XOR8rm, Convert__Reg1_1__Tie0__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 358 /* xor.b */, MSP430::XOR8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 358 /* xor.b */, MSP430::XOR8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 358 /* xor.b */, MSP430::XOR8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, }; bool MSP430AsmParser:: diff --git a/llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc b/llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc index aa8733a6..3c88af21 100644 --- a/llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc +++ b/llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc @@ -116,219 +116,235 @@ namespace MSP430 { AND8rn = 101, AND8rp = 102, AND8rr = 103, - BIC16mm = 104, - BIC16mr = 105, - BIC16rm = 106, - BIC16rr = 107, - BIC8mm = 108, - BIC8mr = 109, - BIC8rm = 110, - BIC8rr = 111, - BIS16mc = 112, - BIS16mi = 113, - BIS16mm = 114, - BIS16mn = 115, - BIS16mp = 116, - BIS16mr = 117, - BIS16rc = 118, - BIS16ri = 119, - BIS16rm = 120, - BIS16rn = 121, - BIS16rp = 122, - BIS16rr = 123, - BIS8mc = 124, - BIS8mi = 125, - BIS8mm = 126, - BIS8mn = 127, - BIS8mp = 128, - BIS8mr = 129, - BIS8rc = 130, - BIS8ri = 131, - BIS8rm = 132, - BIS8rn = 133, - BIS8rp = 134, - BIS8rr = 135, - BIT16mc = 136, - BIT16mi = 137, - BIT16mm = 138, - BIT16mr = 139, - BIT16rc = 140, - BIT16ri = 141, - BIT16rm = 142, - BIT16rr = 143, - BIT8mc = 144, - BIT8mi = 145, - BIT8mm = 146, - BIT8mr = 147, - BIT8rc = 148, - BIT8ri = 149, - BIT8rm = 150, - BIT8rr = 151, - Bi = 152, - Bm = 153, - Br = 154, - CALLi = 155, - CALLm = 156, - CALLr = 157, - CMP16mc = 158, - CMP16mi = 159, - CMP16mr = 160, - CMP16rc = 161, - CMP16ri = 162, - CMP16rm = 163, - CMP16rr = 164, - CMP8mc = 165, - CMP8mi = 166, - CMP8mr = 167, - CMP8rc = 168, - CMP8ri = 169, - CMP8rm = 170, - CMP8rr = 171, - DADD16mc = 172, - DADD16mi = 173, - DADD16mm = 174, - DADD16mn = 175, - DADD16mp = 176, - DADD16mr = 177, - DADD16rc = 178, - DADD16ri = 179, - DADD16rm = 180, - DADD16rn = 181, - DADD16rp = 182, - DADD16rr = 183, - DADD8mc = 184, - DADD8mi = 185, - DADD8mm = 186, - DADD8mn = 187, - DADD8mp = 188, - DADD8mr = 189, - DADD8rc = 190, - DADD8ri = 191, - DADD8rm = 192, - DADD8rn = 193, - DADD8rp = 194, - DADD8rr = 195, - JCC = 196, - JMP = 197, - MOV16mc = 198, - MOV16mi = 199, - MOV16mm = 200, - MOV16mr = 201, - MOV16rc = 202, - MOV16ri = 203, - MOV16rm = 204, - MOV16rn = 205, - MOV16rp = 206, - MOV16rr = 207, - MOV8mc = 208, - MOV8mi = 209, - MOV8mm = 210, - MOV8mr = 211, - MOV8rc = 212, - MOV8ri = 213, - MOV8rm = 214, - MOV8rn = 215, - MOV8rp = 216, - MOV8rr = 217, - MOVZX16rm8 = 218, - MOVZX16rr8 = 219, - POP16r = 220, - PUSH16c = 221, - PUSH16i = 222, - PUSH16r = 223, - PUSH8r = 224, - RET = 225, - RETI = 226, - RRA16r = 227, - RRA8r = 228, - RRC16r = 229, - RRC8r = 230, - Rrcl16 = 231, - Rrcl8 = 232, - SEXT16r = 233, - SUB16mc = 234, - SUB16mi = 235, - SUB16mm = 236, - SUB16mn = 237, - SUB16mp = 238, - SUB16mr = 239, - SUB16rc = 240, - SUB16ri = 241, - SUB16rm = 242, - SUB16rn = 243, - SUB16rp = 244, - SUB16rr = 245, - SUB8mc = 246, - SUB8mi = 247, - SUB8mm = 248, - SUB8mn = 249, - SUB8mp = 250, - SUB8mr = 251, - SUB8rc = 252, - SUB8ri = 253, - SUB8rm = 254, - SUB8rn = 255, - SUB8rp = 256, - SUB8rr = 257, - SUBC16mc = 258, - SUBC16mi = 259, - SUBC16mm = 260, - SUBC16mn = 261, - SUBC16mp = 262, - SUBC16mr = 263, - SUBC16rc = 264, - SUBC16ri = 265, - SUBC16rm = 266, - SUBC16rn = 267, - SUBC16rp = 268, - SUBC16rr = 269, - SUBC8mc = 270, - SUBC8mi = 271, - SUBC8mm = 272, - SUBC8mn = 273, - SUBC8mp = 274, - SUBC8mr = 275, - SUBC8rc = 276, - SUBC8ri = 277, - SUBC8rm = 278, - SUBC8rn = 279, - SUBC8rp = 280, - SUBC8rr = 281, - SWPB16r = 282, - Select16 = 283, - Select8 = 284, - Shl16 = 285, - Shl8 = 286, - Sra16 = 287, - Sra8 = 288, - Srl16 = 289, - Srl8 = 290, - XOR16mc = 291, - XOR16mi = 292, - XOR16mm = 293, - XOR16mn = 294, - XOR16mp = 295, - XOR16mr = 296, - XOR16rc = 297, - XOR16ri = 298, - XOR16rm = 299, - XOR16rn = 300, - XOR16rp = 301, - XOR16rr = 302, - XOR8mc = 303, - XOR8mi = 304, - XOR8mm = 305, - XOR8mn = 306, - XOR8mp = 307, - XOR8mr = 308, - XOR8rc = 309, - XOR8ri = 310, - XOR8rm = 311, - XOR8rn = 312, - XOR8rp = 313, - XOR8rr = 314, - ZEXT16r = 315, - INSTRUCTION_LIST_END = 316 + BIC16mc = 104, + BIC16mi = 105, + BIC16mm = 106, + BIC16mn = 107, + BIC16mp = 108, + BIC16mr = 109, + BIC16rc = 110, + BIC16ri = 111, + BIC16rm = 112, + BIC16rn = 113, + BIC16rp = 114, + BIC16rr = 115, + BIC8mc = 116, + BIC8mi = 117, + BIC8mm = 118, + BIC8mn = 119, + BIC8mp = 120, + BIC8mr = 121, + BIC8rc = 122, + BIC8ri = 123, + BIC8rm = 124, + BIC8rn = 125, + BIC8rp = 126, + BIC8rr = 127, + BIS16mc = 128, + BIS16mi = 129, + BIS16mm = 130, + BIS16mn = 131, + BIS16mp = 132, + BIS16mr = 133, + BIS16rc = 134, + BIS16ri = 135, + BIS16rm = 136, + BIS16rn = 137, + BIS16rp = 138, + BIS16rr = 139, + BIS8mc = 140, + BIS8mi = 141, + BIS8mm = 142, + BIS8mn = 143, + BIS8mp = 144, + BIS8mr = 145, + BIS8rc = 146, + BIS8ri = 147, + BIS8rm = 148, + BIS8rn = 149, + BIS8rp = 150, + BIS8rr = 151, + BIT16mc = 152, + BIT16mi = 153, + BIT16mm = 154, + BIT16mr = 155, + BIT16rc = 156, + BIT16ri = 157, + BIT16rm = 158, + BIT16rr = 159, + BIT8mc = 160, + BIT8mi = 161, + BIT8mm = 162, + BIT8mr = 163, + BIT8rc = 164, + BIT8ri = 165, + BIT8rm = 166, + BIT8rr = 167, + Bi = 168, + Bm = 169, + Br = 170, + CALLi = 171, + CALLm = 172, + CALLr = 173, + CMP16mc = 174, + CMP16mi = 175, + CMP16mr = 176, + CMP16rc = 177, + CMP16ri = 178, + CMP16rm = 179, + CMP16rr = 180, + CMP8mc = 181, + CMP8mi = 182, + CMP8mr = 183, + CMP8rc = 184, + CMP8ri = 185, + CMP8rm = 186, + CMP8rr = 187, + DADD16mc = 188, + DADD16mi = 189, + DADD16mm = 190, + DADD16mn = 191, + DADD16mp = 192, + DADD16mr = 193, + DADD16rc = 194, + DADD16ri = 195, + DADD16rm = 196, + DADD16rn = 197, + DADD16rp = 198, + DADD16rr = 199, + DADD8mc = 200, + DADD8mi = 201, + DADD8mm = 202, + DADD8mn = 203, + DADD8mp = 204, + DADD8mr = 205, + DADD8rc = 206, + DADD8ri = 207, + DADD8rm = 208, + DADD8rn = 209, + DADD8rp = 210, + DADD8rr = 211, + JCC = 212, + JMP = 213, + MOV16mc = 214, + MOV16mi = 215, + MOV16mm = 216, + MOV16mr = 217, + MOV16rc = 218, + MOV16ri = 219, + MOV16rm = 220, + MOV16rn = 221, + MOV16rp = 222, + MOV16rr = 223, + MOV8mc = 224, + MOV8mi = 225, + MOV8mm = 226, + MOV8mr = 227, + MOV8rc = 228, + MOV8ri = 229, + MOV8rm = 230, + MOV8rn = 231, + MOV8rp = 232, + MOV8rr = 233, + MOVZX16rm8 = 234, + MOVZX16rr8 = 235, + POP16r = 236, + PUSH16c = 237, + PUSH16i = 238, + PUSH16r = 239, + PUSH8r = 240, + RET = 241, + RETI = 242, + RRA16r = 243, + RRA8r = 244, + RRC16r = 245, + RRC8r = 246, + Rrcl16 = 247, + Rrcl8 = 248, + SEXT16r = 249, + SUB16mc = 250, + SUB16mi = 251, + SUB16mm = 252, + SUB16mn = 253, + SUB16mp = 254, + SUB16mr = 255, + SUB16rc = 256, + SUB16ri = 257, + SUB16rm = 258, + SUB16rn = 259, + SUB16rp = 260, + SUB16rr = 261, + SUB8mc = 262, + SUB8mi = 263, + SUB8mm = 264, + SUB8mn = 265, + SUB8mp = 266, + SUB8mr = 267, + SUB8rc = 268, + SUB8ri = 269, + SUB8rm = 270, + SUB8rn = 271, + SUB8rp = 272, + SUB8rr = 273, + SUBC16mc = 274, + SUBC16mi = 275, + SUBC16mm = 276, + SUBC16mn = 277, + SUBC16mp = 278, + SUBC16mr = 279, + SUBC16rc = 280, + SUBC16ri = 281, + SUBC16rm = 282, + SUBC16rn = 283, + SUBC16rp = 284, + SUBC16rr = 285, + SUBC8mc = 286, + SUBC8mi = 287, + SUBC8mm = 288, + SUBC8mn = 289, + SUBC8mp = 290, + SUBC8mr = 291, + SUBC8rc = 292, + SUBC8ri = 293, + SUBC8rm = 294, + SUBC8rn = 295, + SUBC8rp = 296, + SUBC8rr = 297, + SWPB16r = 298, + Select16 = 299, + Select8 = 300, + Shl16 = 301, + Shl8 = 302, + Sra16 = 303, + Sra8 = 304, + Srl16 = 305, + Srl8 = 306, + XOR16mc = 307, + XOR16mi = 308, + XOR16mm = 309, + XOR16mn = 310, + XOR16mp = 311, + XOR16mr = 312, + XOR16rc = 313, + XOR16ri = 314, + XOR16rm = 315, + XOR16rn = 316, + XOR16rp = 317, + XOR16rr = 318, + XOR8mc = 319, + XOR8mi = 320, + XOR8mm = 321, + XOR8mn = 322, + XOR8mp = 323, + XOR8mr = 324, + XOR8rc = 325, + XOR8ri = 326, + XOR8rm = 327, + XOR8rn = 328, + XOR8rp = 329, + XOR8rr = 330, + ZEXT16r = 331, + INSTRUCTION_LIST_END = 332 }; namespace Sched { @@ -380,31 +396,28 @@ static const MCOperandInfo OperandInfo28[] = { { MSP430::GR8RegClassID, 0, MCOI: static const MCOperandInfo OperandInfo29[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; static const MCOperandInfo OperandInfo30[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; static const MCOperandInfo OperandInfo31[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo32[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo33[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo34[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo35[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo36[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo37[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo38[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo39[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo40[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo41[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo42[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo43[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo44[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo45[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo46[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo47[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; -static const MCOperandInfo OperandInfo48[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo49[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; -static const MCOperandInfo OperandInfo50[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo51[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo52[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; -static const MCOperandInfo OperandInfo53[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; -static const MCOperandInfo OperandInfo54[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo55[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo56[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo32[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo33[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo34[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo35[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo36[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo37[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo38[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo39[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo40[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo41[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo42[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo43[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; +static const MCOperandInfo OperandInfo44[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo45[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; +static const MCOperandInfo OperandInfo46[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo47[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo48[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; +static const MCOperandInfo OperandInfo49[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; +static const MCOperandInfo OperandInfo50[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo51[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo52[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo53[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; extern const MCInstrDesc MSP430Insts[] = { { 0, 1, 1, 0, 0, 0|(1ULL<InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 316); + II->InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 332); } } // end llvm namespace @@ -1087,7 +1134,7 @@ extern const unsigned MSP430InstrNameIndices[]; extern const char MSP430InstrNameData[]; MSP430GenInstrInfo::MSP430GenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode) : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { - InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 316); + InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 332); } } // end llvm namespace #endif // GET_INSTRINFO_CTOR_DTOR diff --git a/llvm/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc b/llvm/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc index a9b093c3..2cc1528b 100644 --- a/llvm/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc +++ b/llvm/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc @@ -114,14 +114,30 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, UINT64_C(61536), // AND8rn UINT64_C(61552), // AND8rp UINT64_C(61504), // AND8rr - UINT64_C(144), // BIC16mm - UINT64_C(128), // BIC16mr - UINT64_C(16), // BIC16rm - UINT64_C(0), // BIC16rr - UINT64_C(208), // BIC8mm - UINT64_C(192), // BIC8mr - UINT64_C(80), // BIC8rm - UINT64_C(64), // BIC8rr + UINT64_C(49280), // BIC16mc + UINT64_C(49328), // BIC16mi + UINT64_C(49296), // BIC16mm + UINT64_C(49312), // BIC16mn + UINT64_C(49328), // BIC16mp + UINT64_C(49280), // BIC16mr + UINT64_C(49152), // BIC16rc + UINT64_C(49200), // BIC16ri + UINT64_C(49168), // BIC16rm + UINT64_C(49184), // BIC16rn + UINT64_C(49200), // BIC16rp + UINT64_C(49152), // BIC16rr + UINT64_C(49344), // BIC8mc + UINT64_C(49392), // BIC8mi + UINT64_C(49360), // BIC8mm + UINT64_C(49376), // BIC8mn + UINT64_C(49392), // BIC8mp + UINT64_C(49344), // BIC8mr + UINT64_C(49216), // BIC8rc + UINT64_C(49264), // BIC8ri + UINT64_C(49232), // BIC8rm + UINT64_C(49248), // BIC8rn + UINT64_C(49264), // BIC8rp + UINT64_C(49216), // BIC8rr UINT64_C(53376), // BIS16mc UINT64_C(53424), // BIS16mi UINT64_C(53392), // BIS16mm @@ -392,6 +408,8 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, case MSP430::ADDC8mc: case MSP430::AND16mc: case MSP430::AND8mc: + case MSP430::BIC16mc: + case MSP430::BIC8mc: case MSP430::BIS16mc: case MSP430::BIS8mc: case MSP430::BIT8mc: @@ -423,6 +441,8 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, case MSP430::ADDC8rc: case MSP430::AND16rc: case MSP430::AND8rc: + case MSP430::BIC16rc: + case MSP430::BIC8rc: case MSP430::BIS16rc: case MSP430::BIS8rc: case MSP430::DADD16rc: @@ -467,6 +487,8 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, case MSP430::ADDC8mi: case MSP430::AND16mi: case MSP430::AND8mi: + case MSP430::BIC16mi: + case MSP430::BIC8mi: case MSP430::BIS16mi: case MSP430::BIS8mi: case MSP430::BIT16mi: @@ -518,6 +540,8 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, case MSP430::ADDC8ri: case MSP430::AND16ri: case MSP430::AND8ri: + case MSP430::BIC16ri: + case MSP430::BIC8ri: case MSP430::BIS16ri: case MSP430::BIS8ri: case MSP430::DADD16ri: @@ -536,17 +560,6 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, Value |= (op & UINT64_C(65535)) << 16; break; } - case MSP430::BIC16rm: - case MSP430::BIC8rm: { - // op: rd - op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); - Value |= op & UINT64_C(15); - // op: src - op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); - Value |= (op & UINT64_C(1048560)) << 12; - Value |= (op & UINT64_C(15)) << 8; - break; - } case MSP430::BIT16rm: case MSP430::BIT8rm: case MSP430::CMP16rm: @@ -569,6 +582,8 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, case MSP430::ADDC8rm: case MSP430::AND16rm: case MSP430::AND8rm: + case MSP430::BIC16rm: + case MSP430::BIC8rm: case MSP430::BIS16rm: case MSP430::BIS8rm: case MSP430::DADD16rm: @@ -594,16 +609,6 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, Value |= (op & UINT64_C(15)) << 8; break; } - case MSP430::BIC16rr: - case MSP430::BIC8rr: { - // op: rs - op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); - Value |= (op & UINT64_C(15)) << 8; - // op: rd - op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); - Value |= op & UINT64_C(15); - break; - } case MSP430::CALLr: case MSP430::PUSH16r: case MSP430::PUSH8r: { @@ -659,6 +664,12 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, case MSP430::AND8mn: case MSP430::AND8mp: case MSP430::AND8mr: + case MSP430::BIC16mn: + case MSP430::BIC16mp: + case MSP430::BIC16mr: + case MSP430::BIC8mn: + case MSP430::BIC8mp: + case MSP430::BIC8mr: case MSP430::BIS16mn: case MSP430::BIS16mp: case MSP430::BIS16mr: @@ -716,6 +727,10 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, case MSP430::AND16rr: case MSP430::AND8rn: case MSP430::AND8rr: + case MSP430::BIC16rn: + case MSP430::BIC16rr: + case MSP430::BIC8rn: + case MSP430::BIC8rr: case MSP430::BIS16rn: case MSP430::BIS16rr: case MSP430::BIS8rn: @@ -752,6 +767,8 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, case MSP430::ADDC8rp: case MSP430::AND16rp: case MSP430::AND8rp: + case MSP430::BIC16rp: + case MSP430::BIC8rp: case MSP430::BIS16rp: case MSP430::BIS8rp: case MSP430::DADD16rp: @@ -770,17 +787,6 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, Value |= op & UINT64_C(15); break; } - case MSP430::BIC16mr: - case MSP430::BIC8mr: { - // op: rs - op = getMemOpValue(MI, 0, Fixups, STI); - Value |= (op & UINT64_C(15)) << 8; - // op: dst - op = getMemOpValue(MI, 0, Fixups, STI); - Value |= (op & UINT64_C(1048560)) << 12; - Value |= op & UINT64_C(15); - break; - } case MSP430::Bm: { // op: src op = getMemOpValue(MI, 0, Fixups, STI); From 5f2f2caec87f7eeccbd507aed055562d5b02ae43 Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Thu, 20 Dec 2018 16:47:29 -0500 Subject: [PATCH 04/14] Fix bindings for EVM and MSP430 --- bindings/Makefile | 1 + bindings/const_generator.py | 55 +++++++------ .../Keystone.Net/Constants/ARM64Constants.cs | 2 +- .../Keystone.Net/Constants/ARMConstants.cs | 2 +- .../Keystone.Net/Constants/EVMConstants.cs | 10 +++ .../Constants/HexagonConstants.cs | 2 +- .../Constants/KeystoneConstants.cs | 80 ++++++++++--------- .../Keystone.Net/Constants/MSP430Constants.cs | 10 +++ .../Keystone.Net/Constants/MipsConstants.cs | 2 +- .../Keystone.Net/Constants/PPCConstants.cs | 2 +- .../Keystone.Net/Constants/SPARCConstants.cs | 2 +- .../Constants/SystemZConstants.cs | 2 +- .../Keystone.Net/Constants/X86Constants.cs | 2 +- bindings/go/keystone/keystone_const.go | 3 +- bindings/go/keystone/msp430_const.go | 9 +++ bindings/haskell/keystone.cabal | 1 + bindings/haskell/samples/Sample.hs | 3 + bindings/haskell/src/Keystone/CPU/Msp430.chs | 25 ++++++ bindings/java/pom.xml | 2 +- .../java/keystone/KeystoneArchitecture.java | 5 ++ bindings/masm/keystone_x64.inc | 4 +- bindings/masm/keystone_x86.inc | 4 +- bindings/masm/masmApiConst.api.txt | 4 +- bindings/nodejs/consts/index.js | 2 +- bindings/nodejs/consts/keystone.js | 3 +- bindings/nodejs/consts/msp430.js | 4 + bindings/ocaml/ffi_types.ml | 44 ++++++++++ bindings/ocaml/keystone.mli | 2 + bindings/ocaml/test_bindings.ml | 2 + .../powershell/Keystone/Const/keystone_h.cs | 3 +- bindings/powershell/Keystone/Keystone.psm1 | 2 + bindings/python/README.pypi-src | 2 +- bindings/python/keystone/__init__.py | 3 +- bindings/python/keystone/keystone.py | 12 +-- bindings/python/keystone/keystone_const.py | 3 +- bindings/python/keystone/msp430_const.py | 4 + bindings/python/sample.py | 3 + .../lib/keystone/keystone_const.rb | 3 +- .../keystone_gem/lib/keystone/msp430_const.rb | 7 ++ bindings/ruby/sample.rb | 3 + bindings/rust/keystone-sys/src/arm64_const.rs | 11 +++ bindings/rust/keystone-sys/src/arm_const.rs | 11 +++ bindings/rust/keystone-sys/src/evm_const.rs | 11 +++ .../rust/keystone-sys/src/hexagon_const.rs | 11 +++ .../rust/keystone-sys/src/keystone_const.rs | 3 +- bindings/rust/keystone-sys/src/mips_const.rs | 11 +++ .../rust/keystone-sys/src/msp430_const.rs | 11 +++ bindings/rust/keystone-sys/src/ppc_const.rs | 11 +++ bindings/rust/keystone-sys/src/sparc_const.rs | 11 +++ .../rust/keystone-sys/src/systemz_const.rs | 11 +++ bindings/rust/keystone-sys/src/x86_const.rs | 11 +++ bindings/vb6/Form1.frm | 3 + bindings/vb6/mKeystone.bas | 4 + samples/sample.c | 6 +- 54 files changed, 366 insertions(+), 94 deletions(-) create mode 100644 bindings/csharp/Keystone.Net/Constants/EVMConstants.cs create mode 100644 bindings/csharp/Keystone.Net/Constants/MSP430Constants.cs create mode 100644 bindings/go/keystone/msp430_const.go create mode 100644 bindings/haskell/src/Keystone/CPU/Msp430.chs create mode 100644 bindings/nodejs/consts/msp430.js create mode 100644 bindings/python/keystone/msp430_const.py create mode 100644 bindings/ruby/keystone_gem/lib/keystone/msp430_const.rb create mode 100644 bindings/rust/keystone-sys/src/arm64_const.rs create mode 100644 bindings/rust/keystone-sys/src/arm_const.rs create mode 100644 bindings/rust/keystone-sys/src/evm_const.rs create mode 100644 bindings/rust/keystone-sys/src/hexagon_const.rs create mode 100644 bindings/rust/keystone-sys/src/mips_const.rs create mode 100644 bindings/rust/keystone-sys/src/msp430_const.rs create mode 100644 bindings/rust/keystone-sys/src/ppc_const.rs create mode 100644 bindings/rust/keystone-sys/src/sparc_const.rs create mode 100644 bindings/rust/keystone-sys/src/systemz_const.rs create mode 100644 bindings/rust/keystone-sys/src/x86_const.rs diff --git a/bindings/Makefile b/bindings/Makefile index f082bce5..ec88cfab 100644 --- a/bindings/Makefile +++ b/bindings/Makefile @@ -21,6 +21,7 @@ all: python const_generator.py go cd ruby && $(MAKE) gen_const python const_generator.py powershell + python const_generator.py csharp samples: expected python diff --git a/bindings/const_generator.py b/bindings/const_generator.py index db69d55a..7f5b5113 100644 --- a/bindings/const_generator.py +++ b/bindings/const_generator.py @@ -8,7 +8,7 @@ # NOTE: this reflects the value of KS_ERR_ASM_xxx in keystone.h ks_err_val = { 'KS_ERR_ASM': '128', 'KS_ERR_ASM_ARCH': '512' } -include = [ 'arm.h', 'arm64.h', 'mips.h', 'x86.h', 'sparc.h', 'ppc.h', 'systemz.h', 'hexagon.h', 'evm.h', 'keystone.h' ] +include = [ 'arm.h', 'arm64.h', 'mips.h', 'x86.h', 'sparc.h', 'ppc.h', 'systemz.h', 'hexagon.h', 'evm.h', 'msp430.h', 'keystone.h' ] def CamelCase(s): # return re.sub(r'(\w)+\_?', lambda m:m.group(0).capitalize(), s) @@ -35,15 +35,16 @@ def CamelCase(s): 'header': "#![allow(non_camel_case_types)]\n// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.rs]\nuse libc;\n", 'footer': "", # prefixes for constant filenames of all archs - case sensitive - 'arm.h': 'keystone', - 'arm64.h': 'keystone', - 'mips.h': 'keystone', - 'x86.h': 'keystone', - 'sparc.h': 'keystone', - 'systemz.h': 'keystone', - 'ppc.h': 'keystone', - 'hexagon.h': 'keystone', - 'evm.h': 'keystone', + 'arm.h': 'arm', + 'arm64.h': 'arm64', + 'mips.h': 'mips', + 'msp430.h': 'msp430', + 'x86.h': 'x86', + 'sparc.h': 'sparc', + 'systemz.h': 'systemz', + 'ppc.h': 'ppc', + 'hexagon.h': 'hexagon', + 'evm.h': 'evm', 'keystone.h': 'keystone', 'comment_open': '/*', 'comment_close': '*/', @@ -110,6 +111,7 @@ def CamelCase(s): 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', + 'msp430.h': 'msp430', 'x86.h': 'x86', 'sparc.h': 'sparc', 'systemz.h': 'systemz', @@ -172,6 +174,7 @@ def CamelCase(s): 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', + 'msp430.h': 'msp430', 'x86.h': 'x86', 'sparc.h': 'sparc', 'systemz.h': 'systemz', @@ -197,6 +200,7 @@ def CamelCase(s): 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', + 'msp430.h': 'msp430', 'x86.h': 'x86', 'sparc.h': 'sparc', 'systemz.h': 'systemz', @@ -222,6 +226,7 @@ def CamelCase(s): 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', + 'msp430.h': 'msp430', 'x86.h': 'x86', 'sparc.h': 'sparc', 'systemz.h': 'systemz', @@ -240,34 +245,34 @@ def CamelCase(s): ] }, 'csharp': { - 'header': "// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%sConstants.cs]\nnamespace KeystoneNET\n{", + 'header': "// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%sConstants.cs]\nnamespace Keystone\n{", 'footer': "}", - 'out_file': './csharp/KeystoneNET/KeystoneNET/Constants/%sConstants.cs', + 'out_file': './csharp/Keystone.NET/Constants/%sConstants.cs', # prefixes for constant filenames of all archs - case sensitive - 'keystone.h': 'keystone', - 'arm.h': 'arm', - 'arm64.h': 'arm64', - 'mips.h': 'mips', - 'x86.h': 'x86', - 'sparc.h': 'sparc', - 'systemz.h': 'systemz', - 'ppc.h': 'ppc', - 'hexagon.h': 'hexagon', - 'evm.h': 'evm', - 'keystone.h': 'keystone', + 'keystone.h': 'Keystone', + 'arm.h': 'ARM', + 'arm64.h': 'ARM64', + 'mips.h': 'Mips', + 'msp430.h': 'MSP430', + 'x86.h': 'X86', + 'sparc.h': 'SPARC', + 'systemz.h': 'SystemZ', + 'ppc.h': 'PPC', + 'hexagon.h': 'Hexagon', + 'evm.h': 'EVM', 'comment_open': '//', 'comment_close': '', 'rules': [ { 'regex': r'(ARCH)_.*', - 'pre': '\n\tpublic enum KeystoneArchitecture : int\n\t{{\n', + 'pre': '\n\tpublic enum Architecture : int\n\t{{\n', 'post': '\t}', 'line_format': '\t\tKS_{0} = {1},\n', 'fn': (lambda x: x), }, { 'regex': r'(MODE)_.*', - 'pre': '\n\tpublic enum KeystoneMode : uint\n\t{{\n', + 'pre': '\n\tpublic enum Mode : uint\n\t{{\n', 'post': '\t}', 'line_format': '\t\tKS_{0} = {1},\n', 'fn': (lambda x: x), diff --git a/bindings/csharp/Keystone.Net/Constants/ARM64Constants.cs b/bindings/csharp/Keystone.Net/Constants/ARM64Constants.cs index 33eb5458..df6cf463 100644 --- a/bindings/csharp/Keystone.Net/Constants/ARM64Constants.cs +++ b/bindings/csharp/Keystone.Net/Constants/ARM64Constants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64Constants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ARM64Constants.cs] namespace Keystone { public enum Arm64Error : short diff --git a/bindings/csharp/Keystone.Net/Constants/ARMConstants.cs b/bindings/csharp/Keystone.Net/Constants/ARMConstants.cs index f8d0c273..60b44151 100644 --- a/bindings/csharp/Keystone.Net/Constants/ARMConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/ARMConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [armConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ARMConstants.cs] namespace Keystone { public enum ArmError : short diff --git a/bindings/csharp/Keystone.Net/Constants/EVMConstants.cs b/bindings/csharp/Keystone.Net/Constants/EVMConstants.cs new file mode 100644 index 00000000..46d394ef --- /dev/null +++ b/bindings/csharp/Keystone.Net/Constants/EVMConstants.cs @@ -0,0 +1,10 @@ +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [EVMConstants.cs] +namespace Keystone +{ + public enum EvmError : short + { + KS_ERR_ASM_EVM_INVALIDOPERAND = 512, + KS_ERR_ASM_EVM_MISSINGFEATURE = 513, + KS_ERR_ASM_EVM_MNEMONICFAIL = 514, + } +} \ No newline at end of file diff --git a/bindings/csharp/Keystone.Net/Constants/HexagonConstants.cs b/bindings/csharp/Keystone.Net/Constants/HexagonConstants.cs index bfb0da9f..673a66f4 100644 --- a/bindings/csharp/Keystone.Net/Constants/HexagonConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/HexagonConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hexagonConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [HexagonConstants.cs] namespace Keystone { public enum HexagonError : short diff --git a/bindings/csharp/Keystone.Net/Constants/KeystoneConstants.cs b/bindings/csharp/Keystone.Net/Constants/KeystoneConstants.cs index 124e5247..04cd530a 100644 --- a/bindings/csharp/Keystone.Net/Constants/KeystoneConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/KeystoneConstants.cs @@ -3,38 +3,40 @@ namespace Keystone { public enum Architecture : int { - ARM = 1, - ARM64 = 2, - MIPS = 3, - X86 = 4, - PPC = 5, - SPARC = 6, - SYSTEMZ = 7, - HEXAGON = 8, - MAX = 9, + KS_ARCH_ARM = 1, + KS_ARCH_ARM64 = 2, + KS_ARCH_MIPS = 3, + KS_ARCH_X86 = 4, + KS_ARCH_PPC = 5, + KS_ARCH_SPARC = 6, + KS_ARCH_SYSTEMZ = 7, + KS_ARCH_HEXAGON = 8, + KS_ARCH_EVM = 9, + KS_ARCH_MSP430 = 10, + KS_ARCH_MAX = 11, } public enum Mode : uint { - LITTLE_ENDIAN = 0, - BIG_ENDIAN = 1073741824, - ARM = 1, - THUMB = 16, - V8 = 64, - MICRO = 16, - MIPS3 = 32, - MIPS32R6 = 64, - MIPS32 = 4, - MIPS64 = 8, - X16 = 2, - X32 = 4, - X64 = 8, - PPC32 = 4, - PPC64 = 8, - QPX = 16, - SPARC32 = 4, - SPARC64 = 8, - V9 = 16, + KS_MODE_LITTLE_ENDIAN = 0, + KS_MODE_BIG_ENDIAN = 1073741824, + KS_MODE_ARM = 1, + KS_MODE_THUMB = 16, + KS_MODE_V8 = 64, + KS_MODE_MICRO = 16, + KS_MODE_MIPS3 = 32, + KS_MODE_MIPS32R6 = 64, + KS_MODE_MIPS32 = 4, + KS_MODE_MIPS64 = 8, + KS_MODE_16 = 2, + KS_MODE_32 = 4, + KS_MODE_64 = 8, + KS_MODE_PPC32 = 4, + KS_MODE_PPC64 = 8, + KS_MODE_QPX = 16, + KS_MODE_SPARC32 = 4, + KS_MODE_SPARC64 = 8, + KS_MODE_V9 = 16, } public enum KeystoneError : short @@ -86,22 +88,22 @@ public enum KeystoneError : short KS_ERR_ASM_FRAGMENT_INVALID = 163, KS_ERR_ASM_INVALIDOPERAND = 512, KS_ERR_ASM_MISSINGFEATURE = 513, - KS_ERR_ASM_MNEMONICFAIL = 514 + KS_ERR_ASM_MNEMONICFAIL = 514, } - public enum OptionType : int + public enum KeystoneOptionType : short { - SYNTAX = 1, - SYM_RESOLVER = 2, + KS_OPT_SYNTAX = 1, + KS_OPT_SYM_RESOLVER = 2, } - public enum OptionValue : short + public enum KeystoneOptionValue : short { - SYNTAX_INTEL = 1, - SYNTAX_ATT = 2, - SYNTAX_NASM = 4, - SYNTAX_MASM = 8, - SYNTAX_GAS = 16, - SYNTAX_RADIX16 = 32 + KS_OPT_SYNTAX_INTEL = 1, + KS_OPT_SYNTAX_ATT = 2, + KS_OPT_SYNTAX_NASM = 4, + KS_OPT_SYNTAX_MASM = 8, + KS_OPT_SYNTAX_GAS = 16, + KS_OPT_SYNTAX_RADIX16 = 32, } } \ No newline at end of file diff --git a/bindings/csharp/Keystone.Net/Constants/MSP430Constants.cs b/bindings/csharp/Keystone.Net/Constants/MSP430Constants.cs new file mode 100644 index 00000000..e4e8d996 --- /dev/null +++ b/bindings/csharp/Keystone.Net/Constants/MSP430Constants.cs @@ -0,0 +1,10 @@ +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [MSP430Constants.cs] +namespace Keystone +{ + public enum Msp430Error : short + { + KS_ERR_ASM_MSP430_INVALIDOPERAND = 512, + KS_ERR_ASM_MSP430_MISSINGFEATURE = 513, + KS_ERR_ASM_MSP430_MNEMONICFAIL = 514, + } +} \ No newline at end of file diff --git a/bindings/csharp/Keystone.Net/Constants/MipsConstants.cs b/bindings/csharp/Keystone.Net/Constants/MipsConstants.cs index 99be03dc..7a6a2b78 100644 --- a/bindings/csharp/Keystone.Net/Constants/MipsConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/MipsConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mipsConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [MipsConstants.cs] namespace Keystone { public enum MipsError : short diff --git a/bindings/csharp/Keystone.Net/Constants/PPCConstants.cs b/bindings/csharp/Keystone.Net/Constants/PPCConstants.cs index 601585a7..4256560a 100644 --- a/bindings/csharp/Keystone.Net/Constants/PPCConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/PPCConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppcConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [PPCConstants.cs] namespace Keystone { public enum PpcError : short diff --git a/bindings/csharp/Keystone.Net/Constants/SPARCConstants.cs b/bindings/csharp/Keystone.Net/Constants/SPARCConstants.cs index 6de93d20..4b77d77c 100644 --- a/bindings/csharp/Keystone.Net/Constants/SPARCConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/SPARCConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparcConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [SPARCConstants.cs] namespace Keystone { public enum SparcError : short diff --git a/bindings/csharp/Keystone.Net/Constants/SystemZConstants.cs b/bindings/csharp/Keystone.Net/Constants/SystemZConstants.cs index d2b61320..3bb58254 100644 --- a/bindings/csharp/Keystone.Net/Constants/SystemZConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/SystemZConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [systemzConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [SystemZConstants.cs] namespace Keystone { public enum SystemzError : short diff --git a/bindings/csharp/Keystone.Net/Constants/X86Constants.cs b/bindings/csharp/Keystone.Net/Constants/X86Constants.cs index 79743f7d..7d33e988 100644 --- a/bindings/csharp/Keystone.Net/Constants/X86Constants.cs +++ b/bindings/csharp/Keystone.Net/Constants/X86Constants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86Constants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [X86Constants.cs] namespace Keystone { public enum X86Error : short diff --git a/bindings/go/keystone/keystone_const.go b/bindings/go/keystone/keystone_const.go index f78837c0..0e07b785 100644 --- a/bindings/go/keystone/keystone_const.go +++ b/bindings/go/keystone/keystone_const.go @@ -38,7 +38,8 @@ const ( ARCH_SYSTEMZ Architecture = 7 ARCH_HEXAGON Architecture = 8 ARCH_EVM Architecture = 9 - ARCH_MAX Architecture = 10 + ARCH_MSP430 Architecture = 10 + ARCH_MAX Architecture = 11 ) const ( diff --git a/bindings/go/keystone/msp430_const.go b/bindings/go/keystone/msp430_const.go new file mode 100644 index 00000000..986b45e1 --- /dev/null +++ b/bindings/go/keystone/msp430_const.go @@ -0,0 +1,9 @@ +package keystone +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.go] + +const ( + ERR_ASM_MSP430_INVALIDOPERAND Error = 512 + ERR_ASM_MSP430_MISSINGFEATURE Error = 513 + ERR_ASM_MSP430_MNEMONICFAIL Error = 514 +) + diff --git a/bindings/haskell/keystone.cabal b/bindings/haskell/keystone.cabal index e8b16037..309873ff 100644 --- a/bindings/haskell/keystone.cabal +++ b/bindings/haskell/keystone.cabal @@ -19,6 +19,7 @@ library Keystone.CPU.Arm Keystone.CPU.Hexagon Keystone.CPU.Mips + Keystone.CPU.Msp430 Keystone.CPU.Ppc Keystone.CPU.Sparc Keystone.CPU.SystemZ diff --git a/bindings/haskell/samples/Sample.hs b/bindings/haskell/samples/Sample.hs index dba62ce4..f17a87a5 100644 --- a/bindings/haskell/samples/Sample.hs +++ b/bindings/haskell/samples/Sample.hs @@ -72,3 +72,6 @@ main = do -- SystemZ testKs ArchSystemz [ModeBigEndian] ["a %r0, 4095(%r15,%r1)"] Nothing + + -- MSP430 + testKs ArchMsp430 [ModeLittleEndian] ["and r12, r13"] Nothing diff --git a/bindings/haskell/src/Keystone/CPU/Msp430.chs b/bindings/haskell/src/Keystone/CPU/Msp430.chs new file mode 100644 index 00000000..00bb021a --- /dev/null +++ b/bindings/haskell/src/Keystone/CPU/Msp430.chs @@ -0,0 +1,25 @@ +{-# LANGUAGE ForeignFunctionInterface #-} + +{-| +Module : Keystone.CPU.Msp430 +Description : Definitions for the Msp430 architecture. +Copyright : (C) Trey Keown, 2018 +License : GPL-2 + +Definitions for the Msp430 architecture. +-} +module Keystone.CPU.Msp430 + ( + Error(..) + ) where + +{# context lib = "keystone" #} + +#include + +-- | Msp430 errors. +{# enum ks_err_asm_msp430 as Error + { underscoreToCase } + with prefix = "KS_ERR_ASM_MSP430_" + deriving (Show, Eq, Bounded) +#} diff --git a/bindings/java/pom.xml b/bindings/java/pom.xml index 65949b23..9a76b755 100644 --- a/bindings/java/pom.xml +++ b/bindings/java/pom.xml @@ -16,7 +16,7 @@ 0.9.1-0 Keystone Java bindings - Keystone assembler framework: Core (Arm, Arm64, Hexagon, Mips, PowerPC, Sparc, SystemZ and X86) orm. + Keystone assembler framework: Core (Arm, Arm64, Hexagon, Mips, MSP430, PowerPC, Sparc, SystemZ and X86) orm. https://github.com/keystone-engine/keystone/tree/master/bindings/java diff --git a/bindings/java/src/main/java/keystone/KeystoneArchitecture.java b/bindings/java/src/main/java/keystone/KeystoneArchitecture.java index fc30ca7e..403b4460 100644 --- a/bindings/java/src/main/java/keystone/KeystoneArchitecture.java +++ b/bindings/java/src/main/java/keystone/KeystoneArchitecture.java @@ -61,6 +61,11 @@ public enum KeystoneArchitecture implements JnaEnum { */ Evm(9), + /** + * Msp430 architecture + */ + Msp430(10), + Max(10); /** diff --git a/bindings/masm/keystone_x64.inc b/bindings/masm/keystone_x64.inc index eb4b7cdb..40eadce3 100644 --- a/bindings/masm/keystone_x64.inc +++ b/bindings/masm/keystone_x64.inc @@ -32,7 +32,9 @@ KS_ARCH_PPC EQU 5 ; PowerPC architecture (currently un KS_ARCH_SPARC EQU 6 ; Sparc architecture KS_ARCH_SYSTEMZ EQU 7 ; SystemZ architecture (S390X) KS_ARCH_HEXAGON EQU 8 ; Hexagon architecture -KS_ARCH_MAX EQU 9 ; +KS_ARCH_EVM EQU 9 ; EVM architecture +KS_ARCH_MSP430 EQU 10 ; MSP430 architecture +KS_ARCH_MAX EQU 11 ; ; Mode type ks_mode KS_MODE_LITTLE_ENDIAN EQU 0 ; little-endian mode (default mode) diff --git a/bindings/masm/keystone_x86.inc b/bindings/masm/keystone_x86.inc index 8d3a33b8..f99fb5c3 100644 --- a/bindings/masm/keystone_x86.inc +++ b/bindings/masm/keystone_x86.inc @@ -32,7 +32,9 @@ KS_ARCH_PPC EQU 5 ; PowerPC architecture (currently un KS_ARCH_SPARC EQU 6 ; Sparc architecture KS_ARCH_SYSTEMZ EQU 7 ; SystemZ architecture (S390X) KS_ARCH_HEXAGON EQU 8 ; Hexagon architecture -KS_ARCH_MAX EQU 9 ; +KS_ARCH_EVM EQU 9 ; EVM architecture +KS_ARCH_MSP430 EQU 10 ; MSP430 architecture +KS_ARCH_MAX EQU 11 ; ; Mode type ks_mode KS_MODE_LITTLE_ENDIAN EQU 0 ; little-endian mode (default mode) diff --git a/bindings/masm/masmApiConst.api.txt b/bindings/masm/masmApiConst.api.txt index 90399a92..cb635164 100644 --- a/bindings/masm/masmApiConst.api.txt +++ b/bindings/masm/masmApiConst.api.txt @@ -6,8 +6,8 @@ ;----------------------------------------------------------------------------------------------------- 1ks_version,NULL,KS_VERSION_MAJOR 2ks_version,NULL,KS_VERSION_MINOR -1ks_arch_supported,KS_ARCH_ARM,KS_ARCH_ARM64,KS_ARCH_MIPS,KS_ARCH_X86,KS_ARCH_PPC,KS_ARCH_SPARC,KS_ARCH_SYSTEMZ,KS_ARCH_HEXAGON,KS_ARCH_MAX -1ks_open,KS_ARCH_ARM,KS_ARCH_ARM64,KS_ARCH_MIPS,KS_ARCH_X86,KS_ARCH_PPC,KS_ARCH_SPARC,KS_ARCH_SYSTEMZ,KS_ARCH_HEXAGON,KS_ARCH_MAX +1ks_arch_supported,KS_ARCH_ARM,KS_ARCH_ARM64,KS_ARCH_MIPS,KS_ARCH_X86,KS_ARCH_PPC,KS_ARCH_SPARC,KS_ARCH_SYSTEMZ,KS_ARCH_HEXAGON,KS_ARCH_EVM,KS_ARCH_MSP430,KS_ARCH_MAX +1ks_open,KS_ARCH_ARM,KS_ARCH_ARM64,KS_ARCH_MIPS,KS_ARCH_X86,KS_ARCH_PPC,KS_ARCH_SPARC,KS_ARCH_SYSTEMZ,KS_ARCH_HEXAGON,KS_ARCH_EVM,KS_ARCH_MSP430,KS_ARCH_MAX 2ks_open,KS_MODE_LITTLE_ENDIAN,KS_MODE_BIG_ENDIAN,KS_MODE_ARM,KS_MODE_THUMB,KS_MODE_V8,KS_MODE_MICRO,KS_MODE_MIPS3,KS_MODE_MIPS32R6,KS_MODE_MIPS32,KS_MODE_MIPS64,KS_MODE_16,KS_MODE_32,KS_MODE_64,KS_MODE_PPC32,KS_MODE_PPC64,KS_MODE_QPX,KS_MODE_SPARC32,KS_MODE_SPARC64,KS_MODE_V9 1ks_strerror,KS_ERR_OK,KS_ERR_NOMEM,KS_ERR_ARCH,KS_ERR_HANDLE,KS_ERR_MODE,KS_ERR_VERSION,KS_ERR_OPT_INVALID,KS_ERR_ASM_EXPR_TOKEN,KS_ERR_ASM_DIRECTIVE_VALUE_RANGE,KS_ERR_ASM_DIRECTIVE_ID,KS_ERR_ASM_DIRECTIVE_TOKEN,KS_ERR_ASM_DIRECTIVE_STR,KS_ERR_ASM_DIRECTIVE_COMMA,KS_ERR_ASM_DIRECTIVE_RELOC_NAME,KS_ERR_ASM_DIRECTIVE_RELOC_TOKEN,KS_ERR_ASM_DIRECTIVE_FPOINT,KS_ERR_ASM_DIRECTIVE_UNKNOWN,KS_ERR_ASM_DIRECTIVE_EQU,KS_ERR_ASM_DIRECTIVE_INVALID,KS_ERR_ASM_VARIANT_INVALID,KS_ERR_ASM_EXPR_BRACKET,KS_ERR_ASM_SYMBOL_MODIFIER,KS_ERR_ASM_SYMBOL_REDEFINED,KS_ERR_ASM_SYMBOL_MISSING,KS_ERR_ASM_RPAREN,KS_ERR_ASM_STAT_TOKEN,KS_ERR_ASM_UNSUPPORTED,KS_ERR_ASM_MACRO_TOKEN,KS_ERR_ASM_MACRO_PAREN,KS_ERR_ASM_MACRO_EQU,KS_ERR_ASM_MACRO_ARGS,KS_ERR_ASM_MACRO_LEVELS_EXCEED,KS_ERR_ASM_MACRO_STR,KS_ERR_ASM_MACRO_INVALID,KS_ERR_ASM_ESC_BACKSLASH,KS_ERR_ASM_ESC_OCTAL,KS_ERR_ASM_ESC_SEQUENCE,KS_ERR_ASM_ESC_STR,KS_ERR_ASM_TOKEN_INVALID,KS_ERR_ASM_INSN_UNSUPPORTED,KS_ERR_ASM_FIXUP_INVALID,KS_ERR_ASM_LABEL_INVALID,KS_ERR_ASM_FRAGMENT_INVALID,KS_ERR_ASM_INVALIDOPERAND,KS_ERR_ASM_MISSINGFEATURE,KS_ERR_ASM_MNEMONICFAIL,KS_ERR_ASM_X86_INVALIDOPERAND,KS_ERR_ASM_X86_MISSINGFEATURE,KS_ERR_ASM_X86_MNEMONICFAIL,KS_ERR_ASM,KS_ERR_ASM_ARCH 2ks_option,KS_OPT_SYNTAX,KS_OPT_SYM_RESOLVER diff --git a/bindings/nodejs/consts/index.js b/bindings/nodejs/consts/index.js index df58d5ca..737f5743 100644 --- a/bindings/nodejs/consts/index.js +++ b/bindings/nodejs/consts/index.js @@ -1,5 +1,5 @@ var extend = require('util')._extend, - archs = ['arm64', 'arm', 'hexagon', 'mips', 'ppc', 'sparc', 'systemz', 'x86'], + archs = ['arm64', 'arm', 'hexagon', 'mips', 'ppc', 'sparc', 'systemz', 'x86', 'evm', 'msp430'], i module.exports = require('./keystone') diff --git a/bindings/nodejs/consts/keystone.js b/bindings/nodejs/consts/keystone.js index a38e346b..bd210e01 100644 --- a/bindings/nodejs/consts/keystone.js +++ b/bindings/nodejs/consts/keystone.js @@ -13,7 +13,8 @@ module.exports.ARCH_SPARC = 6 module.exports.ARCH_SYSTEMZ = 7 module.exports.ARCH_HEXAGON = 8 module.exports.ARCH_EVM = 9 -module.exports.ARCH_MAX = 10 +module.exports.ARCH_MSP430 = 10 +module.exports.ARCH_MAX = 11 module.exports.MODE_LITTLE_ENDIAN = 0 module.exports.MODE_BIG_ENDIAN = 1073741824 module.exports.MODE_ARM = 1 diff --git a/bindings/nodejs/consts/msp430.js b/bindings/nodejs/consts/msp430.js new file mode 100644 index 00000000..87592e87 --- /dev/null +++ b/bindings/nodejs/consts/msp430.js @@ -0,0 +1,4 @@ +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.js] +module.exports.ERR_ASM_MSP430_INVALIDOPERAND = 512 +module.exports.ERR_ASM_MSP430_MISSINGFEATURE = 513 +module.exports.ERR_ASM_MSP430_MNEMONICFAIL = 514 diff --git a/bindings/ocaml/ffi_types.ml b/bindings/ocaml/ffi_types.ml index 82e13f9a..917d6cec 100644 --- a/bindings/ocaml/ffi_types.ml +++ b/bindings/ocaml/ffi_types.ml @@ -24,6 +24,8 @@ module Types (F: Cstubs.Types.TYPE) = | KS_ARCH_SPARC | KS_ARCH_SYSTEMZ | KS_ARCH_HEXAGON + | KS_ARCH_EVM + | KS_ARCH_MSP430 | KS_ARCH_MAX @@ -221,6 +223,8 @@ module Types (F: Cstubs.Types.TYPE) = let ks_arch_sparc = constant "KS_ARCH_SPARC" int64_t let ks_arch_systemz = constant "KS_ARCH_SYSTEMZ" int64_t let ks_arch_hexagon = constant "KS_ARCH_HEXAGON" int64_t + let ks_arch_evm = constant "KS_ARCH_EVM" int64_t + let ks_arch_msp430 = constant "KS_ARCH_MSP430" int64_t let ks_arch_max = constant "KS_ARCH_MAX" int64_t let ks_arch = enum "ks_arch" [ @@ -232,6 +236,8 @@ module Types (F: Cstubs.Types.TYPE) = KS_ARCH_SPARC, ks_arch_sparc; KS_ARCH_SYSTEMZ, ks_arch_systemz; KS_ARCH_HEXAGON, ks_arch_hexagon; + KS_ARCH_EVM, ks_arch_evm; + KS_ARCH_MSP430, ks_arch_msp430; KS_ARCH_MAX, ks_arch_max ] @@ -524,6 +530,44 @@ module Types (F: Cstubs.Types.TYPE) = ] end + module EVM = + struct + type ks_err_asm_evm = + | KS_ERR_ASM_EVM_INVALIDOPERAND + | KS_ERR_ASM_EVM_MISSINGFEATURE + | KS_ERR_ASM_EVM_MNEMONICFAIL + + + let ks_err_asm_evm_invalidoperand = constant "KS_ERR_ASM_EVM_INVALIDOPERAND" int64_t + let ks_err_asm_evm_missingfeature = constant "KS_ERR_ASM_EVM_MISSINGFEATURE" int64_t + let ks_err_asm_evm_mnemonicfail = constant "KS_ERR_ASM_EVM_MNEMONICFAIL" int64_t + + let ks_err_asm_evm = enum "ks_err_asm_evm" [ + KS_ERR_ASM_EVM_INVALIDOPERAND, ks_err_asm_evm_invalidoperand; + KS_ERR_ASM_EVM_MISSINGFEATURE, ks_err_asm_evm_missingfeature; + KS_ERR_ASM_EVM_MNEMONICFAIL, ks_err_asm_evm_mnemonicfail; + ] + end + + module MSP430 = + struct + type ks_err_asm_msp430 = + | KS_ERR_ASM_MSP430_INVALIDOPERAND + | KS_ERR_ASM_MSP430_MISSINGFEATURE + | KS_ERR_ASM_MSP430_MNEMONICFAIL + + + let ks_err_asm_msp430_invalidoperand = constant "KS_ERR_ASM_MSP430_INVALIDOPERAND" int64_t + let ks_err_asm_msp430_missingfeature = constant "KS_ERR_ASM_MSP430_MISSINGFEATURE" int64_t + let ks_err_asm_msp430_mnemonicfail = constant "KS_ERR_ASM_MSP430_MNEMONICFAIL" int64_t + + let ks_err_asm_msp430 = enum "ks_err_asm_msp430" [ + KS_ERR_ASM_MSP430_INVALIDOPERAND, ks_err_asm_msp430_invalidoperand; + KS_ERR_ASM_MSP430_MISSINGFEATURE, ks_err_asm_msp430_missingfeature; + KS_ERR_ASM_MSP430_MNEMONICFAIL, ks_err_asm_msp430_mnemonicfail; + ] + end + diff --git a/bindings/ocaml/keystone.mli b/bindings/ocaml/keystone.mli index b4991fbd..9bc9f7a8 100644 --- a/bindings/ocaml/keystone.mli +++ b/bindings/ocaml/keystone.mli @@ -17,6 +17,8 @@ module Types : sig | KS_ARCH_SPARC | KS_ARCH_SYSTEMZ | KS_ARCH_HEXAGON + | KS_ARCH_EVM + | KS_ARCH_MSP430 | KS_ARCH_MAX (** Keystone error types. Please see keystone.h for a full description. *) diff --git a/bindings/ocaml/test_bindings.ml b/bindings/ocaml/test_bindings.ml index e4bdd2b9..f57041ab 100644 --- a/bindings/ocaml/test_bindings.ml +++ b/bindings/ocaml/test_bindings.ml @@ -56,3 +56,5 @@ let _ = test_ks T.KS_ARCH_SPARC T.KS_MODE_SPARC32 ~endian:T.KS_MODE_BIG_ENDIAN "add %g1, %g2, %g3"; test_ks T.KS_ARCH_SYSTEMZ T.KS_MODE_BIG_ENDIAN "a %r0, 4095(%r15, %r1)" + + test_ks T.KS_ARCH_MSP430 T.KS_MODE_LITTLE_ENDIAN "and r12, r13" diff --git a/bindings/powershell/Keystone/Const/keystone_h.cs b/bindings/powershell/Keystone/Const/keystone_h.cs index cb7b01ed..fa544e72 100755 --- a/bindings/powershell/Keystone/Const/keystone_h.cs +++ b/bindings/powershell/Keystone/Const/keystone_h.cs @@ -13,7 +13,8 @@ KS_ARCH_SYSTEMZ = 7, KS_ARCH_HEXAGON = 8, KS_ARCH_EVM = 9, -KS_ARCH_MAX = 10, +KS_ARCH_MSP430 = 10, +KS_ARCH_MAX = 11, KS_MODE_LITTLE_ENDIAN = 0, KS_MODE_BIG_ENDIAN = 1073741824, KS_MODE_ARM = 1, diff --git a/bindings/powershell/Keystone/Keystone.psm1 b/bindings/powershell/Keystone/Keystone.psm1 index c72eb429..17d7f968 100755 --- a/bindings/powershell/Keystone/Keystone.psm1 +++ b/bindings/powershell/Keystone/Keystone.psm1 @@ -71,6 +71,8 @@ function Get-KeystoneAssembly { 'KS_ARCH_SPARC', 'KS_ARCH_SYSTEMZ', 'KS_ARCH_HEXAGON', + 'KS_ARCH_EVM', + 'KS_ARCH_MSP430', 'KS_ARCH_MAX') ] [String]$Architecture, diff --git a/bindings/python/README.pypi-src b/bindings/python/README.pypi-src index 603dd9da..b4dbd72c 100644 --- a/bindings/python/README.pypi-src +++ b/bindings/python/README.pypi-src @@ -16,7 +16,7 @@ package instead, which already includes the prebuilt "keystone.dll" inside. Keystone is a lightweight multi-platform, multi-architecture assembler framework. It offers some unparalleled features: -- Multi-architecture, with support for Arm, Arm64 (AArch64/Armv8), Hexagon, Mips, PowerPC, Sparc, SystemZ & X86 (include 16/32/64bit). +- Multi-architecture, with support for Arm, Arm64 (AArch64/Armv8), Hexagon, Mips, MSP430, PowerPC, Sparc, SystemZ & X86 (include 16/32/64bit). - Clean/simple/lightweight/intuitive architecture-neutral API. - Implemented in C/C++ languages, with bindings for Python, NodeJS, Ruby, Go, Rust, Haskell & OCaml available. - Native support for Windows & \*nix (with Mac OSX, Linux, *BSD & Solaris confirmed). diff --git a/bindings/python/keystone/__init__.py b/bindings/python/keystone/__init__.py index 5e4a9663..de0ea509 100644 --- a/bindings/python/keystone/__init__.py +++ b/bindings/python/keystone/__init__.py @@ -1,4 +1,5 @@ # Keystone Python bindings, by Nguyen Anh Quynnh -from . import arm_const, arm64_const, mips_const, sparc_const, hexagon_const, systemz_const, ppc_const, x86_const +from . import arm_const, arm64_const, mips_const, sparc_const, hexagon_const, systemz_const, ppc_const, x86_const,\ + evm_const, msp430_const from .keystone_const import * from .keystone import Ks, ks_version, ks_arch_supported, version_bind, debug, KsError, __version__ diff --git a/bindings/python/keystone/keystone.py b/bindings/python/keystone/keystone.py index 295ceecb..03111840 100644 --- a/bindings/python/keystone/keystone.py +++ b/bindings/python/keystone/keystone.py @@ -4,7 +4,8 @@ if _python2: range = xrange -from . import arm_const, arm64_const, mips_const, sparc_const, hexagon_const, ppc_const, systemz_const, x86_const, evm_const +from . import arm_const, arm64_const, mips_const, sparc_const, hexagon_const, ppc_const, systemz_const, x86_const,\ + evm_const, msp430_const from .keystone_const import * from ctypes import * @@ -228,10 +229,11 @@ def asm(self, string, addr=0, as_bytes=False): # print out debugging info def debug(): - archs = { "arm": KS_ARCH_ARM, "arm64": KS_ARCH_ARM64, \ - "mips": KS_ARCH_MIPS, "sparc": KS_ARCH_SPARC, \ - "systemz": KS_ARCH_SYSTEMZ, "ppc": KS_ARCH_PPC, \ - "hexagon": KS_ARCH_HEXAGON, "x86": KS_ARCH_X86, 'evm': KS_ARCH_EVM } + archs = { "arm": KS_ARCH_ARM, "arm64": KS_ARCH_ARM64, + "mips": KS_ARCH_MIPS, "sparc": KS_ARCH_SPARC, + "systemz": KS_ARCH_SYSTEMZ, "ppc": KS_ARCH_PPC, + "hexagon": KS_ARCH_HEXAGON, "x86": KS_ARCH_X86, + "evm": KS_ARCH_EVM, "msp430": KS_ARCH_MSP430 } all_archs = "" keys = archs.keys() diff --git a/bindings/python/keystone/keystone_const.py b/bindings/python/keystone/keystone_const.py index 9d975c1c..d97deb24 100644 --- a/bindings/python/keystone/keystone_const.py +++ b/bindings/python/keystone/keystone_const.py @@ -13,7 +13,8 @@ KS_ARCH_SYSTEMZ = 7 KS_ARCH_HEXAGON = 8 KS_ARCH_EVM = 9 -KS_ARCH_MAX = 10 +KS_ARCH_MSP430 = 10 +KS_ARCH_MAX = 11 KS_MODE_LITTLE_ENDIAN = 0 KS_MODE_BIG_ENDIAN = 1073741824 KS_MODE_ARM = 1 diff --git a/bindings/python/keystone/msp430_const.py b/bindings/python/keystone/msp430_const.py new file mode 100644 index 00000000..16e155aa --- /dev/null +++ b/bindings/python/keystone/msp430_const.py @@ -0,0 +1,4 @@ +# For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.py] +KS_ERR_ASM_MSP430_INVALIDOPERAND = 512 +KS_ERR_ASM_MSP430_MISSINGFEATURE = 513 +KS_ERR_ASM_MSP430_MNEMONICFAIL = 514 diff --git a/bindings/python/sample.py b/bindings/python/sample.py index 2e2830ee..6ee9f889 100755 --- a/bindings/python/sample.py +++ b/bindings/python/sample.py @@ -94,5 +94,8 @@ def sym_resolver(symbol, value): # SystemZ test_ks(KS_ARCH_SYSTEMZ, KS_MODE_BIG_ENDIAN, b"a %r0, 4095(%r15,%r1)") + # MSP430 + test_ks(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, b"and r12, r13") + # test symbol resolver test_sym_resolver() diff --git a/bindings/ruby/keystone_gem/lib/keystone/keystone_const.rb b/bindings/ruby/keystone_gem/lib/keystone/keystone_const.rb index abbde925..c08659cd 100644 --- a/bindings/ruby/keystone_gem/lib/keystone/keystone_const.rb +++ b/bindings/ruby/keystone_gem/lib/keystone/keystone_const.rb @@ -15,7 +15,8 @@ module Keystone KS_ARCH_SYSTEMZ = 7 KS_ARCH_HEXAGON = 8 KS_ARCH_EVM = 9 - KS_ARCH_MAX = 10 + KS_ARCH_MSP430 = 10 + KS_ARCH_MAX = 11 KS_MODE_LITTLE_ENDIAN = 0 KS_MODE_BIG_ENDIAN = 1073741824 KS_MODE_ARM = 1 diff --git a/bindings/ruby/keystone_gem/lib/keystone/msp430_const.rb b/bindings/ruby/keystone_gem/lib/keystone/msp430_const.rb new file mode 100644 index 00000000..b7a6a293 --- /dev/null +++ b/bindings/ruby/keystone_gem/lib/keystone/msp430_const.rb @@ -0,0 +1,7 @@ +# For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.rb] + +module Keystone + KS_ERR_ASM_MSP430_INVALIDOPERAND = 512 + KS_ERR_ASM_MSP430_MISSINGFEATURE = 513 + KS_ERR_ASM_MSP430_MNEMONICFAIL = 514 +end \ No newline at end of file diff --git a/bindings/ruby/sample.rb b/bindings/ruby/sample.rb index 9839fb11..3c096a8a 100755 --- a/bindings/ruby/sample.rb +++ b/bindings/ruby/sample.rb @@ -58,3 +58,6 @@ def test_ks(arch, mode, code, syntax=0) # SystemZ test_ks(KS_ARCH_SYSTEMZ, KS_MODE_BIG_ENDIAN, "a %r0, 4095(%r15,%r1)") + +# MSP430 +test_ks(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, "and r12, r13") diff --git a/bindings/rust/keystone-sys/src/arm64_const.rs b/bindings/rust/keystone-sys/src/arm64_const.rs new file mode 100644 index 00000000..6805da77 --- /dev/null +++ b/bindings/rust/keystone-sys/src/arm64_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_ARM64_INVALIDOPERAND = 512; + const ASM_ARM64_MISSINGFEATURE = 513; + const ASM_ARM64_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/arm_const.rs b/bindings/rust/keystone-sys/src/arm_const.rs new file mode 100644 index 00000000..8ad5deff --- /dev/null +++ b/bindings/rust/keystone-sys/src/arm_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_ARM_INVALIDOPERAND = 512; + const ASM_ARM_MISSINGFEATURE = 513; + const ASM_ARM_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/evm_const.rs b/bindings/rust/keystone-sys/src/evm_const.rs new file mode 100644 index 00000000..30326484 --- /dev/null +++ b/bindings/rust/keystone-sys/src/evm_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [evm_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_EVM_INVALIDOPERAND = 512; + const ASM_EVM_MISSINGFEATURE = 513; + const ASM_EVM_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/hexagon_const.rs b/bindings/rust/keystone-sys/src/hexagon_const.rs new file mode 100644 index 00000000..2b3138dc --- /dev/null +++ b/bindings/rust/keystone-sys/src/hexagon_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hexagon_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_HEXAGON_INVALIDOPERAND = 512; + const ASM_HEXAGON_MISSINGFEATURE = 513; + const ASM_HEXAGON_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/keystone_const.rs b/bindings/rust/keystone-sys/src/keystone_const.rs index c81f3240..20d31b76 100644 --- a/bindings/rust/keystone-sys/src/keystone_const.rs +++ b/bindings/rust/keystone-sys/src/keystone_const.rs @@ -42,7 +42,8 @@ pub enum Arch { SYSTEMZ = 7, HEXAGON = 8, EVM = 9, - MAX = 10, + MSP430 = 10, + MAX = 11, } #[repr(C)] diff --git a/bindings/rust/keystone-sys/src/mips_const.rs b/bindings/rust/keystone-sys/src/mips_const.rs new file mode 100644 index 00000000..b3c72bd6 --- /dev/null +++ b/bindings/rust/keystone-sys/src/mips_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_MIPS_INVALIDOPERAND = 512; + const ASM_MIPS_MISSINGFEATURE = 513; + const ASM_MIPS_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/msp430_const.rs b/bindings/rust/keystone-sys/src/msp430_const.rs new file mode 100644 index 00000000..8b299e48 --- /dev/null +++ b/bindings/rust/keystone-sys/src/msp430_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_MSP430_INVALIDOPERAND = 512; + const ASM_MSP430_MISSINGFEATURE = 513; + const ASM_MSP430_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/ppc_const.rs b/bindings/rust/keystone-sys/src/ppc_const.rs new file mode 100644 index 00000000..caeea646 --- /dev/null +++ b/bindings/rust/keystone-sys/src/ppc_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_PPC_INVALIDOPERAND = 512; + const ASM_PPC_MISSINGFEATURE = 513; + const ASM_PPC_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/sparc_const.rs b/bindings/rust/keystone-sys/src/sparc_const.rs new file mode 100644 index 00000000..dd544ae1 --- /dev/null +++ b/bindings/rust/keystone-sys/src/sparc_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_SPARC_INVALIDOPERAND = 512; + const ASM_SPARC_MISSINGFEATURE = 513; + const ASM_SPARC_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/systemz_const.rs b/bindings/rust/keystone-sys/src/systemz_const.rs new file mode 100644 index 00000000..d2a8a1f3 --- /dev/null +++ b/bindings/rust/keystone-sys/src/systemz_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [systemz_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_SYSTEMZ_INVALIDOPERAND = 512; + const ASM_SYSTEMZ_MISSINGFEATURE = 513; + const ASM_SYSTEMZ_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/x86_const.rs b/bindings/rust/keystone-sys/src/x86_const.rs new file mode 100644 index 00000000..2db5ce54 --- /dev/null +++ b/bindings/rust/keystone-sys/src/x86_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_X86_INVALIDOPERAND = 512; + const ASM_X86_MISSINGFEATURE = 513; + const ASM_X86_MNEMONICFAIL = 514; + } +} diff --git a/bindings/vb6/Form1.frm b/bindings/vb6/Form1.frm index 4616d0ae..e70e2eda 100644 --- a/bindings/vb6/Form1.frm +++ b/bindings/vb6/Form1.frm @@ -116,6 +116,9 @@ Private Sub Form_Load() ' SystemZ AddResult test_ks(KS_ARCH_SYSTEMZ, KS_MODE_BIG_ENDIAN, "a %r0, 4095(%r15,%r1)", 0, base) + + ' MSP430 + AddResult test_ks(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, "and r12, r13", 0, base) ' symbol resolver test (will enable once in stable release binaries not tested yet) 'AddResult test_ks(KS_ARCH_X86, KS_MODE_32, "jmp _l1; nop", 0, , base, True) diff --git a/bindings/vb6/mKeystone.bas b/bindings/vb6/mKeystone.bas index f5fb7ac4..b5d207b2 100644 --- a/bindings/vb6/mKeystone.bas +++ b/bindings/vb6/mKeystone.bas @@ -24,6 +24,8 @@ Public Enum ks_arch KS_ARCH_SPARC ' Sparc architecture KS_ARCH_SYSTEMZ ' SystemZ architecture (S390X) KS_ARCH_HEXAGON ' Hexagon architecture + KS_ARCH_EVM ' EVM architecture + KS_ARCH_MSP430 ' MSP430 architecture KS_ARCH_MAX End Enum @@ -339,6 +341,8 @@ Function ks_arch2str(v As ks_arch) As String If v = KS_ARCH_SPARC Then r = "KS_ARCH_SPARC" If v = KS_ARCH_SYSTEMZ Then r = "KS_ARCH_SYSTEMZ" If v = KS_ARCH_HEXAGON Then r = "KS_ARCH_HEXAGON" + If v = KS_ARCH_EVM Then r = "KS_ARCH_EVM" + If v = KS_ARCH_MSP430 Then r = "KS_ARCH_MSP430" If v = KS_ARCH_MAX Then r = "KS_ARCH_MAX" If Len(r) = 0 Then r = "Unknown: " & Hex(v) ks_arch2str = r diff --git a/samples/sample.c b/samples/sample.c index e75e181e..ea82e010 100644 --- a/samples/sample.c +++ b/samples/sample.c @@ -137,9 +137,6 @@ int main(int argc, char **argv) test_ks(KS_ARCH_MIPS, KS_MODE_MIPS64, "and $9, $6, $7", 0); test_ks(KS_ARCH_MIPS, KS_MODE_MIPS64 + KS_MODE_BIG_ENDIAN, "and $9, $6, $7", 0); - // MSP430 - test_ks(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, "and r12, r13", 0); - // PowerPC test_ks(KS_ARCH_PPC, KS_MODE_PPC32 + KS_MODE_BIG_ENDIAN, "add 1, 2, 3", 0); test_ks(KS_ARCH_PPC, KS_MODE_PPC64, "add 1, 2, 3", 0); @@ -152,6 +149,9 @@ int main(int argc, char **argv) // SystemZ test_ks(KS_ARCH_SYSTEMZ, KS_MODE_BIG_ENDIAN, "a %r0, 4095(%r15,%r1)", 0); + // MSP430 + test_ks(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, "and r12, r13", 0); + // Test Symbol Resolver test_sym_resolver(); From 5a86943cf23624522b9c4039792ea21119ce4b54 Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Fri, 21 Dec 2018 14:43:44 -0500 Subject: [PATCH 05/14] Remove LLVM_CONSTEXPR (like upstream LLVM did) and fix Java binding See https://github.com/llvm-mirror/llvm/commit/6feedc56f7855aa24baf759f3bc17112ecbf5699#diff-d14f03e012a2bdbf93486dc1c4ce95ec --- .../java/src/main/java/keystone/KeystoneArchitecture.java | 2 +- llvm/include/llvm/ADT/ArrayRef.h | 4 ++-- llvm/include/llvm/ADT/Optional.h | 2 +- llvm/include/llvm/ADT/STLExtras.h | 4 ++-- llvm/include/llvm/Support/Compiler.h | 6 ------ llvm/lib/Support/APInt.cpp | 2 +- 6 files changed, 7 insertions(+), 13 deletions(-) diff --git a/bindings/java/src/main/java/keystone/KeystoneArchitecture.java b/bindings/java/src/main/java/keystone/KeystoneArchitecture.java index 403b4460..e5036459 100644 --- a/bindings/java/src/main/java/keystone/KeystoneArchitecture.java +++ b/bindings/java/src/main/java/keystone/KeystoneArchitecture.java @@ -66,7 +66,7 @@ public enum KeystoneArchitecture implements JnaEnum { */ Msp430(10), - Max(10); + Max(11); /** * Mapping table to determine an enumeration value based on an integer with a complexity of θ(1). diff --git a/llvm/include/llvm/ADT/ArrayRef.h b/llvm/include/llvm/ADT/ArrayRef.h index 1c706cca..42144626 100644 --- a/llvm/include/llvm/ADT/ArrayRef.h +++ b/llvm/include/llvm/ADT/ArrayRef.h @@ -80,7 +80,7 @@ namespace llvm_ks { /// Construct an ArrayRef from a C array. template - /*implicit*/ LLVM_CONSTEXPR ArrayRef(const T (&Arr)[N]) + /*implicit*/ constexpr ArrayRef(const T (&Arr)[N]) : Data(Arr), Length(N) {} /// Construct an ArrayRef from a std::initializer_list. @@ -249,7 +249,7 @@ namespace llvm_ks { /// Construct an MutableArrayRef from a C array. template - /*implicit*/ LLVM_CONSTEXPR MutableArrayRef(T (&Arr)[N]) + /*implicit*/ constexpr MutableArrayRef(T (&Arr)[N]) : ArrayRef(Arr) {} T *data() const { return const_cast(ArrayRef::data()); } diff --git a/llvm/include/llvm/ADT/Optional.h b/llvm/include/llvm/ADT/Optional.h index 817eb709..4f388011 100644 --- a/llvm/include/llvm/ADT/Optional.h +++ b/llvm/include/llvm/ADT/Optional.h @@ -129,7 +129,7 @@ class Optional { T& operator*() LLVM_LVALUE_FUNCTION { assert(hasVal); return *getPointer(); } template - LLVM_CONSTEXPR T getValueOr(U &&value) const LLVM_LVALUE_FUNCTION { + constexpr T getValueOr(U &&value) const LLVM_LVALUE_FUNCTION { return hasValue() ? getValue() : std::forward(value); } diff --git a/llvm/include/llvm/ADT/STLExtras.h b/llvm/include/llvm/ADT/STLExtras.h index 3346de93..47465523 100644 --- a/llvm/include/llvm/ADT/STLExtras.h +++ b/llvm/include/llvm/ADT/STLExtras.h @@ -257,7 +257,7 @@ struct less_second { template struct integer_sequence { typedef T value_type; - static LLVM_CONSTEXPR size_t size() { return sizeof...(I); } + static constexpr size_t size() { return sizeof...(I); } }; /// \brief Alias for the common case of a sequence of size_ts. @@ -279,7 +279,7 @@ struct index_sequence_for : build_index_impl {}; /// Find the length of an array. template -LLVM_CONSTEXPR inline size_t array_lengthof(T (&)[N]) { +constexpr inline size_t array_lengthof(T (&)[N]) { return N; } diff --git a/llvm/include/llvm/Support/Compiler.h b/llvm/include/llvm/Support/Compiler.h index b3416bbf..405e4e59 100644 --- a/llvm/include/llvm/Support/Compiler.h +++ b/llvm/include/llvm/Support/Compiler.h @@ -92,12 +92,6 @@ #define LLVM_LVALUE_FUNCTION #endif -#if __has_feature(cxx_constexpr) || defined(__GXX_EXPERIMENTAL_CXX0X__) -# define LLVM_CONSTEXPR constexpr -#else -# define LLVM_CONSTEXPR -#endif - /// LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked /// into a shared library, then the class should be private to the library and /// not accessible from outside it. Can also be used to mark variables and diff --git a/llvm/lib/Support/APInt.cpp b/llvm/lib/Support/APInt.cpp index f581101b..99b7c038 100644 --- a/llvm/lib/Support/APInt.cpp +++ b/llvm/lib/Support/APInt.cpp @@ -1517,7 +1517,7 @@ static void KnuthDiv(unsigned *u, unsigned *v, unsigned *q, unsigned* r, assert(n>1 && "n must be > 1"); // b denotes the base of the number system. In our case b is 2^32. - LLVM_CONSTEXPR uint64_t b = uint64_t(1) << 32; + constexpr uint64_t b = uint64_t(1) << 32; // D1. [Normalize.] Set d = b / (v[n-1] + 1) and multiply all the digits of // u and v by d. Note that we have taken Knuth's advice here to use a power From 47388b676e2889ee25fc7aafd6e9b3aa51620a6d Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Wed, 2 Jan 2019 13:19:14 -0500 Subject: [PATCH 06/14] Revert bindings --- bindings/Makefile | 5 -- bindings/const_generator.py | 55 ++++++------- .../Keystone.Net/Constants/ARM64Constants.cs | 2 +- .../Keystone.Net/Constants/ARMConstants.cs | 2 +- .../Constants/HexagonConstants.cs | 2 +- .../Constants/KeystoneConstants.cs | 80 +++++++++---------- .../Keystone.Net/Constants/MipsConstants.cs | 2 +- .../Keystone.Net/Constants/PPCConstants.cs | 2 +- .../Keystone.Net/Constants/SPARCConstants.cs | 2 +- .../Constants/SystemZConstants.cs | 2 +- .../Keystone.Net/Constants/X86Constants.cs | 2 +- bindings/go/keystone/keystone_const.go | 3 +- bindings/haskell/keystone.cabal | 1 - bindings/haskell/samples/Sample.hs | 3 - bindings/java/pom.xml | 2 +- .../java/keystone/KeystoneArchitecture.java | 7 +- bindings/masm/keystone_x64.inc | 4 +- bindings/masm/keystone_x86.inc | 4 +- bindings/masm/masmApiConst.api.txt | 4 +- bindings/nodejs/consts/index.js | 2 +- bindings/nodejs/consts/keystone.js | 3 +- bindings/ocaml/ffi_types.ml | 44 ---------- bindings/ocaml/keystone.mli | 2 - bindings/ocaml/test_bindings.ml | 2 - .../powershell/Keystone/Const/keystone_h.cs | 3 +- bindings/powershell/Keystone/Keystone.psm1 | 2 - bindings/python/README.pypi-src | 2 +- bindings/python/keystone/__init__.py | 3 +- bindings/python/keystone/keystone.py | 12 ++- bindings/python/keystone/keystone_const.py | 3 +- bindings/python/sample.py | 3 - .../lib/keystone/keystone_const.rb | 3 +- bindings/ruby/sample.rb | 3 - .../rust/keystone-sys/src/keystone_const.rs | 3 +- bindings/vb6/Form1.frm | 3 - bindings/vb6/mKeystone.bas | 4 - 36 files changed, 92 insertions(+), 189 deletions(-) diff --git a/bindings/Makefile b/bindings/Makefile index ec88cfab..85799b6a 100644 --- a/bindings/Makefile +++ b/bindings/Makefile @@ -7,7 +7,6 @@ DIFF = diff -u -w SAMPLE_ARM = $(TMPDIR)/sample_arm SAMPLE_ARM64 = $(TMPDIR)/sample_arm64 SAMPLE_MIPS = $(TMPDIR)/sample_mips -SAMPLE_MSP430 = $(TMPDIR)/sample_msp430 SAMPLE_M68K = $(TMPDIR)/sample_m68k SAMPLE_SPARC = $(TMPDIR)/sample_sparc SAMPLE_X86 = $(TMPDIR)/sample_x86 @@ -21,7 +20,6 @@ all: python const_generator.py go cd ruby && $(MAKE) gen_const python const_generator.py powershell - python const_generator.py csharp samples: expected python @@ -33,7 +31,6 @@ expected: ../samples/sample_arm > $(SAMPLE_ARM)_e ../samples/sample_arm64 > $(SAMPLE_ARM64)_e ../samples/sample_mips > $(SAMPLE_MIPS)_e - ../samples/sample_msp430 > $(SAMPLE_MSP430)_e ../samples/sample_sparc > $(SAMPLE_SPARC)_e ../samples/sample_m68k > $(SAMPLE_M68K)_e ../samples/sample_x86 > $(SAMPLE_X86)_e @@ -43,7 +40,6 @@ python: FORCE python python/sample_arm.py > $(SAMPLE_ARM)_o python python/sample_arm64.py > $(SAMPLE_ARM64)_o python python/sample_mips.py > $(SAMPLE_MIPS)_o - python python/sample_msp430.py > $(SAMPLE_MSP430)_o python python/sample_sparc.py > $(SAMPLE_SPARC)_o python python/sample_m68k.py > $(SAMPLE_M68K)_o python python/sample_x86.py > $(SAMPLE_X86)_o @@ -68,7 +64,6 @@ sample_diff: FORCE $(DIFF) $(SAMPLE_ARM)_e $(SAMPLE_ARM)_o $(DIFF) $(SAMPLE_ARM64)_e $(SAMPLE_ARM64)_o $(DIFF) $(SAMPLE_MIPS)_e $(SAMPLE_MIPS)_o - $(DIFF) $(SAMPLE_MSP430)_e $(SAMPLE_MSP430)_o $(DIFF) $(SAMPLE_SPARC)_e $(SAMPLE_SPARC)_o $(DIFF) $(SAMPLE_M68K)_e $(SAMPLE_M68K)_o $(DIFF) $(SAMPLE_X86)_e $(SAMPLE_X86)_o diff --git a/bindings/const_generator.py b/bindings/const_generator.py index 7f5b5113..db69d55a 100644 --- a/bindings/const_generator.py +++ b/bindings/const_generator.py @@ -8,7 +8,7 @@ # NOTE: this reflects the value of KS_ERR_ASM_xxx in keystone.h ks_err_val = { 'KS_ERR_ASM': '128', 'KS_ERR_ASM_ARCH': '512' } -include = [ 'arm.h', 'arm64.h', 'mips.h', 'x86.h', 'sparc.h', 'ppc.h', 'systemz.h', 'hexagon.h', 'evm.h', 'msp430.h', 'keystone.h' ] +include = [ 'arm.h', 'arm64.h', 'mips.h', 'x86.h', 'sparc.h', 'ppc.h', 'systemz.h', 'hexagon.h', 'evm.h', 'keystone.h' ] def CamelCase(s): # return re.sub(r'(\w)+\_?', lambda m:m.group(0).capitalize(), s) @@ -35,16 +35,15 @@ def CamelCase(s): 'header': "#![allow(non_camel_case_types)]\n// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.rs]\nuse libc;\n", 'footer': "", # prefixes for constant filenames of all archs - case sensitive - 'arm.h': 'arm', - 'arm64.h': 'arm64', - 'mips.h': 'mips', - 'msp430.h': 'msp430', - 'x86.h': 'x86', - 'sparc.h': 'sparc', - 'systemz.h': 'systemz', - 'ppc.h': 'ppc', - 'hexagon.h': 'hexagon', - 'evm.h': 'evm', + 'arm.h': 'keystone', + 'arm64.h': 'keystone', + 'mips.h': 'keystone', + 'x86.h': 'keystone', + 'sparc.h': 'keystone', + 'systemz.h': 'keystone', + 'ppc.h': 'keystone', + 'hexagon.h': 'keystone', + 'evm.h': 'keystone', 'keystone.h': 'keystone', 'comment_open': '/*', 'comment_close': '*/', @@ -111,7 +110,6 @@ def CamelCase(s): 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', - 'msp430.h': 'msp430', 'x86.h': 'x86', 'sparc.h': 'sparc', 'systemz.h': 'systemz', @@ -174,7 +172,6 @@ def CamelCase(s): 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', - 'msp430.h': 'msp430', 'x86.h': 'x86', 'sparc.h': 'sparc', 'systemz.h': 'systemz', @@ -200,7 +197,6 @@ def CamelCase(s): 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', - 'msp430.h': 'msp430', 'x86.h': 'x86', 'sparc.h': 'sparc', 'systemz.h': 'systemz', @@ -226,7 +222,6 @@ def CamelCase(s): 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', - 'msp430.h': 'msp430', 'x86.h': 'x86', 'sparc.h': 'sparc', 'systemz.h': 'systemz', @@ -245,34 +240,34 @@ def CamelCase(s): ] }, 'csharp': { - 'header': "// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%sConstants.cs]\nnamespace Keystone\n{", + 'header': "// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%sConstants.cs]\nnamespace KeystoneNET\n{", 'footer': "}", - 'out_file': './csharp/Keystone.NET/Constants/%sConstants.cs', + 'out_file': './csharp/KeystoneNET/KeystoneNET/Constants/%sConstants.cs', # prefixes for constant filenames of all archs - case sensitive - 'keystone.h': 'Keystone', - 'arm.h': 'ARM', - 'arm64.h': 'ARM64', - 'mips.h': 'Mips', - 'msp430.h': 'MSP430', - 'x86.h': 'X86', - 'sparc.h': 'SPARC', - 'systemz.h': 'SystemZ', - 'ppc.h': 'PPC', - 'hexagon.h': 'Hexagon', - 'evm.h': 'EVM', + 'keystone.h': 'keystone', + 'arm.h': 'arm', + 'arm64.h': 'arm64', + 'mips.h': 'mips', + 'x86.h': 'x86', + 'sparc.h': 'sparc', + 'systemz.h': 'systemz', + 'ppc.h': 'ppc', + 'hexagon.h': 'hexagon', + 'evm.h': 'evm', + 'keystone.h': 'keystone', 'comment_open': '//', 'comment_close': '', 'rules': [ { 'regex': r'(ARCH)_.*', - 'pre': '\n\tpublic enum Architecture : int\n\t{{\n', + 'pre': '\n\tpublic enum KeystoneArchitecture : int\n\t{{\n', 'post': '\t}', 'line_format': '\t\tKS_{0} = {1},\n', 'fn': (lambda x: x), }, { 'regex': r'(MODE)_.*', - 'pre': '\n\tpublic enum Mode : uint\n\t{{\n', + 'pre': '\n\tpublic enum KeystoneMode : uint\n\t{{\n', 'post': '\t}', 'line_format': '\t\tKS_{0} = {1},\n', 'fn': (lambda x: x), diff --git a/bindings/csharp/Keystone.Net/Constants/ARM64Constants.cs b/bindings/csharp/Keystone.Net/Constants/ARM64Constants.cs index df6cf463..33eb5458 100644 --- a/bindings/csharp/Keystone.Net/Constants/ARM64Constants.cs +++ b/bindings/csharp/Keystone.Net/Constants/ARM64Constants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ARM64Constants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64Constants.cs] namespace Keystone { public enum Arm64Error : short diff --git a/bindings/csharp/Keystone.Net/Constants/ARMConstants.cs b/bindings/csharp/Keystone.Net/Constants/ARMConstants.cs index 60b44151..f8d0c273 100644 --- a/bindings/csharp/Keystone.Net/Constants/ARMConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/ARMConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ARMConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [armConstants.cs] namespace Keystone { public enum ArmError : short diff --git a/bindings/csharp/Keystone.Net/Constants/HexagonConstants.cs b/bindings/csharp/Keystone.Net/Constants/HexagonConstants.cs index 673a66f4..bfb0da9f 100644 --- a/bindings/csharp/Keystone.Net/Constants/HexagonConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/HexagonConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [HexagonConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hexagonConstants.cs] namespace Keystone { public enum HexagonError : short diff --git a/bindings/csharp/Keystone.Net/Constants/KeystoneConstants.cs b/bindings/csharp/Keystone.Net/Constants/KeystoneConstants.cs index 04cd530a..124e5247 100644 --- a/bindings/csharp/Keystone.Net/Constants/KeystoneConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/KeystoneConstants.cs @@ -3,40 +3,38 @@ namespace Keystone { public enum Architecture : int { - KS_ARCH_ARM = 1, - KS_ARCH_ARM64 = 2, - KS_ARCH_MIPS = 3, - KS_ARCH_X86 = 4, - KS_ARCH_PPC = 5, - KS_ARCH_SPARC = 6, - KS_ARCH_SYSTEMZ = 7, - KS_ARCH_HEXAGON = 8, - KS_ARCH_EVM = 9, - KS_ARCH_MSP430 = 10, - KS_ARCH_MAX = 11, + ARM = 1, + ARM64 = 2, + MIPS = 3, + X86 = 4, + PPC = 5, + SPARC = 6, + SYSTEMZ = 7, + HEXAGON = 8, + MAX = 9, } public enum Mode : uint { - KS_MODE_LITTLE_ENDIAN = 0, - KS_MODE_BIG_ENDIAN = 1073741824, - KS_MODE_ARM = 1, - KS_MODE_THUMB = 16, - KS_MODE_V8 = 64, - KS_MODE_MICRO = 16, - KS_MODE_MIPS3 = 32, - KS_MODE_MIPS32R6 = 64, - KS_MODE_MIPS32 = 4, - KS_MODE_MIPS64 = 8, - KS_MODE_16 = 2, - KS_MODE_32 = 4, - KS_MODE_64 = 8, - KS_MODE_PPC32 = 4, - KS_MODE_PPC64 = 8, - KS_MODE_QPX = 16, - KS_MODE_SPARC32 = 4, - KS_MODE_SPARC64 = 8, - KS_MODE_V9 = 16, + LITTLE_ENDIAN = 0, + BIG_ENDIAN = 1073741824, + ARM = 1, + THUMB = 16, + V8 = 64, + MICRO = 16, + MIPS3 = 32, + MIPS32R6 = 64, + MIPS32 = 4, + MIPS64 = 8, + X16 = 2, + X32 = 4, + X64 = 8, + PPC32 = 4, + PPC64 = 8, + QPX = 16, + SPARC32 = 4, + SPARC64 = 8, + V9 = 16, } public enum KeystoneError : short @@ -88,22 +86,22 @@ public enum KeystoneError : short KS_ERR_ASM_FRAGMENT_INVALID = 163, KS_ERR_ASM_INVALIDOPERAND = 512, KS_ERR_ASM_MISSINGFEATURE = 513, - KS_ERR_ASM_MNEMONICFAIL = 514, + KS_ERR_ASM_MNEMONICFAIL = 514 } - public enum KeystoneOptionType : short + public enum OptionType : int { - KS_OPT_SYNTAX = 1, - KS_OPT_SYM_RESOLVER = 2, + SYNTAX = 1, + SYM_RESOLVER = 2, } - public enum KeystoneOptionValue : short + public enum OptionValue : short { - KS_OPT_SYNTAX_INTEL = 1, - KS_OPT_SYNTAX_ATT = 2, - KS_OPT_SYNTAX_NASM = 4, - KS_OPT_SYNTAX_MASM = 8, - KS_OPT_SYNTAX_GAS = 16, - KS_OPT_SYNTAX_RADIX16 = 32, + SYNTAX_INTEL = 1, + SYNTAX_ATT = 2, + SYNTAX_NASM = 4, + SYNTAX_MASM = 8, + SYNTAX_GAS = 16, + SYNTAX_RADIX16 = 32 } } \ No newline at end of file diff --git a/bindings/csharp/Keystone.Net/Constants/MipsConstants.cs b/bindings/csharp/Keystone.Net/Constants/MipsConstants.cs index 7a6a2b78..99be03dc 100644 --- a/bindings/csharp/Keystone.Net/Constants/MipsConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/MipsConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [MipsConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mipsConstants.cs] namespace Keystone { public enum MipsError : short diff --git a/bindings/csharp/Keystone.Net/Constants/PPCConstants.cs b/bindings/csharp/Keystone.Net/Constants/PPCConstants.cs index 4256560a..601585a7 100644 --- a/bindings/csharp/Keystone.Net/Constants/PPCConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/PPCConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [PPCConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppcConstants.cs] namespace Keystone { public enum PpcError : short diff --git a/bindings/csharp/Keystone.Net/Constants/SPARCConstants.cs b/bindings/csharp/Keystone.Net/Constants/SPARCConstants.cs index 4b77d77c..6de93d20 100644 --- a/bindings/csharp/Keystone.Net/Constants/SPARCConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/SPARCConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [SPARCConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparcConstants.cs] namespace Keystone { public enum SparcError : short diff --git a/bindings/csharp/Keystone.Net/Constants/SystemZConstants.cs b/bindings/csharp/Keystone.Net/Constants/SystemZConstants.cs index 3bb58254..d2b61320 100644 --- a/bindings/csharp/Keystone.Net/Constants/SystemZConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/SystemZConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [SystemZConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [systemzConstants.cs] namespace Keystone { public enum SystemzError : short diff --git a/bindings/csharp/Keystone.Net/Constants/X86Constants.cs b/bindings/csharp/Keystone.Net/Constants/X86Constants.cs index 7d33e988..79743f7d 100644 --- a/bindings/csharp/Keystone.Net/Constants/X86Constants.cs +++ b/bindings/csharp/Keystone.Net/Constants/X86Constants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [X86Constants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86Constants.cs] namespace Keystone { public enum X86Error : short diff --git a/bindings/go/keystone/keystone_const.go b/bindings/go/keystone/keystone_const.go index 0e07b785..f78837c0 100644 --- a/bindings/go/keystone/keystone_const.go +++ b/bindings/go/keystone/keystone_const.go @@ -38,8 +38,7 @@ const ( ARCH_SYSTEMZ Architecture = 7 ARCH_HEXAGON Architecture = 8 ARCH_EVM Architecture = 9 - ARCH_MSP430 Architecture = 10 - ARCH_MAX Architecture = 11 + ARCH_MAX Architecture = 10 ) const ( diff --git a/bindings/haskell/keystone.cabal b/bindings/haskell/keystone.cabal index 309873ff..e8b16037 100644 --- a/bindings/haskell/keystone.cabal +++ b/bindings/haskell/keystone.cabal @@ -19,7 +19,6 @@ library Keystone.CPU.Arm Keystone.CPU.Hexagon Keystone.CPU.Mips - Keystone.CPU.Msp430 Keystone.CPU.Ppc Keystone.CPU.Sparc Keystone.CPU.SystemZ diff --git a/bindings/haskell/samples/Sample.hs b/bindings/haskell/samples/Sample.hs index f17a87a5..dba62ce4 100644 --- a/bindings/haskell/samples/Sample.hs +++ b/bindings/haskell/samples/Sample.hs @@ -72,6 +72,3 @@ main = do -- SystemZ testKs ArchSystemz [ModeBigEndian] ["a %r0, 4095(%r15,%r1)"] Nothing - - -- MSP430 - testKs ArchMsp430 [ModeLittleEndian] ["and r12, r13"] Nothing diff --git a/bindings/java/pom.xml b/bindings/java/pom.xml index 9a76b755..65949b23 100644 --- a/bindings/java/pom.xml +++ b/bindings/java/pom.xml @@ -16,7 +16,7 @@ 0.9.1-0 Keystone Java bindings - Keystone assembler framework: Core (Arm, Arm64, Hexagon, Mips, MSP430, PowerPC, Sparc, SystemZ and X86) orm. + Keystone assembler framework: Core (Arm, Arm64, Hexagon, Mips, PowerPC, Sparc, SystemZ and X86) orm. https://github.com/keystone-engine/keystone/tree/master/bindings/java diff --git a/bindings/java/src/main/java/keystone/KeystoneArchitecture.java b/bindings/java/src/main/java/keystone/KeystoneArchitecture.java index e5036459..fc30ca7e 100644 --- a/bindings/java/src/main/java/keystone/KeystoneArchitecture.java +++ b/bindings/java/src/main/java/keystone/KeystoneArchitecture.java @@ -61,12 +61,7 @@ public enum KeystoneArchitecture implements JnaEnum { */ Evm(9), - /** - * Msp430 architecture - */ - Msp430(10), - - Max(11); + Max(10); /** * Mapping table to determine an enumeration value based on an integer with a complexity of θ(1). diff --git a/bindings/masm/keystone_x64.inc b/bindings/masm/keystone_x64.inc index 40eadce3..eb4b7cdb 100644 --- a/bindings/masm/keystone_x64.inc +++ b/bindings/masm/keystone_x64.inc @@ -32,9 +32,7 @@ KS_ARCH_PPC EQU 5 ; PowerPC architecture (currently un KS_ARCH_SPARC EQU 6 ; Sparc architecture KS_ARCH_SYSTEMZ EQU 7 ; SystemZ architecture (S390X) KS_ARCH_HEXAGON EQU 8 ; Hexagon architecture -KS_ARCH_EVM EQU 9 ; EVM architecture -KS_ARCH_MSP430 EQU 10 ; MSP430 architecture -KS_ARCH_MAX EQU 11 ; +KS_ARCH_MAX EQU 9 ; ; Mode type ks_mode KS_MODE_LITTLE_ENDIAN EQU 0 ; little-endian mode (default mode) diff --git a/bindings/masm/keystone_x86.inc b/bindings/masm/keystone_x86.inc index f99fb5c3..8d3a33b8 100644 --- a/bindings/masm/keystone_x86.inc +++ b/bindings/masm/keystone_x86.inc @@ -32,9 +32,7 @@ KS_ARCH_PPC EQU 5 ; PowerPC architecture (currently un KS_ARCH_SPARC EQU 6 ; Sparc architecture KS_ARCH_SYSTEMZ EQU 7 ; SystemZ architecture (S390X) KS_ARCH_HEXAGON EQU 8 ; Hexagon architecture -KS_ARCH_EVM EQU 9 ; EVM architecture -KS_ARCH_MSP430 EQU 10 ; MSP430 architecture -KS_ARCH_MAX EQU 11 ; +KS_ARCH_MAX EQU 9 ; ; Mode type ks_mode KS_MODE_LITTLE_ENDIAN EQU 0 ; little-endian mode (default mode) diff --git a/bindings/masm/masmApiConst.api.txt b/bindings/masm/masmApiConst.api.txt index cb635164..90399a92 100644 --- a/bindings/masm/masmApiConst.api.txt +++ b/bindings/masm/masmApiConst.api.txt @@ -6,8 +6,8 @@ ;----------------------------------------------------------------------------------------------------- 1ks_version,NULL,KS_VERSION_MAJOR 2ks_version,NULL,KS_VERSION_MINOR -1ks_arch_supported,KS_ARCH_ARM,KS_ARCH_ARM64,KS_ARCH_MIPS,KS_ARCH_X86,KS_ARCH_PPC,KS_ARCH_SPARC,KS_ARCH_SYSTEMZ,KS_ARCH_HEXAGON,KS_ARCH_EVM,KS_ARCH_MSP430,KS_ARCH_MAX -1ks_open,KS_ARCH_ARM,KS_ARCH_ARM64,KS_ARCH_MIPS,KS_ARCH_X86,KS_ARCH_PPC,KS_ARCH_SPARC,KS_ARCH_SYSTEMZ,KS_ARCH_HEXAGON,KS_ARCH_EVM,KS_ARCH_MSP430,KS_ARCH_MAX +1ks_arch_supported,KS_ARCH_ARM,KS_ARCH_ARM64,KS_ARCH_MIPS,KS_ARCH_X86,KS_ARCH_PPC,KS_ARCH_SPARC,KS_ARCH_SYSTEMZ,KS_ARCH_HEXAGON,KS_ARCH_MAX +1ks_open,KS_ARCH_ARM,KS_ARCH_ARM64,KS_ARCH_MIPS,KS_ARCH_X86,KS_ARCH_PPC,KS_ARCH_SPARC,KS_ARCH_SYSTEMZ,KS_ARCH_HEXAGON,KS_ARCH_MAX 2ks_open,KS_MODE_LITTLE_ENDIAN,KS_MODE_BIG_ENDIAN,KS_MODE_ARM,KS_MODE_THUMB,KS_MODE_V8,KS_MODE_MICRO,KS_MODE_MIPS3,KS_MODE_MIPS32R6,KS_MODE_MIPS32,KS_MODE_MIPS64,KS_MODE_16,KS_MODE_32,KS_MODE_64,KS_MODE_PPC32,KS_MODE_PPC64,KS_MODE_QPX,KS_MODE_SPARC32,KS_MODE_SPARC64,KS_MODE_V9 1ks_strerror,KS_ERR_OK,KS_ERR_NOMEM,KS_ERR_ARCH,KS_ERR_HANDLE,KS_ERR_MODE,KS_ERR_VERSION,KS_ERR_OPT_INVALID,KS_ERR_ASM_EXPR_TOKEN,KS_ERR_ASM_DIRECTIVE_VALUE_RANGE,KS_ERR_ASM_DIRECTIVE_ID,KS_ERR_ASM_DIRECTIVE_TOKEN,KS_ERR_ASM_DIRECTIVE_STR,KS_ERR_ASM_DIRECTIVE_COMMA,KS_ERR_ASM_DIRECTIVE_RELOC_NAME,KS_ERR_ASM_DIRECTIVE_RELOC_TOKEN,KS_ERR_ASM_DIRECTIVE_FPOINT,KS_ERR_ASM_DIRECTIVE_UNKNOWN,KS_ERR_ASM_DIRECTIVE_EQU,KS_ERR_ASM_DIRECTIVE_INVALID,KS_ERR_ASM_VARIANT_INVALID,KS_ERR_ASM_EXPR_BRACKET,KS_ERR_ASM_SYMBOL_MODIFIER,KS_ERR_ASM_SYMBOL_REDEFINED,KS_ERR_ASM_SYMBOL_MISSING,KS_ERR_ASM_RPAREN,KS_ERR_ASM_STAT_TOKEN,KS_ERR_ASM_UNSUPPORTED,KS_ERR_ASM_MACRO_TOKEN,KS_ERR_ASM_MACRO_PAREN,KS_ERR_ASM_MACRO_EQU,KS_ERR_ASM_MACRO_ARGS,KS_ERR_ASM_MACRO_LEVELS_EXCEED,KS_ERR_ASM_MACRO_STR,KS_ERR_ASM_MACRO_INVALID,KS_ERR_ASM_ESC_BACKSLASH,KS_ERR_ASM_ESC_OCTAL,KS_ERR_ASM_ESC_SEQUENCE,KS_ERR_ASM_ESC_STR,KS_ERR_ASM_TOKEN_INVALID,KS_ERR_ASM_INSN_UNSUPPORTED,KS_ERR_ASM_FIXUP_INVALID,KS_ERR_ASM_LABEL_INVALID,KS_ERR_ASM_FRAGMENT_INVALID,KS_ERR_ASM_INVALIDOPERAND,KS_ERR_ASM_MISSINGFEATURE,KS_ERR_ASM_MNEMONICFAIL,KS_ERR_ASM_X86_INVALIDOPERAND,KS_ERR_ASM_X86_MISSINGFEATURE,KS_ERR_ASM_X86_MNEMONICFAIL,KS_ERR_ASM,KS_ERR_ASM_ARCH 2ks_option,KS_OPT_SYNTAX,KS_OPT_SYM_RESOLVER diff --git a/bindings/nodejs/consts/index.js b/bindings/nodejs/consts/index.js index 737f5743..df58d5ca 100644 --- a/bindings/nodejs/consts/index.js +++ b/bindings/nodejs/consts/index.js @@ -1,5 +1,5 @@ var extend = require('util')._extend, - archs = ['arm64', 'arm', 'hexagon', 'mips', 'ppc', 'sparc', 'systemz', 'x86', 'evm', 'msp430'], + archs = ['arm64', 'arm', 'hexagon', 'mips', 'ppc', 'sparc', 'systemz', 'x86'], i module.exports = require('./keystone') diff --git a/bindings/nodejs/consts/keystone.js b/bindings/nodejs/consts/keystone.js index bd210e01..a38e346b 100644 --- a/bindings/nodejs/consts/keystone.js +++ b/bindings/nodejs/consts/keystone.js @@ -13,8 +13,7 @@ module.exports.ARCH_SPARC = 6 module.exports.ARCH_SYSTEMZ = 7 module.exports.ARCH_HEXAGON = 8 module.exports.ARCH_EVM = 9 -module.exports.ARCH_MSP430 = 10 -module.exports.ARCH_MAX = 11 +module.exports.ARCH_MAX = 10 module.exports.MODE_LITTLE_ENDIAN = 0 module.exports.MODE_BIG_ENDIAN = 1073741824 module.exports.MODE_ARM = 1 diff --git a/bindings/ocaml/ffi_types.ml b/bindings/ocaml/ffi_types.ml index 917d6cec..82e13f9a 100644 --- a/bindings/ocaml/ffi_types.ml +++ b/bindings/ocaml/ffi_types.ml @@ -24,8 +24,6 @@ module Types (F: Cstubs.Types.TYPE) = | KS_ARCH_SPARC | KS_ARCH_SYSTEMZ | KS_ARCH_HEXAGON - | KS_ARCH_EVM - | KS_ARCH_MSP430 | KS_ARCH_MAX @@ -223,8 +221,6 @@ module Types (F: Cstubs.Types.TYPE) = let ks_arch_sparc = constant "KS_ARCH_SPARC" int64_t let ks_arch_systemz = constant "KS_ARCH_SYSTEMZ" int64_t let ks_arch_hexagon = constant "KS_ARCH_HEXAGON" int64_t - let ks_arch_evm = constant "KS_ARCH_EVM" int64_t - let ks_arch_msp430 = constant "KS_ARCH_MSP430" int64_t let ks_arch_max = constant "KS_ARCH_MAX" int64_t let ks_arch = enum "ks_arch" [ @@ -236,8 +232,6 @@ module Types (F: Cstubs.Types.TYPE) = KS_ARCH_SPARC, ks_arch_sparc; KS_ARCH_SYSTEMZ, ks_arch_systemz; KS_ARCH_HEXAGON, ks_arch_hexagon; - KS_ARCH_EVM, ks_arch_evm; - KS_ARCH_MSP430, ks_arch_msp430; KS_ARCH_MAX, ks_arch_max ] @@ -530,44 +524,6 @@ module Types (F: Cstubs.Types.TYPE) = ] end - module EVM = - struct - type ks_err_asm_evm = - | KS_ERR_ASM_EVM_INVALIDOPERAND - | KS_ERR_ASM_EVM_MISSINGFEATURE - | KS_ERR_ASM_EVM_MNEMONICFAIL - - - let ks_err_asm_evm_invalidoperand = constant "KS_ERR_ASM_EVM_INVALIDOPERAND" int64_t - let ks_err_asm_evm_missingfeature = constant "KS_ERR_ASM_EVM_MISSINGFEATURE" int64_t - let ks_err_asm_evm_mnemonicfail = constant "KS_ERR_ASM_EVM_MNEMONICFAIL" int64_t - - let ks_err_asm_evm = enum "ks_err_asm_evm" [ - KS_ERR_ASM_EVM_INVALIDOPERAND, ks_err_asm_evm_invalidoperand; - KS_ERR_ASM_EVM_MISSINGFEATURE, ks_err_asm_evm_missingfeature; - KS_ERR_ASM_EVM_MNEMONICFAIL, ks_err_asm_evm_mnemonicfail; - ] - end - - module MSP430 = - struct - type ks_err_asm_msp430 = - | KS_ERR_ASM_MSP430_INVALIDOPERAND - | KS_ERR_ASM_MSP430_MISSINGFEATURE - | KS_ERR_ASM_MSP430_MNEMONICFAIL - - - let ks_err_asm_msp430_invalidoperand = constant "KS_ERR_ASM_MSP430_INVALIDOPERAND" int64_t - let ks_err_asm_msp430_missingfeature = constant "KS_ERR_ASM_MSP430_MISSINGFEATURE" int64_t - let ks_err_asm_msp430_mnemonicfail = constant "KS_ERR_ASM_MSP430_MNEMONICFAIL" int64_t - - let ks_err_asm_msp430 = enum "ks_err_asm_msp430" [ - KS_ERR_ASM_MSP430_INVALIDOPERAND, ks_err_asm_msp430_invalidoperand; - KS_ERR_ASM_MSP430_MISSINGFEATURE, ks_err_asm_msp430_missingfeature; - KS_ERR_ASM_MSP430_MNEMONICFAIL, ks_err_asm_msp430_mnemonicfail; - ] - end - diff --git a/bindings/ocaml/keystone.mli b/bindings/ocaml/keystone.mli index 9bc9f7a8..b4991fbd 100644 --- a/bindings/ocaml/keystone.mli +++ b/bindings/ocaml/keystone.mli @@ -17,8 +17,6 @@ module Types : sig | KS_ARCH_SPARC | KS_ARCH_SYSTEMZ | KS_ARCH_HEXAGON - | KS_ARCH_EVM - | KS_ARCH_MSP430 | KS_ARCH_MAX (** Keystone error types. Please see keystone.h for a full description. *) diff --git a/bindings/ocaml/test_bindings.ml b/bindings/ocaml/test_bindings.ml index f57041ab..e4bdd2b9 100644 --- a/bindings/ocaml/test_bindings.ml +++ b/bindings/ocaml/test_bindings.ml @@ -56,5 +56,3 @@ let _ = test_ks T.KS_ARCH_SPARC T.KS_MODE_SPARC32 ~endian:T.KS_MODE_BIG_ENDIAN "add %g1, %g2, %g3"; test_ks T.KS_ARCH_SYSTEMZ T.KS_MODE_BIG_ENDIAN "a %r0, 4095(%r15, %r1)" - - test_ks T.KS_ARCH_MSP430 T.KS_MODE_LITTLE_ENDIAN "and r12, r13" diff --git a/bindings/powershell/Keystone/Const/keystone_h.cs b/bindings/powershell/Keystone/Const/keystone_h.cs index fa544e72..cb7b01ed 100755 --- a/bindings/powershell/Keystone/Const/keystone_h.cs +++ b/bindings/powershell/Keystone/Const/keystone_h.cs @@ -13,8 +13,7 @@ KS_ARCH_SYSTEMZ = 7, KS_ARCH_HEXAGON = 8, KS_ARCH_EVM = 9, -KS_ARCH_MSP430 = 10, -KS_ARCH_MAX = 11, +KS_ARCH_MAX = 10, KS_MODE_LITTLE_ENDIAN = 0, KS_MODE_BIG_ENDIAN = 1073741824, KS_MODE_ARM = 1, diff --git a/bindings/powershell/Keystone/Keystone.psm1 b/bindings/powershell/Keystone/Keystone.psm1 index 17d7f968..c72eb429 100755 --- a/bindings/powershell/Keystone/Keystone.psm1 +++ b/bindings/powershell/Keystone/Keystone.psm1 @@ -71,8 +71,6 @@ function Get-KeystoneAssembly { 'KS_ARCH_SPARC', 'KS_ARCH_SYSTEMZ', 'KS_ARCH_HEXAGON', - 'KS_ARCH_EVM', - 'KS_ARCH_MSP430', 'KS_ARCH_MAX') ] [String]$Architecture, diff --git a/bindings/python/README.pypi-src b/bindings/python/README.pypi-src index b4dbd72c..603dd9da 100644 --- a/bindings/python/README.pypi-src +++ b/bindings/python/README.pypi-src @@ -16,7 +16,7 @@ package instead, which already includes the prebuilt "keystone.dll" inside. Keystone is a lightweight multi-platform, multi-architecture assembler framework. It offers some unparalleled features: -- Multi-architecture, with support for Arm, Arm64 (AArch64/Armv8), Hexagon, Mips, MSP430, PowerPC, Sparc, SystemZ & X86 (include 16/32/64bit). +- Multi-architecture, with support for Arm, Arm64 (AArch64/Armv8), Hexagon, Mips, PowerPC, Sparc, SystemZ & X86 (include 16/32/64bit). - Clean/simple/lightweight/intuitive architecture-neutral API. - Implemented in C/C++ languages, with bindings for Python, NodeJS, Ruby, Go, Rust, Haskell & OCaml available. - Native support for Windows & \*nix (with Mac OSX, Linux, *BSD & Solaris confirmed). diff --git a/bindings/python/keystone/__init__.py b/bindings/python/keystone/__init__.py index de0ea509..5e4a9663 100644 --- a/bindings/python/keystone/__init__.py +++ b/bindings/python/keystone/__init__.py @@ -1,5 +1,4 @@ # Keystone Python bindings, by Nguyen Anh Quynnh -from . import arm_const, arm64_const, mips_const, sparc_const, hexagon_const, systemz_const, ppc_const, x86_const,\ - evm_const, msp430_const +from . import arm_const, arm64_const, mips_const, sparc_const, hexagon_const, systemz_const, ppc_const, x86_const from .keystone_const import * from .keystone import Ks, ks_version, ks_arch_supported, version_bind, debug, KsError, __version__ diff --git a/bindings/python/keystone/keystone.py b/bindings/python/keystone/keystone.py index 03111840..295ceecb 100644 --- a/bindings/python/keystone/keystone.py +++ b/bindings/python/keystone/keystone.py @@ -4,8 +4,7 @@ if _python2: range = xrange -from . import arm_const, arm64_const, mips_const, sparc_const, hexagon_const, ppc_const, systemz_const, x86_const,\ - evm_const, msp430_const +from . import arm_const, arm64_const, mips_const, sparc_const, hexagon_const, ppc_const, systemz_const, x86_const, evm_const from .keystone_const import * from ctypes import * @@ -229,11 +228,10 @@ def asm(self, string, addr=0, as_bytes=False): # print out debugging info def debug(): - archs = { "arm": KS_ARCH_ARM, "arm64": KS_ARCH_ARM64, - "mips": KS_ARCH_MIPS, "sparc": KS_ARCH_SPARC, - "systemz": KS_ARCH_SYSTEMZ, "ppc": KS_ARCH_PPC, - "hexagon": KS_ARCH_HEXAGON, "x86": KS_ARCH_X86, - "evm": KS_ARCH_EVM, "msp430": KS_ARCH_MSP430 } + archs = { "arm": KS_ARCH_ARM, "arm64": KS_ARCH_ARM64, \ + "mips": KS_ARCH_MIPS, "sparc": KS_ARCH_SPARC, \ + "systemz": KS_ARCH_SYSTEMZ, "ppc": KS_ARCH_PPC, \ + "hexagon": KS_ARCH_HEXAGON, "x86": KS_ARCH_X86, 'evm': KS_ARCH_EVM } all_archs = "" keys = archs.keys() diff --git a/bindings/python/keystone/keystone_const.py b/bindings/python/keystone/keystone_const.py index d97deb24..9d975c1c 100644 --- a/bindings/python/keystone/keystone_const.py +++ b/bindings/python/keystone/keystone_const.py @@ -13,8 +13,7 @@ KS_ARCH_SYSTEMZ = 7 KS_ARCH_HEXAGON = 8 KS_ARCH_EVM = 9 -KS_ARCH_MSP430 = 10 -KS_ARCH_MAX = 11 +KS_ARCH_MAX = 10 KS_MODE_LITTLE_ENDIAN = 0 KS_MODE_BIG_ENDIAN = 1073741824 KS_MODE_ARM = 1 diff --git a/bindings/python/sample.py b/bindings/python/sample.py index 6ee9f889..2e2830ee 100755 --- a/bindings/python/sample.py +++ b/bindings/python/sample.py @@ -94,8 +94,5 @@ def sym_resolver(symbol, value): # SystemZ test_ks(KS_ARCH_SYSTEMZ, KS_MODE_BIG_ENDIAN, b"a %r0, 4095(%r15,%r1)") - # MSP430 - test_ks(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, b"and r12, r13") - # test symbol resolver test_sym_resolver() diff --git a/bindings/ruby/keystone_gem/lib/keystone/keystone_const.rb b/bindings/ruby/keystone_gem/lib/keystone/keystone_const.rb index c08659cd..abbde925 100644 --- a/bindings/ruby/keystone_gem/lib/keystone/keystone_const.rb +++ b/bindings/ruby/keystone_gem/lib/keystone/keystone_const.rb @@ -15,8 +15,7 @@ module Keystone KS_ARCH_SYSTEMZ = 7 KS_ARCH_HEXAGON = 8 KS_ARCH_EVM = 9 - KS_ARCH_MSP430 = 10 - KS_ARCH_MAX = 11 + KS_ARCH_MAX = 10 KS_MODE_LITTLE_ENDIAN = 0 KS_MODE_BIG_ENDIAN = 1073741824 KS_MODE_ARM = 1 diff --git a/bindings/ruby/sample.rb b/bindings/ruby/sample.rb index 3c096a8a..9839fb11 100755 --- a/bindings/ruby/sample.rb +++ b/bindings/ruby/sample.rb @@ -58,6 +58,3 @@ def test_ks(arch, mode, code, syntax=0) # SystemZ test_ks(KS_ARCH_SYSTEMZ, KS_MODE_BIG_ENDIAN, "a %r0, 4095(%r15,%r1)") - -# MSP430 -test_ks(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, "and r12, r13") diff --git a/bindings/rust/keystone-sys/src/keystone_const.rs b/bindings/rust/keystone-sys/src/keystone_const.rs index 20d31b76..c81f3240 100644 --- a/bindings/rust/keystone-sys/src/keystone_const.rs +++ b/bindings/rust/keystone-sys/src/keystone_const.rs @@ -42,8 +42,7 @@ pub enum Arch { SYSTEMZ = 7, HEXAGON = 8, EVM = 9, - MSP430 = 10, - MAX = 11, + MAX = 10, } #[repr(C)] diff --git a/bindings/vb6/Form1.frm b/bindings/vb6/Form1.frm index e70e2eda..4616d0ae 100644 --- a/bindings/vb6/Form1.frm +++ b/bindings/vb6/Form1.frm @@ -116,9 +116,6 @@ Private Sub Form_Load() ' SystemZ AddResult test_ks(KS_ARCH_SYSTEMZ, KS_MODE_BIG_ENDIAN, "a %r0, 4095(%r15,%r1)", 0, base) - - ' MSP430 - AddResult test_ks(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, "and r12, r13", 0, base) ' symbol resolver test (will enable once in stable release binaries not tested yet) 'AddResult test_ks(KS_ARCH_X86, KS_MODE_32, "jmp _l1; nop", 0, , base, True) diff --git a/bindings/vb6/mKeystone.bas b/bindings/vb6/mKeystone.bas index b5d207b2..f5fb7ac4 100644 --- a/bindings/vb6/mKeystone.bas +++ b/bindings/vb6/mKeystone.bas @@ -24,8 +24,6 @@ Public Enum ks_arch KS_ARCH_SPARC ' Sparc architecture KS_ARCH_SYSTEMZ ' SystemZ architecture (S390X) KS_ARCH_HEXAGON ' Hexagon architecture - KS_ARCH_EVM ' EVM architecture - KS_ARCH_MSP430 ' MSP430 architecture KS_ARCH_MAX End Enum @@ -341,8 +339,6 @@ Function ks_arch2str(v As ks_arch) As String If v = KS_ARCH_SPARC Then r = "KS_ARCH_SPARC" If v = KS_ARCH_SYSTEMZ Then r = "KS_ARCH_SYSTEMZ" If v = KS_ARCH_HEXAGON Then r = "KS_ARCH_HEXAGON" - If v = KS_ARCH_EVM Then r = "KS_ARCH_EVM" - If v = KS_ARCH_MSP430 Then r = "KS_ARCH_MSP430" If v = KS_ARCH_MAX Then r = "KS_ARCH_MAX" If Len(r) = 0 Then r = "Unknown: " & Hex(v) ks_arch2str = r From 7acf343ce62e1fda1cf8b11fff8b0549dc32a44d Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Wed, 2 Jan 2019 13:23:52 -0500 Subject: [PATCH 07/14] Remove added files as well --- .../Keystone.Net/Constants/EVMConstants.cs | 10 -------- .../Keystone.Net/Constants/MSP430Constants.cs | 10 -------- bindings/go/keystone/msp430_const.go | 9 ------- bindings/haskell/src/Keystone/CPU/Msp430.chs | 25 ------------------- bindings/nodejs/consts/msp430.js | 4 --- bindings/python/keystone/msp430_const.py | 4 --- .../keystone_gem/lib/keystone/msp430_const.rb | 7 ------ bindings/rust/keystone-sys/src/arm64_const.rs | 11 -------- bindings/rust/keystone-sys/src/arm_const.rs | 11 -------- bindings/rust/keystone-sys/src/evm_const.rs | 11 -------- .../rust/keystone-sys/src/hexagon_const.rs | 11 -------- bindings/rust/keystone-sys/src/mips_const.rs | 11 -------- .../rust/keystone-sys/src/msp430_const.rs | 11 -------- bindings/rust/keystone-sys/src/ppc_const.rs | 11 -------- bindings/rust/keystone-sys/src/sparc_const.rs | 11 -------- .../rust/keystone-sys/src/systemz_const.rs | 11 -------- bindings/rust/keystone-sys/src/x86_const.rs | 11 -------- 17 files changed, 179 deletions(-) delete mode 100644 bindings/csharp/Keystone.Net/Constants/EVMConstants.cs delete mode 100644 bindings/csharp/Keystone.Net/Constants/MSP430Constants.cs delete mode 100644 bindings/go/keystone/msp430_const.go delete mode 100644 bindings/haskell/src/Keystone/CPU/Msp430.chs delete mode 100644 bindings/nodejs/consts/msp430.js delete mode 100644 bindings/python/keystone/msp430_const.py delete mode 100644 bindings/ruby/keystone_gem/lib/keystone/msp430_const.rb delete mode 100644 bindings/rust/keystone-sys/src/arm64_const.rs delete mode 100644 bindings/rust/keystone-sys/src/arm_const.rs delete mode 100644 bindings/rust/keystone-sys/src/evm_const.rs delete mode 100644 bindings/rust/keystone-sys/src/hexagon_const.rs delete mode 100644 bindings/rust/keystone-sys/src/mips_const.rs delete mode 100644 bindings/rust/keystone-sys/src/msp430_const.rs delete mode 100644 bindings/rust/keystone-sys/src/ppc_const.rs delete mode 100644 bindings/rust/keystone-sys/src/sparc_const.rs delete mode 100644 bindings/rust/keystone-sys/src/systemz_const.rs delete mode 100644 bindings/rust/keystone-sys/src/x86_const.rs diff --git a/bindings/csharp/Keystone.Net/Constants/EVMConstants.cs b/bindings/csharp/Keystone.Net/Constants/EVMConstants.cs deleted file mode 100644 index 46d394ef..00000000 --- a/bindings/csharp/Keystone.Net/Constants/EVMConstants.cs +++ /dev/null @@ -1,10 +0,0 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [EVMConstants.cs] -namespace Keystone -{ - public enum EvmError : short - { - KS_ERR_ASM_EVM_INVALIDOPERAND = 512, - KS_ERR_ASM_EVM_MISSINGFEATURE = 513, - KS_ERR_ASM_EVM_MNEMONICFAIL = 514, - } -} \ No newline at end of file diff --git a/bindings/csharp/Keystone.Net/Constants/MSP430Constants.cs b/bindings/csharp/Keystone.Net/Constants/MSP430Constants.cs deleted file mode 100644 index e4e8d996..00000000 --- a/bindings/csharp/Keystone.Net/Constants/MSP430Constants.cs +++ /dev/null @@ -1,10 +0,0 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [MSP430Constants.cs] -namespace Keystone -{ - public enum Msp430Error : short - { - KS_ERR_ASM_MSP430_INVALIDOPERAND = 512, - KS_ERR_ASM_MSP430_MISSINGFEATURE = 513, - KS_ERR_ASM_MSP430_MNEMONICFAIL = 514, - } -} \ No newline at end of file diff --git a/bindings/go/keystone/msp430_const.go b/bindings/go/keystone/msp430_const.go deleted file mode 100644 index 986b45e1..00000000 --- a/bindings/go/keystone/msp430_const.go +++ /dev/null @@ -1,9 +0,0 @@ -package keystone -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.go] - -const ( - ERR_ASM_MSP430_INVALIDOPERAND Error = 512 - ERR_ASM_MSP430_MISSINGFEATURE Error = 513 - ERR_ASM_MSP430_MNEMONICFAIL Error = 514 -) - diff --git a/bindings/haskell/src/Keystone/CPU/Msp430.chs b/bindings/haskell/src/Keystone/CPU/Msp430.chs deleted file mode 100644 index 00bb021a..00000000 --- a/bindings/haskell/src/Keystone/CPU/Msp430.chs +++ /dev/null @@ -1,25 +0,0 @@ -{-# LANGUAGE ForeignFunctionInterface #-} - -{-| -Module : Keystone.CPU.Msp430 -Description : Definitions for the Msp430 architecture. -Copyright : (C) Trey Keown, 2018 -License : GPL-2 - -Definitions for the Msp430 architecture. --} -module Keystone.CPU.Msp430 - ( - Error(..) - ) where - -{# context lib = "keystone" #} - -#include - --- | Msp430 errors. -{# enum ks_err_asm_msp430 as Error - { underscoreToCase } - with prefix = "KS_ERR_ASM_MSP430_" - deriving (Show, Eq, Bounded) -#} diff --git a/bindings/nodejs/consts/msp430.js b/bindings/nodejs/consts/msp430.js deleted file mode 100644 index 87592e87..00000000 --- a/bindings/nodejs/consts/msp430.js +++ /dev/null @@ -1,4 +0,0 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.js] -module.exports.ERR_ASM_MSP430_INVALIDOPERAND = 512 -module.exports.ERR_ASM_MSP430_MISSINGFEATURE = 513 -module.exports.ERR_ASM_MSP430_MNEMONICFAIL = 514 diff --git a/bindings/python/keystone/msp430_const.py b/bindings/python/keystone/msp430_const.py deleted file mode 100644 index 16e155aa..00000000 --- a/bindings/python/keystone/msp430_const.py +++ /dev/null @@ -1,4 +0,0 @@ -# For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.py] -KS_ERR_ASM_MSP430_INVALIDOPERAND = 512 -KS_ERR_ASM_MSP430_MISSINGFEATURE = 513 -KS_ERR_ASM_MSP430_MNEMONICFAIL = 514 diff --git a/bindings/ruby/keystone_gem/lib/keystone/msp430_const.rb b/bindings/ruby/keystone_gem/lib/keystone/msp430_const.rb deleted file mode 100644 index b7a6a293..00000000 --- a/bindings/ruby/keystone_gem/lib/keystone/msp430_const.rb +++ /dev/null @@ -1,7 +0,0 @@ -# For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.rb] - -module Keystone - KS_ERR_ASM_MSP430_INVALIDOPERAND = 512 - KS_ERR_ASM_MSP430_MISSINGFEATURE = 513 - KS_ERR_ASM_MSP430_MNEMONICFAIL = 514 -end \ No newline at end of file diff --git a/bindings/rust/keystone-sys/src/arm64_const.rs b/bindings/rust/keystone-sys/src/arm64_const.rs deleted file mode 100644 index 6805da77..00000000 --- a/bindings/rust/keystone-sys/src/arm64_const.rs +++ /dev/null @@ -1,11 +0,0 @@ -#![allow(non_camel_case_types)] -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.rs] -use libc; -bitflags! { -#[repr(C)] - pub struct Error: u32 { - const ASM_ARM64_INVALIDOPERAND = 512; - const ASM_ARM64_MISSINGFEATURE = 513; - const ASM_ARM64_MNEMONICFAIL = 514; - } -} diff --git a/bindings/rust/keystone-sys/src/arm_const.rs b/bindings/rust/keystone-sys/src/arm_const.rs deleted file mode 100644 index 8ad5deff..00000000 --- a/bindings/rust/keystone-sys/src/arm_const.rs +++ /dev/null @@ -1,11 +0,0 @@ -#![allow(non_camel_case_types)] -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.rs] -use libc; -bitflags! { -#[repr(C)] - pub struct Error: u32 { - const ASM_ARM_INVALIDOPERAND = 512; - const ASM_ARM_MISSINGFEATURE = 513; - const ASM_ARM_MNEMONICFAIL = 514; - } -} diff --git a/bindings/rust/keystone-sys/src/evm_const.rs b/bindings/rust/keystone-sys/src/evm_const.rs deleted file mode 100644 index 30326484..00000000 --- a/bindings/rust/keystone-sys/src/evm_const.rs +++ /dev/null @@ -1,11 +0,0 @@ -#![allow(non_camel_case_types)] -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [evm_const.rs] -use libc; -bitflags! { -#[repr(C)] - pub struct Error: u32 { - const ASM_EVM_INVALIDOPERAND = 512; - const ASM_EVM_MISSINGFEATURE = 513; - const ASM_EVM_MNEMONICFAIL = 514; - } -} diff --git a/bindings/rust/keystone-sys/src/hexagon_const.rs b/bindings/rust/keystone-sys/src/hexagon_const.rs deleted file mode 100644 index 2b3138dc..00000000 --- a/bindings/rust/keystone-sys/src/hexagon_const.rs +++ /dev/null @@ -1,11 +0,0 @@ -#![allow(non_camel_case_types)] -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hexagon_const.rs] -use libc; -bitflags! { -#[repr(C)] - pub struct Error: u32 { - const ASM_HEXAGON_INVALIDOPERAND = 512; - const ASM_HEXAGON_MISSINGFEATURE = 513; - const ASM_HEXAGON_MNEMONICFAIL = 514; - } -} diff --git a/bindings/rust/keystone-sys/src/mips_const.rs b/bindings/rust/keystone-sys/src/mips_const.rs deleted file mode 100644 index b3c72bd6..00000000 --- a/bindings/rust/keystone-sys/src/mips_const.rs +++ /dev/null @@ -1,11 +0,0 @@ -#![allow(non_camel_case_types)] -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.rs] -use libc; -bitflags! { -#[repr(C)] - pub struct Error: u32 { - const ASM_MIPS_INVALIDOPERAND = 512; - const ASM_MIPS_MISSINGFEATURE = 513; - const ASM_MIPS_MNEMONICFAIL = 514; - } -} diff --git a/bindings/rust/keystone-sys/src/msp430_const.rs b/bindings/rust/keystone-sys/src/msp430_const.rs deleted file mode 100644 index 8b299e48..00000000 --- a/bindings/rust/keystone-sys/src/msp430_const.rs +++ /dev/null @@ -1,11 +0,0 @@ -#![allow(non_camel_case_types)] -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.rs] -use libc; -bitflags! { -#[repr(C)] - pub struct Error: u32 { - const ASM_MSP430_INVALIDOPERAND = 512; - const ASM_MSP430_MISSINGFEATURE = 513; - const ASM_MSP430_MNEMONICFAIL = 514; - } -} diff --git a/bindings/rust/keystone-sys/src/ppc_const.rs b/bindings/rust/keystone-sys/src/ppc_const.rs deleted file mode 100644 index caeea646..00000000 --- a/bindings/rust/keystone-sys/src/ppc_const.rs +++ /dev/null @@ -1,11 +0,0 @@ -#![allow(non_camel_case_types)] -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.rs] -use libc; -bitflags! { -#[repr(C)] - pub struct Error: u32 { - const ASM_PPC_INVALIDOPERAND = 512; - const ASM_PPC_MISSINGFEATURE = 513; - const ASM_PPC_MNEMONICFAIL = 514; - } -} diff --git a/bindings/rust/keystone-sys/src/sparc_const.rs b/bindings/rust/keystone-sys/src/sparc_const.rs deleted file mode 100644 index dd544ae1..00000000 --- a/bindings/rust/keystone-sys/src/sparc_const.rs +++ /dev/null @@ -1,11 +0,0 @@ -#![allow(non_camel_case_types)] -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.rs] -use libc; -bitflags! { -#[repr(C)] - pub struct Error: u32 { - const ASM_SPARC_INVALIDOPERAND = 512; - const ASM_SPARC_MISSINGFEATURE = 513; - const ASM_SPARC_MNEMONICFAIL = 514; - } -} diff --git a/bindings/rust/keystone-sys/src/systemz_const.rs b/bindings/rust/keystone-sys/src/systemz_const.rs deleted file mode 100644 index d2a8a1f3..00000000 --- a/bindings/rust/keystone-sys/src/systemz_const.rs +++ /dev/null @@ -1,11 +0,0 @@ -#![allow(non_camel_case_types)] -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [systemz_const.rs] -use libc; -bitflags! { -#[repr(C)] - pub struct Error: u32 { - const ASM_SYSTEMZ_INVALIDOPERAND = 512; - const ASM_SYSTEMZ_MISSINGFEATURE = 513; - const ASM_SYSTEMZ_MNEMONICFAIL = 514; - } -} diff --git a/bindings/rust/keystone-sys/src/x86_const.rs b/bindings/rust/keystone-sys/src/x86_const.rs deleted file mode 100644 index 2db5ce54..00000000 --- a/bindings/rust/keystone-sys/src/x86_const.rs +++ /dev/null @@ -1,11 +0,0 @@ -#![allow(non_camel_case_types)] -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.rs] -use libc; -bitflags! { -#[repr(C)] - pub struct Error: u32 { - const ASM_X86_INVALIDOPERAND = 512; - const ASM_X86_MISSINGFEATURE = 513; - const ASM_X86_MNEMONICFAIL = 514; - } -} From 4a53811b025629bc67da0a022024d0e51f192984 Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Wed, 2 Jan 2019 13:41:34 -0500 Subject: [PATCH 08/14] Add back changes for bindings created by const_gnerator --- bindings/Makefile | 5 ++ bindings/const_generator.py | 55 +++++++------ .../Keystone.Net/Constants/ARM64Constants.cs | 2 +- .../Keystone.Net/Constants/ARMConstants.cs | 2 +- .../Keystone.Net/Constants/EVMConstants.cs | 10 +++ .../Constants/HexagonConstants.cs | 2 +- .../Constants/KeystoneConstants.cs | 80 ++++++++++--------- .../Keystone.Net/Constants/MSP430Constants.cs | 10 +++ .../Keystone.Net/Constants/MipsConstants.cs | 2 +- .../Keystone.Net/Constants/PPCConstants.cs | 2 +- .../Keystone.Net/Constants/SPARCConstants.cs | 2 +- .../Constants/SystemZConstants.cs | 2 +- .../Keystone.Net/Constants/X86Constants.cs | 2 +- bindings/go/keystone/keystone_const.go | 3 +- bindings/go/keystone/msp430_const.go | 9 +++ .../powershell/Keystone/Const/keystone_h.cs | 3 +- bindings/powershell/Keystone/Keystone.psm1 | 2 + bindings/python/README.pypi-src | 2 +- bindings/python/keystone/__init__.py | 3 +- bindings/python/keystone/keystone.py | 12 +-- bindings/python/keystone/keystone_const.py | 3 +- bindings/python/keystone/msp430_const.py | 4 + bindings/python/sample.py | 3 + bindings/rust/keystone-sys/src/arm64_const.rs | 11 +++ bindings/rust/keystone-sys/src/arm_const.rs | 11 +++ bindings/rust/keystone-sys/src/evm_const.rs | 11 +++ .../rust/keystone-sys/src/hexagon_const.rs | 11 +++ .../rust/keystone-sys/src/keystone_const.rs | 3 +- bindings/rust/keystone-sys/src/mips_const.rs | 11 +++ .../rust/keystone-sys/src/msp430_const.rs | 11 +++ bindings/rust/keystone-sys/src/ppc_const.rs | 11 +++ bindings/rust/keystone-sys/src/sparc_const.rs | 11 +++ .../rust/keystone-sys/src/systemz_const.rs | 11 +++ bindings/rust/keystone-sys/src/x86_const.rs | 11 +++ 34 files changed, 250 insertions(+), 83 deletions(-) create mode 100644 bindings/csharp/Keystone.Net/Constants/EVMConstants.cs create mode 100644 bindings/csharp/Keystone.Net/Constants/MSP430Constants.cs create mode 100644 bindings/go/keystone/msp430_const.go create mode 100644 bindings/python/keystone/msp430_const.py create mode 100644 bindings/rust/keystone-sys/src/arm64_const.rs create mode 100644 bindings/rust/keystone-sys/src/arm_const.rs create mode 100644 bindings/rust/keystone-sys/src/evm_const.rs create mode 100644 bindings/rust/keystone-sys/src/hexagon_const.rs create mode 100644 bindings/rust/keystone-sys/src/mips_const.rs create mode 100644 bindings/rust/keystone-sys/src/msp430_const.rs create mode 100644 bindings/rust/keystone-sys/src/ppc_const.rs create mode 100644 bindings/rust/keystone-sys/src/sparc_const.rs create mode 100644 bindings/rust/keystone-sys/src/systemz_const.rs create mode 100644 bindings/rust/keystone-sys/src/x86_const.rs diff --git a/bindings/Makefile b/bindings/Makefile index 85799b6a..ec88cfab 100644 --- a/bindings/Makefile +++ b/bindings/Makefile @@ -7,6 +7,7 @@ DIFF = diff -u -w SAMPLE_ARM = $(TMPDIR)/sample_arm SAMPLE_ARM64 = $(TMPDIR)/sample_arm64 SAMPLE_MIPS = $(TMPDIR)/sample_mips +SAMPLE_MSP430 = $(TMPDIR)/sample_msp430 SAMPLE_M68K = $(TMPDIR)/sample_m68k SAMPLE_SPARC = $(TMPDIR)/sample_sparc SAMPLE_X86 = $(TMPDIR)/sample_x86 @@ -20,6 +21,7 @@ all: python const_generator.py go cd ruby && $(MAKE) gen_const python const_generator.py powershell + python const_generator.py csharp samples: expected python @@ -31,6 +33,7 @@ expected: ../samples/sample_arm > $(SAMPLE_ARM)_e ../samples/sample_arm64 > $(SAMPLE_ARM64)_e ../samples/sample_mips > $(SAMPLE_MIPS)_e + ../samples/sample_msp430 > $(SAMPLE_MSP430)_e ../samples/sample_sparc > $(SAMPLE_SPARC)_e ../samples/sample_m68k > $(SAMPLE_M68K)_e ../samples/sample_x86 > $(SAMPLE_X86)_e @@ -40,6 +43,7 @@ python: FORCE python python/sample_arm.py > $(SAMPLE_ARM)_o python python/sample_arm64.py > $(SAMPLE_ARM64)_o python python/sample_mips.py > $(SAMPLE_MIPS)_o + python python/sample_msp430.py > $(SAMPLE_MSP430)_o python python/sample_sparc.py > $(SAMPLE_SPARC)_o python python/sample_m68k.py > $(SAMPLE_M68K)_o python python/sample_x86.py > $(SAMPLE_X86)_o @@ -64,6 +68,7 @@ sample_diff: FORCE $(DIFF) $(SAMPLE_ARM)_e $(SAMPLE_ARM)_o $(DIFF) $(SAMPLE_ARM64)_e $(SAMPLE_ARM64)_o $(DIFF) $(SAMPLE_MIPS)_e $(SAMPLE_MIPS)_o + $(DIFF) $(SAMPLE_MSP430)_e $(SAMPLE_MSP430)_o $(DIFF) $(SAMPLE_SPARC)_e $(SAMPLE_SPARC)_o $(DIFF) $(SAMPLE_M68K)_e $(SAMPLE_M68K)_o $(DIFF) $(SAMPLE_X86)_e $(SAMPLE_X86)_o diff --git a/bindings/const_generator.py b/bindings/const_generator.py index db69d55a..7f5b5113 100644 --- a/bindings/const_generator.py +++ b/bindings/const_generator.py @@ -8,7 +8,7 @@ # NOTE: this reflects the value of KS_ERR_ASM_xxx in keystone.h ks_err_val = { 'KS_ERR_ASM': '128', 'KS_ERR_ASM_ARCH': '512' } -include = [ 'arm.h', 'arm64.h', 'mips.h', 'x86.h', 'sparc.h', 'ppc.h', 'systemz.h', 'hexagon.h', 'evm.h', 'keystone.h' ] +include = [ 'arm.h', 'arm64.h', 'mips.h', 'x86.h', 'sparc.h', 'ppc.h', 'systemz.h', 'hexagon.h', 'evm.h', 'msp430.h', 'keystone.h' ] def CamelCase(s): # return re.sub(r'(\w)+\_?', lambda m:m.group(0).capitalize(), s) @@ -35,15 +35,16 @@ def CamelCase(s): 'header': "#![allow(non_camel_case_types)]\n// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.rs]\nuse libc;\n", 'footer': "", # prefixes for constant filenames of all archs - case sensitive - 'arm.h': 'keystone', - 'arm64.h': 'keystone', - 'mips.h': 'keystone', - 'x86.h': 'keystone', - 'sparc.h': 'keystone', - 'systemz.h': 'keystone', - 'ppc.h': 'keystone', - 'hexagon.h': 'keystone', - 'evm.h': 'keystone', + 'arm.h': 'arm', + 'arm64.h': 'arm64', + 'mips.h': 'mips', + 'msp430.h': 'msp430', + 'x86.h': 'x86', + 'sparc.h': 'sparc', + 'systemz.h': 'systemz', + 'ppc.h': 'ppc', + 'hexagon.h': 'hexagon', + 'evm.h': 'evm', 'keystone.h': 'keystone', 'comment_open': '/*', 'comment_close': '*/', @@ -110,6 +111,7 @@ def CamelCase(s): 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', + 'msp430.h': 'msp430', 'x86.h': 'x86', 'sparc.h': 'sparc', 'systemz.h': 'systemz', @@ -172,6 +174,7 @@ def CamelCase(s): 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', + 'msp430.h': 'msp430', 'x86.h': 'x86', 'sparc.h': 'sparc', 'systemz.h': 'systemz', @@ -197,6 +200,7 @@ def CamelCase(s): 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', + 'msp430.h': 'msp430', 'x86.h': 'x86', 'sparc.h': 'sparc', 'systemz.h': 'systemz', @@ -222,6 +226,7 @@ def CamelCase(s): 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', + 'msp430.h': 'msp430', 'x86.h': 'x86', 'sparc.h': 'sparc', 'systemz.h': 'systemz', @@ -240,34 +245,34 @@ def CamelCase(s): ] }, 'csharp': { - 'header': "// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%sConstants.cs]\nnamespace KeystoneNET\n{", + 'header': "// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%sConstants.cs]\nnamespace Keystone\n{", 'footer': "}", - 'out_file': './csharp/KeystoneNET/KeystoneNET/Constants/%sConstants.cs', + 'out_file': './csharp/Keystone.NET/Constants/%sConstants.cs', # prefixes for constant filenames of all archs - case sensitive - 'keystone.h': 'keystone', - 'arm.h': 'arm', - 'arm64.h': 'arm64', - 'mips.h': 'mips', - 'x86.h': 'x86', - 'sparc.h': 'sparc', - 'systemz.h': 'systemz', - 'ppc.h': 'ppc', - 'hexagon.h': 'hexagon', - 'evm.h': 'evm', - 'keystone.h': 'keystone', + 'keystone.h': 'Keystone', + 'arm.h': 'ARM', + 'arm64.h': 'ARM64', + 'mips.h': 'Mips', + 'msp430.h': 'MSP430', + 'x86.h': 'X86', + 'sparc.h': 'SPARC', + 'systemz.h': 'SystemZ', + 'ppc.h': 'PPC', + 'hexagon.h': 'Hexagon', + 'evm.h': 'EVM', 'comment_open': '//', 'comment_close': '', 'rules': [ { 'regex': r'(ARCH)_.*', - 'pre': '\n\tpublic enum KeystoneArchitecture : int\n\t{{\n', + 'pre': '\n\tpublic enum Architecture : int\n\t{{\n', 'post': '\t}', 'line_format': '\t\tKS_{0} = {1},\n', 'fn': (lambda x: x), }, { 'regex': r'(MODE)_.*', - 'pre': '\n\tpublic enum KeystoneMode : uint\n\t{{\n', + 'pre': '\n\tpublic enum Mode : uint\n\t{{\n', 'post': '\t}', 'line_format': '\t\tKS_{0} = {1},\n', 'fn': (lambda x: x), diff --git a/bindings/csharp/Keystone.Net/Constants/ARM64Constants.cs b/bindings/csharp/Keystone.Net/Constants/ARM64Constants.cs index 33eb5458..df6cf463 100644 --- a/bindings/csharp/Keystone.Net/Constants/ARM64Constants.cs +++ b/bindings/csharp/Keystone.Net/Constants/ARM64Constants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64Constants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ARM64Constants.cs] namespace Keystone { public enum Arm64Error : short diff --git a/bindings/csharp/Keystone.Net/Constants/ARMConstants.cs b/bindings/csharp/Keystone.Net/Constants/ARMConstants.cs index f8d0c273..60b44151 100644 --- a/bindings/csharp/Keystone.Net/Constants/ARMConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/ARMConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [armConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ARMConstants.cs] namespace Keystone { public enum ArmError : short diff --git a/bindings/csharp/Keystone.Net/Constants/EVMConstants.cs b/bindings/csharp/Keystone.Net/Constants/EVMConstants.cs new file mode 100644 index 00000000..46d394ef --- /dev/null +++ b/bindings/csharp/Keystone.Net/Constants/EVMConstants.cs @@ -0,0 +1,10 @@ +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [EVMConstants.cs] +namespace Keystone +{ + public enum EvmError : short + { + KS_ERR_ASM_EVM_INVALIDOPERAND = 512, + KS_ERR_ASM_EVM_MISSINGFEATURE = 513, + KS_ERR_ASM_EVM_MNEMONICFAIL = 514, + } +} \ No newline at end of file diff --git a/bindings/csharp/Keystone.Net/Constants/HexagonConstants.cs b/bindings/csharp/Keystone.Net/Constants/HexagonConstants.cs index bfb0da9f..673a66f4 100644 --- a/bindings/csharp/Keystone.Net/Constants/HexagonConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/HexagonConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hexagonConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [HexagonConstants.cs] namespace Keystone { public enum HexagonError : short diff --git a/bindings/csharp/Keystone.Net/Constants/KeystoneConstants.cs b/bindings/csharp/Keystone.Net/Constants/KeystoneConstants.cs index 124e5247..04cd530a 100644 --- a/bindings/csharp/Keystone.Net/Constants/KeystoneConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/KeystoneConstants.cs @@ -3,38 +3,40 @@ namespace Keystone { public enum Architecture : int { - ARM = 1, - ARM64 = 2, - MIPS = 3, - X86 = 4, - PPC = 5, - SPARC = 6, - SYSTEMZ = 7, - HEXAGON = 8, - MAX = 9, + KS_ARCH_ARM = 1, + KS_ARCH_ARM64 = 2, + KS_ARCH_MIPS = 3, + KS_ARCH_X86 = 4, + KS_ARCH_PPC = 5, + KS_ARCH_SPARC = 6, + KS_ARCH_SYSTEMZ = 7, + KS_ARCH_HEXAGON = 8, + KS_ARCH_EVM = 9, + KS_ARCH_MSP430 = 10, + KS_ARCH_MAX = 11, } public enum Mode : uint { - LITTLE_ENDIAN = 0, - BIG_ENDIAN = 1073741824, - ARM = 1, - THUMB = 16, - V8 = 64, - MICRO = 16, - MIPS3 = 32, - MIPS32R6 = 64, - MIPS32 = 4, - MIPS64 = 8, - X16 = 2, - X32 = 4, - X64 = 8, - PPC32 = 4, - PPC64 = 8, - QPX = 16, - SPARC32 = 4, - SPARC64 = 8, - V9 = 16, + KS_MODE_LITTLE_ENDIAN = 0, + KS_MODE_BIG_ENDIAN = 1073741824, + KS_MODE_ARM = 1, + KS_MODE_THUMB = 16, + KS_MODE_V8 = 64, + KS_MODE_MICRO = 16, + KS_MODE_MIPS3 = 32, + KS_MODE_MIPS32R6 = 64, + KS_MODE_MIPS32 = 4, + KS_MODE_MIPS64 = 8, + KS_MODE_16 = 2, + KS_MODE_32 = 4, + KS_MODE_64 = 8, + KS_MODE_PPC32 = 4, + KS_MODE_PPC64 = 8, + KS_MODE_QPX = 16, + KS_MODE_SPARC32 = 4, + KS_MODE_SPARC64 = 8, + KS_MODE_V9 = 16, } public enum KeystoneError : short @@ -86,22 +88,22 @@ public enum KeystoneError : short KS_ERR_ASM_FRAGMENT_INVALID = 163, KS_ERR_ASM_INVALIDOPERAND = 512, KS_ERR_ASM_MISSINGFEATURE = 513, - KS_ERR_ASM_MNEMONICFAIL = 514 + KS_ERR_ASM_MNEMONICFAIL = 514, } - public enum OptionType : int + public enum KeystoneOptionType : short { - SYNTAX = 1, - SYM_RESOLVER = 2, + KS_OPT_SYNTAX = 1, + KS_OPT_SYM_RESOLVER = 2, } - public enum OptionValue : short + public enum KeystoneOptionValue : short { - SYNTAX_INTEL = 1, - SYNTAX_ATT = 2, - SYNTAX_NASM = 4, - SYNTAX_MASM = 8, - SYNTAX_GAS = 16, - SYNTAX_RADIX16 = 32 + KS_OPT_SYNTAX_INTEL = 1, + KS_OPT_SYNTAX_ATT = 2, + KS_OPT_SYNTAX_NASM = 4, + KS_OPT_SYNTAX_MASM = 8, + KS_OPT_SYNTAX_GAS = 16, + KS_OPT_SYNTAX_RADIX16 = 32, } } \ No newline at end of file diff --git a/bindings/csharp/Keystone.Net/Constants/MSP430Constants.cs b/bindings/csharp/Keystone.Net/Constants/MSP430Constants.cs new file mode 100644 index 00000000..e4e8d996 --- /dev/null +++ b/bindings/csharp/Keystone.Net/Constants/MSP430Constants.cs @@ -0,0 +1,10 @@ +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [MSP430Constants.cs] +namespace Keystone +{ + public enum Msp430Error : short + { + KS_ERR_ASM_MSP430_INVALIDOPERAND = 512, + KS_ERR_ASM_MSP430_MISSINGFEATURE = 513, + KS_ERR_ASM_MSP430_MNEMONICFAIL = 514, + } +} \ No newline at end of file diff --git a/bindings/csharp/Keystone.Net/Constants/MipsConstants.cs b/bindings/csharp/Keystone.Net/Constants/MipsConstants.cs index 99be03dc..7a6a2b78 100644 --- a/bindings/csharp/Keystone.Net/Constants/MipsConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/MipsConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mipsConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [MipsConstants.cs] namespace Keystone { public enum MipsError : short diff --git a/bindings/csharp/Keystone.Net/Constants/PPCConstants.cs b/bindings/csharp/Keystone.Net/Constants/PPCConstants.cs index 601585a7..4256560a 100644 --- a/bindings/csharp/Keystone.Net/Constants/PPCConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/PPCConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppcConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [PPCConstants.cs] namespace Keystone { public enum PpcError : short diff --git a/bindings/csharp/Keystone.Net/Constants/SPARCConstants.cs b/bindings/csharp/Keystone.Net/Constants/SPARCConstants.cs index 6de93d20..4b77d77c 100644 --- a/bindings/csharp/Keystone.Net/Constants/SPARCConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/SPARCConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparcConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [SPARCConstants.cs] namespace Keystone { public enum SparcError : short diff --git a/bindings/csharp/Keystone.Net/Constants/SystemZConstants.cs b/bindings/csharp/Keystone.Net/Constants/SystemZConstants.cs index d2b61320..3bb58254 100644 --- a/bindings/csharp/Keystone.Net/Constants/SystemZConstants.cs +++ b/bindings/csharp/Keystone.Net/Constants/SystemZConstants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [systemzConstants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [SystemZConstants.cs] namespace Keystone { public enum SystemzError : short diff --git a/bindings/csharp/Keystone.Net/Constants/X86Constants.cs b/bindings/csharp/Keystone.Net/Constants/X86Constants.cs index 79743f7d..7d33e988 100644 --- a/bindings/csharp/Keystone.Net/Constants/X86Constants.cs +++ b/bindings/csharp/Keystone.Net/Constants/X86Constants.cs @@ -1,4 +1,4 @@ -// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86Constants.cs] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [X86Constants.cs] namespace Keystone { public enum X86Error : short diff --git a/bindings/go/keystone/keystone_const.go b/bindings/go/keystone/keystone_const.go index f78837c0..0e07b785 100644 --- a/bindings/go/keystone/keystone_const.go +++ b/bindings/go/keystone/keystone_const.go @@ -38,7 +38,8 @@ const ( ARCH_SYSTEMZ Architecture = 7 ARCH_HEXAGON Architecture = 8 ARCH_EVM Architecture = 9 - ARCH_MAX Architecture = 10 + ARCH_MSP430 Architecture = 10 + ARCH_MAX Architecture = 11 ) const ( diff --git a/bindings/go/keystone/msp430_const.go b/bindings/go/keystone/msp430_const.go new file mode 100644 index 00000000..986b45e1 --- /dev/null +++ b/bindings/go/keystone/msp430_const.go @@ -0,0 +1,9 @@ +package keystone +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.go] + +const ( + ERR_ASM_MSP430_INVALIDOPERAND Error = 512 + ERR_ASM_MSP430_MISSINGFEATURE Error = 513 + ERR_ASM_MSP430_MNEMONICFAIL Error = 514 +) + diff --git a/bindings/powershell/Keystone/Const/keystone_h.cs b/bindings/powershell/Keystone/Const/keystone_h.cs index cb7b01ed..fa544e72 100755 --- a/bindings/powershell/Keystone/Const/keystone_h.cs +++ b/bindings/powershell/Keystone/Const/keystone_h.cs @@ -13,7 +13,8 @@ KS_ARCH_SYSTEMZ = 7, KS_ARCH_HEXAGON = 8, KS_ARCH_EVM = 9, -KS_ARCH_MAX = 10, +KS_ARCH_MSP430 = 10, +KS_ARCH_MAX = 11, KS_MODE_LITTLE_ENDIAN = 0, KS_MODE_BIG_ENDIAN = 1073741824, KS_MODE_ARM = 1, diff --git a/bindings/powershell/Keystone/Keystone.psm1 b/bindings/powershell/Keystone/Keystone.psm1 index c72eb429..17d7f968 100755 --- a/bindings/powershell/Keystone/Keystone.psm1 +++ b/bindings/powershell/Keystone/Keystone.psm1 @@ -71,6 +71,8 @@ function Get-KeystoneAssembly { 'KS_ARCH_SPARC', 'KS_ARCH_SYSTEMZ', 'KS_ARCH_HEXAGON', + 'KS_ARCH_EVM', + 'KS_ARCH_MSP430', 'KS_ARCH_MAX') ] [String]$Architecture, diff --git a/bindings/python/README.pypi-src b/bindings/python/README.pypi-src index 603dd9da..b4dbd72c 100644 --- a/bindings/python/README.pypi-src +++ b/bindings/python/README.pypi-src @@ -16,7 +16,7 @@ package instead, which already includes the prebuilt "keystone.dll" inside. Keystone is a lightweight multi-platform, multi-architecture assembler framework. It offers some unparalleled features: -- Multi-architecture, with support for Arm, Arm64 (AArch64/Armv8), Hexagon, Mips, PowerPC, Sparc, SystemZ & X86 (include 16/32/64bit). +- Multi-architecture, with support for Arm, Arm64 (AArch64/Armv8), Hexagon, Mips, MSP430, PowerPC, Sparc, SystemZ & X86 (include 16/32/64bit). - Clean/simple/lightweight/intuitive architecture-neutral API. - Implemented in C/C++ languages, with bindings for Python, NodeJS, Ruby, Go, Rust, Haskell & OCaml available. - Native support for Windows & \*nix (with Mac OSX, Linux, *BSD & Solaris confirmed). diff --git a/bindings/python/keystone/__init__.py b/bindings/python/keystone/__init__.py index 5e4a9663..de0ea509 100644 --- a/bindings/python/keystone/__init__.py +++ b/bindings/python/keystone/__init__.py @@ -1,4 +1,5 @@ # Keystone Python bindings, by Nguyen Anh Quynnh -from . import arm_const, arm64_const, mips_const, sparc_const, hexagon_const, systemz_const, ppc_const, x86_const +from . import arm_const, arm64_const, mips_const, sparc_const, hexagon_const, systemz_const, ppc_const, x86_const,\ + evm_const, msp430_const from .keystone_const import * from .keystone import Ks, ks_version, ks_arch_supported, version_bind, debug, KsError, __version__ diff --git a/bindings/python/keystone/keystone.py b/bindings/python/keystone/keystone.py index 295ceecb..03111840 100644 --- a/bindings/python/keystone/keystone.py +++ b/bindings/python/keystone/keystone.py @@ -4,7 +4,8 @@ if _python2: range = xrange -from . import arm_const, arm64_const, mips_const, sparc_const, hexagon_const, ppc_const, systemz_const, x86_const, evm_const +from . import arm_const, arm64_const, mips_const, sparc_const, hexagon_const, ppc_const, systemz_const, x86_const,\ + evm_const, msp430_const from .keystone_const import * from ctypes import * @@ -228,10 +229,11 @@ def asm(self, string, addr=0, as_bytes=False): # print out debugging info def debug(): - archs = { "arm": KS_ARCH_ARM, "arm64": KS_ARCH_ARM64, \ - "mips": KS_ARCH_MIPS, "sparc": KS_ARCH_SPARC, \ - "systemz": KS_ARCH_SYSTEMZ, "ppc": KS_ARCH_PPC, \ - "hexagon": KS_ARCH_HEXAGON, "x86": KS_ARCH_X86, 'evm': KS_ARCH_EVM } + archs = { "arm": KS_ARCH_ARM, "arm64": KS_ARCH_ARM64, + "mips": KS_ARCH_MIPS, "sparc": KS_ARCH_SPARC, + "systemz": KS_ARCH_SYSTEMZ, "ppc": KS_ARCH_PPC, + "hexagon": KS_ARCH_HEXAGON, "x86": KS_ARCH_X86, + "evm": KS_ARCH_EVM, "msp430": KS_ARCH_MSP430 } all_archs = "" keys = archs.keys() diff --git a/bindings/python/keystone/keystone_const.py b/bindings/python/keystone/keystone_const.py index 9d975c1c..d97deb24 100644 --- a/bindings/python/keystone/keystone_const.py +++ b/bindings/python/keystone/keystone_const.py @@ -13,7 +13,8 @@ KS_ARCH_SYSTEMZ = 7 KS_ARCH_HEXAGON = 8 KS_ARCH_EVM = 9 -KS_ARCH_MAX = 10 +KS_ARCH_MSP430 = 10 +KS_ARCH_MAX = 11 KS_MODE_LITTLE_ENDIAN = 0 KS_MODE_BIG_ENDIAN = 1073741824 KS_MODE_ARM = 1 diff --git a/bindings/python/keystone/msp430_const.py b/bindings/python/keystone/msp430_const.py new file mode 100644 index 00000000..16e155aa --- /dev/null +++ b/bindings/python/keystone/msp430_const.py @@ -0,0 +1,4 @@ +# For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.py] +KS_ERR_ASM_MSP430_INVALIDOPERAND = 512 +KS_ERR_ASM_MSP430_MISSINGFEATURE = 513 +KS_ERR_ASM_MSP430_MNEMONICFAIL = 514 diff --git a/bindings/python/sample.py b/bindings/python/sample.py index 2e2830ee..6ee9f889 100755 --- a/bindings/python/sample.py +++ b/bindings/python/sample.py @@ -94,5 +94,8 @@ def sym_resolver(symbol, value): # SystemZ test_ks(KS_ARCH_SYSTEMZ, KS_MODE_BIG_ENDIAN, b"a %r0, 4095(%r15,%r1)") + # MSP430 + test_ks(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, b"and r12, r13") + # test symbol resolver test_sym_resolver() diff --git a/bindings/rust/keystone-sys/src/arm64_const.rs b/bindings/rust/keystone-sys/src/arm64_const.rs new file mode 100644 index 00000000..6805da77 --- /dev/null +++ b/bindings/rust/keystone-sys/src/arm64_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_ARM64_INVALIDOPERAND = 512; + const ASM_ARM64_MISSINGFEATURE = 513; + const ASM_ARM64_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/arm_const.rs b/bindings/rust/keystone-sys/src/arm_const.rs new file mode 100644 index 00000000..8ad5deff --- /dev/null +++ b/bindings/rust/keystone-sys/src/arm_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_ARM_INVALIDOPERAND = 512; + const ASM_ARM_MISSINGFEATURE = 513; + const ASM_ARM_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/evm_const.rs b/bindings/rust/keystone-sys/src/evm_const.rs new file mode 100644 index 00000000..30326484 --- /dev/null +++ b/bindings/rust/keystone-sys/src/evm_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [evm_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_EVM_INVALIDOPERAND = 512; + const ASM_EVM_MISSINGFEATURE = 513; + const ASM_EVM_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/hexagon_const.rs b/bindings/rust/keystone-sys/src/hexagon_const.rs new file mode 100644 index 00000000..2b3138dc --- /dev/null +++ b/bindings/rust/keystone-sys/src/hexagon_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hexagon_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_HEXAGON_INVALIDOPERAND = 512; + const ASM_HEXAGON_MISSINGFEATURE = 513; + const ASM_HEXAGON_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/keystone_const.rs b/bindings/rust/keystone-sys/src/keystone_const.rs index c81f3240..20d31b76 100644 --- a/bindings/rust/keystone-sys/src/keystone_const.rs +++ b/bindings/rust/keystone-sys/src/keystone_const.rs @@ -42,7 +42,8 @@ pub enum Arch { SYSTEMZ = 7, HEXAGON = 8, EVM = 9, - MAX = 10, + MSP430 = 10, + MAX = 11, } #[repr(C)] diff --git a/bindings/rust/keystone-sys/src/mips_const.rs b/bindings/rust/keystone-sys/src/mips_const.rs new file mode 100644 index 00000000..b3c72bd6 --- /dev/null +++ b/bindings/rust/keystone-sys/src/mips_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_MIPS_INVALIDOPERAND = 512; + const ASM_MIPS_MISSINGFEATURE = 513; + const ASM_MIPS_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/msp430_const.rs b/bindings/rust/keystone-sys/src/msp430_const.rs new file mode 100644 index 00000000..8b299e48 --- /dev/null +++ b/bindings/rust/keystone-sys/src/msp430_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_MSP430_INVALIDOPERAND = 512; + const ASM_MSP430_MISSINGFEATURE = 513; + const ASM_MSP430_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/ppc_const.rs b/bindings/rust/keystone-sys/src/ppc_const.rs new file mode 100644 index 00000000..caeea646 --- /dev/null +++ b/bindings/rust/keystone-sys/src/ppc_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_PPC_INVALIDOPERAND = 512; + const ASM_PPC_MISSINGFEATURE = 513; + const ASM_PPC_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/sparc_const.rs b/bindings/rust/keystone-sys/src/sparc_const.rs new file mode 100644 index 00000000..dd544ae1 --- /dev/null +++ b/bindings/rust/keystone-sys/src/sparc_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_SPARC_INVALIDOPERAND = 512; + const ASM_SPARC_MISSINGFEATURE = 513; + const ASM_SPARC_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/systemz_const.rs b/bindings/rust/keystone-sys/src/systemz_const.rs new file mode 100644 index 00000000..d2a8a1f3 --- /dev/null +++ b/bindings/rust/keystone-sys/src/systemz_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [systemz_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_SYSTEMZ_INVALIDOPERAND = 512; + const ASM_SYSTEMZ_MISSINGFEATURE = 513; + const ASM_SYSTEMZ_MNEMONICFAIL = 514; + } +} diff --git a/bindings/rust/keystone-sys/src/x86_const.rs b/bindings/rust/keystone-sys/src/x86_const.rs new file mode 100644 index 00000000..2db5ce54 --- /dev/null +++ b/bindings/rust/keystone-sys/src/x86_const.rs @@ -0,0 +1,11 @@ +#![allow(non_camel_case_types)] +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.rs] +use libc; +bitflags! { +#[repr(C)] + pub struct Error: u32 { + const ASM_X86_INVALIDOPERAND = 512; + const ASM_X86_MISSINGFEATURE = 513; + const ASM_X86_MNEMONICFAIL = 514; + } +} From b9c0b7bf0264b4e4b587df3bcc4717e18785b7d0 Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Wed, 2 Jan 2019 13:43:32 -0500 Subject: [PATCH 09/14] Add back changes for other bindings --- bindings/haskell/keystone.cabal | 1 + bindings/haskell/samples/Sample.hs | 3 ++ bindings/haskell/src/Keystone/CPU/Msp430.chs | 25 +++++++++++ bindings/java/pom.xml | 2 +- .../java/keystone/KeystoneArchitecture.java | 7 ++- bindings/masm/keystone_x64.inc | 4 +- bindings/masm/keystone_x86.inc | 4 +- bindings/masm/masmApiConst.api.txt | 4 +- bindings/nodejs/consts/index.js | 2 +- bindings/nodejs/consts/keystone.js | 3 +- bindings/nodejs/consts/msp430.js | 4 ++ bindings/ocaml/ffi_types.ml | 44 +++++++++++++++++++ bindings/ocaml/keystone.mli | 2 + bindings/ocaml/test_bindings.ml | 2 + .../lib/keystone/keystone_const.rb | 3 +- .../keystone_gem/lib/keystone/msp430_const.rb | 7 +++ bindings/ruby/sample.rb | 3 ++ bindings/vb6/Form1.frm | 3 ++ bindings/vb6/mKeystone.bas | 4 ++ 19 files changed, 118 insertions(+), 9 deletions(-) create mode 100644 bindings/haskell/src/Keystone/CPU/Msp430.chs create mode 100644 bindings/nodejs/consts/msp430.js create mode 100644 bindings/ruby/keystone_gem/lib/keystone/msp430_const.rb diff --git a/bindings/haskell/keystone.cabal b/bindings/haskell/keystone.cabal index e8b16037..309873ff 100644 --- a/bindings/haskell/keystone.cabal +++ b/bindings/haskell/keystone.cabal @@ -19,6 +19,7 @@ library Keystone.CPU.Arm Keystone.CPU.Hexagon Keystone.CPU.Mips + Keystone.CPU.Msp430 Keystone.CPU.Ppc Keystone.CPU.Sparc Keystone.CPU.SystemZ diff --git a/bindings/haskell/samples/Sample.hs b/bindings/haskell/samples/Sample.hs index dba62ce4..f17a87a5 100644 --- a/bindings/haskell/samples/Sample.hs +++ b/bindings/haskell/samples/Sample.hs @@ -72,3 +72,6 @@ main = do -- SystemZ testKs ArchSystemz [ModeBigEndian] ["a %r0, 4095(%r15,%r1)"] Nothing + + -- MSP430 + testKs ArchMsp430 [ModeLittleEndian] ["and r12, r13"] Nothing diff --git a/bindings/haskell/src/Keystone/CPU/Msp430.chs b/bindings/haskell/src/Keystone/CPU/Msp430.chs new file mode 100644 index 00000000..00bb021a --- /dev/null +++ b/bindings/haskell/src/Keystone/CPU/Msp430.chs @@ -0,0 +1,25 @@ +{-# LANGUAGE ForeignFunctionInterface #-} + +{-| +Module : Keystone.CPU.Msp430 +Description : Definitions for the Msp430 architecture. +Copyright : (C) Trey Keown, 2018 +License : GPL-2 + +Definitions for the Msp430 architecture. +-} +module Keystone.CPU.Msp430 + ( + Error(..) + ) where + +{# context lib = "keystone" #} + +#include + +-- | Msp430 errors. +{# enum ks_err_asm_msp430 as Error + { underscoreToCase } + with prefix = "KS_ERR_ASM_MSP430_" + deriving (Show, Eq, Bounded) +#} diff --git a/bindings/java/pom.xml b/bindings/java/pom.xml index 65949b23..9a76b755 100644 --- a/bindings/java/pom.xml +++ b/bindings/java/pom.xml @@ -16,7 +16,7 @@ 0.9.1-0 Keystone Java bindings - Keystone assembler framework: Core (Arm, Arm64, Hexagon, Mips, PowerPC, Sparc, SystemZ and X86) orm. + Keystone assembler framework: Core (Arm, Arm64, Hexagon, Mips, MSP430, PowerPC, Sparc, SystemZ and X86) orm. https://github.com/keystone-engine/keystone/tree/master/bindings/java diff --git a/bindings/java/src/main/java/keystone/KeystoneArchitecture.java b/bindings/java/src/main/java/keystone/KeystoneArchitecture.java index fc30ca7e..e5036459 100644 --- a/bindings/java/src/main/java/keystone/KeystoneArchitecture.java +++ b/bindings/java/src/main/java/keystone/KeystoneArchitecture.java @@ -61,7 +61,12 @@ public enum KeystoneArchitecture implements JnaEnum { */ Evm(9), - Max(10); + /** + * Msp430 architecture + */ + Msp430(10), + + Max(11); /** * Mapping table to determine an enumeration value based on an integer with a complexity of θ(1). diff --git a/bindings/masm/keystone_x64.inc b/bindings/masm/keystone_x64.inc index eb4b7cdb..40eadce3 100644 --- a/bindings/masm/keystone_x64.inc +++ b/bindings/masm/keystone_x64.inc @@ -32,7 +32,9 @@ KS_ARCH_PPC EQU 5 ; PowerPC architecture (currently un KS_ARCH_SPARC EQU 6 ; Sparc architecture KS_ARCH_SYSTEMZ EQU 7 ; SystemZ architecture (S390X) KS_ARCH_HEXAGON EQU 8 ; Hexagon architecture -KS_ARCH_MAX EQU 9 ; +KS_ARCH_EVM EQU 9 ; EVM architecture +KS_ARCH_MSP430 EQU 10 ; MSP430 architecture +KS_ARCH_MAX EQU 11 ; ; Mode type ks_mode KS_MODE_LITTLE_ENDIAN EQU 0 ; little-endian mode (default mode) diff --git a/bindings/masm/keystone_x86.inc b/bindings/masm/keystone_x86.inc index 8d3a33b8..f99fb5c3 100644 --- a/bindings/masm/keystone_x86.inc +++ b/bindings/masm/keystone_x86.inc @@ -32,7 +32,9 @@ KS_ARCH_PPC EQU 5 ; PowerPC architecture (currently un KS_ARCH_SPARC EQU 6 ; Sparc architecture KS_ARCH_SYSTEMZ EQU 7 ; SystemZ architecture (S390X) KS_ARCH_HEXAGON EQU 8 ; Hexagon architecture -KS_ARCH_MAX EQU 9 ; +KS_ARCH_EVM EQU 9 ; EVM architecture +KS_ARCH_MSP430 EQU 10 ; MSP430 architecture +KS_ARCH_MAX EQU 11 ; ; Mode type ks_mode KS_MODE_LITTLE_ENDIAN EQU 0 ; little-endian mode (default mode) diff --git a/bindings/masm/masmApiConst.api.txt b/bindings/masm/masmApiConst.api.txt index 90399a92..cb635164 100644 --- a/bindings/masm/masmApiConst.api.txt +++ b/bindings/masm/masmApiConst.api.txt @@ -6,8 +6,8 @@ ;----------------------------------------------------------------------------------------------------- 1ks_version,NULL,KS_VERSION_MAJOR 2ks_version,NULL,KS_VERSION_MINOR -1ks_arch_supported,KS_ARCH_ARM,KS_ARCH_ARM64,KS_ARCH_MIPS,KS_ARCH_X86,KS_ARCH_PPC,KS_ARCH_SPARC,KS_ARCH_SYSTEMZ,KS_ARCH_HEXAGON,KS_ARCH_MAX -1ks_open,KS_ARCH_ARM,KS_ARCH_ARM64,KS_ARCH_MIPS,KS_ARCH_X86,KS_ARCH_PPC,KS_ARCH_SPARC,KS_ARCH_SYSTEMZ,KS_ARCH_HEXAGON,KS_ARCH_MAX +1ks_arch_supported,KS_ARCH_ARM,KS_ARCH_ARM64,KS_ARCH_MIPS,KS_ARCH_X86,KS_ARCH_PPC,KS_ARCH_SPARC,KS_ARCH_SYSTEMZ,KS_ARCH_HEXAGON,KS_ARCH_EVM,KS_ARCH_MSP430,KS_ARCH_MAX +1ks_open,KS_ARCH_ARM,KS_ARCH_ARM64,KS_ARCH_MIPS,KS_ARCH_X86,KS_ARCH_PPC,KS_ARCH_SPARC,KS_ARCH_SYSTEMZ,KS_ARCH_HEXAGON,KS_ARCH_EVM,KS_ARCH_MSP430,KS_ARCH_MAX 2ks_open,KS_MODE_LITTLE_ENDIAN,KS_MODE_BIG_ENDIAN,KS_MODE_ARM,KS_MODE_THUMB,KS_MODE_V8,KS_MODE_MICRO,KS_MODE_MIPS3,KS_MODE_MIPS32R6,KS_MODE_MIPS32,KS_MODE_MIPS64,KS_MODE_16,KS_MODE_32,KS_MODE_64,KS_MODE_PPC32,KS_MODE_PPC64,KS_MODE_QPX,KS_MODE_SPARC32,KS_MODE_SPARC64,KS_MODE_V9 1ks_strerror,KS_ERR_OK,KS_ERR_NOMEM,KS_ERR_ARCH,KS_ERR_HANDLE,KS_ERR_MODE,KS_ERR_VERSION,KS_ERR_OPT_INVALID,KS_ERR_ASM_EXPR_TOKEN,KS_ERR_ASM_DIRECTIVE_VALUE_RANGE,KS_ERR_ASM_DIRECTIVE_ID,KS_ERR_ASM_DIRECTIVE_TOKEN,KS_ERR_ASM_DIRECTIVE_STR,KS_ERR_ASM_DIRECTIVE_COMMA,KS_ERR_ASM_DIRECTIVE_RELOC_NAME,KS_ERR_ASM_DIRECTIVE_RELOC_TOKEN,KS_ERR_ASM_DIRECTIVE_FPOINT,KS_ERR_ASM_DIRECTIVE_UNKNOWN,KS_ERR_ASM_DIRECTIVE_EQU,KS_ERR_ASM_DIRECTIVE_INVALID,KS_ERR_ASM_VARIANT_INVALID,KS_ERR_ASM_EXPR_BRACKET,KS_ERR_ASM_SYMBOL_MODIFIER,KS_ERR_ASM_SYMBOL_REDEFINED,KS_ERR_ASM_SYMBOL_MISSING,KS_ERR_ASM_RPAREN,KS_ERR_ASM_STAT_TOKEN,KS_ERR_ASM_UNSUPPORTED,KS_ERR_ASM_MACRO_TOKEN,KS_ERR_ASM_MACRO_PAREN,KS_ERR_ASM_MACRO_EQU,KS_ERR_ASM_MACRO_ARGS,KS_ERR_ASM_MACRO_LEVELS_EXCEED,KS_ERR_ASM_MACRO_STR,KS_ERR_ASM_MACRO_INVALID,KS_ERR_ASM_ESC_BACKSLASH,KS_ERR_ASM_ESC_OCTAL,KS_ERR_ASM_ESC_SEQUENCE,KS_ERR_ASM_ESC_STR,KS_ERR_ASM_TOKEN_INVALID,KS_ERR_ASM_INSN_UNSUPPORTED,KS_ERR_ASM_FIXUP_INVALID,KS_ERR_ASM_LABEL_INVALID,KS_ERR_ASM_FRAGMENT_INVALID,KS_ERR_ASM_INVALIDOPERAND,KS_ERR_ASM_MISSINGFEATURE,KS_ERR_ASM_MNEMONICFAIL,KS_ERR_ASM_X86_INVALIDOPERAND,KS_ERR_ASM_X86_MISSINGFEATURE,KS_ERR_ASM_X86_MNEMONICFAIL,KS_ERR_ASM,KS_ERR_ASM_ARCH 2ks_option,KS_OPT_SYNTAX,KS_OPT_SYM_RESOLVER diff --git a/bindings/nodejs/consts/index.js b/bindings/nodejs/consts/index.js index df58d5ca..737f5743 100644 --- a/bindings/nodejs/consts/index.js +++ b/bindings/nodejs/consts/index.js @@ -1,5 +1,5 @@ var extend = require('util')._extend, - archs = ['arm64', 'arm', 'hexagon', 'mips', 'ppc', 'sparc', 'systemz', 'x86'], + archs = ['arm64', 'arm', 'hexagon', 'mips', 'ppc', 'sparc', 'systemz', 'x86', 'evm', 'msp430'], i module.exports = require('./keystone') diff --git a/bindings/nodejs/consts/keystone.js b/bindings/nodejs/consts/keystone.js index a38e346b..bd210e01 100644 --- a/bindings/nodejs/consts/keystone.js +++ b/bindings/nodejs/consts/keystone.js @@ -13,7 +13,8 @@ module.exports.ARCH_SPARC = 6 module.exports.ARCH_SYSTEMZ = 7 module.exports.ARCH_HEXAGON = 8 module.exports.ARCH_EVM = 9 -module.exports.ARCH_MAX = 10 +module.exports.ARCH_MSP430 = 10 +module.exports.ARCH_MAX = 11 module.exports.MODE_LITTLE_ENDIAN = 0 module.exports.MODE_BIG_ENDIAN = 1073741824 module.exports.MODE_ARM = 1 diff --git a/bindings/nodejs/consts/msp430.js b/bindings/nodejs/consts/msp430.js new file mode 100644 index 00000000..87592e87 --- /dev/null +++ b/bindings/nodejs/consts/msp430.js @@ -0,0 +1,4 @@ +// For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.js] +module.exports.ERR_ASM_MSP430_INVALIDOPERAND = 512 +module.exports.ERR_ASM_MSP430_MISSINGFEATURE = 513 +module.exports.ERR_ASM_MSP430_MNEMONICFAIL = 514 diff --git a/bindings/ocaml/ffi_types.ml b/bindings/ocaml/ffi_types.ml index 82e13f9a..917d6cec 100644 --- a/bindings/ocaml/ffi_types.ml +++ b/bindings/ocaml/ffi_types.ml @@ -24,6 +24,8 @@ module Types (F: Cstubs.Types.TYPE) = | KS_ARCH_SPARC | KS_ARCH_SYSTEMZ | KS_ARCH_HEXAGON + | KS_ARCH_EVM + | KS_ARCH_MSP430 | KS_ARCH_MAX @@ -221,6 +223,8 @@ module Types (F: Cstubs.Types.TYPE) = let ks_arch_sparc = constant "KS_ARCH_SPARC" int64_t let ks_arch_systemz = constant "KS_ARCH_SYSTEMZ" int64_t let ks_arch_hexagon = constant "KS_ARCH_HEXAGON" int64_t + let ks_arch_evm = constant "KS_ARCH_EVM" int64_t + let ks_arch_msp430 = constant "KS_ARCH_MSP430" int64_t let ks_arch_max = constant "KS_ARCH_MAX" int64_t let ks_arch = enum "ks_arch" [ @@ -232,6 +236,8 @@ module Types (F: Cstubs.Types.TYPE) = KS_ARCH_SPARC, ks_arch_sparc; KS_ARCH_SYSTEMZ, ks_arch_systemz; KS_ARCH_HEXAGON, ks_arch_hexagon; + KS_ARCH_EVM, ks_arch_evm; + KS_ARCH_MSP430, ks_arch_msp430; KS_ARCH_MAX, ks_arch_max ] @@ -524,6 +530,44 @@ module Types (F: Cstubs.Types.TYPE) = ] end + module EVM = + struct + type ks_err_asm_evm = + | KS_ERR_ASM_EVM_INVALIDOPERAND + | KS_ERR_ASM_EVM_MISSINGFEATURE + | KS_ERR_ASM_EVM_MNEMONICFAIL + + + let ks_err_asm_evm_invalidoperand = constant "KS_ERR_ASM_EVM_INVALIDOPERAND" int64_t + let ks_err_asm_evm_missingfeature = constant "KS_ERR_ASM_EVM_MISSINGFEATURE" int64_t + let ks_err_asm_evm_mnemonicfail = constant "KS_ERR_ASM_EVM_MNEMONICFAIL" int64_t + + let ks_err_asm_evm = enum "ks_err_asm_evm" [ + KS_ERR_ASM_EVM_INVALIDOPERAND, ks_err_asm_evm_invalidoperand; + KS_ERR_ASM_EVM_MISSINGFEATURE, ks_err_asm_evm_missingfeature; + KS_ERR_ASM_EVM_MNEMONICFAIL, ks_err_asm_evm_mnemonicfail; + ] + end + + module MSP430 = + struct + type ks_err_asm_msp430 = + | KS_ERR_ASM_MSP430_INVALIDOPERAND + | KS_ERR_ASM_MSP430_MISSINGFEATURE + | KS_ERR_ASM_MSP430_MNEMONICFAIL + + + let ks_err_asm_msp430_invalidoperand = constant "KS_ERR_ASM_MSP430_INVALIDOPERAND" int64_t + let ks_err_asm_msp430_missingfeature = constant "KS_ERR_ASM_MSP430_MISSINGFEATURE" int64_t + let ks_err_asm_msp430_mnemonicfail = constant "KS_ERR_ASM_MSP430_MNEMONICFAIL" int64_t + + let ks_err_asm_msp430 = enum "ks_err_asm_msp430" [ + KS_ERR_ASM_MSP430_INVALIDOPERAND, ks_err_asm_msp430_invalidoperand; + KS_ERR_ASM_MSP430_MISSINGFEATURE, ks_err_asm_msp430_missingfeature; + KS_ERR_ASM_MSP430_MNEMONICFAIL, ks_err_asm_msp430_mnemonicfail; + ] + end + diff --git a/bindings/ocaml/keystone.mli b/bindings/ocaml/keystone.mli index b4991fbd..9bc9f7a8 100644 --- a/bindings/ocaml/keystone.mli +++ b/bindings/ocaml/keystone.mli @@ -17,6 +17,8 @@ module Types : sig | KS_ARCH_SPARC | KS_ARCH_SYSTEMZ | KS_ARCH_HEXAGON + | KS_ARCH_EVM + | KS_ARCH_MSP430 | KS_ARCH_MAX (** Keystone error types. Please see keystone.h for a full description. *) diff --git a/bindings/ocaml/test_bindings.ml b/bindings/ocaml/test_bindings.ml index e4bdd2b9..f57041ab 100644 --- a/bindings/ocaml/test_bindings.ml +++ b/bindings/ocaml/test_bindings.ml @@ -56,3 +56,5 @@ let _ = test_ks T.KS_ARCH_SPARC T.KS_MODE_SPARC32 ~endian:T.KS_MODE_BIG_ENDIAN "add %g1, %g2, %g3"; test_ks T.KS_ARCH_SYSTEMZ T.KS_MODE_BIG_ENDIAN "a %r0, 4095(%r15, %r1)" + + test_ks T.KS_ARCH_MSP430 T.KS_MODE_LITTLE_ENDIAN "and r12, r13" diff --git a/bindings/ruby/keystone_gem/lib/keystone/keystone_const.rb b/bindings/ruby/keystone_gem/lib/keystone/keystone_const.rb index abbde925..c08659cd 100644 --- a/bindings/ruby/keystone_gem/lib/keystone/keystone_const.rb +++ b/bindings/ruby/keystone_gem/lib/keystone/keystone_const.rb @@ -15,7 +15,8 @@ module Keystone KS_ARCH_SYSTEMZ = 7 KS_ARCH_HEXAGON = 8 KS_ARCH_EVM = 9 - KS_ARCH_MAX = 10 + KS_ARCH_MSP430 = 10 + KS_ARCH_MAX = 11 KS_MODE_LITTLE_ENDIAN = 0 KS_MODE_BIG_ENDIAN = 1073741824 KS_MODE_ARM = 1 diff --git a/bindings/ruby/keystone_gem/lib/keystone/msp430_const.rb b/bindings/ruby/keystone_gem/lib/keystone/msp430_const.rb new file mode 100644 index 00000000..b7a6a293 --- /dev/null +++ b/bindings/ruby/keystone_gem/lib/keystone/msp430_const.rb @@ -0,0 +1,7 @@ +# For Keystone Engine. AUTO-GENERATED FILE, DO NOT EDIT [msp430_const.rb] + +module Keystone + KS_ERR_ASM_MSP430_INVALIDOPERAND = 512 + KS_ERR_ASM_MSP430_MISSINGFEATURE = 513 + KS_ERR_ASM_MSP430_MNEMONICFAIL = 514 +end \ No newline at end of file diff --git a/bindings/ruby/sample.rb b/bindings/ruby/sample.rb index 9839fb11..3c096a8a 100755 --- a/bindings/ruby/sample.rb +++ b/bindings/ruby/sample.rb @@ -58,3 +58,6 @@ def test_ks(arch, mode, code, syntax=0) # SystemZ test_ks(KS_ARCH_SYSTEMZ, KS_MODE_BIG_ENDIAN, "a %r0, 4095(%r15,%r1)") + +# MSP430 +test_ks(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, "and r12, r13") diff --git a/bindings/vb6/Form1.frm b/bindings/vb6/Form1.frm index 4616d0ae..e70e2eda 100644 --- a/bindings/vb6/Form1.frm +++ b/bindings/vb6/Form1.frm @@ -116,6 +116,9 @@ Private Sub Form_Load() ' SystemZ AddResult test_ks(KS_ARCH_SYSTEMZ, KS_MODE_BIG_ENDIAN, "a %r0, 4095(%r15,%r1)", 0, base) + + ' MSP430 + AddResult test_ks(KS_ARCH_MSP430, KS_MODE_LITTLE_ENDIAN, "and r12, r13", 0, base) ' symbol resolver test (will enable once in stable release binaries not tested yet) 'AddResult test_ks(KS_ARCH_X86, KS_MODE_32, "jmp _l1; nop", 0, , base, True) diff --git a/bindings/vb6/mKeystone.bas b/bindings/vb6/mKeystone.bas index f5fb7ac4..b5d207b2 100644 --- a/bindings/vb6/mKeystone.bas +++ b/bindings/vb6/mKeystone.bas @@ -24,6 +24,8 @@ Public Enum ks_arch KS_ARCH_SPARC ' Sparc architecture KS_ARCH_SYSTEMZ ' SystemZ architecture (S390X) KS_ARCH_HEXAGON ' Hexagon architecture + KS_ARCH_EVM ' EVM architecture + KS_ARCH_MSP430 ' MSP430 architecture KS_ARCH_MAX End Enum @@ -339,6 +341,8 @@ Function ks_arch2str(v As ks_arch) As String If v = KS_ARCH_SPARC Then r = "KS_ARCH_SPARC" If v = KS_ARCH_SYSTEMZ Then r = "KS_ARCH_SYSTEMZ" If v = KS_ARCH_HEXAGON Then r = "KS_ARCH_HEXAGON" + If v = KS_ARCH_EVM Then r = "KS_ARCH_EVM" + If v = KS_ARCH_MSP430 Then r = "KS_ARCH_MSP430" If v = KS_ARCH_MAX Then r = "KS_ARCH_MAX" If Len(r) = 0 Then r = "Unknown: " & Hex(v) ks_arch2str = r From d0289f05e1519439369eebda5ac4ef01a2dda9e0 Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Fri, 4 Jan 2019 18:48:01 -0500 Subject: [PATCH 10/14] Update CREDITS.TXT --- CREDITS.TXT | 1 + 1 file changed, 1 insertion(+) diff --git a/CREDITS.TXT b/CREDITS.TXT index 46f0a968..083ac7a2 100644 --- a/CREDITS.TXT +++ b/CREDITS.TXT @@ -51,3 +51,4 @@ David Zimmer: VB6 binding. Michael Mohr: Debian packaging. Jämes Ménétrey (ZenLulz): Java binding. Philippe Antoine (Catena cyber): fuzzing. +Trey Keown: MSP430 support. From 04822e2525a845cb7ee36384ba1a436e0c896b9f Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Mon, 14 Jan 2019 22:06:33 -0500 Subject: [PATCH 11/14] Fix ADRP instruction encoding --- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 2 +- llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 30182862..d429fa8a 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -1133,7 +1133,7 @@ class AArch64Operand : public MCParsedAsmOperand { return false; if (const MCConstantExpr *CE = dyn_cast(Imm.Val)) { - int64_t Val = CE->getValue() - Ctx.getBaseAddress(); + int64_t Val = CE->getValue(); int64_t Min = - (4096 * (1LL << (21 - 1))); int64_t Max = 4096 * ((1LL << (21 - 1)) - 1); return (Val % 4096) == 0 && Val >= Min && Val <= Max; diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp index f7f17eeb..c07084e7 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp @@ -219,7 +219,7 @@ AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, // If the destination is an immediate, we have nothing to do. if (MO.isImm()) - return (MO.getImm() * 4096 - MI.getAddress()) / 4096; + return MO.getImm() - (MI.getAddress() >> 12); assert(MO.isExpr() && "Unexpected target type!"); const MCExpr *Expr = MO.getExpr(); From 79f3947c7fd39ca648b7967a68363c81f5a3540d Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Wed, 16 Jan 2019 00:39:42 -0500 Subject: [PATCH 12/14] Trigger checks on PR again, it failed for some reason unrelated to my code From a2ccf4260e66cbb1c3fd6c580d6ca58b2b467aae Mon Sep 17 00:00:00 2001 From: Trey Keown Date: Wed, 16 Jan 2019 12:01:21 -0500 Subject: [PATCH 13/14] Add correct offset checks back in --- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index d429fa8a..aef22a45 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -1134,9 +1134,10 @@ class AArch64Operand : public MCParsedAsmOperand { if (const MCConstantExpr *CE = dyn_cast(Imm.Val)) { int64_t Val = CE->getValue(); + int64_t Offset = Val - Ctx.getBaseAddress(); int64_t Min = - (4096 * (1LL << (21 - 1))); int64_t Max = 4096 * ((1LL << (21 - 1)) - 1); - return (Val % 4096) == 0 && Val >= Min && Val <= Max; + return (Val % 4096) == 0 && Offset >= Min && Offset <= Max; } return true; From 5b9ffe50937820e4532e2725a5f3ed2e6323d65d Mon Sep 17 00:00:00 2001 From: Dan Pesce Date: Mon, 15 Apr 2019 15:58:08 -0400 Subject: [PATCH 14/14] added llvm support post jan 2 --- .../lib/Target/MSP430/MSP430GenAsmMatcher.inc | 57 +- llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc | 1304 +++++++++-------- .../Target/MSP430/MSP430GenMCCodeEmitter.inc | 88 +- .../Target/MSP430/MSP430GenRegisterInfo.inc | 8 +- .../Target/MSP430/MSP430GenSubtargetInfo.inc | 11 +- 5 files changed, 868 insertions(+), 600 deletions(-) diff --git a/llvm/lib/Target/MSP430/MSP430GenAsmMatcher.inc b/llvm/lib/Target/MSP430/MSP430GenAsmMatcher.inc index 154c8934..aa7cb6b5 100644 --- a/llvm/lib/Target/MSP430/MSP430GenAsmMatcher.inc +++ b/llvm/lib/Target/MSP430/MSP430GenAsmMatcher.inc @@ -221,10 +221,14 @@ enum InstructionConversionKind { Convert__Reg1_1__Reg1_0, Convert__Reg1_1__CGImm1_0, Convert__Reg1_1__Imm1_0, + Convert__Reg1_1__IndReg1_0, Convert__Reg1_1__Mem2_0, + Convert__Reg1_1__PostIndReg1_0, Convert__Reg1_0, Convert__Imm1_0, Convert__Mem2_0, + Convert__IndReg1_0, + Convert__PostIndReg1_0, Convert__Reg1_0__imm_95_0, Convert__regSR__Tie0__imm_95_1, Convert__regSR__Tie0__imm_95_4, @@ -237,7 +241,6 @@ enum InstructionConversionKind { Convert__Reg1_0__Tie0__imm_95__MINUS_1, Convert__Mem2_0__imm_95__MINUS_1, Convert__Imm1_1__Imm1_0, - Convert__Reg1_1__IndReg1_0, Convert__Reg1_1__PostIndReg1_0__Tie1, Convert__regCG__imm_95_0, Convert__CGImm1_0, @@ -285,14 +288,22 @@ static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = { { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done }, // Convert__Reg1_1__Imm1_0 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done }, + // Convert__Reg1_1__IndReg1_0 + { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Done }, // Convert__Reg1_1__Mem2_0 { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done }, + // Convert__Reg1_1__PostIndReg1_0 + { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Done }, // Convert__Reg1_0 { CVT_95_Reg, 1, CVT_Done }, // Convert__Imm1_0 { CVT_95_addImmOperands, 1, CVT_Done }, // Convert__Mem2_0 { CVT_95_addMemOperands, 1, CVT_Done }, + // Convert__IndReg1_0 + { CVT_95_addRegOperands, 1, CVT_Done }, + // Convert__PostIndReg1_0 + { CVT_95_addRegOperands, 1, CVT_Done }, // Convert__Reg1_0__imm_95_0 { CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done }, // Convert__regSR__Tie0__imm_95_1 @@ -317,8 +328,6 @@ static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = { { CVT_95_addMemOperands, 1, CVT_imm_95__MINUS_1, 0, CVT_Done }, // Convert__Imm1_1__Imm1_0 { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done }, - // Convert__Reg1_1__IndReg1_0 - { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Done }, // Convert__Reg1_1__PostIndReg1_0__Tie1 { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Tied, 1, CVT_Done }, // Convert__regCG__imm_95_0 @@ -762,22 +771,32 @@ static const MatchEntry MatchTable0[] = { { 62 /* bit */, MSP430::BIT16ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, { 62 /* bit */, MSP430::BIT16mc, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, { 62 /* bit */, MSP430::BIT16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 62 /* bit */, MSP430::BIT16rn, Convert__Reg1_1__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 62 /* bit */, MSP430::BIT16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, { 62 /* bit */, MSP430::BIT16rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, { 62 /* bit */, MSP430::BIT16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 62 /* bit */, MSP430::BIT16rp, Convert__Reg1_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 62 /* bit */, MSP430::BIT16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, { 66 /* bit.b */, MSP430::BIT8rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, { 66 /* bit.b */, MSP430::BIT8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, { 66 /* bit.b */, MSP430::BIT8rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, { 66 /* bit.b */, MSP430::BIT8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, { 66 /* bit.b */, MSP430::BIT8ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, { 66 /* bit.b */, MSP430::BIT8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 66 /* bit.b */, MSP430::BIT8rn, Convert__Reg1_1__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 66 /* bit.b */, MSP430::BIT8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, { 66 /* bit.b */, MSP430::BIT8rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, { 66 /* bit.b */, MSP430::BIT8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 66 /* bit.b */, MSP430::BIT8rp, Convert__Reg1_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 66 /* bit.b */, MSP430::BIT8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, { 72 /* br */, MSP430::Br, Convert__Reg1_0, 0, { MCK_GR16 }, }, { 72 /* br */, MSP430::Bi, Convert__Imm1_0, 0, { MCK_Imm }, }, { 72 /* br */, MSP430::Bm, Convert__Mem2_0, 0, { MCK_Mem }, }, { 75 /* call */, MSP430::CALLr, Convert__Reg1_0, 0, { MCK_GR16 }, }, { 75 /* call */, MSP430::CALLi, Convert__Imm1_0, 0, { MCK_Imm }, }, + { 75 /* call */, MSP430::CALLn, Convert__IndReg1_0, 0, { MCK_IndReg }, }, { 75 /* call */, MSP430::CALLm, Convert__Mem2_0, 0, { MCK_Mem }, }, + { 75 /* call */, MSP430::CALLp, Convert__PostIndReg1_0, 0, { MCK_PostIndReg }, }, { 80 /* clr */, MSP430::MOV16rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR16 }, }, { 80 /* clr */, MSP430::MOV16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, { 84 /* clr.b */, MSP430::MOV8rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR8 }, }, @@ -791,14 +810,24 @@ static const MatchEntry MatchTable0[] = { { 105 /* cmp */, MSP430::CMP16mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, { 105 /* cmp */, MSP430::CMP16ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, { 105 /* cmp */, MSP430::CMP16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 105 /* cmp */, MSP430::CMP16rn, Convert__Reg1_1__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 105 /* cmp */, MSP430::CMP16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, { 105 /* cmp */, MSP430::CMP16rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, + { 105 /* cmp */, MSP430::CMP16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 105 /* cmp */, MSP430::CMP16rp, Convert__Reg1_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 105 /* cmp */, MSP430::CMP16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, { 109 /* cmp.b */, MSP430::CMP8rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, { 109 /* cmp.b */, MSP430::CMP8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, { 109 /* cmp.b */, MSP430::CMP8rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, { 109 /* cmp.b */, MSP430::CMP8mc, Convert__Mem2_1__CGImm1_0, 0, { MCK_CGImm, MCK_Mem }, }, { 109 /* cmp.b */, MSP430::CMP8ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, { 109 /* cmp.b */, MSP430::CMP8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, + { 109 /* cmp.b */, MSP430::CMP8rn, Convert__Reg1_1__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 109 /* cmp.b */, MSP430::CMP8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, { 109 /* cmp.b */, MSP430::CMP8rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, + { 109 /* cmp.b */, MSP430::CMP8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, + { 109 /* cmp.b */, MSP430::CMP8rp, Convert__Reg1_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_GR8 }, }, + { 109 /* cmp.b */, MSP430::CMP8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, { 115 /* dadc */, MSP430::DADD16rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR16 }, }, { 115 /* dadc */, MSP430::DADD16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, { 120 /* dadc.b */, MSP430::DADD8rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR8 }, }, @@ -858,9 +887,12 @@ static const MatchEntry MatchTable0[] = { { 209 /* mov */, MSP430::MOV16ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, }, { 209 /* mov */, MSP430::MOV16mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, { 209 /* mov */, MSP430::MOV16rn, Convert__Reg1_1__IndReg1_0, 0, { MCK_IndReg, MCK_GR16 }, }, + { 209 /* mov */, MSP430::MOV16mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, { 209 /* mov */, MSP430::MOV16rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR16 }, }, { 209 /* mov */, MSP430::MOV16mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, { 209 /* mov */, MSP430::MOV16rp, Convert__Reg1_1__PostIndReg1_0__Tie1, 0, { MCK_PostIndReg, MCK_GR16 }, }, + { 209 /* mov */, MSP430::MOV16mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, + { 209 /* mov */, MSP430::MOV8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, { 213 /* mov.b */, MSP430::MOV8rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, }, { 213 /* mov.b */, MSP430::MOV8mr, Convert__Mem2_1__Reg1_0, 0, { MCK_GR8, MCK_Mem }, }, { 213 /* mov.b */, MSP430::MOV8rc, Convert__Reg1_1__CGImm1_0, 0, { MCK_CGImm, MCK_GR8 }, }, @@ -868,6 +900,7 @@ static const MatchEntry MatchTable0[] = { { 213 /* mov.b */, MSP430::MOV8ri, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, }, { 213 /* mov.b */, MSP430::MOV8mi, Convert__Mem2_1__Imm1_0, 0, { MCK_Imm, MCK_Mem }, }, { 213 /* mov.b */, MSP430::MOV8rn, Convert__Reg1_1__IndReg1_0, 0, { MCK_IndReg, MCK_GR8 }, }, + { 213 /* mov.b */, MSP430::MOV8mn, Convert__Mem2_1__IndReg1_0, 0, { MCK_IndReg, MCK_Mem }, }, { 213 /* mov.b */, MSP430::MOV8rm, Convert__Reg1_1__Mem2_0, 0, { MCK_Mem, MCK_GR8 }, }, { 213 /* mov.b */, MSP430::MOV8mm, Convert__Mem2_1__Mem2_0, 0, { MCK_Mem, MCK_Mem }, }, { 213 /* mov.b */, MSP430::MOV8rp, Convert__Reg1_1__PostIndReg1_0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, @@ -888,9 +921,21 @@ static const MatchEntry MatchTable0[] = { { 262 /* rlc.b */, MSP430::ADDC8rr, Convert__Reg1_0__Tie0__Reg1_0, 0, { MCK_GR8 }, }, { 262 /* rlc.b */, MSP430::ADDC8mm, Convert__Mem2_0__Mem2_0, 0, { MCK_Mem }, }, { 268 /* rra */, MSP430::RRA16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, + { 268 /* rra */, MSP430::RRA16n, Convert__IndReg1_0, 0, { MCK_IndReg }, }, + { 268 /* rra */, MSP430::RRA16m, Convert__Mem2_0, 0, { MCK_Mem }, }, + { 268 /* rra */, MSP430::RRA16p, Convert__PostIndReg1_0, 0, { MCK_PostIndReg }, }, { 272 /* rra.b */, MSP430::RRA8r, Convert__Reg1_0__Tie0, 0, { MCK_GR8 }, }, + { 272 /* rra.b */, MSP430::RRA8n, Convert__IndReg1_0, 0, { MCK_IndReg }, }, + { 272 /* rra.b */, MSP430::RRA8m, Convert__Mem2_0, 0, { MCK_Mem }, }, + { 272 /* rra.b */, MSP430::RRA8p, Convert__PostIndReg1_0, 0, { MCK_PostIndReg }, }, { 278 /* rrc */, MSP430::RRC16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, + { 278 /* rrc */, MSP430::RRC16n, Convert__IndReg1_0, 0, { MCK_IndReg }, }, + { 278 /* rrc */, MSP430::RRC16m, Convert__Mem2_0, 0, { MCK_Mem }, }, + { 278 /* rrc */, MSP430::RRC16p, Convert__PostIndReg1_0, 0, { MCK_PostIndReg }, }, { 282 /* rrc.b */, MSP430::RRC8r, Convert__Reg1_0__Tie0, 0, { MCK_GR8 }, }, + { 282 /* rrc.b */, MSP430::RRC8n, Convert__IndReg1_0, 0, { MCK_IndReg }, }, + { 282 /* rrc.b */, MSP430::RRC8m, Convert__Mem2_0, 0, { MCK_Mem }, }, + { 282 /* rrc.b */, MSP430::RRC8p, Convert__PostIndReg1_0, 0, { MCK_PostIndReg }, }, { 288 /* sbc */, MSP430::SUBC16rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR16 }, }, { 288 /* sbc */, MSP430::SUBC16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, { 292 /* sbc.b */, MSP430::SUBC8rc, Convert__Reg1_0__Tie0__imm_95_0, 0, { MCK_GR8 }, }, @@ -947,7 +992,13 @@ static const MatchEntry MatchTable0[] = { { 328 /* subc.b */, MSP430::SUBC8rp, Convert__Reg1_1__PostIndReg1_0__Tie0__Tie1, 0, { MCK_PostIndReg, MCK_GR8 }, }, { 328 /* subc.b */, MSP430::SUBC8mp, Convert__Mem2_1__PostIndReg1_0, 0, { MCK_PostIndReg, MCK_Mem }, }, { 335 /* swpb */, MSP430::SWPB16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, + { 335 /* swpb */, MSP430::SWPB16n, Convert__IndReg1_0, 0, { MCK_IndReg }, }, + { 335 /* swpb */, MSP430::SWPB16m, Convert__Mem2_0, 0, { MCK_Mem }, }, + { 335 /* swpb */, MSP430::SWPB16p, Convert__PostIndReg1_0, 0, { MCK_PostIndReg }, }, { 340 /* sxt */, MSP430::SEXT16r, Convert__Reg1_0__Tie0, 0, { MCK_GR16 }, }, + { 340 /* sxt */, MSP430::SEXT16n, Convert__IndReg1_0, 0, { MCK_IndReg }, }, + { 340 /* sxt */, MSP430::SEXT16m, Convert__Mem2_0, 0, { MCK_Mem }, }, + { 340 /* sxt */, MSP430::SEXT16p, Convert__PostIndReg1_0, 0, { MCK_PostIndReg }, }, { 344 /* tst */, MSP430::CMP16rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR16 }, }, { 344 /* tst */, MSP430::CMP16mc, Convert__Mem2_0__imm_95_0, 0, { MCK_Mem }, }, { 348 /* tst.b */, MSP430::CMP8rc, Convert__Reg1_0__imm_95_0, 0, { MCK_GR8 }, }, diff --git a/llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc b/llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc index 3c88af21..5825b9ad 100644 --- a/llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc +++ b/llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc @@ -167,184 +167,226 @@ namespace MSP430 { BIT16mc = 152, BIT16mi = 153, BIT16mm = 154, - BIT16mr = 155, - BIT16rc = 156, - BIT16ri = 157, - BIT16rm = 158, - BIT16rr = 159, - BIT8mc = 160, - BIT8mi = 161, - BIT8mm = 162, - BIT8mr = 163, - BIT8rc = 164, - BIT8ri = 165, - BIT8rm = 166, - BIT8rr = 167, - Bi = 168, - Bm = 169, - Br = 170, - CALLi = 171, - CALLm = 172, - CALLr = 173, - CMP16mc = 174, - CMP16mi = 175, - CMP16mr = 176, - CMP16rc = 177, - CMP16ri = 178, - CMP16rm = 179, - CMP16rr = 180, - CMP8mc = 181, - CMP8mi = 182, - CMP8mr = 183, - CMP8rc = 184, - CMP8ri = 185, - CMP8rm = 186, - CMP8rr = 187, - DADD16mc = 188, - DADD16mi = 189, - DADD16mm = 190, - DADD16mn = 191, - DADD16mp = 192, - DADD16mr = 193, - DADD16rc = 194, - DADD16ri = 195, - DADD16rm = 196, - DADD16rn = 197, - DADD16rp = 198, - DADD16rr = 199, - DADD8mc = 200, - DADD8mi = 201, - DADD8mm = 202, - DADD8mn = 203, - DADD8mp = 204, - DADD8mr = 205, - DADD8rc = 206, - DADD8ri = 207, - DADD8rm = 208, - DADD8rn = 209, - DADD8rp = 210, - DADD8rr = 211, - JCC = 212, - JMP = 213, - MOV16mc = 214, - MOV16mi = 215, - MOV16mm = 216, - MOV16mr = 217, - MOV16rc = 218, - MOV16ri = 219, - MOV16rm = 220, - MOV16rn = 221, - MOV16rp = 222, - MOV16rr = 223, - MOV8mc = 224, - MOV8mi = 225, - MOV8mm = 226, - MOV8mr = 227, - MOV8rc = 228, - MOV8ri = 229, - MOV8rm = 230, - MOV8rn = 231, - MOV8rp = 232, - MOV8rr = 233, - MOVZX16rm8 = 234, - MOVZX16rr8 = 235, - POP16r = 236, - PUSH16c = 237, - PUSH16i = 238, - PUSH16r = 239, - PUSH8r = 240, - RET = 241, - RETI = 242, - RRA16r = 243, - RRA8r = 244, - RRC16r = 245, - RRC8r = 246, - Rrcl16 = 247, - Rrcl8 = 248, - SEXT16r = 249, - SUB16mc = 250, - SUB16mi = 251, - SUB16mm = 252, - SUB16mn = 253, - SUB16mp = 254, - SUB16mr = 255, - SUB16rc = 256, - SUB16ri = 257, - SUB16rm = 258, - SUB16rn = 259, - SUB16rp = 260, - SUB16rr = 261, - SUB8mc = 262, - SUB8mi = 263, - SUB8mm = 264, - SUB8mn = 265, - SUB8mp = 266, - SUB8mr = 267, - SUB8rc = 268, - SUB8ri = 269, - SUB8rm = 270, - SUB8rn = 271, - SUB8rp = 272, - SUB8rr = 273, - SUBC16mc = 274, - SUBC16mi = 275, - SUBC16mm = 276, - SUBC16mn = 277, - SUBC16mp = 278, - SUBC16mr = 279, - SUBC16rc = 280, - SUBC16ri = 281, - SUBC16rm = 282, - SUBC16rn = 283, - SUBC16rp = 284, - SUBC16rr = 285, - SUBC8mc = 286, - SUBC8mi = 287, - SUBC8mm = 288, - SUBC8mn = 289, - SUBC8mp = 290, - SUBC8mr = 291, - SUBC8rc = 292, - SUBC8ri = 293, - SUBC8rm = 294, - SUBC8rn = 295, - SUBC8rp = 296, - SUBC8rr = 297, - SWPB16r = 298, - Select16 = 299, - Select8 = 300, - Shl16 = 301, - Shl8 = 302, - Sra16 = 303, - Sra8 = 304, - Srl16 = 305, - Srl8 = 306, - XOR16mc = 307, - XOR16mi = 308, - XOR16mm = 309, - XOR16mn = 310, - XOR16mp = 311, - XOR16mr = 312, - XOR16rc = 313, - XOR16ri = 314, - XOR16rm = 315, - XOR16rn = 316, - XOR16rp = 317, - XOR16rr = 318, - XOR8mc = 319, - XOR8mi = 320, - XOR8mm = 321, - XOR8mn = 322, - XOR8mp = 323, - XOR8mr = 324, - XOR8rc = 325, - XOR8ri = 326, - XOR8rm = 327, - XOR8rn = 328, - XOR8rp = 329, - XOR8rr = 330, - ZEXT16r = 331, - INSTRUCTION_LIST_END = 332 + BIT16mn = 155, + BIT16mp = 156, + BIT16mr = 157, + BIT16rc = 158, + BIT16ri = 159, + BIT16rm = 160, + BIT16rn = 161, + BIT16rp = 162, + BIT16rr = 163, + BIT8mc = 164, + BIT8mi = 165, + BIT8mm = 166, + BIT8mn = 167, + BIT8mp = 168, + BIT8mr = 169, + BIT8rc = 170, + BIT8ri = 171, + BIT8rm = 172, + BIT8rn = 173, + BIT8rp = 174, + BIT8rr = 175, + Bi = 176, + Bm = 177, + Br = 178, + CALLi = 179, + CALLm = 180, + CALLn = 181, + CALLp = 182, + CALLr = 183, + CMP16mc = 184, + CMP16mi = 185, + CMP16mm = 186, + CMP16mn = 187, + CMP16mp = 188, + CMP16mr = 189, + CMP16rc = 190, + CMP16ri = 191, + CMP16rm = 192, + CMP16rn = 193, + CMP16rp = 194, + CMP16rr = 195, + CMP8mc = 196, + CMP8mi = 197, + CMP8mm = 198, + CMP8mn = 199, + CMP8mp = 200, + CMP8mr = 201, + CMP8rc = 202, + CMP8ri = 203, + CMP8rm = 204, + CMP8rn = 205, + CMP8rp = 206, + CMP8rr = 207, + DADD16mc = 208, + DADD16mi = 209, + DADD16mm = 210, + DADD16mn = 211, + DADD16mp = 212, + DADD16mr = 213, + DADD16rc = 214, + DADD16ri = 215, + DADD16rm = 216, + DADD16rn = 217, + DADD16rp = 218, + DADD16rr = 219, + DADD8mc = 220, + DADD8mi = 221, + DADD8mm = 222, + DADD8mn = 223, + DADD8mp = 224, + DADD8mr = 225, + DADD8rc = 226, + DADD8ri = 227, + DADD8rm = 228, + DADD8rn = 229, + DADD8rp = 230, + DADD8rr = 231, + JCC = 232, + JMP = 233, + MOV16mc = 234, + MOV16mi = 235, + MOV16mm = 236, + MOV16mn = 237, + MOV16mp = 238, + MOV16mr = 239, + MOV16rc = 240, + MOV16ri = 241, + MOV16rm = 242, + MOV16rn = 243, + MOV16rp = 244, + MOV16rr = 245, + MOV8mc = 246, + MOV8mi = 247, + MOV8mm = 248, + MOV8mn = 249, + MOV8mp = 250, + MOV8mr = 251, + MOV8rc = 252, + MOV8ri = 253, + MOV8rm = 254, + MOV8rn = 255, + MOV8rp = 256, + MOV8rr = 257, + MOVZX16rm8 = 258, + MOVZX16rr8 = 259, + POP16r = 260, + PUSH16c = 261, + PUSH16i = 262, + PUSH16r = 263, + PUSH8r = 264, + RET = 265, + RETI = 266, + RRA16m = 267, + RRA16n = 268, + RRA16p = 269, + RRA16r = 270, + RRA8m = 271, + RRA8n = 272, + RRA8p = 273, + RRA8r = 274, + RRC16m = 275, + RRC16n = 276, + RRC16p = 277, + RRC16r = 278, + RRC8m = 279, + RRC8n = 280, + RRC8p = 281, + RRC8r = 282, + Rrcl16 = 283, + Rrcl8 = 284, + SEXT16m = 285, + SEXT16n = 286, + SEXT16p = 287, + SEXT16r = 288, + SUB16mc = 289, + SUB16mi = 290, + SUB16mm = 291, + SUB16mn = 292, + SUB16mp = 293, + SUB16mr = 294, + SUB16rc = 295, + SUB16ri = 296, + SUB16rm = 297, + SUB16rn = 298, + SUB16rp = 299, + SUB16rr = 300, + SUB8mc = 301, + SUB8mi = 302, + SUB8mm = 303, + SUB8mn = 304, + SUB8mp = 305, + SUB8mr = 306, + SUB8rc = 307, + SUB8ri = 308, + SUB8rm = 309, + SUB8rn = 310, + SUB8rp = 311, + SUB8rr = 312, + SUBC16mc = 313, + SUBC16mi = 314, + SUBC16mm = 315, + SUBC16mn = 316, + SUBC16mp = 317, + SUBC16mr = 318, + SUBC16rc = 319, + SUBC16ri = 320, + SUBC16rm = 321, + SUBC16rn = 322, + SUBC16rp = 323, + SUBC16rr = 324, + SUBC8mc = 325, + SUBC8mi = 326, + SUBC8mm = 327, + SUBC8mn = 328, + SUBC8mp = 329, + SUBC8mr = 330, + SUBC8rc = 331, + SUBC8ri = 332, + SUBC8rm = 333, + SUBC8rn = 334, + SUBC8rp = 335, + SUBC8rr = 336, + SWPB16m = 337, + SWPB16n = 338, + SWPB16p = 339, + SWPB16r = 340, + Select16 = 341, + Select8 = 342, + Shl16 = 343, + Shl8 = 344, + Sra16 = 345, + Sra8 = 346, + Srl16 = 347, + Srl8 = 348, + XOR16mc = 349, + XOR16mi = 350, + XOR16mm = 351, + XOR16mn = 352, + XOR16mp = 353, + XOR16mr = 354, + XOR16rc = 355, + XOR16ri = 356, + XOR16rm = 357, + XOR16rn = 358, + XOR16rp = 359, + XOR16rr = 360, + XOR8mc = 361, + XOR8mi = 362, + XOR8mm = 363, + XOR8mn = 364, + XOR8mp = 365, + XOR8mr = 366, + XOR8rc = 367, + XOR8ri = 368, + XOR8rm = 369, + XOR8rn = 370, + XOR8rp = 371, + XOR8rr = 372, + ZEXT16r = 373, + INSTRUCTION_LIST_END = 374 }; namespace Sched { @@ -399,25 +441,26 @@ static const MCOperandInfo OperandInfo31[] = { { MSP430::GR16RegClassID, 0, MCOI static const MCOperandInfo OperandInfo32[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo33[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo34[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo35[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo36[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo37[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo38[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo39[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo40[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo41[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo42[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo43[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; -static const MCOperandInfo OperandInfo44[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo45[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; -static const MCOperandInfo OperandInfo46[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo47[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo48[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; -static const MCOperandInfo OperandInfo49[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; -static const MCOperandInfo OperandInfo50[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo51[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo52[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo53[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo35[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo36[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo37[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo38[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo39[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo40[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo41[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo42[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo43[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo44[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo45[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; +static const MCOperandInfo OperandInfo46[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; +static const MCOperandInfo OperandInfo47[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo48[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo49[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; +static const MCOperandInfo OperandInfo50[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; +static const MCOperandInfo OperandInfo51[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo52[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo53[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo54[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; extern const MCInstrDesc MSP430Insts[] = { { 0, 1, 1, 0, 0, 0|(1ULL<InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 332); + II->InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 374); } } // end llvm namespace @@ -1134,7 +1266,7 @@ extern const unsigned MSP430InstrNameIndices[]; extern const char MSP430InstrNameData[]; MSP430GenInstrInfo::MSP430GenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode) : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { - InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 332); + InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 374); } } // end llvm namespace #endif // GET_INSTRINFO_CTOR_DTOR @@ -1149,7 +1281,7 @@ OPERAND_LAST }; } // end namespace OpName } // end namespace MSP430 -} // end namespace llvm +} // end namespace llvm_ks #endif //GET_INSTRINFO_OPERAND_ENUM #ifdef GET_INSTRINFO_NAMED_OPS @@ -1161,7 +1293,7 @@ int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { return -1; } } // end namespace MSP430 -} // end namespace llvm +} // end namespace llvm_ks #endif //GET_INSTRINFO_NAMED_OPS #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM @@ -1189,6 +1321,6 @@ enum OperandType { }; } // end namespace OpTypes } // end namespace MSP430 -} // end namespace llvm +} // end namespace llvm_ks #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM diff --git a/llvm/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc b/llvm/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc index 2cc1528b..a5778176 100644 --- a/llvm/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc +++ b/llvm/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc @@ -165,38 +165,58 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, UINT64_C(45184), // BIT16mc UINT64_C(45232), // BIT16mi UINT64_C(45200), // BIT16mm + UINT64_C(45216), // BIT16mn + UINT64_C(45232), // BIT16mp UINT64_C(45184), // BIT16mr UINT64_C(45056), // BIT16rc UINT64_C(45104), // BIT16ri UINT64_C(45072), // BIT16rm + UINT64_C(45088), // BIT16rn + UINT64_C(45104), // BIT16rp UINT64_C(45056), // BIT16rr UINT64_C(45248), // BIT8mc UINT64_C(45296), // BIT8mi UINT64_C(45264), // BIT8mm + UINT64_C(45280), // BIT8mn + UINT64_C(45296), // BIT8mp UINT64_C(45248), // BIT8mr UINT64_C(45120), // BIT8rc UINT64_C(45168), // BIT8ri UINT64_C(45136), // BIT8rm + UINT64_C(45152), // BIT8rn + UINT64_C(45168), // BIT8rp UINT64_C(45120), // BIT8rr UINT64_C(16432), // Bi UINT64_C(16400), // Bm UINT64_C(16384), // Br UINT64_C(4784), // CALLi UINT64_C(4752), // CALLm + UINT64_C(4768), // CALLn + UINT64_C(4784), // CALLp UINT64_C(4736), // CALLr UINT64_C(36992), // CMP16mc UINT64_C(37040), // CMP16mi + UINT64_C(37008), // CMP16mm + UINT64_C(37024), // CMP16mn + UINT64_C(37040), // CMP16mp UINT64_C(36992), // CMP16mr UINT64_C(36864), // CMP16rc UINT64_C(36912), // CMP16ri UINT64_C(36880), // CMP16rm + UINT64_C(36896), // CMP16rn + UINT64_C(36912), // CMP16rp UINT64_C(36864), // CMP16rr UINT64_C(37056), // CMP8mc UINT64_C(37104), // CMP8mi + UINT64_C(37072), // CMP8mm + UINT64_C(37088), // CMP8mn + UINT64_C(37104), // CMP8mp UINT64_C(37056), // CMP8mr UINT64_C(36928), // CMP8rc UINT64_C(36976), // CMP8ri UINT64_C(36944), // CMP8rm + UINT64_C(36960), // CMP8rn + UINT64_C(36976), // CMP8rp UINT64_C(36928), // CMP8rr UINT64_C(41088), // DADD16mc UINT64_C(41136), // DADD16mi @@ -227,6 +247,8 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, UINT64_C(16512), // MOV16mc UINT64_C(16560), // MOV16mi UINT64_C(16528), // MOV16mm + UINT64_C(16544), // MOV16mn + UINT64_C(16560), // MOV16mp UINT64_C(16512), // MOV16mr UINT64_C(16384), // MOV16rc UINT64_C(16432), // MOV16ri @@ -237,6 +259,8 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, UINT64_C(16576), // MOV8mc UINT64_C(16624), // MOV8mi UINT64_C(16592), // MOV8mm + UINT64_C(16608), // MOV8mn + UINT64_C(16624), // MOV8mp UINT64_C(16576), // MOV8mr UINT64_C(16448), // MOV8rc UINT64_C(16496), // MOV8ri @@ -253,12 +277,27 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, UINT64_C(4672), // PUSH8r UINT64_C(16688), // RET UINT64_C(4864), // RETI + UINT64_C(4368), // RRA16m + UINT64_C(4384), // RRA16n + UINT64_C(4400), // RRA16p UINT64_C(4352), // RRA16r + UINT64_C(4432), // RRA8m + UINT64_C(4448), // RRA8n + UINT64_C(4464), // RRA8p UINT64_C(4416), // RRA8r + UINT64_C(4112), // RRC16m + UINT64_C(4128), // RRC16n + UINT64_C(4144), // RRC16p UINT64_C(4096), // RRC16r + UINT64_C(4176), // RRC8m + UINT64_C(4192), // RRC8n + UINT64_C(4208), // RRC8p UINT64_C(4160), // RRC8r UINT64_C(0), // Rrcl16 UINT64_C(0), // Rrcl8 + UINT64_C(4496), // SEXT16m + UINT64_C(4512), // SEXT16n + UINT64_C(4528), // SEXT16p UINT64_C(4480), // SEXT16r UINT64_C(32896), // SUB16mc UINT64_C(32944), // SUB16mi @@ -308,6 +347,9 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, UINT64_C(28768), // SUBC8rn UINT64_C(28784), // SUBC8rp UINT64_C(28736), // SUBC8rr + UINT64_C(4240), // SWPB16m + UINT64_C(4256), // SWPB16n + UINT64_C(4272), // SWPB16p UINT64_C(4224), // SWPB16r UINT64_C(0), // Select16 UINT64_C(0), // Select8 @@ -609,17 +651,39 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, Value |= (op & UINT64_C(15)) << 8; break; } + case MSP430::CALLn: + case MSP430::CALLp: case MSP430::CALLr: case MSP430::PUSH16r: - case MSP430::PUSH8r: { + case MSP430::PUSH8r: + case MSP430::RRA16n: + case MSP430::RRA16p: + case MSP430::RRA8n: + case MSP430::RRA8p: + case MSP430::RRC16n: + case MSP430::RRC16p: + case MSP430::RRC8n: + case MSP430::RRC8p: + case MSP430::SEXT16n: + case MSP430::SEXT16p: + case MSP430::SWPB16n: + case MSP430::SWPB16p: { // op: rs op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); Value |= op & UINT64_C(15); break; } + case MSP430::BIT16rn: + case MSP430::BIT16rp: case MSP430::BIT16rr: + case MSP430::BIT8rn: + case MSP430::BIT8rp: case MSP430::BIT8rr: + case MSP430::CMP16rn: + case MSP430::CMP16rp: case MSP430::CMP16rr: + case MSP430::CMP8rn: + case MSP430::CMP8rp: case MSP430::CMP8rr: case MSP430::MOV16rn: case MSP430::MOV16rr: @@ -676,9 +740,17 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, case MSP430::BIS8mn: case MSP430::BIS8mp: case MSP430::BIS8mr: + case MSP430::BIT16mn: + case MSP430::BIT16mp: case MSP430::BIT16mr: + case MSP430::BIT8mn: + case MSP430::BIT8mp: case MSP430::BIT8mr: + case MSP430::CMP16mn: + case MSP430::CMP16mp: case MSP430::CMP16mr: + case MSP430::CMP8mn: + case MSP430::CMP8mp: case MSP430::CMP8mr: case MSP430::DADD16mn: case MSP430::DADD16mp: @@ -686,7 +758,11 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, case MSP430::DADD8mn: case MSP430::DADD8mp: case MSP430::DADD8mr: + case MSP430::MOV16mn: + case MSP430::MOV16mp: case MSP430::MOV16mr: + case MSP430::MOV8mn: + case MSP430::MOV8mp: case MSP430::MOV8mr: case MSP430::SUB16mn: case MSP430::SUB16mp: @@ -794,7 +870,13 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, Value |= (op & UINT64_C(15)) << 8; break; } - case MSP430::CALLm: { + case MSP430::CALLm: + case MSP430::RRA16m: + case MSP430::RRA8m: + case MSP430::RRC16m: + case MSP430::RRC8m: + case MSP430::SEXT16m: + case MSP430::SWPB16m: { // op: src op = getMemOpValue(MI, 0, Fixups, STI); Value |= (op & UINT64_C(1048560)) << 12; @@ -813,6 +895,8 @@ uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, case MSP430::BIS8mm: case MSP430::BIT16mm: case MSP430::BIT8mm: + case MSP430::CMP16mm: + case MSP430::CMP8mm: case MSP430::DADD16mm: case MSP430::DADD8mm: case MSP430::MOV16mm: diff --git a/llvm/lib/Target/MSP430/MSP430GenRegisterInfo.inc b/llvm/lib/Target/MSP430/MSP430GenRegisterInfo.inc index 33a60e98..8ff09bb5 100644 --- a/llvm/lib/Target/MSP430/MSP430GenRegisterInfo.inc +++ b/llvm/lib/Target/MSP430/MSP430GenRegisterInfo.inc @@ -75,7 +75,7 @@ enum { }; } // end namespace MSP430 -} // end namespace llvm +} // end namespace llvm_ks #endif // GET_REGINFO_ENUM @@ -284,7 +284,7 @@ MSP430SubRegIdxRanges, MSP430RegEncodingTable); } -} // end namespace llvm +} // end namespace llvm_ks #endif // GET_REGINFO_MC_DESC @@ -331,7 +331,7 @@ namespace MSP430 { // Register classes extern const TargetRegisterClass GR16RegClass; } // end namespace MSP430 -} // end namespace llvm +} // end namespace llvm_ks #endif // GET_REGINFO_HEADER @@ -625,7 +625,7 @@ MSP430GenRegisterInfo::getFrameLowering(const MachineFunction &MF) { MF.getSubtarget().getFrameLowering()); } -} // end namespace llvm +} // end namespace llvm_ks #endif // GET_REGINFO_TARGET_DESC diff --git a/llvm/lib/Target/MSP430/MSP430GenSubtargetInfo.inc b/llvm/lib/Target/MSP430/MSP430GenSubtargetInfo.inc index fe346f86..9169bbcd 100644 --- a/llvm/lib/Target/MSP430/MSP430GenSubtargetInfo.inc +++ b/llvm/lib/Target/MSP430/MSP430GenSubtargetInfo.inc @@ -19,7 +19,7 @@ enum { FeatureX = 3 }; } // end namespace MSP430 -} // end namespace llvm +} // end namespace llvm_ks #endif // GET_SUBTARGETINFO_ENUM @@ -91,10 +91,11 @@ extern const llvm_ks::SubtargetInfoKV MSP430ProcSchedKV[] = { }; #undef DBGFIELD static inline MCSubtargetInfo *createMSP430MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) { - return new MCSubtargetInfo(TT, CPU, FS, MSP430FeatureKV, MSP430SubTypeKV, NULL); + return new MCSubtargetInfo(TT, CPU, FS, MSP430FeatureKV, MSP430SubTypeKV, NULL); + } -} // end namespace llvm +} // end namespace llvm_ks #endif // GET_SUBTARGETINFO_MC_DESC @@ -131,7 +132,7 @@ public: unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override; DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const; }; -} // end namespace llvm +} // end namespace llvm_ks #endif // GET_SUBTARGETINFO_HEADER @@ -157,7 +158,7 @@ unsigned MSP430GenSubtargetInfo ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const { report_fatal_error("Expected a variant SchedClass"); } // MSP430GenSubtargetInfo::resolveSchedClass -} // end namespace llvm +} // end namespace llvm_ks #endif // GET_SUBTARGETINFO_CTOR