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In below case, the parser think "0", "Time", "1", and "Freq" are ports.
I don't know which line make it confuse.
To prevent that I added two "(r'/*', 'block_comment', 'block_comment')," to the parameter/moduel_port description of verilog_tokens.
Then it worked fine.
output reg Store_Type, /*0:Time, 1:Freq*/
always @(negedge rstb, posedge clk)
begin
if (!rstb) begin
Store_Ant <= 0;
Store_Sym <= 0;
Store_Type <= 0; /*0:Time, 1:Freq*/
Store_val <= 0;
end
else begin
...
end
end
The text was updated successfully, but these errors were encountered:
KyleJeong
changed the title
verilog parser - Wrong parsing
verilog parser - Wrong parsing of comment
May 26, 2018
In below case, the parser think "0", "Time", "1", and "Freq" are ports.
I don't know which line make it confuse.
To prevent that I added two "(r'/*', 'block_comment', 'block_comment')," to the parameter/moduel_port description of verilog_tokens.
Then it worked fine.
output reg Store_Type, /*0:Time, 1:Freq*/
always @(negedge rstb, posedge clk)
begin
if (!rstb) begin
Store_Ant <= 0;
Store_Sym <= 0;
Store_Type <= 0; /*0:Time, 1:Freq*/
Store_val <= 0;
end
else begin
...
end
end
The text was updated successfully, but these errors were encountered: