From bc16d480a5f059926672ee5e70f1198a2c8fb37d Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Tue, 25 Sep 2018 11:39:11 +0800 Subject: [PATCH 01/58] Modify sensor size --- lib/firmware/include/ov5640cfg.h | 8 ++++---- lib/firmware/ov2640.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/firmware/include/ov5640cfg.h b/lib/firmware/include/ov5640cfg.h index ca3427ed..62154882 100644 --- a/lib/firmware/include/ov5640cfg.h +++ b/lib/firmware/include/ov5640cfg.h @@ -92,10 +92,10 @@ const uint16_t ov5640_init_reg_tbl[][2]= 0x3807, 0xa9, /* VH (VE) */ 0x3814, 0x31, /* timing X inc */ 0x3815, 0x31, /* timing Y inc */ - 0x3808, (320 >> 8), /* DVPHO */ - 0x3809, (320 & 0xff), /* DVPHO */ - 0x380a, (240 >> 8), /* DVPVO */ - 0x380b, (240 & 0xff), /* DVPVO */ + 0x3808, 0x01, /* DVPHO */ + 0x3809, 0x40, /* DVPHO */ + 0x380a, 0x00, /* DVPVO */ + 0x380b, 0xF0, /* DVPVO */ 0x380c, 0x05, /* HTS */ 0x380d, 0xF8, /* HTS */ 0x380e, 0x03, /* VTS */ diff --git a/lib/firmware/ov2640.c b/lib/firmware/ov2640.c index c91a9dd7..0cfa7f7d 100644 --- a/lib/firmware/ov2640.c +++ b/lib/firmware/ov2640.c @@ -75,7 +75,7 @@ static const uint8_t ov2640_config[][2] = {0x5f, 0x7d}, {0x60, 0x55}, {0x12, 0x40}, - {0x32, 0x09}, + {0x32, 0xC9}, {0x17, 0x11}, {0x18, 0x43}, {0x19, 0x00}, From fc00f7f5ce4695d9dae8ac92845f18703350deee Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Wed, 26 Sep 2018 13:29:53 +0800 Subject: [PATCH 02/58] Fix coding style --- lib/drivers/i2c.c | 64 +++++++------- lib/drivers/i2s.c | 122 +++++---------------------- lib/drivers/include/i2c.h | 13 ++- lib/drivers/include/i2s.h | 167 ++++++++++++++----------------------- lib/drivers/include/spi.h | 41 +++++---- lib/drivers/include/uart.h | 6 +- lib/drivers/spi.c | 126 +++++++++++++++------------- lib/drivers/timer.c | 3 +- lib/drivers/uart.c | 6 +- lib/firmware/w25qxx.c | 8 +- 10 files changed, 226 insertions(+), 330 deletions(-) diff --git a/lib/drivers/i2c.c b/lib/drivers/i2c.c index 9d74b8ca..06c8c335 100644 --- a/lib/drivers/i2c.c +++ b/lib/drivers/i2c.c @@ -50,7 +50,7 @@ void i2c_init(uint8_t sel, int clk_pin, int data_pin) dmac_init(); } -void i2c_config(uint8_t sel, size_t slaveAddress, size_t address_width,i2c_bus_speed_mode_t bus_speed_mode) +void i2c_config(uint8_t sel, size_t slave_address, size_t address_width,i2c_bus_speed_mode_t bus_speed_mode) { configASSERT(sel < I2C_MAX_NUM); configASSERT(address_width == 7 || address_width == 10); @@ -70,7 +70,7 @@ void i2c_config(uint8_t sel, size_t slaveAddress, size_t address_width,i2c_bus_s (address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(speed_mode); i2c_adapter->ss_scl_hcnt = I2C_SS_SCL_HCNT_COUNT(37); i2c_adapter->ss_scl_lcnt = I2C_SS_SCL_LCNT_COUNT(40); - i2c_adapter->tar = I2C_TAR_ADDRESS(slaveAddress); + i2c_adapter->tar = I2C_TAR_ADDRESS(slave_address); i2c_adapter->intr_mask = 0; i2c_adapter->dma_cr = 0x3; i2c_adapter->dma_rdlr = 0; @@ -78,48 +78,48 @@ void i2c_config(uint8_t sel, size_t slaveAddress, size_t address_width,i2c_bus_s i2c_adapter->enable = I2C_ENABLE_ENABLE; } -int i2c_write_reg(uint8_t sel, uint8_t reg, uint8_t* data_buf, uint8_t length) +int i2c_write_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len) { configASSERT(sel < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[sel]; uint8_t fifo_len, index; - fifo_len = length < 7 ? length : 7; + fifo_len = buf_len < 7 ? buf_len : 7; i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(reg); for (index = 0; index < fifo_len; index++) i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(*data_buf++); - length -= fifo_len; - while (length) + buf_len -= fifo_len; + while (buf_len) { fifo_len = 8 - i2c_adapter->txflr; - fifo_len = length < fifo_len ? length : fifo_len; + fifo_len = buf_len < fifo_len ? buf_len : fifo_len; for (index = 0; index < fifo_len; index++) i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(*data_buf++); if (i2c_adapter->tx_abrt_source != 0) return 1; - length -= fifo_len; + buf_len -= fifo_len; } while (i2c_adapter->status & I2C_STATUS_ACTIVITY) ; return 0; } -int i2c_write_reg_dma(dmac_channel_number_t channel_num, uint8_t sel, uint8_t reg, uint8_t* data_buf, uint8_t length) +int i2c_write_reg_dma(dmac_channel_number_t channel_num, uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len) { configASSERT(sel < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[sel]; - uint32_t* buf = malloc((length + 1) * sizeof(uint32_t)); + uint32_t* buf = malloc((buf_len + 1) * sizeof(uint32_t)); buf[0] = reg; int i; - for (i = 0; i < length + 1; i++) + for (i = 0; i < buf_len + 1; i++) { buf[i + 1] = data_buf[i]; } sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + sel * 2); dmac_set_single_mode(channel_num, buf, (void*)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, - DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, length + 1); + DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, buf_len + 1); dmac_wait_done(channel_num); free((void*)buf); @@ -132,19 +132,19 @@ int i2c_write_reg_dma(dmac_channel_number_t channel_num, uint8_t sel, uint8_t re return 0; } -int i2c_read_reg(uint8_t sel, uint8_t reg, uint8_t* data_buf, uint8_t length) +int i2c_read_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len) { uint8_t fifo_len, index; - uint8_t rx_len = length; + uint8_t rx_len = buf_len; configASSERT(sel < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[sel]; - fifo_len = length < 7 ? length : 7; + fifo_len = buf_len < 7 ? buf_len : 7; i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(reg); for (index = 0; index < fifo_len; index++) i2c_adapter->data_cmd = I2C_DATA_CMD_CMD; - length -= fifo_len; - while (length || rx_len) + buf_len -= fifo_len; + while (buf_len || rx_len) { fifo_len = i2c_adapter->rxflr; fifo_len = rx_len < fifo_len ? rx_len : fifo_len; @@ -152,41 +152,41 @@ int i2c_read_reg(uint8_t sel, uint8_t reg, uint8_t* data_buf, uint8_t length) *data_buf++ = i2c_adapter->data_cmd; rx_len -= fifo_len; fifo_len = 8 - i2c_adapter->txflr; - fifo_len = length < fifo_len ? length : fifo_len; + fifo_len = buf_len < fifo_len ? buf_len : fifo_len; for (index = 0; index < fifo_len; index++) i2c_adapter->data_cmd = I2C_DATA_CMD_CMD; if (i2c_adapter->tx_abrt_source != 0) return 1; - length -= fifo_len; + buf_len -= fifo_len; } return 0; } -int i2c_read_reg_dma(dmac_channel_number_t w_channel_num, dmac_channel_number_t r_channel_num, - uint8_t sel, uint8_t reg, uint8_t* data_buf, uint8_t length) +int i2c_read_reg_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, + uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len) { configASSERT(sel < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[sel]; - uint32_t* write_cmd = malloc(sizeof(uint32_t) * (1 + length)); + uint32_t* write_cmd = malloc(sizeof(uint32_t) * (1 + buf_len)); size_t i; write_cmd[0] = reg; - for (i = 0; i < length; i++) + for (i = 0; i < buf_len; i++) write_cmd[i + 1] = I2C_DATA_CMD_CMD; - sysctl_dma_select(w_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + sel * 2); - sysctl_dma_select(r_channel_num, SYSCTL_DMA_SELECT_I2C0_RX_REQ + sel * 2); + sysctl_dma_select(channel_num_w, SYSCTL_DMA_SELECT_I2C0_TX_REQ + sel * 2); + sysctl_dma_select(channel_num_r, SYSCTL_DMA_SELECT_I2C0_RX_REQ + sel * 2); - dmac_set_single_mode(r_channel_num, (void*)(&i2c_adapter->data_cmd), write_cmd, DMAC_ADDR_NOCHANGE, - DMAC_ADDR_INCREMENT,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, length); + dmac_set_single_mode(channel_num_r, (void*)(&i2c_adapter->data_cmd), write_cmd, DMAC_ADDR_NOCHANGE, + DMAC_ADDR_INCREMENT,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, buf_len); - dmac_set_single_mode(w_channel_num, write_cmd, (void*)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, - DMAC_ADDR_NOCHANGE,DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, length + 1); + dmac_set_single_mode(channel_num_w, write_cmd, (void*)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, + DMAC_ADDR_NOCHANGE,DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, buf_len + 1); - dmac_wait_done(w_channel_num); - dmac_wait_done(r_channel_num); + dmac_wait_done(channel_num_w); + dmac_wait_done(channel_num_r); - for (i = 0; i < length; i++) + for (i = 0; i < buf_len; i++) { data_buf[i] = write_cmd[i]; } diff --git a/lib/drivers/i2s.c b/lib/drivers/i2s.c index f3dd3615..36e80bee 100644 --- a/lib/drivers/i2s.c +++ b/lib/drivers/i2s.c @@ -157,7 +157,7 @@ void i2s_rx_channel_configure(i2s_device_num_t device_num, /* flush tx fifo*/ i2s_set_rx_word_length(device_num, word_length, channel_num); - /* Word length is RESOLUTION_32_BIT */ + /* Word buf_len is RESOLUTION_32_BIT */ i2s_master_configure(device_num, word_select_size, NO_CLOCK_GATING, word_mode); @@ -195,7 +195,7 @@ void i2s_tx_channel_configure(i2s_device_num_t device_num, i2s_transmit_dma_divide(I2S_DEVICE_0, 1); } i2s_set_tx_word_length(device_num, word_length, channel_num); - /* Word length is RESOLUTION_16_BIT */ + /* Word buf_len is RESOLUTION_16_BIT */ i2s_master_configure(device_num, word_select_size, NO_CLOCK_GATING, word_mode); /* word select size is 16 bits,gating after 16 bit */ @@ -405,9 +405,7 @@ int i2s_transmit_dma_divide(i2s_device_num_t device_num, uint32_t enable) return 0; } -int32_t i2s_receive_data(i2s_device_num_t device_num, - i2s_channel_num_t channel_num, uint64_t *buf, - uint32_t length) +int i2s_receive_data(i2s_device_num_t device_num, i2s_channel_num_t channel_num, uint64_t *buf, size_t buf_len) { uint32_t i = 0; isr_t u_isr; @@ -415,7 +413,7 @@ int32_t i2s_receive_data(i2s_device_num_t device_num, readl(&i2s[device_num]->channel[channel_num].ror); /*clear over run*/ - for (i = 0; i < length;) + for (i = 0; i < buf_len;) { u_isr.reg_data = readl(&i2s[device_num]->channel[channel_num].isr); if (u_isr.isr.rxda == 1) @@ -428,18 +426,8 @@ int32_t i2s_receive_data(i2s_device_num_t device_num, return 0; } -int32_t i2s_receive_data_dma(i2s_device_num_t device_num, uint32_t *buf, - uint32_t length, dmac_channel_number_t channel_num) -{ - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_I2S0_RX_REQ + device_num * 2); - dmac_set_single_mode(channel_num, (void *)(&i2s[device_num]->rxdma), /*pcm*/buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, - DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, length); - dmac_wait_done(channel_num); - return 0; -} - -int32_t i2s_recv_dma(i2s_device_num_t device_num, uint32_t *buf, - uint32_t length, dmac_channel_number_t channel_num) +int i2s_receive_data_dma(i2s_device_num_t device_num, uint32_t *buf, + size_t buf_len, dmac_channel_number_t channel_num) { static uint8_t dmac_recv_flag[6] = {0,0,0,0,0,0}; if(dmac_recv_flag[channel_num]) @@ -447,13 +435,13 @@ int32_t i2s_recv_dma(i2s_device_num_t device_num, uint32_t *buf, else dmac_recv_flag[channel_num] = 1; sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_I2S0_RX_REQ + device_num * 2); - dmac_set_single_mode(channel_num, (void *)(&i2s[device_num]->rxdma), /*pcm*/buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, - DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, length); + dmac_set_single_mode(channel_num, (void *)(&i2s[device_num]->rxdma), buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, + DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, buf_len); return 0; } -int32_t i2s_special_dma(i2s_device_num_t device_src_num, i2s_device_num_t device_dest_num, - uint32_t length, dmac_channel_number_t channel_num) +int i2s_rx_to_tx(i2s_device_num_t device_src_num, i2s_device_num_t device_dest_num, + size_t buf_len, dmac_channel_number_t channel_num) { static uint8_t dmac_recv_flag[6] = {0,0,0,0,0,0}; if(dmac_recv_flag[channel_num]) @@ -462,12 +450,11 @@ int32_t i2s_special_dma(i2s_device_num_t device_src_num, i2s_device_num_t device dmac_recv_flag[channel_num] = 1; sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_I2S0_RX_REQ + device_src_num * 2); dmac_set_single_mode(channel_num, (void *)(&i2s[device_src_num]->rxdma), (void *)(&i2s[device_dest_num]->txdma), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE, - DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, length); + DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, buf_len); return 0; } -int i2s_transmit_data(i2s_device_num_t device_num, - i2s_channel_num_t channel_num, uint8_t *pcm, uint32_t length, uint8_t single_length) +int i2s_send_data(i2s_device_num_t device_num, i2s_channel_num_t channel_num, uint8_t *pcm, size_t buf_len, size_t single_length) { isr_t u_isr; uint32_t left_buffer = 0; @@ -477,11 +464,11 @@ int i2s_transmit_data(i2s_device_num_t device_num, if (channel_num < CHANNEL_0 || channel_num > CHANNEL_3) return -1; - length = length / (single_length / 8) / 2; /* sample num */ + buf_len = buf_len / (single_length / 8) / 2; /* sample num */ readl(&i2s[device_num]->channel[channel_num].tor); /* read clear overrun flag */ - for (j = 0; j < length;) + for (j = 0; j < buf_len;) { u_isr.reg_data = readl(&i2s[device_num]->channel[channel_num].isr); if (u_isr.isr.txfe == 1) @@ -519,73 +506,7 @@ int i2s_transmit_data(i2s_device_num_t device_num, return 0; } -int i2s_trans_data(i2s_device_num_t device_num,i2s_channel_num_t channel_num, - uint8_t *pcm, uint32_t length, uint8_t single_length, uint8_t track_num) -{ - isr_t u_isr; - uint32_t left_buffer = 0; - uint32_t right_buffer = 0; - uint32_t i = 0; - uint32_t j = 0; - if (channel_num < CHANNEL_0 || channel_num > CHANNEL_3) - return -1; - readl(&i2s[device_num]->channel[channel_num].tor); - /* read clear overrun flag */ - - for (j = 0; j < length;) - { - u_isr.reg_data = readl(&i2s[device_num]->channel[channel_num].isr); - if (u_isr.isr.txfe == 1) - { - switch(single_length) - { - case 16: - left_buffer = ((uint16_t *)pcm)[i++]; - track_num == 2 ? (right_buffer = ((uint16_t *)pcm)[i++]) : (right_buffer = 0); - break; - case 24: - left_buffer = 0; - left_buffer |= pcm[i++]; - left_buffer |= pcm[i++] << 8; - left_buffer |= pcm[i++] << 16; - right_buffer = 0; - if(track_num == 2) - { - right_buffer |= pcm[i++]; - right_buffer |= pcm[i++] << 8; - right_buffer |= pcm[i++] << 16; - } - break; - case 32: - left_buffer = ((uint32_t *)pcm)[i++]; - track_num == 2 ? (right_buffer = ((uint32_t *)pcm)[i++]) : (right_buffer = 0); - break; - default: - left_buffer = pcm[i++]; - track_num == 2 ? (right_buffer = pcm[i++]) : (right_buffer = 0); - break; - } - writel(left_buffer, &i2s[device_num]->channel[channel_num].left_rxtx); - writel(right_buffer, &i2s[device_num]->channel[channel_num].right_rxtx); - j ++; - } - } - return 0; -} - -int i2s_transmit_data_dma(i2s_device_num_t device_num, - void *pcm, uint32_t length, uint8_t single_length, dmac_channel_number_t channel_num) -{ - length = length / (single_length / 8) / 2; - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_I2S0_TX_REQ + device_num * 2); - dmac_set_single_mode(channel_num, pcm/*buf*/, (void *)(&i2s[device_num]->txdma), DMAC_ADDR_INCREMENT, - DMAC_ADDR_NOCHANGE,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, length); - dmac_wait_done(channel_num); - return 0; -} - -void i2s_send_data_dma(i2s_device_num_t device_num, - void *pcm, uint32_t length, dmac_channel_number_t channel_num) +void i2s_send_data_dma(i2s_device_num_t device_num, void *pcm, size_t buf_len, dmac_channel_number_t channel_num) { static uint8_t dmac_init_flag[6] = {0,0,0,0,0,0}; if(dmac_init_flag[channel_num]) @@ -594,10 +515,10 @@ void i2s_send_data_dma(i2s_device_num_t device_num, dmac_init_flag[channel_num] = 1; sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_I2S0_TX_REQ + device_num * 2); dmac_set_single_mode(channel_num, pcm, (void *)(&i2s[device_num]->txdma), DMAC_ADDR_INCREMENT, - DMAC_ADDR_NOCHANGE, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, length); + DMAC_ADDR_NOCHANGE, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, buf_len); } -void parse_voice(uint32_t *buf, uint8_t *pcm, uint32_t length, uint32_t bits_per_sample, +void i2s_parse_voice(uint32_t *buf, uint8_t *pcm, uint32_t length, uint32_t bits_per_sample, uint8_t track_num, uint32_t *send_len) { uint32_t i,j=0; @@ -640,10 +561,11 @@ void parse_voice(uint32_t *buf, uint8_t *pcm, uint32_t length, uint32_t bits_pe } } + int i2s_play(i2s_device_num_t device_num,dmac_channel_number_t channel_num, - uint8_t *buf, size_t length, uint32_t frame, uint32_t bits_per_sample, uint8_t track_num) + uint8_t *buf, size_t buf_len, size_t frame, size_t bits_per_sample, uint8_t track_num) { - uint32_t sample_cnt = length / ( bits_per_sample / 8 ) / track_num; + uint32_t sample_cnt = buf_len / ( bits_per_sample / 8 ) / track_num; uint32_t frame_cnt = sample_cnt / frame; uint32_t frame_remain = sample_cnt % frame; uint32_t i; @@ -685,14 +607,14 @@ int i2s_play(i2s_device_num_t device_num,dmac_channel_number_t channel_num, for (i = 0; i < frame_cnt; i++) { trans_buf = buf + i * frame * (bits_per_sample / 8) * track_num; - parse_voice(buff[flag], trans_buf, frame, bits_per_sample, track_num, &send_len); + i2s_parse_voice(buff[flag], trans_buf, frame, bits_per_sample, track_num, &send_len); i2s_send_data_dma(device_num,buff[flag], send_len, channel_num); flag = !flag; } if (frame_remain) { trans_buf = buf + frame_cnt * frame * (bits_per_sample / 8) * track_num; - parse_voice(buff[flag], trans_buf, frame_remain, bits_per_sample, track_num, &send_len); + i2s_parse_voice(buff[flag], trans_buf, frame_remain, bits_per_sample, track_num, &send_len); i2s_send_data_dma(device_num, trans_buf, send_len, channel_num); } free(buff[0]); diff --git a/lib/drivers/include/i2c.h b/lib/drivers/include/i2c.h index 1ca3a2cc..b35fe56d 100644 --- a/lib/drivers/include/i2c.h +++ b/lib/drivers/include/i2c.h @@ -365,8 +365,7 @@ void i2c_clk_init(uint8_t sel); * @param[in] address_width address width 7bit or 10bit * @param[in] bus_speed_mode i2c rate */ -void i2c_config(uint8_t sel, size_t slaveAddress, size_t address_width, - i2c_bus_speed_mode_t bus_speed_mode); +void i2c_config(uint8_t sel, size_t slave_address, size_t address_width,i2c_bus_speed_mode_t bus_speed_mode); /** * @brief I2c send data @@ -380,7 +379,7 @@ void i2c_config(uint8_t sel, size_t slaveAddress, size_t address_width, * - 0 Success * - Other Fail */ -int i2c_write_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, uint8_t length); +int i2c_write_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len); /** * @brief I2c receive data @@ -394,7 +393,7 @@ int i2c_write_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, uint8_t length); * - 0 Success * - Other Fail */ -int i2c_read_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, uint8_t length); +int i2c_read_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len); /** * @brief I2c send data by dma @@ -409,7 +408,7 @@ int i2c_read_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, uint8_t length); * - 0 Success * - Other Fail */ -int i2c_write_reg_dma(dmac_channel_number_t channel_num, uint8_t sel, uint8_t reg, uint8_t *data_buf, uint8_t length); +int i2c_write_reg_dma(dmac_channel_number_t channel_num, uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len); /** * @brief I2c receive data @@ -424,8 +423,8 @@ int i2c_write_reg_dma(dmac_channel_number_t channel_num, uint8_t sel, uint8_t re * - 0 Success * - Other Fail */ -int i2c_read_reg_dma(dmac_channel_number_t w_channel_num, dmac_channel_number_t r_channel_num, - uint8_t sel, uint8_t reg, uint8_t *data_buf, uint8_t length); +int i2c_read_reg_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, + uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len); #ifdef __cplusplus } diff --git a/lib/drivers/include/i2s.h b/lib/drivers/include/i2s.h index 95786c83..b7f59eea 100644 --- a/lib/drivers/include/i2s.h +++ b/lib/drivers/include/i2s.h @@ -656,8 +656,7 @@ void i2s_dev_enable(i2s_device_num_t device_num, uint32_t enable); * - 0 Success * - Other Fail */ -int i2s_receive_channel_enable(i2s_device_num_t device_num, - i2s_channel_num_t channel_num, uint32_t enable); +int i2s_receive_channel_enable(i2s_device_num_t device_num, i2s_channel_num_t channel_num, uint32_t enable); /** * @brief Set I2S transmit channel enable or disable @@ -670,8 +669,17 @@ int i2s_receive_channel_enable(i2s_device_num_t device_num, * - 0 Success * - Other Fail */ -int i2s_transmit_channel_enable(i2s_device_num_t device_num, - i2s_channel_num_t channel_num, uint32_t enable); +int i2s_transmit_channel_enable(i2s_device_num_t device_num, i2s_channel_num_t channel_num, uint32_t enable); + +/** +* @brief I2s init +* +* @param[in] device_num The device number +* @param[in] rxtx_mode I2s work mode +* @param[in] channel_mask Channel mask to which channel work +* +*/ +void i2s_init(i2s_device_num_t device_num, i2s_transmit_t rxtx_mode, uint32_t channel_mask); /** * @brief Read pcm data from channel_num channel @@ -679,45 +687,84 @@ int i2s_transmit_channel_enable(i2s_device_num_t device_num, * @param[in] device_num which of device * @param[in] channel_num The channel number * @param[in] buf save read data - * @param[in] length the length to read form i2s + * @param[in] buf_len the length to read form i2s * * @return result * - 0 Success * - Other Fail */ -int32_t i2s_receive_data(i2s_device_num_t device_num, - i2s_channel_num_t channel_num, uint64_t *buf, - uint32_t length); +int i2s_receive_data(i2s_device_num_t device_num, i2s_channel_num_t channel_num, uint64_t *buf, size_t buf_len); /** * @brief Read pcm data from dma * * @param[in] device_num which of device * @param[in] buf save read data - * @param[in] length the length to read form i2s + * @param[in] buf_len the length to read form i2s * @param[in] channel_num The dma channel number * * @return result * - 0 Success * - Other Fail */ -int32_t i2s_receive_data_dma(i2s_device_num_t device_num, uint32_t *buf, - uint32_t length, dmac_channel_number_t channel_num); +int i2s_receive_data_dma(i2s_device_num_t device_num, uint32_t *buf, size_t buf_len, dmac_channel_number_t channel_num); /** - * @brief Read pcm data from dma + * @brief Write pcm data to channel_num channel * + * @param[in] device_num The i2s number + * @param[in] channel_num The channel number + * @param[in] pcm 32bit (16 bits left and 16bits right)pcm data * @param[in] device_num which of device - * @param[in] buf save read data - * @param[in] length the length to read form i2s - * @param[in] channel_num The dma channel number * * @return result * - 0 Success * - Other Fail */ -int32_t i2s_recv_dma(i2s_device_num_t device_num, uint32_t *buf, - uint32_t length, dmac_channel_number_t channel_num); +int i2s_send_data(i2s_device_num_t device_num, i2s_channel_num_t channel_num, uint8_t *pcm, size_t buf_len, size_t single_length); + +/** + * @brief Write pcm data to channel_num channel by dma, first wait dmac done + * + * @param[in] device_num which of device + * @param[in] pcm Send data + * @param[in] buf_len Send data length + * @param[in] channel_num dmac channel + * + */ +void i2s_send_data_dma(i2s_device_num_t device_num, void *pcm, size_t buf_len, dmac_channel_number_t channel_num); + +/** + * @brief Write pcm data to channel_num channel by dma + * + * @param[in] device_num which of device + * @param[in] channel_num which of device + * @param[in] buf Send data + * @param[in] buf_len Send data length + * @param[in] frame I2s frame number + * @param[in] bits_per_sample I2s sample bits + * @param[in] track_num track num + * + * @return result + * - 0 Success + * - Other Fail + */ +int i2s_play(i2s_device_num_t device_num,dmac_channel_number_t channel_num, uint8_t *buf, size_t buf_len, size_t frame, size_t bits_per_sample, uint8_t track_num); + +/** + * @brief Send receive data to transmit channel by dma + * + * @param[in] device_src_num I2s receive + * @param[in] device_dest_num I2s transfer + * @param[in] buf_len Data length + * @param[in] channel_num Dmac channel + * + * @return result + * - 0 Success + * - Other Fail + */ +int i2s_rx_to_tx(i2s_device_num_t device_src_num, i2s_device_num_t device_dest_num, + size_t buf_len, dmac_channel_number_t channel_num); /** * @brief Mask or unmask interrupt @@ -918,92 +965,6 @@ int i2s_receive_dma_enable(i2s_device_num_t device_num, uint32_t enable); */ int i2s_transmit_dma_divide(i2s_device_num_t device_num, uint32_t enable); -/** - * @brief Write pcm data to channel_num channel - * - * @param[in] device_num The i2s number - * @param[in] channel_num The channel number - * @param[in] pcm 32bit (16 bits left and 16bits right)pcm data - * @param[in] device_num which of device - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_transmit_data(i2s_device_num_t device_num, - i2s_channel_num_t channel_num, uint8_t *pcm, uint32_t length, uint8_t single_length); - -/** - * @brief I2s init - * - * @param[in] device_num The device number - * @param[in] rxtx_mode I2s work mode - * @param[in] channel_mask Channel mask to which channel work - * - */ -void i2s_init(i2s_device_num_t device_num, i2s_transmit_t rxtx_mode, uint32_t channel_mask); - -/** - * @brief Write pcm data to channel_num channel by dma - * - * @param[in] device_num which of device - * @param[in] pcm Send data - * @param[in] length Send data length - * @param[in] single_length Send data width - * @param[in] channel_num dmac channel - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_transmit_data_dma(i2s_device_num_t device_num, - void *pcm, uint32_t length, uint8_t single_length, dmac_channel_number_t channel_num); - -/** - * @brief Write pcm data to channel_num channel by dma, first wait dmac done - * - * @param[in] device_num which of device - * @param[in] pcm Send data - * @param[in] length Send data length - * @param[in] channel_num dmac channel - * - */ -void i2s_send_data_dma(i2s_device_num_t device_num, - void *pcm, uint32_t length, dmac_channel_number_t channel_num); - -/** - * @brief Write pcm data to channel_num channel by dma - * - * @param[in] device_num which of device - * @param[in] channel_num which of device - * @param[in] buf Send data - * @param[in] length Send data length - * @param[in] frame I2s frame number - * @param[in] bits_per_sample I2s sample bits - * @param[in] track_num track num - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_play(i2s_device_num_t device_num,dmac_channel_number_t channel_num, - uint8_t *buf, size_t length, uint32_t frame, uint32_t bits_per_sample, uint8_t track_num); - -/** - * @brief Write pcm data by dma from i2s to i2s - * - * @param[in] device_src_num I2s receive - * @param[in] device_dest_num I2s transfer - * @param[in] length Data length - * @param[in] channel_num Dmac channel - * - * @return result - * - 0 Success - * - Other Fail - */ -int32_t i2s_special_dma(i2s_device_num_t device_src_num, i2s_device_num_t device_dest_num, - uint32_t length, dmac_channel_number_t channel_num); - #ifdef __cplusplus } #endif diff --git a/lib/drivers/include/spi.h b/lib/drivers/include/spi.h index 848eaff4..a9e38348 100644 --- a/lib/drivers/include/spi.h +++ b/lib/drivers/include/spi.h @@ -197,8 +197,7 @@ void spi_trans_config(uint8_t spi_bus, size_t instruction_length, size_t address * - 0 Success * - Other Fail */ -int spi_send_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, - uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len); +int spi_send_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** @@ -215,8 +214,7 @@ int spi_send_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, * - 0 Success * - Other Fail */ -int spi_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, - uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len); +int spi_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** @@ -233,8 +231,7 @@ int spi_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, * - 0 Success * - Other Fail */ -int spi_special_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, - uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len); +int spi_quad_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special send data @@ -250,8 +247,7 @@ int spi_special_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_b * - 0 Success * - Other Fail */ -int spi_special_send_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, - uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len); +int spi_quad_send_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** * @brief Spi set transfer mode @@ -350,7 +346,7 @@ void spi_set_trans_mode(uint8_t spi_bus, spi_addr_inst_trans_mode_t trans_mode); * - Other Fail */ int spi_send_data_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, - uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len); + uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** @@ -369,8 +365,8 @@ int spi_send_data_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32 * - 0 Success * - Other Fail */ -int spi_receive_data_dma(dmac_channel_number_t w_channel_num, dmac_channel_number_t r_channel_num, - uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len); +int spi_receive_data_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, + uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** @@ -388,8 +384,8 @@ int spi_receive_data_dma(dmac_channel_number_t w_channel_num, dmac_channel_numbe * - 0 Success * - Other Fail */ -int spi_special_send_data_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, - uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len); +int spi_quad_send_data_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, + uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** * @brief Spi special receive data by dma @@ -407,8 +403,8 @@ int spi_special_send_data_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, * - 0 Success * - Other Fail */ -int spi_special_receive_data_dma(dmac_channel_number_t w_channel_num, dmac_channel_number_t r_channel_num, - uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len); +int spi_quad_receive_data_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, + uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi fill dma @@ -423,8 +419,7 @@ int spi_special_receive_data_dma(dmac_channel_number_t w_channel_num, dmac_chann * - 0 Success * - Other Fail */ -int spi_fill_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, - uint32_t *cmd_buff, uint32_t cmd_len); +int spi_fill_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len); /** * @brief Spi normal send by dma @@ -441,7 +436,17 @@ int spi_fill_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chi * - Other Fail */ int spi_normal_send_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, - void *tx_buff, uint32_t tx_len, spi_transfer_width_t stw); + void *tx_buff, size_t tx_len, spi_transfer_width_t stw); + +/** + * @brief Spi normal send by dma + * + * @param[in] spi_bus Spi bus number + * @param[in] spi_clk Spi clock rate + * + * @return The real spi clock rate + */ +uint32_t spi_set_clk_rate(uint8_t spi_bus, uint32_t spi_clk); #ifdef __cplusplus } diff --git a/lib/drivers/include/uart.h b/lib/drivers/include/uart.h index 8d3009eb..4efc8884 100644 --- a/lib/drivers/include/uart.h +++ b/lib/drivers/include/uart.h @@ -149,9 +149,9 @@ typedef enum _uart_rede_sel typedef enum _uart_parity { - UART_PARITY_None, - UART_PARITY_Odd, - UART_PARITY_Even + UART_PARITY_NONE, + UART_PARITY_ODD, + UART_PARITY_EVEN } uart_parity_t; /** diff --git a/lib/drivers/spi.c b/lib/drivers/spi.c index fee48e1b..4b4304d0 100644 --- a/lib/drivers/spi.c +++ b/lib/drivers/spi.c @@ -30,20 +30,23 @@ volatile spi_t *const spi[4] = (volatile spi_t *)SPI3_BASE_ADDR }; -int spi_clk_init(uint8_t spi_bus){ +int spi_clk_init(uint8_t spi_bus) +{ configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); sysctl_clock_enable(SYSCTL_CLOCK_SPI0 + spi_bus); sysctl_clock_set_threshold(SYSCTL_THRESHOLD_SPI0 + spi_bus, 0); return 0; } -int spi_init(uint8_t spi_bus){ +int spi_init(uint8_t spi_bus) +{ spi_clk_init(spi_bus); dmac_init(); return 0; } -int spi_master_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame_format, size_t data_bit_length){ +int spi_master_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame_format, size_t data_bit_length) +{ configASSERT(data_bit_length >= 4 && data_bit_length <= 32); configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); @@ -92,6 +95,22 @@ int spi_master_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame return 0; } +uint32_t spi_set_clk_rate(uint8_t spi_bus, uint32_t spi_clk) +{ + uint32_t spi_baudr = sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_bus) / spi_clk; + if(spi_baudr < 2 ) + { + spi_baudr = 2; + } + else if(spi_baudr > 65534) + { + spi_baudr = 65534; + } + volatile spi_t *spi_adapter = spi[spi_bus]; + spi_adapter->baudr = spi_baudr; + return sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_bus) / spi_baudr; +} + void spi_trans_config(uint8_t spi_bus, size_t instruction_length, size_t address_length, size_t wait_cycles, spi_addr_inst_trans_mode_t trans_mode) { @@ -125,7 +144,7 @@ void spi_trans_config(uint8_t spi_bus, size_t instruction_length, size_t address spi_handle->spi_ctrlr0 = (wait_cycles << 11) | (inst_l << 8) | (addr_l << 2) | trans_mode; } -int spi_send_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) +int spi_send_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { uint32_t index, fifo_len; configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); @@ -157,7 +176,7 @@ int spi_send_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, uint8_t } int spi_send_data_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, - uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) + uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); volatile spi_t *spi_handle = spi[spi_bus]; @@ -181,7 +200,6 @@ int spi_send_data_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32 dmac_wait_done(channel_num); free((void*)buf); - while ((spi_handle->sr & 0x05) != 0x04) ; spi_handle->ser = 0x00; @@ -190,7 +208,7 @@ int spi_send_data_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32 } int spi_normal_send_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, - void *tx_buff, uint32_t tx_len, spi_transfer_width_t stw) + void *tx_buff, size_t tx_len, spi_transfer_width_t stw) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); volatile spi_t *spi_handle = spi[spi_bus]; @@ -229,7 +247,7 @@ int spi_normal_send_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint return 0; } -int spi_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) +int spi_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { uint32_t index, fifo_len; configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); @@ -252,8 +270,8 @@ int spi_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, uint return 0; } -int spi_receive_data_dma(dmac_channel_number_t w_channel_num, dmac_channel_number_t r_channel_num, - uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) +int spi_receive_data_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, + uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); volatile spi_t *spi_handle = spi[spi_bus]; @@ -268,18 +286,17 @@ int spi_receive_data_dma(dmac_channel_number_t w_channel_num, dmac_channel_numbe spi_handle->ssienr = 0x01; spi_handle->ser = chip_sel; - sysctl_dma_select(w_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_bus * 2); - sysctl_dma_select(r_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_bus * 2); - + sysctl_dma_select(channel_num_w, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_bus * 2); + sysctl_dma_select(channel_num_r, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_bus * 2); - dmac_set_single_mode(r_channel_num, (void *)(&spi_handle->dr[0]), write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, + dmac_set_single_mode(channel_num_r, (void *)(&spi_handle->dr[0]), write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len); - dmac_set_single_mode(w_channel_num, write_cmd, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, + dmac_set_single_mode(channel_num_w, write_cmd, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len); - dmac_wait_done(w_channel_num); - dmac_wait_done(r_channel_num); + dmac_wait_done(channel_num_w); + dmac_wait_done(channel_num_r); for(i = 0; i < rx_len; i++){ rx_buff[i] = write_cmd[i]; @@ -291,8 +308,7 @@ int spi_receive_data_dma(dmac_channel_number_t w_channel_num, dmac_channel_numbe return 0; } - -int spi_special_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) +int spi_quad_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { uint32_t index, fifo_len; configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); @@ -315,47 +331,44 @@ int spi_special_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_b return 0; } -int spi_special_receive_data_dma(dmac_channel_number_t w_channel_num, dmac_channel_number_t r_channel_num, - uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) +int spi_quad_receive_data_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, + uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - volatile spi_t *spi_handle = spi[spi_bus]; - - uint32_t * write_cmd = malloc(sizeof(uint32_t) * (cmd_len + rx_len)); - size_t i; - for (i = 0; i < cmd_len; i++) - write_cmd[i] = cmd_buff[i]; - - spi_handle->ctrlr1 = rx_len - 1; - spi_handle->dmacr = 0x3; - spi_handle->ssienr = 0x01; - spi_handle->ser = chip_sel; + configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); + volatile spi_t *spi_handle = spi[spi_bus]; - sysctl_dma_select(w_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_bus * 2); - sysctl_dma_select(r_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_bus * 2); + uint32_t * write_cmd = malloc(sizeof(uint32_t) * (cmd_len + rx_len)); + size_t i; + for (i = 0; i < cmd_len; i++) + write_cmd[i] = cmd_buff[i]; + spi_handle->ctrlr1 = rx_len - 1; + spi_handle->dmacr = 0x3; + spi_handle->ssienr = 0x01; + spi_handle->ser = chip_sel; - dmac_set_single_mode(r_channel_num, (void *)(&spi_handle->dr[0]), write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, - DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len); + sysctl_dma_select(channel_num_w, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_bus * 2); + sysctl_dma_select(channel_num_r, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_bus * 2); - dmac_set_single_mode(w_channel_num, write_cmd, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, - DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len); + dmac_set_single_mode(channel_num_r, (void *)(&spi_handle->dr[0]), write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, + DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len); - dmac_wait_done(w_channel_num); - dmac_wait_done(r_channel_num); + dmac_set_single_mode(channel_num_w, write_cmd, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, + DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len); - for(i = 0; i < rx_len; i++){ - rx_buff[i] = write_cmd[i]; - } - free(write_cmd); - spi_handle->ser = 0x00; - spi_handle->ssienr = 0x00; - return 0; + dmac_wait_done(channel_num_w); + dmac_wait_done(channel_num_r); + for(i = 0; i < rx_len; i++){ + rx_buff[i] = write_cmd[i]; + } + free(write_cmd); + spi_handle->ser = 0x00; + spi_handle->ssienr = 0x00; + return 0; } - -int spi_special_send_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) +int spi_quad_send_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { uint32_t index, fifo_len; configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); @@ -385,8 +398,8 @@ int spi_special_send_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff return 0; } -int spi_special_send_data_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, - uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) +int spi_quad_send_data_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, + uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); volatile spi_t *spi_handle = spi[spi_bus]; @@ -417,8 +430,7 @@ int spi_special_send_data_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, return 0; } -int spi_fill_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, - uint32_t *cmd_buff, uint32_t cmd_len) +int spi_fill_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); volatile spi_t *spi_handle = spi[spi_bus]; @@ -504,11 +516,7 @@ int spi_get_frame_format(uint8_t spi_bus) return ((spi_handle->ctrlr0 >> frf_offset) & 0x03); } -/* - SPI MODE0-3 - Serial Clock Polarity - Serial Clock Phase -*/ + void spi_set_work_mode(uint8_t spi_bus, spi_mode_t mode) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); diff --git a/lib/drivers/timer.c b/lib/drivers/timer.c index 9322e581..568a75fc 100644 --- a/lib/drivers/timer.c +++ b/lib/drivers/timer.c @@ -124,7 +124,8 @@ void timer_channel_clear_interrupt(uint32_t tim, uint32_t channel) timer[tim]->channel[channel].eoi = timer[tim]->channel[channel].eoi; } -void timer_set_enable(uint32_t tim, uint32_t channel, uint32_t enable){ +void timer_set_enable(uint32_t tim, uint32_t channel, uint32_t enable) +{ if (enable) timer[tim]->channel[channel].control = TIMER_CR_USER_MODE | TIMER_CR_ENABLE; else diff --git a/lib/drivers/uart.c b/lib/drivers/uart.c index 255b683a..e15722bc 100644 --- a/lib/drivers/uart.c +++ b/lib/drivers/uart.c @@ -143,13 +143,13 @@ void uart_config(uint8_t channel, size_t baud_rate, size_t data_width, uart_stop uint32_t parity_val; switch (parity) { - case UART_PARITY_None: + case UART_PARITY_NONE: parity_val = 0; break; - case UART_PARITY_Odd: + case UART_PARITY_ODD: parity_val = 1; break; - case UART_PARITY_Even: + case UART_PARITY_EVEN: parity_val = 3; break; default: diff --git a/lib/firmware/w25qxx.c b/lib/firmware/w25qxx.c index 95f3b66f..655e799f 100644 --- a/lib/firmware/w25qxx.c +++ b/lib/firmware/w25qxx.c @@ -61,25 +61,25 @@ static w25qxx_status_t w25qxx_send_data_dma(uint8_t *cmd_buff, uint8_t cmd_len, static w25qxx_status_t w25qxx_receive_data_enhanced(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) { - spi_special_receive_data(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); + spi_quad_receive_data(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); return W25QXX_OK; } static w25qxx_status_t w25qxx_receive_data_enhanced_dma(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) { - spi_special_receive_data_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); + spi_quad_receive_data_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); return W25QXX_OK; } static w25qxx_status_t w25qxx_send_data_enhanced(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) { - spi_special_send_data(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); + spi_quad_send_data(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); return W25QXX_OK; } static w25qxx_status_t w25qxx_send_data_enhanced_dma(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) { - spi_special_send_data_dma(DMAC_CHANNEL0, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); + spi_quad_send_data_dma(DMAC_CHANNEL0, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); return W25QXX_OK; } From cf90287c6392a57e9d39d47ef3091df0c6252461 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Thu, 27 Sep 2018 23:02:11 +0800 Subject: [PATCH 03/58] Modify i2c driver --- lib/drivers/i2c.c | 142 +++++++++++++++++--------------------- lib/drivers/include/i2c.h | 98 +++++++++++--------------- 2 files changed, 106 insertions(+), 134 deletions(-) diff --git a/lib/drivers/i2c.c b/lib/drivers/i2c.c index 06c8c335..ae7d5d60 100644 --- a/lib/drivers/i2c.c +++ b/lib/drivers/i2c.c @@ -28,32 +28,18 @@ volatile i2c_t* const i2c[3] = (volatile i2c_t*)I2C2_BASE_ADDR }; -void i2c_pin_init(uint8_t sel, int clk_pin, int data_pin) +static void i2c_clk_init(i2c_device_num_t i2c_num) { - configASSERT(sel < I2C_MAX_NUM); - fpioa_set_function(clk_pin, FUNC_I2C0_SCLK + (2 * sel)); - fpioa_set_function(data_pin, FUNC_I2C0_SDA + (2 * sel)); + configASSERT(i2c_num < I2C_MAX_NUM); + sysctl_clock_enable(SYSCTL_CLOCK_I2C0 + i2c_num); + sysctl_clock_set_threshold(SYSCTL_THRESHOLD_I2C0 + i2c_num, 3); } -void i2c_clk_init(uint8_t sel) +void i2c_config(i2c_device_num_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode) { - configASSERT(sel < I2C_MAX_NUM); - sysctl_clock_enable(SYSCTL_CLOCK_I2C0 + sel); - sysctl_clock_set_threshold(SYSCTL_THRESHOLD_I2C0 + sel, 3); -} - -void i2c_init(uint8_t sel, int clk_pin, int data_pin) -{ - configASSERT(sel < I2C_MAX_NUM); - i2c_pin_init(sel, clk_pin, data_pin); - i2c_clk_init(sel); - dmac_init(); -} - -void i2c_config(uint8_t sel, size_t slave_address, size_t address_width,i2c_bus_speed_mode_t bus_speed_mode) -{ - configASSERT(sel < I2C_MAX_NUM); + configASSERT(i2c_num < I2C_MAX_NUM); configASSERT(address_width == 7 || address_width == 10); + i2c_clk_init(i2c_num); int speed_mode = 1; switch (bus_speed_mode) { @@ -64,7 +50,7 @@ void i2c_config(uint8_t sel, size_t slave_address, size_t address_width,i2c_bus_ break; } /*set config*/ - volatile i2c_t* i2c_adapter = i2c[sel]; + volatile i2c_t* i2c_adapter = i2c[i2c_num]; i2c_adapter->enable = 0; i2c_adapter->con = I2C_CON_MASTER_MODE | I2C_CON_SLAVE_DISABLE | I2C_CON_RESTART_EN | (address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(speed_mode); @@ -78,50 +64,44 @@ void i2c_config(uint8_t sel, size_t slave_address, size_t address_width,i2c_bus_ i2c_adapter->enable = I2C_ENABLE_ENABLE; } -int i2c_write_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len) +int i2c_send_data(i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len) { - configASSERT(sel < I2C_MAX_NUM); - volatile i2c_t* i2c_adapter = i2c[sel]; + configASSERT(i2c_num < I2C_MAX_NUM); + volatile i2c_t* i2c_adapter = i2c[i2c_num]; uint8_t fifo_len, index; - fifo_len = buf_len < 7 ? buf_len : 7; - i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(reg); - for (index = 0; index < fifo_len; index++) - i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(*data_buf++); - buf_len -= fifo_len; - while (buf_len) + while (send_buf_len) { fifo_len = 8 - i2c_adapter->txflr; - fifo_len = buf_len < fifo_len ? buf_len : fifo_len; + fifo_len = send_buf_len < fifo_len ? send_buf_len : fifo_len; for (index = 0; index < fifo_len; index++) - i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(*data_buf++); + i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(*send_buf++); if (i2c_adapter->tx_abrt_source != 0) return 1; - buf_len -= fifo_len; + send_buf_len -= fifo_len; } while (i2c_adapter->status & I2C_STATUS_ACTIVITY) ; return 0; } -int i2c_write_reg_dma(dmac_channel_number_t channel_num, uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len) +int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len) { - configASSERT(sel < I2C_MAX_NUM); - volatile i2c_t* i2c_adapter = i2c[sel]; + configASSERT(i2c_num < I2C_MAX_NUM); + volatile i2c_t* i2c_adapter = i2c[i2c_num]; - uint32_t* buf = malloc((buf_len + 1) * sizeof(uint32_t)); - buf[0] = reg; + uint32_t* buf = malloc(send_buf_len * sizeof(uint32_t)); int i; - for (i = 0; i < buf_len + 1; i++) + for (i = 0; i < send_buf_len; i++) { - buf[i + 1] = data_buf[i]; + buf[i] = send_buf[i]; } - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + sel * 2); - dmac_set_single_mode(channel_num, buf, (void*)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, - DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, buf_len + 1); + sysctl_dma_select(dma_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2); + dmac_set_single_mode(dma_channel_num, buf, (void*)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, + DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, send_buf_len); - dmac_wait_done(channel_num); + dmac_wait_done(dma_channel_num); free((void*)buf); while (i2c_adapter->status & I2C_STATUS_ACTIVITY) @@ -132,65 +112,73 @@ int i2c_write_reg_dma(dmac_channel_number_t channel_num, uint8_t sel, uint8_t re return 0; } -int i2c_read_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len) +int i2c_receive_data(i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len) { uint8_t fifo_len, index; - uint8_t rx_len = buf_len; - configASSERT(sel < I2C_MAX_NUM); - volatile i2c_t* i2c_adapter = i2c[sel]; - - fifo_len = buf_len < 7 ? buf_len : 7; - i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(reg); - for (index = 0; index < fifo_len; index++) - i2c_adapter->data_cmd = I2C_DATA_CMD_CMD; - buf_len -= fifo_len; - while (buf_len || rx_len) + uint8_t rx_len = receive_buf_len; + configASSERT(i2c_num < I2C_MAX_NUM); + volatile i2c_t* i2c_adapter = i2c[i2c_num]; + + while (send_buf_len) + { + fifo_len = 8 - i2c_adapter->txflr; + fifo_len = send_buf_len < fifo_len ? send_buf_len : fifo_len; + for (index = 0; index < fifo_len; index++) + i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(*send_buf++); + if (i2c_adapter->tx_abrt_source != 0) + return 1; + send_buf_len -= fifo_len; + } + + while (receive_buf_len || rx_len) { fifo_len = i2c_adapter->rxflr; fifo_len = rx_len < fifo_len ? rx_len : fifo_len; for (index = 0; index < fifo_len; index++) - *data_buf++ = i2c_adapter->data_cmd; + *receive_buf++ = i2c_adapter->data_cmd; rx_len -= fifo_len; fifo_len = 8 - i2c_adapter->txflr; - fifo_len = buf_len < fifo_len ? buf_len : fifo_len; + fifo_len = receive_buf_len < fifo_len ? receive_buf_len : fifo_len; for (index = 0; index < fifo_len; index++) i2c_adapter->data_cmd = I2C_DATA_CMD_CMD; if (i2c_adapter->tx_abrt_source != 0) return 1; - buf_len -= fifo_len; + receive_buf_len -= fifo_len; } return 0; } -int i2c_read_reg_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, - uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len) +int i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, + i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len) { - configASSERT(sel < I2C_MAX_NUM); - volatile i2c_t* i2c_adapter = i2c[sel]; + configASSERT(i2c_num < I2C_MAX_NUM); + volatile i2c_t* i2c_adapter = i2c[i2c_num]; - uint32_t* write_cmd = malloc(sizeof(uint32_t) * (1 + buf_len)); + uint32_t* write_cmd = malloc(sizeof(uint32_t) * (send_buf_len + receive_buf_len)); size_t i; - write_cmd[0] = reg; - for (i = 0; i < buf_len; i++) - write_cmd[i + 1] = I2C_DATA_CMD_CMD; + for(i = 0; i < send_buf_len; i++) + write_cmd[i] = *send_buf++; + for (i = 0; i < receive_buf_len; i++) + write_cmd[i + send_buf_len] = I2C_DATA_CMD_CMD; - sysctl_dma_select(channel_num_w, SYSCTL_DMA_SELECT_I2C0_TX_REQ + sel * 2); - sysctl_dma_select(channel_num_r, SYSCTL_DMA_SELECT_I2C0_RX_REQ + sel * 2); + sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2); + sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_I2C0_RX_REQ + i2c_num * 2); - dmac_set_single_mode(channel_num_r, (void*)(&i2c_adapter->data_cmd), write_cmd, DMAC_ADDR_NOCHANGE, - DMAC_ADDR_INCREMENT,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, buf_len); + dmac_set_single_mode(dma_receive_channel_num, (void*)(&i2c_adapter->data_cmd), write_cmd, DMAC_ADDR_NOCHANGE, + DMAC_ADDR_INCREMENT,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, receive_buf_len); - dmac_set_single_mode(channel_num_w, write_cmd, (void*)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, - DMAC_ADDR_NOCHANGE,DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, buf_len + 1); + dmac_set_single_mode(dma_send_channel_num, write_cmd, (void*)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, + DMAC_ADDR_NOCHANGE,DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, receive_buf_len + send_buf_len); - dmac_wait_done(channel_num_w); - dmac_wait_done(channel_num_r); + dmac_wait_done(dma_send_channel_num); + dmac_wait_done(dma_receive_channel_num); - for (i = 0; i < buf_len; i++) + for (i = 0; i < receive_buf_len; i++) { - data_buf[i] = write_cmd[i]; + receive_buf[i] = write_cmd[i]; } free(write_cmd); return 0; } + diff --git a/lib/drivers/include/i2c.h b/lib/drivers/include/i2c.h index b35fe56d..af65d536 100644 --- a/lib/drivers/include/i2c.h +++ b/lib/drivers/include/i2c.h @@ -325,6 +325,14 @@ typedef struct _i2c extern volatile i2c_t *const i2c[3]; +typedef enum _i2c_device_num +{ + I2C_DEVICE_0, + I2C_DEVICE_1, + I2C_DEVICE_2, + I2C_DEVICE_MAX, +} i2c_device_num_t; + typedef enum _i2c_bus_speed_mode { I2C_BS_STANDARD, @@ -333,98 +341,74 @@ typedef enum _i2c_bus_speed_mode } i2c_bus_speed_mode_t; /** - * @brief I2c init - * - * @param[in] sel i2c bus - * @param[in] clk_pin i2c clk pin - * @param[in] data_pin i2c data pin - */ -void i2c_init(uint8_t sel, int clk_pin, int data_pin); - -/** - * @brief I2c pin init + * @brief Set i2c params * - * @param[in] sel i2c bus - * @param[in] clk_pin i2c clk pin - * @param[in] data_pin i2c data pin - */ -void i2c_pin_init(uint8_t sel, int clk_pin, int data_pin); - -/** - * @brief I2c clk init - * - * @param[in] sel i2c bus - */ -void i2c_clk_init(uint8_t sel); - -/** - * @brief I2c set param - * - * @param[in] sel i2c bus - * @param[in] slaveAddress i2c slave address + * @param[in] i2c_num i2c number + * @param[in] slave_address i2c slave device address * @param[in] address_width address width 7bit or 10bit * @param[in] bus_speed_mode i2c rate */ -void i2c_config(uint8_t sel, size_t slave_address, size_t address_width,i2c_bus_speed_mode_t bus_speed_mode); +void i2c_config(i2c_device_num_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode); /** * @brief I2c send data * - * @param[in] sel i2c bus - * @param[in] reg i2c slave reg address - * @param[in] data_buf send data - * @param[in] length send length + * @param[in] i2c_num i2c number + * @param[in] send_buf send data + * @param[in] send_buf_len send data length * * @return result * - 0 Success * - Other Fail */ -int i2c_write_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len); +int i2c_send_data(i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len); - /** - * @brief I2c receive data +/** + * @brief I2c send data by dma * - * @param[in] sel i2c bus - * @param[in] reg i2c slave reg address - * @param[in] data_buf receive data - * @param[in] length receive length + * @param[in] dma_channel_num dma channel + * @param[in] i2c_num i2c number + * @param[in] send_buf send data + * @param[in] send_buf_len send data length * * @return result * - 0 Success * - Other Fail */ -int i2c_read_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len); +int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len); /** - * @brief I2c send data by dma + * @brief I2c receive data * - * @param[in] channel_num dma channel - * @param[in] sel i2c bus - * @param[in] reg i2c slave reg address - * @param[in] data_buf send data - * @param[in] length send length + * @param[in] i2c_num i2c number + * @param[in] send_buf send data address + * @param[in] send_buf_len length of send buf + * @param[in] receive_buf receive buf address + * @param[in] receive_buf_len length of receive buf * * @return result * - 0 Success * - Other Fail - */ -int i2c_write_reg_dma(dmac_channel_number_t channel_num, uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len); +*/ +int i2c_receive_data(i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len); /** - * @brief I2c receive data + * @brief I2c receive data by dma * - * @param[in] channel_num dma channel - * @param[in] sel i2c bus - * @param[in] reg i2c slave reg address - * @param[in] data_buf receive data - * @param[in] length receive length + * @param[in] dma_send_channel_num send dma channel + * @param[in] dma_receive_channel_num receive dma channel + * @param[in] i2c_num i2c number + * @param[in] send_buf send data address + * @param[in] send_buf_len length of send buf + * @param[in] receive_buf receive buf address + * @param[in] receive_buf_len length of receive buf * * @return result * - 0 Success * - Other Fail */ -int i2c_read_reg_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, - uint8_t sel, uint8_t reg, uint8_t *data_buf, size_t buf_len); +int i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, + i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len); #ifdef __cplusplus } From 8f78288f2951791fef4cfca101ef5e994cc96e54 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Thu, 27 Sep 2018 23:03:13 +0800 Subject: [PATCH 04/58] Modify sd3068 demo --- lib/firmware/include/sd3068.h | 3 ++- lib/firmware/sd3068.c | 27 +++++++++++++++++++-------- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/lib/firmware/include/sd3068.h b/lib/firmware/include/sd3068.h index 2f0c1470..696ec8e1 100644 --- a/lib/firmware/include/sd3068.h +++ b/lib/firmware/include/sd3068.h @@ -16,6 +16,7 @@ #define _SD3068_H #include +#include "i2c.h" #define SD3068_ADDR 0x32 #define SD3068_ADDR_LENTH 7 @@ -30,7 +31,7 @@ typedef struct _sd_time uint32_t sec:6; } __attribute__((packed, aligned(4))) sd_time_t; -void sd3068_init(uint8_t sel); +void sd3068_init(i2c_device_num_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode); int sd3068_write_enable(void); int sd3068_write_disable(void); int sd3068_set_time(sd_time_t time); diff --git a/lib/firmware/sd3068.c b/lib/firmware/sd3068.c index 868ce998..4af24e3d 100644 --- a/lib/firmware/sd3068.c +++ b/lib/firmware/sd3068.c @@ -17,36 +17,47 @@ #include "fpioa.h" #include "common.h" #include "sysctl.h" -#include "i2c.h" +#include +#include -uint8_t i2c_bus_no = 0; +uint32_t i2c_bus_no = 0; -void sd3068_init(uint8_t sel) +void sd3068_init(i2c_device_num_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode) { - i2c_bus_no = sel; + i2c_bus_no = i2c_num; + i2c_config(i2c_num, slave_address, address_width, bus_speed_mode); } static int sd3068_write_reg(uint8_t reg, uint8_t *data_buf, uint8_t length) { - i2c_write_reg(i2c_bus_no, reg, data_buf, length); + uint8_t *buf = malloc(length + 1); + buf[0] = reg; + memcpy(buf + 1, data_buf, length); + i2c_send_data(i2c_bus_no, buf, length + 1); + free(buf); return 0; } static int sd3068_write_reg_dma(uint8_t reg, uint8_t *data_buf, uint8_t length) { - i2c_write_reg_dma(DMAC_CHANNEL0, i2c_bus_no, reg, data_buf, length); + + uint8_t *buf = malloc(length + 1); + buf[0] = reg; + memcpy(buf + 1, data_buf, length); + i2c_send_data_dma(DMAC_CHANNEL0, i2c_bus_no, buf, length + 1); + free(buf); return 0; } static int sd3068_read_reg(uint8_t reg, uint8_t *data_buf, uint8_t length) { - i2c_read_reg(i2c_bus_no, reg, data_buf, length); + i2c_receive_data(i2c_bus_no, ®, 1, data_buf, length); return 0; } static int sd3068_read_reg_dma(uint8_t reg, uint8_t *data_buf, uint8_t length) { - i2c_read_reg_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, i2c_bus_no, reg, data_buf, length); + i2c_receive_data_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, i2c_bus_no, ®, 1, data_buf, length); return 0; } From 0ba945f1e712a2603280722581f0720a4a54d497 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Thu, 27 Sep 2018 23:04:02 +0800 Subject: [PATCH 05/58] Modify wdt driver --- lib/drivers/include/wdt.h | 34 +++++++++++------------ lib/drivers/wdt.c | 57 +++++++++++++++++++-------------------- 2 files changed, 45 insertions(+), 46 deletions(-) diff --git a/lib/drivers/include/wdt.h b/lib/drivers/include/wdt.h index d329c8d4..bfdb0ad3 100644 --- a/lib/drivers/include/wdt.h +++ b/lib/drivers/include/wdt.h @@ -117,44 +117,44 @@ typedef struct _wdt */ extern volatile wdt_t *const wdt[2]; -/** - * @brief Feed wdt - */ -void wdt_feed(uint8_t id); - /** * @brief Enable wdt * * @param[in] id Wdt id 0 or 1 * */ -void wdt_enable(uint8_t id); +static void wdt_enable(uint8_t id); /** - * @brief Clear wdt interrupt + * @brief Response to wdt timeouted * * @param[in] id Wdt id 0 or 1 + * @param[in] mode Set wdt reseponse mode * */ -void wdt_interrupt_clear(uint8_t id); +static void wdt_response_mode(uint8_t id, uint8_t mode); /** - * @brief Clear wdt interrupt + * @brief Set wdt timeout * - * @param[in] id Wdt id 0 or 1 - * @param[in] mode Set wdt work mode + * @param[in] id Wdt id 0 or 1 + * @param[in] timeout Wdt trigger time * */ -void wdt_response_mode(uint8_t id, uint8_t mode); +static void wdt_set_timeout(uint8_t id, uint8_t timeout); /** - * @brief Set wdt timeout + * @brief Feed wdt + */ +void wdt_feed(uint8_t id); + +/** + * @brief Clear wdt interrupt * - * @param[in] id Wdt id 0 or 1 - * @param[in] timeout Wdt trigger time + * @param[in] id Wdt id 0 or 1 * */ -void wdt_timeout_set(uint8_t id, uint8_t timeout); +void wdt_clear_interrupt(uint8_t id); /** * @brief Start wdt @@ -163,7 +163,7 @@ void wdt_timeout_set(uint8_t id, uint8_t timeout); * @param[in] toms Wdt trigger time * */ -int wdt_start(uint8_t id, size_t toms); +int wdt_start(uint8_t id, uint64_t toms); /** * @brief Stop wdt diff --git a/lib/drivers/wdt.c b/lib/drivers/wdt.c index efba1aec..fd308043 100644 --- a/lib/drivers/wdt.c +++ b/lib/drivers/wdt.c @@ -27,53 +27,38 @@ volatile wdt_t *const wdt[2] = (volatile wdt_t *)WDT1_BASE_ADDR }; -void wdt_feed(uint8_t id) -{ - wdt[id]->crr = WDT_CRR_MASK; -} - -void wdt_enable(uint8_t id) +static void wdt_enable(uint8_t id) { wdt[id]->crr = WDT_CRR_MASK; wdt[id]->cr |= WDT_CR_ENABLE; } -void wdt_disable(uint8_t id) +static void wdt_disable(uint8_t id) { wdt[id]->crr = WDT_CRR_MASK; wdt[id]->cr &= (~WDT_CR_ENABLE); } -void wdt_timeout_set(uint8_t id, uint8_t timeout) +static void wdt_set_timeout(uint8_t id, uint8_t timeout) { wdt[id]->torr = WDT_TORR_TOP(timeout); } -void wdt_response_mode(uint8_t id, uint8_t mode) +static void wdt_response_mode(uint8_t id, uint8_t mode) { wdt[id]->cr &= (~WDT_CR_RMOD_MASK); wdt[id]->cr |= mode; } -void wdt_interrupt_clear(uint8_t id) -{ - wdt[id]->eoi = wdt[id]->eoi; -} - -void wdt_set_irq(uint8_t id, plic_irq_callback_t on_irq) -{ - wdt_irq[id] = on_irq; -} - -size_t wdt_get_pclk(uint8_t id) +static uint64_t wdt_get_pclk(uint8_t id) { return id ? sysctl_clock_get_freq(SYSCTL_CLOCK_WDT1) : sysctl_clock_get_freq(SYSCTL_CLOCK_WDT0); } -ssize_t log_2(size_t x) +static uint64_t log_2(uint64_t x) { - ssize_t i = 0; - for (i = sizeof(size_t) * 8; i >= 0; i--) + int64_t i = 0; + for (i = sizeof(uint64_t) * 8; i >= 0; i--) { if ((x >> i) & 0x1) { @@ -83,10 +68,10 @@ ssize_t log_2(size_t x) return i; } -uint8_t wdt_get_top(uint8_t id, size_t timeout_ms) +static uint8_t wdt_get_top(uint8_t id, uint64_t timeout_ms) { - size_t wdt_clk = wdt_get_pclk(id); - size_t ret = (timeout_ms * wdt_clk / 1000) >> 16; + uint64_t wdt_clk = wdt_get_pclk(id); + uint64_t ret = (timeout_ms * wdt_clk / 1000) >> 16; if (ret) ret = log_2(ret); if (ret > 0xf) @@ -94,11 +79,25 @@ uint8_t wdt_get_top(uint8_t id, size_t timeout_ms) return (uint8_t)ret; } +void wdt_feed(uint8_t id) +{ + wdt[id]->crr = WDT_CRR_MASK; +} + +void wdt_clear_interrupt(uint8_t id) +{ + wdt[id]->eoi = wdt[id]->eoi; +} + +void wdt_set_irq(uint8_t id, plic_irq_callback_t on_irq) +{ + wdt_irq[id] = on_irq; +} -int wdt_start(uint8_t id, size_t toms) +int wdt_start(uint8_t id, uint64_t toms) { wdt_disable(id); - wdt_interrupt_clear(id); + wdt_clear_interrupt(id); plic_irq_register(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT, wdt_irq[id], NULL); plic_set_priority(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT, 1); plic_irq_enable(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT); @@ -108,7 +107,7 @@ int wdt_start(uint8_t id, size_t toms) sysctl_clock_enable(id ? SYSCTL_CLOCK_WDT1 : SYSCTL_CLOCK_WDT0); wdt_response_mode(id, WDT_CR_RMOD_INTERRUPT); uint8_t m_top = wdt_get_top(id, toms); - wdt_timeout_set(id, m_top); + wdt_set_timeout(id, m_top); wdt_enable(id); return 0; } From 012401c0c3ee8808ac25a287974da8aff8f06342 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Thu, 27 Sep 2018 23:04:36 +0800 Subject: [PATCH 06/58] Modify nt35310 demo --- lib/firmware/nt35310.c | 41 ++++++++++++++++------------------------- 1 file changed, 16 insertions(+), 25 deletions(-) diff --git a/lib/firmware/nt35310.c b/lib/firmware/nt35310.c index 944f03a8..25ea4d45 100644 --- a/lib/firmware/nt35310.c +++ b/lib/firmware/nt35310.c @@ -64,56 +64,47 @@ void tft_hard_init(void) { init_dcx(); pin_mux_init(); - spi_master_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 8); + spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 8); } void tft_write_command(uint8_t cmd) { set_dcx_control(); - spi_set_tmod(SPI_CHANNEL, SPI_TMOD_TRANS); - spi_set_frame_format(SPI_CHANNEL, SPI_FF_OCTAL); - spi_set_frame_size(SPI_CHANNEL, 8); - spi_trans_config(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_normal_send_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT, (uint8_t *)(&cmd), 1,SPI_TRANS_CHAR); + spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 8); + spi_config_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); + spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT, (uint8_t *)(&cmd), 1,SPI_TRANS_CHAR); } void tft_write_byte(uint8_t *data_buf, uint32_t length) { set_dcx_data(); - spi_set_tmod(SPI_CHANNEL, SPI_TMOD_TRANS); - spi_set_frame_format(SPI_CHANNEL, SPI_FF_OCTAL); - spi_set_frame_size(SPI_CHANNEL, 8); - spi_trans_config(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_normal_send_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT, data_buf, length, SPI_TRANS_CHAR); + spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 8); + spi_config_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); + spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT, data_buf, length, SPI_TRANS_CHAR); } void tft_write_half(uint16_t *data_buf, uint32_t length) { set_dcx_data(); - spi_set_tmod(SPI_CHANNEL, SPI_TMOD_TRANS); - spi_set_frame_format(SPI_CHANNEL, SPI_FF_OCTAL); - spi_set_frame_size(SPI_CHANNEL, 16); - spi_trans_config(SPI_CHANNEL, 16/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_normal_send_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_SHORT); + spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 16); + spi_config_non_standard(SPI_CHANNEL, 16/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); + spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_SHORT); } void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag) { set_dcx_data(); - spi_set_tmod(SPI_CHANNEL, SPI_TMOD_TRANS); - spi_set_frame_format(SPI_CHANNEL, SPI_FF_OCTAL); - spi_set_frame_size(SPI_CHANNEL, 32); - spi_trans_config(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_normal_send_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_INT); + spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 32); + + spi_config_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); + spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_INT); } void tft_fill_data(uint32_t *data_buf, uint32_t length) { set_dcx_data(); - spi_set_tmod(SPI_CHANNEL, SPI_TMOD_TRANS); - spi_set_frame_format(SPI_CHANNEL, SPI_FF_OCTAL); - spi_set_frame_size(SPI_CHANNEL, 32); - spi_trans_config(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); + spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 32); + spi_config_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); spi_fill_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT,data_buf, length); } From 13a36417d8747c72c33902fec6dea0db5c87b4ec Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Thu, 27 Sep 2018 23:05:27 +0800 Subject: [PATCH 07/58] Modify spi driver --- lib/drivers/include/spi.h | 124 +++-------------- lib/drivers/spi.c | 280 +++++++++----------------------------- lib/firmware/w25qxx.c | 86 +++++------- 3 files changed, 117 insertions(+), 373 deletions(-) diff --git a/lib/drivers/include/spi.h b/lib/drivers/include/spi.h index a9e38348..6d893708 100644 --- a/lib/drivers/include/spi.h +++ b/lib/drivers/include/spi.h @@ -100,6 +100,14 @@ typedef struct _spi } __attribute__((packed, aligned(4))) spi_t; /* clang-format on */ +typedef enum _spi_device_num +{ + SPI_DEVICE_0, + SPI_DEVICE_1, + SPI_DEVICE_2, + SPI_DEVICE_3, + SPI_DEVICE_MAX, +} spi_device_num_t; typedef enum _spi_mode { @@ -140,21 +148,8 @@ typedef enum _spi_transfer_width SPI_TRANS_INT = 0x2, } spi_transfer_width_t; - extern volatile spi_t *const spi[4]; - -/** - * @brief Spi initialize - * - * @param[in] spi_bus Spi bus number - * - * @return Result - * - 0 Success - * - Other Fail - */ -int spi_init(uint8_t spi_bus); - /** * @brief Spi master mode configuration * @@ -167,7 +162,7 @@ int spi_init(uint8_t spi_bus); * - 0 Success * - Other Fail */ -int spi_master_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame_format, +int spi_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame_format, size_t data_bit_length); /** @@ -180,7 +175,7 @@ int spi_master_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame * @param[in] trans_mode Spi transfer mode * */ -void spi_trans_config(uint8_t spi_bus, size_t instruction_length, size_t address_length, +void spi_config_non_standard(uint8_t spi_bus, size_t instruction_length, size_t address_length, size_t wait_cycles, spi_addr_inst_trans_mode_t trans_mode); /** @@ -197,7 +192,7 @@ void spi_trans_config(uint8_t spi_bus, size_t instruction_length, size_t address * - 0 Success * - Other Fail */ -int spi_send_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); +int spi_send_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** @@ -214,7 +209,7 @@ int spi_send_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t * - 0 Success * - Other Fail */ -int spi_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +int spi_receive_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** @@ -231,7 +226,7 @@ int spi_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size * - 0 Success * - Other Fail */ -int spi_quad_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +int spi_receive_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special send data @@ -247,88 +242,7 @@ int spi_quad_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff * - 0 Success * - Other Fail */ -int spi_quad_send_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); - -/** - * @brief Spi set transfer mode - * - * @param[in] spi_bus Spi bus number - * @param[in] tmod Spi tmod - * - */ -void spi_set_tmod(uint8_t spi_bus, uint32_t tmod); - -/** - * @brief Spi set frame format - * - * @param[in] spi_bus Spi bus number - * @param[in] spi_frf Spi frame format - * - */ -void spi_set_frame_format(uint8_t spi_bus, uint32_t spi_frf); - -/** - * @brief Spi get frame format - * - * @param[in] spi_bus Spi bus number - * - * @return frame foramt - */ -int spi_get_frame_format(uint8_t spi_bus); - -/** - * @brief Spi set work mode - * - * @param[in] spi_bus Spi bus number - * @param[in] mode Spi work mode - * - */ -void spi_set_work_mode(uint8_t spi_bus, spi_mode_t mode); - -/** - * @brief Spi set frame size - * - * @param[in] spi_bus Spi bus number - * @param[in] dfs Spi frame size - * - */ -void spi_set_frame_size(uint8_t spi_bus, uint32_t dfs); - -/** - * @brief Spi set wait cycles - * - * @param[in] spi_bus Spi bus number - * @param[in] wcycles Spi wait cycles - * - */ -void spi_set_wait_cycles(uint8_t spi_bus, uint32_t wcycles); - -/** - * @brief Spi set instruction length - * - * @param[in] spi_bus Spi bus number - * @param[in] instruction_length Spi instruction length - * - */ -void spi_set_inst_length(uint8_t spi_bus, uint32_t instruction_length); - -/** - * @brief Spi set address length - * - * @param[in] spi_bus Spi bus number - * @param[in] address_length Spi address length - * - */ -void spi_set_address_length(uint8_t spi_bus, uint32_t address_length); - -/** - * @brief Spi set transfer mode - * - * @param[in] spi_bus Spi bus number - * @param[in] trans_mode Spi tansfer mode - * - */ -void spi_set_trans_mode(uint8_t spi_bus, spi_addr_inst_trans_mode_t trans_mode); +int spi_send_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** * @brief Spi send data by dma @@ -345,7 +259,7 @@ void spi_set_trans_mode(uint8_t spi_bus, spi_addr_inst_trans_mode_t trans_mode); * - 0 Success * - Other Fail */ -int spi_send_data_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, +int spi_send_data_standard_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); @@ -365,7 +279,7 @@ int spi_send_data_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32 * - 0 Success * - Other Fail */ -int spi_receive_data_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, +int spi_receive_data_standard_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); @@ -384,7 +298,7 @@ int spi_receive_data_dma(dmac_channel_number_t channel_num_w, dmac_channel_numbe * - 0 Success * - Other Fail */ -int spi_quad_send_data_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, +int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** @@ -403,7 +317,7 @@ int spi_quad_send_data_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, ui * - 0 Success * - Other Fail */ -int spi_quad_receive_data_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, +int spi_receive_data_multiple_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** @@ -435,7 +349,7 @@ int spi_fill_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chi * - 0 Success * - Other Fail */ -int spi_normal_send_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, +int spi_send_data_normal_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, void *tx_buff, size_t tx_len, spi_transfer_width_t stw); /** diff --git a/lib/drivers/spi.c b/lib/drivers/spi.c index 4b4304d0..9ce42ba4 100644 --- a/lib/drivers/spi.c +++ b/lib/drivers/spi.c @@ -30,7 +30,7 @@ volatile spi_t *const spi[4] = (volatile spi_t *)SPI3_BASE_ADDR }; -int spi_clk_init(uint8_t spi_bus) +static int spi_clk_init(uint8_t spi_bus) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); sysctl_clock_enable(SYSCTL_CLOCK_SPI0 + spi_bus); @@ -38,17 +38,32 @@ int spi_clk_init(uint8_t spi_bus) return 0; } -int spi_init(uint8_t spi_bus) +static void spi_set_tmod(uint8_t spi_bus, uint32_t tmod) { - spi_clk_init(spi_bus); - dmac_init(); - return 0; + configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); + volatile spi_t *spi_handle = spi[spi_bus]; + uint8_t tmod_offset = 0; + switch(spi_bus){ + case 0: + case 1: + tmod_offset = 8; + break; + case 2: + configASSERT(!"Spi Bus 2 Not Support!"); + break; + case 3: + default: + tmod_offset = 10; + break; + } + set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset); } -int spi_master_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame_format, size_t data_bit_length) +int spi_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame_format, size_t data_bit_length) { configASSERT(data_bit_length >= 4 && data_bit_length <= 32); configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); + spi_clk_init(spi_bus); uint8_t dfs_offset, frf_offset; switch(spi_bus){ @@ -95,23 +110,7 @@ int spi_master_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame return 0; } -uint32_t spi_set_clk_rate(uint8_t spi_bus, uint32_t spi_clk) -{ - uint32_t spi_baudr = sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_bus) / spi_clk; - if(spi_baudr < 2 ) - { - spi_baudr = 2; - } - else if(spi_baudr > 65534) - { - spi_baudr = 65534; - } - volatile spi_t *spi_adapter = spi[spi_bus]; - spi_adapter->baudr = spi_baudr; - return sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_bus) / spi_baudr; -} - -void spi_trans_config(uint8_t spi_bus, size_t instruction_length, size_t address_length, +void spi_config_non_standard(uint8_t spi_bus, size_t instruction_length, size_t address_length, size_t wait_cycles, spi_addr_inst_trans_mode_t trans_mode) { configASSERT(wait_cycles < (1 << 5)); @@ -144,11 +143,27 @@ void spi_trans_config(uint8_t spi_bus, size_t instruction_length, size_t address spi_handle->spi_ctrlr0 = (wait_cycles << 11) | (inst_l << 8) | (addr_l << 2) | trans_mode; } -int spi_send_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) +uint32_t spi_set_clk_rate(uint8_t spi_bus, uint32_t spi_clk) +{ + uint32_t spi_baudr = sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_bus) / spi_clk; + if(spi_baudr < 2 ) + { + spi_baudr = 2; + } + else if(spi_baudr > 65534) + { + spi_baudr = 65534; + } + volatile spi_t *spi_adapter = spi[spi_bus]; + spi_adapter->baudr = spi_baudr; + return sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_bus) / spi_baudr; +} + +int spi_send_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { uint32_t index, fifo_len; configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - + spi_set_tmod(spi_bus, SPI_TMOD_TRANS); volatile spi_t *spi_handle = spi[spi_bus]; spi_handle->ssienr = 0x01; while (cmd_len){ @@ -175,12 +190,12 @@ int spi_send_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t return 0; } -int spi_send_data_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, +int spi_send_data_standard_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); + spi_set_tmod(spi_bus, SPI_TMOD_TRANS); volatile spi_t *spi_handle = spi[spi_bus]; - uint32_t *buf = malloc((cmd_len + tx_len) * sizeof(uint32_t)); int i; for(i = 0; i < cmd_len; i++){ @@ -207,16 +222,18 @@ int spi_send_data_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32 return 0; } -int spi_normal_send_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, +int spi_send_data_normal_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, void *tx_buff, size_t tx_len, spi_transfer_width_t stw) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); + spi_set_tmod(spi_bus, SPI_TMOD_TRANS); volatile spi_t *spi_handle = spi[spi_bus]; - uint32_t *buf = malloc((tx_len) * sizeof(uint32_t)); int i; - for(i = 0; i < tx_len; i++){ - switch(stw){ + for(i = 0; i < tx_len; i++) + { + switch(stw) + { case SPI_TRANS_SHORT: buf[i] = ((uint16_t *)tx_buff)[i]; break; @@ -247,18 +264,19 @@ int spi_normal_send_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint return 0; } -int spi_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +int spi_receive_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { uint32_t index, fifo_len; configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); + spi_set_tmod(spi_bus, SPI_TMOD_EEROM); volatile spi_t *spi_handle = spi[spi_bus]; - spi_handle->ctrlr1 = rx_len - 1; spi_handle->ssienr = 0x01; while (cmd_len--) spi_handle->dr[0] = *cmd_buff++; spi_handle->ser = chip_sel; - while (rx_len) { + while (rx_len) + { fifo_len = spi_handle->rxflr; fifo_len = fifo_len < rx_len ? fifo_len : rx_len; for (index = 0; index < fifo_len; index++) @@ -270,12 +288,12 @@ int spi_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size return 0; } -int spi_receive_data_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, +int spi_receive_data_standard_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); + spi_set_tmod(spi_bus, SPI_TMOD_EEROM); volatile spi_t *spi_handle = spi[spi_bus]; - uint32_t * write_cmd = malloc(sizeof(uint32_t) * (cmd_len + rx_len)); size_t i; for (i = 0; i < cmd_len; i++) @@ -308,12 +326,12 @@ int spi_receive_data_dma(dmac_channel_number_t channel_num_w, dmac_channel_numbe return 0; } -int spi_quad_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +int spi_receive_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { uint32_t index, fifo_len; configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); + spi_set_tmod(spi_bus, SPI_TMOD_RECV); volatile spi_t *spi_handle = spi[spi_bus]; - spi_handle->ctrlr1 = rx_len - 1; spi_handle->ssienr = 0x01; while (cmd_len--) @@ -331,12 +349,12 @@ int spi_quad_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff return 0; } -int spi_quad_receive_data_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, +int spi_receive_data_multiple_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); + spi_set_tmod(spi_bus, SPI_TMOD_RECV); volatile spi_t *spi_handle = spi[spi_bus]; - uint32_t * write_cmd = malloc(sizeof(uint32_t) * (cmd_len + rx_len)); size_t i; for (i = 0; i < cmd_len; i++) @@ -368,13 +386,12 @@ int spi_quad_receive_data_dma(dmac_channel_number_t channel_num_w, dmac_channel_ return 0; } -int spi_quad_send_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) +int spi_send_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { uint32_t index, fifo_len; configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - + spi_set_tmod(spi_bus, SPI_TMOD_TRANS); volatile spi_t *spi_handle = spi[spi_bus]; - spi_handle->ssienr = 0x01; while (cmd_len--) spi_handle->dr[0] = *cmd_buff++; @@ -398,12 +415,12 @@ int spi_quad_send_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, s return 0; } -int spi_quad_send_data_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, +int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); + spi_set_tmod(spi_bus, SPI_TMOD_TRANS); volatile spi_t *spi_handle = spi[spi_bus]; - uint32_t *buf = malloc((cmd_len + tx_len) * sizeof(uint32_t)); int i; for(i = 0; i < cmd_len; i++){ @@ -433,8 +450,8 @@ int spi_quad_send_data_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, ui int spi_fill_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len) { configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); + spi_set_tmod(spi_bus, SPI_TMOD_TRANS); volatile spi_t *spi_handle = spi[spi_bus]; - spi_handle->dmacr = 0x2; /*enable dma transmit*/ spi_handle->ssienr = 0x01; @@ -451,174 +468,3 @@ int spi_fill_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chi return 0; } -void spi_set_tmod(uint8_t spi_bus, uint32_t tmod) -{ - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - volatile spi_t *spi_handle = spi[spi_bus]; - uint8_t tmod_offset = 0; - switch(spi_bus){ - case 0: - case 1: - tmod_offset = 8; - break; - case 2: - configASSERT(!"Spi Bus 2 Not Support!"); - break; - case 3: - default: - tmod_offset = 10; - break; - } - - set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset); -} - -void spi_set_frame_format(uint8_t spi_bus, uint32_t spi_frf) -{ - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - volatile spi_t *spi_handle = spi[spi_bus]; - uint8_t frf_offset = 0; - switch(spi_bus){ - case 0: - case 1: - frf_offset = 21; - break; - case 2: - configASSERT(!"Spi Bus 2 Not Support!"); - break; - case 3: - default: - frf_offset = 22; - break; - } - - set_bit(&spi_handle->ctrlr0, 3 << frf_offset, spi_frf << frf_offset); -} - -int spi_get_frame_format(uint8_t spi_bus) -{ - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - volatile spi_t *spi_handle = spi[spi_bus]; - uint8_t frf_offset = 0; - switch(spi_bus){ - case 0: - case 1: - frf_offset = 21; - break; - case 2: - configASSERT(!"Spi Bus 2 Not Support!"); - break; - case 3: - default: - frf_offset = 22; - break; - } - return ((spi_handle->ctrlr0 >> frf_offset) & 0x03); -} - - -void spi_set_work_mode(uint8_t spi_bus, spi_mode_t mode) -{ - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - volatile spi_t *spi_handle = spi[spi_bus]; - set_bit(&spi_handle->ctrlr0, 0x3 << 6, mode << 6); -} - -void spi_set_frame_size(uint8_t spi_bus, uint32_t dfs) -{ - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - volatile spi_t *spi_handle = spi[spi_bus]; - - uint8_t dfs_offset; - switch(spi_bus){ - case 0: - case 1: - dfs_offset = 16; - break; - case 2: - configASSERT(!"Spi Bus 2 Not Support!"); - break; - case 3: - default: - dfs_offset = 0; - break; - } - int frame_format = spi_get_frame_format(spi_bus); - switch (frame_format) - { - case SPI_FF_DUAL: - configASSERT(dfs % 2 == 0); - break; - case SPI_FF_QUAD: - configASSERT(dfs % 4 == 0); - break; - case SPI_FF_OCTAL: - configASSERT(dfs % 8 == 0); - break; - default: - break; - } - set_bit(&spi_handle->ctrlr0, 0x1F << dfs_offset, (dfs-1) << dfs_offset); -} - -void spi_set_wait_cycles(uint8_t spi_bus, uint32_t wcycles) -{ - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - configASSERT(wcycles < (1 << 5)); - int frame_format = spi_get_frame_format(spi_bus); - configASSERT(frame_format != SPI_FF_STANDARD); - volatile spi_t *spi_handle = spi[spi_bus]; - - set_bit(&spi_handle->spi_ctrlr0, 0x1F << 11, wcycles << 11); -} - -void spi_set_inst_length(uint8_t spi_bus, uint32_t instruction_length) -{ - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - int frame_format = spi_get_frame_format(spi_bus); - configASSERT(frame_format != SPI_FF_STANDARD); - volatile spi_t *spi_handle = spi[spi_bus]; - - uint32_t inst_l = 0; - switch (instruction_length) - { - case 0: - inst_l = 0; - break; - case 4: - inst_l = 1; - break; - case 8: - inst_l = 2; - break; - case 16: - inst_l = 3; - break; - default: - configASSERT("Invalid instruction length"); - break; - } - - set_bit(&spi_handle->spi_ctrlr0, 0x3 << 8, inst_l << 8); -} - -void spi_set_address_length(uint8_t spi_bus, uint32_t address_length) -{ - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - int frame_format = spi_get_frame_format(spi_bus); - configASSERT(frame_format != SPI_FF_STANDARD); - configASSERT(address_length % 4 == 0 && address_length <= 60); - volatile spi_t *spi_handle = spi[spi_bus]; - uint32_t addr_l = address_length / 4; - set_bit(&spi_handle->spi_ctrlr0, 0xF << 2, addr_l << 2); -} - -void spi_set_trans_mode(uint8_t spi_bus, spi_addr_inst_trans_mode_t trans_mode) -{ - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - int frame_format = spi_get_frame_format(spi_bus); - configASSERT(frame_format != SPI_FF_STANDARD); - volatile spi_t *spi_handle = spi[spi_bus]; - set_bit(&spi_handle->spi_ctrlr0, 0x3 << 0, trans_mode << 0); -} - diff --git a/lib/firmware/w25qxx.c b/lib/firmware/w25qxx.c index 655e799f..a38eeb83 100644 --- a/lib/firmware/w25qxx.c +++ b/lib/firmware/w25qxx.c @@ -18,8 +18,8 @@ #include "sysctl.h" #include "dmac.h" -uint8_t spi_bus_no = 0; -uint8_t spi_chip_select = 0; +uint32_t spi_bus_no = 0; +uint32_t spi_chip_select = 0; static volatile spi_t *spi_handle; w25qxx_status_t (*w25qxx_page_program_fun)(uint32_t addr, uint8_t *data_buf, uint32_t length); @@ -33,53 +33,51 @@ static w25qxx_status_t w25qxx_quad_page_program_dma(uint32_t addr, uint8_t *data static w25qxx_status_t w25qxx_receive_data(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) { - spi_set_tmod(spi_bus_no, SPI_TMOD_EEROM); - spi_receive_data(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_receive_data_standard(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); return W25QXX_OK; } static w25qxx_status_t w25qxx_receive_data_dma(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) { - spi_set_tmod(spi_bus_no, SPI_TMOD_EEROM); - spi_receive_data_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_receive_data_standard_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); return W25QXX_OK; } static w25qxx_status_t w25qxx_send_data(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) { - spi_set_tmod(spi_bus_no, SPI_TMOD_TRANS); - spi_send_data(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); + spi_send_data_standard(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); return W25QXX_OK; } static w25qxx_status_t w25qxx_send_data_dma(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) { - spi_set_tmod(spi_bus_no, SPI_TMOD_TRANS); - spi_send_data_dma(DMAC_CHANNEL0, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); + spi_send_data_standard_dma(DMAC_CHANNEL0, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); return W25QXX_OK; } static w25qxx_status_t w25qxx_receive_data_enhanced(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) { - spi_quad_receive_data(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); + spi_receive_data_multiple(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); return W25QXX_OK; } static w25qxx_status_t w25qxx_receive_data_enhanced_dma(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) { - spi_quad_receive_data_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); + spi_receive_data_multiple_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); return W25QXX_OK; } static w25qxx_status_t w25qxx_send_data_enhanced(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) { - spi_quad_send_data(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); + spi_send_data_multiple(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); return W25QXX_OK; } static w25qxx_status_t w25qxx_send_data_enhanced_dma(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) { - spi_quad_send_data_dma(DMAC_CHANNEL0, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); + spi_send_data_multiple_dma(DMAC_CHANNEL0, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); return W25QXX_OK; } @@ -87,7 +85,7 @@ w25qxx_status_t w25qxx_init(uint8_t spi_index, uint8_t spi_ss) { spi_bus_no = spi_index; spi_chip_select = spi_ss; - spi_master_config(spi_bus_no, SPI_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_STANDARD, DATALENGTH); w25qxx_page_program_fun = w25qxx_page_program; w25qxx_read_fun = w25qxx_stand_read_data; return W25QXX_OK; @@ -97,7 +95,7 @@ w25qxx_status_t w25qxx_init_dma(uint8_t spi_index, uint8_t spi_ss) { spi_bus_no = spi_index; spi_chip_select = spi_ss; - spi_master_config(spi_bus_no, SPI_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_STANDARD, DATALENGTH); w25qxx_page_program_fun = w25qxx_page_program_dma; w25qxx_read_fun = w25qxx_stand_read_data; return W25QXX_OK; @@ -356,11 +354,9 @@ static w25qxx_status_t w25qxx_quad_page_program(uint32_t addr, uint8_t *data_buf cmd[0] = QUAD_PAGE_PROGRAM; cmd[1] = addr; w25qxx_write_enable(); - spi_set_tmod(spi_bus_no, SPI_TMOD_TRANS); - spi_set_frame_format(spi_bus_no, SPI_FF_QUAD); - spi_trans_config(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_send_data_enhanced(cmd, 2, data_buf, length); - spi_set_frame_format(spi_bus_no, SPI_FF_STANDARD); while (w25qxx_is_busy() == W25QXX_BUSY) ; return W25QXX_OK; @@ -373,11 +369,9 @@ static w25qxx_status_t w25qxx_quad_page_program_dma(uint32_t addr, uint8_t *data cmd[0] = QUAD_PAGE_PROGRAM; cmd[1] = addr; w25qxx_write_enable_dma(); - spi_set_tmod(spi_bus_no, SPI_TMOD_TRANS); - spi_set_frame_format(spi_bus_no, SPI_FF_QUAD); - spi_trans_config(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_send_data_enhanced_dma(cmd, 2, data_buf, length); - spi_set_frame_format(spi_bus_no, SPI_FF_STANDARD); while (w25qxx_is_busy_dma() == W25QXX_BUSY) ; return W25QXX_OK; @@ -500,42 +494,38 @@ static w25qxx_status_t _w25qxx_read_data(uint32_t addr, uint8_t *data_buf, uint3 *(((uint8_t *)cmd) + 2) = (uint8_t)(addr >> 8); *(((uint8_t *)cmd) + 3) = (uint8_t)(addr >> 0); *(((uint8_t *)cmd) + 4) = 0xFF; + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_STANDARD, DATALENGTH); w25qxx_receive_data((uint8_t *)cmd, 5, data_buf, length); break; case W25QXX_DUAL: cmd[0] = FAST_READ_DUAL_OUTPUT; cmd[1] = addr; - spi_set_tmod(spi_bus_no, SPI_TMOD_RECV); - spi_set_frame_format(spi_bus_no, SPI_FF_DUAL); - spi_trans_config(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_DUAL, DATALENGTH); + spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); break; case W25QXX_DUAL_FAST: cmd[0] = FAST_READ_DUAL_IO; cmd[1] = addr << 8; - spi_set_tmod(spi_bus_no, SPI_TMOD_RECV); - spi_set_frame_format(spi_bus_no, SPI_FF_DUAL); - spi_trans_config(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_DUAL, DATALENGTH); + spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); break; case W25QXX_QUAD: cmd[0] = FAST_READ_QUAL_OUTPUT; cmd[1] = addr; - spi_set_tmod(spi_bus_no, SPI_TMOD_RECV); - spi_set_frame_format(spi_bus_no, SPI_FF_QUAD); - spi_trans_config(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); break; case W25QXX_QUAD_FAST: cmd[0] = FAST_READ_QUAL_IO; cmd[1] = addr << 8; - spi_set_tmod(spi_bus_no, SPI_TMOD_RECV); - spi_set_frame_format(spi_bus_no, SPI_FF_QUAD); - spi_trans_config(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); break; } - spi_set_frame_format(spi_bus_no, SPI_AITM_STANDARD); return W25QXX_OK; } @@ -562,38 +552,32 @@ static w25qxx_status_t w25qxx_read_data_dma_less_1000bytes(uint32_t addr, uint8_ case W25QXX_DUAL: cmd[0] = FAST_READ_DUAL_OUTPUT; cmd[1] = addr; - spi_set_tmod(spi_bus_no, SPI_TMOD_RECV); - spi_set_frame_format(spi_bus_no, SPI_FF_DUAL); - spi_trans_config(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_DUAL, DATALENGTH); + spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); break; case W25QXX_DUAL_FAST: cmd[0] = FAST_READ_DUAL_IO; cmd[1] = addr << 8; - spi_set_tmod(spi_bus_no, SPI_TMOD_RECV); - spi_set_frame_format(spi_bus_no, SPI_FF_DUAL); - spi_trans_config(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_DUAL, DATALENGTH); + spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); break; case W25QXX_QUAD: cmd[0] = FAST_READ_QUAL_OUTPUT; cmd[1] = addr; - spi_set_tmod(spi_bus_no, SPI_TMOD_RECV); - spi_set_frame_format(spi_bus_no, SPI_FF_QUAD); - spi_trans_config(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); - break; case W25QXX_QUAD_FAST: cmd[0] = FAST_READ_QUAL_IO; cmd[1] = addr << 8; - spi_set_tmod(spi_bus_no, SPI_TMOD_RECV); - spi_set_frame_format(spi_bus_no, SPI_FF_QUAD); - spi_trans_config(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); + spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); break; } - spi_set_frame_format(spi_bus_no, SPI_FF_STANDARD); return W25QXX_OK; } From deaf7de51c62bef65f839ee7d4ca9764fbbc8541 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Thu, 27 Sep 2018 23:05:59 +0800 Subject: [PATCH 08/58] Fix init_bss bug --- lds/kendryte.ld | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lds/kendryte.ld b/lds/kendryte.ld index e54adee5..4450861c 100644 --- a/lds/kendryte.ld +++ b/lds/kendryte.ld @@ -138,6 +138,7 @@ SECTIONS *(.data .data.* .gnu.linkonce.d.*) SORT(CONSTRUCTORS) } > ram : DATA + /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ @@ -148,7 +149,7 @@ SECTIONS *(.sdata .sdata.* .gnu.linkonce.s.*) } > ram : DATA _edata = .; PROVIDE (edata = .); - + /*. = ALIGN(64);*/ __bss_start = .; .sbss : { From b213b8a1e3fed64437fa2b8d2d986f125948ff21 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Fri, 28 Sep 2018 10:03:49 +0800 Subject: [PATCH 09/58] Fix out of memory bug --- lds/kendryte.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lds/kendryte.ld b/lds/kendryte.ld index 4450861c..62c73d5a 100644 --- a/lds/kendryte.ld +++ b/lds/kendryte.ld @@ -148,8 +148,8 @@ SECTIONS *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) *(.sdata .sdata.* .gnu.linkonce.s.*) } > ram : DATA + . = ALIGN(64); _edata = .; PROVIDE (edata = .); - /*. = ALIGN(64);*/ __bss_start = .; .sbss : { From a92c618aac5c957790fd7b3c4faec8795074a110 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Fri, 28 Sep 2018 15:48:49 +0800 Subject: [PATCH 10/58] Fix out of mem bug --- lds/kendryte.ld | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lds/kendryte.ld b/lds/kendryte.ld index 62c73d5a..740b8b21 100644 --- a/lds/kendryte.ld +++ b/lds/kendryte.ld @@ -138,7 +138,7 @@ SECTIONS *(.data .data.* .gnu.linkonce.d.*) SORT(CONSTRUCTORS) } > ram : DATA - + . = ALIGN(32); /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ @@ -148,7 +148,7 @@ SECTIONS *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) *(.sdata .sdata.* .gnu.linkonce.s.*) } > ram : DATA - . = ALIGN(64); + . = ALIGN(32); _edata = .; PROVIDE (edata = .); __bss_start = .; .sbss : @@ -157,6 +157,7 @@ SECTIONS *(.sbss .sbss.* .gnu.linkonce.sb.*) *(.scommon) } > ram : DYN_DATA + . = ALIGN(32); .bss : { *(.dynbss) From 2772ff0cb10c8efe699d909d69c24b853f748b32 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Fri, 28 Sep 2018 15:50:40 +0800 Subject: [PATCH 11/58] Modify func --- lib/bsp/entry_user.c | 9 +- lib/bsp/printf.c | 2 +- lib/bsp/syscalls.c | 6 +- lib/drivers/aes.c | 2 +- lib/drivers/audio_bf.c | 441 ---------------- lib/drivers/common.c | 2 +- lib/drivers/dmac.c | 16 +- lib/drivers/dvp.c | 46 +- lib/drivers/fpioa.c | 2 +- lib/drivers/gpio.c | 17 +- lib/drivers/gpiohs.c | 18 +- lib/drivers/i2c.c | 16 +- lib/drivers/i2s.c | 52 +- lib/drivers/include/audio_bf.h | 329 ------------ lib/drivers/include/dmac.h | 248 --------- lib/drivers/include/dvp.h | 24 +- lib/drivers/include/gpio.h | 14 +- lib/drivers/include/gpiohs.h | 18 +- lib/drivers/include/i2c.h | 14 +- lib/drivers/include/i2s.h | 54 +- lib/drivers/include/otp.h | 361 ------------- lib/drivers/include/pwm.h | 57 ++ lib/drivers/include/rtc.h | 30 +- lib/drivers/include/spi.h | 65 ++- lib/drivers/include/sysclock.h | 43 -- lib/drivers/include/sysctl.h | 75 +-- lib/drivers/include/timer.h | 203 +------- lib/drivers/include/uarths.h | 8 +- lib/drivers/include/{common.h => utils.h} | 4 +- lib/drivers/include/wdt.h | 50 +- lib/drivers/otp.c | 602 ---------------------- lib/drivers/pwm.c | 50 ++ lib/drivers/rtc.c | 24 +- lib/drivers/sha256.c | 2 +- lib/drivers/spi.c | 283 +++++----- lib/drivers/sysclock.c | 51 -- lib/drivers/sysctl.c | 98 +++- lib/drivers/timer.c | 71 +-- lib/drivers/uart.c | 4 +- lib/drivers/uarths.c | 14 +- lib/drivers/utils.c | 55 ++ lib/drivers/wdt.c | 39 +- lib/firmware/include/sd3068.h | 2 +- lib/firmware/lcd.c | 2 +- lib/firmware/nt35310.c | 20 +- lib/firmware/ov2640.c | 8 +- lib/firmware/ov5640.c | 4 +- lib/firmware/sd3068.c | 4 +- 48 files changed, 732 insertions(+), 2827 deletions(-) delete mode 100644 lib/drivers/audio_bf.c delete mode 100644 lib/drivers/include/audio_bf.h delete mode 100644 lib/drivers/include/otp.h create mode 100644 lib/drivers/include/pwm.h delete mode 100644 lib/drivers/include/sysclock.h rename lib/drivers/include/{common.h => utils.h} (99%) delete mode 100644 lib/drivers/otp.c create mode 100644 lib/drivers/pwm.c create mode 100644 lib/drivers/utils.c diff --git a/lib/bsp/entry_user.c b/lib/bsp/entry_user.c index a1c4bd95..d2b5a07c 100644 --- a/lib/bsp/entry_user.c +++ b/lib/bsp/entry_user.c @@ -21,11 +21,14 @@ #include "fpioa.h" #include "platform.h" #include "plic.h" -#include "sysclock.h" #include "sysctl.h" #include "syslog.h" #include "uarths.h" +#define PLL0_OUTPUT_FREQ 320000000UL +#define PLL1_OUTPUT_FREQ 160000000UL +#define PLL2_OUTPUT_FREQ 45158400UL + volatile char * const ram = (volatile char*)RAM_BASE_ADDR; extern char _heap_start[]; @@ -65,9 +68,9 @@ void _init_bsp(int core_id, int number_of_cores) /* Init FPIOA */ fpioa_init(); /* PLL init */ - sys_clock_init(); + sysctl_set_pll_frequency(PLL0_OUTPUT_FREQ, PLL1_OUTPUT_FREQ, PLL2_OUTPUT_FREQ); /* Init UART */ - uart_init(); + uarths_init(); /* Dmac init */ dmac_init(); /* Plic init */ diff --git a/lib/bsp/printf.c b/lib/bsp/printf.c index 226a38b1..5995e93f 100644 --- a/lib/bsp/printf.c +++ b/lib/bsp/printf.c @@ -648,7 +648,7 @@ int tfp_sprintf(char *str, const char *format, ...) static void uart_putf(void *unused, char c) { UNUSED(unused); - uart_putchar(c); + uarths_putchar(c); } int printk(const char *format, ...) diff --git a/lib/bsp/syscalls.c b/lib/bsp/syscalls.c index c0b3687c..f981bcb8 100644 --- a/lib/bsp/syscalls.c +++ b/lib/bsp/syscalls.c @@ -112,7 +112,7 @@ void __attribute__((noreturn)) sys_exit(int code) *reg = (1UL << 31); /* Send 0 to uart */ - uart_putchar(0); + uarths_putchar(0); while (1) continue; @@ -126,7 +126,7 @@ static int sys_nosys(long a0, long a1, long a2, long a3, long a4, long a5, unsig LOGE(TAG, "Unsupported syscall %ld: a0=%lx, a1=%lx, a2=%lx!\n", n, a0, a1, a2); /* Send 0 to uart */ - uart_putchar(0); + uarths_putchar(0); while (1) continue; return -ENOSYS; @@ -213,7 +213,7 @@ static ssize_t sys_write(int file, const void *ptr, size_t len) { /* Write data */ while (length-- > 0 && *data != 0) - uart_putchar(*(data++)); + uarths_putchar(*(data++)); /* Return the actual size written */ res = len; diff --git a/lib/drivers/aes.c b/lib/drivers/aes.c index ad317846..ab3f2060 100644 --- a/lib/drivers/aes.c +++ b/lib/drivers/aes.c @@ -22,7 +22,7 @@ volatile aes_t* const aes = (volatile aes_t*)AES_BASE_ADDR; void aes_clkinit() { - sysctl_clock_enable(SYSCTL_CLOCK_AES); + sysctl_clock_tnable(SYSCTL_CLOCK_AES); sysctl_reset(SYSCTL_RESET_AES); } diff --git a/lib/drivers/audio_bf.c b/lib/drivers/audio_bf.c deleted file mode 100644 index 3f0a5e54..00000000 --- a/lib/drivers/audio_bf.c +++ /dev/null @@ -1,441 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include -#include "encoding.h" -#include "audio_bf.h" -#include "syscalls.h" -#include "sysctl.h" - -#define BEAFORMING_BASE_ADDR (0x50250200U) - -volatile audio_bf_reg_t* const audio_bf = (volatile audio_bf_reg_t*)BEAFORMING_BASE_ADDR; - -/** - * Voice strength average value right shift factor. When performing sound direction detect, - * the average value of samples from different channels is required, this right shift factor - * is used to perform division. - * 0x0: no right shift; - * 0x1: right shift by 1-bit; - * . . . . . . - * 0xF: right shift by 14-bit. -*/ -void audio_bf_set_audio_gain(uint16_t gain) -{ - audio_bf_ch_cfg_t ch_cfg = audio_bf->bf_ch_cfg_reg; - - ch_cfg.we_bf_target_dir = 0; - ch_cfg.we_bf_sound_ch_en = 0; - ch_cfg.we_data_src_mode = 0; - ch_cfg.we_audio_gain = 1; - ch_cfg.audio_gain = gain; - audio_bf->bf_ch_cfg_reg = ch_cfg; -} - -void audio_bf_set_smpl_shift(uint8_t smpl_shift) -{ - audio_bf_dwsz_cfg_t tmp = audio_bf->bf_dwsz_cfg_reg; - - tmp.smpl_shift_bits = smpl_shift; - audio_bf->bf_dwsz_cfg_reg = tmp; -} - -uint8_t audio_bf_get_smpl_shift(void) -{ - audio_bf_dwsz_cfg_t tmp = audio_bf->bf_dwsz_cfg_reg; - - return tmp.smpl_shift_bits; -} - -/** - * BF unit sound channel enable control bits. Bit 'x' corresponds to enable bit for sound - * channel 'x' (x = 0, 1, 2, . . ., 7). BF sound channels are related with I2S host RX channels. - * BF sound channel 0/1 correspond to the left/right channel of I2S RX0; BF channel 2/3 correspond - * to left/right channels of I2S RX1; and things like that. Software write '1' to enable a sound - * channel and hardware automatically clear the bit after the sample buffers used for direction - * searching is filled full. - * 0x1: writing '1' to enable the corresponding BF sound channel. - */ -void audio_bf_set_channel_enabled(uint8_t channel_bit) -{ - audio_bf_ch_cfg_t ch_cfg; - - ch_cfg.we_audio_gain = 0; - ch_cfg.we_bf_target_dir = 0; - ch_cfg.we_bf_sound_ch_en = 1; - ch_cfg.bf_sound_ch_en = channel_bit; - audio_bf->bf_ch_cfg_reg = ch_cfg; -} - -/** - * BF unit sound channel enable control bits. Bit 'x' corresponds to enable bit for sound - * channel 'x' (x = 0, 1, 2, . . ., 7). BF sound channels are related with I2S host RX channels. - * BF sound channel 0/1 correspond to the left/right channel of I2S RX0; BF channel 2/3 correspond - * to left/right channels of I2S RX1; and things like that. Software write '1' to enable a sound - * channel and hardware automatically clear the bit after the sample buffers used for direction - * searching is filled full. - * 0x1: writing '1' to enable the corresponding BF sound channel. - */ -void audio_bf_channel_enable(uint8_t channel_bit) -{ - audio_bf_ch_cfg_t ch_cfg = audio_bf->bf_ch_cfg_reg; - - ch_cfg.we_audio_gain = 0; - ch_cfg.we_bf_target_dir = 0; - ch_cfg.we_data_src_mode = 0; - ch_cfg.we_bf_sound_ch_en = 1; - ch_cfg.bf_sound_ch_en = channel_bit; - audio_bf->bf_ch_cfg_reg = ch_cfg; -} - -/** - * audio data source configure parameter. This parameter controls where the audio data source comes from. - * 0x0: audio data directly sourcing from audio_bf internal buffer; - * 0x1: audio data sourcing from FFT result buffer. - */ -void audio_bf_set_src_mode(uint8_t src_mode) -{ - audio_bf_ch_cfg_t ch_cfg = audio_bf->bf_ch_cfg_reg; - - ch_cfg.we_audio_gain = 0; - ch_cfg.we_bf_target_dir = 0; - ch_cfg.we_bf_sound_ch_en = 0; - ch_cfg.we_data_src_mode = 1; - ch_cfg.data_src_mode = src_mode; - audio_bf->bf_ch_cfg_reg = ch_cfg; -} - -/** - * I2S host beam-forming direction sample ibuffer read index configure register - */ -void audio_bf_set_direction_delay(uint8_t dir_num, uint8_t* dir_bidx) -{ - audio_bf->bf_dir_bidx[dir_num][0] = (audio_bf_dir_bidx_t){ - .dir_rd_idx0 = dir_bidx[0], - .dir_rd_idx1 = dir_bidx[1], - .dir_rd_idx2 = dir_bidx[2], - .dir_rd_idx3 = dir_bidx[3]}; - audio_bf->bf_dir_bidx[dir_num][1] = (audio_bf_dir_bidx_t){ - .dir_rd_idx0 = dir_bidx[4], - .dir_rd_idx1 = dir_bidx[5], - .dir_rd_idx2 = dir_bidx[6], - .dir_rd_idx3 = dir_bidx[7]}; -} - -/** - * Sound direction searching enable bit. Software writes '1' to start sound direction searching function. - * When all the sound sample buffers are filled full, this bit is cleared by hardware (this sample buffers - * are used for direction detect only). - * 0x1: enable direction searching. - */ -void audio_bf_dir_enable(void) -{ - audio_bf_ctl_t bf_en_tmp = audio_bf->bf_ctl_reg; - - bf_en_tmp.we_bf_dir_search_en = 1; - bf_en_tmp.bf_dir_search_en = 1; - audio_bf->bf_ctl_reg = bf_en_tmp; -} - -void audio_bf_dir_reset(void) -{ - audio_bf_ctl_t bf_en_tmp = audio_bf->bf_ctl_reg; - - bf_en_tmp.we_search_path_rst = 1; - bf_en_tmp.search_path_reset = 1; - audio_bf->bf_ctl_reg = bf_en_tmp; -} - -/** - * Valid voice sample stream generation enable bit. After sound direction searching is done, software can - * configure this bit to generate a stream of voice samples for voice recognition. - * 0x1: enable output of voice sample stream. - * 0x0: stop the voice samlpe stream output. - */ -void audio_bf_voc_enable(uint8_t enable_flag) -{ - audio_bf_ctl_t bf_en_tmp = audio_bf->bf_ctl_reg; - - bf_en_tmp.we_bf_stream_gen = 1; - bf_en_tmp.bf_stream_gen_en = enable_flag; - audio_bf->bf_ctl_reg = bf_en_tmp; -} - -void audio_bf_voc_reset(void) -{ - audio_bf_ctl_t bf_en_tmp = audio_bf->bf_ctl_reg; - - bf_en_tmp.we_voice_gen_path_rst = 1; - bf_en_tmp.voice_gen_path_reset = 1; - audio_bf->bf_ctl_reg = bf_en_tmp; -} - -/** - * Target direction select for valid voice output. When the source voice direaction searching - * is done, software can use this field to select one from 16 sound directions for the following - * voice recognition - * 0x0: select sound direction 0; 0x1: select sound direction 1; - * . . . . . . - * 0xF: select sound direction 15. -*/ -void audio_bf_voc_set_direction(en_bf_dir_t direction) -{ - audio_bf_ch_cfg_t ch_cfg = audio_bf->bf_ch_cfg_reg; - - ch_cfg.we_bf_sound_ch_en = 0; - ch_cfg.we_audio_gain = 0; - ch_cfg.we_data_src_mode = 0; - ch_cfg.we_bf_target_dir = 1; - ch_cfg.bf_target_dir = direction; - audio_bf->bf_ch_cfg_reg = ch_cfg; - - audio_bf_ctl_t bf_en_tmp = audio_bf->bf_ctl_reg; - - bf_en_tmp.we_update_voice_dir = 1; - bf_en_tmp.update_voice_dir = 1; - audio_bf->bf_ctl_reg = bf_en_tmp; -} - -/** - * I2S host beam-forming Filter FIR16 Coefficient Register - */ -void audio_bf_dir_set_prev_fir(uint16_t* fir_coef) -{ - uint8_t i = 0; - - for (i = 0; i < 9; i++) - { - audio_bf->bf_pre_fir0_coef[i] = (audio_bf_fir_coef_t){ - .fir_tap0 = fir_coef[i * 2], - .fir_tap1 = i == 8 ? 0 : fir_coef[i * 2 + 1]}; - } -} - -void audio_bf_dir_set_post_fir(uint16_t* fir_coef) -{ - uint8_t i = 0; - - for (i = 0; i < 9; i++) - { - audio_bf->bf_post_fir0_coef[i] = (audio_bf_fir_coef_t){ - .fir_tap0 = fir_coef[i * 2], - .fir_tap1 = i == 8 ? 0 : fir_coef[i * 2 + 1]}; - } -} - -void audio_bf_voc_set_prev_fir(uint16_t* fir_coef) -{ - uint8_t i = 0; - - for (i = 0; i < 9; i++) - { - audio_bf->bf_pre_fir1_coef[i] = (audio_bf_fir_coef_t){ - .fir_tap0 = fir_coef[i * 2], - .fir_tap1 = i == 8 ? 0 : fir_coef[i * 2 + 1]}; - } -} - -void audio_bf_voc_set_post_fir(uint16_t* fir_coef) -{ - uint8_t i = 0; - - for (i = 0; i < 9; i++) - { - audio_bf->bf_post_fir1_coef[i] = (audio_bf_fir_coef_t){ - .fir_tap0 = fir_coef[i * 2], - .fir_tap1 = i == 8 ? 0 : fir_coef[i * 2 + 1]}; - } -} - -void audio_bf_set_fft_shift_factor(uint8_t enable_flag, uint16_t shift_factor) -{ - audio_bf->bf_fft_cfg_reg = (audio_bf_fft_cfg_t){ - .fft_enable = enable_flag, - .fft_shift_factor = shift_factor}; - - audio_bf_ch_cfg_t ch_cfg = audio_bf->bf_ch_cfg_reg; - - ch_cfg.we_data_src_mode = 1; - ch_cfg.data_src_mode = enable_flag; - audio_bf->bf_ch_cfg_reg = ch_cfg; -} - -void audio_bf_dir_set_down_size(uint8_t dir_dwn_size) -{ - audio_bf_dwsz_cfg_t tmp = audio_bf->bf_dwsz_cfg_reg; - - tmp.dir_dwn_siz_rate = dir_dwn_size; - audio_bf->bf_dwsz_cfg_reg = tmp; -} - -void audio_bf_dir_set_interrupt_mask(uint8_t dir_int_mask) -{ - audio_bf_int_mask_t tmp = audio_bf->bf_int_mask_reg; - - tmp.dir_data_rdy_msk = dir_int_mask; - audio_bf->bf_int_mask_reg = tmp; -} - -void audio_bf_voc_set_down_size(uint8_t voc_dwn_size) -{ - audio_bf_dwsz_cfg_t tmp = audio_bf->bf_dwsz_cfg_reg; - - tmp.voc_dwn_siz_rate = voc_dwn_size; - audio_bf->bf_dwsz_cfg_reg = tmp; -} - -void audio_bf_voc_set_interrupt_mask(uint8_t voc_int_mask) -{ - audio_bf_int_mask_t tmp = audio_bf->bf_int_mask_reg; - - tmp.voc_buf_rdy_msk = voc_int_mask; - audio_bf->bf_int_mask_reg = tmp; -} - -void audio_bf_set_down_size(uint8_t dir_dwn_size, uint8_t voc_dwn_size) -{ - audio_bf_dwsz_cfg_t tmp = audio_bf->bf_dwsz_cfg_reg; - - tmp.dir_dwn_siz_rate = dir_dwn_size; - tmp.voc_dwn_siz_rate = voc_dwn_size; - audio_bf->bf_dwsz_cfg_reg = tmp; -} - -void audio_bf_set_interrupt_mask(uint8_t dir_int_mask, uint8_t voc_int_mask) -{ - audio_bf->bf_int_mask_reg = (audio_bf_int_mask_t){ - .dir_data_rdy_msk = dir_int_mask, - .voc_buf_rdy_msk = voc_int_mask}; -} - -void audio_bf_dir_clear_int_state(void) -{ - audio_bf->bf_int_stat_reg = (audio_bf_int_stat_t){ - .dir_search_data_rdy = 1}; -} - -void audio_bf_voc_clear_int_state(void) -{ - audio_bf->bf_int_stat_reg = (audio_bf_int_stat_t){ - .voc_buf_data_rdy = 1}; -} - -void audio_bf_voc_reset_saturation_counter(void) -{ - audio_bf->saturation_counter = 1 << 31; -} - -/* heigh 16 bit is counter, low 16 bit is total.*/ -uint32_t audio_bf_voc_get_saturation_counter(void) -{ - return audio_bf->saturation_counter; -} - -void audio_bf_voc_set_saturation_limit(uint16_t upper, uint16_t bottom) -{ - audio_bf->saturation_limits = (uint32_t)bottom << 16 | upper; -} - -/* heigh 16 bit is counter, low 16 bit is total.*/ -uint32_t audio_bf_voc_get_saturation_limit(void) -{ - return audio_bf->saturation_limits; -} - -static void print_fir(const char* member_name, volatile audio_bf_fir_coef_t* pfir) -{ - int i; - printf(" for(int i = 0; i < 9; i++){\n"); - for (i = 0; i < 9; i++) - { - audio_bf_fir_coef_t fir = pfir[i]; - - printf(" audio_bf->%s[%d] = (audio_bf_fir_coef_t){\n", member_name, i); - printf(" .fir_tap0 = 0x%x,\n", fir.fir_tap0); - printf(" .fir_tap1 = 0x%x\n", fir.fir_tap1); - printf(" };\n"); - } - printf(" }\n"); -} - -void audio_bf_print_setting(void) -{ - int i; - printf("void audio_bf_setting(void) {\n"); - audio_bf_ch_cfg_t bf_ch_cfg_reg = audio_bf->bf_ch_cfg_reg; - - printf(" audio_bf->bf_ch_cfg_reg = (audio_bf_ch_cfg_t){\n"); - printf(" .we_audio_gain = 1, .we_bf_target_dir = 1, .we_bf_sound_ch_en = 1,\n"); - printf(" .audio_gain = 0x%x, .bf_target_dir = %d, .bf_sound_ch_en = %d, .data_src_mode = %d\n", - bf_ch_cfg_reg.audio_gain, bf_ch_cfg_reg.bf_target_dir, bf_ch_cfg_reg.bf_sound_ch_en, bf_ch_cfg_reg.data_src_mode); - printf(" };\n"); - - audio_bf_ctl_t bf_ctl_reg = audio_bf->bf_ctl_reg; - - printf(" audio_bf->bf_ctl_reg = (audio_bf_ctl_t){\n"); - printf(" .we_bf_stream_gen = 1, .we_bf_dir_search_en = 1,\n"); - printf(" .bf_stream_gen_en = %d, .bf_dir_search_en = %d\n", - bf_ctl_reg.bf_stream_gen_en, bf_ctl_reg.bf_dir_search_en); - printf(" };\n"); - - printf(" for(int i = 0; i < 16; i++){\n"); - for (i = 0; i < 16; i++) - { - audio_bf_dir_bidx_t bidx0 = audio_bf->bf_dir_bidx[i][0]; - audio_bf_dir_bidx_t bidx1 = audio_bf->bf_dir_bidx[i][1]; - - printf(" audio_bf->bf_dir_bidx[%d][0] = (audio_bf_dir_bidx_t){\n", i); - printf(" .dir_rd_idx0 = 0x%x,\n", bidx0.dir_rd_idx0); - printf(" .dir_rd_idx1 = 0x%x,\n", bidx0.dir_rd_idx1); - printf(" .dir_rd_idx2 = 0x%x,\n", bidx0.dir_rd_idx2); - printf(" .dir_rd_idx3 = 0x%x\n", bidx0.dir_rd_idx3); - printf(" };\n"); - printf(" audio_bf->bf_dir_bidx[%d][1] = (audio_bf_dir_bidx_t){\n", i); - printf(" .dir_rd_idx0 = 0x%x,\n", bidx1.dir_rd_idx0); - printf(" .dir_rd_idx1 = 0x%x,\n", bidx1.dir_rd_idx1); - printf(" .dir_rd_idx2 = 0x%x,\n", bidx1.dir_rd_idx2); - printf(" .dir_rd_idx3 = 0x%x\n", bidx1.dir_rd_idx3); - printf(" };\n"); - } - printf(" }\n"); - - print_fir("bf_pre_fir0_coef", audio_bf->bf_pre_fir0_coef); - print_fir("bf_post_fir0_coef", audio_bf->bf_post_fir0_coef); - print_fir("bf_pre_fir1_coef", audio_bf->bf_pre_fir1_coef); - print_fir("bf_post_fir1_coef", audio_bf->bf_post_fir1_coef); - - audio_bf_dwsz_cfg_t bf_dwsz_cfg_reg = audio_bf->bf_dwsz_cfg_reg; - - printf(" audio_bf->bf_dwsz_cfg_reg = (audio_bf_dwsz_cfg_t){\n"); - printf(" .dir_dwn_siz_rate = %d, .voc_dwn_siz_rate = %d\n", - bf_dwsz_cfg_reg.dir_dwn_siz_rate, bf_dwsz_cfg_reg.voc_dwn_siz_rate); - printf(" };\n"); - - audio_bf_fft_cfg_t bf_fft_cfg_reg = audio_bf->bf_fft_cfg_reg; - - printf(" audio_bf->bf_fft_cfg_reg = (audio_bf_fft_cfg_t){\n"); - printf(" .fft_enable = %d, .fft_shift_factor = 0x%x\n", - bf_fft_cfg_reg.fft_enable, bf_fft_cfg_reg.fft_shift_factor); - printf(" };\n"); - - audio_bf_int_mask_t bf_int_mask_reg = audio_bf->bf_int_mask_reg; - - printf(" audio_bf->bf_int_mask_reg = (audio_bf_int_mask_t){\n"); - printf(" .dir_data_rdy_msk = %d, .voc_buf_rdy_msk = %d\n", - bf_int_mask_reg.dir_data_rdy_msk, bf_int_mask_reg.voc_buf_rdy_msk); - printf(" };\n"); - - printf("}\n"); -} diff --git a/lib/drivers/common.c b/lib/drivers/common.c index 9e4e5145..c06b6005 100644 --- a/lib/drivers/common.c +++ b/lib/drivers/common.c @@ -14,7 +14,7 @@ */ #include #include "encoding.h" -#include "common.h" +#include "utils.h" void set_bit(volatile uint32_t* bits, uint32_t mask, uint32_t value) { diff --git a/lib/drivers/dmac.c b/lib/drivers/dmac.c index db220385..a6f114cc 100644 --- a/lib/drivers/dmac.c +++ b/lib/drivers/dmac.c @@ -18,7 +18,7 @@ #include "dmac.h" #include "sysctl.h" #include "fpioa.h" -#include "common.h" +#include "utils.h" #include "plic.h" #include "stdlib.h" @@ -45,7 +45,7 @@ uint64_t dmac_read_channel_id(dmac_channel_number_t channel_num) return dmac->channel[channel_num].axi_id; } -void dmac_enable(void) +static void dmac_enable(void) { dmac_cfg_u_t dmac_cfg; @@ -75,7 +75,7 @@ void src_transaction_complete_int_enable(dmac_channel_number_t channel_num) writeq(ch_intstat.data, &dmac->channel[channel_num].intstatus_en); } -void dmac_channel_enable(dmac_channel_number_t channel_num) +static void dmac_channel_enable(dmac_channel_number_t channel_num) { dmac_chen_u_t chen; @@ -113,7 +113,7 @@ void dmac_channel_enable(dmac_channel_number_t channel_num) writeq(chen.data, &dmac->chen); } -void dmac_channel_disable(dmac_channel_number_t channel_num) +static void dmac_channel_disable(dmac_channel_number_t channel_num) { dmac_chen_u_t chen; @@ -241,7 +241,7 @@ void dmac_enable_common_interrupt_signal(void) writeq(intsignal.data, &dmac->com_intsignal_en); } -void dmac_enable_channel_interrupt_status(dmac_channel_number_t channel_num) +static void dmac_enable_channel_interrupt_status(dmac_channel_number_t channel_num) { writeq(0xffffffff, &dmac->channel[channel_num].intclear); writeq(0xffffffff, &dmac->channel[channel_num].intstatus_en); @@ -258,7 +258,7 @@ void dmac_enable_channel_interrupt_signal(dmac_channel_number_t channel_num, } -void dmac_chanel_interrupt_clear(dmac_channel_number_t channel_num) +static void dmac_chanel_interrupt_clear(dmac_channel_number_t channel_num) { writeq(0xffffffff, &dmac->channel[channel_num].intclear); } @@ -333,7 +333,7 @@ int dmac_set_channel_config(dmac_channel_number_t channel_num, return 0; } -int dmac_set_channel_param(dmac_channel_number_t channel_num, +static int dmac_set_channel_param(dmac_channel_number_t channel_num, void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, dmac_burst_trans_length_t dmac_msize, dmac_transfer_width_t dmac_trans_width, @@ -547,7 +547,7 @@ void dmac_init(void) dmac_cfg_u_t dmac_cfg; dmac_reset_u_t dmac_reset; - sysctl_clock_enable(SYSCTL_CLOCK_DMA); + sysctl_clock_tnable(SYSCTL_CLOCK_DMA); dmac_reset.data = readq(&dmac->reset); dmac_reset.reset.rst = 1; diff --git a/lib/drivers/dvp.c b/lib/drivers/dvp.c index 182f8e35..e8b6ce4b 100644 --- a/lib/drivers/dvp.c +++ b/lib/drivers/dvp.c @@ -15,12 +15,12 @@ #include #include #include "dvp.h" -#include "common.h" +#include "utils.h" #include "fpioa.h" #include "sysctl.h" volatile dvp_t* const dvp = (volatile dvp_t*)DVP_BASE_ADDR; -static uint8_t reg_len = 8; +static uint8_t g_sccb_reg_len = 8; void mdelay(uint32_t ms) { @@ -52,45 +52,45 @@ static void dvp_sccb_start_transfer(void) ; } -int dvp_sccb_write(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data) +int dvp_sccb_write_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data) { uint32_t tmp; tmp = dvp->sccb_cfg & (~DVP_SCCB_BYTE_NUM_MASK); - (reg_len == 8) ? (tmp |= DVP_SCCB_BYTE_NUM_3) : (tmp |= DVP_SCCB_BYTE_NUM_4); + (g_sccb_reg_len == 8) ? (tmp |= DVP_SCCB_BYTE_NUM_3) : (tmp |= DVP_SCCB_BYTE_NUM_4); dvp->sccb_cfg = tmp; - if (reg_len == 8) + if (g_sccb_reg_len == 8) { - dvp->sccb_ctl = DVP_SCCB_WRITE_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr) | DVP_SCCB_WDATA_BYTE0(reg_data); + dvp->sccb_ctl = dvp_sccb_write_data_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr) | DVP_SCCB_WDATA_BYTE0(reg_data); } else { - dvp->sccb_ctl = DVP_SCCB_WRITE_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr >> 8) | DVP_SCCB_WDATA_BYTE0(reg_addr & 0xff) | DVP_SCCB_WDATA_BYTE1(reg_data); + dvp->sccb_ctl = dvp_sccb_write_data_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr >> 8) | DVP_SCCB_WDATA_BYTE0(reg_addr & 0xff) | DVP_SCCB_WDATA_BYTE1(reg_data); } dvp_sccb_start_transfer(); return 0; } -uint8_t dvp_sccb_read(uint8_t dev_addr, uint16_t reg_addr) +uint8_t dvp_sccb_read_data(uint8_t dev_addr, uint16_t reg_addr) { uint32_t tmp; tmp = dvp->sccb_cfg & (~DVP_SCCB_BYTE_NUM_MASK); - (reg_len == 8) ? (tmp |= DVP_SCCB_BYTE_NUM_2) : (tmp |= DVP_SCCB_BYTE_NUM_3); + (g_sccb_reg_len == 8) ? (tmp |= DVP_SCCB_BYTE_NUM_2) : (tmp |= DVP_SCCB_BYTE_NUM_3); dvp->sccb_cfg = tmp; - if (reg_len == 8) + if (g_sccb_reg_len == 8) { - dvp->sccb_ctl = DVP_SCCB_WRITE_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr); + dvp->sccb_ctl = dvp_sccb_write_data_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr); } else { - dvp->sccb_ctl = DVP_SCCB_WRITE_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr >> 8) | DVP_SCCB_WDATA_BYTE0(reg_addr & 0xff); + dvp->sccb_ctl = dvp_sccb_write_data_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr >> 8) | DVP_SCCB_WDATA_BYTE0(reg_addr & 0xff); } dvp_sccb_start_transfer(); @@ -130,10 +130,10 @@ static void dvp_reset(void) mdelay(200); } -int dvp_init(uint8_t reglen) +int dvp_init(uint8_t reg_len) { - reg_len = reglen; - sysctl_clock_enable(SYSCTL_CLOCK_DVP); + g_sccb_reg_len = reg_len; + sysctl_clock_tnable(SYSCTL_CLOCK_DVP); sysctl_reset(SYSCTL_RESET_DVP); dvp->cmos_cfg &= (~DVP_CMOS_CLK_DIV_MASK); dvp->cmos_cfg |= DVP_CMOS_CLK_DIV(0) | DVP_CMOS_CLK_ENABLE; @@ -154,7 +154,7 @@ int dvp_set_image_format(uint32_t format) return 0; } -void dvp_burst_enable(void) +void dvp_enable_burst(void) { dvp->dvp_cfg |= DVP_CFG_BURST_SIZE_4BEATS; @@ -162,7 +162,7 @@ void dvp_burst_enable(void) dvp->axi |= DVP_AXI_GM_MLEN_4BYTE; } -void dvp_burst_disable(void) +void dvp_disable_burst(void) { dvp->dvp_cfg &= (~DVP_CFG_BURST_SIZE_4BEATS); @@ -204,7 +204,7 @@ int dvp_set_display_addr(uint32_t addr) return 0; } -int dvp_frame_start(void) +int dvp_start_frame(void) { while (!(dvp->sts & DVP_STS_FRAME_START)) ; @@ -213,12 +213,12 @@ int dvp_frame_start(void) return 0; } -void dvp_convert_start(void) +void dvp_start_convert(void) { dvp->sts = DVP_STS_DVP_EN | DVP_STS_DVP_EN_WE; } -int dvp_convert_finish(void) +int dvp_finish_convert(void) { while (!(dvp->sts & DVP_STS_FRAME_FINISH)) ; @@ -241,7 +241,7 @@ int dvp_get_image(void) return 0; } -void dvp_interrupt_config(uint32_t interrupt, uint8_t status) +void dvp_config_interrupt(uint32_t interrupt, uint8_t status) { if (status) dvp->dvp_cfg |= interrupt; @@ -249,14 +249,14 @@ void dvp_interrupt_config(uint32_t interrupt, uint8_t status) dvp->dvp_cfg &= (~interrupt); } -int dvp_interrupt_get(uint32_t interrupt) +int dvp_get_interrupt(uint32_t interrupt) { if (dvp->sts & interrupt) return 1; return 0; } -void dvp_interrupt_clear(uint32_t interrupt) +void dvp_clear_interrupt(uint32_t interrupt) { interrupt |= (interrupt << 1); dvp->sts |= interrupt; diff --git a/lib/drivers/fpioa.c b/lib/drivers/fpioa.c index c47681c0..a722139d 100644 --- a/lib/drivers/fpioa.c +++ b/lib/drivers/fpioa.c @@ -5195,7 +5195,7 @@ int fpioa_init(void) int i = 0; /* Enable fpioa clock in system controller */ - sysctl_clock_enable(SYSCTL_CLOCK_FPIOA); + sysctl_clock_tnable(SYSCTL_CLOCK_FPIOA); /* Initialize tie */ fpioa_tie_t tie = { 0 }; diff --git a/lib/drivers/gpio.c b/lib/drivers/gpio.c index 080cfb0b..b0049daa 100644 --- a/lib/drivers/gpio.c +++ b/lib/drivers/gpio.c @@ -13,7 +13,7 @@ * limitations under the License. */ #include "gpio.h" -#include "common.h" +#include "utils.h" #include "fpioa.h" #include "sysctl.h" #define GPIO_MAX_PINNO 8 @@ -22,17 +22,10 @@ volatile gpio_t* const gpio = (volatile gpio_t*)GPIO_BASE_ADDR; int gpio_init(void) { - sysctl_clock_enable(SYSCTL_CLOCK_GPIO); - return 0; + return sysctl_clock_tnable(SYSCTL_CLOCK_GPIO); } -void gpio_pin_init(size_t pin_num, size_t gpio_pin) -{ - configASSERT(gpio_pin < GPIO_MAX_PINNO); - fpioa_set_function(pin_num, FUNC_GPIO0 + gpio_pin); -} - -void gpio_set_drive_mode(size_t pin, gpio_drive_mode_t mode) +void gpio_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode) { configASSERT(pin < GPIO_MAX_PINNO); int io_number = fpioa_get_io_by_func(FUNC_GPIO0 + pin); @@ -67,7 +60,7 @@ void gpio_set_drive_mode(size_t pin, gpio_drive_mode_t mode) set_gpio_bit(gpio->direction.u32, pin, dir); } -gpio_pin_value_t gpio_get_pin_value(size_t pin) +gpio_pin_value_t gpio_get_pin(uint8_t pin) { configASSERT(pin < GPIO_MAX_PINNO); uint32_t dir = get_gpio_bit(gpio->direction.u32, pin); @@ -75,7 +68,7 @@ gpio_pin_value_t gpio_get_pin_value(size_t pin) return get_gpio_bit(reg, pin); } -void gpio_set_pin_value(size_t pin, gpio_pin_value_t value) +void gpio_set_pin(uint8_t pin, gpio_pin_value_t value) { configASSERT(pin < GPIO_MAX_PINNO); uint32_t dir = get_gpio_bit(gpio->direction.u32, pin); diff --git a/lib/drivers/gpiohs.c b/lib/drivers/gpiohs.c index 696cee23..91093045 100644 --- a/lib/drivers/gpiohs.c +++ b/lib/drivers/gpiohs.c @@ -13,7 +13,7 @@ * limitations under the License. */ #include "gpiohs.h" -#include "common.h" +#include "utils.h" #include "fpioa.h" #include "sysctl.h" #define GPIOHS_MAX_PINNO 32 @@ -38,13 +38,7 @@ int gpiohs_init(void) return 0; } -void gpiohs_pin_init(size_t pin_num, size_t gpio_pin) -{ - configASSERT(gpio_pin < GPIOHS_MAX_PINNO); - fpioa_set_function(pin_num, FUNC_GPIOHS0 + gpio_pin); -} - -void gpiohs_set_drive_mode(size_t pin, gpio_drive_mode_t mode) +void gpiohs_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode) { configASSERT(pin < GPIOHS_MAX_PINNO); int io_number = fpioa_get_io_by_func(FUNC_GPIOHS0 + pin); @@ -82,19 +76,19 @@ void gpiohs_set_drive_mode(size_t pin, gpio_drive_mode_t mode) set_gpio_bit(reg, pin, 1); } -gpio_pin_value_t gpiohs_get_pin_value(size_t pin) +gpio_pin_value_t gpiohs_get_pin(uint8_t pin) { configASSERT(pin < GPIOHS_MAX_PINNO); return get_gpio_bit(gpiohs->input_val.u32, pin); } -void gpiohs_set_pin_value(size_t pin, gpio_pin_value_t value) +void gpiohs_set_pin(uint8_t pin, gpio_pin_value_t value) { configASSERT(pin < GPIOHS_MAX_PINNO); set_gpio_bit(gpiohs->output_val.u32, pin, value); } -void gpiohs_set_pin_edge(size_t pin, gpio_pin_edge_t edge) +void gpiohs_set_pin_edge(uint8_t pin, gpio_pin_edge_t edge) { uint32_t rise, fall, irq; switch (edge) @@ -168,7 +162,7 @@ int gpiohs_pin_onchange_isr(void* userdata) return 0; } -void gpiohs_set_irq(size_t pin, uint32_t priority, void (*func)()) +void gpiohs_set_irq(uint8_t pin, uint32_t priority, void (*func)()) { pin_context[pin].pin = pin; diff --git a/lib/drivers/i2c.c b/lib/drivers/i2c.c index ae7d5d60..ed0170fd 100644 --- a/lib/drivers/i2c.c +++ b/lib/drivers/i2c.c @@ -14,7 +14,7 @@ */ #include #include "i2c.h" -#include "common.h" +#include "utils.h" #include "fpioa.h" #include "platform.h" #include "stdlib.h" @@ -28,14 +28,14 @@ volatile i2c_t* const i2c[3] = (volatile i2c_t*)I2C2_BASE_ADDR }; -static void i2c_clk_init(i2c_device_num_t i2c_num) +static void i2c_clk_init(i2c_device_number_t i2c_num) { configASSERT(i2c_num < I2C_MAX_NUM); - sysctl_clock_enable(SYSCTL_CLOCK_I2C0 + i2c_num); + sysctl_clock_tnable(SYSCTL_CLOCK_I2C0 + i2c_num); sysctl_clock_set_threshold(SYSCTL_THRESHOLD_I2C0 + i2c_num, 3); } -void i2c_config(i2c_device_num_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode) +void i2c_config(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode) { configASSERT(i2c_num < I2C_MAX_NUM); configASSERT(address_width == 7 || address_width == 10); @@ -64,7 +64,7 @@ void i2c_config(i2c_device_num_t i2c_num, uint32_t slave_address, uint32_t addre i2c_adapter->enable = I2C_ENABLE_ENABLE; } -int i2c_send_data(i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len) +int i2c_send_data(i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len) { configASSERT(i2c_num < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[i2c_num]; @@ -85,7 +85,7 @@ int i2c_send_data(i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_l return 0; } -int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len) +int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len) { configASSERT(i2c_num < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[i2c_num]; @@ -112,7 +112,7 @@ int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_num_t i2 return 0; } -int i2c_receive_data(i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len) +int i2c_receive_data(i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len) { uint8_t fifo_len, index; uint8_t rx_len = receive_buf_len; @@ -149,7 +149,7 @@ int i2c_receive_data(i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_bu } int i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len) + i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len) { configASSERT(i2c_num < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[i2c_num]; diff --git a/lib/drivers/i2s.c b/lib/drivers/i2s.c index 36e80bee..8abcd773 100644 --- a/lib/drivers/i2s.c +++ b/lib/drivers/i2s.c @@ -25,9 +25,9 @@ volatile i2s_t *const i2s[3] = (volatile i2s_t *)I2S2_BASE_ADDR }; -void i2s_init(i2s_device_num_t device_num, i2s_transmit_t rxtx_mode, uint32_t channel_mask) +void i2s_init(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode, uint32_t channel_mask) { - sysctl_clock_enable(SYSCTL_CLOCK_I2S0 + device_num); + sysctl_clock_tnable(SYSCTL_CLOCK_I2S0 + device_num); sysctl_reset(SYSCTL_RESET_I2S0 + device_num); sysctl_clock_set_threshold(SYSCTL_THRESHOLD_I2S0 + device_num, 7); /*96k:5,44k:12,24k:23,22k:25 16k:35 sampling*/ @@ -72,7 +72,7 @@ void i2s_init(i2s_device_num_t device_num, i2s_transmit_t rxtx_mode, uint32_t ch } } -void i2s_device_enable(i2s_device_num_t device_num) +void i2s_device_enable(i2s_device_number_t device_num) { ier_t u_ier; @@ -81,7 +81,7 @@ void i2s_device_enable(i2s_device_num_t device_num) writel(u_ier.reg_data, &i2s[device_num]->ier); } -void i2s_dev_enable(i2s_device_num_t device_num, uint32_t enable) +void i2s_dev_enable(i2s_device_number_t device_num, uint32_t enable) { ier_t u_ier; @@ -90,7 +90,7 @@ void i2s_dev_enable(i2s_device_num_t device_num, uint32_t enable) writel(u_ier.reg_data, &i2s[device_num]->ier); } -void i2s_disable_block(i2s_device_num_t device_num, i2s_transmit_t rxtx_mode) +void i2s_disable_block(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode) { irer_t u_irer; iter_t u_iter; @@ -111,7 +111,7 @@ void i2s_disable_block(i2s_device_num_t device_num, i2s_transmit_t rxtx_mode) } } -void i2s_receive_enable(i2s_device_num_t device_num, i2s_channel_num_t channel_num) +void i2s_receive_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num) { irer_t u_irer; @@ -124,7 +124,7 @@ void i2s_receive_enable(i2s_device_num_t device_num, i2s_channel_num_t channel_n /* Receive channel enable */ } -void i2s_transimit_enable(i2s_device_num_t device_num, i2s_channel_num_t channel_num) +void i2s_transimit_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num) { iter_t u_iter; @@ -137,7 +137,7 @@ void i2s_transimit_enable(i2s_device_num_t device_num, i2s_channel_num_t channel /* Transmit channel enable */ } -void i2s_rx_channel_configure(i2s_device_num_t device_num, +void i2s_rx_channel_configure(i2s_device_number_t device_num, i2s_channel_num_t channel_num, word_length_t word_length, word_select_cycles_t word_select_size, @@ -172,7 +172,7 @@ void i2s_rx_channel_configure(i2s_device_num_t device_num, i2s_receive_channel_enable(device_num, channel_num, 1); } -void i2s_tx_channel_configure(i2s_device_num_t device_num, +void i2s_tx_channel_configure(i2s_device_number_t device_num, i2s_channel_num_t channel_num, word_length_t word_length, word_select_cycles_t word_select_size, @@ -206,7 +206,7 @@ void i2s_tx_channel_configure(i2s_device_num_t device_num, i2s_transmit_channel_enable(device_num, channel_num, 1); } -int i2s_set_rx_word_length(i2s_device_num_t device_num, +int i2s_set_rx_word_length(i2s_device_number_t device_num, word_length_t word_length, i2s_channel_num_t channel_num) { @@ -223,7 +223,7 @@ int i2s_set_rx_word_length(i2s_device_num_t device_num, return 0; } -int i2s_set_tx_word_length(i2s_device_num_t device_num, +int i2s_set_tx_word_length(i2s_device_number_t device_num, word_length_t word_length, i2s_channel_num_t channel_num) { @@ -240,7 +240,7 @@ int i2s_set_tx_word_length(i2s_device_num_t device_num, return 0; } -int i2s_master_configure(i2s_device_num_t device_num, +int i2s_master_configure(i2s_device_number_t device_num, word_select_cycles_t word_select_size, sclk_gating_cycles_t gating_cycles, i2s_work_mode_t word_mode) @@ -269,7 +269,7 @@ int i2s_master_configure(i2s_device_num_t device_num, return 0; } -int i2s_set_rx_threshold(i2s_device_num_t device_num, +int i2s_set_rx_threshold(i2s_device_number_t device_num, fifo_threshold_t threshold, i2s_channel_num_t channel_num) { @@ -287,7 +287,7 @@ int i2s_set_rx_threshold(i2s_device_num_t device_num, return 0; } -int i2s_set_tx_threshold(i2s_device_num_t device_num, +int i2s_set_tx_threshold(i2s_device_number_t device_num, fifo_threshold_t threshold, i2s_channel_num_t channel_num) { @@ -304,7 +304,7 @@ int i2s_set_tx_threshold(i2s_device_num_t device_num, return 0; } -int i2s_set_mask_interrupt(i2s_device_num_t device_num, +int i2s_set_mask_interrupt(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint32_t rx_available_int, uint32_t rx_overrun_int, uint32_t tx_empty_int, uint32_t tx_overrun_int) @@ -336,7 +336,7 @@ int i2s_set_mask_interrupt(i2s_device_num_t device_num, return 0; } -int i2s_receive_channel_enable(i2s_device_num_t device_num, +int i2s_receive_channel_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint32_t enable) { rer_t u_rer; @@ -349,7 +349,7 @@ int i2s_receive_channel_enable(i2s_device_num_t device_num, return 0; } -int i2s_transmit_channel_enable(i2s_device_num_t device_num, +int i2s_transmit_channel_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint32_t enable) { ter_t u_ter; @@ -363,7 +363,7 @@ int i2s_transmit_channel_enable(i2s_device_num_t device_num, return 0; } -int i2s_transmit_dma_enable(i2s_device_num_t device_num, uint32_t enable) +int i2s_transmit_dma_enable(i2s_device_number_t device_num, uint32_t enable) { ccr_t u_ccr; @@ -377,7 +377,7 @@ int i2s_transmit_dma_enable(i2s_device_num_t device_num, uint32_t enable) return 0; } -int i2s_receive_dma_enable(i2s_device_num_t device_num, uint32_t enable) +int i2s_receive_dma_enable(i2s_device_number_t device_num, uint32_t enable) { ccr_t u_ccr; @@ -391,7 +391,7 @@ int i2s_receive_dma_enable(i2s_device_num_t device_num, uint32_t enable) return 0; } -int i2s_transmit_dma_divide(i2s_device_num_t device_num, uint32_t enable) +int i2s_transmit_dma_divide(i2s_device_number_t device_num, uint32_t enable) { ccr_t u_ccr; @@ -405,7 +405,7 @@ int i2s_transmit_dma_divide(i2s_device_num_t device_num, uint32_t enable) return 0; } -int i2s_receive_data(i2s_device_num_t device_num, i2s_channel_num_t channel_num, uint64_t *buf, size_t buf_len) +int i2s_receive_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint64_t *buf, size_t buf_len) { uint32_t i = 0; isr_t u_isr; @@ -426,7 +426,7 @@ int i2s_receive_data(i2s_device_num_t device_num, i2s_channel_num_t channel_num, return 0; } -int i2s_receive_data_dma(i2s_device_num_t device_num, uint32_t *buf, +int i2s_receive_data_dma(i2s_device_number_t device_num, uint32_t *buf, size_t buf_len, dmac_channel_number_t channel_num) { static uint8_t dmac_recv_flag[6] = {0,0,0,0,0,0}; @@ -440,7 +440,7 @@ int i2s_receive_data_dma(i2s_device_num_t device_num, uint32_t *buf, return 0; } -int i2s_rx_to_tx(i2s_device_num_t device_src_num, i2s_device_num_t device_dest_num, +int i2s_rx_to_tx(i2s_device_number_t device_src_num, i2s_device_number_t device_dest_num, size_t buf_len, dmac_channel_number_t channel_num) { static uint8_t dmac_recv_flag[6] = {0,0,0,0,0,0}; @@ -454,7 +454,7 @@ int i2s_rx_to_tx(i2s_device_num_t device_src_num, i2s_device_num_t device_dest_n return 0; } -int i2s_send_data(i2s_device_num_t device_num, i2s_channel_num_t channel_num, uint8_t *pcm, size_t buf_len, size_t single_length) +int i2s_send_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint8_t *pcm, size_t buf_len, size_t single_length) { isr_t u_isr; uint32_t left_buffer = 0; @@ -506,7 +506,7 @@ int i2s_send_data(i2s_device_num_t device_num, i2s_channel_num_t channel_num, ui return 0; } -void i2s_send_data_dma(i2s_device_num_t device_num, void *pcm, size_t buf_len, dmac_channel_number_t channel_num) +void i2s_send_data_dma(i2s_device_number_t device_num, void *pcm, size_t buf_len, dmac_channel_number_t channel_num) { static uint8_t dmac_init_flag[6] = {0,0,0,0,0,0}; if(dmac_init_flag[channel_num]) @@ -562,7 +562,7 @@ void i2s_parse_voice(uint32_t *buf, uint8_t *pcm, uint32_t length, uint32_t bit } -int i2s_play(i2s_device_num_t device_num,dmac_channel_number_t channel_num, +int i2s_play(i2s_device_number_t device_num,dmac_channel_number_t channel_num, uint8_t *buf, size_t buf_len, size_t frame, size_t bits_per_sample, uint8_t track_num) { uint32_t sample_cnt = buf_len / ( bits_per_sample / 8 ) / track_num; diff --git a/lib/drivers/include/audio_bf.h b/lib/drivers/include/audio_bf.h deleted file mode 100644 index bc7d5886..00000000 --- a/lib/drivers/include/audio_bf.h +++ /dev/null @@ -1,329 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _DRIVER_AUDIO_BF_H -#define _DRIVER_AUDIO_BF_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum _en_bf_dir -{ - BF_DIR0 = 0, - BF_DIR1, - BF_DIR2, - BF_DIR3, - BF_DIR4, - BF_DIR5, - BF_DIR6, - BF_DIR7, - BF_DIR8, - BF_DIR9, - BF_DIR10, - BF_DIR11, - BF_DIR12, - BF_DIR13, - BF_DIR14, - BF_DIR15, -} en_bf_dir_t; - -typedef struct _audio_bf_ch_cfg -{ - /** - * BF unit sound channel enable control bits. - * Bit 'x' corresponds to enable bit for sound channel 'x' (x = 0, 1, 2, - * . . ., 7). BF sound channels are related with I2S host RX channels. - * BF sound channel 0/1 correspond to the left/right channel of I2S RX0; - * BF channel 2/3 correspond to left/right channels of I2S RX1; and - * things like that. 0x1: writing '1' to enable the corresponding BF - * sound channel. 0x0: writing '0' to close the corresponding BF sound - * channel. - */ - uint32_t bf_sound_ch_en : 8; - /** - * Target direction select for valid voice output. - * When the source voice direaction searching is done, software can use - * this field to select one from 16 sound directions for the following - * voice recognition. 0x0: select sound direction 0; 0x1: select sound - * direction 1; . . . . . . 0xF: select sound direction 15. - */ - uint32_t bf_target_dir : 4; - /** - * This is the audio sample gain factor. Using this gain factor to - * enhance or reduce the stength of the sum of at most 8 source - * sound channel outputs. This is a unsigned 11-bit fix-point number, - * bit 10 is integer part and bit 9~0 are the fractional part. - */ - uint32_t audio_gain : 11; - uint32_t reserved1 : 1; - /** - * audio data source configure parameter. This parameter controls where - * the audio data source comes from. 0x0: audio data directly sourcing - * from audio_bf internal buffer; 0x1: audio data sourcing from - * FFT result buffer. - */ - uint32_t data_src_mode : 1; - uint32_t reserved2 : 3; - /** - * write enable for bf_sound_ch_en parameter. - * 0x1: allowing updates made to 'bf_sound_ch_en'. - * Access Mode: write only - */ - uint32_t we_bf_sound_ch_en : 1; - /** - * write enable for bf_target_dir parameter. - * 0x1: allowing updates made to 'bf_target_dir'. - * Access Mode: write only - */ - uint32_t we_bf_target_dir : 1; - /** - * write enable for audio_gain parameter. - * 0x1: allowing updates made to 'audio_gain'. - * Access Mode: write only - */ - uint32_t we_audio_gain : 1; - /** - * write enable for data_out_mode parameter. - * 0x1: allowing updates made to 'data_src_mode'. - */ - uint32_t we_data_src_mode : 1; -} __attribute__((packed, aligned(4))) audio_bf_ch_cfg_t; - -typedef struct _audio_bf_ctl -{ - /** - * Sound direction searching enable bit. - * Software writes '1' to start sound direction searching function. - * When all the sound sample buffers are filled full, this bit is - * cleared by hardware (this sample buffers are used for direction - * detect only). 0x1: enable direction searching. - */ - uint32_t bf_dir_search_en : 1; - /* - *use this parameter to reset all the control logic on direction search processing path. This bit is self-clearing. - * 0x1: apply reset to direction searching control logic; - * 0x0: No operation. - */ - uint32_t search_path_reset : 1; - uint32_t reserved : 2; - /** - * Valid voice sample stream generation enable bit. - * After sound direction searching is done, software can configure this - * bit to generate a stream of voice samples for voice recognition. 0x1: - * enable output of voice sample stream. 0x0: stop the voice samlpe - * stream output. - */ - uint32_t bf_stream_gen_en : 1; - /* - *use this parameter to reset all the control logic on voice stream generating path. This bit is self-clearing. - * 0x1: apply reset to voice stream generating control logic; - * 0x0: No operation. - */ - uint32_t voice_gen_path_reset : 1; - /* - *use this parameter to switch to a new voice source direction. Software write '1' here and hardware will automatically clear it. - * 0x1: write '1' here to request switching to new voice source direction. - */ - uint32_t update_voice_dir : 1; - - uint32_t reserved1 : 1; - //write enable for 'bf_dir_search_en' parameter. - uint32_t we_bf_dir_search_en : 1; - uint32_t we_search_path_rst : 1; - uint32_t we_bf_stream_gen : 1; - uint32_t we_voice_gen_path_rst : 1; - uint32_t we_update_voice_dir : 1; - uint32_t reserved2 : 19; - -} __attribute__((packed, aligned(4))) audio_bf_ctl_t; - -typedef struct _audio_bf_dir_bidx -{ - uint32_t dir_rd_idx0 : 6; - uint32_t reserved : 2; - uint32_t dir_rd_idx1 : 6; - uint32_t reserved1 : 2; - uint32_t dir_rd_idx2 : 6; - uint32_t reserved2 : 2; - uint32_t dir_rd_idx3 : 6; - uint32_t reserved3 : 2; -} __attribute__((packed, aligned(4))) audio_bf_dir_bidx_t; - -typedef struct _audio_bf_fir_coef -{ - uint32_t fir_tap0 : 16; - uint32_t fir_tap1 : 16; -} __attribute__((packed, aligned(4))) audio_bf_fir_coef_t; - -typedef struct _audio_bf_dwsz_cfg -{ - /** - * TThe down-sizing ratio used for direction searching. - * 0x0: no down-sizing; - * 0x1: 1/2 down sizing; - * 0x2: 1/3 down sizing; - * . . . . . . - * 0xF: 1/16 down sizing. - */ - uint32_t dir_dwn_siz_rate : 4; - /** - * The down-sizing ratio used for voice stream generation. - * 0x0: no down-sizing; - * 0x1: 1/2 down sizing; - * 0x2: 1/3 down sizing; - * . . . . . . - * 0xF: 1/16 down sizing. - */ - uint32_t voc_dwn_siz_rate : 4; - /** - * This bit field is used to perform sample precision reduction when - * the source sound sample (from I2S0 host receiving channels) - * precision is 20/24/32 bits. - * 0x0: take bits 15~0 from the source sound sample; - * 0x1: take bits 16~1 from the source sound sample; - * 0x2: take bits 17~2 from the source sound sample; - * . . . . . . - * 0x10: take bits 31~16 from the source sound sample; - */ - uint32_t smpl_shift_bits : 5; - uint32_t reserved : 19; -} __attribute__((packed, aligned(4))) audio_bf_dwsz_cfg_t; - -typedef struct _audio_bf_fft_cfg -{ - uint32_t fft_shift_factor : 9; - uint32_t reserved1 : 3; - uint32_t fft_enable : 1; - uint32_t reserved2 : 19; -} __attribute__((packed, aligned(4))) audio_bf_fft_cfg_t; - -typedef struct _audio_bf_int_stat -{ - /** - * sound direction searching data ready interrupt event. - * Writing '1' to clear this interrupt event. - * 0x1: data is ready for sound direction detect; - * 0x0: no event. - */ - uint32_t dir_search_data_rdy : 1; - /** - * voice output stream buffer data ready interrupt event. - * When a block of 512 voice samples are collected, this interrupt event - * is asserted. Writing '1' to clear this interrupt event. 0x1: voice - * output stream buffer data is ready; 0x0: no event. - */ - uint32_t voc_buf_data_rdy : 1; - uint32_t reserved : 30; -} __attribute__((packed, aligned(4))) audio_bf_int_stat_t; - -typedef struct _audio_bf_int_mask -{ - /** - * This is the interrupt mask to dir searching data ready interrupt. - * 0x1: mask off this interrupt; - * 0x0: enable this interrupt. - */ - uint32_t dir_data_rdy_msk : 1; - /** - * This is the interrupt mask to voice output stream buffer ready - * interrupt. 0x1: mask off this interrupt; 0x0: enable this interrupt. - */ - uint32_t voc_buf_rdy_msk : 1; - uint32_t reserved : 30; -} __attribute__((packed, aligned(4))) audio_bf_int_mask_t; - -typedef struct _audio_bf_reg -{ - /* 0x200 */ - audio_bf_ch_cfg_t bf_ch_cfg_reg; - /* 0x204 */ - audio_bf_ctl_t bf_ctl_reg; - /* 0x208 */ - audio_bf_dir_bidx_t bf_dir_bidx[16][2]; - /* 0x288 */ - audio_bf_fir_coef_t bf_pre_fir0_coef[9]; - /* 0x2ac */ - audio_bf_fir_coef_t bf_post_fir0_coef[9]; - /* 0x2d0 */ - audio_bf_fir_coef_t bf_pre_fir1_coef[9]; - /* 0x2f4 */ - audio_bf_fir_coef_t bf_post_fir1_coef[9]; - /* 0x318 */ - audio_bf_dwsz_cfg_t bf_dwsz_cfg_reg; - /* 0x31c */ - audio_bf_fft_cfg_t bf_fft_cfg_reg; - /* 0x320 */ - /** - * This is the read register for system DMA to read data stored in - * sample out buffers (the sample out buffers are used for sound - * direction detect). Each data contains two sound samples. - */ - volatile uint32_t sobuf_dma_rdata; - /* 0x324 */ - /** - * This is the read register for system DMA to read data stored in voice - * out buffers (the voice out buffers are used for voice recognition). - * Each data contains two sound samples. - */ - volatile uint32_t vobuf_dma_rdata; - /* 0x328 */ - audio_bf_int_stat_t bf_int_stat_reg; - /* 0x32c */ - audio_bf_int_mask_t bf_int_mask_reg; - /* 0x330 */ - uint32_t saturation_counter; - /* 0x334 */ - uint32_t saturation_limits; -} __attribute__((packed, aligned(4))) audio_bf_reg_t; - -extern volatile audio_bf_reg_t* const audio_bf; - -void audio_bf_set_audio_gain(uint16_t gain); -void audio_bf_set_smpl_shift(uint8_t smpl_shift); -uint8_t audio_bf_get_smpl_shift(void); -void audio_bf_set_channel_enabled(uint8_t channel_bit); -void audio_bf_set_direction_delay(uint8_t dir_num, uint8_t* dir_bidx); -void audio_bf_set_fft_shift_factor(uint8_t enable_flag, uint16_t shift_factor); -void audio_bf_set_down_size(uint8_t dir_dwn_siz, uint8_t voc_dwn_siz); -void audio_bf_set_interrupt_mask(uint8_t dir_int_mask, uint8_t voc_int_mask); - -void audio_bf_dir_enable(void); -void audio_bf_dir_reset(void); -void audio_bf_dir_set_prev_fir(uint16_t* fir_coef); -void audio_bf_dir_set_post_fir(uint16_t* fir_coef); -void audio_bf_dir_set_down_size(uint8_t dir_dwn_size); -void audio_bf_dir_set_interrupt_mask(uint8_t dir_int_mask); -void audio_bf_dir_clear_int_state(void); - -void audio_bf_voc_enable(uint8_t enable_flag); -void audio_bf_voc_reset(void); -void audio_bf_voc_set_direction(en_bf_dir_t direction); -void audio_bf_voc_set_prev_fir(uint16_t* fir_coef); -void audio_bf_voc_set_post_fir(uint16_t* fir_coef); -void audio_bf_voc_set_down_size(uint8_t voc_dwn_size); -void audio_bf_voc_set_interrupt_mask(uint8_t voc_int_mask); -void audio_bf_voc_clear_int_state(void); -void audio_bf_voc_reset_saturation_counter(void); -uint32_t audio_bf_voc_get_saturation_counter(void); -void audio_bf_voc_set_saturation_limit(uint16_t upper, uint16_t bottom); -uint32_t audio_bf_voc_get_saturation_limit(void); - -void audio_bf_print_setting(void); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRIVER_AUDIO_BF_H */ diff --git a/lib/drivers/include/dmac.h b/lib/drivers/include/dmac.h index f1093dd8..c41d348b 100644 --- a/lib/drivers/include/dmac.h +++ b/lib/drivers/include/dmac.h @@ -1404,254 +1404,6 @@ extern volatile dmac_t *const dmac; */ void dmac_init(void); -/** - * @brief Read dmac id - * - * @return Dmac id - */ -uint64_t dmac_read_id(void); - -/** - * @brief Read dmac component version - * - * @return Dmac version - */ -uint64_t dmac_read_version(void); - -/** - * @brief Read AXI channel id - * - * @param[in] channel_num The channel number - * - * @return channel AXI ID data - */ -uint64_t dmac_read_channel_id(dmac_channel_number_t ch); - -/** - * @brief Set channle configure - * - * @param[in] channel_num The channel number - * @param[in] cfg_param The configuration parameter - * - * @return result - * - 0 Success - * - Other Fail - */ -int dmac_set_channel_config(dmac_channel_number_t channel_num, - dmac_channel_config_t *cfg_param); - -/** - * @brief Get channel configure param - * - * @param[in] channel_num The channel number - * @param[out] cfg_param The configuration parameter - * - * @return result - * - 0 Success - * - Other Fail - */ -int dmac_get_channel_config(dmac_channel_number_t channel_num, - dmac_channel_config_t *cfg_param); - -/** - * @brief Enable dmac source transaction complete interrupt - * - * @param[in] channel_num The channel number - */ -void src_transaction_complete_int_enable(dmac_channel_number_t channel_num); - -/** - * @brief Enable dmac channel - * - * @param[in] channel_num The channel number - */ -void dmac_channel_enable(dmac_channel_number_t channel_num); - -/** - * @brief Enable dmac - */ -void dmac_enable(void); - -/** - * @brief Enable dmac channel interrupt status - * - * @param[in] channel_num The channel number - */ -void dmac_enable_channel_interrupt_status(dmac_channel_number_t channel_num); - -/** - * @brief Disable dmac channel interrupt status - * - * @param[in] channel_num The channel number - */ -void dmac_disable_channel_interrupt_status(dmac_channel_number_t channel_num); - -/** - * @brief Check whether channel is busy - * - * @param[in] channel_num The channel number - * - * @return result - * - 0 Not busy - * - 1 Busy - */ -int32_t dmac_check_channel_busy(dmac_channel_number_t channel_num); - -/** - * @brief Clear interrupt status - * - * @param[in] channel_num The channel number - */ -void dmac_chanel_interrupt_clear(dmac_channel_number_t channel_num); - -/** - * @brief Create link list item - * - * @param[in] channel_num The channel number - * @param[in] LLI_row_num The lli row number - * @param[in] LLI_last_row The lli last row - * @param[out] lli_item The lli item - * @param[in] cfg_param The configuration parameter - */ -void dmac_link_list_item(dmac_channel_number_t channel_num, uint8_t lli_row_num, - int8_t lli_last_row, dmac_lli_item_t *lli_item, - dmac_channel_config_t *cfg_param); - -/** - * @brief linked list mode list addr entry, - * descriptor table must be 64 byte aligned - * - * @param[in] channel_num The channel number - * @param[in] addr The address - */ -void dmac_set_linked_list_addr_point(dmac_channel_number_t channel_num, - uint64_t *addr); - -/** - * @brief Set flow control - * - * @param[in] channel_num The channel number - * @param[in] flow_control The flow control - */ -void dmac_set_flow_control(dmac_channel_number_t channel_num, - dmac_transfer_flow_t flow_control); - -/** - * @brief Set multitransfer type and handshake - * - * @param[in] channel_num The channel number - * @param[in] transfer_type The transfer type - * @param[in] handshak_select The handshake select - */ -void dmac_set_destination_transfer_control(dmac_channel_number_t channel_num, - dmac_multiblk_transfer_type_t transfer_type, - dmac_sw_hw_hs_select_t handshak_select); - -/** - * @brief Set multitransfer type and handshak - * - * @param[in] channel_num The channel number - * @param[in] transfer_type The transfer type - * @param[in] handshak_select The handshake select - */ -void dmac_set_source_transfer_control(dmac_channel_number_t channel_num, - dmac_multiblk_transfer_type_t transfer_type, - dmac_sw_hw_hs_select_t handshak_select); - -/** - * @brief Set destination's master,address mode, transfer width and transfer length - * - * @param[in] channel_num The channel number - * @param[in] master_select The master select - * @param[in] address_mode The address mode - * @param[in] tr_width The tr width - * @param[in] burst_length The burst length - */ -void dmac_master_control(dmac_channel_number_t channel_num, - dmac_master_number_t master_select, - dmac_address_increment_t address_mode, - dmac_transfer_width_t tr_width, - dmac_burst_trans_length_t burst_length); - -/** - * @brief Set source's master,address mode, transfer width and transfer length - * - * @param[in] channel_num The channel number - * @param[in] master_select The master select - * @param[in] address_mode The address mode - * @param[in] tr_width The transfer width - * @param[in] burst_length The burst transfer length - */ -void dmac_source_control(dmac_channel_number_t channel_num, - dmac_master_number_t master_select, - dmac_address_increment_t address_mode, - dmac_transfer_width_t tr_width, - dmac_burst_trans_length_t burst_length); - -/** - * @brief Set block transfer size - * - * @param[in] channel_num The channel number - * @param[in] block_size The block size - */ -void dmac_set_block_ts(dmac_channel_number_t channel_num, uint32_t block_size); - -/** - * @brief Set dmac address - * - * @param[in] channel_num The channel number - * @param src_addr The source address - * @param dst_src The destination source - */ -void dmac_set_address(dmac_channel_number_t channel_num, uint64_t src_addr, - uint64_t dst_addr); - -/** - * @brief Disable channel - * - * @param[in] channel_num The channel number - */ -void dmac_channel_disable(dmac_channel_number_t channel_num); - -/** - * @brief Update dmac shadow register - * - * @param[in] channel_num The channel number - * @param[in] last_block The last block - * @param[in] cfg_param The configuration parameter - */ -void dmac_update_shandow_register(dmac_channel_number_t channel_num, int8_t last_block, - dmac_channel_config_t *cfg_param); - -/** - * @brief Set shadow register invalid flag, used for first block transfer, after configure - * - * @param[in] channel_num The channel number - */ -void dmac_set_shadow_invalid_flag(dmac_channel_number_t channel_num); - -/** - * @brief Set dmac channel parameters - * - * @param[in] channel_num The channel number - * @param[in] src The source address - * @param[in] dest The destination address - * @param[in] src_inc Whether the source address auto increment - * @param[in] dest_inc Whether the destination address auto increment - * @param[in] dmac_msize The dmac burst transfer length - * @param[in] dmac_trans_width The dmac transfer width - * @param[in] blockSize The block size - * - * @return result - * - 0 Success - * - Other Fail - */ -int dmac_set_channel_param(dmac_channel_number_t channel_num, - void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, - dmac_burst_trans_length_t dmac_msize, - dmac_transfer_width_t dmac_trans_width, - uint32_t blockSize); - /** * @brief Set dmac param * diff --git a/lib/drivers/include/dvp.h b/lib/drivers/include/dvp.h index a6fad608..35ff866a 100644 --- a/lib/drivers/include/dvp.h +++ b/lib/drivers/include/dvp.h @@ -73,7 +73,7 @@ typedef struct _dvp #define DVP_SCCB_RDATA_BYTE(x) ((x) >> 24) /* DVP SCCB Control Register */ -#define DVP_SCCB_WRITE_ENABLE 0x00000001 +#define dvp_sccb_write_data_ENABLE 0x00000001 #define DVP_SCCB_DEVICE_ADDRESS(x) ((x) << 0) #define DVP_SCCB_REG_ADDRESS(x) ((x) << 8) #define DVP_SCCB_WDATA_BYTE0(x) ((x) << 16) @@ -107,7 +107,7 @@ extern volatile dvp_t* const dvp; * - 0 Success * - Other Fail */ -int dvp_init(uint8_t reglen); +int dvp_init(uint8_t reg_len); /** * @brief Set image format @@ -165,7 +165,7 @@ int dvp_set_display_addr(uint32_t addr); * - 0 Success * - Other Fail */ -int dvp_frame_start(void); +int dvp_start_frame(void); /** * @brief The DVP convert start @@ -174,7 +174,7 @@ int dvp_frame_start(void); * - 0 Success * - Other Fail */ -void dvp_convert_start(void); +void dvp_start_convert(void); /** * @brief The DVP convert finish @@ -183,7 +183,7 @@ void dvp_convert_start(void); * - 0 Success * - Other Fail */ -int dvp_convert_finish(void); +int dvp_finish_convert(void); /** * @brief Get the image data @@ -207,7 +207,7 @@ int dvp_get_image(void); * - 0 Success * - Other Fail */ -int dvp_sccb_write(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data); +int dvp_sccb_write_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data); /** * @brief Use SCCB read register @@ -217,17 +217,17 @@ int dvp_sccb_write(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data); * * @return The register value */ -uint8_t dvp_sccb_read(uint8_t dev_addr, uint16_t reg_addr); +uint8_t dvp_sccb_read_data(uint8_t dev_addr, uint16_t reg_addr); /** * @brief Enable dvp burst */ -void dvp_burst_enable(void); +void dvp_enable_burst(void); /** * @brief Disable dvp burst */ -void dvp_burst_disable(void); +void dvp_disable_burst(void); /** * @brief Enable or disable dvp interrupt @@ -236,7 +236,7 @@ void dvp_burst_disable(void); * @param[in] status 0:disable 1:enable * */ -void dvp_interrupt_config(uint32_t interrupt, uint8_t status); +void dvp_config_interrupt(uint32_t interrupt, uint8_t status); /** * @brief Get dvp interrupt status @@ -248,7 +248,7 @@ void dvp_interrupt_config(uint32_t interrupt, uint8_t status); * - 0 false * - 1 true */ -int dvp_interrupt_get(uint32_t interrupt); +int dvp_get_interrupt(uint32_t interrupt); /** * @brief Clear dvp interrupt status @@ -256,7 +256,7 @@ int dvp_interrupt_get(uint32_t interrupt); * @param[in] interrupt Dvp interrupt * */ -void dvp_interrupt_clear(uint32_t interrupt); +void dvp_clear_interrupt(uint32_t interrupt); /** * @brief Enable dvp auto mode diff --git a/lib/drivers/include/gpio.h b/lib/drivers/include/gpio.h index c5de2e10..9d96e175 100644 --- a/lib/drivers/include/gpio.h +++ b/lib/drivers/include/gpio.h @@ -133,21 +133,13 @@ extern volatile gpio_t *const gpio; */ int gpio_init(void); -/** - * @brief Gpio pin initialize, map Pin number to Gpio function pin - * - * @param[in] pin_num Pin number - * @param[in] gpio_pin Gpio pin - */ -void gpio_pin_init(size_t pin_num, size_t gpio_pin); - /** * @brief Set Gpio drive mode * * @param[in] pin Gpio pin * @param[in] mode Gpio pin drive mode */ -void gpio_set_drive_mode(size_t pin, gpio_drive_mode_t mode); +void gpio_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode); /** * @brief Get Gpio pin value @@ -158,7 +150,7 @@ void gpio_set_drive_mode(size_t pin, gpio_drive_mode_t mode); * - GPIO_PV_Low Gpio pin low * - GPIO_PV_High Gpio pin high */ -gpio_pin_value_t gpio_get_pin_value(size_t pin); +gpio_pin_value_t gpio_get_pin(uint8_t pin); /** * @brief Set Gpio pin value @@ -166,7 +158,7 @@ gpio_pin_value_t gpio_get_pin_value(size_t pin); * @param[in] pin Gpio pin * @param[in] value Gpio pin value */ -void gpio_set_pin_value(size_t pin, gpio_pin_value_t value); +void gpio_set_pin(uint8_t pin, gpio_pin_value_t value); #ifdef __cplusplus } diff --git a/lib/drivers/include/gpiohs.h b/lib/drivers/include/gpiohs.h index a11462ca..30a934fd 100644 --- a/lib/drivers/include/gpiohs.h +++ b/lib/drivers/include/gpiohs.h @@ -207,21 +207,13 @@ extern volatile gpiohs_t *const gpiohs; */ int gpiohs_init(void); -/** - * @brief Gpiohs pin initialize, map Pin number to Gpio function pin - * - * @param[in] pin_num Pin number - * @param[in] gpio_pin Gpiohs pin - */ -void gpiohs_pin_init(size_t pin_num, size_t gpio_pin); - /** * @brief Set Gpiohs drive mode * * @param[in] pin Gpiohs pin * @param[in] mode Gpiohs pin drive mode */ -void gpiohs_set_drive_mode(size_t pin, gpio_drive_mode_t mode); +void gpiohs_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode); /** * @brief Get Gpiohs pin value @@ -232,7 +224,7 @@ void gpiohs_set_drive_mode(size_t pin, gpio_drive_mode_t mode); * - GPIO_PV_Low Gpiohs pin low * - GPIO_PV_High Gpiohs pin high */ -gpio_pin_value_t gpiohs_get_pin_value(size_t pin); +gpio_pin_value_t gpiohs_get_pin(uint8_t pin); /** * @brief Set Gpiohs pin value @@ -240,7 +232,7 @@ gpio_pin_value_t gpiohs_get_pin_value(size_t pin); * @param[in] pin Gpiohs pin * @param[in] value Gpiohs pin value */ -void gpiohs_set_pin_value(size_t pin, gpio_pin_value_t value); +void gpiohs_set_pin(uint8_t pin, gpio_pin_value_t value); /** * @brief Set Gpiohs pin edge for interrupt @@ -248,7 +240,7 @@ void gpiohs_set_pin_value(size_t pin, gpio_pin_value_t value); * @param[in] pin Gpiohs pin * @param[in] edge Gpiohs pin edge type */ -void gpiohs_set_pin_edge(size_t pin, gpio_pin_edge_t edge); +void gpiohs_set_pin_edge(uint8_t pin, gpio_pin_edge_t edge); /** * @brief Set Gpiohs pin interrupt @@ -257,7 +249,7 @@ void gpiohs_set_pin_edge(size_t pin, gpio_pin_edge_t edge); * @param[in] priority Gpiohs pin interrupt priority * @param[in] func Gpiohs pin interrupt service routine */ -void gpiohs_set_irq(size_t pin, uint32_t priority, void(*func)()); +void gpiohs_set_irq(uint8_t pin, uint32_t priority, void(*func)()); #ifdef __cplusplus } diff --git a/lib/drivers/include/i2c.h b/lib/drivers/include/i2c.h index af65d536..581fdd8b 100644 --- a/lib/drivers/include/i2c.h +++ b/lib/drivers/include/i2c.h @@ -325,13 +325,13 @@ typedef struct _i2c extern volatile i2c_t *const i2c[3]; -typedef enum _i2c_device_num +typedef enum _i2c_device_number { I2C_DEVICE_0, I2C_DEVICE_1, I2C_DEVICE_2, I2C_DEVICE_MAX, -} i2c_device_num_t; +} i2c_device_number_t; typedef enum _i2c_bus_speed_mode { @@ -348,7 +348,7 @@ typedef enum _i2c_bus_speed_mode * @param[in] address_width address width 7bit or 10bit * @param[in] bus_speed_mode i2c rate */ -void i2c_config(i2c_device_num_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode); +void i2c_config(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode); /** * @brief I2c send data @@ -361,7 +361,7 @@ void i2c_config(i2c_device_num_t i2c_num, uint32_t slave_address, uint32_t addre * - 0 Success * - Other Fail */ -int i2c_send_data(i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len); +int i2c_send_data(i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len); /** * @brief I2c send data by dma @@ -375,7 +375,7 @@ int i2c_send_data(i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_l * - 0 Success * - Other Fail */ -int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len); +int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len); /** * @brief I2c receive data @@ -390,7 +390,7 @@ int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_num_t i2 * - 0 Success * - Other Fail */ -int i2c_receive_data(i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len); +int i2c_receive_data(i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len); /** * @brief I2c receive data by dma @@ -408,7 +408,7 @@ int i2c_receive_data(i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_bu * - Other Fail */ int i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - i2c_device_num_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len); + i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len); #ifdef __cplusplus } diff --git a/lib/drivers/include/i2s.h b/lib/drivers/include/i2s.h index b7f59eea..0d7ca67c 100644 --- a/lib/drivers/include/i2s.h +++ b/lib/drivers/include/i2s.h @@ -29,13 +29,13 @@ extern "C" { #define I2S0_SCLK 88 #define I2S0_WS 89 -typedef enum _i2s_device_num +typedef enum _i2s_device_number { I2S_DEVICE_0 = 0, I2S_DEVICE_1 = 1, I2S_DEVICE_2 = 2, I2S_DEVICE_MAX -} i2s_device_num_t; +} i2s_device_number_t; typedef enum _i2s_channel_num { @@ -635,7 +635,7 @@ extern volatile i2s_t *const i2s[3]; * @param[in] device_num the device of i2s * */ -void i2s_device_enable(i2s_device_num_t device_num); +void i2s_device_enable(i2s_device_number_t device_num); /** * @brief Enable or disable i2s device @@ -643,7 +643,7 @@ void i2s_device_enable(i2s_device_num_t device_num); * @param[in] device_num The device of i2s * @param[in] enable Enable flag 0:disable, 1:enable */ -void i2s_dev_enable(i2s_device_num_t device_num, uint32_t enable); +void i2s_dev_enable(i2s_device_number_t device_num, uint32_t enable); /** * @brief Set I2S recive channel enable or disable @@ -656,7 +656,7 @@ void i2s_dev_enable(i2s_device_num_t device_num, uint32_t enable); * - 0 Success * - Other Fail */ -int i2s_receive_channel_enable(i2s_device_num_t device_num, i2s_channel_num_t channel_num, uint32_t enable); +int i2s_receive_channel_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint32_t enable); /** * @brief Set I2S transmit channel enable or disable @@ -669,7 +669,7 @@ int i2s_receive_channel_enable(i2s_device_num_t device_num, i2s_channel_num_t ch * - 0 Success * - Other Fail */ -int i2s_transmit_channel_enable(i2s_device_num_t device_num, i2s_channel_num_t channel_num, uint32_t enable); +int i2s_transmit_channel_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint32_t enable); /** * @brief I2s init @@ -679,7 +679,7 @@ int i2s_transmit_channel_enable(i2s_device_num_t device_num, i2s_channel_num_t c * @param[in] channel_mask Channel mask to which channel work * */ -void i2s_init(i2s_device_num_t device_num, i2s_transmit_t rxtx_mode, uint32_t channel_mask); +void i2s_init(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode, uint32_t channel_mask); /** * @brief Read pcm data from channel_num channel @@ -693,7 +693,7 @@ void i2s_init(i2s_device_num_t device_num, i2s_transmit_t rxtx_mode, uint32_t ch * - 0 Success * - Other Fail */ -int i2s_receive_data(i2s_device_num_t device_num, i2s_channel_num_t channel_num, uint64_t *buf, size_t buf_len); +int i2s_receive_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint64_t *buf, size_t buf_len); /** * @brief Read pcm data from dma @@ -707,7 +707,7 @@ int i2s_receive_data(i2s_device_num_t device_num, i2s_channel_num_t channel_num, * - 0 Success * - Other Fail */ -int i2s_receive_data_dma(i2s_device_num_t device_num, uint32_t *buf, size_t buf_len, dmac_channel_number_t channel_num); +int i2s_receive_data_dma(i2s_device_number_t device_num, uint32_t *buf, size_t buf_len, dmac_channel_number_t channel_num); /** * @brief Write pcm data to channel_num channel @@ -721,7 +721,7 @@ int i2s_receive_data_dma(i2s_device_num_t device_num, uint32_t *buf, size_t buf_ * - 0 Success * - Other Fail */ -int i2s_send_data(i2s_device_num_t device_num, i2s_channel_num_t channel_num, uint8_t *pcm, size_t buf_len, size_t single_length); +int i2s_send_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint8_t *pcm, size_t buf_len, size_t single_length); /** * @brief Write pcm data to channel_num channel by dma, first wait dmac done @@ -732,7 +732,7 @@ int i2s_send_data(i2s_device_num_t device_num, i2s_channel_num_t channel_num, ui * @param[in] channel_num dmac channel * */ -void i2s_send_data_dma(i2s_device_num_t device_num, void *pcm, size_t buf_len, dmac_channel_number_t channel_num); +void i2s_send_data_dma(i2s_device_number_t device_num, void *pcm, size_t buf_len, dmac_channel_number_t channel_num); /** * @brief Write pcm data to channel_num channel by dma @@ -749,7 +749,7 @@ void i2s_send_data_dma(i2s_device_num_t device_num, void *pcm, size_t buf_len, d * - 0 Success * - Other Fail */ -int i2s_play(i2s_device_num_t device_num,dmac_channel_number_t channel_num, uint8_t *buf, size_t buf_len, size_t frame, size_t bits_per_sample, uint8_t track_num); +int i2s_play(i2s_device_number_t device_num,dmac_channel_number_t channel_num, uint8_t *buf, size_t buf_len, size_t frame, size_t bits_per_sample, uint8_t track_num); /** * @brief Send receive data to transmit channel by dma @@ -763,7 +763,7 @@ int i2s_play(i2s_device_num_t device_num,dmac_channel_number_t channel_num, uint * - 0 Success * - Other Fail */ -int i2s_rx_to_tx(i2s_device_num_t device_src_num, i2s_device_num_t device_dest_num, +int i2s_rx_to_tx(i2s_device_number_t device_src_num, i2s_device_number_t device_dest_num, size_t buf_len, dmac_channel_number_t channel_num); /** @@ -780,7 +780,7 @@ int i2s_rx_to_tx(i2s_device_num_t device_src_num, i2s_device_num_t device_dest_n * - 0 Success * - Other Fail */ -int i2s_set_mask_interrupt(i2s_device_num_t device_num, +int i2s_set_mask_interrupt(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint32_t rx_available, uint32_t rx_overrun_int, uint32_t tx_empty_int, uint32_t tx_overrun_int); @@ -795,7 +795,7 @@ int i2s_set_mask_interrupt(i2s_device_num_t device_num, * - 0 Success * - Other Fail */ -int i2s_set_tx_threshold(i2s_device_num_t device_num, +int i2s_set_tx_threshold(i2s_device_number_t device_num, fifo_threshold_t threshold, i2s_channel_num_t channel_num); @@ -810,7 +810,7 @@ int i2s_set_tx_threshold(i2s_device_num_t device_num, * - 0 Success * - Other Fail */ -int i2s_set_rx_threshold(i2s_device_num_t device_num, +int i2s_set_rx_threshold(i2s_device_number_t device_num, fifo_threshold_t threshold, i2s_channel_num_t channel_num); @@ -827,7 +827,7 @@ int i2s_set_rx_threshold(i2s_device_num_t device_num, * - 0 Success * - Other Fail */ -int i2s_master_configure(i2s_device_num_t device_num, +int i2s_master_configure(i2s_device_number_t device_num, word_select_cycles_t word_select_size, sclk_gating_cycles_t gating_cycles, i2s_work_mode_t word_mode); @@ -842,7 +842,7 @@ int i2s_master_configure(i2s_device_num_t device_num, * - 0 Success * - Other Fail */ -int i2s_set_rx_word_length(i2s_device_num_t device_num, +int i2s_set_rx_word_length(i2s_device_number_t device_num, word_length_t word_length, i2s_channel_num_t channel_num); @@ -857,7 +857,7 @@ int i2s_set_rx_word_length(i2s_device_num_t device_num, * - 0 Success * - Other Fail */ -int i2s_set_tx_word_length(i2s_device_num_t device_num, +int i2s_set_tx_word_length(i2s_device_number_t device_num, word_length_t word_length, i2s_channel_num_t channel_num); @@ -876,7 +876,7 @@ int i2s_fpioa_sysctl(void); * @param[in] device_num The device number * @param[in] channel_num The channel number */ -void i2s_receive_enable(i2s_device_num_t device_num, +void i2s_receive_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num); /** @@ -885,7 +885,7 @@ void i2s_receive_enable(i2s_device_num_t device_num, * @param[in] device_num The device number * @param[in] channel_num The channel number */ -void i2s_transimit_enable(i2s_device_num_t device_num, +void i2s_transimit_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num); /** @@ -897,7 +897,7 @@ void i2s_transimit_enable(i2s_device_num_t device_num, * @param[in] word_select_size The word select size * @param[in] trigger_level The trigger level */ -void i2s_rx_channel_configure(i2s_device_num_t device_num, +void i2s_rx_channel_configure(i2s_device_number_t device_num, i2s_channel_num_t channel_num, word_length_t word_length, word_select_cycles_t word_select_size, @@ -913,7 +913,7 @@ void i2s_rx_channel_configure(i2s_device_num_t device_num, * @param[in] word_select_size The word select size * @param[in] trigger_level The trigger level */ -void i2s_tx_channel_configure(i2s_device_num_t device_num, +void i2s_tx_channel_configure(i2s_device_number_t device_num, i2s_channel_num_t channel_num, word_length_t word_length, word_select_cycles_t word_select_size, @@ -926,7 +926,7 @@ void i2s_tx_channel_configure(i2s_device_num_t device_num, * @param[in] device_num The device number * @param[in] rxtx_mode The rxtx mode */ -void i2s_disable_block(i2s_device_num_t device_num, +void i2s_disable_block(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode); /** @@ -939,7 +939,7 @@ void i2s_disable_block(i2s_device_num_t device_num, * 0 Success * Other Fail */ -int i2s_transmit_dma_enable(i2s_device_num_t device_num, uint32_t enable); +int i2s_transmit_dma_enable(i2s_device_number_t device_num, uint32_t enable); /** * @brief Enable I2S receive DMA @@ -951,7 +951,7 @@ int i2s_transmit_dma_enable(i2s_device_num_t device_num, uint32_t enable); * - 0 Success * - Other Fail */ -int i2s_receive_dma_enable(i2s_device_num_t device_num, uint32_t enable); +int i2s_receive_dma_enable(i2s_device_number_t device_num, uint32_t enable); /** * @brief Split I2S transmit DMA from 32bit to two 16bit left and right @@ -963,7 +963,7 @@ int i2s_receive_dma_enable(i2s_device_num_t device_num, uint32_t enable); * - 0 Success * - Other Fail */ -int i2s_transmit_dma_divide(i2s_device_num_t device_num, uint32_t enable); +int i2s_transmit_dma_divide(i2s_device_number_t device_num, uint32_t enable); #ifdef __cplusplus } diff --git a/lib/drivers/include/otp.h b/lib/drivers/include/otp.h deleted file mode 100644 index 7db47574..00000000 --- a/lib/drivers/include/otp.h +++ /dev/null @@ -1,361 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _DRIVER_OTP_H -#define _DRIVER_OTP_H - -#include - -/* clang-format off */ -#define OTP_COMMON_DATA_ADDR 0x00000000U -#define OTP_SYSTEM_DATA_ADDR 0x00003AD0U -#define OTP_BISR_DATA_ADDR 0x00003DD0U -#define OTP_BLOCK_CTL_ADDR 0x00003FD0U -#define OTP_WIRED_REG_ADDR 0x00003FE0U -#define OTP_AES_KEY_ADDR 0x00003FF0U - -#define OTP_BUSY_FLAG 0x00000001U -#define OTP_BYPASS_FLAG 0x00000002U -#define OTP_TEST_FLAG 0x00000004U -/* clang-format on */ - -typedef enum _otp_status -{ - OTP_OK = 0, - OTP_ERROR_TIMEOUT, /* operation timeout*/ - OTP_ERROR_ADDRESS, /* invalid address*/ - OTP_ERROR_WRITE, /* write error*/ - OTP_ERROR_BLANK, /* blank check error*/ - OTP_ERROR_BISR, /* bisr error*/ - OTP_ERROR_TESTDEC, /* testdec error*/ - OTP_ERROR_WRTEST, /* wrtest error*/ - OTP_ERROR_KEYCOMP, /* key is wrong*/ - OTP_ERROR_PARAM, /* param error*/ - OTP_ERROR_NULL, /* undefine error*/ - OTP_BLOCK_NORMAL, /* block can be written*/ - OTP_BLOCK_PROTECTED,/* block can not be written*/ - OTP_FUNC_ENABLE, /* function available*/ - OTP_FUNC_DISABLE, /* function unavailable*/ - OTP_FLAG_SET, /* flag set*/ - OTP_FLAG_UNSET, /* flag unset*/ -} otp_status_t; - -typedef enum _otp_data_block -{ - COMMON_DATA_BLOCK1 = 0, - COMMON_DATA_BLOCK2, - COMMON_DATA_BLOCK3, - COMMON_DATA_BLOCK4, - COMMON_DATA_BLOCK5, - COMMON_DATA_BLOCK6, - COMMON_DATA_BLOCK7, - COMMON_DATA_BLOCK8, - COMMON_DATA_BLOCK9, - COMMON_DATA_BLOCK10, - COMMON_DATA_BLOCK11, - COMMON_DATA_BLOCK12, - COMMON_DATA_BLOCK13, - COMMON_DATA_BLOCK14, - COMMON_DATA_BLOCK15, - DATA_BLOCK_RESERVE, - SYSTEM_DATA_BLOCK1, - SYSTEM_DATA_BLOCK2, - SYSTEM_DATA_BLOCK3, - SYSTEM_DATA_BLOCK4, - SYSTEM_DATA_BLOCK5, - SYSTEM_DATA_BLOCK6, - SYSTEM_DATA_BLOCK7, - SYSTEM_DATA_BLOCK8, - SYSTEM_DATA_BLOCK9, - SYSTEM_DATA_BLOCK10, - SYSTEM_DATA_BLOCK11, - SYSTEM_DATA_BLOCK12, - SYSTEM_DATA_BLOCK13, - SYSTEM_DATA_BLOCK14, - SYSTEM_DATA_BLOCK15, - SYSTEM_DATA_BLOCK16, - SYSTEM_DATA_BLOCK17, - SYSTEM_DATA_BLOCK18, - SYSTEM_DATA_BLOCK19, - SYSTEM_DATA_BLOCK20, - SYSTEM_DATA_BLOCK21, - SYSTEM_DATA_BLOCK22, - SYSTEM_DATA_BLOCK23, - SYSTEM_DATA_BLOCK24, - SYSTEM_DATA_BLOCK25, - SYSTEM_DATA_BLOCK26, - SYSTEM_DATA_BLOCK27, - SYSTEM_DATA_BLOCK28, - SYSTEM_DATA_BLOCK29, - SYSTEM_DATA_BLOCK30, - SYSTEM_DATA_BLOCK31, - SYSTEM_DATA_BLOCK32, - SYSTEM_DATA_BLOCK33, - SYSTEM_DATA_BLOCK34, - SYSTEM_DATA_BLOCK35, - SYSTEM_DATA_BLOCK36, - SYSTEM_DATA_BLOCK37, - SYSTEM_DATA_BLOCK38, - SYSTEM_DATA_BLOCK39, - SYSTEM_DATA_BLOCK40, - SYSTEM_DATA_BLOCK41, - SYSTEM_DATA_BLOCK42, - SYSTEM_DATA_BLOCK43, - SYSTEM_DATA_BLOCK44, - SYSTEM_DATA_BLOCK45, - SYSTEM_DATA_BLOCK46, - SYSTEM_DATA_BLOCK47, - SYSTEM_DATA_BLOCK48, - DATA_BLOCK_MAX = 64, -} otp_data_block_t; - -typedef enum _otp_func_reg -{ - BLANK_TEST_DISABLE = 0, - RAM_BISR_DISABLE, - AES_WRITE_DISABLE, - AES_VERIFY_DISABLE, - JTAG_DISABLE, - TEST_EN_DISABLE = 6, - ISP_DISABLE, - OTP_FUNC_FIRMWARE_CIPHER_DISABLE, - FUNC_REG_MAX = 64, -} otp_func_reg_t; - -typedef struct _otp -{ - volatile uint32_t otp_ceb; - volatile uint32_t otp_test_mode; - volatile uint32_t otp_mode; - volatile uint32_t gb_otp_en; - volatile uint32_t dat_in_finish; - volatile uint32_t otp_bisr_fail; - volatile uint32_t test_step; - volatile uint32_t otp_pwrrdy; - volatile uint32_t otp_last_dat; - volatile uint32_t otp_data; - volatile uint32_t otp_pwr_mode; - volatile uint32_t otp_in_dat; - volatile uint32_t otp_apb_adr; - volatile uint32_t td_result; - volatile uint32_t data_acp_flag; - volatile uint32_t otp_adr_in_flag; - volatile uint32_t wr_result; - volatile uint32_t otp_thershold; - volatile uint32_t bisr_finish; - volatile uint32_t key_cmp_result; - volatile uint32_t otp_cmp_key; - volatile uint32_t cmp_result_rdy; - volatile uint32_t otp_cle; - volatile uint32_t data_blk_ctrl; - volatile uint32_t otp_wrg_adr_flag; - volatile uint32_t pro_wrong; - volatile uint32_t otp_status; - volatile uint32_t otp_pro_adr; - volatile uint32_t blank_finish; - volatile uint32_t bisr2otp_en; - volatile uint32_t otp_cpu_ctrl; - volatile uint32_t otp_web_cpu; - volatile uint32_t otp_rstb_cpu; - volatile uint32_t otp_seltm_cpu; - volatile uint32_t otp_readen_cpu; - volatile uint32_t otp_pgmen_cpu; - volatile uint32_t otp_dle_cpu; - volatile uint32_t otp_din_cpu; - volatile uint32_t otp_cpumpen_cpu; - volatile uint32_t otp_cle_cpu; - volatile uint32_t otp_ceb_cpu; - volatile uint32_t otp_adr_cpu; - volatile uint32_t otp_dat_cpu; - volatile uint32_t otp_data_rdy; - volatile uint32_t block_flag_high; - volatile uint32_t block_flag_low; - volatile uint32_t reg_flag_high; - volatile uint32_t reg_flag_low; -} __attribute__((packed, aligned(4))) otp_t; - -/** - * @brief Init OTP - * - * @note The otp clock frequency is 12.5M by default - * - * @param[in] div bus_clk / otp_clk - */ -void otp_init(uint8_t div); - -/** - * @brief Enable otp test mode - */ -void otp_test_enable(void); - -/** - * @brief Disable otp test mode - */ -void otp_test_disable(void); - -/** - * @brief Enable key output to aes - */ -void otp_key_output_enable(void); - -/** - * @brief Disable key output to aes - */ -void otp_key_output_disable(void); - -/** - * @brief Get the wrong address when programming fails - * - * @return The wrong address - */ -uint32_t otp_wrong_address_get(void); - -/** - * @brief Get OTP status - * - * @param[in] flag status flag - * - * @return Results of the operation - */ -otp_status_t otp_status_get(uint32_t flag); - -/** - * @brief Perform the blank check operation - * - * @return Results of the operation - */ -otp_status_t otp_blank_check(void); - -/** - * @brief Perform the testdec operation - * - * @return Results of the operation - */ -otp_status_t otp_testdec(void); - -/** - * @brief Perform the wrtest operation - * - * @return Results of the operation - */ -otp_status_t otp_wrtest(void); - -/** - * @brief Write data - * - * @param[in] addr Start programming address(bit) - * @param[in] data_buf Need to write the data point - * @param[in] length Need to write the data length(bit) - * - * @return Results of the operation - */ -otp_status_t otp_write_data(uint32_t addr, uint8_t *data_buf, uint32_t length); - -/** - * @brief Read data - * - * @param[in] addr Start read address(bit). - * @param[in] data_buf Need to read the data point - * @param[in] length Need to read the data length(bit) - * - * @return Results of the operation - */ -otp_status_t otp_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length); - -/** - * @brief Write the key - * - * @param[in] data_buf The key data,length is 128 bits(4 words) - * - * @return Results of the operation - */ -otp_status_t otp_key_write(uint8_t *data_buf); - -/** - * @brief Compare the key - * - * @param[in] data_buf The key data,length is 128 bits(4 words) - * - * @return Results of the operation - */ -otp_status_t otp_key_compare(uint8_t *data_buf); - -/** - * @brief Data block write protect - * - * @param[in] block Need to write a protected data block - * - * @return Results of the operation - */ -otp_status_t otp_data_block_protect_set(otp_data_block_t block); - -/** - * @brief Disable the specified function - * - * @param[in] reg Need to disable the function - * - * @return Results of the operation - */ -otp_status_t otp_func_reg_disable_set(otp_func_reg_t func); - -/** - * @brief Get the data block status - * - * @param[in] block The specified data block - * - * @return Results of the operation - */ -otp_status_t otp_data_block_protect_get(otp_data_block_t block); - -/** - * @brief Get the function status - * - * @param[in] reg The specified function - * - * @return Results of the operation - */ -otp_status_t otp_func_reg_disable_get(otp_func_reg_t func); - -/** - * @brief Refresh the data block status - * - * @param[in] block The specified data block - * - * @return Results of the operation - */ -otp_status_t otp_data_block_protect_refresh(otp_data_block_t block); - -/** - * @brief Write data(bypass mode) - * - * @param[in] addr Start programming address(bit) - * @param[in] data_buf Need to write the data point - * @param[in] length Need to write the data length(bit) - * - * @return Results of the operation - */ -otp_status_t otp_soft_write(uint32_t addr, uint8_t *data_buf, uint32_t length); - -/** - * @brief Read data(bypass mode) - * - * @param[in] addr Start read address(bit).Be sure to align 16 bits - * @param[in] data_buf Need to read the data point - * @param[in] length Need to read the data length(half word/16bits) - * - * @return Results of the operation - */ -otp_status_t otp_soft_read(uint32_t addr, uint8_t *data_buf, uint32_t length); - -#endif diff --git a/lib/drivers/include/pwm.h b/lib/drivers/include/pwm.h new file mode 100644 index 00000000..e1318d29 --- /dev/null +++ b/lib/drivers/include/pwm.h @@ -0,0 +1,57 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef _DRIVER_PWM_H +#define _DRIVER_PWM_H + +#include +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Init pwm timer + * + * @param[in] timer timer + */ +void pwm_init(uint32_t tim); + +/** + * @brief Enable timer + * + * @param[in] timer timer + * @param[in] channel channel + * @param[in] enable Enable or disable + * + */ +void pwm_set_enable(uint32_t timer, uint32_t channel, int enable); + +/** + * @brief Set pwm duty + * + * @param[in] timer timer + * @param[in] channel channel + * @param[in] frequency pwm frequency + * @param[in] duty duty + * + */ +double pwm_set_frequency(uint32_t timer, uint32_t channel, double frequency, double duty); + + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_PWM_H */ diff --git a/lib/drivers/include/rtc.h b/lib/drivers/include/rtc.h index 6dad0375..37bacdcb 100644 --- a/lib/drivers/include/rtc.h +++ b/lib/drivers/include/rtc.h @@ -29,8 +29,6 @@ extern "C" { #endif -typedef struct tm tm; - /** * @brief RTC timer mode * @@ -351,16 +349,17 @@ typedef struct _rtc */ extern volatile rtc_t *const rtc; extern volatile uint32_t *const rtc_base; + /** - * @brief Set RTC timer mode + * @brief RTC timer set mode * - * @param[in] timer_mode The timer mode + * @param timer_mode timer mode * - * @return result + * @return Result * - 0 Success * - Other Fail */ -int rtc_timer_mode_set(rtc_timer_mode_t timer_mode); +int rtc_timer_set_mode(rtc_timer_mode_t timer_mode); /** * @brief Get RTC timer mode @@ -378,14 +377,14 @@ rtc_timer_mode_t rtc_timer_get_mode(void); * - 0 Success * - Other Fail */ -int rtc_timer_set_tm(const tm *tm); +int rtc_timer_set_tm(const struct tm *tm); /** * @brief Get date time from RTC * * @return The Broken-down date time */ -tm *rtc_timer_get_tm(void); +struct tm *rtc_timer_get_tm(void); /** * @brief Set date time to Alarm @@ -396,14 +395,14 @@ tm *rtc_timer_get_tm(void); * - 0 Success * - Other Fail */ -int rtc_timer_set_alarm_tm(const tm *tm); +int rtc_timer_set_alarm_tm(const struct tm *tm); /** * @brief Get date time from Alarm * * @return The Broken-down date time */ -tm *rtc_timer_get_alarm_tm(void); +struct tm *rtc_timer_get_alarm_tm(void); /** * @brief Check if it is a leap year @@ -588,17 +587,6 @@ rtc_mask_t rtc_alarm_interrupt_mask_get(void); */ int rtc_init(void); -/** - * @brief RTC timer set mode - * - * @param timer_mode timer mode - * - * @return Result - * - 0 Success - * - Other Fail - */ -int rtc_timer_set_mode(rtc_timer_mode_t timer_mode); - #ifdef __cplusplus } #endif diff --git a/lib/drivers/include/spi.h b/lib/drivers/include/spi.h index 6d893708..d0ddb439 100644 --- a/lib/drivers/include/spi.h +++ b/lib/drivers/include/spi.h @@ -109,13 +109,13 @@ typedef enum _spi_device_num SPI_DEVICE_MAX, } spi_device_num_t; -typedef enum _spi_mode +typedef enum _spi_work_mode { SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3, -} spi_mode_t; +} spi_work_mode_t; typedef enum _spi_frame_format { @@ -151,9 +151,9 @@ typedef enum _spi_transfer_width extern volatile spi_t *const spi[4]; /** - * @brief Spi master mode configuration + * @brief Set spi configuration * - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] mode Spi mode * @param[in] frame_format Spi frame format * @param[in] data_bit_length Spi data bit length @@ -162,26 +162,25 @@ extern volatile spi_t *const spi[4]; * - 0 Success * - Other Fail */ -int spi_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame_format, - size_t data_bit_length); +int spi_config(spi_device_num_t spi_num, spi_work_mode_t mode, spi_frame_format_t frame_format, size_t data_bit_length); /** - * @brief Spi transmit configuration + * @brief Set multiline configuration * - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] instruction_length Instruction length * @param[in] address_length Address length * @param[in] wait_cycles Wait cycles * @param[in] trans_mode Spi transfer mode * */ -void spi_config_non_standard(uint8_t spi_bus, size_t instruction_length, size_t address_length, +void spi_config_non_standard(spi_device_num_t spi_num, size_t instruction_length, size_t address_length, size_t wait_cycles, spi_addr_inst_trans_mode_t trans_mode); /** * @brief Spi send data * - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] chip_sel Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length @@ -192,13 +191,13 @@ void spi_config_non_standard(uint8_t spi_bus, size_t instruction_length, size_t * - 0 Success * - Other Fail */ -int spi_send_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); +int spi_send_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** * @brief Spi receive data * - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] chip_sel Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length @@ -209,13 +208,13 @@ int spi_send_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff * - 0 Success * - Other Fail */ -int spi_receive_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +int spi_receive_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special receive data * - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] chip_sel Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length @@ -226,12 +225,12 @@ int spi_receive_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_b * - 0 Success * - Other Fail */ -int spi_receive_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +int spi_receive_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special send data * - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] chip_sel Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length @@ -242,13 +241,13 @@ int spi_receive_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_ * - 0 Success * - Other Fail */ -int spi_send_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); +int spi_send_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** * @brief Spi send data by dma * * @param[in] channel_num Dmac channel number - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] chip_sel Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length @@ -259,7 +258,7 @@ int spi_send_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buf * - 0 Success * - Other Fail */ -int spi_send_data_standard_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, +int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); @@ -268,7 +267,7 @@ int spi_send_data_standard_dma(dmac_channel_number_t channel_num, uint8_t spi_bu * * @param[in] w_channel_num Dmac write channel number * @param[in] r_channel_num Dmac read channel number - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] chip_sel Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length @@ -279,15 +278,15 @@ int spi_send_data_standard_dma(dmac_channel_number_t channel_num, uint8_t spi_bu * - 0 Success * - Other Fail */ -int spi_receive_data_standard_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, - uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, + spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special send data by dma * * @param[in] channel_num Dmac channel number - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] chip_sel Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length @@ -298,7 +297,7 @@ int spi_receive_data_standard_dma(dmac_channel_number_t channel_num_w, dmac_chan * - 0 Success * - Other Fail */ -int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, +int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** @@ -306,7 +305,7 @@ int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,uint8_t spi_bus * * @param[in] w_channel_num Dmac write channel number * @param[in] r_channel_num Dmac read channel number - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] chip_sel Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length @@ -317,14 +316,14 @@ int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,uint8_t spi_bus * - 0 Success * - Other Fail */ -int spi_receive_data_multiple_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, - uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, + spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi fill dma * * @param[in] channel_num Dmac channel number - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] chip_sel Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length @@ -333,13 +332,13 @@ int spi_receive_data_multiple_dma(dmac_channel_number_t channel_num_w, dmac_chan * - 0 Success * - Other Fail */ -int spi_fill_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len); +int spi_fill_data_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len); /** * @brief Spi normal send by dma * * @param[in] channel_num Dmac channel number - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] chip_sel Spi chip select * @param[in] tx_buff Spi transmit buffer point * @param[in] tx_len Spi transmit buffer length @@ -349,18 +348,18 @@ int spi_fill_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chi * - 0 Success * - Other Fail */ -int spi_send_data_normal_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, +int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, uint32_t chip_sel, void *tx_buff, size_t tx_len, spi_transfer_width_t stw); /** * @brief Spi normal send by dma * - * @param[in] spi_bus Spi bus number + * @param[in] spi_num Spi bus number * @param[in] spi_clk Spi clock rate * * @return The real spi clock rate */ -uint32_t spi_set_clk_rate(uint8_t spi_bus, uint32_t spi_clk); +uint32_t spi_set_clk_rate(spi_device_num_t spi_num, uint32_t spi_clk); #ifdef __cplusplus } diff --git a/lib/drivers/include/sysclock.h b/lib/drivers/include/sysclock.h deleted file mode 100644 index b2734a29..00000000 --- a/lib/drivers/include/sysclock.h +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _SYS_CLOCK_H -#define _SYS_CLOCK_H -#include "stdint.h" - -#define PLL0_OUTPUT_FREQ 320000000UL -#define PLL1_OUTPUT_FREQ 160000000UL -#define PLL2_OUTPUT_FREQ 45158400UL -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Init PLL freqency - */ -void sys_clock_init(); - -/** - * @brief Set frequency of CPU - * @param[in] frequency The desired frequency in Hz - * - * @return The actual frequency of CPU after set - */ -uint32_t system_set_cpu_frequency(uint32_t frequency); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/drivers/include/sysctl.h b/lib/drivers/include/sysctl.h index 45b0bd88..2e6e87ff 100644 --- a/lib/drivers/include/sysctl.h +++ b/lib/drivers/include/sysctl.h @@ -64,15 +64,15 @@ extern "C" { * */ -typedef enum _sysctl_pll_e +typedef enum _sysctl_pll_t { SYSCTL_PLL0, SYSCTL_PLL1, SYSCTL_PLL2, SYSCTL_PLL_MAX -} sysctl_pll_e; +} sysctl_pll_t; -typedef enum _sysctl_clock_source_e +typedef enum _sysctl_clock_source_t { SYSCTL_SOURCE_IN0, SYSCTL_SOURCE_PLL0, @@ -80,9 +80,9 @@ typedef enum _sysctl_clock_source_e SYSCTL_SOURCE_PLL2, SYSCTL_SOURCE_ACLK, SYSCTL_SOURCE_MAX -} sysctl_clock_source_e; +} sysctl_clock_source_t; -typedef enum _sysctl_dma_channel_e +typedef enum _sysctl_dma_channel_t { SYSCTL_DMA_CHANNEL_0, SYSCTL_DMA_CHANNEL_1, @@ -91,9 +91,9 @@ typedef enum _sysctl_dma_channel_e SYSCTL_DMA_CHANNEL_4, SYSCTL_DMA_CHANNEL_5, SYSCTL_DMA_CHANNEL_MAX -} sysctl_dma_channel_e; +} sysctl_dma_channel_t; -typedef enum _sysctl_dma_select_e +typedef enum _sysctl_dma_select_t { SYSCTL_DMA_SELECT_SSI0_RX_REQ, SYSCTL_DMA_SELECT_SSI0_TX_REQ, @@ -129,12 +129,12 @@ typedef enum _sysctl_dma_select_e SYSCTL_DMA_SELECT_I2S0_BF_DIR_REQ, SYSCTL_DMA_SELECT_I2S0_BF_VOICE_REQ, SYSCTL_DMA_SELECT_MAX -} sysctl_dma_select_e; +} sysctl_dma_select_t; /** * @brief System controller clock id */ -typedef enum _sysctl_clock_e +typedef enum _sysctl_clock_t { SYSCTL_CLOCK_PLL0, SYSCTL_CLOCK_PLL1, @@ -177,12 +177,12 @@ typedef enum _sysctl_clock_e SYSCTL_CLOCK_ACLK = 40, SYSCTL_CLOCK_HCLK, SYSCTL_CLOCK_MAX -} sysctl_clock_e; +} sysctl_clock_t; /** * @brief System controller clock select id */ -typedef enum _sysctl_clock_select_e +typedef enum _sysctl_clock_select_t { SYSCTL_CLOCK_SELECT_PLL0_BYPASS, SYSCTL_CLOCK_SELECT_PLL1_BYPASS, @@ -195,12 +195,12 @@ typedef enum _sysctl_clock_select_e SYSCTL_CLOCK_SELECT_TIMER2, SYSCTL_CLOCK_SELECT_SPI3_SAMPLE, SYSCTL_CLOCK_SELECT_MAX = 11 -} sysctl_clock_select_e; +} sysctl_clock_select_t; /** * @brief System controller clock threshold id */ -typedef enum _sysctl_threshold_e +typedef enum _sysctl_threshold_t { SYSCTL_THRESHOLD_ACLK, SYSCTL_THRESHOLD_APB0, @@ -230,7 +230,7 @@ typedef enum _sysctl_threshold_e SYSCTL_THRESHOLD_WDT0, SYSCTL_THRESHOLD_WDT1, SYSCTL_THRESHOLD_MAX = 28 -} sysctl_threshold_e; +} sysctl_threshold_t; /** * @brief System controller reset control id @@ -273,7 +273,7 @@ typedef enum _io_power_mode { POWER_V33, POWER_V18 -} io_power_mode_t; +} sysctl_io_power_mode_t; /** * @brief Git short commit id @@ -833,7 +833,7 @@ extern volatile sysctl_t *const sysctl; * - 0 Success * - Other Fail */ -int sysctl_clock_enable(sysctl_clock_e clock); +int sysctl_clock_tnable(sysctl_clock_t clock); /** * @brief Enable clock for peripheral @@ -844,7 +844,7 @@ int sysctl_clock_enable(sysctl_clock_e clock); * - 0 Success * - Other Fail */ -int sysctl_clock_disable(sysctl_clock_e clock); +int sysctl_clock_disable(sysctl_clock_t clock); /** * @brief Sysctl clock set threshold @@ -856,7 +856,7 @@ int sysctl_clock_disable(sysctl_clock_e clock); * - 0 Success * - Other Fail */ -int sysctl_clock_set_threshold(sysctl_threshold_e which, int threshold); +int sysctl_clock_set_threshold(sysctl_threshold_t which, int threshold); /** * @brief Sysctl clock get threshold @@ -867,7 +867,7 @@ int sysctl_clock_set_threshold(sysctl_threshold_e which, int threshold); * - Other Value of threshold * - -1 Fail */ -int sysctl_clock_get_threshold(sysctl_threshold_e which); +int sysctl_clock_get_threshold(sysctl_threshold_t which); /** * @brief Sysctl clock set clock select @@ -879,7 +879,7 @@ int sysctl_clock_get_threshold(sysctl_threshold_e which); * - 0 Success * - Other Fail */ -int sysctl_clock_set_clock_select(sysctl_clock_select_e which, int select); +int sysctl_clock_set_clock_select(sysctl_clock_select_t which, int select); /** * @brief Sysctl clock get clock select @@ -890,7 +890,7 @@ int sysctl_clock_set_clock_select(sysctl_clock_select_e which, int select); * - Other Value of clock select * - -1 Fail */ -int sysctl_clock_get_clock_select(sysctl_clock_select_e which); +int sysctl_clock_get_clock_select(sysctl_clock_select_t which); /** * @brief Get clock source frequency @@ -899,7 +899,7 @@ int sysctl_clock_get_clock_select(sysctl_clock_select_e which); * * @return The frequency of clock source */ -uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_e input); +uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_t input); /** * @brief Get PLL frequency @@ -908,7 +908,7 @@ uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_e input); * * @return The frequency of PLL */ -uint32_t sysctl_pll_get_freq(sysctl_pll_e pll); +uint32_t sysctl_pll_get_freq(sysctl_pll_t pll); /** * @brief Set PLL frequency and input clock @@ -919,7 +919,7 @@ uint32_t sysctl_pll_get_freq(sysctl_pll_e pll); * * @return The frequency of PLL */ -uint32_t sysctl_pll_set_freq(sysctl_pll_e pll, sysctl_clock_source_e source, uint32_t freq); +uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uint32_t freq); /** * @brief Get base clock frequency by clock id @@ -928,7 +928,7 @@ uint32_t sysctl_pll_set_freq(sysctl_pll_e pll, sysctl_clock_source_e source, uin * * @return The clock frequency */ -uint32_t sysctl_clock_get_freq(sysctl_clock_e clock); +uint32_t sysctl_clock_get_freq(sysctl_clock_t clock); /** * @brief Reset device by reset controller @@ -960,7 +960,7 @@ uint32_t sysctl_get_freq(void); * - 1 Pll is lock * - 0 Pll have lost lock */ -int sysctl_pll_is_lock(sysctl_pll_e pll); +int sysctl_pll_is_lock(sysctl_pll_t pll); /** * @brief Clear pll lock status @@ -971,7 +971,7 @@ int sysctl_pll_is_lock(sysctl_pll_e pll); * - 0 Success * - Other Fail */ -int sysctl_pll_clear_slip(sysctl_pll_e pll); +int sysctl_pll_clear_slip(sysctl_pll_t pll); /** * @brief Enable the PLL and power on with reset @@ -982,7 +982,7 @@ int sysctl_pll_clear_slip(sysctl_pll_e pll); * - 0 Success * - Other Fail */ -int sysctl_pll_enable(sysctl_pll_e pll); +int sysctl_pll_tnable(sysctl_pll_t pll); /** * @brief Disable the PLL and power off @@ -993,7 +993,7 @@ int sysctl_pll_enable(sysctl_pll_e pll); * - 0 Success * - Other Fail */ -int sysctl_pll_disable(sysctl_pll_e pll); +int sysctl_pll_disable(sysctl_pll_t pll); /** * @brief Select DMA channel handshake peripheral signal @@ -1005,7 +1005,7 @@ int sysctl_pll_disable(sysctl_pll_e pll); * - 0 Success * - Other Fail */ -int sysctl_dma_select(sysctl_dma_channel_e channel, sysctl_dma_select_e select); +int sysctl_dma_select(sysctl_dma_channel_t channel, sysctl_dma_select_t select); /** * @brief Fast set all PLL and CPU clock @@ -1037,7 +1037,20 @@ uint32_t sysctl_spi0_dvp_data_set(uint8_t en); * - 0 Success * - Other Fail */ -uint32_t sysctl_power_mode_sel(uint8_t power_bank, io_power_mode_t io_power_mode); +uint32_t sysctl_power_mode_sel(uint8_t power_bank, sysctl_io_power_mode_t io_power_mode); + +/** + * @brief Set frequency of CPU + * @param[in] frequency The desired frequency in Hz + * + * @return The actual frequency of CPU after set + */ +uint32_t sysctl_set_cpu_frequency(uint32_t frequency); + +/** + * @brief Init PLL freqency + */ +void sysctl_set_pll_frequency(uint64_t pll0, uint64_t pll1, uint64_t pll2); #ifdef __cplusplus } diff --git a/lib/drivers/include/timer.h b/lib/drivers/include/timer.h index b43850d5..36d00535 100644 --- a/lib/drivers/include/timer.h +++ b/lib/drivers/include/timer.h @@ -54,6 +54,23 @@ typedef struct _kendryte_timer volatile uint32_t load_count2[4]; } __attribute__((packed, aligned(4))) kendryte_timer_t; +typedef enum _timer_deivce_number +{ + TIMER_DEVICE_0, + TIMER_DEVICE_1, + TIMER_DEVICE_2, + TIMER_DEVICE_MAX, +} timer_device_number_t; + +typedef enum _timer_channel_number +{ + TIMER_CHANNEL_0, + TIMER_CHANNEL_1, + TIMER_CHANNEL_2, + TIMER_CHANNEL_3, + TIMER_CHANNEL_MAX, +} timer_channel_number_t; + /* TIMER Control Register */ #define TIMER_CR_ENABLE 0x00000001 #define TIMER_CR_MODE_MASK 0x00000002 @@ -65,162 +82,6 @@ typedef struct _kendryte_timer extern volatile kendryte_timer_t *const timer[3]; -/** - * @brief Set timer clock frequency - * - * @param[in] timer timer - * @param[in] div clock divide value - */ -void timer_set_clock_div(uint32_t timer, uint32_t div); - -/** - * @brief Enable timer channel - * - * @param[in] timer timer - * @param[in] channel channel - */ -void timer_enable(uint32_t timer, uint32_t channel); - -/** - * @brief Disable timer channel - * - * @param[in] timer timer - * @param[in] channel channel - */ -void timer_disable(uint32_t timer, uint32_t channel); - -/** - * @brief Enable timer channel PWM - * - * @param[in] timer timer - * @param[in] channel channel - */ -void timer_enable_pwm(uint32_t timer, uint32_t channel); - -/** - * @brief Disable timer channel PWM - * - * @param[in] timer timer - * @param[in] channel channel - */ -void timer_disable_pwm(uint32_t timer, uint32_t channel); - -/** - * @brief Enable timer channel interrupt - * - * @param[in] timer timer - * @param[in] channel channel - */ -void timer_enable_interrupt(uint32_t timer, uint32_t channel); - -/** - * @brief Disable timer channel interrupt - * - * @param[in] timer timer - * @param[in] channel channel - */ -void timer_disable_interrupt(uint32_t timer, uint32_t channel); - -/** - * @brief Set timer channel mode - * - * @param[in] timer timer - * @param[in] channel channel - * @param[in] mode mode - */ -void timer_set_mode(uint32_t timer, uint32_t channel, uint32_t mode); - -/** - * @brief Set timer channel reload value - * - * @param[in] timer timer - * @param[in] channel channel - * @param[in] count count - */ -void timer_set_reload(uint32_t timer, uint32_t channel, uint32_t count); - -/** - * @brief Set timer channel reload value2 - * - * @param[in] timer timer - * @param[in] channel channel - * @param[in] count count - */ -void timer_set_reload2(uint32_t timer, uint32_t channel, uint32_t count); - -/** - * @brief Get timer channel count - * - * @param[in] timer timer - * @param[in] channel channel - * - * @return current value - */ -uint32_t timer_get_count(uint32_t timer, uint32_t channel); - -/** - * @brief Get timer channel reload value - * - * @param[in] timer timer - * @param[in] channel channel - * - * @return reload value - */ -uint32_t timer_get_reload(uint32_t timer, uint32_t channel); - -/** - * @brief Get timer channel reload value2 - * - * @param[in] timer timer - * @param[in] channel channel - * - * @return reload value2 - */ -uint32_t timer_get_reload2(uint32_t timer, uint32_t channel); - -/** - * @brief Get timer interrupt status - * - * @param[in] timer timer - * - * @return interrupt status - */ -uint32_t timer_get_interrupt_status(uint32_t timer); - -/** - * @brief Get timer raw interrupt status - * - * @param[in] timer timer - * - * @return raw interrupt status - */ -uint32_t timer_get_raw_interrupt_status(uint32_t timer); - -/** - * @brief Get timer interrupt status - * - * @param[in] timer timer - * @param[in] channel channel - * - * @return interrupt status - */ -uint32_t timer_channel_get_interrupt_status(uint32_t timer, uint32_t channel); - -/** - * @brief Clear interrupt - * - * @param[in] timer timer - */ -void timer_clear_interrupt(uint32_t timer); - -/** - * @brief Clear interrupt - * - * @param[in] timer timer - * @param[in] channel channel - */ -void timer_channel_clear_interrupt(uint32_t timer, uint32_t channel); - /** * @brief Set timer timeout @@ -231,14 +92,14 @@ void timer_channel_clear_interrupt(uint32_t timer, uint32_t channel); * * @return the real timeout */ -size_t timer_set_interval(uint32_t timer, uint32_t channel, size_t nanoseconds); +size_t timer_set_interval(timer_device_number_t timer, timer_channel_number_t channel, size_t nanoseconds); /** * @brief Init timer * * @param[in] timer timer */ -void timer_init(uint32_t timer); +void timer_init(timer_device_number_t timer); /** * @brief Set timer timeout function @@ -249,17 +110,7 @@ void timer_init(uint32_t timer); * @param[in] priority interrupt priority * */ -void timer_set_irq(uint32_t timer, uint32_t channel, void(*func)(), uint32_t priority); - -/** - * @brief Enable timer - * - * @param[in] timer timer - * @param[in] channel channel - * @param[in] enable Enable or disable - * - */ -void timer_set_enable(uint32_t timer, uint32_t channel, uint32_t enable); +void timer_set_irq(timer_device_number_t timer, timer_channel_number_t channel, void(*func)(), uint32_t priority); /** * @brief Enable timer @@ -269,19 +120,7 @@ void timer_set_enable(uint32_t timer, uint32_t channel, uint32_t enable); * @param[in] enable Enable or disable * */ -void pwm_set_enable(uint32_t timer, uint32_t channel, int enable); - -/** - * @brief Set pwm duty - * - * @param[in] timer timer - * @param[in] channel channel - * @param[in] frequency pwm frequency - * @param[in] duty duty - * - */ -double pwm_set_frequency(uint32_t timer, uint32_t channel, double frequency, double duty); - +void timer_set_enable(timer_device_number_t timer, timer_channel_number_t channel, uint32_t enable); #ifdef __cplusplus } diff --git a/lib/drivers/include/uarths.h b/lib/drivers/include/uarths.h index a8015da4..a2dd3807 100644 --- a/lib/drivers/include/uarths.h +++ b/lib/drivers/include/uarths.h @@ -179,7 +179,7 @@ extern volatile uarths_t *const uarths; * - 0 Success * - Other Fail */ -int uart_init(); +int uarths_init(void); /** * @brief Put a char to UART @@ -192,7 +192,7 @@ int uart_init(); * - 0 Success * - Other Fail */ -int uart_putchar(char c); +int uarths_putchar(char c); /** * @brief Send a string to UART @@ -205,7 +205,7 @@ int uart_putchar(char c); * - 0 Success * - Other Fail */ -int uart_puts(const char *s); +int uarths_puts(const char *s); /** @@ -213,7 +213,7 @@ int uart_puts(const char *s); * * @return byte as int type from UART */ -int uart_getc(void); +int uarths_getc(void); #ifdef __cplusplus diff --git a/lib/drivers/include/common.h b/lib/drivers/include/utils.h similarity index 99% rename from lib/drivers/include/common.h rename to lib/drivers/include/utils.h index a72122ab..ae2af7b9 100644 --- a/lib/drivers/include/common.h +++ b/lib/drivers/include/utils.h @@ -12,8 +12,8 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef _DRIVER_COMMON_H -#define _DRIVER_COMMON_H +#ifndef _DRIVER_UTILS_H +#define _DRIVER_UTILS_H #ifdef __cplusplus #include diff --git a/lib/drivers/include/wdt.h b/lib/drivers/include/wdt.h index bfdb0ad3..3a02f31e 100644 --- a/lib/drivers/include/wdt.h +++ b/lib/drivers/include/wdt.h @@ -60,6 +60,13 @@ typedef struct _wdt volatile uint32_t comp_type; } __attribute__((packed, aligned(4))) wdt_t; +typedef enum _wdt_device_number +{ + WDT_DEVICE_0, + WDT_DEVICE_1, + WDT_DEVICE_MAX, +} wdt_device_number_t; + #define WDT_RESET_ALL 0x00000000U #define WDT_RESET_CPU 0x00000001U @@ -112,41 +119,10 @@ typedef struct _wdt #define WDT_COMP_TYPE_MASK 0xFFFFFFFFU /* clang-format on */ -/** - * @brief WDT object instanse - */ -extern volatile wdt_t *const wdt[2]; - -/** - * @brief Enable wdt - * - * @param[in] id Wdt id 0 or 1 - * - */ -static void wdt_enable(uint8_t id); - -/** - * @brief Response to wdt timeouted - * - * @param[in] id Wdt id 0 or 1 - * @param[in] mode Set wdt reseponse mode - * - */ -static void wdt_response_mode(uint8_t id, uint8_t mode); - -/** - * @brief Set wdt timeout - * - * @param[in] id Wdt id 0 or 1 - * @param[in] timeout Wdt trigger time - * - */ -static void wdt_set_timeout(uint8_t id, uint8_t timeout); - /** * @brief Feed wdt */ -void wdt_feed(uint8_t id); +void wdt_feed(wdt_device_number_t id); /** * @brief Clear wdt interrupt @@ -154,16 +130,16 @@ void wdt_feed(uint8_t id); * @param[in] id Wdt id 0 or 1 * */ -void wdt_clear_interrupt(uint8_t id); +void wdt_clear_interrupt(wdt_device_number_t id); /** * @brief Start wdt * * @param[in] id Wdt id 0 or 1 - * @param[in] toms Wdt trigger time + * @param[in] time_out_ms Wdt trigger time * */ -int wdt_start(uint8_t id, uint64_t toms); +int wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t on_irq); /** * @brief Stop wdt @@ -171,7 +147,7 @@ int wdt_start(uint8_t id, uint64_t toms); * @param[in] id Wdt id 0 or 1 * */ -void wdt_stop(uint8_t id); +void wdt_stop(wdt_device_number_t id); /** * @brief Set wdt interrupt function @@ -180,7 +156,7 @@ void wdt_stop(uint8_t id); * @param[in] on_irq Wdt interrupt function * */ -void wdt_set_irq(uint8_t id, plic_irq_callback_t on_irq); +void wdt_set_irq(wdt_device_number_t id, plic_irq_callback_t on_irq); #ifdef __cplusplus } diff --git a/lib/drivers/otp.c b/lib/drivers/otp.c deleted file mode 100644 index 35bd0998..00000000 --- a/lib/drivers/otp.c +++ /dev/null @@ -1,602 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "otp.h" -#include "platform.h" -#include "sysctl.h" - -/* clang-format off */ -#define DELAY_TIMEOUT 0xFFFFFFU -#define WRTEST_NUM 0xA5U -/* clang-format on */ - -volatile otp_t* const otp = (volatile otp_t*)OTP_BASE_ADDR; - -void otp_init(uint8_t div) -{ - sysctl_clock_enable(SYSCTL_CLOCK_OTP); - otp->otp_cpu_ctrl = 0; - otp->otp_thershold = div; - otp->data_blk_ctrl = 0; - otp->gb_otp_en = 0; - otp->otp_pwr_mode = 0; - otp->otp_web_cpu = 1; - otp->otp_rstb_cpu = 1; - otp->otp_seltm_cpu = 0; - otp->otp_readen_cpu = 0; - otp->otp_pgmen_cpu = 0; - otp->otp_dle_cpu = 0; - otp->otp_din_cpu = 0; - otp->otp_cpumpen_cpu = 0; - otp->otp_cle_cpu = 0; - otp->otp_ceb_cpu = 1; - otp->otp_adr_cpu = 0; - otp->otp_dat_cpu = 0; -} - -void otp_test_enable(void) -{ - otp->otp_cpu_ctrl = 0xCAAC; -} - -void otp_test_disable(void) -{ - otp->otp_cpu_ctrl = 0; -} - -void otp_key_output_enable(void) -{ - otp->gb_otp_en = 1; -} - -void otp_key_output_disable(void) -{ - otp->gb_otp_en = 0; -} - -otp_status_t otp_status_get(uint32_t flag) -{ - if (otp->otp_status & flag) - return OTP_FLAG_SET; - return OTP_FLAG_UNSET; -} - -static otp_status_t otp_bisr_write(void) -{ - uint32_t time_out = 0; - - otp->otp_cle = 1; - otp->otp_mode = 0x02; - otp->otp_test_mode = 0x30; - otp->test_step = 0; - otp->otp_ceb = 0; - while (otp->bisr_finish == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - otp->bisr_finish = 0; - if (otp->pro_wrong) - return OTP_ERROR_BISR; - return OTP_OK; -} - -static otp_status_t otp_bisr_read(void) -{ - uint32_t time_out = 0; - - otp->otp_cle = 1; - otp->otp_mode = 0x02; - otp->otp_test_mode = 0x30; - otp->test_step = 1; - otp->otp_ceb = 0; - while (otp->bisr_finish == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - otp->bisr_finish = 0; - return OTP_OK; -} - -otp_status_t otp_blank_check(void) -{ - otp_status_t status; - uint32_t time_out = 0; - - if (otp_func_reg_disable_get(BLANK_TEST_DISABLE) == OTP_FUNC_DISABLE) - return OTP_FUNC_DISABLE; - - otp->otp_cle = 1; - otp->otp_mode = 0x02; - otp->otp_test_mode = 0x24; - otp->blank_finish = 0; - otp->otp_ceb = 0; - while (otp->blank_finish == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - if (otp->otp_bisr_fail) - return OTP_ERROR_BLANK; - - status = otp_bisr_write(); - if (status != OTP_OK) - return status; - status = otp_bisr_read(); - if (status != OTP_OK) - return status; - status = otp_func_reg_disable_set(BLANK_TEST_DISABLE); - if (status != OTP_OK) - return status; - return OTP_OK; -} - -otp_status_t otp_testdec(void) -{ - uint32_t time_out = 0; - - otp->otp_cle = 1; - otp->otp_mode = 0x02; - otp->otp_test_mode = 0x21; - otp->otp_ceb = 0; - while (otp->td_result == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - if (otp->td_result == 0x01) - { - otp->td_result = 0; - return OTP_ERROR_TESTDEC; - } - return OTP_OK; -} - -otp_status_t otp_wrtest(void) -{ - uint16_t addr, data, i, j; - uint32_t time_out; - - otp->otp_cle = 1; - otp->otp_mode = 0x02; - otp->otp_test_mode = 0x01; - otp->test_step = 0; - otp->data_acp_flag = 0; - otp->otp_ceb = 0; - addr = 0; - for (i = 0; i < 128; i++) - { - data = WRTEST_NUM; - for (j = 0; j < 8; j++) - { - if ((addr == 1023) || (data & 0x01)) - { - time_out = 0; - while (otp->otp_adr_in_flag == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - otp->otp_apb_adr = addr; - if (addr == 1023) - { - otp->otp_in_dat = data & 0x01; - otp->otp_last_dat = 0x01; - } - else - otp->otp_in_dat = 0x01; - otp->dat_in_finish = 0x01; - time_out = 0; - while (otp->data_acp_flag == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - if (otp->data_acp_flag == 0x01) - { - otp->data_acp_flag = 0; - return OTP_ERROR_WRITE; - } - otp->data_acp_flag = 0; - } - data >>= 1; - addr++; - } - } - time_out = 0; - while ((otp->wr_result & 0x04) == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - otp->wr_result &= 0xFFFFFFFB; - - otp->otp_cle = 1; - otp->otp_mode = 0x02; - otp->otp_test_mode = 0x01; - otp->test_step = 1; - otp->data_acp_flag = 0; - otp->otp_ceb = 0; - addr = 0; - for (i = 0; i < 128; i++) - { - time_out = 0; - while (otp->otp_adr_in_flag == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - if (otp->wr_result == 0x01) - { - otp->wr_result = 0; - return OTP_ERROR_WRTEST; - } - } - otp->otp_in_dat = WRTEST_NUM; - otp->otp_apb_adr = addr; - if (i == 127) - otp->otp_last_dat = 0x01; - addr += 8; - } - time_out = 0; - while ((otp->wr_result & 0x03) == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - if ((otp->wr_result & 0x03) == 0x01) - { - otp->wr_result = 0; - return OTP_ERROR_WRTEST; - } - return OTP_OK; -} - -static otp_status_t otp_write_byte(uint32_t addr, uint8_t* data_buf, uint32_t length) -{ - otp_status_t status; - uint8_t data, index; - uint32_t time_out; - - otp->otp_cle = 0; - otp->otp_mode = 1; - otp->data_acp_flag = 0; - otp->otp_wrg_adr_flag = 0; - otp->otp_ceb = 0; - index = 0; - addr *= 8; - length *= 8; - data = *data_buf++; - while (length--) - { - if ((length == 0) || (data & 0x01)) - { - time_out = 0; - while (otp->otp_adr_in_flag == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - otp->otp_apb_adr = addr; - if (length == 0) - { - otp->otp_in_dat = data & 0x01; - otp->otp_last_dat = 1; - } - else - otp->otp_in_dat = 1; - otp->dat_in_finish = 1; - time_out = 0; - while (otp->data_acp_flag == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - if (otp->otp_wrg_adr_flag == 1) - return OTP_ERROR_ADDRESS; - if (otp->data_acp_flag == 1) - return OTP_ERROR_WRITE; - otp->data_acp_flag = 0; - } - data >>= 1; - addr++; - index++; - if (index == 8) - { - index = 0; - data = *data_buf++; - } - } - - status = otp_bisr_write(); - if (status != OTP_OK) - return status; - status = otp_bisr_read(); - if (status != OTP_OK) - return status; - return OTP_OK; -} - -static otp_status_t otp_read_byte(uint32_t addr, uint8_t* data_buf, uint32_t length) -{ - uint32_t time_out; - - otp->otp_cle = 0; - otp->otp_mode = 0; - otp->otp_wrg_adr_flag = 0; - otp->otp_ceb = 0; - addr *= 8; - while (length--) - { - time_out = 0; - while (otp->otp_adr_in_flag == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - if (length == 0) - otp->otp_last_dat = 1; - otp->otp_apb_adr = addr; - time_out = 0; - while (otp->otp_data_rdy == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - if (otp->otp_wrg_adr_flag == 0x01) - return OTP_ERROR_ADDRESS; - *data_buf++ = otp->otp_data; - addr += 8; - } - return OTP_OK; -} - -otp_status_t otp_write_data(uint32_t addr, uint8_t* data_buf, uint32_t length) -{ - otp_status_t status; - - if (addr >= OTP_BISR_DATA_ADDR) - return OTP_ERROR_ADDRESS; - length = length <= OTP_BISR_DATA_ADDR - addr ? length : OTP_BISR_DATA_ADDR - addr; - - status = otp_write_byte(addr, data_buf, length); - if (status == OTP_ERROR_ADDRESS) - status = OTP_BLOCK_PROTECTED; - return status; -} - -otp_status_t otp_read_data(uint32_t addr, uint8_t* data_buf, uint32_t length) -{ - otp_status_t status; - - if (addr >= OTP_BISR_DATA_ADDR) - return OTP_ERROR_ADDRESS; - length = length <= OTP_BISR_DATA_ADDR - addr ? length : OTP_BISR_DATA_ADDR - addr; - - status = otp_read_byte(addr, data_buf, length); - if (status == OTP_ERROR_ADDRESS) - status = OTP_ERROR_NULL; - return status; -} - -otp_status_t otp_key_write(uint8_t* data_buf) -{ - otp_status_t status; - - status = otp_write_byte(OTP_AES_KEY_ADDR, data_buf, 16); - if (status == OTP_ERROR_ADDRESS) - status = OTP_FUNC_DISABLE; - return status; -} - -otp_status_t otp_key_compare(uint8_t* data_buf) -{ - uint32_t time_out = 0; - - otp->key_cmp_result = 0; - otp->otp_cmp_key = ((uint32_t)data_buf[0] << 24) | ((uint32_t)data_buf[1] << 16) | ((uint32_t)data_buf[2] << 8) | (uint32_t)data_buf[3]; - otp->otp_cmp_key = ((uint32_t)data_buf[4] << 24) | ((uint32_t)data_buf[5] << 16) | ((uint32_t)data_buf[6] << 8) | (uint32_t)data_buf[7]; - otp->otp_cmp_key = ((uint32_t)data_buf[8] << 24) | ((uint32_t)data_buf[9] << 16) | ((uint32_t)data_buf[10] << 8) | (uint32_t)data_buf[11]; - otp->otp_cmp_key = ((uint32_t)data_buf[12] << 24) | ((uint32_t)data_buf[13] << 16) | ((uint32_t)data_buf[14] << 8) | (uint32_t)data_buf[15]; - while (otp->key_cmp_result == 0) - { - time_out++; - if (time_out >= DELAY_TIMEOUT) - return OTP_ERROR_TIMEOUT; - } - if (otp->key_cmp_result == 0x01) - return OTP_ERROR_KEYCOMP; - else if (otp->key_cmp_result == 0x03) - return OTP_FUNC_DISABLE; - return OTP_OK; -} - -otp_status_t otp_data_block_protect_set(otp_data_block_t block) -{ - otp_status_t status; - uint8_t value; - - if (block >= DATA_BLOCK_MAX) - return OTP_ERROR_PARAM; - otp->data_blk_ctrl = 0x01; - value = 0x03 << ((block % 4) * 2); - status = otp_write_byte(OTP_BLOCK_CTL_ADDR + block / 4, &value, 1); - otp->data_blk_ctrl = 0; - return status; -} - -otp_status_t otp_func_reg_disable_set(otp_func_reg_t func) -{ - otp_status_t status; - uint8_t value; - - if (func >= FUNC_REG_MAX) - return OTP_ERROR_PARAM; - otp->data_blk_ctrl = 0x01; - value = 0x03 << ((func % 4) * 2); - status = otp_write_byte(OTP_WIRED_REG_ADDR + func / 4, &value, 1); - otp->data_blk_ctrl = 0; - return status; -} - -otp_status_t otp_data_block_protect_get(otp_data_block_t block) -{ - if (block < DATA_BLOCK_MAX / 2) - { - if (otp->block_flag_low & (0x01 << block)) - return OTP_BLOCK_PROTECTED; - } - else if (block < DATA_BLOCK_MAX) - { - if (otp->block_flag_high & (0x01 << (block - DATA_BLOCK_MAX / 2))) - return OTP_BLOCK_PROTECTED; - } - else - return OTP_ERROR_PARAM; - return OTP_BLOCK_NORMAL; -} - -otp_status_t otp_func_reg_disable_get(otp_func_reg_t func) -{ - if (func < FUNC_REG_MAX / 2) - { - if (otp->reg_flag_low & (0x01 << func)) - return OTP_FUNC_DISABLE; - } - else if (func < FUNC_REG_MAX) - { - if (otp->reg_flag_high & (0x01 << (func - FUNC_REG_MAX / 2))) - return OTP_FUNC_DISABLE; - } - else - return OTP_ERROR_PARAM; - return OTP_FUNC_ENABLE; -} - -otp_status_t otp_data_block_protect_refresh(otp_data_block_t block) -{ - uint8_t value; - - if (block < DATA_BLOCK_MAX) - return otp_read_byte(OTP_BLOCK_CTL_ADDR + block / 4, &value, 1); - else - return OTP_ERROR_PARAM; -} - -otp_status_t otp_soft_write(uint32_t addr, uint8_t* data_buf, uint32_t length) -{ - uint8_t data, index, count; - - otp->otp_ceb_cpu = 1; - otp->otp_cle_cpu = 0; - otp->otp_seltm_cpu = 0; - otp->otp_readen_cpu = 0; - otp->otp_dle_cpu = 0; - otp->otp_web_cpu = 1; - otp->otp_cpumpen_cpu = 0; - otp->otp_pgmen_cpu = 0; - otp->otp_rstb_cpu = 1; - - otp->otp_ceb_cpu = 0; - otp->otp_rstb_cpu = 0; - otp->otp_rstb_cpu = 1; - - index = 0; - addr *= 8; - length *= 8; - data = *data_buf++; - while (length) - { - otp->otp_adr_cpu = addr; - otp->otp_din_cpu = data & 0x01; - otp->otp_dle_cpu = 1; - otp->otp_web_cpu = 0; - otp->otp_web_cpu = 1; - otp->otp_dle_cpu = 0; - count = 20; - while (count--) - { - otp->otp_pgmen_cpu = 1; - otp->otp_cpumpen_cpu = 1; - otp->otp_web_cpu = 0; - otp->otp_web_cpu = 1; - otp->otp_cpumpen_cpu = 0; - otp->otp_pgmen_cpu = 0; - if (otp->otp_dat_cpu == 0) - break; - } - if (otp->otp_dat_cpu & 0x01) - break; - data >>= 1; - addr++; - index++; - if (index == 8) - { - index = 0; - data = *data_buf++; - } - length--; - } - otp->otp_ceb_cpu = 1; - if (length) - return OTP_ERROR_WRITE; - return OTP_OK; -} - -otp_status_t otp_soft_read(uint32_t addr, uint8_t* data_buf, uint32_t length) -{ - otp->otp_ceb_cpu = 1; - otp->otp_dle_cpu = 0; - otp->otp_cle_cpu = 0; - otp->otp_pgmen_cpu = 0; - otp->otp_web_cpu = 1; - otp->otp_readen_cpu = 0; - otp->otp_rstb_cpu = 1; - - otp->otp_ceb_cpu = 0; - otp->otp_rstb_cpu = 0; - otp->otp_rstb_cpu = 1; - - while (length) - { - otp->otp_adr_cpu = addr; - otp->otp_readen_cpu = 1; - *data_buf++ = otp->otp_dat_cpu; - otp->otp_readen_cpu = 0; - addr += 8; - length--; - } - otp->otp_ceb_cpu = 1; - if (length) - return OTP_ERROR_WRITE; - return OTP_OK; -} - -uint32_t otp_wrong_address_get(void) -{ - return otp->otp_pro_adr; -} diff --git a/lib/drivers/pwm.c b/lib/drivers/pwm.c new file mode 100644 index 00000000..2e1d446f --- /dev/null +++ b/lib/drivers/pwm.c @@ -0,0 +1,50 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "timer.h" +#include "pwm.h" +#include "sysctl.h" +#include +#include "utils.h" +#include "plic.h" +#include "io.h" + +void pwm_init(uint32_t tim) +{ + sysctl_clock_tnable(SYSCTL_CLOCK_TIMER0 + tim); +} + +void pwm_set_enable(uint32_t tim, uint32_t channel, int enable) +{ + if (enable) + timer[tim]->channel[channel].control = TIMER_CR_INTERRUPT_MASK | TIMER_CR_PWM_ENABLE | TIMER_CR_USER_MODE | TIMER_CR_ENABLE; + else + timer[tim]->channel[channel].control = TIMER_CR_INTERRUPT_MASK; +} + +double pwm_set_frequency(uint32_t tim, uint32_t channel, double frequency, double duty) +{ + uint32_t clk_freq = sysctl_clock_get_freq(SYSCTL_CLOCK_TIMER0 + tim); + + int32_t periods = (int32_t)(clk_freq / frequency); + configASSERT(periods > 0 && periods <= INT32_MAX); + frequency = clk_freq / (double)periods; + + uint32_t percent = (uint32_t)(duty * periods); + timer[tim]->channel[channel].load_count = periods - percent; + timer[tim]->load_count2[channel] = percent; + + return frequency; +} + diff --git a/lib/drivers/rtc.c b/lib/drivers/rtc.c index f7a704e9..0db469c0 100644 --- a/lib/drivers/rtc.c +++ b/lib/drivers/rtc.c @@ -21,7 +21,7 @@ volatile rtc_t *const rtc = (volatile rtc_t *)RTC_BASE_ADDR; -tm rtc_date_time; +struct tm rtc_date_time; int rtc_timer_set_mode(rtc_timer_mode_t timer_mode) { @@ -85,7 +85,7 @@ static inline int rtc_in_range(int value, int min, int max) return ((value >= min) && (value <= max)); } -int rtc_timer_set_tm(const tm *tm) +int rtc_timer_set_tm(const struct tm *tm) { rtc_date_t timer_date; rtc_time_t timer_time; @@ -178,7 +178,7 @@ int rtc_timer_set_tm(const tm *tm) return 0; } -int rtc_timer_set_alarm_tm(const tm *tm) +int rtc_timer_set_alarm_tm(const struct tm *tm) { rtc_alarm_date_t alarm_date; rtc_alarm_time_t alarm_time; @@ -277,7 +277,7 @@ int rtc_get_wday(int year, int month, int day) return weekday; } -tm *rtc_timer_get_tm(void) +struct tm *rtc_timer_get_tm(void) { if (rtc_timer_get_mode() != RTC_TIMER_RUNNING) return NULL; @@ -286,7 +286,7 @@ tm *rtc_timer_get_tm(void) rtc_time_t timer_time = rtc->time; rtc_extended_t timer_extended = rtc->extended; - tm *tm = &rtc_date_time; + struct tm *tm = &rtc_date_time; tm->tm_sec = timer_time.second % 60; tm->tm_min = timer_time.minute % 60; @@ -301,7 +301,7 @@ tm *rtc_timer_get_tm(void) return tm; } -tm *rtc_timer_get_alarm_tm(void) +struct tm *rtc_timer_get_alarm_tm(void) { if (rtc_timer_get_mode() != RTC_TIMER_RUNNING) return NULL; @@ -310,7 +310,7 @@ tm *rtc_timer_get_alarm_tm(void) rtc_alarm_time_t alarm_time = rtc->alarm_time; rtc_extended_t timer_extended = rtc->extended; - tm *tm = &rtc_date_time; + struct tm *tm = &rtc_date_time; tm->tm_sec = alarm_time.second % 60; tm->tm_min = alarm_time.minute % 60; @@ -328,7 +328,7 @@ tm *rtc_timer_get_alarm_tm(void) int rtc_timer_set(int year, int month, int day, int hour, int minute, int second) { - tm date_time = + struct tm date_time = { .tm_sec = second, .tm_min = minute, @@ -345,7 +345,7 @@ int rtc_timer_set(int year, int month, int day, int hour, int minute, int second int rtc_timer_get(int *year, int *month, int *day, int *hour, int *minute, int *second) { - tm *tm = rtc_timer_get_tm(); + struct tm *tm = rtc_timer_get_tm(); if (tm) { @@ -369,7 +369,7 @@ int rtc_timer_get(int *year, int *month, int *day, int *hour, int *minute, int * int rtc_timer_set_alarm(int year, int month, int day, int hour, int minute, int second) { - tm date_time = { + struct tm date_time = { .tm_sec = second, .tm_min = minute, .tm_hour = hour, @@ -386,7 +386,7 @@ int rtc_timer_set_alarm(int year, int month, int day, int hour, int minute, int int rtc_timer_get_alarm(int *year, int *month, int *day, int *hour, int *minute, int *second) { - tm *tm = rtc_timer_get_alarm_tm(); + struct tm *tm = rtc_timer_get_alarm_tm(); if (tm) { if (year) @@ -565,7 +565,7 @@ int rtc_init(void) /* Reset RTC */ sysctl_reset(SYSCTL_RESET_RTC); /* Enable RTC */ - sysctl_clock_enable(SYSCTL_CLOCK_RTC); + sysctl_clock_tnable(SYSCTL_CLOCK_RTC); rtc_timer_set_mode(RTC_TIMER_SETTING); /* Unprotect RTC */ rtc_protect_set(0); diff --git a/lib/drivers/sha256.c b/lib/drivers/sha256.c index 458e33ac..89701598 100644 --- a/lib/drivers/sha256.c +++ b/lib/drivers/sha256.c @@ -46,7 +46,7 @@ static const uint8_t padding[64] = int sha256_init(uint8_t dma_en, uint32_t input_size, SHA256Context_t* sc) { - sysctl_clock_enable(SYSCTL_CLOCK_SHA); + sysctl_clock_tnable(SYSCTL_CLOCK_SHA); sysctl_reset(SYSCTL_RESET_SHA); input_size = (input_size + 64) / 64; if (dma_en) diff --git a/lib/drivers/spi.c b/lib/drivers/spi.c index 9ce42ba4..b77e9f77 100644 --- a/lib/drivers/spi.c +++ b/lib/drivers/spi.c @@ -15,13 +15,11 @@ #include "platform.h" #include "spi.h" #include "fpioa.h" -#include "common.h" +#include "utils.h" #include "sysctl.h" #include #include -#define SPI_MAX_NUM 4 - volatile spi_t *const spi[4] = { (volatile spi_t *)SPI0_BASE_ADDR, @@ -30,43 +28,45 @@ volatile spi_t *const spi[4] = (volatile spi_t *)SPI3_BASE_ADDR }; -static int spi_clk_init(uint8_t spi_bus) +static int spi_clk_init(uint8_t spi_num) { - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - sysctl_clock_enable(SYSCTL_CLOCK_SPI0 + spi_bus); - sysctl_clock_set_threshold(SYSCTL_THRESHOLD_SPI0 + spi_bus, 0); + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + sysctl_clock_tnable(SYSCTL_CLOCK_SPI0 + spi_num); + sysctl_clock_set_threshold(SYSCTL_THRESHOLD_SPI0 + spi_num, 0); return 0; } -static void spi_set_tmod(uint8_t spi_bus, uint32_t tmod) +static void spi_set_tmod(uint8_t spi_num, uint32_t tmod) { - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - volatile spi_t *spi_handle = spi[spi_bus]; + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + volatile spi_t *spi_handle = spi[spi_num]; uint8_t tmod_offset = 0; - switch(spi_bus){ - case 0: - case 1: - tmod_offset = 8; - break; - case 2: - configASSERT(!"Spi Bus 2 Not Support!"); - break; - case 3: - default: - tmod_offset = 10; - break; + switch(spi_num) + { + case 0: + case 1: + tmod_offset = 8; + break; + case 2: + configASSERT(!"Spi Bus 2 Not Support!"); + break; + case 3: + default: + tmod_offset = 10; + break; } set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset); } -int spi_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame_format, size_t data_bit_length) +int spi_config(spi_device_num_t spi_num, spi_work_mode_t mode, spi_frame_format_t frame_format, size_t data_bit_length) { configASSERT(data_bit_length >= 4 && data_bit_length <= 32); - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - spi_clk_init(spi_bus); + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_clk_init(spi_num); uint8_t dfs_offset, frf_offset; - switch(spi_bus){ + switch(spi_num) + { case 0: case 1: dfs_offset = 16; @@ -84,19 +84,19 @@ int spi_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame_format switch (frame_format) { - case SPI_FF_DUAL: - configASSERT(data_bit_length % 2 == 0); - break; - case SPI_FF_QUAD: - configASSERT(data_bit_length % 4 == 0); - break; - case SPI_FF_OCTAL: - configASSERT(data_bit_length % 8 == 0); - break; - default: - break; + case SPI_FF_DUAL: + configASSERT(data_bit_length % 2 == 0); + break; + case SPI_FF_QUAD: + configASSERT(data_bit_length % 4 == 0); + break; + case SPI_FF_OCTAL: + configASSERT(data_bit_length % 8 == 0); + break; + default: + break; } - volatile spi_t *spi_adapter = spi[spi_bus]; + volatile spi_t *spi_adapter = spi[spi_num]; spi_adapter->baudr = 0x14; spi_adapter->imr = 0x00; @@ -110,31 +110,31 @@ int spi_config(uint8_t spi_bus, spi_mode_t mode, spi_frame_format_t frame_format return 0; } -void spi_config_non_standard(uint8_t spi_bus, size_t instruction_length, size_t address_length, +void spi_config_non_standard(spi_device_num_t spi_num, size_t instruction_length, size_t address_length, size_t wait_cycles, spi_addr_inst_trans_mode_t trans_mode) { configASSERT(wait_cycles < (1 << 5)); configASSERT(trans_mode < 3); - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - volatile spi_t *spi_handle = spi[spi_bus]; + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + volatile spi_t *spi_handle = spi[spi_num]; uint32_t inst_l; switch (instruction_length) { - case 0: - inst_l = 0; - break; - case 4: - inst_l = 1; - break; - case 8: - inst_l = 2; - break; - case 16: - inst_l = 3; - break; - default: - configASSERT(!"Invalid instruction length"); - break; + case 0: + inst_l = 0; + break; + case 4: + inst_l = 1; + break; + case 8: + inst_l = 2; + break; + case 16: + inst_l = 3; + break; + default: + configASSERT(!"Invalid instruction length"); + break; } configASSERT(address_length % 4 == 0 && address_length <= 60); @@ -143,9 +143,9 @@ void spi_config_non_standard(uint8_t spi_bus, size_t instruction_length, size_t spi_handle->spi_ctrlr0 = (wait_cycles << 11) | (inst_l << 8) | (addr_l << 2) | trans_mode; } -uint32_t spi_set_clk_rate(uint8_t spi_bus, uint32_t spi_clk) +uint32_t spi_set_clk_rate(spi_device_num_t spi_num, uint32_t spi_clk) { - uint32_t spi_baudr = sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_bus) / spi_clk; + uint32_t spi_baudr = sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_num) / spi_clk; if(spi_baudr < 2 ) { spi_baudr = 2; @@ -154,19 +154,20 @@ uint32_t spi_set_clk_rate(uint8_t spi_bus, uint32_t spi_clk) { spi_baudr = 65534; } - volatile spi_t *spi_adapter = spi[spi_bus]; + volatile spi_t *spi_adapter = spi[spi_num]; spi_adapter->baudr = spi_baudr; - return sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_bus) / spi_baudr; + return sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_num) / spi_baudr; } -int spi_send_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) +int spi_send_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { uint32_t index, fifo_len; - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - spi_set_tmod(spi_bus, SPI_TMOD_TRANS); - volatile spi_t *spi_handle = spi[spi_bus]; + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_TRANS); + volatile spi_t *spi_handle = spi[spi_num]; spi_handle->ssienr = 0x01; - while (cmd_len){ + while (cmd_len) + { spi_handle->dr[0] = *cmd_buff++; cmd_len--; } @@ -175,8 +176,9 @@ int spi_send_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff for (index = 0; index < fifo_len; index++) spi_handle->dr[0] = *tx_buff++; tx_len -= fifo_len; - spi_handle->ser = chip_sel; - while (tx_len) { + spi_handle->ser = 1 << chip_sel; + while (tx_len) + { fifo_len = 32 - spi_handle->txflr; fifo_len = fifo_len < tx_len ? fifo_len : tx_len; for (index = 0; index < fifo_len; index++) @@ -190,28 +192,30 @@ int spi_send_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff return 0; } -int spi_send_data_standard_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, +int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - spi_set_tmod(spi_bus, SPI_TMOD_TRANS); - volatile spi_t *spi_handle = spi[spi_bus]; + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_TRANS); + volatile spi_t *spi_handle = spi[spi_num]; uint32_t *buf = malloc((cmd_len + tx_len) * sizeof(uint32_t)); int i; - for(i = 0; i < cmd_len; i++){ + for(i = 0; i < cmd_len; i++) + { buf[i] = cmd_buff[i]; } - for(i = 0; i < tx_len; i++){ + for(i = 0; i < tx_len; i++) + { buf[cmd_len + i] = tx_buff[i]; } spi_handle->dmacr = 0x2; /*enable dma transmit*/ spi_handle->ssienr = 0x01; - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_bus * 2); + sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); dmac_set_single_mode(channel_num, buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len + tx_len); - spi_handle->ser = chip_sel; + spi_handle->ser = 1 << chip_sel; dmac_wait_done(channel_num); free((void*)buf); @@ -222,12 +226,12 @@ int spi_send_data_standard_dma(dmac_channel_number_t channel_num, uint8_t spi_bu return 0; } -int spi_send_data_normal_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, uint32_t chip_sel, +int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, uint32_t chip_sel, void *tx_buff, size_t tx_len, spi_transfer_width_t stw) { - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - spi_set_tmod(spi_bus, SPI_TMOD_TRANS); - volatile spi_t *spi_handle = spi[spi_bus]; + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_TRANS); + volatile spi_t *spi_handle = spi[spi_num]; uint32_t *buf = malloc((tx_len) * sizeof(uint32_t)); int i; for(i = 0; i < tx_len; i++) @@ -250,10 +254,10 @@ int spi_send_data_normal_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, spi_handle->dmacr = 0x2; /*enable dma transmit*/ spi_handle->ssienr = 0x01; - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_bus * 2); + sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); dmac_set_single_mode(channel_num, buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, tx_len); - spi_handle->ser = chip_sel; + spi_handle->ser = 1 << chip_sel; dmac_wait_done(channel_num); free((void*)buf); @@ -264,17 +268,17 @@ int spi_send_data_normal_dma(dmac_channel_number_t channel_num, uint8_t spi_bus, return 0; } -int spi_receive_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +int spi_receive_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { uint32_t index, fifo_len; - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - spi_set_tmod(spi_bus, SPI_TMOD_EEROM); - volatile spi_t *spi_handle = spi[spi_bus]; + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_EEROM); + volatile spi_t *spi_handle = spi[spi_num]; spi_handle->ctrlr1 = rx_len - 1; spi_handle->ssienr = 0x01; while (cmd_len--) spi_handle->dr[0] = *cmd_buff++; - spi_handle->ser = chip_sel; + spi_handle->ser = 1 << chip_sel; while (rx_len) { fifo_len = spi_handle->rxflr; @@ -288,12 +292,12 @@ int spi_receive_data_standard(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_b return 0; } -int spi_receive_data_standard_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, - uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, + spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - spi_set_tmod(spi_bus, SPI_TMOD_EEROM); - volatile spi_t *spi_handle = spi[spi_bus]; + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_EEROM); + volatile spi_t *spi_handle = spi[spi_num]; uint32_t * write_cmd = malloc(sizeof(uint32_t) * (cmd_len + rx_len)); size_t i; for (i = 0; i < cmd_len; i++) @@ -302,19 +306,19 @@ int spi_receive_data_standard_dma(dmac_channel_number_t channel_num_w, dmac_chan spi_handle->ctrlr1 = rx_len - 1; spi_handle->dmacr = 0x3; spi_handle->ssienr = 0x01; - spi_handle->ser = chip_sel; + spi_handle->ser = 1 << chip_sel; - sysctl_dma_select(channel_num_w, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_bus * 2); - sysctl_dma_select(channel_num_r, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_bus * 2); + sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); + sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2); - dmac_set_single_mode(channel_num_r, (void *)(&spi_handle->dr[0]), write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, + dmac_set_single_mode(dma_receive_channel_num, (void *)(&spi_handle->dr[0]), write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len); - dmac_set_single_mode(channel_num_w, write_cmd, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, + dmac_set_single_mode(dma_send_channel_num, write_cmd, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len); - dmac_wait_done(channel_num_w); - dmac_wait_done(channel_num_r); + dmac_wait_done(dma_send_channel_num); + dmac_wait_done(dma_receive_channel_num); for(i = 0; i < rx_len; i++){ rx_buff[i] = write_cmd[i]; @@ -326,18 +330,19 @@ int spi_receive_data_standard_dma(dmac_channel_number_t channel_num_w, dmac_chan return 0; } -int spi_receive_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +int spi_receive_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { uint32_t index, fifo_len; - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - spi_set_tmod(spi_bus, SPI_TMOD_RECV); - volatile spi_t *spi_handle = spi[spi_bus]; + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_RECV); + volatile spi_t *spi_handle = spi[spi_num]; spi_handle->ctrlr1 = rx_len - 1; spi_handle->ssienr = 0x01; while (cmd_len--) spi_handle->dr[0] = *cmd_buff++; - spi_handle->ser = chip_sel; - while (rx_len) { + spi_handle->ser = 1 << chip_sel; + while (rx_len) + { fifo_len = spi_handle->rxflr; fifo_len = fifo_len < rx_len ? fifo_len : rx_len; for (index = 0; index < fifo_len; index++) @@ -349,12 +354,12 @@ int spi_receive_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_ return 0; } -int spi_receive_data_multiple_dma(dmac_channel_number_t channel_num_w, dmac_channel_number_t channel_num_r, - uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, + spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - spi_set_tmod(spi_bus, SPI_TMOD_RECV); - volatile spi_t *spi_handle = spi[spi_bus]; + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_RECV); + volatile spi_t *spi_handle = spi[spi_num]; uint32_t * write_cmd = malloc(sizeof(uint32_t) * (cmd_len + rx_len)); size_t i; for (i = 0; i < cmd_len; i++) @@ -363,21 +368,22 @@ int spi_receive_data_multiple_dma(dmac_channel_number_t channel_num_w, dmac_chan spi_handle->ctrlr1 = rx_len - 1; spi_handle->dmacr = 0x3; spi_handle->ssienr = 0x01; - spi_handle->ser = chip_sel; + spi_handle->ser = 1 << chip_sel; - sysctl_dma_select(channel_num_w, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_bus * 2); - sysctl_dma_select(channel_num_r, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_bus * 2); + sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); + sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2); - dmac_set_single_mode(channel_num_r, (void *)(&spi_handle->dr[0]), write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, + dmac_set_single_mode(dma_receive_channel_num, (void *)(&spi_handle->dr[0]), write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len); - dmac_set_single_mode(channel_num_w, write_cmd, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, + dmac_set_single_mode(dma_send_channel_num, write_cmd, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len); - dmac_wait_done(channel_num_w); - dmac_wait_done(channel_num_r); + dmac_wait_done(dma_send_channel_num); + dmac_wait_done(dma_receive_channel_num); - for(i = 0; i < rx_len; i++){ + for(i = 0; i < rx_len; i++) + { rx_buff[i] = write_cmd[i]; } free(write_cmd); @@ -386,12 +392,12 @@ int spi_receive_data_multiple_dma(dmac_channel_number_t channel_num_w, dmac_chan return 0; } -int spi_send_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) +int spi_send_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { uint32_t index, fifo_len; - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - spi_set_tmod(spi_bus, SPI_TMOD_TRANS); - volatile spi_t *spi_handle = spi[spi_bus]; + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_TRANS); + volatile spi_t *spi_handle = spi[spi_num]; spi_handle->ssienr = 0x01; while (cmd_len--) spi_handle->dr[0] = *cmd_buff++; @@ -400,8 +406,9 @@ int spi_send_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buf for (index = 0; index < fifo_len; index++) spi_handle->dr[0] = *tx_buff++; tx_len -= fifo_len; - spi_handle->ser = chip_sel; - while (tx_len) { + spi_handle->ser = 1 << chip_sel; + while (tx_len) + { fifo_len = 32 - spi_handle->txflr; fifo_len = fifo_len < tx_len ? fifo_len : tx_len; for (index = 0; index < fifo_len; index++) @@ -415,28 +422,30 @@ int spi_send_data_multiple(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buf return 0; } -int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, +int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - spi_set_tmod(spi_bus, SPI_TMOD_TRANS); - volatile spi_t *spi_handle = spi[spi_bus]; + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_TRANS); + volatile spi_t *spi_handle = spi[spi_num]; uint32_t *buf = malloc((cmd_len + tx_len) * sizeof(uint32_t)); int i; - for(i = 0; i < cmd_len; i++){ + for(i = 0; i < cmd_len; i++) + { buf[i] = cmd_buff[i]; } - for(i = 0; i < tx_len; i++){ + for(i = 0; i < tx_len; i++) + { buf[cmd_len + i] = tx_buff[i]; } spi_handle->dmacr = 0x2; /*enable dma transmit*/ spi_handle->ssienr = 0x01; - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_bus * 2); + sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); dmac_set_single_mode(channel_num, buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len + tx_len); - spi_handle->ser = chip_sel; + spi_handle->ser = 1 << chip_sel; dmac_wait_done(channel_num); free((void*)buf); @@ -447,18 +456,18 @@ int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,uint8_t spi_bus return 0; } -int spi_fill_dma(dmac_channel_number_t channel_num,uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len) +int spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len) { - configASSERT(spi_bus < SPI_MAX_NUM && spi_bus != 2); - spi_set_tmod(spi_bus, SPI_TMOD_TRANS); - volatile spi_t *spi_handle = spi[spi_bus]; + configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_TRANS); + volatile spi_t *spi_handle = spi[spi_num]; spi_handle->dmacr = 0x2; /*enable dma transmit*/ spi_handle->ssienr = 0x01; - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_bus * 2); + sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); dmac_set_single_mode(channel_num, cmd_buff, (void *)(&spi_handle->dr[0]), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, cmd_len); - spi_handle->ser = chip_sel; + spi_handle->ser = 1 << chip_sel; dmac_wait_done(channel_num); while ((spi_handle->sr & 0x05) != 0x04) diff --git a/lib/drivers/sysclock.c b/lib/drivers/sysclock.c index 36bd89a9..583c9b2a 100644 --- a/lib/drivers/sysclock.c +++ b/lib/drivers/sysclock.c @@ -12,58 +12,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#include "sysclock.h" #include "stdio.h" #include "sysctl.h" #include "uarths.h" -void sys_clock_init() -{ - sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0); - - sysctl_pll_enable(SYSCTL_PLL0); - sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, PLL0_OUTPUT_FREQ); - while (sysctl_pll_is_lock(SYSCTL_PLL0) == 0) - sysctl_pll_clear_slip(SYSCTL_PLL0); - sysctl_clock_enable(SYSCTL_CLOCK_PLL0); - sysctl->clk_sel0.aclk_divider_sel = 0; - sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); - - sysctl_pll_enable(SYSCTL_PLL1); - sysctl_pll_set_freq(SYSCTL_PLL1, SYSCTL_SOURCE_IN0, PLL1_OUTPUT_FREQ); - while (sysctl_pll_is_lock(SYSCTL_PLL1) == 0) - sysctl_pll_clear_slip(SYSCTL_PLL1); - sysctl_clock_enable(SYSCTL_CLOCK_PLL1); - - sysctl_pll_enable(SYSCTL_PLL2); - sysctl_pll_set_freq(SYSCTL_PLL2, SYSCTL_SOURCE_IN0, PLL2_OUTPUT_FREQ); - while (sysctl_pll_is_lock(SYSCTL_PLL2) == 0) - sysctl_pll_clear_slip(SYSCTL_PLL2); - sysctl_clock_enable(SYSCTL_CLOCK_PLL2); -} - -uint32_t system_set_cpu_frequency(uint32_t frequency) -{ - sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0); - sysctl->pll0.pll_reset0 = 1; - - uint32_t result = sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, frequency * 2); - sysctl->pll0.pll_reset0 = 0; - while (1) - { - uint32_t lock = sysctl->pll_lock.pll_lock0 & 0x3; - if (lock == 0x3) - { - break; - } - else - { - sysctl->pll_lock.pll_slip_clear0 = 1; - } - } - - sysctl->pll0.pll_out_en0 = 1; - sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); - uart_init(); - return result; -} diff --git a/lib/drivers/sysctl.c b/lib/drivers/sysctl.c index 47f9cc94..0827cf14 100644 --- a/lib/drivers/sysctl.c +++ b/lib/drivers/sysctl.c @@ -162,7 +162,7 @@ void sysctl_reset(sysctl_reset_t reset) sysctl_reset_ctl(reset, 0); } -static int sysctl_clock_bus_en(sysctl_clock_e clock, uint8_t en) +static int sysctl_clock_bus_en(sysctl_clock_t clock, uint8_t en) { /* * The timer is under APB0, to prevent apb0_clk_en1 and apb0_clk_en0 @@ -232,7 +232,7 @@ static int sysctl_clock_bus_en(sysctl_clock_e clock, uint8_t en) return 0; } -static int sysctl_clock_device_en(sysctl_clock_e clock, uint8_t en) +static int sysctl_clock_device_en(sysctl_clock_t clock, uint8_t en) { switch (clock) { @@ -382,7 +382,7 @@ static int sysctl_clock_device_en(sysctl_clock_e clock, uint8_t en) return 0; } -int sysctl_clock_enable(sysctl_clock_e clock) +int sysctl_clock_tnable(sysctl_clock_t clock) { if (clock >= SYSCTL_CLOCK_MAX) return -1; @@ -391,7 +391,7 @@ int sysctl_clock_enable(sysctl_clock_e clock) return 0; } -int sysctl_clock_disable(sysctl_clock_e clock) +int sysctl_clock_disable(sysctl_clock_t clock) { if (clock >= SYSCTL_CLOCK_MAX) return -1; @@ -400,7 +400,7 @@ int sysctl_clock_disable(sysctl_clock_e clock) return 0; } -int sysctl_clock_set_threshold(sysctl_threshold_e which, int threshold) +int sysctl_clock_set_threshold(sysctl_threshold_t which, int threshold) { switch (which) { @@ -505,7 +505,7 @@ int sysctl_clock_set_threshold(sysctl_threshold_e which, int threshold) return 0; } -int sysctl_clock_get_threshold(sysctl_threshold_e which) +int sysctl_clock_get_threshold(sysctl_threshold_t which) { int threshold = 0; @@ -603,7 +603,7 @@ int sysctl_clock_get_threshold(sysctl_threshold_e which) return threshold; } -int sysctl_clock_set_clock_select(sysctl_clock_select_e which, int select) +int sysctl_clock_set_clock_select(sysctl_clock_select_t which, int select) { switch (which) { @@ -652,7 +652,7 @@ int sysctl_clock_set_clock_select(sysctl_clock_select_e which, int select) return 0; } -int sysctl_clock_get_clock_select(sysctl_clock_select_e which) +int sysctl_clock_get_clock_select(sysctl_clock_select_t which) { int clock_select = 0; @@ -699,7 +699,7 @@ int sysctl_clock_get_clock_select(sysctl_clock_select_e which) return clock_select; } -uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_e input) +uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_t input) { uint32_t result; @@ -728,7 +728,7 @@ uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_e input) return result; } -int sysctl_pll_is_lock(sysctl_pll_e pll) +int sysctl_pll_is_lock(sysctl_pll_t pll) { /* * All bit enable means PLL lock @@ -771,7 +771,7 @@ int sysctl_pll_is_lock(sysctl_pll_e pll) return 0; } -int sysctl_pll_clear_slip(sysctl_pll_e pll) +int sysctl_pll_clear_slip(sysctl_pll_t pll) { if (pll >= SYSCTL_PLL_MAX) return -1; @@ -797,7 +797,7 @@ int sysctl_pll_clear_slip(sysctl_pll_e pll) return sysctl_pll_is_lock(pll) ? 0 : -1; } -int sysctl_pll_enable(sysctl_pll_e pll) +int sysctl_pll_tnable(sysctl_pll_t pll) { /* * ---+ @@ -885,7 +885,7 @@ int sysctl_pll_enable(sysctl_pll_e pll) return 0; } -int sysctl_pll_disable(sysctl_pll_e pll) +int sysctl_pll_disable(sysctl_pll_t pll) { if (pll >= SYSCTL_PLL_MAX) return -1; @@ -932,7 +932,7 @@ int sysctl_pll_disable(sysctl_pll_e pll) return 0; } -uint32_t sysctl_pll_get_freq(sysctl_pll_e pll) +uint32_t sysctl_pll_get_freq(sysctl_pll_t pll) { uint32_t freq_in = 0, freq_out = 0; uint32_t nr = 0, nf = 0, od = 0; @@ -984,7 +984,7 @@ uint32_t sysctl_pll_get_freq(sysctl_pll_e pll) return freq_out; } -uint32_t sysctl_pll_set_freq(sysctl_pll_e pll, sysctl_clock_source_e source, uint32_t freq) +uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uint32_t freq) { uint32_t freq_in = 0; @@ -1282,7 +1282,7 @@ uint32_t sysctl_pll_set_freq(sysctl_pll_e pll, sysctl_clock_source_e source, uin return sysctl_pll_get_freq(pll); } -uint32_t sysctl_clock_get_freq(sysctl_clock_e clock) +uint32_t sysctl_clock_get_freq(sysctl_clock_t clock) { uint32_t source = 0; uint32_t result = 0; @@ -1620,7 +1620,7 @@ uint32_t sysctl_clock_get_freq(sysctl_clock_e clock) return result; } -int sysctl_dma_select(sysctl_dma_channel_e channel, sysctl_dma_select_e select) +int sysctl_dma_select(sysctl_dma_channel_t channel, sysctl_dma_select_t select) { sysctl_dma_sel0_t dma_sel0; sysctl_dma_sel1_t dma_sel1; @@ -1705,9 +1705,9 @@ uint32_t sysctl_pll_fast_enable_pll(void) sysctl->pll1 = pll1; sysctl->pll2 = pll2; - sysctl_pll_enable(SYSCTL_PLL0); - sysctl_pll_enable(SYSCTL_PLL1); - sysctl_pll_enable(SYSCTL_PLL2); + sysctl_pll_tnable(SYSCTL_PLL0); + sysctl_pll_tnable(SYSCTL_PLL1); + sysctl_pll_tnable(SYSCTL_PLL2); while (sysctl_pll_is_lock(SYSCTL_PLL0) == 0) sysctl_pll_clear_slip(SYSCTL_PLL0); @@ -1716,9 +1716,9 @@ uint32_t sysctl_pll_fast_enable_pll(void) while (sysctl_pll_is_lock(SYSCTL_PLL2) == 0) sysctl_pll_clear_slip(SYSCTL_PLL2); - sysctl_clock_enable(SYSCTL_CLOCK_PLL0); - sysctl_clock_enable(SYSCTL_CLOCK_PLL1); - sysctl_clock_enable(SYSCTL_CLOCK_PLL2); + sysctl_clock_tnable(SYSCTL_CLOCK_PLL0); + sysctl_clock_tnable(SYSCTL_CLOCK_PLL1); + sysctl_clock_tnable(SYSCTL_CLOCK_PLL2); /* Set ACLK to PLL0 */ sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); @@ -1732,7 +1732,7 @@ uint32_t sysctl_spi0_dvp_data_set(uint8_t en) return 0; } -uint32_t sysctl_power_mode_sel(uint8_t power_bank, io_power_mode_t io_power_mode) +uint32_t sysctl_power_mode_sel(uint8_t power_bank, sysctl_io_power_mode_t io_power_mode) { if(io_power_mode) *((uint32_t *)(&sysctl->power_sel)) |= (1 << power_bank); @@ -1741,3 +1741,53 @@ uint32_t sysctl_power_mode_sel(uint8_t power_bank, io_power_mode_t io_power_mode return 0; } +void sysctl_set_pll_frequency(uint64_t pll0, uint64_t pll1, uint64_t pll2) +{ + sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0); + + sysctl_pll_tnable(SYSCTL_PLL0); + sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, pll0); + while (sysctl_pll_is_lock(SYSCTL_PLL0) == 0) + sysctl_pll_clear_slip(SYSCTL_PLL0); + sysctl_clock_tnable(SYSCTL_CLOCK_PLL0); + sysctl->clk_sel0.aclk_divider_sel = 0; + sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); + + sysctl_pll_tnable(SYSCTL_PLL1); + sysctl_pll_set_freq(SYSCTL_PLL1, SYSCTL_SOURCE_IN0, pll1); + while (sysctl_pll_is_lock(SYSCTL_PLL1) == 0) + sysctl_pll_clear_slip(SYSCTL_PLL1); + sysctl_clock_tnable(SYSCTL_CLOCK_PLL1); + + sysctl_pll_tnable(SYSCTL_PLL2); + sysctl_pll_set_freq(SYSCTL_PLL2, SYSCTL_SOURCE_IN0, pll2); + while (sysctl_pll_is_lock(SYSCTL_PLL2) == 0) + sysctl_pll_clear_slip(SYSCTL_PLL2); + sysctl_clock_tnable(SYSCTL_CLOCK_PLL2); +} + +uint32_t sysctl_set_cpu_frequency(uint32_t frequency) +{ + sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0); + sysctl->pll0.pll_reset0 = 1; + + uint32_t result = sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, frequency * 2); + sysctl->pll0.pll_reset0 = 0; + while (1) + { + uint32_t lock = sysctl->pll_lock.pll_lock0 & 0x3; + if (lock == 0x3) + { + break; + } + else + { + sysctl->pll_lock.pll_slip_clear0 = 1; + } + } + + sysctl->pll0.pll_out_en0 = 1; + sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); + return result; +} + diff --git a/lib/drivers/timer.c b/lib/drivers/timer.c index 568a75fc..09f2ab7e 100644 --- a/lib/drivers/timer.c +++ b/lib/drivers/timer.c @@ -15,7 +15,7 @@ #include "timer.h" #include "sysctl.h" #include "stddef.h" -#include "common.h" +#include "utils.h" #include "plic.h" #include "io.h" @@ -26,105 +26,105 @@ volatile kendryte_timer_t *const timer[3] = (volatile kendryte_timer_t *)TIMER2_BASE_ADDR }; -void timer_init(uint32_t tim) +void timer_init(timer_device_number_t tim) { - sysctl_clock_enable(SYSCTL_CLOCK_TIMER0 + tim); + sysctl_clock_tnable(SYSCTL_CLOCK_TIMER0 + tim); } -void timer_set_clock_div(uint32_t tim, uint32_t div) +void timer_set_clock_div(timer_device_number_t tim, uint32_t div) { sysctl_clock_set_threshold(tim == 0 ? SYSCTL_THRESHOLD_TIMER0 : tim == 1 ? SYSCTL_THRESHOLD_TIMER1 : SYSCTL_THRESHOLD_TIMER2, div); } -void timer_enable(uint32_t tim, uint32_t channel) +void timer_enable(timer_device_number_t tim, timer_channel_number_t channel) { timer[tim]->channel[channel].control |= TIMER_CR_ENABLE; } -void timer_disable(uint32_t tim, uint32_t channel) +void timer_disable(timer_device_number_t tim, timer_channel_number_t channel) { timer[tim]->channel[channel].control &= (~TIMER_CR_ENABLE); } -void timer_enable_pwm(uint32_t tim, uint32_t channel) +void timer_enable_pwm(timer_device_number_t tim, timer_channel_number_t channel) { timer[tim]->channel[channel].control |= TIMER_CR_PWM_ENABLE; } -void timer_disable_pwm(uint32_t tim, uint32_t channel) +void timer_disable_pwm(timer_device_number_t tim, timer_channel_number_t channel) { timer[tim]->channel[channel].control &= (~TIMER_CR_PWM_ENABLE); } -void timer_enable_interrupt(uint32_t tim, uint32_t channel) +void timer_enable_interrupt(timer_device_number_t tim, timer_channel_number_t channel) { timer[tim]->channel[channel].control &= (~TIMER_CR_INTERRUPT_MASK); } -void timer_disable_interrupt(uint32_t tim, uint32_t channel) +void timer_disable_interrupt(timer_device_number_t tim, timer_channel_number_t channel) { timer[tim]->channel[channel].control |= TIMER_CR_INTERRUPT_MASK; } -void timer_set_mode(uint32_t tim, uint32_t channel, uint32_t mode) +void timer_set_mode(timer_device_number_t tim, timer_channel_number_t channel, uint32_t mode) { timer[tim]->channel[channel].control &= (~TIMER_CR_MODE_MASK); timer[tim]->channel[channel].control |= mode; } -void timer_set_reload(uint32_t tim, uint32_t channel, uint32_t count) +void timer_set_reload(timer_device_number_t tim, timer_channel_number_t channel, uint32_t count) { timer[tim]->channel[channel].load_count = count; } -void timer_set_reload2(uint32_t tim, uint32_t channel, uint32_t count) +void timer_set_reload2(timer_device_number_t tim, timer_channel_number_t channel, uint32_t count) { timer[tim]->load_count2[channel] = count; } -uint32_t timer_get_count(uint32_t tim, uint32_t channel) +uint32_t timer_get_count(timer_device_number_t tim, timer_channel_number_t channel) { return timer[tim]->channel[channel].current_value; } -uint32_t timer_get_reload(uint32_t tim, uint32_t channel) +uint32_t timer_get_reload(timer_device_number_t tim, timer_channel_number_t channel) { return timer[tim]->channel[channel].load_count; } -uint32_t timer_get_reload2(uint32_t tim, uint32_t channel) +uint32_t timer_get_reload2(timer_device_number_t tim, timer_channel_number_t channel) { return timer[tim]->load_count2[channel]; } -uint32_t timer_get_interrupt_status(uint32_t tim) +uint32_t timer_get_interrupt_status(timer_device_number_t tim) { return timer[tim]->intr_stat; } -uint32_t timer_get_raw_interrupt_status(uint32_t tim) +uint32_t timer_get_raw_interrupt_status(timer_device_number_t tim) { return timer[tim]->raw_intr_stat; } -uint32_t timer_channel_get_interrupt_status(uint32_t tim, uint32_t channel) +uint32_t timer_channel_get_interrupt_status(timer_device_number_t tim, timer_channel_number_t channel) { return timer[tim]->channel[channel].intr_stat; } -void timer_clear_interrupt(uint32_t tim) +void timer_clear_interrupt(timer_device_number_t tim) { timer[tim]->eoi = timer[tim]->eoi; } -void timer_channel_clear_interrupt(uint32_t tim, uint32_t channel) +void timer_channel_clear_interrupt(timer_device_number_t tim, timer_channel_number_t channel) { timer[tim]->channel[channel].eoi = timer[tim]->channel[channel].eoi; } -void timer_set_enable(uint32_t tim, uint32_t channel, uint32_t enable) +void timer_set_enable(timer_device_number_t tim, timer_channel_number_t channel, uint32_t enable) { if (enable) timer[tim]->channel[channel].control = TIMER_CR_USER_MODE | TIMER_CR_ENABLE; @@ -132,7 +132,7 @@ void timer_set_enable(uint32_t tim, uint32_t channel, uint32_t enable) timer[tim]->channel[channel].control = TIMER_CR_INTERRUPT_MASK; } -size_t timer_set_interval(uint32_t tim, uint32_t channel, size_t nanoseconds) +size_t timer_set_interval(timer_device_number_t tim, timer_channel_number_t channel, size_t nanoseconds) { uint32_t clk_freq = sysctl_clock_get_freq(SYSCTL_CLOCK_TIMER0 + tim); @@ -173,7 +173,7 @@ static int timer_isr(void *parm) return 0; } -void timer_set_irq(uint32_t tim, uint32_t channel, void(*func)(), uint32_t priority) +void timer_set_irq(timer_device_number_t tim, timer_channel_number_t channel, void(*func)(), uint32_t priority) { time_irq[tim][channel] = func; if (channel < 2) @@ -190,26 +190,3 @@ void timer_set_irq(uint32_t tim, uint32_t channel, void(*func)(), uint32_t prior } } -void pwm_set_enable(uint32_t tim, uint32_t channel, int enable) -{ - if (enable) - timer[tim]->channel[channel].control = TIMER_CR_INTERRUPT_MASK | TIMER_CR_PWM_ENABLE | TIMER_CR_USER_MODE | TIMER_CR_ENABLE; - else - timer[tim]->channel[channel].control = TIMER_CR_INTERRUPT_MASK; -} - -double pwm_set_frequency(uint32_t tim, uint32_t channel, double frequency, double duty) -{ - uint32_t clk_freq = sysctl_clock_get_freq(SYSCTL_CLOCK_TIMER0 + tim); - - int32_t periods = (int32_t)(clk_freq / frequency); - configASSERT(periods > 0 && periods <= INT32_MAX); - frequency = clk_freq / (double)periods; - - uint32_t percent = (uint32_t)(duty * periods); - timer[tim]->channel[channel].load_count = periods - percent; - timer[tim]->load_count2[channel] = percent; - - return frequency; -} - diff --git a/lib/drivers/uart.c b/lib/drivers/uart.c index e15722bc..d32c1014 100644 --- a/lib/drivers/uart.c +++ b/lib/drivers/uart.c @@ -17,7 +17,7 @@ #include "plic.h" #include "sysctl.h" #include "uart.h" -#include "common.h" +#include "utils.h" #include "atomic.h" #define __UART_BRATE_CONST 16 @@ -181,7 +181,7 @@ void uart_config(uint8_t channel, size_t baud_rate, size_t data_width, uart_stop void uartapb_init(uint8_t channel) { - sysctl_clock_enable(SYSCTL_CLOCK_UART1 + channel); + sysctl_clock_tnable(SYSCTL_CLOCK_UART1 + channel); ring_buff_t *rb = malloc(sizeof(ring_buff_t)); rb->head = 0; diff --git a/lib/drivers/uarths.c b/lib/drivers/uarths.c index 02e938c3..034c0efd 100644 --- a/lib/drivers/uarths.c +++ b/lib/drivers/uarths.c @@ -21,7 +21,7 @@ volatile uarths_t *const uarths = (volatile uarths_t *)UARTHS_BASE_ADDR; -static inline int uart_putc(char c) +static inline int uarths_putc(char c) { /* Read core id */ unsigned long core_id = current_coreid(); @@ -53,7 +53,7 @@ static inline int uart_putc(char c) return 0; } -int uart_getc(void) +int uarths_getc(void) { /* while not empty */ uarths_rxdata_t recv = uarths->rxdata; @@ -64,20 +64,20 @@ int uart_getc(void) return recv.data; } -int uart_putchar(char c) +int uarths_putchar(char c) { - return uart_putc(c); + return uarths_putc(c); } -int uart_puts(const char *s) +int uarths_puts(const char *s) { while (*s) - if (uart_putc(*s++) != 0) + if (uarths_putc(*s++) != 0) return -1; return 0; } -int uart_init() +int uarths_init(void) { uint32_t freq = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU); uint16_t div = freq / 115200 - 1; diff --git a/lib/drivers/utils.c b/lib/drivers/utils.c new file mode 100644 index 00000000..c06b6005 --- /dev/null +++ b/lib/drivers/utils.c @@ -0,0 +1,55 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "encoding.h" +#include "utils.h" + +void set_bit(volatile uint32_t* bits, uint32_t mask, uint32_t value) +{ + uint32_t org = (*bits) & ~mask; + *bits = org | (value & mask); +} + +void set_bit_offset(volatile uint32_t* bits, uint32_t mask, size_t offset, uint32_t value) +{ + set_bit(bits, mask << offset, value << offset); +} + +void set_gpio_bit(volatile uint32_t* bits, size_t offset, uint32_t value) +{ + set_bit_offset(bits, 1, offset, value); +} + +uint32_t get_bit(volatile uint32_t* bits, uint32_t mask, size_t offset) +{ + return ((*bits) & (mask << offset)) >> offset; +} + +uint32_t get_gpio_bit(volatile uint32_t* bits, size_t offset) +{ + return get_bit(bits, 1, offset); +} + +void machine_irq_enable(void) +{ + set_csr(mie, MIP_MEIP); + set_csr(mstatus, MSTATUS_MIE); +} + +void machine_irq_disable(void) +{ + clear_csr(mie, MIP_MEIP); + clear_csr(mstatus, MSTATUS_MIE); +} diff --git a/lib/drivers/wdt.c b/lib/drivers/wdt.c index fd308043..63c3c8b5 100644 --- a/lib/drivers/wdt.c +++ b/lib/drivers/wdt.c @@ -15,47 +15,45 @@ #include "wdt.h" #include "platform.h" #include "stddef.h" -#include "common.h" +#include "utils.h" #include "sysctl.h" #include "plic.h" -plic_irq_callback_t wdt_irq[2]; - volatile wdt_t *const wdt[2] = { (volatile wdt_t *)WDT0_BASE_ADDR, (volatile wdt_t *)WDT1_BASE_ADDR }; -static void wdt_enable(uint8_t id) +static void wdt_enable(wdt_device_number_t id) { wdt[id]->crr = WDT_CRR_MASK; wdt[id]->cr |= WDT_CR_ENABLE; } -static void wdt_disable(uint8_t id) +static void wdt_disable(wdt_device_number_t id) { wdt[id]->crr = WDT_CRR_MASK; wdt[id]->cr &= (~WDT_CR_ENABLE); } -static void wdt_set_timeout(uint8_t id, uint8_t timeout) +static void wdt_set_timeout(wdt_device_number_t id, uint8_t timeout) { wdt[id]->torr = WDT_TORR_TOP(timeout); } -static void wdt_response_mode(uint8_t id, uint8_t mode) +static void wdt_response_mode(wdt_device_number_t id, uint8_t mode) { wdt[id]->cr &= (~WDT_CR_RMOD_MASK); wdt[id]->cr |= mode; } -static uint64_t wdt_get_pclk(uint8_t id) +static uint64_t wdt_get_pclk(wdt_device_number_t id) { return id ? sysctl_clock_get_freq(SYSCTL_CLOCK_WDT1) : sysctl_clock_get_freq(SYSCTL_CLOCK_WDT0); } -static uint64_t log_2(uint64_t x) +static uint64_t wdt_log_2(uint64_t x) { int64_t i = 0; for (i = sizeof(uint64_t) * 8; i >= 0; i--) @@ -68,51 +66,46 @@ static uint64_t log_2(uint64_t x) return i; } -static uint8_t wdt_get_top(uint8_t id, uint64_t timeout_ms) +static uint8_t wdt_get_top(wdt_device_number_t id, uint64_t timeout_ms) { uint64_t wdt_clk = wdt_get_pclk(id); uint64_t ret = (timeout_ms * wdt_clk / 1000) >> 16; if (ret) - ret = log_2(ret); + ret = wdt_log_2(ret); if (ret > 0xf) ret = 0xf; return (uint8_t)ret; } -void wdt_feed(uint8_t id) +void wdt_feed(wdt_device_number_t id) { wdt[id]->crr = WDT_CRR_MASK; } -void wdt_clear_interrupt(uint8_t id) +void wdt_clear_interrupt(wdt_device_number_t id) { wdt[id]->eoi = wdt[id]->eoi; } -void wdt_set_irq(uint8_t id, plic_irq_callback_t on_irq) -{ - wdt_irq[id] = on_irq; -} - -int wdt_start(uint8_t id, uint64_t toms) +int wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t on_irq) { wdt_disable(id); wdt_clear_interrupt(id); - plic_irq_register(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT, wdt_irq[id], NULL); + plic_irq_register(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT, on_irq, NULL); plic_set_priority(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT, 1); plic_irq_enable(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT); sysctl_reset(id ? SYSCTL_RESET_WDT1 : SYSCTL_RESET_WDT0); sysctl_clock_set_threshold(id ? SYSCTL_THRESHOLD_WDT1 : SYSCTL_THRESHOLD_WDT0, 0); - sysctl_clock_enable(id ? SYSCTL_CLOCK_WDT1 : SYSCTL_CLOCK_WDT0); + sysctl_clock_tnable(id ? SYSCTL_CLOCK_WDT1 : SYSCTL_CLOCK_WDT0); wdt_response_mode(id, WDT_CR_RMOD_INTERRUPT); - uint8_t m_top = wdt_get_top(id, toms); + uint8_t m_top = wdt_get_top(id, time_out_ms); wdt_set_timeout(id, m_top); wdt_enable(id); return 0; } -void wdt_stop(uint8_t id) +void wdt_stop(wdt_device_number_t id) { wdt_disable(id); } diff --git a/lib/firmware/include/sd3068.h b/lib/firmware/include/sd3068.h index 696ec8e1..dfa7df36 100644 --- a/lib/firmware/include/sd3068.h +++ b/lib/firmware/include/sd3068.h @@ -31,7 +31,7 @@ typedef struct _sd_time uint32_t sec:6; } __attribute__((packed, aligned(4))) sd_time_t; -void sd3068_init(i2c_device_num_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode); +void sd3068_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode); int sd3068_write_enable(void); int sd3068_write_disable(void); int sd3068_set_time(sd_time_t time); diff --git a/lib/firmware/lcd.c b/lib/firmware/lcd.c index ec637e81..30f62b8a 100644 --- a/lib/firmware/lcd.c +++ b/lib/firmware/lcd.c @@ -16,7 +16,7 @@ #include "lcd.h" #include "nt35310.h" #include "font.h" -#include "common.h" +#include "utils.h" #include "sleep.h" static lcd_ctl_t lcd_ctl; diff --git a/lib/firmware/nt35310.c b/lib/firmware/nt35310.c index 25ea4d45..791cad9d 100644 --- a/lib/firmware/nt35310.c +++ b/lib/firmware/nt35310.c @@ -19,7 +19,7 @@ #include "spi.h" #include "dmac.h" #include "plic.h" -#include +#include #define __SPI_SYSCTL(x, y) SYSCTL_##x##_SPI##y #define _SPI_SYSCTL(x, y) __SPI_SYSCTL(x, y) @@ -36,21 +36,21 @@ void init_dcx(void) gpiohs_init(); fpioa_set_function(DCX_IO, FUNC_GPIOHS0 + DCX_GPIONUM);/*dcx*/ gpiohs_set_drive_mode(DCX_GPIONUM, GPIO_DM_Output); - gpiohs_set_pin_value(DCX_GPIONUM, GPIO_PV_High); + gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_High); fpioa_set_function(RESET_IO, FUNC_GPIOHS0 + RESET_GPIONUM);/*reset*/ gpiohs_set_drive_mode(RESET_GPIONUM, GPIO_DM_Output); - gpiohs_set_pin_value(RESET_GPIONUM, GPIO_PV_High); + gpiohs_set_pin(RESET_GPIONUM, GPIO_PV_High); } void set_dcx_control(void) { - gpiohs_set_pin_value(DCX_GPIONUM, GPIO_PV_Low); + gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_Low); } void set_dcx_data(void) { - gpiohs_set_pin_value(DCX_GPIONUM, GPIO_PV_High); + gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_High); } void pin_mux_init(void) @@ -72,7 +72,7 @@ void tft_write_command(uint8_t cmd) set_dcx_control(); spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 8); spi_config_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT, (uint8_t *)(&cmd), 1,SPI_TRANS_CHAR); + spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT, (uint8_t *)(&cmd), 1,SPI_TRANS_CHAR); } void tft_write_byte(uint8_t *data_buf, uint32_t length) @@ -80,7 +80,7 @@ void tft_write_byte(uint8_t *data_buf, uint32_t length) set_dcx_data(); spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 8); spi_config_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT, data_buf, length, SPI_TRANS_CHAR); + spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT, data_buf, length, SPI_TRANS_CHAR); } void tft_write_half(uint16_t *data_buf, uint32_t length) @@ -88,7 +88,7 @@ void tft_write_half(uint16_t *data_buf, uint32_t length) set_dcx_data(); spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 16); spi_config_non_standard(SPI_CHANNEL, 16/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_SHORT); + spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_SHORT); } void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag) @@ -97,7 +97,7 @@ void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag) spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 32); spi_config_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_INT); + spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_INT); } void tft_fill_data(uint32_t *data_buf, uint32_t length) @@ -105,6 +105,6 @@ void tft_fill_data(uint32_t *data_buf, uint32_t length) set_dcx_data(); spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 32); spi_config_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_fill_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT,data_buf, length); + spi_fill_data_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length); } diff --git a/lib/firmware/ov2640.c b/lib/firmware/ov2640.c index 0cfa7f7d..2d356118 100644 --- a/lib/firmware/ov2640.c +++ b/lib/firmware/ov2640.c @@ -229,15 +229,15 @@ int ov2640_init(void) { uint16_t index = 0; for (index = 0; ov2640_config[index][0]; index++) - dvp_sccb_write(OV2640_ADDR, ov2640_config[index][0], ov2640_config[index][1]); + dvp_sccb_write_data(OV2640_ADDR, ov2640_config[index][0], ov2640_config[index][1]); return 0; } int ov2640_read_id(uint16_t *manuf_id, uint16_t *device_id) { - dvp_sccb_write(OV2640_ADDR, 0xFF, 0x01); - *manuf_id = (dvp_sccb_read(OV2640_ADDR, 0x1C) << 8) | dvp_sccb_read(OV2640_ADDR, 0x1D); - *device_id = (dvp_sccb_read(OV2640_ADDR, 0x0A) << 8) | dvp_sccb_read(OV2640_ADDR, 0x0B); + dvp_sccb_write_data(OV2640_ADDR, 0xFF, 0x01); + *manuf_id = (dvp_sccb_read_data(OV2640_ADDR, 0x1C) << 8) | dvp_sccb_read_data(OV2640_ADDR, 0x1D); + *device_id = (dvp_sccb_read_data(OV2640_ADDR, 0x0A) << 8) | dvp_sccb_read_data(OV2640_ADDR, 0x0B); return 0; } diff --git a/lib/firmware/ov5640.c b/lib/firmware/ov5640.c index 69926c2b..1d0b0e3f 100644 --- a/lib/firmware/ov5640.c +++ b/lib/firmware/ov5640.c @@ -28,13 +28,13 @@ void hal_delay(uint32_t delay) uint8_t ov5640_wr_reg(uint16_t reg,uint8_t data) { - dvp_sccb_write(OV5640_ADDR, reg, data); + dvp_sccb_write_data(OV5640_ADDR, reg, data); return 0; } uint8_t ov5640_rd_reg(uint16_t reg) { - return dvp_sccb_read(OV5640_ADDR, reg); + return dvp_sccb_read_data(OV5640_ADDR, reg); } uint8_t ov5640_init(void) diff --git a/lib/firmware/sd3068.c b/lib/firmware/sd3068.c index 4af24e3d..5ccc59cd 100644 --- a/lib/firmware/sd3068.c +++ b/lib/firmware/sd3068.c @@ -15,14 +15,14 @@ #include #include "sd3068.h" #include "fpioa.h" -#include "common.h" +#include "utils.h" #include "sysctl.h" #include #include uint32_t i2c_bus_no = 0; -void sd3068_init(i2c_device_num_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode) +void sd3068_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode) { i2c_bus_no = i2c_num; i2c_config(i2c_num, slave_address, address_width, bus_speed_mode); From 181ecdf4d9a5597cbaf73d34a11080881c960956 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Fri, 28 Sep 2018 16:16:56 +0800 Subject: [PATCH 12/58] Modify table to enable --- lib/drivers/aes.c | 2 +- lib/drivers/dmac.c | 2 +- lib/drivers/dvp.c | 2 +- lib/drivers/fpioa.c | 2 +- lib/drivers/gpio.c | 2 +- lib/drivers/i2c.c | 2 +- lib/drivers/i2s.c | 2 +- lib/drivers/include/sysctl.h | 4 ++-- lib/drivers/pwm.c | 2 +- lib/drivers/rtc.c | 2 +- lib/drivers/sha256.c | 2 +- lib/drivers/spi.c | 2 +- lib/drivers/sysctl.c | 28 ++++++++++++++-------------- lib/drivers/timer.c | 2 +- lib/drivers/uart.c | 2 +- lib/drivers/wdt.c | 2 +- 16 files changed, 30 insertions(+), 30 deletions(-) diff --git a/lib/drivers/aes.c b/lib/drivers/aes.c index ab3f2060..ad317846 100644 --- a/lib/drivers/aes.c +++ b/lib/drivers/aes.c @@ -22,7 +22,7 @@ volatile aes_t* const aes = (volatile aes_t*)AES_BASE_ADDR; void aes_clkinit() { - sysctl_clock_tnable(SYSCTL_CLOCK_AES); + sysctl_clock_enable(SYSCTL_CLOCK_AES); sysctl_reset(SYSCTL_RESET_AES); } diff --git a/lib/drivers/dmac.c b/lib/drivers/dmac.c index a6f114cc..ce009496 100644 --- a/lib/drivers/dmac.c +++ b/lib/drivers/dmac.c @@ -547,7 +547,7 @@ void dmac_init(void) dmac_cfg_u_t dmac_cfg; dmac_reset_u_t dmac_reset; - sysctl_clock_tnable(SYSCTL_CLOCK_DMA); + sysctl_clock_enable(SYSCTL_CLOCK_DMA); dmac_reset.data = readq(&dmac->reset); dmac_reset.reset.rst = 1; diff --git a/lib/drivers/dvp.c b/lib/drivers/dvp.c index e8b6ce4b..bb4ef1e5 100644 --- a/lib/drivers/dvp.c +++ b/lib/drivers/dvp.c @@ -133,7 +133,7 @@ static void dvp_reset(void) int dvp_init(uint8_t reg_len) { g_sccb_reg_len = reg_len; - sysctl_clock_tnable(SYSCTL_CLOCK_DVP); + sysctl_clock_enable(SYSCTL_CLOCK_DVP); sysctl_reset(SYSCTL_RESET_DVP); dvp->cmos_cfg &= (~DVP_CMOS_CLK_DIV_MASK); dvp->cmos_cfg |= DVP_CMOS_CLK_DIV(0) | DVP_CMOS_CLK_ENABLE; diff --git a/lib/drivers/fpioa.c b/lib/drivers/fpioa.c index a722139d..c47681c0 100644 --- a/lib/drivers/fpioa.c +++ b/lib/drivers/fpioa.c @@ -5195,7 +5195,7 @@ int fpioa_init(void) int i = 0; /* Enable fpioa clock in system controller */ - sysctl_clock_tnable(SYSCTL_CLOCK_FPIOA); + sysctl_clock_enable(SYSCTL_CLOCK_FPIOA); /* Initialize tie */ fpioa_tie_t tie = { 0 }; diff --git a/lib/drivers/gpio.c b/lib/drivers/gpio.c index b0049daa..9d26b6a4 100644 --- a/lib/drivers/gpio.c +++ b/lib/drivers/gpio.c @@ -22,7 +22,7 @@ volatile gpio_t* const gpio = (volatile gpio_t*)GPIO_BASE_ADDR; int gpio_init(void) { - return sysctl_clock_tnable(SYSCTL_CLOCK_GPIO); + return sysctl_clock_enable(SYSCTL_CLOCK_GPIO); } void gpio_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode) diff --git a/lib/drivers/i2c.c b/lib/drivers/i2c.c index ed0170fd..a8920b94 100644 --- a/lib/drivers/i2c.c +++ b/lib/drivers/i2c.c @@ -31,7 +31,7 @@ volatile i2c_t* const i2c[3] = static void i2c_clk_init(i2c_device_number_t i2c_num) { configASSERT(i2c_num < I2C_MAX_NUM); - sysctl_clock_tnable(SYSCTL_CLOCK_I2C0 + i2c_num); + sysctl_clock_enable(SYSCTL_CLOCK_I2C0 + i2c_num); sysctl_clock_set_threshold(SYSCTL_THRESHOLD_I2C0 + i2c_num, 3); } diff --git a/lib/drivers/i2s.c b/lib/drivers/i2s.c index 8abcd773..7c97f131 100644 --- a/lib/drivers/i2s.c +++ b/lib/drivers/i2s.c @@ -27,7 +27,7 @@ volatile i2s_t *const i2s[3] = void i2s_init(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode, uint32_t channel_mask) { - sysctl_clock_tnable(SYSCTL_CLOCK_I2S0 + device_num); + sysctl_clock_enable(SYSCTL_CLOCK_I2S0 + device_num); sysctl_reset(SYSCTL_RESET_I2S0 + device_num); sysctl_clock_set_threshold(SYSCTL_THRESHOLD_I2S0 + device_num, 7); /*96k:5,44k:12,24k:23,22k:25 16k:35 sampling*/ diff --git a/lib/drivers/include/sysctl.h b/lib/drivers/include/sysctl.h index 2e6e87ff..91a69ce9 100644 --- a/lib/drivers/include/sysctl.h +++ b/lib/drivers/include/sysctl.h @@ -833,7 +833,7 @@ extern volatile sysctl_t *const sysctl; * - 0 Success * - Other Fail */ -int sysctl_clock_tnable(sysctl_clock_t clock); +int sysctl_clock_enable(sysctl_clock_t clock); /** * @brief Enable clock for peripheral @@ -982,7 +982,7 @@ int sysctl_pll_clear_slip(sysctl_pll_t pll); * - 0 Success * - Other Fail */ -int sysctl_pll_tnable(sysctl_pll_t pll); +int sysctl_pll_enable(sysctl_pll_t pll); /** * @brief Disable the PLL and power off diff --git a/lib/drivers/pwm.c b/lib/drivers/pwm.c index 2e1d446f..16a4ef45 100644 --- a/lib/drivers/pwm.c +++ b/lib/drivers/pwm.c @@ -22,7 +22,7 @@ void pwm_init(uint32_t tim) { - sysctl_clock_tnable(SYSCTL_CLOCK_TIMER0 + tim); + sysctl_clock_enable(SYSCTL_CLOCK_TIMER0 + tim); } void pwm_set_enable(uint32_t tim, uint32_t channel, int enable) diff --git a/lib/drivers/rtc.c b/lib/drivers/rtc.c index 0db469c0..826a4f7e 100644 --- a/lib/drivers/rtc.c +++ b/lib/drivers/rtc.c @@ -565,7 +565,7 @@ int rtc_init(void) /* Reset RTC */ sysctl_reset(SYSCTL_RESET_RTC); /* Enable RTC */ - sysctl_clock_tnable(SYSCTL_CLOCK_RTC); + sysctl_clock_enable(SYSCTL_CLOCK_RTC); rtc_timer_set_mode(RTC_TIMER_SETTING); /* Unprotect RTC */ rtc_protect_set(0); diff --git a/lib/drivers/sha256.c b/lib/drivers/sha256.c index 89701598..458e33ac 100644 --- a/lib/drivers/sha256.c +++ b/lib/drivers/sha256.c @@ -46,7 +46,7 @@ static const uint8_t padding[64] = int sha256_init(uint8_t dma_en, uint32_t input_size, SHA256Context_t* sc) { - sysctl_clock_tnable(SYSCTL_CLOCK_SHA); + sysctl_clock_enable(SYSCTL_CLOCK_SHA); sysctl_reset(SYSCTL_RESET_SHA); input_size = (input_size + 64) / 64; if (dma_en) diff --git a/lib/drivers/spi.c b/lib/drivers/spi.c index b77e9f77..7c904e68 100644 --- a/lib/drivers/spi.c +++ b/lib/drivers/spi.c @@ -31,7 +31,7 @@ volatile spi_t *const spi[4] = static int spi_clk_init(uint8_t spi_num) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); - sysctl_clock_tnable(SYSCTL_CLOCK_SPI0 + spi_num); + sysctl_clock_enable(SYSCTL_CLOCK_SPI0 + spi_num); sysctl_clock_set_threshold(SYSCTL_THRESHOLD_SPI0 + spi_num, 0); return 0; } diff --git a/lib/drivers/sysctl.c b/lib/drivers/sysctl.c index 0827cf14..ac0ce449 100644 --- a/lib/drivers/sysctl.c +++ b/lib/drivers/sysctl.c @@ -382,7 +382,7 @@ static int sysctl_clock_device_en(sysctl_clock_t clock, uint8_t en) return 0; } -int sysctl_clock_tnable(sysctl_clock_t clock) +int sysctl_clock_enable(sysctl_clock_t clock) { if (clock >= SYSCTL_CLOCK_MAX) return -1; @@ -797,7 +797,7 @@ int sysctl_pll_clear_slip(sysctl_pll_t pll) return sysctl_pll_is_lock(pll) ? 0 : -1; } -int sysctl_pll_tnable(sysctl_pll_t pll) +int sysctl_pll_enable(sysctl_pll_t pll) { /* * ---+ @@ -1705,9 +1705,9 @@ uint32_t sysctl_pll_fast_enable_pll(void) sysctl->pll1 = pll1; sysctl->pll2 = pll2; - sysctl_pll_tnable(SYSCTL_PLL0); - sysctl_pll_tnable(SYSCTL_PLL1); - sysctl_pll_tnable(SYSCTL_PLL2); + sysctl_pll_enable(SYSCTL_PLL0); + sysctl_pll_enable(SYSCTL_PLL1); + sysctl_pll_enable(SYSCTL_PLL2); while (sysctl_pll_is_lock(SYSCTL_PLL0) == 0) sysctl_pll_clear_slip(SYSCTL_PLL0); @@ -1716,9 +1716,9 @@ uint32_t sysctl_pll_fast_enable_pll(void) while (sysctl_pll_is_lock(SYSCTL_PLL2) == 0) sysctl_pll_clear_slip(SYSCTL_PLL2); - sysctl_clock_tnable(SYSCTL_CLOCK_PLL0); - sysctl_clock_tnable(SYSCTL_CLOCK_PLL1); - sysctl_clock_tnable(SYSCTL_CLOCK_PLL2); + sysctl_clock_enable(SYSCTL_CLOCK_PLL0); + sysctl_clock_enable(SYSCTL_CLOCK_PLL1); + sysctl_clock_enable(SYSCTL_CLOCK_PLL2); /* Set ACLK to PLL0 */ sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); @@ -1745,25 +1745,25 @@ void sysctl_set_pll_frequency(uint64_t pll0, uint64_t pll1, uint64_t pll2) { sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0); - sysctl_pll_tnable(SYSCTL_PLL0); + sysctl_pll_enable(SYSCTL_PLL0); sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, pll0); while (sysctl_pll_is_lock(SYSCTL_PLL0) == 0) sysctl_pll_clear_slip(SYSCTL_PLL0); - sysctl_clock_tnable(SYSCTL_CLOCK_PLL0); + sysctl_clock_enable(SYSCTL_CLOCK_PLL0); sysctl->clk_sel0.aclk_divider_sel = 0; sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); - sysctl_pll_tnable(SYSCTL_PLL1); + sysctl_pll_enable(SYSCTL_PLL1); sysctl_pll_set_freq(SYSCTL_PLL1, SYSCTL_SOURCE_IN0, pll1); while (sysctl_pll_is_lock(SYSCTL_PLL1) == 0) sysctl_pll_clear_slip(SYSCTL_PLL1); - sysctl_clock_tnable(SYSCTL_CLOCK_PLL1); + sysctl_clock_enable(SYSCTL_CLOCK_PLL1); - sysctl_pll_tnable(SYSCTL_PLL2); + sysctl_pll_enable(SYSCTL_PLL2); sysctl_pll_set_freq(SYSCTL_PLL2, SYSCTL_SOURCE_IN0, pll2); while (sysctl_pll_is_lock(SYSCTL_PLL2) == 0) sysctl_pll_clear_slip(SYSCTL_PLL2); - sysctl_clock_tnable(SYSCTL_CLOCK_PLL2); + sysctl_clock_enable(SYSCTL_CLOCK_PLL2); } uint32_t sysctl_set_cpu_frequency(uint32_t frequency) diff --git a/lib/drivers/timer.c b/lib/drivers/timer.c index 09f2ab7e..6ca964f1 100644 --- a/lib/drivers/timer.c +++ b/lib/drivers/timer.c @@ -28,7 +28,7 @@ volatile kendryte_timer_t *const timer[3] = void timer_init(timer_device_number_t tim) { - sysctl_clock_tnable(SYSCTL_CLOCK_TIMER0 + tim); + sysctl_clock_enable(SYSCTL_CLOCK_TIMER0 + tim); } void timer_set_clock_div(timer_device_number_t tim, uint32_t div) diff --git a/lib/drivers/uart.c b/lib/drivers/uart.c index d32c1014..8942cebe 100644 --- a/lib/drivers/uart.c +++ b/lib/drivers/uart.c @@ -181,7 +181,7 @@ void uart_config(uint8_t channel, size_t baud_rate, size_t data_width, uart_stop void uartapb_init(uint8_t channel) { - sysctl_clock_tnable(SYSCTL_CLOCK_UART1 + channel); + sysctl_clock_enable(SYSCTL_CLOCK_UART1 + channel); ring_buff_t *rb = malloc(sizeof(ring_buff_t)); rb->head = 0; diff --git a/lib/drivers/wdt.c b/lib/drivers/wdt.c index 63c3c8b5..bea86dd8 100644 --- a/lib/drivers/wdt.c +++ b/lib/drivers/wdt.c @@ -97,7 +97,7 @@ int wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t sysctl_reset(id ? SYSCTL_RESET_WDT1 : SYSCTL_RESET_WDT0); sysctl_clock_set_threshold(id ? SYSCTL_THRESHOLD_WDT1 : SYSCTL_THRESHOLD_WDT0, 0); - sysctl_clock_tnable(id ? SYSCTL_CLOCK_WDT1 : SYSCTL_CLOCK_WDT0); + sysctl_clock_enable(id ? SYSCTL_CLOCK_WDT1 : SYSCTL_CLOCK_WDT0); wdt_response_mode(id, WDT_CR_RMOD_INTERRUPT); uint8_t m_top = wdt_get_top(id, time_out_ms); wdt_set_timeout(id, m_top); From 3b29e1da0001d1f6b67fce2b500f60993bbb28c5 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Fri, 28 Sep 2018 16:49:33 +0800 Subject: [PATCH 13/58] Fix syscall overflow bug --- lib/bsp/crt.S | 395 ++++++++++++++++++++++++--------------------- lib/bsp/syscalls.c | 94 ++++++----- 2 files changed, 270 insertions(+), 219 deletions(-) diff --git a/lib/bsp/crt.S b/lib/bsp/crt.S index 31aa6780..0cc3c204 100644 --- a/lib/bsp/crt.S +++ b/lib/bsp/crt.S @@ -11,7 +11,8 @@ # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. -# include "encoding.h" + +#include "encoding.h" # define REGBYTES 8 # define STKSHIFT 17 @@ -30,37 +31,37 @@ _start: la t0, trap_entry csrw mtvec, t0 - li x1, 0 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10,0 - li x11,0 - li x12,0 - li x13,0 - li x14,0 - li x15,0 - li x16,0 - li x17,0 - li x18,0 - li x19,0 - li x20,0 - li x21,0 - li x22,0 - li x23,0 - li x24,0 - li x25,0 - li x26,0 - li x27,0 - li x28,0 - li x29,0 - li x30,0 - li x31,0 + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10,0 + li x11,0 + li x12,0 + li x13,0 + li x14,0 + li x15,0 + li x16,0 + li x17,0 + li x18,0 + li x19,0 + li x20,0 + li x21,0 + li x22,0 + li x23,0 + li x24,0 + li x25,0 + li x26,0 + li x27,0 + li x28,0 + li x29,0 + li x30,0 + li x31,0 li t0, MSTATUS_FS csrs mstatus, t0 @@ -99,10 +100,10 @@ _start: fmv.d.x f30,x0 fmv.d.x f31,x0 -.option push -.option norelax - la gp, __global_pointer$ -.option pop + .option push + .option norelax + la gp, __global_pointer$ + .option pop la tp, _end + 63 and tp, tp, -64 csrr a0, mhartid @@ -223,167 +224,199 @@ trap_entry: .handle_syscall: ld t0, 0x0(sp) addi sp, sp, REGBYTES + addi sp, sp, -64*REGBYTES + sd x1, 1*REGBYTES(sp) + sd x2, 2*REGBYTES(sp) + sd x3, 3*REGBYTES(sp) + sd x4, 4*REGBYTES(sp) + sd x5, 5*REGBYTES(sp) + sd x6, 6*REGBYTES(sp) + sd x7, 7*REGBYTES(sp) + sd x8, 8*REGBYTES(sp) + sd x9, 9*REGBYTES(sp) + sd x10, 10*REGBYTES(sp) + sd x11, 11*REGBYTES(sp) + sd x12, 12*REGBYTES(sp) + sd x13, 13*REGBYTES(sp) + sd x14, 14*REGBYTES(sp) + sd x15, 15*REGBYTES(sp) + sd x16, 16*REGBYTES(sp) + sd x17, 17*REGBYTES(sp) + + csrr a0, mcause + csrr a1, mepc + mv a2, sp + add a3, sp, 32*REGBYTES - csrr a6, mepc jal handle_syscall - csrw mepc, a1 + + csrw mepc, a0 + ld x1, 1*REGBYTES(sp) + ld x2, 2*REGBYTES(sp) + ld x3, 3*REGBYTES(sp) + ld x4, 4*REGBYTES(sp) + ld x5, 5*REGBYTES(sp) + ld x6, 6*REGBYTES(sp) + ld x7, 7*REGBYTES(sp) + ld x8, 8*REGBYTES(sp) + ld x9, 9*REGBYTES(sp) + ld x10, 10*REGBYTES(sp) + ld x11, 11*REGBYTES(sp) + ld x12, 12*REGBYTES(sp) + ld x13, 13*REGBYTES(sp) + ld x14, 14*REGBYTES(sp) + ld x15, 15*REGBYTES(sp) + ld x16, 16*REGBYTES(sp) + ld x17, 17*REGBYTES(sp) + + addi sp, sp, 64*REGBYTES mret .handle_except: ld t0, 0x0(sp) addi sp, sp, REGBYTES addi sp, sp, -64*REGBYTES - sd x0, 0 * REGBYTES(sp) - sd x1, 1 * REGBYTES(sp) - sd x2, 2 * REGBYTES(sp) - sd x3, 3 * REGBYTES(sp) - sd x4, 4 * REGBYTES(sp) - sd x5, 5 * REGBYTES(sp) - sd x6, 6 * REGBYTES(sp) - sd x7, 7 * REGBYTES(sp) - sd x8, 8 * REGBYTES(sp) - sd x9, 9 * REGBYTES(sp) - sd x10, 10 * REGBYTES(sp) - sd x11, 11 * REGBYTES(sp) - sd x12, 12 * REGBYTES(sp) - sd x13, 13 * REGBYTES(sp) - sd x14, 14 * REGBYTES(sp) - sd x15, 15 * REGBYTES(sp) - sd x16, 16 * REGBYTES(sp) - sd x17, 17 * REGBYTES(sp) - sd x18, 18 * REGBYTES(sp) - sd x19, 19 * REGBYTES(sp) - sd x20, 20 * REGBYTES(sp) - sd x21, 21 * REGBYTES(sp) - sd x22, 22 * REGBYTES(sp) - sd x23, 23 * REGBYTES(sp) - sd x24, 24 * REGBYTES(sp) - sd x25, 25 * REGBYTES(sp) - sd x26, 26 * REGBYTES(sp) - sd x27, 27 * REGBYTES(sp) - sd x28, 28 * REGBYTES(sp) - sd x29, 29 * REGBYTES(sp) - sd x30, 30 * REGBYTES(sp) - sd x31, 31 * REGBYTES(sp) - - fsd f0, ( 0 + 32) * REGBYTES(sp) - fsd f1, ( 1 + 32) * REGBYTES(sp) - fsd f2, ( 2 + 32) * REGBYTES(sp) - fsd f3, ( 3 + 32) * REGBYTES(sp) - fsd f4, ( 4 + 32) * REGBYTES(sp) - fsd f5, ( 5 + 32) * REGBYTES(sp) - fsd f6, ( 6 + 32) * REGBYTES(sp) - fsd f7, ( 7 + 32) * REGBYTES(sp) - fsd f8, ( 8 + 32) * REGBYTES(sp) - fsd f9, ( 9 + 32) * REGBYTES(sp) - fsd f10, (10 + 32) * REGBYTES(sp) - fsd f11, (11 + 32) * REGBYTES(sp) - fsd f12, (12 + 32) * REGBYTES(sp) - fsd f13, (13 + 32) * REGBYTES(sp) - fsd f14, (14 + 32) * REGBYTES(sp) - fsd f15, (15 + 32) * REGBYTES(sp) - fsd f16, (16 + 32) * REGBYTES(sp) - fsd f17, (17 + 32) * REGBYTES(sp) - fsd f18, (18 + 32) * REGBYTES(sp) - fsd f19, (19 + 32) * REGBYTES(sp) - fsd f20, (20 + 32) * REGBYTES(sp) - fsd f21, (21 + 32) * REGBYTES(sp) - fsd f22, (22 + 32) * REGBYTES(sp) - fsd f23, (23 + 32) * REGBYTES(sp) - fsd f24, (24 + 32) * REGBYTES(sp) - fsd f25, (25 + 32) * REGBYTES(sp) - fsd f26, (26 + 32) * REGBYTES(sp) - fsd f27, (27 + 32) * REGBYTES(sp) - fsd f28, (28 + 32) * REGBYTES(sp) - fsd f29, (29 + 32) * REGBYTES(sp) - fsd f30, (30 + 32) * REGBYTES(sp) - fsd f31, (31 + 32) * REGBYTES(sp) + sd x1, 1*REGBYTES(sp) + sd x2, 2*REGBYTES(sp) + sd x3, 3*REGBYTES(sp) + sd x4, 4*REGBYTES(sp) + sd x5, 5*REGBYTES(sp) + sd x6, 6*REGBYTES(sp) + sd x7, 7*REGBYTES(sp) + sd x8, 8*REGBYTES(sp) + sd x9, 9*REGBYTES(sp) + sd x10, 10*REGBYTES(sp) + sd x11, 11*REGBYTES(sp) + sd x12, 12*REGBYTES(sp) + sd x13, 13*REGBYTES(sp) + sd x14, 14*REGBYTES(sp) + sd x15, 15*REGBYTES(sp) + sd x16, 16*REGBYTES(sp) + sd x17, 17*REGBYTES(sp) + sd x18, 18*REGBYTES(sp) + sd x19, 19*REGBYTES(sp) + sd x20, 20*REGBYTES(sp) + sd x21, 21*REGBYTES(sp) + sd x22, 22*REGBYTES(sp) + sd x23, 23*REGBYTES(sp) + sd x24, 24*REGBYTES(sp) + sd x25, 25*REGBYTES(sp) + sd x26, 26*REGBYTES(sp) + sd x27, 27*REGBYTES(sp) + sd x28, 28*REGBYTES(sp) + sd x29, 29*REGBYTES(sp) + sd x30, 30*REGBYTES(sp) + sd x31, 31*REGBYTES(sp) + + fsd f0, ( 0 + 32)*REGBYTES(sp) + fsd f1, ( 1 + 32)*REGBYTES(sp) + fsd f2, ( 2 + 32)*REGBYTES(sp) + fsd f3, ( 3 + 32)*REGBYTES(sp) + fsd f4, ( 4 + 32)*REGBYTES(sp) + fsd f5, ( 5 + 32)*REGBYTES(sp) + fsd f6, ( 6 + 32)*REGBYTES(sp) + fsd f7, ( 7 + 32)*REGBYTES(sp) + fsd f8, ( 8 + 32)*REGBYTES(sp) + fsd f9, ( 9 + 32)*REGBYTES(sp) + fsd f10,( 10 + 32)*REGBYTES(sp) + fsd f11,( 11 + 32)*REGBYTES(sp) + fsd f12,( 12 + 32)*REGBYTES(sp) + fsd f13,( 13 + 32)*REGBYTES(sp) + fsd f14,( 14 + 32)*REGBYTES(sp) + fsd f15,( 15 + 32)*REGBYTES(sp) + fsd f16,( 16 + 32)*REGBYTES(sp) + fsd f17,( 17 + 32)*REGBYTES(sp) + fsd f18,( 18 + 32)*REGBYTES(sp) + fsd f19,( 19 + 32)*REGBYTES(sp) + fsd f20,( 20 + 32)*REGBYTES(sp) + fsd f21,( 21 + 32)*REGBYTES(sp) + fsd f22,( 22 + 32)*REGBYTES(sp) + fsd f23,( 23 + 32)*REGBYTES(sp) + fsd f24,( 24 + 32)*REGBYTES(sp) + fsd f25,( 25 + 32)*REGBYTES(sp) + fsd f26,( 26 + 32)*REGBYTES(sp) + fsd f27,( 27 + 32)*REGBYTES(sp) + fsd f28,( 28 + 32)*REGBYTES(sp) + fsd f29,( 29 + 32)*REGBYTES(sp) + fsd f30,( 30 + 32)*REGBYTES(sp) + fsd f31,( 31 + 32)*REGBYTES(sp) csrr a0, mcause csrr a1, mepc mv a2, sp - add a3, sp, 32 * REGBYTES + add a3, sp, 32*REGBYTES + jal handle_except - csrw mepc, a0 - ld x1, 1 * REGBYTES(sp) - ld x2, 2 * REGBYTES(sp) - ld x3, 3 * REGBYTES(sp) - ld x4, 4 * REGBYTES(sp) - ld x5, 5 * REGBYTES(sp) - ld x6, 6 * REGBYTES(sp) - ld x7, 7 * REGBYTES(sp) - ld x8, 8 * REGBYTES(sp) - ld x9, 9 * REGBYTES(sp) - ld x10, 10 * REGBYTES(sp) - ld x11, 11 * REGBYTES(sp) - ld x12, 12 * REGBYTES(sp) - ld x13, 13 * REGBYTES(sp) - ld x14, 14 * REGBYTES(sp) - ld x15, 15 * REGBYTES(sp) - ld x16, 16 * REGBYTES(sp) - ld x17, 17 * REGBYTES(sp) - ld x18, 18 * REGBYTES(sp) - ld x19, 19 * REGBYTES(sp) - ld x20, 20 * REGBYTES(sp) - ld x21, 21 * REGBYTES(sp) - ld x22, 22 * REGBYTES(sp) - ld x23, 23 * REGBYTES(sp) - ld x24, 24 * REGBYTES(sp) - ld x25, 25 * REGBYTES(sp) - ld x26, 26 * REGBYTES(sp) - ld x27, 27 * REGBYTES(sp) - ld x28, 28 * REGBYTES(sp) - ld x29, 29 * REGBYTES(sp) - ld x30, 30 * REGBYTES(sp) - ld x31, 31 * REGBYTES(sp) - - fld f0, ( 0 + 32) * REGBYTES(sp) - fld f1, ( 1 + 32) * REGBYTES(sp) - fld f2, ( 2 + 32) * REGBYTES(sp) - fld f3, ( 3 + 32) * REGBYTES(sp) - fld f4, ( 4 + 32) * REGBYTES(sp) - fld f5, ( 5 + 32) * REGBYTES(sp) - fld f6, ( 6 + 32) * REGBYTES(sp) - fld f7, ( 7 + 32) * REGBYTES(sp) - fld f8, ( 8 + 32) * REGBYTES(sp) - fld f9, ( 9 + 32) * REGBYTES(sp) - fld f10, (10 + 32) * REGBYTES(sp) - fld f11, (11 + 32) * REGBYTES(sp) - fld f12, (12 + 32) * REGBYTES(sp) - fld f13, (13 + 32) * REGBYTES(sp) - fld f14, (14 + 32) * REGBYTES(sp) - fld f15, (15 + 32) * REGBYTES(sp) - fld f16, (16 + 32) * REGBYTES(sp) - fld f17, (17 + 32) * REGBYTES(sp) - fld f18, (18 + 32) * REGBYTES(sp) - fld f19, (19 + 32) * REGBYTES(sp) - fld f20, (20 + 32) * REGBYTES(sp) - fld f21, (21 + 32) * REGBYTES(sp) - fld f22, (22 + 32) * REGBYTES(sp) - fld f23, (23 + 32) * REGBYTES(sp) - fld f24, (24 + 32) * REGBYTES(sp) - fld f25, (25 + 32) * REGBYTES(sp) - fld f26, (26 + 32) * REGBYTES(sp) - fld f27, (27 + 32) * REGBYTES(sp) - fld f28, (28 + 32) * REGBYTES(sp) - fld f29, (29 + 32) * REGBYTES(sp) - fld f30, (30 + 32) * REGBYTES(sp) - fld f31, (31 + 32) * REGBYTES(sp) - - addi sp, sp, 64 * REGBYTES + csrw mepc, a0 + ld x1, 1*REGBYTES(sp) + ld x2, 2*REGBYTES(sp) + ld x3, 3*REGBYTES(sp) + ld x4, 4*REGBYTES(sp) + ld x5, 5*REGBYTES(sp) + ld x6, 6*REGBYTES(sp) + ld x7, 7*REGBYTES(sp) + ld x8, 8*REGBYTES(sp) + ld x9, 9*REGBYTES(sp) + ld x10, 10*REGBYTES(sp) + ld x11, 11*REGBYTES(sp) + ld x12, 12*REGBYTES(sp) + ld x13, 13*REGBYTES(sp) + ld x14, 14*REGBYTES(sp) + ld x15, 15*REGBYTES(sp) + ld x16, 16*REGBYTES(sp) + ld x17, 17*REGBYTES(sp) + ld x18, 18*REGBYTES(sp) + ld x19, 19*REGBYTES(sp) + ld x20, 20*REGBYTES(sp) + ld x21, 21*REGBYTES(sp) + ld x22, 22*REGBYTES(sp) + ld x23, 23*REGBYTES(sp) + ld x24, 24*REGBYTES(sp) + ld x25, 25*REGBYTES(sp) + ld x26, 26*REGBYTES(sp) + ld x27, 27*REGBYTES(sp) + ld x28, 28*REGBYTES(sp) + ld x29, 29*REGBYTES(sp) + ld x30, 30*REGBYTES(sp) + ld x31, 31*REGBYTES(sp) + + fld f0, ( 0 + 32)*REGBYTES(sp) + fld f1, ( 1 + 32)*REGBYTES(sp) + fld f2, ( 2 + 32)*REGBYTES(sp) + fld f3, ( 3 + 32)*REGBYTES(sp) + fld f4, ( 4 + 32)*REGBYTES(sp) + fld f5, ( 5 + 32)*REGBYTES(sp) + fld f6, ( 6 + 32)*REGBYTES(sp) + fld f7, ( 7 + 32)*REGBYTES(sp) + fld f8, ( 8 + 32)*REGBYTES(sp) + fld f9, ( 9 + 32)*REGBYTES(sp) + fld f10,( 10 + 32)*REGBYTES(sp) + fld f11,( 11 + 32)*REGBYTES(sp) + fld f12,( 12 + 32)*REGBYTES(sp) + fld f13,( 13 + 32)*REGBYTES(sp) + fld f14,( 14 + 32)*REGBYTES(sp) + fld f15,( 15 + 32)*REGBYTES(sp) + fld f16,( 16 + 32)*REGBYTES(sp) + fld f17,( 17 + 32)*REGBYTES(sp) + fld f18,( 18 + 32)*REGBYTES(sp) + fld f19,( 19 + 32)*REGBYTES(sp) + fld f20,( 20 + 32)*REGBYTES(sp) + fld f21,( 21 + 32)*REGBYTES(sp) + fld f22,( 22 + 32)*REGBYTES(sp) + fld f23,( 23 + 32)*REGBYTES(sp) + fld f24,( 24 + 32)*REGBYTES(sp) + fld f25,( 25 + 32)*REGBYTES(sp) + fld f26,( 26 + 32)*REGBYTES(sp) + fld f27,( 27 + 32)*REGBYTES(sp) + fld f28,( 28 + 32)*REGBYTES(sp) + fld f29,( 29 + 32)*REGBYTES(sp) + fld f30,( 30 + 32)*REGBYTES(sp) + fld f31,( 31 + 32)*REGBYTES(sp) + + addi sp, sp, 64*REGBYTES mret -.global _init -.type _init, @function -.global _fini -.type _fini, @function -_init: -_fini: - ret - .size _init, .-_init - .size _fini, .-_fini - .section ".tdata.begin" .globl _tdata_begin _tdata_begin: diff --git a/lib/bsp/syscalls.c b/lib/bsp/syscalls.c index f981bcb8..64418c38 100644 --- a/lib/bsp/syscalls.c +++ b/lib/bsp/syscalls.c @@ -307,23 +307,11 @@ static int sys_gettimeofday(struct timeval *tp, void *tzp) return 0; } -#define SYS_RET(epc_val, err_val) \ -syscall_ret_t ret = \ -{ \ - .err = err_val, \ - .epc = epc_val \ -}; \ -return ret; - -typedef struct _syscall_ret -{ - ssize_t err; - uintptr_t epc; -} syscall_ret_t; - -syscall_ret_t __attribute__((weak)) -handle_ecall(uintptr_t a0, uintptr_t a1, uintptr_t a2, uintptr_t a3, uintptr_t a4, uintptr_t a5, uintptr_t epc, uintptr_t n) +uintptr_t __attribute__((weak)) +handle_ecall(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) { + UNUSED(cause); + UNUSED(fregs); enum syscall_id_e { SYS_ID_NOSYS, @@ -401,32 +389,31 @@ handle_ecall(uintptr_t a0, uintptr_t a1, uintptr_t a2, uintptr_t a3, uintptr_t a #pragma GCC diagnostic warning "-Woverride-init" #endif - ssize_t err = syscall_table[syscall_id_table[0xFF & n]] + regs[10] = syscall_table[syscall_id_table[0xFF & regs[17]]] ( - a0, /* a0 */ - a1, /* a1 */ - a2, /* a2 */ - a3, /* a3 */ - a4, /* a4 */ - a5, /* a5 */ - n /* n */ + regs[10], /* a0 */ + regs[11], /* a1 */ + regs[12], /* a2 */ + regs[13], /* a3 */ + regs[14], /* a4 */ + regs[15], /* a5 */ + regs[17] /* n */ ); - epc += ((*(unsigned short*)epc & 3) == 3 ? 4 : 2); - SYS_RET(epc, err); -// return epc + ((*(unsigned short *)epc & 3) == 3 ? 4 : 2); + + return epc + ((*(unsigned short *)epc & 3) == 3 ? 4 : 2); } -syscall_ret_t __attribute__((weak, alias("handle_ecall"))) -handle_ecall_u(uintptr_t a0, uintptr_t a1, uintptr_t a2, uintptr_t a3, uintptr_t a4, uintptr_t a5, uintptr_t epc, uintptr_t n); +uintptr_t __attribute__((weak, alias("handle_ecall"))) +handle_ecall_u(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]); -syscall_ret_t __attribute__((weak, alias("handle_ecall"))) -handle_ecall_h(uintptr_t a0, uintptr_t a1, uintptr_t a2, uintptr_t a3, uintptr_t a4, uintptr_t a5, uintptr_t epc, uintptr_t n); +uintptr_t __attribute__((weak, alias("handle_ecall"))) +handle_ecall_h(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]); -syscall_ret_t __attribute__((weak, alias("handle_ecall"))) -handle_ecall_s(uintptr_t a0, uintptr_t a1, uintptr_t a2, uintptr_t a3, uintptr_t a4, uintptr_t a5, uintptr_t epc, uintptr_t n); +uintptr_t __attribute__((weak, alias("handle_ecall"))) +handle_ecall_s(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]); -syscall_ret_t __attribute__((weak, alias("handle_ecall"))) -handle_ecall_m(uintptr_t a0, uintptr_t a1, uintptr_t a2, uintptr_t a3, uintptr_t a4, uintptr_t a5, uintptr_t epc, uintptr_t n); +uintptr_t __attribute__((weak, alias("handle_ecall"))) +handle_ecall_m(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]); uintptr_t __attribute__((weak)) handle_misaligned_fetch(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) @@ -625,9 +612,33 @@ handle_fault_store(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t return epc; } -syscall_ret_t handle_syscall(uintptr_t a0, uintptr_t a1, uintptr_t a2, uintptr_t a3, uintptr_t a4, uintptr_t a5, uintptr_t epc, uintptr_t n) +#if 0 +uintptr_t handle_syscall(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) +{ + + static uintptr_t (* const cause_table[])(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) = + { + [CAUSE_MISALIGNED_FETCH] = handle_misaligned_fetch, + [CAUSE_FAULT_FETCH] = handle_fault_fetch, + [CAUSE_ILLEGAL_INSTRUCTION] = handle_illegal_instruction, + [CAUSE_BREAKPOINT] = handle_breakpoint, + [CAUSE_MISALIGNED_LOAD] = handle_misaligned_load, + [CAUSE_FAULT_LOAD] = handle_fault_load, + [CAUSE_MISALIGNED_STORE] = handle_misaligned_store, + [CAUSE_FAULT_STORE] = handle_fault_store, + [CAUSE_USER_ECALL] = handle_ecall_u, + [CAUSE_SUPERVISOR_ECALL] = handle_ecall_h, + [CAUSE_HYPERVISOR_ECALL] = handle_ecall_s, + [CAUSE_MACHINE_ECALL] = handle_ecall_m, + }; + + return cause_table[cause](cause, epc, regs, fregs); +} +#else +uintptr_t handle_syscall(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) { - static syscall_ret_t (* const cause_table[])(uintptr_t a0, uintptr_t a1, uintptr_t a2, uintptr_t a3, uintptr_t a4, uintptr_t a5, uintptr_t epc, uintptr_t n) = + + static uintptr_t (* const cause_table[])(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) = { [CAUSE_USER_ECALL] = handle_ecall_u, [CAUSE_SUPERVISOR_ECALL] = handle_ecall_h, @@ -635,7 +646,7 @@ syscall_ret_t handle_syscall(uintptr_t a0, uintptr_t a1, uintptr_t a2, uintptr_t [CAUSE_MACHINE_ECALL] = handle_ecall_m, }; - return cause_table[read_csr(mcause)](a0, a1, a2, a3, a4, a5, epc, n); + return cause_table[cause](cause, epc, regs, fregs); } uintptr_t handle_except(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) { @@ -655,3 +666,10 @@ uintptr_t handle_except(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uint return cause_table[cause](cause, epc, regs, fregs); } +#endif + +size_t get_free_heap_size(void) +{ + return (size_t)(&_heap_end[0] - _heap_cur); +} + From 4c6f017f24299d8eeaeec9b90d0efb4cb7c48c4e Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Fri, 28 Sep 2018 18:28:11 +0800 Subject: [PATCH 14/58] Recover crts ld --- cmake/compile-flags.cmake | 1 - lds/kendryte.ld | 192 ++++++++--------- lib/bsp/crt.S | 439 ++++++++++++++------------------------ lib/bsp/entry_user.c | 4 +- lib/bsp/include/entry.h | 21 +- lib/bsp/interrupt.c | 22 +- lib/bsp/syscalls.c | 34 --- src/hello_world/main.c | 3 + 8 files changed, 286 insertions(+), 430 deletions(-) diff --git a/cmake/compile-flags.cmake b/cmake/compile-flags.cmake index 76f1fead..8ac7d9da 100644 --- a/cmake/compile-flags.cmake +++ b/cmake/compile-flags.cmake @@ -18,7 +18,6 @@ add_compile_flags(BOTH -ffunction-sections -fdata-sections -fstrict-volatile-bitfields - -fno-zero-initialized-in-bss -Os -ggdb ) diff --git a/lds/kendryte.ld b/lds/kendryte.ld index 740b8b21..b2fdbe88 100644 --- a/lds/kendryte.ld +++ b/lds/kendryte.ld @@ -17,9 +17,15 @@ MEMORY ram_nocache (wxa!ri) : ORIGIN = 0x40000000, LENGTH = (6 * 1024 * 1024) } +PROVIDE( _rom_start = ORIGIN(rom) ); +PROVIDE( _rom_end = ORIGIN(rom) + LENGTH(rom) ); +PROVIDE( _ram_start = ORIGIN(ram) ); PROVIDE( _ram_end = ORIGIN(ram) + LENGTH(ram) ); +PROVIDE( _io_start = 0x40000000 ); +PROVIDE( _io_end = _io_start + LENGTH(ram) ); PROVIDE( _stack_size = 1 << 17 ); + /* * The OUTPUT_ARCH command specifies the machine architecture where the * argument is one of the names used in the Kendryte library. @@ -32,14 +38,25 @@ OUTPUT_ARCH( "riscv" ) */ ENTRY(_start) +/* + * The GROUP command is special since the listed archives will be + * searched repeatedly until there are no new undefined references. We + * need this since -lc depends on -lgloss and -lgloss depends on -lc. I + * thought gcc would automatically include -lgcc when needed, but + * in this file includes it explicitly here and I was seeing link errors + * without it. + */ +/* GROUP( -lc -lgloss -lgcc ) */ + /* * The linker only pays attention to the PHDRS command when generating * an ELF output file. In other cases, the linker will simply ignore PHDRS. */ PHDRS { - DATA PT_LOAD; - DYN_DATA PT_NULL; + ram_ro PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; } /* @@ -48,31 +65,21 @@ PHDRS */ SECTIONS { - .text.start : - { - KEEP( *(.text.start) ) - } > ram : DATA - - .init : - { - KEEP (*(SORT_NONE(.init))) - } > ram : DATA - + /* Program code segment, also known as a text segment */ .text : { - *(.text.unlikely .text.*_unlikely .text.unlikely.*) - *(.text.exit .text.exit.*) + PROVIDE( _text = ABSOLUTE(.) ); + /* Initialization code segment */ + KEEP( *(.text.start) ) + *(.text.unlikely .text.unlikely.*) *(.text.startup .text.startup.*) - *(.text.hot .text.hot.*) - *(.text .stub .text.* .gnu.linkonce.t.*) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - } > ram : DATA + /* Normal code segment */ + *(.text .text.*) + *(.gnu.linkonce.t.*) - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } > ram : DATA + . = ALIGN(8); + PROVIDE( _etext = ABSOLUTE(.) ); + } >ram AT>ram :ram_ro /* Read-only data segment */ .rodata : @@ -80,28 +87,33 @@ SECTIONS *(.rdata) *(.rodata .rodata.*) *(.gnu.linkonce.r.*) - } > ram : DATA + } >ram AT>ram :ram_ro + + . = ALIGN(8); + /* Init array and fini array */ .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - } > ram : DATA + } >ram AT>ram :ram_ro + .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); - } > ram : DATA + } >ram AT>ram :ram_ro + .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); - } > ram : DATA + } >ram AT>ram :ram_ro .ctors : { @@ -123,7 +135,8 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } > ram : DATA + } >ram AT>ram :ram_ro + .dtors : { KEEP (*crtbegin.o(.dtors)) @@ -131,40 +144,64 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } > ram : DATA + } >ram AT>ram :ram_ro - .data : + . = ALIGN(8); + + .lalign : { - *(.data .data.* .gnu.linkonce.d.*) - SORT(CONSTRUCTORS) - } > ram : DATA - . = ALIGN(32); - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : + . = ALIGN(8); + PROVIDE( _data_lma = . ); + } >ram AT>ram :ram_ro + + .dalign : { - __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - } > ram : DATA - . = ALIGN(32); - _edata = .; PROVIDE (edata = .); - __bss_start = .; - .sbss : + . = ALIGN(8); + PROVIDE( _data = . ); + } >ram AT>ram :ram_init + + . = ALIGN(8); + + /* .data, .sdata and .srodata segment */ + .data : { - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } > ram : DYN_DATA - . = ALIGN(32); + /* Writable data segment (.data segment) */ + *(.data .data.*) + *(.gnu.linkonce.d.*) + /* Have _gp point to middle of sdata/sbss to maximize displacement range */ + . = ALIGN(8); + PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800); + /* Writable small data segment (.sdata segment) */ + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + /* Read-only small data segment (.srodata segment) */ + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + /* Align _edata to cache line size */ + . = ALIGN(64); + PROVIDE( _edata = ABSOLUTE(.) ); + } >ram AT>ram :ram_init + + /* .bss and .sbss segment */ .bss : { - *(.dynbss) - *(.bss .bss.* .gnu.linkonce.b.*) + PROVIDE( _bss = ABSOLUTE(.) ); + /* Writable uninitialized small data segment (.sbss segment)*/ + *(.sbss .sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + /* Uninitialized writeable data section (.bss segment)*/ + *(.bss .bss.*) + *(.gnu.linkonce.b.*) *(COMMON) - } > ram : DYN_DATA - __bss_end = .; + + . = ALIGN(8); + PROVIDE( _ebss = ABSOLUTE(.) ); + } >ram AT>ram :ram PROVIDE( _tls_data = ABSOLUTE(.) ); /* @@ -181,7 +218,7 @@ SECTIONS *(.tdata .tdata.*) *(.gnu.linkonce.td.*) KEEP( *(.tdata.end) ) - } > ram : DATA + } >ram AT>ram :ram /* Thread-local bss segment, .tbss (zero-initialized tls). */ .tbss : @@ -189,7 +226,7 @@ SECTIONS *(.tbss .tbss.*) *(.gnu.linkonce.tb.*) KEEP( *(.tbss.end) ) - } > ram : DYN_DATA + } >ram AT>ram :ram /* * End of uninitalized data segement @@ -202,47 +239,12 @@ SECTIONS . = ALIGN(64); PROVIDE( _end = ABSOLUTE(.) ); /* Leave 2 holes for stack & TLS, the size can set in kconfig */ - PROVIDE( _heap_start = ABSOLUTE(.) + _stack_size * 5 ); + PROVIDE( _heap_start = ABSOLUTE(.) + _stack_size * 2 ); PROVIDE( _tp0 = (_end + 63) & (-64) ); PROVIDE( _tp1 = _tp0 + _stack_size ); - PROVIDE( _sp0 = _tp1 + _stack_size ); - PROVIDE( _sp1 = _sp0 + _stack_size ); + PROVIDE( _sp0 = _tp0 + _stack_size ); + PROVIDE( _sp1 = _tp1 + _stack_size ); /* Heap end is at the end of memory, the memory size can set in kconfig */ PROVIDE( _heap_end = _ram_end ); - - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } } diff --git a/lib/bsp/crt.S b/lib/bsp/crt.S index 0cc3c204..6d4e6a78 100644 --- a/lib/bsp/crt.S +++ b/lib/bsp/crt.S @@ -14,6 +14,10 @@ #include "encoding.h" +# define LREG ld +# define SREG sd +# define LFREG fld +# define SFREG fsd # define REGBYTES 8 # define STKSHIFT 17 @@ -23,6 +27,11 @@ _start: j 1f .word 0xdeadbeef + .align 3 + .global g_wake_up + g_wake_up: + .dword 1 + .dword 0 1: csrw mideleg, 0 csrw medeleg, 0 @@ -63,6 +72,14 @@ _start: li x30,0 li x31,0 + csrr t0, misa + bltz t0, 1f + li a0, 1234 + j sys_exit +1: + + andi t0, t0, 1 << ('f' - 'a') + beqz t0, 1f li t0, MSTATUS_FS csrs mstatus, t0 @@ -100,6 +117,7 @@ _start: fmv.d.x f30,x0 fmv.d.x f31,x0 +1: .option push .option norelax la gp, __global_pointer$ @@ -107,6 +125,9 @@ _start: la tp, _end + 63 and tp, tp, -64 csrr a0, mhartid + li a1, 2 + +1:bgeu a0, a1, 1b sll a2, a0, STKSHIFT add tp, tp, a2 @@ -120,299 +141,149 @@ _start: .type trap_entry, @function .align 2 trap_entry: - addi sp, sp, -REGBYTES - sd t0, 0x0(sp) - csrr t0, mcause - bgez t0, .handle_syscall - - ld t0, 0x0(sp) - addi sp, sp, REGBYTES - addi sp, sp, -36*REGBYTES - - sd ra, 0 * REGBYTES(sp) - sd t0, 1 * REGBYTES(sp) - sd t1, 2 * REGBYTES(sp) - sd t2, 3 * REGBYTES(sp) - sd a0, 4 * REGBYTES(sp) - sd a1, 5 * REGBYTES(sp) - sd a2, 6 * REGBYTES(sp) - sd a3, 7 * REGBYTES(sp) - sd a4, 8 * REGBYTES(sp) - sd a5, 9 * REGBYTES(sp) - sd a6, 10 * REGBYTES(sp) - sd a7, 11 * REGBYTES(sp) - sd t3, 12 * REGBYTES(sp) - sd t4, 13 * REGBYTES(sp) - sd t5, 14 * REGBYTES(sp) - sd t6, 15 * REGBYTES(sp) + addi sp, sp, -64*REGBYTES - fsd ft0, ( 0 + 16) * REGBYTES(sp) - fsd ft1, ( 1 + 16) * REGBYTES(sp) - fsd ft2, ( 2 + 16) * REGBYTES(sp) - fsd ft3, ( 3 + 16) * REGBYTES(sp) - fsd ft4, ( 4 + 16) * REGBYTES(sp) - fsd ft5, ( 5 + 16) * REGBYTES(sp) - fsd ft6, ( 6 + 16) * REGBYTES(sp) - fsd ft7, ( 7 + 16) * REGBYTES(sp) - fsd fa0, ( 8 + 16) * REGBYTES(sp) - fsd fa1, ( 9 + 16) * REGBYTES(sp) - fsd fa2, (10 + 16) * REGBYTES(sp) - fsd fa3, (11 + 16) * REGBYTES(sp) - fsd fa4, (12 + 16) * REGBYTES(sp) - fsd fa5, (13 + 16) * REGBYTES(sp) - fsd fa6, (14 + 16) * REGBYTES(sp) - fsd fa7, (15 + 16) * REGBYTES(sp) - fsd ft8, (16 + 16) * REGBYTES(sp) - fsd ft9, (17 + 16) * REGBYTES(sp) - fsd ft10, (18 + 16) * REGBYTES(sp) - fsd ft11, (19 + 16) * REGBYTES(sp) + SREG x1, 1*REGBYTES(sp) + SREG x2, 2*REGBYTES(sp) + SREG x3, 3*REGBYTES(sp) + SREG x4, 4*REGBYTES(sp) + SREG x5, 5*REGBYTES(sp) + SREG x6, 6*REGBYTES(sp) + SREG x7, 7*REGBYTES(sp) + SREG x8, 8*REGBYTES(sp) + SREG x9, 9*REGBYTES(sp) + SREG x10, 10*REGBYTES(sp) + SREG x11, 11*REGBYTES(sp) + SREG x12, 12*REGBYTES(sp) + SREG x13, 13*REGBYTES(sp) + SREG x14, 14*REGBYTES(sp) + SREG x15, 15*REGBYTES(sp) + SREG x16, 16*REGBYTES(sp) + SREG x17, 17*REGBYTES(sp) + SREG x18, 18*REGBYTES(sp) + SREG x19, 19*REGBYTES(sp) + SREG x20, 20*REGBYTES(sp) + SREG x21, 21*REGBYTES(sp) + SREG x22, 22*REGBYTES(sp) + SREG x23, 23*REGBYTES(sp) + SREG x24, 24*REGBYTES(sp) + SREG x25, 25*REGBYTES(sp) + SREG x26, 26*REGBYTES(sp) + SREG x27, 27*REGBYTES(sp) + SREG x28, 28*REGBYTES(sp) + SREG x29, 29*REGBYTES(sp) + SREG x30, 30*REGBYTES(sp) + SREG x31, 31*REGBYTES(sp) + + SFREG f0, ( 0 + 32)*REGBYTES(sp) + SFREG f1, ( 1 + 32)*REGBYTES(sp) + SFREG f2, ( 2 + 32)*REGBYTES(sp) + SFREG f3, ( 3 + 32)*REGBYTES(sp) + SFREG f4, ( 4 + 32)*REGBYTES(sp) + SFREG f5, ( 5 + 32)*REGBYTES(sp) + SFREG f6, ( 6 + 32)*REGBYTES(sp) + SFREG f7, ( 7 + 32)*REGBYTES(sp) + SFREG f8, ( 8 + 32)*REGBYTES(sp) + SFREG f9, ( 9 + 32)*REGBYTES(sp) + SFREG f10,( 10 + 32)*REGBYTES(sp) + SFREG f11,( 11 + 32)*REGBYTES(sp) + SFREG f12,( 12 + 32)*REGBYTES(sp) + SFREG f13,( 13 + 32)*REGBYTES(sp) + SFREG f14,( 14 + 32)*REGBYTES(sp) + SFREG f15,( 15 + 32)*REGBYTES(sp) + SFREG f16,( 16 + 32)*REGBYTES(sp) + SFREG f17,( 17 + 32)*REGBYTES(sp) + SFREG f18,( 18 + 32)*REGBYTES(sp) + SFREG f19,( 19 + 32)*REGBYTES(sp) + SFREG f20,( 20 + 32)*REGBYTES(sp) + SFREG f21,( 21 + 32)*REGBYTES(sp) + SFREG f22,( 22 + 32)*REGBYTES(sp) + SFREG f23,( 23 + 32)*REGBYTES(sp) + SFREG f24,( 24 + 32)*REGBYTES(sp) + SFREG f25,( 25 + 32)*REGBYTES(sp) + SFREG f26,( 26 + 32)*REGBYTES(sp) + SFREG f27,( 27 + 32)*REGBYTES(sp) + SFREG f28,( 28 + 32)*REGBYTES(sp) + SFREG f29,( 29 + 32)*REGBYTES(sp) + SFREG f30,( 30 + 32)*REGBYTES(sp) + SFREG f31,( 31 + 32)*REGBYTES(sp) csrr a0, mcause csrr a1, mepc - + mv a2, sp + add a3, sp, 32*REGBYTES + bgez a0, .handle_syscall .handle_irq: jal handle_irq - csrw mepc, a0 - - ld ra, 0 * REGBYTES(sp) - ld t0, 1 * REGBYTES(sp) - ld t1, 2 * REGBYTES(sp) - ld t2, 3 * REGBYTES(sp) - ld a0, 4 * REGBYTES(sp) - ld a1, 5 * REGBYTES(sp) - ld a2, 6 * REGBYTES(sp) - ld a3, 7 * REGBYTES(sp) - ld a4, 8 * REGBYTES(sp) - ld a5, 9 * REGBYTES(sp) - ld a6, 10 * REGBYTES(sp) - ld a7, 11 * REGBYTES(sp) - ld t3, 12 * REGBYTES(sp) - ld t4, 13 * REGBYTES(sp) - ld t5, 14 * REGBYTES(sp) - ld t6, 15 * REGBYTES(sp) - - fld ft0, ( 0 + 16) * REGBYTES(sp) - fld ft1, ( 1 + 16) * REGBYTES(sp) - fld ft2, ( 2 + 16) * REGBYTES(sp) - fld ft3, ( 3 + 16) * REGBYTES(sp) - fld ft4, ( 4 + 16) * REGBYTES(sp) - fld ft5, ( 5 + 16) * REGBYTES(sp) - fld ft6, ( 6 + 16) * REGBYTES(sp) - fld ft7, ( 7 + 16) * REGBYTES(sp) - fld fa0, ( 8 + 16) * REGBYTES(sp) - fld fa1, ( 9 + 16) * REGBYTES(sp) - fld fa2, (10 + 16) * REGBYTES(sp) - fld fa3, (11 + 16) * REGBYTES(sp) - fld fa4, (12 + 16) * REGBYTES(sp) - fld fa5, (13 + 16) * REGBYTES(sp) - fld fa6, (14 + 16) * REGBYTES(sp) - fld fa7, (15 + 16) * REGBYTES(sp) - fld ft8, (16 + 16) * REGBYTES(sp) - fld ft9, (17 + 16) * REGBYTES(sp) - fld ft10, (18 + 16) * REGBYTES(sp) - fld ft11, (19 + 16) * REGBYTES(sp) - - addi sp, sp, 36*REGBYTES - mret - - csrr t0, mcause - addi t0, t0, -CAUSE_USER_ECALL - bltz t0, .handle_except - ld t0, 0x0(sp) - addi sp, sp, REGBYTES - + j .restore .handle_syscall: - ld t0, 0x0(sp) - addi sp, sp, REGBYTES - addi sp, sp, -64*REGBYTES - sd x1, 1*REGBYTES(sp) - sd x2, 2*REGBYTES(sp) - sd x3, 3*REGBYTES(sp) - sd x4, 4*REGBYTES(sp) - sd x5, 5*REGBYTES(sp) - sd x6, 6*REGBYTES(sp) - sd x7, 7*REGBYTES(sp) - sd x8, 8*REGBYTES(sp) - sd x9, 9*REGBYTES(sp) - sd x10, 10*REGBYTES(sp) - sd x11, 11*REGBYTES(sp) - sd x12, 12*REGBYTES(sp) - sd x13, 13*REGBYTES(sp) - sd x14, 14*REGBYTES(sp) - sd x15, 15*REGBYTES(sp) - sd x16, 16*REGBYTES(sp) - sd x17, 17*REGBYTES(sp) - - csrr a0, mcause - csrr a1, mepc - mv a2, sp - add a3, sp, 32*REGBYTES - jal handle_syscall - - csrw mepc, a0 - ld x1, 1*REGBYTES(sp) - ld x2, 2*REGBYTES(sp) - ld x3, 3*REGBYTES(sp) - ld x4, 4*REGBYTES(sp) - ld x5, 5*REGBYTES(sp) - ld x6, 6*REGBYTES(sp) - ld x7, 7*REGBYTES(sp) - ld x8, 8*REGBYTES(sp) - ld x9, 9*REGBYTES(sp) - ld x10, 10*REGBYTES(sp) - ld x11, 11*REGBYTES(sp) - ld x12, 12*REGBYTES(sp) - ld x13, 13*REGBYTES(sp) - ld x14, 14*REGBYTES(sp) - ld x15, 15*REGBYTES(sp) - ld x16, 16*REGBYTES(sp) - ld x17, 17*REGBYTES(sp) - - addi sp, sp, 64*REGBYTES - mret - -.handle_except: - ld t0, 0x0(sp) - addi sp, sp, REGBYTES - addi sp, sp, -64*REGBYTES - sd x1, 1*REGBYTES(sp) - sd x2, 2*REGBYTES(sp) - sd x3, 3*REGBYTES(sp) - sd x4, 4*REGBYTES(sp) - sd x5, 5*REGBYTES(sp) - sd x6, 6*REGBYTES(sp) - sd x7, 7*REGBYTES(sp) - sd x8, 8*REGBYTES(sp) - sd x9, 9*REGBYTES(sp) - sd x10, 10*REGBYTES(sp) - sd x11, 11*REGBYTES(sp) - sd x12, 12*REGBYTES(sp) - sd x13, 13*REGBYTES(sp) - sd x14, 14*REGBYTES(sp) - sd x15, 15*REGBYTES(sp) - sd x16, 16*REGBYTES(sp) - sd x17, 17*REGBYTES(sp) - sd x18, 18*REGBYTES(sp) - sd x19, 19*REGBYTES(sp) - sd x20, 20*REGBYTES(sp) - sd x21, 21*REGBYTES(sp) - sd x22, 22*REGBYTES(sp) - sd x23, 23*REGBYTES(sp) - sd x24, 24*REGBYTES(sp) - sd x25, 25*REGBYTES(sp) - sd x26, 26*REGBYTES(sp) - sd x27, 27*REGBYTES(sp) - sd x28, 28*REGBYTES(sp) - sd x29, 29*REGBYTES(sp) - sd x30, 30*REGBYTES(sp) - sd x31, 31*REGBYTES(sp) - - fsd f0, ( 0 + 32)*REGBYTES(sp) - fsd f1, ( 1 + 32)*REGBYTES(sp) - fsd f2, ( 2 + 32)*REGBYTES(sp) - fsd f3, ( 3 + 32)*REGBYTES(sp) - fsd f4, ( 4 + 32)*REGBYTES(sp) - fsd f5, ( 5 + 32)*REGBYTES(sp) - fsd f6, ( 6 + 32)*REGBYTES(sp) - fsd f7, ( 7 + 32)*REGBYTES(sp) - fsd f8, ( 8 + 32)*REGBYTES(sp) - fsd f9, ( 9 + 32)*REGBYTES(sp) - fsd f10,( 10 + 32)*REGBYTES(sp) - fsd f11,( 11 + 32)*REGBYTES(sp) - fsd f12,( 12 + 32)*REGBYTES(sp) - fsd f13,( 13 + 32)*REGBYTES(sp) - fsd f14,( 14 + 32)*REGBYTES(sp) - fsd f15,( 15 + 32)*REGBYTES(sp) - fsd f16,( 16 + 32)*REGBYTES(sp) - fsd f17,( 17 + 32)*REGBYTES(sp) - fsd f18,( 18 + 32)*REGBYTES(sp) - fsd f19,( 19 + 32)*REGBYTES(sp) - fsd f20,( 20 + 32)*REGBYTES(sp) - fsd f21,( 21 + 32)*REGBYTES(sp) - fsd f22,( 22 + 32)*REGBYTES(sp) - fsd f23,( 23 + 32)*REGBYTES(sp) - fsd f24,( 24 + 32)*REGBYTES(sp) - fsd f25,( 25 + 32)*REGBYTES(sp) - fsd f26,( 26 + 32)*REGBYTES(sp) - fsd f27,( 27 + 32)*REGBYTES(sp) - fsd f28,( 28 + 32)*REGBYTES(sp) - fsd f29,( 29 + 32)*REGBYTES(sp) - fsd f30,( 30 + 32)*REGBYTES(sp) - fsd f31,( 31 + 32)*REGBYTES(sp) - - csrr a0, mcause - csrr a1, mepc - mv a2, sp - add a3, sp, 32*REGBYTES - - jal handle_except - +.restore: csrw mepc, a0 - ld x1, 1*REGBYTES(sp) - ld x2, 2*REGBYTES(sp) - ld x3, 3*REGBYTES(sp) - ld x4, 4*REGBYTES(sp) - ld x5, 5*REGBYTES(sp) - ld x6, 6*REGBYTES(sp) - ld x7, 7*REGBYTES(sp) - ld x8, 8*REGBYTES(sp) - ld x9, 9*REGBYTES(sp) - ld x10, 10*REGBYTES(sp) - ld x11, 11*REGBYTES(sp) - ld x12, 12*REGBYTES(sp) - ld x13, 13*REGBYTES(sp) - ld x14, 14*REGBYTES(sp) - ld x15, 15*REGBYTES(sp) - ld x16, 16*REGBYTES(sp) - ld x17, 17*REGBYTES(sp) - ld x18, 18*REGBYTES(sp) - ld x19, 19*REGBYTES(sp) - ld x20, 20*REGBYTES(sp) - ld x21, 21*REGBYTES(sp) - ld x22, 22*REGBYTES(sp) - ld x23, 23*REGBYTES(sp) - ld x24, 24*REGBYTES(sp) - ld x25, 25*REGBYTES(sp) - ld x26, 26*REGBYTES(sp) - ld x27, 27*REGBYTES(sp) - ld x28, 28*REGBYTES(sp) - ld x29, 29*REGBYTES(sp) - ld x30, 30*REGBYTES(sp) - ld x31, 31*REGBYTES(sp) - - fld f0, ( 0 + 32)*REGBYTES(sp) - fld f1, ( 1 + 32)*REGBYTES(sp) - fld f2, ( 2 + 32)*REGBYTES(sp) - fld f3, ( 3 + 32)*REGBYTES(sp) - fld f4, ( 4 + 32)*REGBYTES(sp) - fld f5, ( 5 + 32)*REGBYTES(sp) - fld f6, ( 6 + 32)*REGBYTES(sp) - fld f7, ( 7 + 32)*REGBYTES(sp) - fld f8, ( 8 + 32)*REGBYTES(sp) - fld f9, ( 9 + 32)*REGBYTES(sp) - fld f10,( 10 + 32)*REGBYTES(sp) - fld f11,( 11 + 32)*REGBYTES(sp) - fld f12,( 12 + 32)*REGBYTES(sp) - fld f13,( 13 + 32)*REGBYTES(sp) - fld f14,( 14 + 32)*REGBYTES(sp) - fld f15,( 15 + 32)*REGBYTES(sp) - fld f16,( 16 + 32)*REGBYTES(sp) - fld f17,( 17 + 32)*REGBYTES(sp) - fld f18,( 18 + 32)*REGBYTES(sp) - fld f19,( 19 + 32)*REGBYTES(sp) - fld f20,( 20 + 32)*REGBYTES(sp) - fld f21,( 21 + 32)*REGBYTES(sp) - fld f22,( 22 + 32)*REGBYTES(sp) - fld f23,( 23 + 32)*REGBYTES(sp) - fld f24,( 24 + 32)*REGBYTES(sp) - fld f25,( 25 + 32)*REGBYTES(sp) - fld f26,( 26 + 32)*REGBYTES(sp) - fld f27,( 27 + 32)*REGBYTES(sp) - fld f28,( 28 + 32)*REGBYTES(sp) - fld f29,( 29 + 32)*REGBYTES(sp) - fld f30,( 30 + 32)*REGBYTES(sp) - fld f31,( 31 + 32)*REGBYTES(sp) + LREG x1, 1*REGBYTES(sp) + LREG x2, 2*REGBYTES(sp) + LREG x3, 3*REGBYTES(sp) + LREG x4, 4*REGBYTES(sp) + LREG x5, 5*REGBYTES(sp) + LREG x6, 6*REGBYTES(sp) + LREG x7, 7*REGBYTES(sp) + LREG x8, 8*REGBYTES(sp) + LREG x9, 9*REGBYTES(sp) + LREG x10, 10*REGBYTES(sp) + LREG x11, 11*REGBYTES(sp) + LREG x12, 12*REGBYTES(sp) + LREG x13, 13*REGBYTES(sp) + LREG x14, 14*REGBYTES(sp) + LREG x15, 15*REGBYTES(sp) + LREG x16, 16*REGBYTES(sp) + LREG x17, 17*REGBYTES(sp) + LREG x18, 18*REGBYTES(sp) + LREG x19, 19*REGBYTES(sp) + LREG x20, 20*REGBYTES(sp) + LREG x21, 21*REGBYTES(sp) + LREG x22, 22*REGBYTES(sp) + LREG x23, 23*REGBYTES(sp) + LREG x24, 24*REGBYTES(sp) + LREG x25, 25*REGBYTES(sp) + LREG x26, 26*REGBYTES(sp) + LREG x27, 27*REGBYTES(sp) + LREG x28, 28*REGBYTES(sp) + LREG x29, 29*REGBYTES(sp) + LREG x30, 30*REGBYTES(sp) + LREG x31, 31*REGBYTES(sp) + + LFREG f0, ( 0 + 32)*REGBYTES(sp) + LFREG f1, ( 1 + 32)*REGBYTES(sp) + LFREG f2, ( 2 + 32)*REGBYTES(sp) + LFREG f3, ( 3 + 32)*REGBYTES(sp) + LFREG f4, ( 4 + 32)*REGBYTES(sp) + LFREG f5, ( 5 + 32)*REGBYTES(sp) + LFREG f6, ( 6 + 32)*REGBYTES(sp) + LFREG f7, ( 7 + 32)*REGBYTES(sp) + LFREG f8, ( 8 + 32)*REGBYTES(sp) + LFREG f9, ( 9 + 32)*REGBYTES(sp) + LFREG f10,( 10 + 32)*REGBYTES(sp) + LFREG f11,( 11 + 32)*REGBYTES(sp) + LFREG f12,( 12 + 32)*REGBYTES(sp) + LFREG f13,( 13 + 32)*REGBYTES(sp) + LFREG f14,( 14 + 32)*REGBYTES(sp) + LFREG f15,( 15 + 32)*REGBYTES(sp) + LFREG f16,( 16 + 32)*REGBYTES(sp) + LFREG f17,( 17 + 32)*REGBYTES(sp) + LFREG f18,( 18 + 32)*REGBYTES(sp) + LFREG f19,( 19 + 32)*REGBYTES(sp) + LFREG f20,( 20 + 32)*REGBYTES(sp) + LFREG f21,( 21 + 32)*REGBYTES(sp) + LFREG f22,( 22 + 32)*REGBYTES(sp) + LFREG f23,( 23 + 32)*REGBYTES(sp) + LFREG f24,( 24 + 32)*REGBYTES(sp) + LFREG f25,( 25 + 32)*REGBYTES(sp) + LFREG f26,( 26 + 32)*REGBYTES(sp) + LFREG f27,( 27 + 32)*REGBYTES(sp) + LFREG f28,( 28 + 32)*REGBYTES(sp) + LFREG f29,( 29 + 32)*REGBYTES(sp) + LFREG f30,( 30 + 32)*REGBYTES(sp) + LFREG f31,( 31 + 32)*REGBYTES(sp) addi sp, sp, 64*REGBYTES mret diff --git a/lib/bsp/entry_user.c b/lib/bsp/entry_user.c index d2b5a07c..b2e059ba 100644 --- a/lib/bsp/entry_user.c +++ b/lib/bsp/entry_user.c @@ -34,7 +34,7 @@ volatile char * const ram = (volatile char*)RAM_BASE_ADDR; extern char _heap_start[]; extern char _heap_end[]; -static volatile uint32_t g_wake_up[2] = { 1, 0 }; +extern volatile uint64_t g_wake_up[2]; void thread_entry(int core_id) { @@ -63,6 +63,8 @@ void _init_bsp(int core_id, int number_of_cores) if (core_id == 0) { + /* Copy lma data to memory */ + init_lma(); /* Initialize bss data to 0 */ init_bss(); /* Init FPIOA */ diff --git a/lib/bsp/include/entry.h b/lib/bsp/include/entry.h index 42ab2c34..2aded614 100644 --- a/lib/bsp/include/entry.h +++ b/lib/bsp/include/entry.h @@ -23,14 +23,27 @@ extern "C" { #endif +static inline void init_lma(void) +{ + extern unsigned int _data_lma; + extern unsigned int _data; + extern unsigned int _edata; + unsigned int *src, *dst; + + src = &_data_lma; + dst = &_data; + while (dst < &_edata) + *dst++ = *src++; +} + static inline void init_bss(void) { - extern unsigned int __bss_start; - extern unsigned int __bss_end; + extern unsigned int _bss; + extern unsigned int _ebss; unsigned int *dst; - dst = &__bss_start; - while (dst < &__bss_end) + dst = &_bss; + while (dst < &_ebss) *dst++ = 0; } diff --git a/lib/bsp/interrupt.c b/lib/bsp/interrupt.c index e616f399..802a6e5b 100644 --- a/lib/bsp/interrupt.c +++ b/lib/bsp/interrupt.c @@ -22,27 +22,25 @@ #include "syscalls.h" #include "syslog.h" -static const char* TAG = "INTERRUPT"; - uintptr_t __attribute__((weak)) -handle_irq_dummy(uintptr_t cause, uintptr_t epc) +handle_irq_dummy(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) { - LOGE(TAG, "unhandled interrupt: Cause 0x%016lx, EPC 0x%016lx\n", cause, epc); + dump_core("unhandled interrupt", cause, epc, regs, fregs); sys_exit(1337); return epc; } uintptr_t __attribute__((weak, alias("handle_irq_dummy"))) -handle_irq_m_soft(uintptr_t cause, uintptr_t epc); +handle_irq_m_soft(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]); uintptr_t __attribute__((weak, alias("handle_irq_dummy"))) -handle_irq_m_timer(uintptr_t cause, uintptr_t epc); +handle_irq_m_timer(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]); uintptr_t __attribute__((weak, alias("handle_irq_dummy"))) -handle_irq_m_ext(uintptr_t cause, uintptr_t epc); +handle_irq_m_ext(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]); uintptr_t __attribute__((weak)) -handle_irq(uintptr_t cause, uintptr_t epc) +handle_irq(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) { #if defined(__GNUC__) #pragma GCC diagnostic ignored "-Woverride-init" @@ -50,17 +48,19 @@ handle_irq(uintptr_t cause, uintptr_t epc) /* clang-format off */ static uintptr_t (* const irq_table[])( uintptr_t cause, - uintptr_t epc) = + uintptr_t epc, + uintptr_t regs[32], + uintptr_t fregs[32]) = { [0 ... 14] = handle_irq_dummy, [IRQ_M_SOFT] = handle_irq_m_soft, [IRQ_M_TIMER] = handle_irq_m_timer, [IRQ_M_EXT] = handle_irq_m_ext, }; - /* clang-format on */ + /* clang-format on */ #if defined(__GNUC__) #pragma GCC diagnostic warning "-Woverride-init" #endif - return irq_table[cause & CAUSE_MACHINE_IRQ_REASON_MASK](cause, epc); + return irq_table[cause & CAUSE_MACHINE_IRQ_REASON_MASK](cause, epc, regs, fregs); } diff --git a/lib/bsp/syscalls.c b/lib/bsp/syscalls.c index 64418c38..b4b10b29 100644 --- a/lib/bsp/syscalls.c +++ b/lib/bsp/syscalls.c @@ -612,7 +612,6 @@ handle_fault_store(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t return epc; } -#if 0 uintptr_t handle_syscall(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) { @@ -634,39 +633,6 @@ uintptr_t handle_syscall(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uin return cause_table[cause](cause, epc, regs, fregs); } -#else -uintptr_t handle_syscall(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) -{ - - static uintptr_t (* const cause_table[])(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) = - { - [CAUSE_USER_ECALL] = handle_ecall_u, - [CAUSE_SUPERVISOR_ECALL] = handle_ecall_h, - [CAUSE_HYPERVISOR_ECALL] = handle_ecall_s, - [CAUSE_MACHINE_ECALL] = handle_ecall_m, - }; - - return cause_table[cause](cause, epc, regs, fregs); -} -uintptr_t handle_except(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) -{ - - static uintptr_t (* const cause_table[])(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) = - { - [CAUSE_MISALIGNED_FETCH] = handle_misaligned_fetch, - [CAUSE_FAULT_FETCH] = handle_fault_fetch, - [CAUSE_ILLEGAL_INSTRUCTION] = handle_illegal_instruction, - [CAUSE_BREAKPOINT] = handle_breakpoint, - [CAUSE_MISALIGNED_LOAD] = handle_misaligned_load, - [CAUSE_FAULT_LOAD] = handle_fault_load, - [CAUSE_MISALIGNED_STORE] = handle_misaligned_store, - [CAUSE_FAULT_STORE] = handle_fault_store, - }; - - return cause_table[cause](cause, epc, regs, fregs); -} - -#endif size_t get_free_heap_size(void) { diff --git a/src/hello_world/main.c b/src/hello_world/main.c index 0afd43ea..0e987e38 100644 --- a/src/hello_world/main.c +++ b/src/hello_world/main.c @@ -15,6 +15,9 @@ #include #include "sleep.h" #include "encoding.h" +float power[512]; +uint64_t fft_out_data[256]; + int main() { uint64_t core_id = current_coreid(); From 404d12d7556030162a6f65442eb2586f44df4bc9 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Sun, 30 Sep 2018 00:11:31 +0800 Subject: [PATCH 15/58] Modify drivers --- lib/drivers/dmac.c | 17 +- lib/drivers/dvp.c | 10 +- lib/drivers/gpio.c | 8 +- lib/drivers/gpiohs.c | 33 +-- lib/drivers/i2s.c | 350 ++++++++++++++-------------- lib/drivers/include/dmac.h | 4 +- lib/drivers/include/dvp.h | 14 +- lib/drivers/include/fpioa.h | 44 ++-- lib/drivers/include/gpio_common.h | 20 +- lib/drivers/include/gpiohs.h | 9 - lib/drivers/include/i2s.h | 368 ++++-------------------------- lib/drivers/include/pwm.h | 23 +- lib/drivers/include/rtc.h | 196 ---------------- lib/drivers/include/spi.h | 102 +++++---- lib/drivers/include/timer.h | 8 +- lib/drivers/include/uart.h | 34 ++- lib/drivers/include/uarths.h | 2 +- lib/drivers/include/wdt.h | 17 -- lib/drivers/pwm.c | 18 +- lib/drivers/rtc.c | 17 +- lib/drivers/spi.c | 61 ++--- lib/drivers/timer.c | 122 +++++----- lib/drivers/uart.c | 25 +- lib/firmware/nt35310.c | 17 +- lib/firmware/ov2640.c | 8 +- lib/firmware/ov5640.c | 4 +- lib/firmware/w25qxx.c | 34 +-- 27 files changed, 538 insertions(+), 1027 deletions(-) diff --git a/lib/drivers/dmac.c b/lib/drivers/dmac.c index ce009496..37c569c1 100644 --- a/lib/drivers/dmac.c +++ b/lib/drivers/dmac.c @@ -26,8 +26,11 @@ volatile dmac_t *const dmac = (dmac_t *)DMAC_BASE_ADDR; static int is_memory(uintptr_t address) { - enum { mem_len = 6 * 1024 * 1024 }; - return ((address >= 0x80000000) && (address < 0x80000000 + mem_len)) || ((address >= 0x40000000) && (address < 0x40000000 + mem_len)) || (address == 0x50450040); + enum { + mem_len = 6 * 1024 * 1024, + mem_no_cache_len = 8 * 1024 * 1024, + }; + return ((address >= 0x80000000) && (address < 0x80000000 + mem_len)) || ((address >= 0x40000000) && (address < 0x40000000 + mem_no_cache_len)) || (address == 0x50450040); } uint64_t dmac_read_id(void) @@ -335,7 +338,7 @@ int dmac_set_channel_config(dmac_channel_number_t channel_num, static int dmac_set_channel_param(dmac_channel_number_t channel_num, void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, - dmac_burst_trans_length_t dmac_msize, + dmac_burst_trans_length_t dmac_burst_size, dmac_transfer_width_t dmac_trans_width, uint32_t blockSize) { @@ -383,8 +386,8 @@ static int dmac_set_channel_param(dmac_channel_number_t channel_num, ctl.ch_ctl.src_tr_width = dmac_trans_width; ctl.ch_ctl.dst_tr_width = dmac_trans_width; /* transfer width */ - ctl.ch_ctl.src_msize = dmac_msize; - ctl.ch_ctl.dst_msize = dmac_msize; + ctl.ch_ctl.src_msize = dmac_burst_size; + ctl.ch_ctl.dst_msize = dmac_burst_size; writeq(ctl.data, &dmac->channel[channel_num].ctl); @@ -695,13 +698,13 @@ void dmac_set_shadow_invalid_flag(dmac_channel_number_t channel_num) void dmac_set_single_mode(dmac_channel_number_t channel_num, void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, - dmac_burst_trans_length_t dmac_msize, + dmac_burst_trans_length_t dmac_burst_size, dmac_transfer_width_t dmac_trans_width, uint32_t blockSize) { dmac_channel_disable(channel_num); dmac_set_channel_param(channel_num, src, dest, src_inc,dest_inc, - dmac_msize,dmac_trans_width,blockSize); + dmac_burst_size,dmac_trans_width,blockSize); dmac_enable(); dmac_chanel_interrupt_clear(channel_num); /* clear interrupt */ dmac_enable_channel_interrupt_status(channel_num); diff --git a/lib/drivers/dvp.c b/lib/drivers/dvp.c index bb4ef1e5..b54ef08e 100644 --- a/lib/drivers/dvp.c +++ b/lib/drivers/dvp.c @@ -52,7 +52,7 @@ static void dvp_sccb_start_transfer(void) ; } -int dvp_sccb_write_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data) +int dvp_sccb_send_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data) { uint32_t tmp; @@ -75,7 +75,7 @@ int dvp_sccb_write_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data) return 0; } -uint8_t dvp_sccb_read_data(uint8_t dev_addr, uint16_t reg_addr) +uint8_t dvp_sccb_receive_data(uint8_t dev_addr, uint16_t reg_addr) { uint32_t tmp; @@ -241,9 +241,9 @@ int dvp_get_image(void) return 0; } -void dvp_config_interrupt(uint32_t interrupt, uint8_t status) +void dvp_config_interrupt(uint32_t interrupt, uint8_t enable) { - if (status) + if (enable) dvp->dvp_cfg |= interrupt; else dvp->dvp_cfg &= (~interrupt); @@ -272,7 +272,7 @@ void dvp_disable_auto(void) dvp->dvp_cfg &= (~DVP_CFG_AUTO_ENABLE); } -void dvp_set_output_enable(size_t index, int enable) +void dvp_set_output_enable(dvp_output_mode_t index, int enable) { configASSERT(index < 2); diff --git a/lib/drivers/gpio.c b/lib/drivers/gpio.c index 9d26b6a4..9a051b93 100644 --- a/lib/drivers/gpio.c +++ b/lib/drivers/gpio.c @@ -36,19 +36,19 @@ void gpio_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode) switch (mode) { - case GPIO_DM_Input: + case GPIO_DM_INPUT: pull = FPIOA_PULL_NONE; dir = 0; break; - case GPIO_DM_InputPullDown: + case GPIO_DM_INPUT_PULL_DOWN: pull = FPIOA_PULL_DOWN; dir = 0; break; - case GPIO_DM_InputPullUp: + case GPIO_DM_INPUT_PULL_UP: pull = FPIOA_PULL_UP; dir = 0; break; - case GPIO_DM_Output: + case GPIO_DM_OUTPUT: pull = FPIOA_PULL_DOWN; dir = 1; break; diff --git a/lib/drivers/gpiohs.c b/lib/drivers/gpiohs.c index 91093045..b094497b 100644 --- a/lib/drivers/gpiohs.c +++ b/lib/drivers/gpiohs.c @@ -29,15 +29,6 @@ typedef struct _gpiohs_pin_context gpiohs_pin_context pin_context[32]; -int gpiohs_init(void) -{ - gpiohs->rise_ie.u32[0] = 0; - gpiohs->rise_ip.u32[0] = 0xFFFFFFFF; - gpiohs->fall_ie.u32[0] = 0; - gpiohs->fall_ip.u32[0] = 0xFFFFFFFF; - return 0; -} - void gpiohs_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode) { configASSERT(pin < GPIOHS_MAX_PINNO); @@ -49,19 +40,19 @@ void gpiohs_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode) switch (mode) { - case GPIO_DM_Input: + case GPIO_DM_INPUT: pull = FPIOA_PULL_NONE; dir = 0; break; - case GPIO_DM_InputPullDown: + case GPIO_DM_INPUT_PULL_DOWN: pull = FPIOA_PULL_DOWN; dir = 0; break; - case GPIO_DM_InputPullUp: + case GPIO_DM_INPUT_PULL_UP: pull = FPIOA_PULL_UP; dir = 0; break; - case GPIO_DM_Output: + case GPIO_DM_OUTPUT: pull = FPIOA_PULL_DOWN; dir = 1; break; @@ -93,18 +84,18 @@ void gpiohs_set_pin_edge(uint8_t pin, gpio_pin_edge_t edge) uint32_t rise, fall, irq; switch (edge) { - case GPIO_PE_None: + case GPIO_PE_NONE: rise = fall = irq = 0; break; - case GPIO_PE_Falling: + case GPIO_PE_FALLING: rise = 0; fall = irq = 1; break; - case GPIO_PE_Rising: + case GPIO_PE_RISING: fall = 0; rise = irq = 1; break; - case GPIO_PE_Both: + case GPIO_PE_BOTH: rise = fall = irq = 1; break; default: @@ -124,18 +115,18 @@ int gpiohs_pin_onchange_isr(void* userdata) uint32_t rise, fall; switch (ctx->edge) { - case GPIO_PE_None: + case GPIO_PE_NONE: rise = fall = 0; break; - case GPIO_PE_Falling: + case GPIO_PE_FALLING: rise = 0; fall = 1; break; - case GPIO_PE_Rising: + case GPIO_PE_RISING: fall = 0; rise = 1; break; - case GPIO_PE_Both: + case GPIO_PE_BOTH: rise = fall = 1; break; default: diff --git a/lib/drivers/i2s.c b/lib/drivers/i2s.c index 7c97f131..0bf4c731 100644 --- a/lib/drivers/i2s.c +++ b/lib/drivers/i2s.c @@ -25,90 +25,31 @@ volatile i2s_t *const i2s[3] = (volatile i2s_t *)I2S2_BASE_ADDR }; -void i2s_init(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode, uint32_t channel_mask) -{ - sysctl_clock_enable(SYSCTL_CLOCK_I2S0 + device_num); - sysctl_reset(SYSCTL_RESET_I2S0 + device_num); - sysctl_clock_set_threshold(SYSCTL_THRESHOLD_I2S0 + device_num, 7); - /*96k:5,44k:12,24k:23,22k:25 16k:35 sampling*/ - /*sample rate*32bit*2 =75MHz/((N+1)*2) */ - i2s_device_enable(device_num); - i2s_disable_block(device_num, TRANSMITTER); - i2s_disable_block(device_num, RECEIVER); - - if (rxtx_mode == TRANSMITTER) - { - for (int i=0; i<4; i++) - { - if ((channel_mask & 0x3) == 0x3) - { - i2s_set_mask_interrupt(device_num, CHANNEL_0 + i, 1, 1, 1, 1); - i2s_transimit_enable(device_num, CHANNEL_0 + i); - } - else - { - i2s_transmit_channel_enable(device_num, CHANNEL_0 + i, 0); - } - channel_mask >>= 2; - } - i2s_transmit_dma_enable(device_num, 1); - } - else - { - for (int i=0; i<4; i++) - { - if ((channel_mask & 0x3) == 0x3) - { - i2s_set_mask_interrupt(device_num, CHANNEL_0 + i, 1, 1, 1, 1); - i2s_receive_enable(device_num, CHANNEL_0 + i); - } - else - { - i2s_receive_channel_enable(device_num, CHANNEL_0 + i, 0); - } - channel_mask >>= 2; - } - i2s_receive_dma_enable(device_num, 1); - } -} - -void i2s_device_enable(i2s_device_number_t device_num) +int i2s_receive_channel_enable(i2s_device_number_t device_num, + i2s_channel_num_t channel_num, uint32_t enable) { - ier_t u_ier; + rer_t u_rer; - u_ier.reg_data = readl(&i2s[device_num]->ier); - u_ier.ier.ien = 1; - writel(u_ier.reg_data, &i2s[device_num]->ier); + if (channel_num < I2S_CHANNEL_0 || channel_num > I2S_CHANNEL_3) + return -1; + u_rer.reg_data = readl(&i2s[device_num]->channel[channel_num].rer); + u_rer.rer.rxchenx = enable; + writel(u_rer.reg_data, &i2s[device_num]->channel[channel_num].rer); + return 0; } -void i2s_dev_enable(i2s_device_number_t device_num, uint32_t enable) +int i2s_transmit_channel_enable(i2s_device_number_t device_num, + i2s_channel_num_t channel_num, uint32_t enable) { - ier_t u_ier; - - u_ier.reg_data = readl(&i2s[device_num]->ier); - u_ier.ier.ien = enable; - writel(u_ier.reg_data, &i2s[device_num]->ier); -} + ter_t u_ter; -void i2s_disable_block(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode) -{ - irer_t u_irer; - iter_t u_iter; + if (channel_num < I2S_CHANNEL_0 || channel_num > I2S_CHANNEL_3) + return -1; - if (rxtx_mode == RECEIVER) - { - u_irer.reg_data = readl(&i2s[device_num]->irer); - u_irer.irer.rxen = 0; - writel(u_irer.reg_data, &i2s[device_num]->irer); - /* Receiver block disable */ - } - else - { - u_iter.reg_data = readl(&i2s[device_num]->iter); - u_iter.iter.txen = 0; - writel(u_iter.reg_data, &i2s[device_num]->iter); - /* Transmitter block disable */ - } + u_ter.reg_data = readl(&i2s[device_num]->channel[channel_num].ter); + u_ter.ter.txchenx = enable; + writel(u_ter.reg_data, &i2s[device_num]->channel[channel_num].ter); + return 0; } void i2s_receive_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num) @@ -118,7 +59,7 @@ void i2s_receive_enable(i2s_device_number_t device_num, i2s_channel_num_t channe u_irer.reg_data = readl(&i2s[device_num]->irer); u_irer.irer.rxen = 1; writel(u_irer.reg_data, &i2s[device_num]->irer); - /* Receiver block enable */ + /* I2S_RECEIVER block enable */ i2s_receive_channel_enable(device_num, channel_num, 1); /* Receive channel enable */ @@ -131,90 +72,51 @@ void i2s_transimit_enable(i2s_device_number_t device_num, i2s_channel_num_t chan u_iter.reg_data = readl(&i2s[device_num]->iter); u_iter.iter.txen = 1; writel(u_iter.reg_data, &i2s[device_num]->iter); - /* Transmitter block enable */ + /* I2S_TRANSMITTER block enable */ i2s_transmit_channel_enable(device_num, channel_num, 1); /* Transmit channel enable */ } -void i2s_rx_channel_configure(i2s_device_number_t device_num, - i2s_channel_num_t channel_num, - word_length_t word_length, - word_select_cycles_t word_select_size, - fifo_threshold_t trigger_level, - i2s_work_mode_t word_mode) +void i2s_set_enable(i2s_device_number_t device_num, uint32_t enable) { - i2s_receive_channel_enable(device_num, channel_num, 0); - /* Receive channel disable */ - - writel(0, &i2s[device_num]->channel[channel_num].ter); - /* disable tx */ - - writel(1, &i2s[device_num]->channel[channel_num].rff); - /* flash individual fifo */ - - writel(1, &i2s[device_num]->rxffr); - /* flush tx fifo*/ - - i2s_set_rx_word_length(device_num, word_length, channel_num); - /* Word buf_len is RESOLUTION_32_BIT */ - - i2s_master_configure(device_num, - word_select_size, NO_CLOCK_GATING, word_mode); - /* word select size is 32 bits,no clock gating */ - - i2s_set_rx_threshold(device_num, trigger_level, channel_num); - /* Interrupt trigger when FIFO level is 8 */ - - readl(&i2s[device_num]->channel[channel_num].ror); - readl(&i2s[device_num]->channel[channel_num].tor); + ier_t u_ier; - i2s_receive_channel_enable(device_num, channel_num, 1); + u_ier.reg_data = readl(&i2s[device_num]->ier); + u_ier.ier.ien = enable; + writel(u_ier.reg_data, &i2s[device_num]->ier); } -void i2s_tx_channel_configure(i2s_device_number_t device_num, - i2s_channel_num_t channel_num, - word_length_t word_length, - word_select_cycles_t word_select_size, - fifo_threshold_t trigger_level, - i2s_work_mode_t word_mode) +void i2s_disable_block(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode) { - writel(0, &i2s[device_num]->channel[channel_num].rer); - /* disable rx */ - - i2s_transmit_channel_enable(device_num, channel_num, 0); - /* Transmit channel disable */ - - writel(1, &i2s[device_num]->txffr); - /* flush tx fifo */ - writel(1, &i2s[device_num]->channel[channel_num].tff); - /* flush individual fifo */ + irer_t u_irer; + iter_t u_iter; - if (word_length == RESOLUTION_16_BIT) + if (rxtx_mode == I2S_RECEIVER) { - i2s_transmit_dma_divide(I2S_DEVICE_0, 1); + u_irer.reg_data = readl(&i2s[device_num]->irer); + u_irer.irer.rxen = 0; + writel(u_irer.reg_data, &i2s[device_num]->irer); + /* I2S_RECEIVER block disable */ + } + else + { + u_iter.reg_data = readl(&i2s[device_num]->iter); + u_iter.iter.txen = 0; + writel(u_iter.reg_data, &i2s[device_num]->iter); + /* I2S_TRANSMITTER block disable */ } - i2s_set_tx_word_length(device_num, word_length, channel_num); - /* Word buf_len is RESOLUTION_16_BIT */ - - i2s_master_configure(device_num, word_select_size, NO_CLOCK_GATING, word_mode); - /* word select size is 16 bits,gating after 16 bit */ - - i2s_set_tx_threshold(device_num, trigger_level, channel_num); - /* Interrupt trigger when FIFO level is 8 */ - - i2s_transmit_channel_enable(device_num, channel_num, 1); } int i2s_set_rx_word_length(i2s_device_number_t device_num, - word_length_t word_length, + i2s_word_length_t word_length, i2s_channel_num_t channel_num) { rcr_tcr_t u_rcr; if (word_length > RESOLUTION_32_BIT || word_length < IGNORE_WORD_LENGTH) return -1; - if (channel_num < CHANNEL_0 || channel_num > CHANNEL_3) + if (channel_num < I2S_CHANNEL_0 || channel_num > I2S_CHANNEL_3) return -1; u_rcr.reg_data = readl(&i2s[device_num]->channel[channel_num].rcr); @@ -224,14 +126,14 @@ int i2s_set_rx_word_length(i2s_device_number_t device_num, } int i2s_set_tx_word_length(i2s_device_number_t device_num, - word_length_t word_length, + i2s_word_length_t word_length, i2s_channel_num_t channel_num) { rcr_tcr_t u_tcr; if (word_length > RESOLUTION_32_BIT || word_length < IGNORE_WORD_LENGTH) return -1; - if (channel_num < CHANNEL_0 || channel_num > CHANNEL_3) + if (channel_num < I2S_CHANNEL_0 || channel_num > I2S_CHANNEL_3) return -1; u_tcr.reg_data = readl(&i2s[device_num]->channel[channel_num].tcr); @@ -241,8 +143,8 @@ int i2s_set_tx_word_length(i2s_device_number_t device_num, } int i2s_master_configure(i2s_device_number_t device_num, - word_select_cycles_t word_select_size, - sclk_gating_cycles_t gating_cycles, + i2s_word_select_cycles_t word_select_size, + i2s_sclk_gating_cycles_t gating_cycles, i2s_work_mode_t word_mode) { ccr_t u_ccr; @@ -270,14 +172,14 @@ int i2s_master_configure(i2s_device_number_t device_num, } int i2s_set_rx_threshold(i2s_device_number_t device_num, - fifo_threshold_t threshold, + i2s_fifo_threshold_t threshold, i2s_channel_num_t channel_num) { rfcr_t u_rfcr; if (threshold < TRIGGER_LEVEL_1 || threshold > TRIGGER_LEVEL_16) return -1; - if (channel_num < CHANNEL_0 || channel_num > CHANNEL_3) + if (channel_num < I2S_CHANNEL_0 || channel_num > I2S_CHANNEL_3) return -1; u_rfcr.reg_data = readl(&i2s[device_num]->channel[channel_num].rfcr); @@ -288,14 +190,14 @@ int i2s_set_rx_threshold(i2s_device_number_t device_num, } int i2s_set_tx_threshold(i2s_device_number_t device_num, - fifo_threshold_t threshold, + i2s_fifo_threshold_t threshold, i2s_channel_num_t channel_num) { tfcr_t u_tfcr; if (threshold < TRIGGER_LEVEL_1 || threshold > TRIGGER_LEVEL_16) return -1; - if (channel_num < CHANNEL_0 || channel_num > CHANNEL_3) + if (channel_num < I2S_CHANNEL_0 || channel_num > I2S_CHANNEL_3) return -1; u_tfcr.reg_data = readl(&i2s[device_num]->channel[channel_num].tfcr); @@ -311,7 +213,7 @@ int i2s_set_mask_interrupt(i2s_device_number_t device_num, { imr_t u_imr; - if (channel_num < CHANNEL_0 || channel_num > CHANNEL_3) + if (channel_num < I2S_CHANNEL_0 || channel_num > I2S_CHANNEL_3) return -1; u_imr.reg_data = readl(&i2s[device_num]->channel[channel_num].imr); @@ -336,33 +238,6 @@ int i2s_set_mask_interrupt(i2s_device_number_t device_num, return 0; } -int i2s_receive_channel_enable(i2s_device_number_t device_num, - i2s_channel_num_t channel_num, uint32_t enable) -{ - rer_t u_rer; - - if (channel_num < CHANNEL_0 || channel_num > CHANNEL_3) - return -1; - u_rer.reg_data = readl(&i2s[device_num]->channel[channel_num].rer); - u_rer.rer.rxchenx = enable; - writel(u_rer.reg_data, &i2s[device_num]->channel[channel_num].rer); - return 0; -} - -int i2s_transmit_channel_enable(i2s_device_number_t device_num, - i2s_channel_num_t channel_num, uint32_t enable) -{ - ter_t u_ter; - - if (channel_num < CHANNEL_0 || channel_num > CHANNEL_3) - return -1; - - u_ter.reg_data = readl(&i2s[device_num]->channel[channel_num].ter); - u_ter.ter.txchenx = enable; - writel(u_ter.reg_data, &i2s[device_num]->channel[channel_num].ter); - return 0; -} - int i2s_transmit_dma_enable(i2s_device_number_t device_num, uint32_t enable) { ccr_t u_ccr; @@ -461,7 +336,7 @@ int i2s_send_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint32_t right_buffer = 0; uint32_t i = 0; uint32_t j = 0; - if (channel_num < CHANNEL_0 || channel_num > CHANNEL_3) + if (channel_num < I2S_CHANNEL_0 || channel_num > I2S_CHANNEL_3) return -1; buf_len = buf_len / (single_length / 8) / 2; /* sample num */ @@ -506,7 +381,7 @@ int i2s_send_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, return 0; } -void i2s_send_data_dma(i2s_device_number_t device_num, void *pcm, size_t buf_len, dmac_channel_number_t channel_num) +void i2s_send_data_dma(i2s_device_number_t device_num, void *buf, size_t buf_len, dmac_channel_number_t channel_num) { static uint8_t dmac_init_flag[6] = {0,0,0,0,0,0}; if(dmac_init_flag[channel_num]) @@ -514,7 +389,7 @@ void i2s_send_data_dma(i2s_device_number_t device_num, void *pcm, size_t buf_len else dmac_init_flag[channel_num] = 1; sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_I2S0_TX_REQ + device_num * 2); - dmac_set_single_mode(channel_num, pcm, (void *)(&i2s[device_num]->txdma), DMAC_ADDR_INCREMENT, + dmac_set_single_mode(channel_num, buf, (void *)(&i2s[device_num]->txdma), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, buf_len); } @@ -622,3 +497,120 @@ int i2s_play(i2s_device_number_t device_num,dmac_channel_number_t channel_num, return 0; } +void i2s_rx_channel_config(i2s_device_number_t device_num, + i2s_channel_num_t channel_num, + i2s_word_length_t word_length, + i2s_word_select_cycles_t word_select_size, + i2s_fifo_threshold_t trigger_level, + i2s_work_mode_t word_mode) +{ + i2s_receive_channel_enable(device_num, channel_num, 0); + /* Receive channel disable */ + + writel(0, &i2s[device_num]->channel[channel_num].ter); + /* disable tx */ + + writel(1, &i2s[device_num]->channel[channel_num].rff); + /* flash individual fifo */ + + writel(1, &i2s[device_num]->rxffr); + /* flush tx fifo*/ + + i2s_set_rx_word_length(device_num, word_length, channel_num); + /* Word buf_len is RESOLUTION_32_BIT */ + + i2s_master_configure(device_num, + word_select_size, NO_CLOCK_GATING, word_mode); + /* word select size is 32 bits,no clock gating */ + + i2s_set_rx_threshold(device_num, trigger_level, channel_num); + /* Interrupt trigger when FIFO level is 8 */ + + readl(&i2s[device_num]->channel[channel_num].ror); + readl(&i2s[device_num]->channel[channel_num].tor); + + i2s_receive_channel_enable(device_num, channel_num, 1); +} + +void i2s_tx_channel_config(i2s_device_number_t device_num, + i2s_channel_num_t channel_num, + i2s_word_length_t word_length, + i2s_word_select_cycles_t word_select_size, + i2s_fifo_threshold_t trigger_level, + i2s_work_mode_t word_mode) +{ + writel(0, &i2s[device_num]->channel[channel_num].rer); + /* disable rx */ + + i2s_transmit_channel_enable(device_num, channel_num, 0); + /* Transmit channel disable */ + + writel(1, &i2s[device_num]->txffr); + /* flush tx fifo */ + writel(1, &i2s[device_num]->channel[channel_num].tff); + /* flush individual fifo */ + + if (word_length == RESOLUTION_16_BIT) + { + i2s_transmit_dma_divide(I2S_DEVICE_0, 1); + } + i2s_set_tx_word_length(device_num, word_length, channel_num); + /* Word buf_len is RESOLUTION_16_BIT */ + + i2s_master_configure(device_num, word_select_size, NO_CLOCK_GATING, word_mode); + /* word select size is 16 bits,gating after 16 bit */ + + i2s_set_tx_threshold(device_num, trigger_level, channel_num); + /* Interrupt trigger when FIFO level is 8 */ + + i2s_transmit_channel_enable(device_num, channel_num, 1); +} + + +void i2s_init(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode, uint32_t channel_mask) +{ + sysctl_clock_enable(SYSCTL_CLOCK_I2S0 + device_num); + sysctl_reset(SYSCTL_RESET_I2S0 + device_num); + sysctl_clock_set_threshold(SYSCTL_THRESHOLD_I2S0 + device_num, 7); + /*96k:5,44k:12,24k:23,22k:25 16k:35 sampling*/ + /*sample rate*32bit*2 =75MHz/((N+1)*2) */ + i2s_set_enable(device_num, 1); + i2s_disable_block(device_num, I2S_TRANSMITTER); + i2s_disable_block(device_num, I2S_RECEIVER); + + if (rxtx_mode == I2S_TRANSMITTER) + { + for (int i=0; i<4; i++) + { + if ((channel_mask & 0x3) == 0x3) + { + i2s_set_mask_interrupt(device_num, I2S_CHANNEL_0 + i, 1, 1, 1, 1); + i2s_transimit_enable(device_num, I2S_CHANNEL_0 + i); + } + else + { + i2s_transmit_channel_enable(device_num, I2S_CHANNEL_0 + i, 0); + } + channel_mask >>= 2; + } + i2s_transmit_dma_enable(device_num, 1); + } + else + { + for (int i=0; i<4; i++) + { + if ((channel_mask & 0x3) == 0x3) + { + i2s_set_mask_interrupt(device_num, I2S_CHANNEL_0 + i, 1, 1, 1, 1); + i2s_receive_enable(device_num, I2S_CHANNEL_0 + i); + } + else + { + i2s_receive_channel_enable(device_num, I2S_CHANNEL_0 + i, 0); + } + channel_mask >>= 2; + } + i2s_receive_dma_enable(device_num, 1); + } +} + diff --git a/lib/drivers/include/dmac.h b/lib/drivers/include/dmac.h index c41d348b..e733ba74 100644 --- a/lib/drivers/include/dmac.h +++ b/lib/drivers/include/dmac.h @@ -1412,14 +1412,14 @@ void dmac_init(void); * @param[in] dest Dmac dest * @param[in] src_inc Source address increase or not * @param[in] dest_inc Dest address increase or not - * @param[in] dmac_msize Dmac burst length + * @param[in] dmac_burst_size Dmac burst length * @param[in] dmac_trans_width Dmac transfer data width * @param[in] blockSize Dmac transfer length * */ void dmac_set_single_mode(dmac_channel_number_t channel_num, void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, - dmac_burst_trans_length_t dmac_msize, + dmac_burst_trans_length_t dmac_burst_size, dmac_transfer_width_t dmac_trans_width, uint32_t blockSize); diff --git a/lib/drivers/include/dvp.h b/lib/drivers/include/dvp.h index 35ff866a..e3c43b4d 100644 --- a/lib/drivers/include/dvp.h +++ b/lib/drivers/include/dvp.h @@ -95,6 +95,12 @@ typedef struct _dvp #define DVP_STS_SCCB_EN_WE 0x02000000 /* clang-format on */ +typedef enum _dvp_output_mode +{ + DVP_OUTPUT_AI, + DVP_OUTPUT_DISPLAY, +} dvp_output_mode_t; + /** * @brief DVP object instance */ @@ -207,7 +213,7 @@ int dvp_get_image(void); * - 0 Success * - Other Fail */ -int dvp_sccb_write_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data); +int dvp_sccb_send_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data); /** * @brief Use SCCB read register @@ -217,7 +223,7 @@ int dvp_sccb_write_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data); * * @return The register value */ -uint8_t dvp_sccb_read_data(uint8_t dev_addr, uint16_t reg_addr); +uint8_t dvp_sccb_receive_data(uint8_t dev_addr, uint16_t reg_addr); /** * @brief Enable dvp burst @@ -236,7 +242,7 @@ void dvp_disable_burst(void); * @param[in] status 0:disable 1:enable * */ -void dvp_config_interrupt(uint32_t interrupt, uint8_t status); +void dvp_config_interrupt(uint32_t interrupt, uint8_t enable); /** * @brief Get dvp interrupt status @@ -275,7 +281,7 @@ void dvp_disable_auto(void); * @param[in] enable 0:disable, 1:enable * */ -void dvp_set_output_enable(size_t index, int enable); +void dvp_set_output_enable(dvp_output_mode_t index, int enable); #ifdef __cplusplus } diff --git a/lib/drivers/include/fpioa.h b/lib/drivers/include/fpioa.h index 396dcdbb..873eb47d 100644 --- a/lib/drivers/include/fpioa.h +++ b/lib/drivers/include/fpioa.h @@ -72,8 +72,8 @@ extern "C" { * | 15 | SPI0_SS3 | SPI0 Chip Select 3 | * | 16 | SPI0_ARB | SPI0 Arbitration | * | 17 | SPI0_SCLK | SPI0 Serial Clock | - * | 18 | UARTHS_RX | UART High speed Receiver | - * | 19 | UARTHS_TX | UART High speed Transmitter | + * | 18 | UARTHS_RX | UART High speed I2S_RECEIVER | + * | 19 | UARTHS_TX | UART High speed I2S_TRANSMITTER | * | 20 | CLK_IN1 | Clock Input 1 | * | 21 | CLK_IN2 | Clock Input 2 | * | 22 | CLK_SPI1 | Clock SPI1 | @@ -118,12 +118,12 @@ extern "C" { * | 61 | GPIO5 | GPIO pin 5 | * | 62 | GPIO6 | GPIO pin 6 | * | 63 | GPIO7 | GPIO pin 7 | - * | 64 | UART1_RX | UART1 Receiver | - * | 65 | UART1_TX | UART1 Transmitter | - * | 66 | UART2_RX | UART2 Receiver | - * | 67 | UART2_TX | UART2 Transmitter | - * | 68 | UART3_RX | UART3 Receiver | - * | 69 | UART3_TX | UART3 Transmitter | + * | 64 | UART1_RX | UART1 I2S_RECEIVER | + * | 65 | UART1_TX | UART1 I2S_TRANSMITTER | + * | 66 | UART2_RX | UART2 I2S_RECEIVER | + * | 67 | UART2_TX | UART2 I2S_TRANSMITTER | + * | 68 | UART3_RX | UART3 I2S_RECEIVER | + * | 69 | UART3_TX | UART3 I2S_TRANSMITTER | * | 70 | SPI1_D0 | SPI1 Data 0 | * | 71 | SPI1_D1 | SPI1 Data 1 | * | 72 | SPI1_D2 | SPI1 Data 2 | @@ -213,7 +213,7 @@ extern "C" { * | 156 | UART1_OUT1 | UART1 User-designated Output 1 | * | 157 | UART1_SIR_OUT | UART1 Serial Infrared Output | * | 158 | UART1_BAUD | UART1 Transmit Clock Output | - * | 159 | UART1_RE | UART1 Receiver Output Enable | + * | 159 | UART1_RE | UART1 I2S_RECEIVER Output Enable | * | 160 | UART1_DE | UART1 Driver Output Enable | * | 161 | UART1_RS485_EN | UART1 RS485 Enable | * | 162 | UART2_CTS | UART2 Clear To Send | @@ -227,7 +227,7 @@ extern "C" { * | 170 | UART2_OUT1 | UART2 User-designated Output 1 | * | 171 | UART2_SIR_OUT | UART2 Serial Infrared Output | * | 172 | UART2_BAUD | UART2 Transmit Clock Output | - * | 173 | UART2_RE | UART2 Receiver Output Enable | + * | 173 | UART2_RE | UART2 I2S_RECEIVER Output Enable | * | 174 | UART2_DE | UART2 Driver Output Enable | * | 175 | UART2_RS485_EN | UART2 RS485 Enable | * | 176 | UART3_CTS | UART3 Clear To Send | @@ -241,7 +241,7 @@ extern "C" { * | 184 | UART3_OUT1 | UART3 User-designated Output 1 | * | 185 | UART3_SIR_OUT | UART3 Serial Infrared Output | * | 186 | UART3_BAUD | UART3 Transmit Clock Output | - * | 187 | UART3_RE | UART3 Receiver Output Enable | + * | 187 | UART3_RE | UART3 I2S_RECEIVER Output Enable | * | 188 | UART3_DE | UART3 Driver Output Enable | * | 189 | UART3_RS485_EN | UART3 RS485 Enable | * | 190 | TIMER0_TOGGLE1 | TIMER0 Toggle Output 1 | @@ -337,8 +337,8 @@ typedef enum _fpioa_function FUNC_SPI0_SS3 = 15, /*!< SPI0 Chip Select 3 */ FUNC_SPI0_ARB = 16, /*!< SPI0 Arbitration */ FUNC_SPI0_SCLK = 17, /*!< SPI0 Serial Clock */ - FUNC_UARTHS_RX = 18, /*!< UART High speed Receiver */ - FUNC_UARTHS_TX = 19, /*!< UART High speed Transmitter */ + FUNC_UARTHS_RX = 18, /*!< UART High speed I2S_RECEIVER */ + FUNC_UARTHS_TX = 19, /*!< UART High speed I2S_TRANSMITTER */ FUNC_CLK_IN1 = 20, /*!< Clock Input 1 */ FUNC_CLK_IN2 = 21, /*!< Clock Input 2 */ FUNC_CLK_SPI1 = 22, /*!< Clock SPI1 */ @@ -383,12 +383,12 @@ typedef enum _fpioa_function FUNC_GPIO5 = 61, /*!< GPIO pin 5 */ FUNC_GPIO6 = 62, /*!< GPIO pin 6 */ FUNC_GPIO7 = 63, /*!< GPIO pin 7 */ - FUNC_UART1_RX = 64, /*!< UART1 Receiver */ - FUNC_UART1_TX = 65, /*!< UART1 Transmitter */ - FUNC_UART2_RX = 66, /*!< UART2 Receiver */ - FUNC_UART2_TX = 67, /*!< UART2 Transmitter */ - FUNC_UART3_RX = 68, /*!< UART3 Receiver */ - FUNC_UART3_TX = 69, /*!< UART3 Transmitter */ + FUNC_UART1_RX = 64, /*!< UART1 I2S_RECEIVER */ + FUNC_UART1_TX = 65, /*!< UART1 I2S_TRANSMITTER */ + FUNC_UART2_RX = 66, /*!< UART2 I2S_RECEIVER */ + FUNC_UART2_TX = 67, /*!< UART2 I2S_TRANSMITTER */ + FUNC_UART3_RX = 68, /*!< UART3 I2S_RECEIVER */ + FUNC_UART3_TX = 69, /*!< UART3 I2S_TRANSMITTER */ FUNC_SPI1_D0 = 70, /*!< SPI1 Data 0 */ FUNC_SPI1_D1 = 71, /*!< SPI1 Data 1 */ FUNC_SPI1_D2 = 72, /*!< SPI1 Data 2 */ @@ -478,7 +478,7 @@ typedef enum _fpioa_function FUNC_UART1_OUT1 = 156, /*!< UART1 User-designated Output 1 */ FUNC_UART1_SIR_OUT = 157, /*!< UART1 Serial Infrared Output */ FUNC_UART1_BAUD = 158, /*!< UART1 Transmit Clock Output */ - FUNC_UART1_RE = 159, /*!< UART1 Receiver Output Enable */ + FUNC_UART1_RE = 159, /*!< UART1 I2S_RECEIVER Output Enable */ FUNC_UART1_DE = 160, /*!< UART1 Driver Output Enable */ FUNC_UART1_RS485_EN = 161, /*!< UART1 RS485 Enable */ FUNC_UART2_CTS = 162, /*!< UART2 Clear To Send */ @@ -492,7 +492,7 @@ typedef enum _fpioa_function FUNC_UART2_OUT1 = 170, /*!< UART2 User-designated Output 1 */ FUNC_UART2_SIR_OUT = 171, /*!< UART2 Serial Infrared Output */ FUNC_UART2_BAUD = 172, /*!< UART2 Transmit Clock Output */ - FUNC_UART2_RE = 173, /*!< UART2 Receiver Output Enable */ + FUNC_UART2_RE = 173, /*!< UART2 I2S_RECEIVER Output Enable */ FUNC_UART2_DE = 174, /*!< UART2 Driver Output Enable */ FUNC_UART2_RS485_EN = 175, /*!< UART2 RS485 Enable */ FUNC_UART3_CTS = 176, /*!< UART3 Clear To Send */ @@ -506,7 +506,7 @@ typedef enum _fpioa_function FUNC_UART3_OUT1 = 184, /*!< UART3 User-designated Output 1 */ FUNC_UART3_SIR_OUT = 185, /*!< UART3 Serial Infrared Output */ FUNC_UART3_BAUD = 186, /*!< UART3 Transmit Clock Output */ - FUNC_UART3_RE = 187, /*!< UART3 Receiver Output Enable */ + FUNC_UART3_RE = 187, /*!< UART3 I2S_RECEIVER Output Enable */ FUNC_UART3_DE = 188, /*!< UART3 Driver Output Enable */ FUNC_UART3_RS485_EN = 189, /*!< UART3 RS485 Enable */ FUNC_TIMER0_TOGGLE1 = 190, /*!< TIMER0 Toggle Output 1 */ diff --git a/lib/drivers/include/gpio_common.h b/lib/drivers/include/gpio_common.h index 3899bd7d..40e52745 100644 --- a/lib/drivers/include/gpio_common.h +++ b/lib/drivers/include/gpio_common.h @@ -21,22 +21,18 @@ extern "C" { typedef enum _gpio_drive_mode { - GPIO_DM_Input, - GPIO_DM_InputPullDown, - GPIO_DM_InputPullUp, - GPIO_DM_Output, - GPIO_DM_OutputOpenDrain, - GPIO_DM_OutputOpenDrainPullUp, - GPIO_DM_OutputOpenSource, - GPIO_DM_OutputOpenSourcePullDown + GPIO_DM_INPUT, + GPIO_DM_INPUT_PULL_DOWN, + GPIO_DM_INPUT_PULL_UP, + GPIO_DM_OUTPUT, } gpio_drive_mode_t; typedef enum _gpio_pin_edge { - GPIO_PE_None, - GPIO_PE_Falling, - GPIO_PE_Rising, - GPIO_PE_Both + GPIO_PE_NONE, + GPIO_PE_FALLING, + GPIO_PE_RISING, + GPIO_PE_BOTH } gpio_pin_edge_t; typedef enum _gpio_pin_value diff --git a/lib/drivers/include/gpiohs.h b/lib/drivers/include/gpiohs.h index 30a934fd..48a1c104 100644 --- a/lib/drivers/include/gpiohs.h +++ b/lib/drivers/include/gpiohs.h @@ -198,15 +198,6 @@ typedef struct _gpiohs */ extern volatile gpiohs_t *const gpiohs; -/** - * @brief Gpiohs initialize - * - * @return Result - * - 0 Success - * - Other Fail - */ -int gpiohs_init(void); - /** * @brief Set Gpiohs drive mode * diff --git a/lib/drivers/include/i2s.h b/lib/drivers/include/i2s.h index 0d7ca67c..1a6d3e6e 100644 --- a/lib/drivers/include/i2s.h +++ b/lib/drivers/include/i2s.h @@ -39,16 +39,16 @@ typedef enum _i2s_device_number typedef enum _i2s_channel_num { - CHANNEL_0 = 0, - CHANNEL_1 = 1, - CHANNEL_2 = 2, - CHANNEL_3 = 3 + I2S_CHANNEL_0 = 0, + I2S_CHANNEL_1 = 1, + I2S_CHANNEL_2 = 2, + I2S_CHANNEL_3 = 3 } i2s_channel_num_t; typedef enum _i2s_transmit { - TRANSMITTER = 0, - RECEIVER = 1 + I2S_TRANSMITTER = 0, + I2S_RECEIVER = 1 } i2s_transmit_t; typedef enum _i2s_work_mode @@ -70,7 +70,7 @@ typedef enum _sclk_gating_cycles CLOCK_CYCLES_20 = 0x3, /* Gating after 24 sclk cycles */ CLOCK_CYCLES_24 = 0x4 -} sclk_gating_cycles_t; +} i2s_sclk_gating_cycles_t; typedef enum _word_select_cycles { @@ -80,24 +80,23 @@ typedef enum _word_select_cycles SCLK_CYCLES_24 = 0x1, /* 32 sclk cycles */ SCLK_CYCLES_32 = 0x2 - -} word_select_cycles_t; +} i2s_word_select_cycles_t; typedef enum _word_length { /* Ignore the word length */ IGNORE_WORD_LENGTH = 0x0, - /* 12-bit data resolution of the receiver */ + /* 12-bit data resolution of the I2S_RECEIVER */ RESOLUTION_12_BIT = 0x1, - /* 16-bit data resolution of the receiver */ + /* 16-bit data resolution of the I2S_RECEIVER */ RESOLUTION_16_BIT = 0x2, - /* 20-bit data resolution of the receiver */ + /* 20-bit data resolution of the I2S_RECEIVER */ RESOLUTION_20_BIT = 0x3, - /* 24-bit data resolution of the receiver */ + /* 24-bit data resolution of the I2S_RECEIVER */ RESOLUTION_24_BIT = 0x4, - /* 32-bit data resolution of the receiver */ + /* 32-bit data resolution of the I2S_RECEIVER */ RESOLUTION_32_BIT = 0x5 -} word_length_t; +} i2s_word_length_t; typedef enum _fifo_threshold { @@ -133,7 +132,7 @@ typedef enum _fifo_threshold TRIGGER_LEVEL_15 = 0xe, /* Interrupt trigger when FIFO level is 16 */ TRIGGER_LEVEL_16 = 0xf -} fifo_threshold_t; +} i2s_fifo_threshold_t; typedef struct _i2s_ier @@ -152,9 +151,9 @@ typedef union _ier_u typedef struct _i2s_irer { - /* Bit 0 is receiver block enable, - * 0 for receiver disable - * 1 for receiver enable + /* Bit 0 is I2S_RECEIVER block enable, + * 0 for I2S_RECEIVER disable + * 1 for I2S_RECEIVER enable */ uint32_t rxen : 1; /* Bits [31:1] is reserved */ @@ -170,9 +169,9 @@ typedef union _irer_u typedef struct _i2s_iter { uint32_t txen : 1; - /* Bit 0 is transmitter block enable, - * 0 for transmitter disable - * 1 for transmitter enable + /* Bit 0 is I2S_TRANSMITTER block enable, + * 0 for I2S_TRANSMITTER disable + * 1 for I2S_TRANSMITTER enable */ uint32_t resv : 31; /* Bits [31:1] is reserved */ @@ -245,7 +244,7 @@ typedef union _ccr_u typedef struct _i2s_rxffr { uint32_t rxffr : 1; - /* Bit 0 is receiver FIFO reset, + /* Bit 0 is I2S_RECEIVER FIFO reset, * 0 for does not flush RX FIFO, 1 for flush RX FIFO */ uint32_t resv : 31; @@ -322,13 +321,13 @@ typedef union _ter_u typedef struct _i2s_rcr_tcr { /* Bits [2:0] is used to program desired data resolution of - * receiver/transmitter, + * I2S_RECEIVER/I2S_TRANSMITTER, * 0x0 for ignore the word length - * 0x1 for 12-bit data resolution of the receiver/transmitter, - * 0x2 for 16-bit data resolution of the receiver/transmitter, - * 0x3 for 20-bit data resolution of the receiver/transmitter, - * 0x4 for 24-bit data resolution of the receiver/transmitter, - * 0x5 for 32-bit data resolution of the receiver/transmitter + * 0x1 for 12-bit data resolution of the I2S_RECEIVER/I2S_TRANSMITTER, + * 0x2 for 16-bit data resolution of the I2S_RECEIVER/I2S_TRANSMITTER, + * 0x3 for 20-bit data resolution of the I2S_RECEIVER/I2S_TRANSMITTER, + * 0x4 for 24-bit data resolution of the I2S_RECEIVER/I2S_TRANSMITTER, + * 0x5 for 32-bit data resolution of the I2S_RECEIVER/I2S_TRANSMITTER */ uint32_t wlen : 3; /* Bits [31:3] is reseved */ @@ -342,7 +341,7 @@ typedef union _rcr_tcr_u { typedef struct _i2s_isr { - /* Bit 0 is status of receiver data avaliable interrupt + /* Bit 0 is status of I2S_RECEIVER data avaliable interrupt * 0x0 for RX FIFO trigger level not reached * 0x1 for RX FIFO trigger level is reached */ @@ -445,7 +444,7 @@ typedef union _tor_u typedef struct _i2s_rfcr { /* Bits [3:0] is used program the trigger level in the RX FIFO at - * which the receiver data available interrupt generate, + * which the I2S_RECEIVER data available interrupt generate, * 0x0 for interrupt trigger when FIFO level is 1, * 0x2 for interrupt trigger when FIFO level is 2, * 0x3 for interrupt trigger when FIFO level is 4, @@ -476,7 +475,7 @@ typedef union _rfcr_u typedef struct _i2s_tfcr { /* Bits [3:0] is used program the trigger level in the TX FIFO at - * which the receiver data available interrupt generate, + * which the I2S_RECEIVER data available interrupt generate, * 0x0 for interrupt trigger when FIFO level is 1, * 0x2 for interrupt trigger when FIFO level is 2, * 0x3 for interrupt trigger when FIFO level is 4, @@ -506,7 +505,7 @@ typedef union _tfcr_u typedef struct _i2s_rff { - /* Bit 0 is receiver channel FIFO reset, + /* Bit 0 is I2S_RECEIVER channel FIFO reset, * 0x0 for does not flush an individual RX FIFO, * 0x1 for flush an indiviadual RX FIFO */ @@ -587,30 +586,30 @@ typedef struct _i2s { /* I2S Enable Register (0x00) */ volatile uint32_t ier; - /* I2S Receiver Block Enable Register (0x04) */ + /* I2S I2S_RECEIVER Block Enable Register (0x04) */ volatile uint32_t irer; - /* I2S Transmitter Block Enable Register (0x08) */ + /* I2S I2S_TRANSMITTER Block Enable Register (0x08) */ volatile uint32_t iter; /* Clock Enable Register (0x0c) */ volatile uint32_t cer; /* Clock Configuration Register (0x10) */ volatile uint32_t ccr; - /* Receiver Block FIFO Reset Register (0x04) */ + /* I2S_RECEIVER Block FIFO Reset Register (0x04) */ volatile uint32_t rxffr; - /* Transmitter Block FIFO Reset Register (0x18) */ + /* I2S_TRANSMITTER Block FIFO Reset Register (0x18) */ volatile uint32_t txffr; /* reserved (0x1c) */ volatile uint32_t reserved1; volatile i2s_channel_t channel[4]; /* reserved (0x118-0x1bc) */ volatile uint32_t reserved2[40]; - /* Receiver Block DMA Register (0x1c0) */ + /* I2S_RECEIVER Block DMA Register (0x1c0) */ volatile uint32_t rxdma; - /* Reset Receiver Block DMA Register (0x1c4) */ + /* Reset I2S_RECEIVER Block DMA Register (0x1c4) */ volatile uint32_t rrxdma; - /* Transmitter Block DMA Register (0x1c8) */ + /* I2S_TRANSMITTER Block DMA Register (0x1c8) */ volatile uint32_t txdma; - /* Reset Transmitter Block DMA Register (0x1cc) */ + /* Reset I2S_TRANSMITTER Block DMA Register (0x1cc) */ volatile uint32_t rtxdma; /* reserved (0x1d0-0x1ec) */ volatile uint32_t reserved3[8]; @@ -629,48 +628,6 @@ typedef struct _i2s */ extern volatile i2s_t *const i2s[3]; -/** - * @brief i2s device - * - * @param[in] device_num the device of i2s - * - */ -void i2s_device_enable(i2s_device_number_t device_num); - -/** - * @brief Enable or disable i2s device - * - * @param[in] device_num The device of i2s - * @param[in] enable Enable flag 0:disable, 1:enable - */ -void i2s_dev_enable(i2s_device_number_t device_num, uint32_t enable); - -/** - * @brief Set I2S recive channel enable or disable - * - * @param[in] device_num which of device - * @param[in] channel_num The channel number - * @param[in] enable The enable or disable - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_receive_channel_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint32_t enable); - -/** - * @brief Set I2S transmit channel enable or disable - * - * @param[in] device_num which of device - * @param[in] channel_num The channel number - * @param[in] enable The enable or disable - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_transmit_channel_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint32_t enable); - /** * @brief I2s init * @@ -681,20 +638,6 @@ int i2s_transmit_channel_enable(i2s_device_number_t device_num, i2s_channel_num_ */ void i2s_init(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode, uint32_t channel_mask); -/** - * @brief Read pcm data from channel_num channel - * - * @param[in] device_num which of device - * @param[in] channel_num The channel number - * @param[in] buf save read data - * @param[in] buf_len the length to read form i2s - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_receive_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint64_t *buf, size_t buf_len); - /** * @brief Read pcm data from dma * @@ -709,20 +652,6 @@ int i2s_receive_data(i2s_device_number_t device_num, i2s_channel_num_t channel_n */ int i2s_receive_data_dma(i2s_device_number_t device_num, uint32_t *buf, size_t buf_len, dmac_channel_number_t channel_num); -/** - * @brief Write pcm data to channel_num channel - * - * @param[in] device_num The i2s number - * @param[in] channel_num The channel number - * @param[in] pcm 32bit (16 bits left and 16bits right)pcm data - * @param[in] device_num which of device - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_send_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint8_t *pcm, size_t buf_len, size_t single_length); - /** * @brief Write pcm data to channel_num channel by dma, first wait dmac done * @@ -732,161 +661,7 @@ int i2s_send_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, * @param[in] channel_num dmac channel * */ -void i2s_send_data_dma(i2s_device_number_t device_num, void *pcm, size_t buf_len, dmac_channel_number_t channel_num); - -/** - * @brief Write pcm data to channel_num channel by dma - * - * @param[in] device_num which of device - * @param[in] channel_num which of device - * @param[in] buf Send data - * @param[in] buf_len Send data length - * @param[in] frame I2s frame number - * @param[in] bits_per_sample I2s sample bits - * @param[in] track_num track num - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_play(i2s_device_number_t device_num,dmac_channel_number_t channel_num, uint8_t *buf, size_t buf_len, size_t frame, size_t bits_per_sample, uint8_t track_num); - -/** - * @brief Send receive data to transmit channel by dma - * - * @param[in] device_src_num I2s receive - * @param[in] device_dest_num I2s transfer - * @param[in] buf_len Data length - * @param[in] channel_num Dmac channel - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_rx_to_tx(i2s_device_number_t device_src_num, i2s_device_number_t device_dest_num, - size_t buf_len, dmac_channel_number_t channel_num); - -/** - * @brief Mask or unmask interrupt - * - * @param[in] channel_num The channel number - * @param[in] rx_available The receive available interrupt - * @param[in] rx_overrun_int The receive overrun interrupt - * @param[in] tx_empty_int The transmit empty interrupt - * @param[in] tx_overrun_int The transmit overrun interrupt - * @param[in] device_num which of device - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_set_mask_interrupt(i2s_device_number_t device_num, - i2s_channel_num_t channel_num, - uint32_t rx_available, uint32_t rx_overrun_int, - uint32_t tx_empty_int, uint32_t tx_overrun_int); -/** - * @brief Set transmit threshold - * - * @param[in] threshold The threshold data - * @param[in] channel_num The channel number - * @param[in] device_num which of device - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_set_tx_threshold(i2s_device_number_t device_num, - fifo_threshold_t threshold, - i2s_channel_num_t channel_num); - -/** - * @brief Set receive threshold - * - * @param[in] threshold The threshold data - * @param[in] channel_num The channel number - * @param[in] device_num which of device - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_set_rx_threshold(i2s_device_number_t device_num, - fifo_threshold_t threshold, - i2s_channel_num_t channel_num); - -/** - * @brief Configure I2s master mode word select size and clock gating param - * - * @param[in] device_num which of device - * @param[in] word_select_size clock cycle - * @param[in] gating_cycles The sclk gating cycles - - * @param[in] word_mode work mode standard,left justify, - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_master_configure(i2s_device_number_t device_num, - word_select_cycles_t word_select_size, - sclk_gating_cycles_t gating_cycles, - i2s_work_mode_t word_mode); -/** - * @brief Set rx fifo word length - * - * @param[in] device_num which of device - * @param[in] word_length word length - * @param[in] channel_num The channel number - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_set_rx_word_length(i2s_device_number_t device_num, - word_length_t word_length, - i2s_channel_num_t channel_num); - -/** - * @brief set tx fifo word length - * - * @param[in] device_num which of device - * @param[in] word_length word length - * @param[in] channel_num The channel number - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_set_tx_word_length(i2s_device_number_t device_num, - word_length_t word_length, - i2s_channel_num_t channel_num); - -/** - * @brief i2s fpioa set and clock configure - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_fpioa_sysctl(void); - -/** - * @brief i2s receive enable - * - * @param[in] device_num The device number - * @param[in] channel_num The channel number - */ -void i2s_receive_enable(i2s_device_number_t device_num, - i2s_channel_num_t channel_num); - -/** - * @brief i2s transimit enable - * - * @param[in] device_num The device number - * @param[in] channel_num The channel number - */ -void i2s_transimit_enable(i2s_device_number_t device_num, - i2s_channel_num_t channel_num); +void i2s_send_data_dma(i2s_device_number_t device_num, void *buf, size_t buf_len, dmac_channel_number_t channel_num); /** * @brief I2S receive channel configure @@ -897,11 +672,11 @@ void i2s_transimit_enable(i2s_device_number_t device_num, * @param[in] word_select_size The word select size * @param[in] trigger_level The trigger level */ -void i2s_rx_channel_configure(i2s_device_number_t device_num, +void i2s_rx_channel_config(i2s_device_number_t device_num, i2s_channel_num_t channel_num, - word_length_t word_length, - word_select_cycles_t word_select_size, - fifo_threshold_t trigger_level, + i2s_word_length_t word_length, + i2s_word_select_cycles_t word_select_size, + i2s_fifo_threshold_t trigger_level, i2s_work_mode_t word_mode); /** @@ -913,58 +688,13 @@ void i2s_rx_channel_configure(i2s_device_number_t device_num, * @param[in] word_select_size The word select size * @param[in] trigger_level The trigger level */ -void i2s_tx_channel_configure(i2s_device_number_t device_num, +void i2s_tx_channel_config(i2s_device_number_t device_num, i2s_channel_num_t channel_num, - word_length_t word_length, - word_select_cycles_t word_select_size, - fifo_threshold_t trigger_level, + i2s_word_length_t word_length, + i2s_word_select_cycles_t word_select_size, + i2s_fifo_threshold_t trigger_level, i2s_work_mode_t word_mode); -/** - * @brief disable block - * - * @param[in] device_num The device number - * @param[in] rxtx_mode The rxtx mode - */ -void i2s_disable_block(i2s_device_number_t device_num, - i2s_transmit_t rxtx_mode); - -/** - * @brief Enable I2S transmit DMA - * - * @param[in] device_num The device number - * @param[in] enable The enable - * - * @return result - * 0 Success - * Other Fail - */ -int i2s_transmit_dma_enable(i2s_device_number_t device_num, uint32_t enable); - -/** - * @brief Enable I2S receive DMA - * - * @param[in] device_num The device number - * @param[in] enable The enable - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_receive_dma_enable(i2s_device_number_t device_num, uint32_t enable); - -/** - * @brief Split I2S transmit DMA from 32bit to two 16bit left and right - * - * @param[in] device_num The device number - * @param[in] enable The enable - * - * @return result - * - 0 Success - * - Other Fail - */ -int i2s_transmit_dma_divide(i2s_device_number_t device_num, uint32_t enable); - #ifdef __cplusplus } #endif diff --git a/lib/drivers/include/pwm.h b/lib/drivers/include/pwm.h index e1318d29..45af61dd 100644 --- a/lib/drivers/include/pwm.h +++ b/lib/drivers/include/pwm.h @@ -21,12 +21,29 @@ extern "C" { #endif +typedef enum _pwm_device_number +{ + PWM_DEVICE_0, + PWM_DEVICE_1, + PWM_DEVICE_2, + PWM_DEVICE_MAX, +} pwm_device_number_t; + +typedef enum _pwm_channel_number +{ + PWM_CHANNEL_0, + PWM_CHANNEL_1, + PWM_CHANNEL_2, + PWM_CHANNEL_3, + PWM_CHANNEL_MAX, +} pwm_channel_number_t; + /** * @brief Init pwm timer * * @param[in] timer timer */ -void pwm_init(uint32_t tim); +void pwm_init(pwm_device_number_t pwm_number); /** * @brief Enable timer @@ -36,7 +53,7 @@ void pwm_init(uint32_t tim); * @param[in] enable Enable or disable * */ -void pwm_set_enable(uint32_t timer, uint32_t channel, int enable); +void pwm_set_enable(pwm_device_number_t pwm_number, pwm_channel_number_t channel, int enable); /** * @brief Set pwm duty @@ -47,7 +64,7 @@ void pwm_set_enable(uint32_t timer, uint32_t channel, int enable); * @param[in] duty duty * */ -double pwm_set_frequency(uint32_t timer, uint32_t channel, double frequency, double duty); +double pwm_set_frequency(pwm_device_number_t pwm_number, pwm_channel_number_t channel, double frequency, double duty); #ifdef __cplusplus diff --git a/lib/drivers/include/rtc.h b/lib/drivers/include/rtc.h index 37bacdcb..91fde348 100644 --- a/lib/drivers/include/rtc.h +++ b/lib/drivers/include/rtc.h @@ -350,95 +350,6 @@ typedef struct _rtc extern volatile rtc_t *const rtc; extern volatile uint32_t *const rtc_base; -/** - * @brief RTC timer set mode - * - * @param timer_mode timer mode - * - * @return Result - * - 0 Success - * - Other Fail - */ -int rtc_timer_set_mode(rtc_timer_mode_t timer_mode); - -/** - * @brief Get RTC timer mode - * - * @return The timer mode - */ -rtc_timer_mode_t rtc_timer_get_mode(void); - -/** - * @brief Set date time to RTC - * - * @param[in] tm The Broken-down date time - * - * @return result - * - 0 Success - * - Other Fail - */ -int rtc_timer_set_tm(const struct tm *tm); - -/** - * @brief Get date time from RTC - * - * @return The Broken-down date time - */ -struct tm *rtc_timer_get_tm(void); - -/** - * @brief Set date time to Alarm - * - * @param[in] tm The Broken-down date time - * - * @return result - * - 0 Success - * - Other Fail - */ -int rtc_timer_set_alarm_tm(const struct tm *tm); - -/** - * @brief Get date time from Alarm - * - * @return The Broken-down date time - */ -struct tm *rtc_timer_get_alarm_tm(void); - -/** - * @brief Check if it is a leap year - * - * @param[in] year The year - * - * @return result - * - 0 Success - * - Other Fail - */ -int rtc_year_is_leap(int year); - -/** - * @brief Get day of year from date - * - * @param[in] year The year - * @param[in] month The month - * @param[in] day The day - * - * @return The day of year from date - */ -int rtc_get_yday(int year, int month, int day); - -/** - * @brief Get the day of the week from date - * - * @param[in] year The year - * @param[in] month The month - * @param[in] day The day - * - * @return The day of the week. - * Where Sunday = 0, Monday = 1, Tuesday = 2, Wednesday = 3, - * Thursday = 4, Friday = 5, Saturday = 6. - */ -int rtc_get_wday(int year, int month, int day); - /** * @brief Set date time to RTC * @@ -471,113 +382,6 @@ int rtc_timer_set(int year, int month, int day, int hour, int minute, int second */ int rtc_timer_get(int *year, int *month, int *day, int *hour, int *minute, int *second); -/** - * @brief Set date time to Alarm - * - * @param[in] year The year - * @param[in] month The month - * @param[in] day The day - * @param[in] hour The hour - * @param[in] minute The minute - * @param[in] second The second - * - * @return result - * - 0 Success - * - Other Fail - */ -int rtc_timer_set_alarm(int year, int month, int day, int hour, int minute, int second); - -/** - * @brief Get date time from Alarm - * - * @param year The year - * @param month The month - * @param day The day - * @param hour The hour - * @param minute The minute - * @param second The second - * - * @return result - * - 0 Success - * - Other Fail - */ -int rtc_timer_get_alarm(int *year, int *month, int *day, int *hour, int *minute, int *second); - -/** - * @brief Set rtc tick interrupt - * - * @param enable enable or disale rtc interrupt - * - * @return Result - * - 0 Success - * - Other Fail - */ -int rtc_tick_interrupt_set(int enable); - -/** - * @brief Get tick interrupt - * - * - * @return Result - * - 0 Disable - * - 1 Enable - */ -int rtc_tick_interrupt_get(void); - -/** - * @brief Set tick interrupt mode - * - * @param mode The mode interrumpted - * - * @return Result - * - 0 Success - * - Other Fail - */ -int rtc_tick_interrupt_mode_set(rtc_tick_interrupt_mode_t mode); - -/** - * @brief Get tick interrupt mode - * - * @return Tick interrupt mode - */ -rtc_tick_interrupt_mode_t rtc_tick_interrupt_mode_get(void); - -/** - * @brief Enable alarm interrupt - * - * @param enable Enable or disable alarm interrupt - * - * @return Result - * - 0 Success - * - Other Fail - */ -int rtc_alarm_interrupt_set(int enable); - -/** - * @brief Get alarm interrupt status - * - * @return Alarm interrupt status - */ -int rtc_alarm_interrupt_get(void); - -/** - * @brief Set alarm interrupt mask - * - * @param mask Alarm interrupt mask - * - * @return Result - * - 0 Success - * - Other Fail - */ -int rtc_alarm_interrupt_mask_set(rtc_mask_t mask); - -/** - * @brief Get alarm interrupt mask - * - * @return Alarm interrupt mask - */ -rtc_mask_t rtc_alarm_interrupt_mask_get(void); - /** * @brief Initialize RTC * diff --git a/lib/drivers/include/spi.h b/lib/drivers/include/spi.h index d0ddb439..0662cecd 100644 --- a/lib/drivers/include/spi.h +++ b/lib/drivers/include/spi.h @@ -111,10 +111,10 @@ typedef enum _spi_device_num typedef enum _spi_work_mode { - SPI_MODE_0, - SPI_MODE_1, - SPI_MODE_2, - SPI_MODE_3, + SPI_WORK_MODE_0, + SPI_WORK_MODE_1, + SPI_WORK_MODE_2, + SPI_WORK_MODE_3, } spi_work_mode_t; typedef enum _spi_frame_format @@ -125,12 +125,12 @@ typedef enum _spi_frame_format SPI_FF_OCTAL } spi_frame_format_t; -typedef enum _spi_addr_inst_trans_mode +typedef enum _spi_instruction_address_trans_mode { SPI_AITM_STANDARD, SPI_AITM_ADDR_STANDARD, SPI_AITM_AS_FRAME_FORMAT -} spi_addr_inst_trans_mode_t; +} spi_instruction_address_trans_mode_t; typedef enum _spi_transfer_mode { @@ -148,6 +148,16 @@ typedef enum _spi_transfer_width SPI_TRANS_INT = 0x2, } spi_transfer_width_t; +typedef enum _spi_chip_select +{ + SPI_CHIP_SELECT_0, + SPI_CHIP_SELECT_1, + SPI_CHIP_SELECT_2, + SPI_CHIP_SELECT_3, + SPI_CHIP_SELECT_MAX, +} spi_chip_select_t; + + extern volatile spi_t *const spi[4]; /** @@ -162,26 +172,26 @@ extern volatile spi_t *const spi[4]; * - 0 Success * - Other Fail */ -int spi_config(spi_device_num_t spi_num, spi_work_mode_t mode, spi_frame_format_t frame_format, size_t data_bit_length); +int spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format, size_t data_bit_length); /** * @brief Set multiline configuration * - * @param[in] spi_num Spi bus number - * @param[in] instruction_length Instruction length - * @param[in] address_length Address length - * @param[in] wait_cycles Wait cycles - * @param[in] trans_mode Spi transfer mode + * @param[in] spi_num Spi bus number + * @param[in] instruction_length Instruction length + * @param[in] address_length Address length + * @param[in] wait_cycles Wait cycles + * @param[in] instruction_address_trans_mode Spi transfer mode * */ -void spi_config_non_standard(spi_device_num_t spi_num, size_t instruction_length, size_t address_length, - size_t wait_cycles, spi_addr_inst_trans_mode_t trans_mode); +int spi_config_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length, + uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode); /** * @brief Spi send data * * @param[in] spi_num Spi bus number - * @param[in] chip_sel Spi chip select + * @param[in] chip_select Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length * @param[in] tx_buff Spi transmit buffer point @@ -191,14 +201,13 @@ void spi_config_non_standard(spi_device_num_t spi_num, size_t instruction_length * - 0 Success * - Other Fail */ -int spi_send_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); - +int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** * @brief Spi receive data * * @param[in] spi_num Spi bus number - * @param[in] chip_sel Spi chip select + * @param[in] chip_select Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length * @param[in] rx_buff Spi receive buffer point @@ -208,14 +217,13 @@ int spi_send_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8_t * - 0 Success * - Other Fail */ -int spi_receive_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); - +int spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special receive data * * @param[in] spi_num Spi bus number - * @param[in] chip_sel Spi chip select + * @param[in] chip_select Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length * @param[in] rx_buff Spi receive buffer point @@ -225,13 +233,13 @@ int spi_receive_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8 * - 0 Success * - Other Fail */ -int spi_receive_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +int spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special send data * * @param[in] spi_num Spi bus number - * @param[in] chip_sel Spi chip select + * @param[in] chip_select Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length * @param[in] tx_buff Spi transmit buffer point @@ -241,14 +249,14 @@ int spi_receive_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint3 * - 0 Success * - Other Fail */ -int spi_send_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); +int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** * @brief Spi send data by dma * * @param[in] channel_num Dmac channel number * @param[in] spi_num Spi bus number - * @param[in] chip_sel Spi chip select + * @param[in] chip_select Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length * @param[in] tx_buff Spi transmit buffer point @@ -258,17 +266,16 @@ int spi_send_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint32_t * - 0 Success * - Other Fail */ -int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, uint32_t chip_sel, +int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); - /** * @brief Spi receive data by dma * * @param[in] w_channel_num Dmac write channel number * @param[in] r_channel_num Dmac read channel number * @param[in] spi_num Spi bus number - * @param[in] chip_sel Spi chip select + * @param[in] chip_select Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length * @param[in] rx_buff Spi receive buffer point @@ -279,15 +286,14 @@ int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num * - Other Fail */ int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); - + spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special send data by dma * * @param[in] channel_num Dmac channel number * @param[in] spi_num Spi bus number - * @param[in] chip_sel Spi chip select + * @param[in] chip_select Spi chip select * @param[in] cmd_buff Spi command buffer point * @param[in] cmd_len Spi command length * @param[in] tx_buff Spi transmit buffer point @@ -297,49 +303,49 @@ int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dm * - 0 Success * - Other Fail */ -int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, uint32_t chip_sel, +int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); /** * @brief Spi special receive data by dma * - * @param[in] w_channel_num Dmac write channel number - * @param[in] r_channel_num Dmac read channel number - * @param[in] spi_num Spi bus number - * @param[in] chip_sel Spi chip select - * @param[in] cmd_buff Spi command buffer point - * @param[in] cmd_len Spi command length - * @param[in] rx_buff Spi receive buffer point - * @param[in] rx_len Spi receive buffer length + * @param[in] dma_send_channel_num Dmac write channel number + * @param[in] dma_receive_channel_num Dmac read channel number + * @param[in] spi_num Spi bus number + * @param[in] chip_select Spi chip select + * @param[in] cmd_buff Spi command buffer point + * @param[in] cmd_len Spi command length + * @param[in] rx_buff Spi receive buffer point + * @param[in] rx_len Spi receive buffer length * * @return Result * - 0 Success * - Other Fail */ int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); + spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi fill dma * * @param[in] channel_num Dmac channel number * @param[in] spi_num Spi bus number - * @param[in] chip_sel Spi chip select - * @param[in] cmd_buff Spi command buffer point - * @param[in] cmd_len Spi command length + * @param[in] chip_select Spi chip select + * @param[in] tx_buff Spi command buffer point + * @param[in] tx_len Spi command length * * @return Result * - 0 Success * - Other Fail */ -int spi_fill_data_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len); +int spi_fill_data_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *tx_buff, size_t tx_len); /** * @brief Spi normal send by dma * * @param[in] channel_num Dmac channel number * @param[in] spi_num Spi bus number - * @param[in] chip_sel Spi chip select + * @param[in] chip_select Spi chip select * @param[in] tx_buff Spi transmit buffer point * @param[in] tx_len Spi transmit buffer length * @param[in] stw Spi transfer width @@ -348,8 +354,8 @@ int spi_fill_data_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num * - 0 Success * - Other Fail */ -int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, uint32_t chip_sel, - void *tx_buff, size_t tx_len, spi_transfer_width_t stw); +int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, + void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width); /** * @brief Spi normal send by dma diff --git a/lib/drivers/include/timer.h b/lib/drivers/include/timer.h index 36d00535..805dc552 100644 --- a/lib/drivers/include/timer.h +++ b/lib/drivers/include/timer.h @@ -92,14 +92,14 @@ extern volatile kendryte_timer_t *const timer[3]; * * @return the real timeout */ -size_t timer_set_interval(timer_device_number_t timer, timer_channel_number_t channel, size_t nanoseconds); +size_t timer_set_interval(timer_device_number_t timer_number, timer_channel_number_t channel, size_t nanoseconds); /** * @brief Init timer * * @param[in] timer timer */ -void timer_init(timer_device_number_t timer); +void timer_init(timer_device_number_t timer_number); /** * @brief Set timer timeout function @@ -110,7 +110,7 @@ void timer_init(timer_device_number_t timer); * @param[in] priority interrupt priority * */ -void timer_set_irq(timer_device_number_t timer, timer_channel_number_t channel, void(*func)(), uint32_t priority); +void timer_set_irq(timer_device_number_t timer_number, timer_channel_number_t channel, void(*func)(), uint32_t priority); /** * @brief Enable timer @@ -120,7 +120,7 @@ void timer_set_irq(timer_device_number_t timer, timer_channel_number_t channel, * @param[in] enable Enable or disable * */ -void timer_set_enable(timer_device_number_t timer, timer_channel_number_t channel, uint32_t enable); +void timer_set_enable(timer_device_number_t timer_number, timer_channel_number_t channel, uint32_t enable); #ifdef __cplusplus } diff --git a/lib/drivers/include/uart.h b/lib/drivers/include/uart.h index 4efc8884..fb8d209f 100644 --- a/lib/drivers/include/uart.h +++ b/lib/drivers/include/uart.h @@ -15,7 +15,7 @@ /** * @file - * @brief Universal Asynchronous Receiver/Transmitter (UART) + * @brief Universal Asynchronous I2S_RECEIVER/I2S_TRANSMITTER (UART) * * The UART peripheral supports the following features: * @@ -110,6 +110,14 @@ typedef struct _uart volatile uint32_t CTR; } uart_t; +typedef enum _uart_device_number +{ + UART_DEVICE_1, + UART_DEVICE_2, + UART_DEVICE_3, + UART_DEVICE_MAX, +} uart_device_number_t; + typedef enum _uart_bitwidth { UART_BITWIDTH_5BIT = 0, @@ -118,13 +126,6 @@ typedef enum _uart_bitwidth UART_BITWIDTH_8BIT, } uart_bitwidth_t; -typedef enum _uart_pority -{ - UART_PORITY_DISABLE = 0, - UART_PORITY_ODD = 1, - UART_PORITY_EVEN = 3 -} uart_pority_t; - typedef enum _uart_stopbit { UART_STOP_1, @@ -132,15 +133,6 @@ typedef enum _uart_stopbit UART_STOP_2 } uart_stopbit_t; -typedef struct _uart_info -{ - uint32_t baudrate; - uart_bitwidth_t bitwidth; - uart_stopbit_t stopbit; - uart_pority_t pority; - uint32_t is_hw_flow_en; -} uart_info_t; - typedef enum _uart_rede_sel { DISABLE = 0, @@ -163,7 +155,7 @@ typedef enum _uart_parity * * @return Transfer length */ -int uart_write(uint8_t channel, const char* buffer, size_t len); +int uart_send_data(uart_device_number_t channel, const char *buffer, size_t buf_len); /** * @brief Read data from uart @@ -174,7 +166,7 @@ int uart_write(uint8_t channel, const char* buffer, size_t len); * * @return Receive length */ -int uart_read(uint8_t channel, char* buffer, size_t len); +int uart_receive_data(uart_device_number_t channel, char *buffer, size_t buf_len); /** * @brief Init uart @@ -182,7 +174,7 @@ int uart_read(uint8_t channel, char* buffer, size_t len); * @param[in] channel Uart index * */ -void uartapb_init(uint8_t channel); +void uart_init(uart_device_number_t channel); /** * @brief Set uart param @@ -194,7 +186,7 @@ void uartapb_init(uint8_t channel); * @param[in] parity Odd Even parity * */ -void uart_config(uint8_t channel, size_t baud_rate, size_t data_width, uart_stopbit_t stopbit, uart_parity_t parity); +void uart_config(uart_device_number_t channel, uint32_t baud_rate, uart_bitwidth_t data_width, uart_stopbit_t stopbit, uart_parity_t parity); #ifdef __cplusplus } diff --git a/lib/drivers/include/uarths.h b/lib/drivers/include/uarths.h index a2dd3807..2da75f64 100644 --- a/lib/drivers/include/uarths.h +++ b/lib/drivers/include/uarths.h @@ -15,7 +15,7 @@ /** * @file - * @brief Universal Asynchronous Receiver/Transmitter (UART) + * @brief Universal Asynchronous I2S_RECEIVER/I2S_TRANSMITTER (UART) * * The UART peripheral supports the following features: * diff --git a/lib/drivers/include/wdt.h b/lib/drivers/include/wdt.h index 3a02f31e..37f4623e 100644 --- a/lib/drivers/include/wdt.h +++ b/lib/drivers/include/wdt.h @@ -124,14 +124,6 @@ typedef enum _wdt_device_number */ void wdt_feed(wdt_device_number_t id); -/** - * @brief Clear wdt interrupt - * - * @param[in] id Wdt id 0 or 1 - * - */ -void wdt_clear_interrupt(wdt_device_number_t id); - /** * @brief Start wdt * @@ -149,15 +141,6 @@ int wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t */ void wdt_stop(wdt_device_number_t id); -/** - * @brief Set wdt interrupt function - * - * @param[in] id Wdt id 0 or 1 - * @param[in] on_irq Wdt interrupt function - * - */ -void wdt_set_irq(wdt_device_number_t id, plic_irq_callback_t on_irq); - #ifdef __cplusplus } #endif diff --git a/lib/drivers/pwm.c b/lib/drivers/pwm.c index 16a4ef45..9d1ed111 100644 --- a/lib/drivers/pwm.c +++ b/lib/drivers/pwm.c @@ -20,30 +20,30 @@ #include "plic.h" #include "io.h" -void pwm_init(uint32_t tim) +void pwm_init(pwm_device_number_t pwm_number) { - sysctl_clock_enable(SYSCTL_CLOCK_TIMER0 + tim); + sysctl_clock_enable(SYSCTL_CLOCK_TIMER0 + pwm_number); } -void pwm_set_enable(uint32_t tim, uint32_t channel, int enable) +void pwm_set_enable(pwm_device_number_t pwm_number, pwm_channel_number_t channel, int enable) { if (enable) - timer[tim]->channel[channel].control = TIMER_CR_INTERRUPT_MASK | TIMER_CR_PWM_ENABLE | TIMER_CR_USER_MODE | TIMER_CR_ENABLE; + timer[pwm_number]->channel[channel].control = TIMER_CR_INTERRUPT_MASK | TIMER_CR_PWM_ENABLE | TIMER_CR_USER_MODE | TIMER_CR_ENABLE; else - timer[tim]->channel[channel].control = TIMER_CR_INTERRUPT_MASK; + timer[pwm_number]->channel[channel].control = TIMER_CR_INTERRUPT_MASK; } -double pwm_set_frequency(uint32_t tim, uint32_t channel, double frequency, double duty) +double pwm_set_frequency(pwm_device_number_t pwm_number, pwm_channel_number_t channel, double frequency, double duty) { - uint32_t clk_freq = sysctl_clock_get_freq(SYSCTL_CLOCK_TIMER0 + tim); + uint32_t clk_freq = sysctl_clock_get_freq(SYSCTL_CLOCK_TIMER0 + pwm_number); int32_t periods = (int32_t)(clk_freq / frequency); configASSERT(periods > 0 && periods <= INT32_MAX); frequency = clk_freq / (double)periods; uint32_t percent = (uint32_t)(duty * periods); - timer[tim]->channel[channel].load_count = periods - percent; - timer[tim]->load_count2[channel] = percent; + timer[pwm_number]->channel[channel].load_count = periods - percent; + timer[pwm_number]->load_count2[channel] = percent; return frequency; } diff --git a/lib/drivers/rtc.c b/lib/drivers/rtc.c index 826a4f7e..ec407485 100644 --- a/lib/drivers/rtc.c +++ b/lib/drivers/rtc.c @@ -46,9 +46,7 @@ int rtc_timer_set_mode(rtc_timer_mode_t timer_mode) register_ctrl.write_enable = 0; break; } - rtc->register_ctrl = register_ctrl; - return 0; } @@ -409,10 +407,13 @@ int rtc_timer_get_alarm(int *year, int *month, int *day, int *hour, int *minute, int rtc_timer_set_clock_frequency(unsigned int frequency) { + rtc_initial_count_t initial_count; initial_count.count = frequency; + rtc_timer_set_mode(RTC_TIMER_SETTING); rtc->initial_count = initial_count; + rtc_timer_set_mode(RTC_TIMER_RUNNING); return 0; } @@ -423,10 +424,13 @@ unsigned int rtc_timer_get_clock_frequency(void) int rtc_timer_set_clock_count_value(unsigned int count) { + rtc_current_count_t current_count; current_count.count = count; + rtc_timer_set_mode(RTC_TIMER_SETTING); rtc->current_count = current_count; + rtc_timer_set_mode(RTC_TIMER_RUNNING); return 0; } @@ -438,9 +442,10 @@ unsigned int rtc_timer_get_clock_count_value(void) int rtc_tick_interrupt_set(int enable) { rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl; - interrupt_ctrl.tick_enable = enable; + rtc_timer_set_mode(RTC_TIMER_SETTING); rtc->interrupt_ctrl = interrupt_ctrl; + rtc_timer_set_mode(RTC_TIMER_RUNNING); return 0; } @@ -456,7 +461,9 @@ int rtc_tick_interrupt_mode_set(rtc_tick_interrupt_mode_t mode) rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl; interrupt_ctrl.tick_int_mode = mode; + rtc_timer_set_mode(RTC_TIMER_SETTING); rtc->interrupt_ctrl = interrupt_ctrl; + rtc_timer_set_mode(RTC_TIMER_RUNNING); return 0; } @@ -555,8 +562,9 @@ int rtc_protect_set(int enable) register_ctrl.initial_count_mask = 1; register_ctrl.interrupt_register_mask = 1; } - + rtc_timer_set_mode(RTC_TIMER_SETTING); rtc->register_ctrl = register_ctrl; + rtc_timer_set_mode(RTC_TIMER_RUNNING); return 0; } @@ -566,7 +574,6 @@ int rtc_init(void) sysctl_reset(SYSCTL_RESET_RTC); /* Enable RTC */ sysctl_clock_enable(SYSCTL_CLOCK_RTC); - rtc_timer_set_mode(RTC_TIMER_SETTING); /* Unprotect RTC */ rtc_protect_set(0); /* Set RTC clock frequency */ diff --git a/lib/drivers/spi.c b/lib/drivers/spi.c index 7c904e68..2d29b3d7 100644 --- a/lib/drivers/spi.c +++ b/lib/drivers/spi.c @@ -58,7 +58,7 @@ static void spi_set_tmod(uint8_t spi_num, uint32_t tmod) set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset); } -int spi_config(spi_device_num_t spi_num, spi_work_mode_t mode, spi_frame_format_t frame_format, size_t data_bit_length) +int spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format, size_t data_bit_length) { configASSERT(data_bit_length >= 4 && data_bit_length <= 32); configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -105,16 +105,16 @@ int spi_config(spi_device_num_t spi_num, spi_work_mode_t mode, spi_frame_format_ spi_adapter->dmardlr = 0x00; spi_adapter->ser = 0x00; spi_adapter->ssienr = 0x00; - spi_adapter->ctrlr0 = (mode << 6) | (frame_format << frf_offset) | ((data_bit_length - 1) << dfs_offset); + spi_adapter->ctrlr0 = (work_mode << 6) | (frame_format << frf_offset) | ((data_bit_length - 1) << dfs_offset); spi_adapter->spi_ctrlr0 = 0; return 0; } -void spi_config_non_standard(spi_device_num_t spi_num, size_t instruction_length, size_t address_length, - size_t wait_cycles, spi_addr_inst_trans_mode_t trans_mode) +int spi_config_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length, + uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode) { configASSERT(wait_cycles < (1 << 5)); - configASSERT(trans_mode < 3); + configASSERT(instruction_address_trans_mode < 3); configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); volatile spi_t *spi_handle = spi[spi_num]; uint32_t inst_l; @@ -140,7 +140,8 @@ void spi_config_non_standard(spi_device_num_t spi_num, size_t instruction_length configASSERT(address_length % 4 == 0 && address_length <= 60); uint32_t addr_l = address_length / 4; - spi_handle->spi_ctrlr0 = (wait_cycles << 11) | (inst_l << 8) | (addr_l << 2) | trans_mode; + spi_handle->spi_ctrlr0 = (wait_cycles << 11) | (inst_l << 8) | (addr_l << 2) | instruction_address_trans_mode; + return 0; } uint32_t spi_set_clk_rate(spi_device_num_t spi_num, uint32_t spi_clk) @@ -159,7 +160,7 @@ uint32_t spi_set_clk_rate(spi_device_num_t spi_num, uint32_t spi_clk) return sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_num) / spi_baudr; } -int spi_send_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) +int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { uint32_t index, fifo_len; configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -176,7 +177,7 @@ int spi_send_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8_t for (index = 0; index < fifo_len; index++) spi_handle->dr[0] = *tx_buff++; tx_len -= fifo_len; - spi_handle->ser = 1 << chip_sel; + spi_handle->ser = 1 << chip_select; while (tx_len) { fifo_len = 32 - spi_handle->txflr; @@ -192,7 +193,7 @@ int spi_send_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8_t return 0; } -int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, uint32_t chip_sel, +int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -215,7 +216,7 @@ int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); dmac_set_single_mode(channel_num, buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len + tx_len); - spi_handle->ser = 1 << chip_sel; + spi_handle->ser = 1 << chip_select; dmac_wait_done(channel_num); free((void*)buf); @@ -226,8 +227,8 @@ int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num return 0; } -int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, uint32_t chip_sel, - void *tx_buff, size_t tx_len, spi_transfer_width_t stw) +int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, + void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); spi_set_tmod(spi_num, SPI_TMOD_TRANS); @@ -236,7 +237,7 @@ int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t int i; for(i = 0; i < tx_len; i++) { - switch(stw) + switch(spi_transfer_width) { case SPI_TRANS_SHORT: buf[i] = ((uint16_t *)tx_buff)[i]; @@ -257,7 +258,7 @@ int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); dmac_set_single_mode(channel_num, buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, tx_len); - spi_handle->ser = 1 << chip_sel; + spi_handle->ser = 1 << chip_select; dmac_wait_done(channel_num); free((void*)buf); @@ -268,7 +269,7 @@ int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t return 0; } -int spi_receive_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +int spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { uint32_t index, fifo_len; configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -278,7 +279,7 @@ int spi_receive_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8 spi_handle->ssienr = 0x01; while (cmd_len--) spi_handle->dr[0] = *cmd_buff++; - spi_handle->ser = 1 << chip_sel; + spi_handle->ser = 1 << chip_select; while (rx_len) { fifo_len = spi_handle->rxflr; @@ -293,7 +294,7 @@ int spi_receive_data_standard(spi_device_num_t spi_num, uint32_t chip_sel, uint8 } int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - spi_device_num_t spi_num, uint32_t chip_sel, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) + spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); spi_set_tmod(spi_num, SPI_TMOD_EEROM); @@ -306,7 +307,7 @@ int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dm spi_handle->ctrlr1 = rx_len - 1; spi_handle->dmacr = 0x3; spi_handle->ssienr = 0x01; - spi_handle->ser = 1 << chip_sel; + spi_handle->ser = 1 << chip_select; sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2); @@ -330,7 +331,7 @@ int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dm return 0; } -int spi_receive_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +int spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { uint32_t index, fifo_len; configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -340,7 +341,7 @@ int spi_receive_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint3 spi_handle->ssienr = 0x01; while (cmd_len--) spi_handle->dr[0] = *cmd_buff++; - spi_handle->ser = 1 << chip_sel; + spi_handle->ser = 1 << chip_select; while (rx_len) { fifo_len = spi_handle->rxflr; @@ -355,7 +356,7 @@ int spi_receive_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint3 } int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) + spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); spi_set_tmod(spi_num, SPI_TMOD_RECV); @@ -368,7 +369,7 @@ int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dm spi_handle->ctrlr1 = rx_len - 1; spi_handle->dmacr = 0x3; spi_handle->ssienr = 0x01; - spi_handle->ser = 1 << chip_sel; + spi_handle->ser = 1 << chip_select; sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2); @@ -392,7 +393,7 @@ int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dm return 0; } -int spi_send_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) +int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { uint32_t index, fifo_len; configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -406,7 +407,7 @@ int spi_send_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint32_t for (index = 0; index < fifo_len; index++) spi_handle->dr[0] = *tx_buff++; tx_len -= fifo_len; - spi_handle->ser = 1 << chip_sel; + spi_handle->ser = 1 << chip_select; while (tx_len) { fifo_len = 32 - spi_handle->txflr; @@ -422,7 +423,7 @@ int spi_send_data_multiple(spi_device_num_t spi_num, uint32_t chip_sel, uint32_t return 0; } -int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, uint32_t chip_sel, +int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -445,7 +446,7 @@ int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_ sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); dmac_set_single_mode(channel_num, buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len + tx_len); - spi_handle->ser = 1 << chip_sel; + spi_handle->ser = 1 << chip_select; dmac_wait_done(channel_num); free((void*)buf); @@ -456,7 +457,7 @@ int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_ return 0; } -int spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, uint32_t chip_sel, uint32_t *cmd_buff, size_t cmd_len) +int spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *tx_buff, size_t tx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); spi_set_tmod(spi_num, SPI_TMOD_TRANS); @@ -465,9 +466,9 @@ int spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_nu spi_handle->ssienr = 0x01; sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); - dmac_set_single_mode(channel_num, cmd_buff, (void *)(&spi_handle->dr[0]), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE, - DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, cmd_len); - spi_handle->ser = 1 << chip_sel; + dmac_set_single_mode(channel_num, tx_buff, (void *)(&spi_handle->dr[0]), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE, + DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, tx_len); + spi_handle->ser = 1 << chip_select; dmac_wait_done(channel_num); while ((spi_handle->sr & 0x05) != 0x04) diff --git a/lib/drivers/timer.c b/lib/drivers/timer.c index 6ca964f1..35664466 100644 --- a/lib/drivers/timer.c +++ b/lib/drivers/timer.c @@ -26,120 +26,120 @@ volatile kendryte_timer_t *const timer[3] = (volatile kendryte_timer_t *)TIMER2_BASE_ADDR }; -void timer_init(timer_device_number_t tim) +void timer_init(timer_device_number_t timer_number) { - sysctl_clock_enable(SYSCTL_CLOCK_TIMER0 + tim); + sysctl_clock_enable(SYSCTL_CLOCK_TIMER0 + timer_number); } -void timer_set_clock_div(timer_device_number_t tim, uint32_t div) +void timer_set_clock_div(timer_device_number_t timer_number, uint32_t div) { - sysctl_clock_set_threshold(tim == 0 ? SYSCTL_THRESHOLD_TIMER0 : - tim == 1 ? SYSCTL_THRESHOLD_TIMER1 : + sysctl_clock_set_threshold(timer_number == 0 ? SYSCTL_THRESHOLD_TIMER0 : + timer_number == 1 ? SYSCTL_THRESHOLD_TIMER1 : SYSCTL_THRESHOLD_TIMER2, div); } -void timer_enable(timer_device_number_t tim, timer_channel_number_t channel) +void timer_enable(timer_device_number_t timer_number, timer_channel_number_t channel) { - timer[tim]->channel[channel].control |= TIMER_CR_ENABLE; + timer[timer_number]->channel[channel].control |= TIMER_CR_ENABLE; } -void timer_disable(timer_device_number_t tim, timer_channel_number_t channel) +void timer_disable(timer_device_number_t timer_number, timer_channel_number_t channel) { - timer[tim]->channel[channel].control &= (~TIMER_CR_ENABLE); + timer[timer_number]->channel[channel].control &= (~TIMER_CR_ENABLE); } -void timer_enable_pwm(timer_device_number_t tim, timer_channel_number_t channel) +void timer_enable_pwm(timer_device_number_t timer_number, timer_channel_number_t channel) { - timer[tim]->channel[channel].control |= TIMER_CR_PWM_ENABLE; + timer[timer_number]->channel[channel].control |= TIMER_CR_PWM_ENABLE; } -void timer_disable_pwm(timer_device_number_t tim, timer_channel_number_t channel) +void timer_disable_pwm(timer_device_number_t timer_number, timer_channel_number_t channel) { - timer[tim]->channel[channel].control &= (~TIMER_CR_PWM_ENABLE); + timer[timer_number]->channel[channel].control &= (~TIMER_CR_PWM_ENABLE); } -void timer_enable_interrupt(timer_device_number_t tim, timer_channel_number_t channel) +void timer_enable_interrupt(timer_device_number_t timer_number, timer_channel_number_t channel) { - timer[tim]->channel[channel].control &= (~TIMER_CR_INTERRUPT_MASK); + timer[timer_number]->channel[channel].control &= (~TIMER_CR_INTERRUPT_MASK); } -void timer_disable_interrupt(timer_device_number_t tim, timer_channel_number_t channel) +void timer_disable_interrupt(timer_device_number_t timer_number, timer_channel_number_t channel) { - timer[tim]->channel[channel].control |= TIMER_CR_INTERRUPT_MASK; + timer[timer_number]->channel[channel].control |= TIMER_CR_INTERRUPT_MASK; } -void timer_set_mode(timer_device_number_t tim, timer_channel_number_t channel, uint32_t mode) +void timer_set_mode(timer_device_number_t timer_number, timer_channel_number_t channel, uint32_t mode) { - timer[tim]->channel[channel].control &= (~TIMER_CR_MODE_MASK); - timer[tim]->channel[channel].control |= mode; + timer[timer_number]->channel[channel].control &= (~TIMER_CR_MODE_MASK); + timer[timer_number]->channel[channel].control |= mode; } -void timer_set_reload(timer_device_number_t tim, timer_channel_number_t channel, uint32_t count) +void timer_set_reload(timer_device_number_t timer_number, timer_channel_number_t channel, uint32_t count) { - timer[tim]->channel[channel].load_count = count; + timer[timer_number]->channel[channel].load_count = count; } -void timer_set_reload2(timer_device_number_t tim, timer_channel_number_t channel, uint32_t count) +void timer_set_reload2(timer_device_number_t timer_number, timer_channel_number_t channel, uint32_t count) { - timer[tim]->load_count2[channel] = count; + timer[timer_number]->load_count2[channel] = count; } -uint32_t timer_get_count(timer_device_number_t tim, timer_channel_number_t channel) +uint32_t timer_get_count(timer_device_number_t timer_number, timer_channel_number_t channel) { - return timer[tim]->channel[channel].current_value; + return timer[timer_number]->channel[channel].current_value; } -uint32_t timer_get_reload(timer_device_number_t tim, timer_channel_number_t channel) +uint32_t timer_get_reload(timer_device_number_t timer_number, timer_channel_number_t channel) { - return timer[tim]->channel[channel].load_count; + return timer[timer_number]->channel[channel].load_count; } -uint32_t timer_get_reload2(timer_device_number_t tim, timer_channel_number_t channel) +uint32_t timer_get_reload2(timer_device_number_t timer_number, timer_channel_number_t channel) { - return timer[tim]->load_count2[channel]; + return timer[timer_number]->load_count2[channel]; } -uint32_t timer_get_interrupt_status(timer_device_number_t tim) +uint32_t timer_get_interrupt_status(timer_device_number_t timer_number) { - return timer[tim]->intr_stat; + return timer[timer_number]->intr_stat; } -uint32_t timer_get_raw_interrupt_status(timer_device_number_t tim) +uint32_t timer_get_raw_interrupt_status(timer_device_number_t timer_number) { - return timer[tim]->raw_intr_stat; + return timer[timer_number]->raw_intr_stat; } -uint32_t timer_channel_get_interrupt_status(timer_device_number_t tim, timer_channel_number_t channel) +uint32_t timer_channel_get_interrupt_status(timer_device_number_t timer_number, timer_channel_number_t channel) { - return timer[tim]->channel[channel].intr_stat; + return timer[timer_number]->channel[channel].intr_stat; } -void timer_clear_interrupt(timer_device_number_t tim) +void timer_clear_interrupt(timer_device_number_t timer_number) { - timer[tim]->eoi = timer[tim]->eoi; + timer[timer_number]->eoi = timer[timer_number]->eoi; } -void timer_channel_clear_interrupt(timer_device_number_t tim, timer_channel_number_t channel) +void timer_channel_clear_interrupt(timer_device_number_t timer_number, timer_channel_number_t channel) { - timer[tim]->channel[channel].eoi = timer[tim]->channel[channel].eoi; + timer[timer_number]->channel[channel].eoi = timer[timer_number]->channel[channel].eoi; } -void timer_set_enable(timer_device_number_t tim, timer_channel_number_t channel, uint32_t enable) +void timer_set_enable(timer_device_number_t timer_number, timer_channel_number_t channel, uint32_t enable) { if (enable) - timer[tim]->channel[channel].control = TIMER_CR_USER_MODE | TIMER_CR_ENABLE; + timer[timer_number]->channel[channel].control = TIMER_CR_USER_MODE | TIMER_CR_ENABLE; else - timer[tim]->channel[channel].control = TIMER_CR_INTERRUPT_MASK; + timer[timer_number]->channel[channel].control = TIMER_CR_INTERRUPT_MASK; } -size_t timer_set_interval(timer_device_number_t tim, timer_channel_number_t channel, size_t nanoseconds) +size_t timer_set_interval(timer_device_number_t timer_number, timer_channel_number_t channel, size_t nanoseconds) { - uint32_t clk_freq = sysctl_clock_get_freq(SYSCTL_CLOCK_TIMER0 + tim); + uint32_t clk_freq = sysctl_clock_get_freq(SYSCTL_CLOCK_TIMER0 + timer_number); double min_step = 1e9 / clk_freq; size_t value = (size_t)(nanoseconds / min_step); configASSERT(value > 0 && value < UINT32_MAX); - timer[tim]->channel[channel].load_count = (uint32_t)value; + timer[timer_number]->channel[channel].load_count = (uint32_t)value; return (size_t)(min_step * value); } @@ -148,45 +148,45 @@ timer_ontick time_irq[3][4] = { NULL }; static int timer_isr(void *parm) { - uint32_t tim; - for (tim = 0; tim < 3; tim++) + uint32_t timer_number; + for (timer_number = 0; timer_number < 3; timer_number++) { - if (parm == timer[tim]) + if (parm == timer[timer_number]) break; } - uint32_t channel = timer[tim]->intr_stat; + uint32_t channel = timer[timer_number]->intr_stat; size_t i = 0; for (i = 0; i < 4; i++) { if (channel & 1) { - if (time_irq[tim][i]) - (time_irq[tim][i])(); + if (time_irq[timer_number][i]) + (time_irq[timer_number][i])(); break; } channel >>= 1; } - readl(&timer[tim]->eoi); + readl(&timer[timer_number]->eoi); return 0; } -void timer_set_irq(timer_device_number_t tim, timer_channel_number_t channel, void(*func)(), uint32_t priority) +void timer_set_irq(timer_device_number_t timer_number, timer_channel_number_t channel, void(*func)(), uint32_t priority) { - time_irq[tim][channel] = func; + time_irq[timer_number][channel] = func; if (channel < 2) { - plic_set_priority(IRQN_TIMER0A_INTERRUPT + tim * 2, priority); - plic_irq_register(IRQN_TIMER0A_INTERRUPT + tim * 2, timer_isr, (void *)timer[tim]); - plic_irq_enable(IRQN_TIMER0A_INTERRUPT + tim * 2); + plic_set_priority(IRQN_TIMER0A_INTERRUPT + timer_number * 2, priority); + plic_irq_register(IRQN_TIMER0A_INTERRUPT + timer_number * 2, timer_isr, (void *)timer[timer_number]); + plic_irq_enable(IRQN_TIMER0A_INTERRUPT + timer_number * 2); } else { - plic_set_priority(IRQN_TIMER0B_INTERRUPT + tim * 2, priority); - plic_irq_register(IRQN_TIMER0B_INTERRUPT + tim * 2, timer_isr, NULL); - plic_irq_enable(IRQN_TIMER0B_INTERRUPT + tim * 2); + plic_set_priority(IRQN_TIMER0B_INTERRUPT + timer_number * 2, priority); + plic_irq_register(IRQN_TIMER0B_INTERRUPT + timer_number * 2, timer_isr, NULL); + plic_irq_enable(IRQN_TIMER0B_INTERRUPT + timer_number * 2); } } diff --git a/lib/drivers/uart.c b/lib/drivers/uart.c index 8942cebe..bf0fb96d 100644 --- a/lib/drivers/uart.c +++ b/lib/drivers/uart.c @@ -22,13 +22,6 @@ #define __UART_BRATE_CONST 16 -typedef struct _uart_devinfo_t -{ - uart_t *uart; - const uart_info_t *uart_info; - uint32_t uart_status; -} uart_devinfo_t; - volatile uart_t* const uart[3] = { (volatile uart_t*)UART1_BASE_ADDR, @@ -62,7 +55,7 @@ static int write_ringbuff(uint8_t channel, uint8_t rdata) return 0; } -static int read_ringbuff(uint8_t channel, char *rdata, size_t len) +static int read_ringbuff(uart_device_number_t channel, char *rdata, size_t len) { ring_buff_t *rb = ring_recv[channel]; size_t cnt = 0; @@ -92,7 +85,7 @@ static int on_irq_apbuart_recv(void *param) return 0; } -static int uartapb_putc(uint8_t channel, char c) +static int uartapb_putc(uart_device_number_t channel, char c) { while (!(uart[channel]->LSR & (1u << 6))) continue; @@ -100,7 +93,7 @@ static int uartapb_putc(uint8_t channel, char c) return 0; } -int uartapb_getc(uint8_t channel) +int uartapb_getc(uart_device_number_t channel) { while (!(uart[channel]->LSR & 1)) continue; @@ -109,15 +102,15 @@ int uartapb_getc(uint8_t channel) } -int uart_read(uint8_t channel, char* buffer, size_t len) +int uart_receive_data(uart_device_number_t channel, char *buffer, size_t buf_len) { - return read_ringbuff(channel, buffer, len); + return read_ringbuff(channel, buffer, buf_len); } -int uart_write(uint8_t channel, const char* buffer, size_t len) +int uart_send_data(uart_device_number_t channel, const char *buffer, size_t buf_len) { int write = 0; - while (write < len) + while (write < buf_len) { uartapb_putc(channel, *buffer++); write++; @@ -126,7 +119,7 @@ int uart_write(uint8_t channel, const char* buffer, size_t len) return write; } -void uart_config(uint8_t channel, size_t baud_rate, size_t data_width, uart_stopbit_t stopbit, uart_parity_t parity) +void uart_config(uart_device_number_t channel, uint32_t baud_rate, uart_bitwidth_t data_width, uart_stopbit_t stopbit, uart_parity_t parity) { configASSERT(data_width >= 5 && data_width <= 8); @@ -179,7 +172,7 @@ void uart_config(uint8_t channel, size_t baud_rate, size_t data_width, uart_stop uart[channel]->IER = 1; /*RX INT enable*/ } -void uartapb_init(uint8_t channel) +void uart_init(uart_device_number_t channel) { sysctl_clock_enable(SYSCTL_CLOCK_UART1 + channel); diff --git a/lib/firmware/nt35310.c b/lib/firmware/nt35310.c index 791cad9d..09031fda 100644 --- a/lib/firmware/nt35310.c +++ b/lib/firmware/nt35310.c @@ -33,13 +33,12 @@ void init_dcx(void) { - gpiohs_init(); fpioa_set_function(DCX_IO, FUNC_GPIOHS0 + DCX_GPIONUM);/*dcx*/ - gpiohs_set_drive_mode(DCX_GPIONUM, GPIO_DM_Output); + gpiohs_set_drive_mode(DCX_GPIONUM, GPIO_DM_OUTPUT); gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_High); fpioa_set_function(RESET_IO, FUNC_GPIOHS0 + RESET_GPIONUM);/*reset*/ - gpiohs_set_drive_mode(RESET_GPIONUM, GPIO_DM_Output); + gpiohs_set_drive_mode(RESET_GPIONUM, GPIO_DM_OUTPUT); gpiohs_set_pin(RESET_GPIONUM, GPIO_PV_High); } @@ -64,13 +63,13 @@ void tft_hard_init(void) { init_dcx(); pin_mux_init(); - spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 8); + spi_config(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8); } void tft_write_command(uint8_t cmd) { set_dcx_control(); - spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 8); + spi_config(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8); spi_config_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT, (uint8_t *)(&cmd), 1,SPI_TRANS_CHAR); } @@ -78,7 +77,7 @@ void tft_write_command(uint8_t cmd) void tft_write_byte(uint8_t *data_buf, uint32_t length) { set_dcx_data(); - spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 8); + spi_config(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8); spi_config_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT, data_buf, length, SPI_TRANS_CHAR); } @@ -86,7 +85,7 @@ void tft_write_byte(uint8_t *data_buf, uint32_t length) void tft_write_half(uint16_t *data_buf, uint32_t length) { set_dcx_data(); - spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 16); + spi_config(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 16); spi_config_non_standard(SPI_CHANNEL, 16/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_SHORT); } @@ -94,7 +93,7 @@ void tft_write_half(uint16_t *data_buf, uint32_t length) void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag) { set_dcx_data(); - spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 32); + spi_config(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 32); spi_config_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_INT); @@ -103,7 +102,7 @@ void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag) void tft_fill_data(uint32_t *data_buf, uint32_t length) { set_dcx_data(); - spi_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 32); + spi_config(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 32); spi_config_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); spi_fill_data_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length); } diff --git a/lib/firmware/ov2640.c b/lib/firmware/ov2640.c index 2d356118..418be00b 100644 --- a/lib/firmware/ov2640.c +++ b/lib/firmware/ov2640.c @@ -229,15 +229,15 @@ int ov2640_init(void) { uint16_t index = 0; for (index = 0; ov2640_config[index][0]; index++) - dvp_sccb_write_data(OV2640_ADDR, ov2640_config[index][0], ov2640_config[index][1]); + dvp_sccb_send_data(OV2640_ADDR, ov2640_config[index][0], ov2640_config[index][1]); return 0; } int ov2640_read_id(uint16_t *manuf_id, uint16_t *device_id) { - dvp_sccb_write_data(OV2640_ADDR, 0xFF, 0x01); - *manuf_id = (dvp_sccb_read_data(OV2640_ADDR, 0x1C) << 8) | dvp_sccb_read_data(OV2640_ADDR, 0x1D); - *device_id = (dvp_sccb_read_data(OV2640_ADDR, 0x0A) << 8) | dvp_sccb_read_data(OV2640_ADDR, 0x0B); + dvp_sccb_send_data(OV2640_ADDR, 0xFF, 0x01); + *manuf_id = (dvp_sccb_receive_data(OV2640_ADDR, 0x1C) << 8) | dvp_sccb_receive_data(OV2640_ADDR, 0x1D); + *device_id = (dvp_sccb_receive_data(OV2640_ADDR, 0x0A) << 8) | dvp_sccb_receive_data(OV2640_ADDR, 0x0B); return 0; } diff --git a/lib/firmware/ov5640.c b/lib/firmware/ov5640.c index 1d0b0e3f..6b8250b2 100644 --- a/lib/firmware/ov5640.c +++ b/lib/firmware/ov5640.c @@ -28,13 +28,13 @@ void hal_delay(uint32_t delay) uint8_t ov5640_wr_reg(uint16_t reg,uint8_t data) { - dvp_sccb_write_data(OV5640_ADDR, reg, data); + dvp_sccb_send_data(OV5640_ADDR, reg, data); return 0; } uint8_t ov5640_rd_reg(uint16_t reg) { - return dvp_sccb_read_data(OV5640_ADDR, reg); + return dvp_sccb_receive_data(OV5640_ADDR, reg); } uint8_t ov5640_init(void) diff --git a/lib/firmware/w25qxx.c b/lib/firmware/w25qxx.c index a38eeb83..856f0ce5 100644 --- a/lib/firmware/w25qxx.c +++ b/lib/firmware/w25qxx.c @@ -33,14 +33,14 @@ static w25qxx_status_t w25qxx_quad_page_program_dma(uint32_t addr, uint8_t *data static w25qxx_status_t w25qxx_receive_data(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) { - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); spi_receive_data_standard(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); return W25QXX_OK; } static w25qxx_status_t w25qxx_receive_data_dma(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) { - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); spi_receive_data_standard_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); return W25QXX_OK; } @@ -85,7 +85,7 @@ w25qxx_status_t w25qxx_init(uint8_t spi_index, uint8_t spi_ss) { spi_bus_no = spi_index; spi_chip_select = spi_ss; - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); w25qxx_page_program_fun = w25qxx_page_program; w25qxx_read_fun = w25qxx_stand_read_data; return W25QXX_OK; @@ -95,7 +95,7 @@ w25qxx_status_t w25qxx_init_dma(uint8_t spi_index, uint8_t spi_ss) { spi_bus_no = spi_index; spi_chip_select = spi_ss; - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); w25qxx_page_program_fun = w25qxx_page_program_dma; w25qxx_read_fun = w25qxx_stand_read_data; return W25QXX_OK; @@ -354,7 +354,7 @@ static w25qxx_status_t w25qxx_quad_page_program(uint32_t addr, uint8_t *data_buf cmd[0] = QUAD_PAGE_PROGRAM; cmd[1] = addr; w25qxx_write_enable(); - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_send_data_enhanced(cmd, 2, data_buf, length); while (w25qxx_is_busy() == W25QXX_BUSY) @@ -369,7 +369,7 @@ static w25qxx_status_t w25qxx_quad_page_program_dma(uint32_t addr, uint8_t *data cmd[0] = QUAD_PAGE_PROGRAM; cmd[1] = addr; w25qxx_write_enable_dma(); - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_send_data_enhanced_dma(cmd, 2, data_buf, length); while (w25qxx_is_busy_dma() == W25QXX_BUSY) @@ -494,35 +494,35 @@ static w25qxx_status_t _w25qxx_read_data(uint32_t addr, uint8_t *data_buf, uint3 *(((uint8_t *)cmd) + 2) = (uint8_t)(addr >> 8); *(((uint8_t *)cmd) + 3) = (uint8_t)(addr >> 0); *(((uint8_t *)cmd) + 4) = 0xFF; - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); w25qxx_receive_data((uint8_t *)cmd, 5, data_buf, length); break; case W25QXX_DUAL: cmd[0] = FAST_READ_DUAL_OUTPUT; cmd[1] = addr; - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_DUAL, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); break; case W25QXX_DUAL_FAST: cmd[0] = FAST_READ_DUAL_IO; cmd[1] = addr << 8; - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_DUAL, DATALENGTH); - spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); + spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); break; case W25QXX_QUAD: cmd[0] = FAST_READ_QUAL_OUTPUT; cmd[1] = addr; - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); break; case W25QXX_QUAD_FAST: cmd[0] = FAST_READ_QUAL_IO; cmd[1] = addr << 8; - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); break; } @@ -552,28 +552,28 @@ static w25qxx_status_t w25qxx_read_data_dma_less_1000bytes(uint32_t addr, uint8_ case W25QXX_DUAL: cmd[0] = FAST_READ_DUAL_OUTPUT; cmd[1] = addr; - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_DUAL, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); break; case W25QXX_DUAL_FAST: cmd[0] = FAST_READ_DUAL_IO; cmd[1] = addr << 8; - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_DUAL, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); break; case W25QXX_QUAD: cmd[0] = FAST_READ_QUAL_OUTPUT; cmd[1] = addr; - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); break; case W25QXX_QUAD_FAST: cmd[0] = FAST_READ_QUAL_IO; cmd[1] = addr << 8; - spi_config(spi_bus_no, SPI_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); break; From 7d1af72f3fa87b557b2687ac94eff064d5d94986 Mon Sep 17 00:00:00 2001 From: jiangxiangbing Date: Sun, 30 Sep 2018 10:34:47 +0800 Subject: [PATCH 16/58] update fft --- lib/bsp/interrupt.c | 2 +- lib/drivers/aes.c | 500 +++++++++++----------- lib/drivers/dmac.c | 4 +- lib/drivers/fft.c | 69 +++ lib/drivers/hard_fft.c | 150 ------- lib/drivers/include/aes.h | 204 ++------- lib/drivers/include/dmac.h | 2 +- lib/drivers/include/{hard_fft.h => fft.h} | 89 +--- lib/drivers/include/sha256.h | 75 +--- lib/drivers/sha256.c | 141 +++--- src/hello_world/main.c | 72 ++-- 11 files changed, 492 insertions(+), 816 deletions(-) create mode 100644 lib/drivers/fft.c delete mode 100644 lib/drivers/hard_fft.c rename lib/drivers/include/{hard_fft.h => fft.h} (73%) diff --git a/lib/bsp/interrupt.c b/lib/bsp/interrupt.c index 802a6e5b..4695f990 100644 --- a/lib/bsp/interrupt.c +++ b/lib/bsp/interrupt.c @@ -57,7 +57,7 @@ handle_irq(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[3 [IRQ_M_TIMER] = handle_irq_m_timer, [IRQ_M_EXT] = handle_irq_m_ext, }; - /* clang-format on */ + /* clang-format on */ #if defined(__GNUC__) #pragma GCC diagnostic warning "-Woverride-init" #endif diff --git a/lib/drivers/aes.c b/lib/drivers/aes.c index ad317846..f77ed3ae 100644 --- a/lib/drivers/aes.c +++ b/lib/drivers/aes.c @@ -12,354 +12,354 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#include -#include -#include "encoding.h" -#include "aes.h" -#include "sysctl.h" +#include +#include volatile aes_t* const aes = (volatile aes_t*)AES_BASE_ADDR; -void aes_clkinit() +void aes_clk_init() { sysctl_clock_enable(SYSCTL_CLOCK_AES); sysctl_reset(SYSCTL_RESET_AES); } -int aes_init(uint8_t* key_addr, uint8_t key_length, uint8_t* aes_iv, - uint8_t iv_length, uint8_t* aes_aad, aes_cipher_mod_t cipher_mod, - aes_encrypt_sel_t encrypt_sel, uint32_t add_size, uint32_t data_size) -{ - int i, remainder, num, cnt; - uint32_t u32data; - uint8_t u8data[4] = {0}; - - if ((cipher_mod == AES_ECB) || (cipher_mod == AES_CBC)) - data_size = ((data_size + 15) / 16) * 16; - aes->aes_endian |= 1; - - /* write key Low byte alignment*/ - num = key_length / 4; - for (i = 0; i < num; i++) - aes->aes_key[i] = *((uint32_t*)(&key_addr[key_length - (4 * i) - 4])); - remainder = key_length % 4; - if (remainder) - { - switch (remainder) - { - case 1: - u8data[0] = key_addr[0]; - break; - case 2: - u8data[0] = key_addr[0]; - u8data[1] = key_addr[1]; - break; - case 3: - u8data[0] = key_addr[0]; - u8data[1] = key_addr[1]; - u8data[2] = key_addr[2]; - break; - default: - break; - } - aes->aes_key[num] = *((uint32_t*)(&u8data[0])); - } - - /*write iv Low byte alignment*/ - num = iv_length / 4; - for (i = 0; i < num; i++) - aes->aes_iv[i] = *((uint32_t*)(&aes_iv[iv_length - (4 * i) - 4])); - remainder = iv_length % 4; - if (remainder) - { - switch (remainder) - { - case 1: - u8data[0] = aes_iv[0]; - break; - case 2: - u8data[0] = aes_iv[0]; - u8data[1] = aes_iv[1]; - break; - case 3: - u8data[0] = aes_iv[0]; - u8data[1] = aes_iv[1]; - u8data[2] = aes_iv[2]; - break; - default: - break; - } - aes->aes_iv[num] = *((uint32_t*)(&u8data[0])); - } - - aes->mode_ctl.cipher_mode = cipher_mod; - - /* - * [1:0],set the first bit and second bit 00:ecb; 01:cbc; - * 10,11：aes_gcm - */ - aes->encrypt_sel = encrypt_sel; - aes->gb_aad_end_adr = add_size - 1; - aes->gb_pc_end_adr = data_size - 1; - aes->gb_aes_en |= 1; - - /* write aad */ - if (cipher_mod == AES_GCM) - { - num = add_size / 4; - for (i = 0; i < num; i++) - { - u32data = *((uint32_t*)(&aes_aad[i * 4])); - while (!aes_get_data_in_flag()) - ; - aes_write_aad(u32data); - } - cnt = 4 * num; - remainder = add_size % 4; - if (remainder) - { - switch (remainder) - { - case 1: - u8data[0] = aes_aad[cnt]; - break; - case 2: - u8data[0] = aes_aad[cnt]; - u8data[1] = aes_aad[cnt + 1]; - break; - case 3: - u8data[0] = aes_aad[cnt]; - u8data[1] = aes_aad[cnt + 1]; - u8data[2] = aes_aad[cnt + 2]; - break; - default: - return 0; - } - u32data = *((uint32_t*)(&u8data[0])); - while (!aes_get_data_in_flag()) - ; - aes_write_aad(u32data); - } - } - - return 1; -} - -int aes_write_aad(uint32_t aad_data) +static void aes_write_add(uint32_t aad_data) { aes->aes_aad_data = aad_data; - return 0; } -int aes_write_text(uint32_t text_data) +static void aes_write_text(uint32_t text_data) { aes->aes_text_data = text_data; - return 0; } -int aes_write_tag(uint32_t* tag) +static void gcm_write_tag(uint32_t* tag) { aes->gcm_in_tag[0] = tag[3]; aes->gcm_in_tag[1] = tag[2]; aes->gcm_in_tag[2] = tag[1]; aes->gcm_in_tag[3] = tag[0]; - return 0; } -int aes_get_data_in_flag(void) +static uint32_t aes_get_data_in_flag(void) { - /* data can in flag 1: data ready 0: data not ready */ return aes->data_in_flag; } -int aes_get_data_out_flag(void) +static uint32_t aes_get_data_out_flag(void) { - /* data can output flag 1: data ready 0: data not ready */ return aes->data_out_flag; } -int aes_get_tag_in_flag(void) +static uint32_t gcm_get_tag_in_flag(void) { - /* data can output flag 1: data ready 0: data not ready */ return aes->tag_in_flag; } -uint32_t aes_read_out_data(void) +static uint32_t aes_read_out_data(void) { return aes->aes_out_data; } -int aes_check_tag(void) +static uint32_t gcm_get_tag_chk(void) { return aes->tag_chk; } -int aes_get_tag(uint8_t* l_tag) +static void gcm_get_tag(uint8_t *gcm_tag) { - uint32_t u32tag; + uint32_t uint32_tag; uint8_t i = 0; - u32tag = aes->gcm_out_tag[3]; - l_tag[i++] = (uint8_t)((u32tag >> 24) & 0xff); - l_tag[i++] = (uint8_t)((u32tag >> 16) & 0xff); - l_tag[i++] = (uint8_t)((u32tag >> 8) & 0xff); - l_tag[i++] = (uint8_t)((u32tag)&0xff); + uint32_tag = aes->gcm_out_tag[3]; + gcm_tag[i++] = (uint8_t)((uint32_tag >> 24) & 0xff); + gcm_tag[i++] = (uint8_t)((uint32_tag >> 16) & 0xff); + gcm_tag[i++] = (uint8_t)((uint32_tag >> 8) & 0xff); + gcm_tag[i++] = (uint8_t)((uint32_tag)&0xff); - u32tag = aes->gcm_out_tag[2]; - l_tag[i++] = (uint8_t)((u32tag >> 24) & 0xff); - l_tag[i++] = (uint8_t)((u32tag >> 16) & 0xff); - l_tag[i++] = (uint8_t)((u32tag >> 8) & 0xff); - l_tag[i++] = (uint8_t)((u32tag)&0xff); + uint32_tag = aes->gcm_out_tag[2]; + gcm_tag[i++] = (uint8_t)((uint32_tag >> 24) & 0xff); + gcm_tag[i++] = (uint8_t)((uint32_tag >> 16) & 0xff); + gcm_tag[i++] = (uint8_t)((uint32_tag >> 8) & 0xff); + gcm_tag[i++] = (uint8_t)((uint32_tag)&0xff); - u32tag = aes->gcm_out_tag[1]; - l_tag[i++] = (uint8_t)((u32tag >> 24) & 0xff); - l_tag[i++] = (uint8_t)((u32tag >> 16) & 0xff); - l_tag[i++] = (uint8_t)((u32tag >> 8) & 0xff); - l_tag[i++] = (uint8_t)((u32tag)&0xff); + uint32_tag = aes->gcm_out_tag[1]; + gcm_tag[i++] = (uint8_t)((uint32_tag >> 24) & 0xff); + gcm_tag[i++] = (uint8_t)((uint32_tag >> 16) & 0xff); + gcm_tag[i++] = (uint8_t)((uint32_tag >> 8) & 0xff); + gcm_tag[i++] = (uint8_t)((uint32_tag)&0xff); - u32tag = aes->gcm_out_tag[0]; - l_tag[i++] = (uint8_t)((u32tag >> 24) & 0xff); - l_tag[i++] = (uint8_t)((u32tag >> 16) & 0xff); - l_tag[i++] = (uint8_t)((u32tag >> 8) & 0xff); - l_tag[i++] = (uint8_t)((u32tag)&0xff); - return 1; + uint32_tag = aes->gcm_out_tag[0]; + gcm_tag[i++] = (uint8_t)((uint32_tag >> 24) & 0xff); + gcm_tag[i++] = (uint8_t)((uint32_tag >> 16) & 0xff); + gcm_tag[i++] = (uint8_t)((uint32_tag >> 8) & 0xff); + gcm_tag[i++] = (uint8_t)((uint32_tag)&0xff); } -int aes_clear_chk_tag(void) +static void gcm_clear_chk_tag(void) { aes->tag_clear = 0; - return 0; } -int aes_process_less_80_bytes(uint8_t* aes_in_data, - uint8_t* aes_out_data, - uint32_t data_size, - aes_cipher_mod_t cipher_mod) +static uint32_t gcm_check_tag(uint32_t *gcm_tag) { - int padding_size; - int num, i, remainder, cnt; - uint32_t u32data; - uint8_t u8data[4] = {0}; - /* Fill 128 bits (16byte) */ - padding_size = ((data_size + 15) / 16) * 16; + while (!gcm_get_tag_in_flag()) + ; + gcm_write_tag(gcm_tag); + while (!gcm_get_tag_chk()) + ; + if (gcm_get_tag_chk() == 0x2) + { + gcm_clear_chk_tag(); + return 1; + } + else + { + gcm_clear_chk_tag(); + return 0; + } +} - /* write text */ - num = data_size / 4; - for (i = 0; i < num; i++) +static void aes_init(uint8_t *input_key, size_t input_key_len, uint8_t *iv, + size_t iv_len, uint8_t *gcm_add, aes_cipher_mode_t cipher_mode, + aes_encrypt_sel_t encrypt_sel, size_t gcm_add_len, size_t input_data_len) +{ + size_t remainder, uint32_num, uint8_num, i; + uint32_t uint32_data; + uint8_t uint8_data[4] = {0}; + size_t padding_len = input_data_len; + aes_clk_init(); + if ((cipher_mode == AES_ECB) || (cipher_mode == AES_CBC)) + padding_len = ((input_data_len + 15) / 16) * 16; + aes->aes_endian |= 1; + uint32_num = input_key_len / 4; + for (i = 0; i < uint32_num; i++) { - u32data = *((uint32_t*)(&aes_in_data[i * 4])); + if (i < 4) + aes->aes_key[i] = *((uint32_t*)(&input_key[input_key_len - (4 * i) - 4])); + else + aes->aes_key_ext[i - 4] = *((uint32_t*)(&input_key[input_key_len - (4 * i) - 4])); + } + remainder = input_key_len % 4; + if (remainder) + { + switch (remainder) + { + case 1: + uint8_data[0] = input_key[0]; + break; + case 2: + uint8_data[0] = input_key[0]; + uint8_data[1] = input_key[1]; + break; + case 3: + uint8_data[0] = input_key[0]; + uint8_data[1] = input_key[1]; + uint8_data[2] = input_key[2]; + break; + default: + break; + } + if (uint32_num < 4) + aes->aes_key[uint32_num] = *((uint32_t*)(&uint8_data[0])); + else + aes->aes_key_ext[uint32_num - 4] = *((uint32_t*)(&uint8_data[0])); + } + uint32_num = iv_len / 4; + for (i = 0; i < uint32_num; i++) + aes->aes_iv[i] = *((uint32_t*)(&iv[iv_len - (4 * i) - 4])); + remainder = iv_len % 4; + if (remainder) + { + switch (remainder) + { + case 1: + uint8_data[0] = iv[0]; + break; + case 2: + uint8_data[0] = iv[0]; + uint8_data[1] = iv[1]; + break; + case 3: + uint8_data[0] = iv[0]; + uint8_data[1] = iv[1]; + uint8_data[2] = iv[2]; + break; + default: + break; + } + aes->aes_iv[uint32_num] = *((uint32_t*)(&uint8_data[0])); + } + aes->mode_ctl.kmode = input_key_len / 8 - 2; /* 00:AES_128 01:AES_192 10:AES_256 11:RESERVED */ + aes->mode_ctl.cipher_mode = cipher_mode; + aes->encrypt_sel = encrypt_sel; + aes->gb_aad_end_adr = gcm_add_len - 1; + aes->gb_pc_end_adr = padding_len - 1; + aes->gb_aes_en |= 1; + + if (cipher_mode == AES_GCM) + { + uint32_num = gcm_add_len / 4; + for (i = 0; i < uint32_num; i++) + { + uint32_data = *((uint32_t*)(&gcm_add[i * 4])); + while (!aes_get_data_in_flag()) + ; + aes_write_add(uint32_data); + } + uint8_num = 4 * uint32_num; + remainder = gcm_add_len % 4; + if (remainder) + { + switch (remainder) + { + case 1: + uint8_data[0] = gcm_add[uint8_num]; + break; + case 2: + uint8_data[0] = gcm_add[uint8_num]; + uint8_data[1] = gcm_add[uint8_num + 1]; + break; + case 3: + uint8_data[0] = gcm_add[uint8_num]; + uint8_data[1] = gcm_add[uint8_num + 1]; + uint8_data[2] = gcm_add[uint8_num + 2]; + break; + default: + break; + } + uint32_data = *((uint32_t*)(&uint8_data[0])); + while (!aes_get_data_in_flag()) + ; + aes_write_add(uint32_data); + } + } +} + +static void process_less_80_bytes(uint8_t *input_data, uint8_t *output_data, size_t input_data_len, aes_cipher_mode_t cipher_mode) +{ + size_t padding_len, uint32_num, uint8_num, remainder, i; + uint32_t uint32_data; + uint8_t uint8_data[4] = {0}; + + padding_len = ((input_data_len + 15) / 16) * 16; + uint32_num = input_data_len / 4; + for (i = 0; i < uint32_num; i++) + { + uint32_data = *((uint32_t*)(&input_data[i * 4])); while (!aes_get_data_in_flag()) ; - aes_write_text(u32data); + aes_write_text(uint32_data); } - cnt = 4 * num; - remainder = data_size % 4; + uint8_num = 4 * uint32_num; + remainder = input_data_len % 4; if (remainder) { switch (remainder) { - case 1: - u8data[0] = aes_in_data[cnt]; - break; - case 2: - u8data[0] = aes_in_data[cnt]; - u8data[1] = aes_in_data[cnt + 1]; - break; - case 3: - u8data[0] = aes_in_data[cnt]; - u8data[1] = aes_in_data[cnt + 1]; - u8data[2] = aes_in_data[cnt + 2]; - break; - default: - return 0; + case 1: + uint8_data[0] = input_data[uint8_num]; + break; + case 2: + uint8_data[0] = input_data[uint8_num]; + uint8_data[1] = input_data[uint8_num + 1]; + break; + case 3: + uint8_data[0] = input_data[uint8_num]; + uint8_data[1] = input_data[uint8_num + 1]; + uint8_data[2] = input_data[uint8_num + 2]; + break; + default: + break; } - u32data = *((uint32_t*)(&u8data[0])); + uint32_data = *((uint32_t*)(&uint8_data[0])); while (!aes_get_data_in_flag()) ; - aes_write_text(u32data); + aes_write_text(uint32_data); } - if ((cipher_mod == AES_ECB) || (cipher_mod == AES_CBC)) + if ((cipher_mode == AES_ECB) || (cipher_mode == AES_CBC)) { - /* use 0 to Fill 128 bits */ - num = (padding_size - data_size) / 4; - for (i = 0; i < num; i++) + uint32_num = (padding_len - input_data_len) / 4; + for (i = 0; i < uint32_num; i++) { while (!aes_get_data_in_flag()) ; aes_write_text(0); } - /* get data */ - num = padding_size / 4; + uint32_num = padding_len / 4; } - /* get data */ - for (i = 0; i < num; i++) + for (i = 0; i < uint32_num; i++) { while (!aes_get_data_out_flag()) ; - *((uint32_t*)(&aes_out_data[i * 4])) = aes_read_out_data(); + *((uint32_t*)(&output_data[i * 4])) = aes_read_out_data(); } - if ((cipher_mod == AES_GCM) && (remainder)) + if ((cipher_mode == AES_GCM) && (remainder)) { while (!aes_get_data_out_flag()) ; - - *((uint32_t*)(&u8data[0])) = aes_read_out_data(); + *((uint32_t*)(&uint8_data[0])) = aes_read_out_data(); switch (remainder) { - case 1: - aes_out_data[num * 4] = u8data[0]; - break; - case 2: - aes_out_data[num * 4] = u8data[0]; - aes_out_data[(i * 4) + 1] = u8data[1]; - break; - case 3: - aes_out_data[num * 4] = u8data[0]; - aes_out_data[(i * 4) + 1] = u8data[1]; - aes_out_data[(i * 4) + 2] = u8data[2]; - break; - default: - return 0; + case 1: + output_data[uint32_num * 4] = uint8_data[0]; + break; + case 2: + output_data[uint32_num * 4] = uint8_data[0]; + output_data[(i * 4) + 1] = uint8_data[1]; + break; + case 3: + output_data[uint32_num * 4] = uint8_data[0]; + output_data[(i * 4) + 1] = uint8_data[1]; + output_data[(i * 4) + 2] = uint8_data[2]; + break; + default: + break; } } - return 1; } -int aes_process(uint8_t* aes_in_data, - uint8_t* aes_out_data, - uint32_t data_size, - aes_cipher_mod_t cipher_mod) +static void aes_process(uint8_t *input_data, uint8_t *output_data, size_t input_data_len, aes_cipher_mode_t cipher_mode) { - uint32_t i, temp_size; + size_t temp_len = 0; + uint32_t i = 0; - i = 0; - if (data_size >= 80) + if (input_data_len >= 80) { - for (i = 0; i < (data_size / 80); i++) - aes_process_less_80_bytes(&aes_in_data[i * 80], &aes_out_data[i * 80], 80, cipher_mod); + for (i = 0; i < (input_data_len / 80); i++) + process_less_80_bytes(&input_data[i * 80], &output_data[i * 80], 80, cipher_mode); } - temp_size = data_size % 80; - if (temp_size) - aes_process_less_80_bytes(&aes_in_data[i * 80], &aes_out_data[i * 80], temp_size, cipher_mod); - return 1; + temp_len = input_data_len % 80; + if (temp_len) + process_less_80_bytes(&input_data[i * 80], &output_data[i * 80], temp_len, cipher_mode); } -int aes_check_gcm_tag(uint32_t* aes_gcm_tag) +void aes_hard_decrypt(aes_param_t *param) { - /* check tag */ - while (!aes_get_tag_in_flag()) - ; - aes_write_tag(aes_gcm_tag); - while (!aes_check_tag()) - ; - if (aes_check_tag() == 2) + size_t padding_len = param->input_data_len; + if (param->cipher_mode == AES_CBC || param->cipher_mode == AES_ECB) { - aes_clear_chk_tag(); - return 1; + padding_len = ((padding_len + 15) / 16) * 16; } - else + aes_init(param->input_key, param->input_key_len, param->iv, param->iv_len, param->gcm_add, + param->cipher_mode, AES_HARD_DECRYPTION, param->gcm_add_len, param->input_data_len); + aes_process(param->input_data, param->output_data, padding_len, param->cipher_mode); + if (param->cipher_mode == AES_GCM) { - aes_clear_chk_tag(); - return 0; + gcm_get_tag(param->gcm_tag); + gcm_check_tag((uint32_t *)param->gcm_tag); } } + +void aes_hard_encrypt(aes_param_t *param) +{ + aes_init(param->input_key, param->input_key_len, param->iv, param->iv_len, param->gcm_add, + param->cipher_mode, AES_HARD_ENCRYPTION, param->gcm_add_len, param->input_data_len); + aes_process(param->input_data, param->output_data, param->input_data_len, param->cipher_mode); + if (param->cipher_mode == AES_GCM) + { + gcm_get_tag(param->gcm_tag); + gcm_check_tag((uint32_t *)param->gcm_tag); + } +} + diff --git a/lib/drivers/dmac.c b/lib/drivers/dmac.c index 37c569c1..46c9dcb3 100644 --- a/lib/drivers/dmac.c +++ b/lib/drivers/dmac.c @@ -337,7 +337,7 @@ int dmac_set_channel_config(dmac_channel_number_t channel_num, } static int dmac_set_channel_param(dmac_channel_number_t channel_num, - void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, + const void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, dmac_burst_trans_length_t dmac_burst_size, dmac_transfer_width_t dmac_trans_width, uint32_t blockSize) @@ -697,7 +697,7 @@ void dmac_set_shadow_invalid_flag(dmac_channel_number_t channel_num) } void dmac_set_single_mode(dmac_channel_number_t channel_num, - void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, + const void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, dmac_burst_trans_length_t dmac_burst_size, dmac_transfer_width_t dmac_trans_width, uint32_t blockSize) diff --git a/lib/drivers/fft.c b/lib/drivers/fft.c new file mode 100644 index 00000000..b5cd7431 --- /dev/null +++ b/lib/drivers/fft.c @@ -0,0 +1,69 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include + +static volatile fft_t* const fft = (volatile fft_t*)FFT_BASE_ADDR; + +static void fft_init(uint8_t point, uint8_t mode, uint16_t shift, uint8_t is_dma, uint8_t input_mode, uint8_t data_mode) +{ + fft->fft_ctrl.fft_point = point; /* 0:512, 1:256, 2:128, 3:64 */ + fft->fft_ctrl.fft_mode = mode; /* 1: fft, 0: ifft */ + fft->fft_ctrl.fft_shift = shift; + fft->fft_ctrl.dma_send = is_dma; + fft->fft_ctrl.fft_enable = 1; + fft->fft_ctrl.fft_input_mode = input_mode; + fft->fft_ctrl.fft_data_mode = data_mode; +} + +void fft_complex_uint16_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, + fft_direction_t direction, const uint64_t* input, size_t point_num, uint64_t* output) +{ + uint16_t shift = (direction==FFT_DIR_FORWARD) ? 0x1ff : 0x0; + fft_point_t point = FFT_512; + switch(point_num) + { + case 512: + point = FFT_512; + break; + case 256: + point = FFT_256; + break; + case 128: + point = FFT_128; + break; + case 64: + point = FFT_64; + break; + default: + configASSERT(!"fft point error"); + break; + } + sysctl_clock_enable(SYSCTL_CLOCK_FFT); + sysctl_reset(SYSCTL_RESET_FFT); + fft_init(point, direction, shift, 1, 0, 0); + sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_FFT_RX_REQ); + sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_FFT_TX_REQ); + dmac_set_single_mode(dma_receive_channel_num, (void*)(&fft->fft_output_fifo), output, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, + DMAC_MSIZE_4, DMAC_TRANS_WIDTH_64, point_num>>1); + dmac_set_single_mode(dma_send_channel_num, input, (void*)(&fft->fft_input_fifo), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, + DMAC_MSIZE_4, DMAC_TRANS_WIDTH_64, point_num>>1); + dmac_wait_done(dma_receive_channel_num); +} + + diff --git a/lib/drivers/hard_fft.c b/lib/drivers/hard_fft.c deleted file mode 100644 index fdab617c..00000000 --- a/lib/drivers/hard_fft.c +++ /dev/null @@ -1,150 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include -#include "encoding.h" -#include "hard_fft.h" -#include "platform.h" -#include "syscalls.h" -#include "sysctl.h" - -#define FFT_RESULT_ADDR (0x42100000 + 0x2000) -volatile uint64_t* fft_result = (volatile uint64_t*)FFT_RESULT_ADDR; - -volatile fft_t* const fft = (volatile fft_t*)FFT_BASE_ADDR; - -int fft_init(uint8_t point, uint8_t mode, uint16_t shift, uint8_t is_dma, uint8_t input_mode, uint8_t data_mode) -{ - fft->fft_ctrl.fft_point = point; /* 0:512, 1:256, 2:128, 3:64 */ - fft->fft_ctrl.fft_mode = mode; /* 1: fft, 0: ifft */ - fft->fft_ctrl.fft_shift = shift; - fft->fft_ctrl.dma_send = is_dma; - fft->fft_ctrl.fft_enable = 1; - fft->fft_ctrl.fft_input_mode = input_mode; - fft->fft_ctrl.fft_data_mode = data_mode; - return 0; -} - -void fft_reset(void) -{ - fft->fifo_ctrl.resp_fifo_flush_n = 0; - fft->fifo_ctrl.cmd_fifo_flush_n = 0; - fft->fifo_ctrl.gs_fifo_flush_n = 0; -} - -void fft_enable_int(void) -{ - fft->intr_mask.fft_done_mask = 1; -} - -void fft_input_data(float* x, float* y, uint8_t point) -{ - uint16_t point_num = 0; - uint16_t i; - fft_data_t input_data; - - if (point == 0) - point_num = 512; - else if (point == 1) - point_num = 256; - else if (point == 2) - point_num = 128; - else if (point == 3) - point_num = 64; - point_num = point_num / 2; /* one time send two data */ - - for (i = 0; i < point_num; i++) - { - input_data.R1 = (int16_t)(x[2 * i] * 32); - input_data.I1 = (int16_t)(y[2 * i] * 32); - input_data.R2 = (int16_t)(x[2 * i + 1] * 32); - input_data.I2 = (int16_t)(y[2 * i + 1] * 32); - - fft->fft_input_fifo.fft_input_fifo = *(uint64_t*)&input_data; - printf("%d, %d\n", input_data.R1, input_data.I1); - printf("%d, %d\n", input_data.R2, input_data.I2); - } -} - -void fft_input_intdata(int16_t* data, uint8_t point) -{ - uint16_t point_num = 0; - uint16_t i; - fft_data_t input_data; - - if (point == 0) - point_num = 512; - else if (point == 1) - point_num = 256; - else if (point == 2) - point_num = 128; - else if (point == 3) - point_num = 64; - point_num = point_num / 2; /* one time send two data */ - - for (i = 0; i < point_num; i++) - { - input_data.R1 = data[2 * i]; - input_data.I1 = 0; - input_data.R2 = data[2 * i + 1]; - input_data.I2 = 0; - - fft->fft_input_fifo.fft_input_fifo = *(uint64_t*)&input_data; - } -} - -uint8_t fft_get_finish_flag(void) -{ - return (uint8_t)fft->fft_status.fft_done_status & 0x01; -} - -void FixToDou(float* fData, uint32_t u32Data) -{ - if (u32Data & 0x8000) - *fData = -((float)(u32Data & 0x7fff)) / 32; - else - *fData = ((float)u32Data) / 32; -} - -void fft_get_result(float* x, float* y, uint8_t point) -{ - uint64_t u64Data; - uint16_t point_num = 0; - uint16_t i; - fft_data_t output_data; - - if (point == 0) - point_num = 512; - else if (point == 1) - point_num = 256; - else if (point == 2) - point_num = 128; - else if (point == 3) - point_num = 64; - point_num = point_num / 2; - - for (i = 0; i < point_num; i++) - { - u64Data = fft_result[i]; /*fft->fft_output_fifo.fft_output_fifo;*/ - - output_data = *(fft_data_t*)&u64Data; - - x[2 * i] = ((float)output_data.R1) / 32; - y[2 * i] = ((float)output_data.I1) / 32; - x[2 * i + 1] = ((float)output_data.R2) / 32; - y[2 * i + 1] = ((float)output_data.I2) / 32; - } -} - diff --git a/lib/drivers/include/aes.h b/lib/drivers/include/aes.h index b47c33d5..d48c3349 100644 --- a/lib/drivers/include/aes.h +++ b/lib/drivers/include/aes.h @@ -14,15 +14,34 @@ */ #ifndef _DRIVER_AES_H #define _DRIVER_AES_H - +#include #include -#include "encoding.h" -#include "platform.h" #ifdef __cplusplus extern "C" { #endif +typedef enum _aes_cipher_mode +{ + AES_ECB = 0, + AES_CBC = 1, + AES_GCM = 2, + CIPHER_MAX, +} aes_cipher_mode_t; + +typedef enum _aes_kmode +{ + AES_128 = 16, + AES_192 = 24, + AES_256 = 32, +} aes_kmode_t; + +typedef enum _aes_encrypt_sel +{ + AES_HARD_ENCRYPTION = 0, + AES_HARD_DECRYPTION = 1, +} aes_encrypt_sel_t; + typedef struct _aes_mode_ctl { /* set the first bit and second bit 00:ecb; 01:cbc,10：aes_gcm */ @@ -85,170 +104,23 @@ typedef struct _aes uint32_t aes_key_ext[4]; } __attribute__((packed, aligned(4))) aes_t; -typedef enum _aes_cipher_mod -{ - AES_ECB = 0, - AES_CBC = 1, - AES_GCM = 2, -} aes_cipher_mod_t; - -typedef enum _aes_kmode -{ - AES_128 = 0, - AES_192 = 1, - AES_256 = 2, -} aes_kmode_t; - -typedef enum _aes_encrypt_sel +typedef struct _aes_param { - AES_ENCRYPTION = 0, - AES_DECRYPTION = 1, -} aes_encrypt_sel_t; - -/** - * @brief Aes initialize - * - * @param[in] key_addr Key address - * @param[in] key_length Key length - * @param[in] aes_iv Aes iv - * @param[in] iv_length Iv length - * @param[in] aes_aad Aes aad - * @param[in] cipher_mod Aes cipher mode - * @param[in] encrypt_sel Aes encrypt select - * @param[in] add_size Aad size - * @param[in] data_size Data size - * - * @return result - * - 1 Success - * - Other Fail - */ -int aes_init(uint8_t* key_addr, uint8_t key_length, uint8_t* aes_iv, - uint8_t iv_length, uint8_t* aes_aad, aes_cipher_mod_t cipher_mod, - aes_encrypt_sel_t encrypt_sel, uint32_t add_size, uint32_t data_size); - -/** - * @brief Aes write aad data - * - * @param[in] aad_data Aes aad data - * - * @return result - * - 0 Success - * - Other Fail - */ -int aes_write_aad(uint32_t aad_data); - -/** - * @brief Aes write text data - * - * @param[in] text_data Aes aad data - * - * @return result - * - 0 Success - * - Other Fail - */ -int aes_write_text(uint32_t text_data); - -/** - * @brief Aes write tag - * - * @param[in] text_data Aes tag point - * - * @return result - * - 0 Success - * - Other Fail - */ -int aes_write_tag(uint32_t* tag); - -/** - * @brief Aes get data in flag - * - * @return Data in flag - */ -int aes_get_data_in_flag(void); - -/** - * @brief Aes get data out flag - * - * @return Data out flag - */ -int aes_get_data_out_flag(void); - -/** - * @brief Aes get tag in flag - * - * @return Tag in flag - */ -int aes_get_tag_in_flag(void); - -/** - * @brief Aes read out data - * - * @return Out data - */ -uint32_t aes_read_out_data(void); - -/** - * @brief Aes check tag - * - * @return Tag check result - * - 0 Check not finish - * - 1 Check fail - * - 2 Check success - */ -int aes_check_tag(void); - -/** - * @brief Aes get gcm out tag - * - * @param[out] l_tag gcm out tag - * - * @return Tag check result - * - 1 Success - * - Other Fail - */ -int aes_get_tag(uint8_t* l_tag); - -/** - * @brief Aes clear check tag - * - * @return Tag check result - * - 0 Success - * - Other Fail - */ -int aes_clear_chk_tag(void); - -/** - * @brief Aes process - * - * @param[in] aes_in_data Aes in data - * @param[in] aes_out_data Aes out data - * @param[in] data_size Aes data size - * @param[in] cipher_mod Aes cipher mode - * - * @return Tag check result - * - 1 Success - * - Other Fail - */ -int aes_process(uint8_t* aes_in_data, - uint8_t* aes_out_data, - uint32_t data_size, - aes_cipher_mod_t cipher_mod); - -/** - * @brief Aes check gcm tag - * - * @param[in] aes_gcm_tag Aes gcm tag - * - * @return Tag check result - * - 1 Success - * - Other Fail - */ -int aes_check_gcm_tag(uint32_t* aes_gcm_tag); - -/** - * @brief Aes clock initialize - */ -void aes_clkinit(); + uint8_t *input_data; + size_t input_data_len; + uint8_t *input_key; + size_t input_key_len; + uint8_t *iv; + uint8_t iv_len; + uint8_t* gcm_add; + size_t gcm_add_len; + aes_cipher_mode_t cipher_mode; + uint8_t *output_data; + uint8_t *gcm_tag; +} aes_param_t; + +void aes_hard_decrypt(aes_param_t *param); +void aes_hard_encrypt(aes_param_t *param); #ifdef __cplusplus } diff --git a/lib/drivers/include/dmac.h b/lib/drivers/include/dmac.h index e733ba74..76cd8b83 100644 --- a/lib/drivers/include/dmac.h +++ b/lib/drivers/include/dmac.h @@ -1418,7 +1418,7 @@ void dmac_init(void); * */ void dmac_set_single_mode(dmac_channel_number_t channel_num, - void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, + const void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, dmac_burst_trans_length_t dmac_burst_size, dmac_transfer_width_t dmac_trans_width, uint32_t blockSize); diff --git a/lib/drivers/include/hard_fft.h b/lib/drivers/include/fft.h similarity index 73% rename from lib/drivers/include/hard_fft.h rename to lib/drivers/include/fft.h index dd3dba48..f18a90a8 100644 --- a/lib/drivers/include/hard_fft.h +++ b/lib/drivers/include/fft.h @@ -12,8 +12,8 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef _DRIVER_HARD_FFT_H -#define _DRIVER_HARD_FFT_H +#ifndef _DRIVER_FFT_H +#define _DRIVER_FFT_H #include #include "platform.h" @@ -38,18 +38,17 @@ typedef struct _fft_data typedef enum _fft_point { - FFT_N512, - FFT_N256, - FFT_N128, - FFT_N64, + FFT_512, + FFT_256, + FFT_128, + FFT_64, } fft_point_t; -typedef enum _fft_mode +typedef enum _fft_direction { - IFFT_MODE, - FFT_MODE, -} fft_mode_t; - + FFT_DIR_BACKWARD, + FFT_DIR_FORWARD +} fft_direction_t; /** * @brief FFT algorithm accelerator register @@ -195,73 +194,9 @@ typedef struct _fft fft_fft_output_fifo_t fft_output_fifo; } __attribute__((packed, aligned(8))) fft_t; -/** - * @brief Fft initialize - * - * @param[in] point fft point, 0:512, 1:256, 2:128, 3:64 - * @param[in] mode fft or ifft, 1: fft, 0: ifft - * @param[in] shift fft shift - * @param[in] is_dma dma send flag - * @param[in] input_mode fft input mode - * @param[in] data_mode fft data mode - * - * @return Result - * 0 Success - * Other Fail - */ -int fft_init(uint8_t point, uint8_t mode, uint16_t shift, uint8_t is_dma, uint8_t input_mode, uint8_t data_mode); - -/** - * @brief Fft reset - * - */ -void fft_reset(void); - -/** - * @brief Enable fft done interrupt - * - */ -void fft_enable_int(void); - -/** - * @brief Fft input data(complex numbers) - * - * @param[in] x complex numbers real part - * @param[in] y complex numbers imaginary part - * @param[in] point fft point - */ -void fft_input_data(float *x, float *y, uint8_t point); - -/** - * @brief Fft input data(integer) - * - * @param[in] data integer - * @param[in] point fft point - */ -void fft_input_intdata(int16_t *data, uint8_t point); - -/** - * @brief Get fft finish flag - * - * @return Result - * 1 Fft finish - * Other Not complete - */ -uint8_t fft_get_finish_flag(void); - -/** - * @brief Get fft result - * - * @param[out] x complex numbers real part - * @param[out] y complex numbers imaginary part - * @param[in] point fft point - */ -void fft_get_result(float *x, float *y, uint8_t point); -/** - * @brief Fast Fourier transform (FFT) algorithm accelerator object - */ -extern volatile fft_t *const fft; +void fft_complex_uint16_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, + fft_direction_t direction, const uint64_t* input, size_t point_num, uint64_t* output); #ifdef __cplusplus } diff --git a/lib/drivers/include/sha256.h b/lib/drivers/include/sha256.h index 01d32703..415c9ee4 100644 --- a/lib/drivers/include/sha256.h +++ b/lib/drivers/include/sha256.h @@ -14,81 +14,46 @@ */ #ifndef _SHA256_H #define _SHA256_H - #include -#include "encoding.h" -#include "platform.h" -#define DISABLE_SHA_DMA 0 -#define ENABLE_SHA_DMA 1 +#ifdef __cplusplus +extern "C" { +#endif + +#define ENABLE_SHA 1 +#define SHA256_BIG_ENDIAN (0x1 << 16) + +#define SHA256_HASH_LEN 32 +#define SHA256_HASH_WORDS 8 +#define SHA256_BLOCK_LEN 64L -/** - * @brief AES - * - */ typedef struct _sha256 { uint32_t sha_result[8]; uint32_t sha_data_in1; uint32_t sha_data_in2; - uint32_t sha_data_num; /*1 unit represents 64 bytes*/ + uint32_t sha_data_num; uint32_t sha_status; uint32_t reserved0; uint32_t sha_input_ctrl; } __attribute__((packed, aligned(4))) sha256_t; -#define SHA256_HASH_SIZE 32 - -/* Hash size in 32-bit words */ -#define SHA256_HASH_WORDS 8 - -struct _SHA256Context +typedef struct _sha256_context { - uint64_t totalLength; - uint32_t hash[SHA256_HASH_WORDS]; - uint32_t bufferLength; + size_t total_length; + size_t buffer_length; union { uint32_t words[16]; uint8_t bytes[64]; } buffer; -#ifdef RUNTIME_ENDIAN - int littleEndian; -#endif /* RUNTIME_ENDIAN */ -}; +} sha256_context_t; -typedef struct _SHA256Context SHA256Context_t; +void sha256_hard_calculate(const uint8_t *data, size_t data_len, uint8_t *output); -/** - * @brief Sha256 initialize - * - * @param[in] dma_en Dma enable flag - * @param[in] input_size Input size - * @param[in] sc Sha256 Context point - * - * @return Result - * - 0 Success - * - Other Fail - */ -int sha256_init(uint8_t dma_en, uint32_t input_size, SHA256Context_t *sc); - -/** - * @brief Sha256 update - * - * @param[in] sc Sha256 Context point - * @param[in] data Input data point - * @param[in] len Input data size - * - */ -void sha256_update(SHA256Context_t *sc, const void *data, uint32_t len); - -/** - * @brief Sha256 final - * - * @param[in] sc Sha256 Context point - * @param[out] hash Sha256 result - * - */ -void sha256_final(SHA256Context_t *sc, uint8_t hash[SHA256_HASH_SIZE]); +#ifdef __cplusplus +} +#endif #endif + diff --git a/lib/drivers/sha256.c b/lib/drivers/sha256.c index 458e33ac..9a33ae97 100644 --- a/lib/drivers/sha256.c +++ b/lib/drivers/sha256.c @@ -12,27 +12,16 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#include -#include -#include "encoding.h" -#include "sha256.h" -#include "syscalls.h" -#include "sysctl.h" - -volatile sha256_t* const sha256 = (volatile sha256_t*)SHA256_BASE_ADDR; +#include +#include +#include #define ROTL(x, n) (((x) << (n)) | ((x) >> (32 - (n)))) #define ROTR(x, n) (((x) >> (n)) | ((x) << (32 - (n)))) -#define _BYTESWAP(x) ((ROTR((x), 8) & 0xff00ff00L) | (ROTL((x), 8) & 0x00ff00ffL)) -#define _BYTESWAP64(x) __byteswap64(x) +#define BYTESWAP(x) ((ROTR((x), 8) & 0xff00ff00L) | (ROTL((x), 8) & 0x00ff00ffL)) +#define BYTESWAP64(x) byteswap64(x) -static inline uint64_t __byteswap64(uint64_t x) -{ - uint32_t a = x >> 32; - uint32_t b = (uint32_t)x; - - return ((uint64_t)_BYTESWAP(b) << 32) | (uint64_t)_BYTESWAP(a); -} +volatile sha256_t* const sha256 = (volatile sha256_t*)SHA256_BASE_ADDR; static const uint8_t padding[64] = { 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -42,94 +31,90 @@ static const uint8_t padding[64] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00}; + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00 +}; -int sha256_init(uint8_t dma_en, uint32_t input_size, SHA256Context_t* sc) +static inline uint64_t byteswap64(uint64_t x) { + uint32_t a = x >> 32; + uint32_t b = (uint32_t)x; + return ((uint64_t)BYTESWAP(b) << 32) | (uint64_t)BYTESWAP(a); +} + +static void sha256_init(sha256_context_t *context, size_t buf_len) +{ + size_t padding_len = 0; sysctl_clock_enable(SYSCTL_CLOCK_SHA); sysctl_reset(SYSCTL_RESET_SHA); - input_size = (input_size + 64) / 64; - if (dma_en) - sha256->sha_input_ctrl |= 1; - else - sha256->sha_input_ctrl &= ~0x01; - - sha256->sha_data_num = input_size; - - sha256->sha_status |= 1 << 16; /*0 for little endian, 1 for big endian*/ - sha256->sha_status |= 1; /*enable sha256*/ - - sc->totalLength = 0LL; - sc->hash[0] = 0x6a09e667L; - sc->hash[1] = 0xbb67ae85L; - sc->hash[2] = 0x3c6ef372L; - sc->hash[3] = 0xa54ff53aL; - sc->hash[4] = 0x510e527fL; - sc->hash[5] = 0x9b05688cL; - sc->hash[6] = 0x1f83d9abL; - sc->hash[7] = 0x5be0cd19L; - sc->bufferLength = 0L; - return 1; + padding_len = (buf_len + SHA256_BLOCK_LEN + 8) / SHA256_BLOCK_LEN; + sha256->sha_input_ctrl &= (~0x1); + sha256->sha_data_num = padding_len; + sha256->sha_status |= SHA256_BIG_ENDIAN; + sha256->sha_status |= ENABLE_SHA; + context->total_length = 0LL; + context->buffer_length = 0L; } -void sha256_update(SHA256Context_t* sc, const void* vdata, uint32_t len) +static void sha256_update(sha256_context_t *context, const void *data_buf, size_t buf_len) { - const uint8_t* data = vdata; - uint32_t bufferBytesLeft; - uint32_t bytesToCopy; + const uint8_t* data = data_buf; + size_t buffer_bytes_left; + size_t bytes_to_copy; uint32_t i; - while (len) + while (buf_len) { - bufferBytesLeft = 64L - sc->bufferLength; - - bytesToCopy = bufferBytesLeft; - if (bytesToCopy > len) - bytesToCopy = len; - - memcpy(&sc->buffer.bytes[sc->bufferLength], data, bytesToCopy); - - sc->totalLength += bytesToCopy * 8L; - - sc->bufferLength += bytesToCopy; - data += bytesToCopy; - len -= bytesToCopy; - - if (sc->bufferLength == 64L) + buffer_bytes_left = SHA256_BLOCK_LEN - context->buffer_length; + bytes_to_copy = buffer_bytes_left; + if (bytes_to_copy > buf_len) + bytes_to_copy = buf_len; + memcpy(&context->buffer.bytes[context->buffer_length], data, bytes_to_copy); + context->total_length += bytes_to_copy * 8; + context->buffer_length += bytes_to_copy; + data += bytes_to_copy; + buf_len -= bytes_to_copy; + if (context->buffer_length == SHA256_BLOCK_LEN) { for (i = 0; i < 16; i++) { while (sha256->sha_input_ctrl & (1 << 8)) ; - sha256->sha_data_in1 = sc->buffer.words[i]; + sha256->sha_data_in1 = context->buffer.words[i]; } - sc->bufferLength = 0L; + context->buffer_length = 0L; } } } -void sha256_final(SHA256Context_t* sc, uint8_t hash[SHA256_HASH_SIZE]) +static void sha256_final(sha256_context_t *context, uint8_t *output) { - uint32_t bytesToPad; - uint64_t lengthPad; - int i; - - bytesToPad = 120L - sc->bufferLength; - if (bytesToPad > 64L) - bytesToPad -= 64L; - lengthPad = _BYTESWAP64(sc->totalLength); - sha256_update(sc, padding, bytesToPad); - sha256_update(sc, &lengthPad, 8L); + size_t bytes_to_pad; + size_t length_pad; + uint32_t i; + bytes_to_pad = 120 - context->buffer_length; + if (bytes_to_pad > 64) + bytes_to_pad -= 64; + length_pad = BYTESWAP64(context->total_length); + sha256_update(context, padding, bytes_to_pad); + sha256_update(context, &length_pad, 8); while (!(sha256->sha_status & 0x01)) ; - - if (hash) + if (output) { for (i = 0; i < SHA256_HASH_WORDS; i++) { - *((uint32_t*)hash) = sha256->sha_result[SHA256_HASH_WORDS - i - 1]; - hash += 4; + *((uint32_t*)output) = sha256->sha_result[SHA256_HASH_WORDS - i - 1]; + output += 4; } } } + +void sha256_hard_calculate(const uint8_t *data, size_t data_len, uint8_t *output) +{ + sha256_context_t sha; + sha256_init(&sha, data_len); + sha256_update(&sha, data, data_len); + sha256_final(&sha, output); +} + diff --git a/src/hello_world/main.c b/src/hello_world/main.c index 0e987e38..68b58067 100644 --- a/src/hello_world/main.c +++ b/src/hello_world/main.c @@ -1,36 +1,36 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "sleep.h" -#include "encoding.h" -float power[512]; -uint64_t fft_out_data[256]; - -int main() -{ - uint64_t core_id = current_coreid(); - if (core_id == 0) - { - printf("Core 0 Hello, world!\n"); - } - else - { - msleep(100); - printf("Core 1 Hello, world!\n"); - } - while (1) - ; - return 0; -} +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "sleep.h" +#include "encoding.h" +float power[512]; +uint64_t fft_out_data[256]; + +int main() +{ + uint64_t core_id = current_coreid(); + if (core_id == 0) + { + printf("Core 0 Hello, world!\n"); + } + else + { + msleep(100); + printf("Core 1 Hello, world!\n"); + } + while (1) + ; + return 0; +} From a7aff2e528cb4167883b15a9f91630393cede944 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Sun, 30 Sep 2018 12:31:11 +0800 Subject: [PATCH 17/58] Modify sysctrl --- lib/drivers/common.c | 11 ----------- lib/drivers/include/sysctl.h | 10 ++++++++++ lib/drivers/include/utils.h | 10 ---------- lib/drivers/sysctl.c | 13 +++++++++++++ 4 files changed, 23 insertions(+), 21 deletions(-) diff --git a/lib/drivers/common.c b/lib/drivers/common.c index c06b6005..005ef743 100644 --- a/lib/drivers/common.c +++ b/lib/drivers/common.c @@ -42,14 +42,3 @@ uint32_t get_gpio_bit(volatile uint32_t* bits, size_t offset) return get_bit(bits, 1, offset); } -void machine_irq_enable(void) -{ - set_csr(mie, MIP_MEIP); - set_csr(mstatus, MSTATUS_MIE); -} - -void machine_irq_disable(void) -{ - clear_csr(mie, MIP_MEIP); - clear_csr(mstatus, MSTATUS_MIE); -} diff --git a/lib/drivers/include/sysctl.h b/lib/drivers/include/sysctl.h index 91a69ce9..54b31e8e 100644 --- a/lib/drivers/include/sysctl.h +++ b/lib/drivers/include/sysctl.h @@ -1052,6 +1052,16 @@ uint32_t sysctl_set_cpu_frequency(uint32_t frequency); */ void sysctl_set_pll_frequency(uint64_t pll0, uint64_t pll1, uint64_t pll2); +/** + * @brief Enable interrupt + */ +void sysctl_enable_irq(void); + +/** + * @brief Disable interrupt + */ +void sysctl_disable_irq(void); + #ifdef __cplusplus } #endif diff --git a/lib/drivers/include/utils.h b/lib/drivers/include/utils.h index ae2af7b9..28cf3df9 100644 --- a/lib/drivers/include/utils.h +++ b/lib/drivers/include/utils.h @@ -340,16 +340,6 @@ uint32_t get_bit(volatile uint32_t* bits, uint32_t mask, size_t offset); */ uint32_t get_gpio_bit(volatile uint32_t* bits, size_t offset); -/** - * @brief Enable interrupt - */ -void machine_irq_enable(); - -/** - * @brief Disable interrupt - */ -void machine_irq_disable(); - #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/lib/drivers/sysctl.c b/lib/drivers/sysctl.c index ac0ce449..020a6466 100644 --- a/lib/drivers/sysctl.c +++ b/lib/drivers/sysctl.c @@ -18,6 +18,7 @@ #include #include "sysctl.h" #include "string.h" +#include "encoding.h" #define SYSCTRL_CLOCK_FREQ_IN0 (26000000UL) @@ -1791,3 +1792,15 @@ uint32_t sysctl_set_cpu_frequency(uint32_t frequency) return result; } +void sysctl_enable_irq(void) +{ + set_csr(mie, MIP_MEIP); + set_csr(mstatus, MSTATUS_MIE); +} + +void sysctl_disable_irq(void) +{ + clear_csr(mie, MIP_MEIP); + clear_csr(mstatus, MSTATUS_MIE); +} + From 099b055b19e9977146b7c95df3d2dcde4761f1a7 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Sun, 30 Sep 2018 14:48:22 +0800 Subject: [PATCH 18/58] Add const --- lib/drivers/dmac.c | 4 ++-- lib/drivers/i2c.c | 8 ++++---- lib/drivers/i2s.c | 2 +- lib/drivers/include/dmac.h | 2 +- lib/drivers/include/i2c.h | 8 ++++---- lib/drivers/include/i2s.h | 2 +- lib/drivers/include/spi.h | 20 ++++++++++---------- lib/drivers/spi.c | 20 ++++++++++---------- lib/drivers/utils.c | 11 ----------- 9 files changed, 33 insertions(+), 44 deletions(-) diff --git a/lib/drivers/dmac.c b/lib/drivers/dmac.c index 37c569c1..46c9dcb3 100644 --- a/lib/drivers/dmac.c +++ b/lib/drivers/dmac.c @@ -337,7 +337,7 @@ int dmac_set_channel_config(dmac_channel_number_t channel_num, } static int dmac_set_channel_param(dmac_channel_number_t channel_num, - void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, + const void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, dmac_burst_trans_length_t dmac_burst_size, dmac_transfer_width_t dmac_trans_width, uint32_t blockSize) @@ -697,7 +697,7 @@ void dmac_set_shadow_invalid_flag(dmac_channel_number_t channel_num) } void dmac_set_single_mode(dmac_channel_number_t channel_num, - void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, + const void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, dmac_burst_trans_length_t dmac_burst_size, dmac_transfer_width_t dmac_trans_width, uint32_t blockSize) diff --git a/lib/drivers/i2c.c b/lib/drivers/i2c.c index a8920b94..5c719a49 100644 --- a/lib/drivers/i2c.c +++ b/lib/drivers/i2c.c @@ -64,7 +64,7 @@ void i2c_config(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t ad i2c_adapter->enable = I2C_ENABLE_ENABLE; } -int i2c_send_data(i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len) +int i2c_send_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len) { configASSERT(i2c_num < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[i2c_num]; @@ -85,7 +85,7 @@ int i2c_send_data(i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_bu return 0; } -int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len) +int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len) { configASSERT(i2c_num < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[i2c_num]; @@ -112,7 +112,7 @@ int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t return 0; } -int i2c_receive_data(i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len) +int i2c_receive_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len) { uint8_t fifo_len, index; uint8_t rx_len = receive_buf_len; @@ -149,7 +149,7 @@ int i2c_receive_data(i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send } int i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len) + i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len) { configASSERT(i2c_num < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[i2c_num]; diff --git a/lib/drivers/i2s.c b/lib/drivers/i2s.c index 0bf4c731..bd7702ba 100644 --- a/lib/drivers/i2s.c +++ b/lib/drivers/i2s.c @@ -381,7 +381,7 @@ int i2s_send_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, return 0; } -void i2s_send_data_dma(i2s_device_number_t device_num, void *buf, size_t buf_len, dmac_channel_number_t channel_num) +void i2s_send_data_dma(i2s_device_number_t device_num, const void *buf, size_t buf_len, dmac_channel_number_t channel_num) { static uint8_t dmac_init_flag[6] = {0,0,0,0,0,0}; if(dmac_init_flag[channel_num]) diff --git a/lib/drivers/include/dmac.h b/lib/drivers/include/dmac.h index e733ba74..76cd8b83 100644 --- a/lib/drivers/include/dmac.h +++ b/lib/drivers/include/dmac.h @@ -1418,7 +1418,7 @@ void dmac_init(void); * */ void dmac_set_single_mode(dmac_channel_number_t channel_num, - void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, + const void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, dmac_burst_trans_length_t dmac_burst_size, dmac_transfer_width_t dmac_trans_width, uint32_t blockSize); diff --git a/lib/drivers/include/i2c.h b/lib/drivers/include/i2c.h index 581fdd8b..cc8aed57 100644 --- a/lib/drivers/include/i2c.h +++ b/lib/drivers/include/i2c.h @@ -361,7 +361,7 @@ void i2c_config(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t ad * - 0 Success * - Other Fail */ -int i2c_send_data(i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len); +int i2c_send_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len); /** * @brief I2c send data by dma @@ -375,7 +375,7 @@ int i2c_send_data(i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_bu * - 0 Success * - Other Fail */ -int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len); +int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len); /** * @brief I2c receive data @@ -390,7 +390,7 @@ int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t * - 0 Success * - Other Fail */ -int i2c_receive_data(i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len); +int i2c_receive_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len); /** * @brief I2c receive data by dma @@ -408,7 +408,7 @@ int i2c_receive_data(i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send * - Other Fail */ int i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - i2c_device_number_t i2c_num, uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len); + i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len); #ifdef __cplusplus } diff --git a/lib/drivers/include/i2s.h b/lib/drivers/include/i2s.h index 1a6d3e6e..269451db 100644 --- a/lib/drivers/include/i2s.h +++ b/lib/drivers/include/i2s.h @@ -661,7 +661,7 @@ int i2s_receive_data_dma(i2s_device_number_t device_num, uint32_t *buf, size_t b * @param[in] channel_num dmac channel * */ -void i2s_send_data_dma(i2s_device_number_t device_num, void *buf, size_t buf_len, dmac_channel_number_t channel_num); +void i2s_send_data_dma(i2s_device_number_t device_num, const void *buf, size_t buf_len, dmac_channel_number_t channel_num); /** * @brief I2S receive channel configure diff --git a/lib/drivers/include/spi.h b/lib/drivers/include/spi.h index 0662cecd..c2ab1383 100644 --- a/lib/drivers/include/spi.h +++ b/lib/drivers/include/spi.h @@ -201,7 +201,7 @@ int spi_config_non_standard(spi_device_num_t spi_num, uint32_t instruction_lengt * - 0 Success * - Other Fail */ -int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); +int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len); /** * @brief Spi receive data @@ -217,7 +217,7 @@ int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_sele * - 0 Success * - Other Fail */ -int spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +int spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special receive data @@ -233,7 +233,7 @@ int spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_s * - 0 Success * - Other Fail */ -int spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +int spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special send data @@ -249,7 +249,7 @@ int spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_s * - 0 Success * - Other Fail */ -int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); +int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len); /** * @brief Spi send data by dma @@ -267,7 +267,7 @@ int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_sele * - Other Fail */ int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, - uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); + const uint8_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len); /** * @brief Spi receive data by dma @@ -286,7 +286,7 @@ int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num * - Other Fail */ int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); + spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special send data by dma @@ -304,7 +304,7 @@ int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dm * - Other Fail */ int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, spi_chip_select_t chip_select, - uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len); + const uint32_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len); /** * @brief Spi special receive data by dma @@ -323,7 +323,7 @@ int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_ * - Other Fail */ int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); + spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi fill dma @@ -338,7 +338,7 @@ int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dm * - 0 Success * - Other Fail */ -int spi_fill_data_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *tx_buff, size_t tx_len); +int spi_fill_data_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *tx_buff, size_t tx_len); /** * @brief Spi normal send by dma @@ -355,7 +355,7 @@ int spi_fill_data_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num * - Other Fail */ int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, - void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width); + const void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width); /** * @brief Spi normal send by dma diff --git a/lib/drivers/spi.c b/lib/drivers/spi.c index 2d29b3d7..621a28ab 100644 --- a/lib/drivers/spi.c +++ b/lib/drivers/spi.c @@ -160,7 +160,7 @@ uint32_t spi_set_clk_rate(spi_device_num_t spi_num, uint32_t spi_clk) return sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_num) / spi_baudr; } -int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) +int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len) { uint32_t index, fifo_len; configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -194,7 +194,7 @@ int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_sele } int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, - uint8_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) + const uint8_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); spi_set_tmod(spi_num, SPI_TMOD_TRANS); @@ -228,7 +228,7 @@ int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num } int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, - void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width) + const void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); spi_set_tmod(spi_num, SPI_TMOD_TRANS); @@ -269,7 +269,7 @@ int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t return 0; } -int spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +int spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { uint32_t index, fifo_len; configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -294,7 +294,7 @@ int spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_s } int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - spi_device_num_t spi_num, spi_chip_select_t chip_select, uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) + spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); spi_set_tmod(spi_num, SPI_TMOD_EEROM); @@ -331,7 +331,7 @@ int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dm return 0; } -int spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +int spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { uint32_t index, fifo_len; configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -356,7 +356,7 @@ int spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_s } int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) + spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); spi_set_tmod(spi_num, SPI_TMOD_RECV); @@ -393,7 +393,7 @@ int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dm return 0; } -int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) +int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len) { uint32_t index, fifo_len; configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -424,7 +424,7 @@ int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_sele } int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, spi_chip_select_t chip_select, - uint32_t *cmd_buff, size_t cmd_len, uint8_t *tx_buff, size_t tx_len) + const uint32_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); spi_set_tmod(spi_num, SPI_TMOD_TRANS); @@ -457,7 +457,7 @@ int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_ return 0; } -int spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, uint32_t *tx_buff, size_t tx_len) +int spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *tx_buff, size_t tx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); spi_set_tmod(spi_num, SPI_TMOD_TRANS); diff --git a/lib/drivers/utils.c b/lib/drivers/utils.c index c06b6005..005ef743 100644 --- a/lib/drivers/utils.c +++ b/lib/drivers/utils.c @@ -42,14 +42,3 @@ uint32_t get_gpio_bit(volatile uint32_t* bits, size_t offset) return get_bit(bits, 1, offset); } -void machine_irq_enable(void) -{ - set_csr(mie, MIP_MEIP); - set_csr(mstatus, MSTATUS_MIE); -} - -void machine_irq_disable(void) -{ - clear_csr(mie, MIP_MEIP); - clear_csr(mstatus, MSTATUS_MIE); -} From 86eb6953a7bcf84f9612f2a7f595e9f1def2b8e8 Mon Sep 17 00:00:00 2001 From: jiangxiangbing Date: Sun, 30 Sep 2018 15:04:53 +0800 Subject: [PATCH 19/58] update fft --- lib/drivers/fft.c | 4 ++-- lib/drivers/include/aes.h | 2 +- lib/drivers/include/fft.h | 2 +- src/hello_world/main.c | 3 --- 4 files changed, 4 insertions(+), 7 deletions(-) diff --git a/lib/drivers/fft.c b/lib/drivers/fft.c index b5cd7431..6f4866c9 100644 --- a/lib/drivers/fft.c +++ b/lib/drivers/fft.c @@ -18,7 +18,7 @@ #include #include -static volatile fft_t* const fft = (volatile fft_t*)FFT_BASE_ADDR; +static volatile fft_t *const fft = (volatile fft_t *)FFT_BASE_ADDR; static void fft_init(uint8_t point, uint8_t mode, uint16_t shift, uint8_t is_dma, uint8_t input_mode, uint8_t data_mode) { @@ -32,7 +32,7 @@ static void fft_init(uint8_t point, uint8_t mode, uint16_t shift, uint8_t is_dma } void fft_complex_uint16_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - fft_direction_t direction, const uint64_t* input, size_t point_num, uint64_t* output) + fft_direction_t direction, const uint64_t *input, size_t point_num, uint64_t *output) { uint16_t shift = (direction==FFT_DIR_FORWARD) ? 0x1ff : 0x0; fft_point_t point = FFT_512; diff --git a/lib/drivers/include/aes.h b/lib/drivers/include/aes.h index d48c3349..25184803 100644 --- a/lib/drivers/include/aes.h +++ b/lib/drivers/include/aes.h @@ -26,7 +26,7 @@ typedef enum _aes_cipher_mode AES_ECB = 0, AES_CBC = 1, AES_GCM = 2, - CIPHER_MAX, + AES_CIPHER_MAX, } aes_cipher_mode_t; typedef enum _aes_kmode diff --git a/lib/drivers/include/fft.h b/lib/drivers/include/fft.h index f18a90a8..07502495 100644 --- a/lib/drivers/include/fft.h +++ b/lib/drivers/include/fft.h @@ -196,7 +196,7 @@ typedef struct _fft void fft_complex_uint16_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - fft_direction_t direction, const uint64_t* input, size_t point_num, uint64_t* output); + fft_direction_t direction, const uint64_t *input, size_t point_num, uint64_t *output); #ifdef __cplusplus } diff --git a/src/hello_world/main.c b/src/hello_world/main.c index 68b58067..c505db98 100644 --- a/src/hello_world/main.c +++ b/src/hello_world/main.c @@ -15,9 +15,6 @@ #include #include "sleep.h" #include "encoding.h" -float power[512]; -uint64_t fft_out_data[256]; - int main() { uint64_t core_id = current_coreid(); From 3f4721bb8febb66362e55e9ae0171a14ad90dfb2 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Sun, 30 Sep 2018 18:12:37 +0800 Subject: [PATCH 20/58] Moidfy void func --- lib/drivers/include/plic.h | 2 +- lib/drivers/include/spi.h | 2 +- lib/drivers/include/uarths.h | 2 +- lib/drivers/plic.c | 3 +-- lib/drivers/spi.c | 3 +-- lib/drivers/uarths.c | 4 +--- lib/drivers/wdt.c | 16 ++-------------- 7 files changed, 8 insertions(+), 24 deletions(-) diff --git a/lib/drivers/include/plic.h b/lib/drivers/include/plic.h index 6b3b33ec..62a13a8e 100644 --- a/lib/drivers/include/plic.h +++ b/lib/drivers/include/plic.h @@ -367,7 +367,7 @@ typedef int (*plic_irq_callback_t)(void *ctx); * - 0 Success * - Other Fail */ -int plic_init(void); +void plic_init(void); /** * @brief Enable PLIC external interrupt diff --git a/lib/drivers/include/spi.h b/lib/drivers/include/spi.h index c2ab1383..219cc63f 100644 --- a/lib/drivers/include/spi.h +++ b/lib/drivers/include/spi.h @@ -172,7 +172,7 @@ extern volatile spi_t *const spi[4]; * - 0 Success * - Other Fail */ -int spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format, size_t data_bit_length); +void spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format, size_t data_bit_length); /** * @brief Set multiline configuration diff --git a/lib/drivers/include/uarths.h b/lib/drivers/include/uarths.h index 2da75f64..7681613c 100644 --- a/lib/drivers/include/uarths.h +++ b/lib/drivers/include/uarths.h @@ -179,7 +179,7 @@ extern volatile uarths_t *const uarths; * - 0 Success * - Other Fail */ -int uarths_init(void); +void uarths_init(void); /** * @brief Put a char to UART diff --git a/lib/drivers/plic.c b/lib/drivers/plic.c index ae93d139..ca2d6797 100644 --- a/lib/drivers/plic.c +++ b/lib/drivers/plic.c @@ -29,7 +29,7 @@ typedef struct _plic_instance_t static plic_instance_t plic_instance[PLIC_NUM_CORES][IRQN_MAX]; -int plic_init(void) +void plic_init(void) { int i = 0; @@ -72,7 +72,6 @@ int plic_init(void) /* Enable machine external interrupts. */ set_csr(mie, MIP_MEIP); - return 0; } int plic_irq_enable(plic_irq_t irq_number) diff --git a/lib/drivers/spi.c b/lib/drivers/spi.c index 621a28ab..f77c8db5 100644 --- a/lib/drivers/spi.c +++ b/lib/drivers/spi.c @@ -58,7 +58,7 @@ static void spi_set_tmod(uint8_t spi_num, uint32_t tmod) set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset); } -int spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format, size_t data_bit_length) +void spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format, size_t data_bit_length) { configASSERT(data_bit_length >= 4 && data_bit_length <= 32); configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -107,7 +107,6 @@ int spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_fo spi_adapter->ssienr = 0x00; spi_adapter->ctrlr0 = (work_mode << 6) | (frame_format << frf_offset) | ((data_bit_length - 1) << dfs_offset); spi_adapter->spi_ctrlr0 = 0; - return 0; } int spi_config_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length, diff --git a/lib/drivers/uarths.c b/lib/drivers/uarths.c index 034c0efd..8386e86e 100644 --- a/lib/drivers/uarths.c +++ b/lib/drivers/uarths.c @@ -77,7 +77,7 @@ int uarths_puts(const char *s) return 0; } -int uarths_init(void) +void uarths_init(void) { uint32_t freq = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU); uint16_t div = freq / 115200 - 1; @@ -92,6 +92,4 @@ int uarths_init(void) uarths->ip.rxwm = 1; uarths->ie.txwm = 0; uarths->ie.rxwm = 1; - - return 0; } diff --git a/lib/drivers/wdt.c b/lib/drivers/wdt.c index bea86dd8..e811ec57 100644 --- a/lib/drivers/wdt.c +++ b/lib/drivers/wdt.c @@ -18,6 +18,7 @@ #include "utils.h" #include "sysctl.h" #include "plic.h" +#include "math.h" volatile wdt_t *const wdt[2] = { @@ -53,25 +54,12 @@ static uint64_t wdt_get_pclk(wdt_device_number_t id) return id ? sysctl_clock_get_freq(SYSCTL_CLOCK_WDT1) : sysctl_clock_get_freq(SYSCTL_CLOCK_WDT0); } -static uint64_t wdt_log_2(uint64_t x) -{ - int64_t i = 0; - for (i = sizeof(uint64_t) * 8; i >= 0; i--) - { - if ((x >> i) & 0x1) - { - break; - } - } - return i; -} - static uint8_t wdt_get_top(wdt_device_number_t id, uint64_t timeout_ms) { uint64_t wdt_clk = wdt_get_pclk(id); uint64_t ret = (timeout_ms * wdt_clk / 1000) >> 16; if (ret) - ret = wdt_log_2(ret); + ret = (uint32_t)log2(ret); if (ret > 0xf) ret = 0xf; return (uint8_t)ret; From d01376925ef6b260f332cc7a1f15f7f23eb1c05c Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Sun, 30 Sep 2018 20:13:17 +0800 Subject: [PATCH 21/58] Modify lcd for KD233 --- lib/firmware/include/nt35310.h | 2 +- lib/firmware/nt35310.c | 10 +++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/lib/firmware/include/nt35310.h b/lib/firmware/include/nt35310.h index a2fdae5c..c92add77 100644 --- a/lib/firmware/include/nt35310.h +++ b/lib/firmware/include/nt35310.h @@ -95,7 +95,7 @@ #define DIGITAL_GAMMA_CTL2 0xE3 #define INTERFACE_CTL 0xF6 -#define DCX_IO (34) +#define DCX_IO (8) #define RESET_IO (30) #define RESET_GPIONUM (3) #define DCX_GPIONUM (2) diff --git a/lib/firmware/nt35310.c b/lib/firmware/nt35310.c index 09031fda..33dcfcf9 100644 --- a/lib/firmware/nt35310.c +++ b/lib/firmware/nt35310.c @@ -31,15 +31,18 @@ #define _SPI(x, y) __SPI(x, y) #define SPI(x) _SPI(SPI_CHANNEL, x) +#define TEST2_0 + void init_dcx(void) { fpioa_set_function(DCX_IO, FUNC_GPIOHS0 + DCX_GPIONUM);/*dcx*/ gpiohs_set_drive_mode(DCX_GPIONUM, GPIO_DM_OUTPUT); gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_High); - +#ifndef TEST2_0 fpioa_set_function(RESET_IO, FUNC_GPIOHS0 + RESET_GPIONUM);/*reset*/ gpiohs_set_drive_mode(RESET_GPIONUM, GPIO_DM_OUTPUT); gpiohs_set_pin(RESET_GPIONUM, GPIO_PV_High); +#endif } void set_dcx_control(void) @@ -54,8 +57,13 @@ void set_dcx_data(void) void pin_mux_init(void) { +#ifndef TEST2_0 fpioa_set_function(31, SPI_SS); fpioa_set_function(32, SPI(SCLK)); +#else + fpioa_set_function(6, SPI_SS); + fpioa_set_function(7, SPI(SCLK)); +#endif sysctl_spi0_dvp_data_set(1); } From 44455c68b8ec3c9684cd399ce1e216f6e2644947 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Sun, 30 Sep 2018 21:00:50 +0800 Subject: [PATCH 22/58] Add tag 0.3.0 --- CHANGELOG.md | 11 +++++++++++ lib/drivers/include/plic.h | 4 ++-- lib/drivers/plic.c | 7 +++---- 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 11a509ca..edc3887c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -17,3 +17,14 @@ Kendryte K210 first SDK with FreeRTOS, have fun. - Fix spi lcd unwork issues - Fix dual core startup issues - Use "__global_pointer$" instead of "_gp" + +## 0.3.0 + +- Major change + - Modify AES、FFT、SHA、I2C、SPI、WDT、SPI driver +- Breaking changes + - Modify struct enum union format +- Non-breaking bug fixes + - Fix out of memory issues + - Fix lcd unused issues + diff --git a/lib/drivers/include/plic.h b/lib/drivers/include/plic.h index 62a13a8e..1215c68c 100644 --- a/lib/drivers/include/plic.h +++ b/lib/drivers/include/plic.h @@ -442,7 +442,7 @@ int plic_irq_complete(uint32_t source); * - 0 Success * - Other Fail */ -int plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void *ctx); +void plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void *ctx); /** * @brief Deegister user callback function by IRQ number @@ -453,7 +453,7 @@ int plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void *ctx); * - 0 Success * - Other Fail */ -int plic_irq_deregister(plic_irq_t irq); +void plic_irq_deregister(plic_irq_t irq); /* For c++ compatibility */ #ifdef __cplusplus diff --git a/lib/drivers/plic.c b/lib/drivers/plic.c index ca2d6797..70d8f580 100644 --- a/lib/drivers/plic.c +++ b/lib/drivers/plic.c @@ -138,7 +138,7 @@ int plic_irq_complete(uint32_t source) return 0; } -int plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void* ctx) +void plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void* ctx) { /* Read core id */ unsigned long core_id = current_coreid(); @@ -146,13 +146,12 @@ int plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void* ctx) plic_instance[core_id][irq].callback = callback; /* Assign user context */ plic_instance[core_id][irq].ctx = ctx; - return 0; } -int plic_irq_deregister(plic_irq_t irq) +void plic_irq_deregister(plic_irq_t irq) { /* Just assign NULL to user callback function and context */ - return plic_irq_register(irq, NULL, NULL); + plic_irq_register(irq, NULL, NULL); } /*Entry Point for PLIC Interrupt Handler*/ From 046475632fc5618e934fdf92d712899a9d42a3ae Mon Sep 17 00:00:00 2001 From: latyas Date: Mon, 1 Oct 2018 16:38:38 +0800 Subject: [PATCH 23/58] update dvp api signatures --- lib/drivers/dvp.c | 54 ++++++---------- lib/drivers/include/dvp.h | 127 +++++++++++++------------------------- 2 files changed, 64 insertions(+), 117 deletions(-) diff --git a/lib/drivers/dvp.c b/lib/drivers/dvp.c index b54ef08e..7a901ec1 100644 --- a/lib/drivers/dvp.c +++ b/lib/drivers/dvp.c @@ -22,7 +22,7 @@ volatile dvp_t* const dvp = (volatile dvp_t*)DVP_BASE_ADDR; static uint8_t g_sccb_reg_len = 8; -void mdelay(uint32_t ms) +static void mdelay(uint32_t ms) { uint32_t i; @@ -52,7 +52,7 @@ static void dvp_sccb_start_transfer(void) ; } -int dvp_sccb_send_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data) +void dvp_sccb_send_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data) { uint32_t tmp; @@ -64,15 +64,13 @@ int dvp_sccb_send_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data) if (g_sccb_reg_len == 8) { - dvp->sccb_ctl = dvp_sccb_write_data_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr) | DVP_SCCB_WDATA_BYTE0(reg_data); + dvp->sccb_ctl = DVP_SCCB_WRITE_DATA_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr) | DVP_SCCB_WDATA_BYTE0(reg_data); } else { - dvp->sccb_ctl = dvp_sccb_write_data_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr >> 8) | DVP_SCCB_WDATA_BYTE0(reg_addr & 0xff) | DVP_SCCB_WDATA_BYTE1(reg_data); + dvp->sccb_ctl = DVP_SCCB_WRITE_DATA_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr >> 8) | DVP_SCCB_WDATA_BYTE0(reg_addr & 0xff) | DVP_SCCB_WDATA_BYTE1(reg_data); } dvp_sccb_start_transfer(); - - return 0; } uint8_t dvp_sccb_receive_data(uint8_t dev_addr, uint16_t reg_addr) @@ -80,17 +78,21 @@ uint8_t dvp_sccb_receive_data(uint8_t dev_addr, uint16_t reg_addr) uint32_t tmp; tmp = dvp->sccb_cfg & (~DVP_SCCB_BYTE_NUM_MASK); - (g_sccb_reg_len == 8) ? (tmp |= DVP_SCCB_BYTE_NUM_2) : (tmp |= DVP_SCCB_BYTE_NUM_3); + + if (g_sccb_reg_len == 8) + tmp |= DVP_SCCB_BYTE_NUM_2; + else + tmp |= DVP_SCCB_BYTE_NUM_3; dvp->sccb_cfg = tmp; if (g_sccb_reg_len == 8) { - dvp->sccb_ctl = dvp_sccb_write_data_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr); + dvp->sccb_ctl = DVP_SCCB_WRITE_DATA_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr); } else { - dvp->sccb_ctl = dvp_sccb_write_data_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr >> 8) | DVP_SCCB_WDATA_BYTE0(reg_addr & 0xff); + dvp->sccb_ctl = DVP_SCCB_WRITE_DATA_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_addr) | DVP_SCCB_REG_ADDRESS(reg_addr >> 8) | DVP_SCCB_WDATA_BYTE0(reg_addr & 0xff); } dvp_sccb_start_transfer(); @@ -98,7 +100,7 @@ uint8_t dvp_sccb_receive_data(uint8_t dev_addr, uint16_t reg_addr) dvp_sccb_start_transfer(); - return DVP_SCCB_RDATA_BYTE(dvp->sccb_cfg); + return (uint8_t) DVP_SCCB_RDATA_BYTE(dvp->sccb_cfg); } static void dvp_io_init(void) @@ -130,7 +132,7 @@ static void dvp_reset(void) mdelay(200); } -int dvp_init(uint8_t reg_len) +void dvp_init(uint8_t reg_len) { g_sccb_reg_len = reg_len; sysctl_clock_enable(SYSCTL_CLOCK_DVP); @@ -140,18 +142,14 @@ int dvp_init(uint8_t reg_len) dvp_io_init(); dvp_sccb_clk_init(); dvp_reset(); - - return 0; } -int dvp_set_image_format(uint32_t format) +void dvp_set_image_format(uint32_t format) { uint32_t tmp; tmp = dvp->dvp_cfg & (~DVP_CFG_FORMAT_MASK); dvp->dvp_cfg = tmp | format; - - return 0; } void dvp_enable_burst(void) @@ -170,7 +168,7 @@ void dvp_disable_burst(void) dvp->axi |= DVP_AXI_GM_MLEN_1BYTE; } -int dvp_set_image_size(uint32_t width, uint32_t height) +void dvp_set_image_size(uint32_t width, uint32_t height) { uint32_t tmp; @@ -184,33 +182,25 @@ int dvp_set_image_size(uint32_t width, uint32_t height) tmp |= DVP_CFG_HREF_BURST_NUM(width / 8 / 1); dvp->dvp_cfg = tmp; - - return 0; } -int dvp_set_ai_addr(uint32_t r_addr, uint32_t g_addr, uint32_t b_addr) +void dvp_set_ai_addr(uint32_t r_addr, uint32_t g_addr, uint32_t b_addr) { dvp->r_addr = r_addr; dvp->g_addr = g_addr; dvp->b_addr = b_addr; - - return 0; } -int dvp_set_display_addr(uint32_t addr) +void dvp_set_display_addr(uint32_t addr) { dvp->rgb_addr = addr; - - return 0; } -int dvp_start_frame(void) +void dvp_start_frame(void) { while (!(dvp->sts & DVP_STS_FRAME_START)) ; dvp->sts = (DVP_STS_FRAME_START | DVP_STS_FRAME_START_WE); - - return 0; } void dvp_start_convert(void) @@ -218,16 +208,14 @@ void dvp_start_convert(void) dvp->sts = DVP_STS_DVP_EN | DVP_STS_DVP_EN_WE; } -int dvp_finish_convert(void) +void dvp_finish_convert(void) { while (!(dvp->sts & DVP_STS_FRAME_FINISH)) ; dvp->sts = DVP_STS_FRAME_FINISH | DVP_STS_FRAME_FINISH_WE; - - return 0; } -int dvp_get_image(void) +void dvp_get_image(void) { while (!(dvp->sts & DVP_STS_FRAME_START)) ; @@ -237,8 +225,6 @@ int dvp_get_image(void) dvp->sts = DVP_STS_FRAME_FINISH | DVP_STS_FRAME_FINISH_WE | DVP_STS_FRAME_START | DVP_STS_FRAME_START_WE | DVP_STS_DVP_EN | DVP_STS_DVP_EN_WE; while (!(dvp->sts & DVP_STS_FRAME_FINISH)) ; - - return 0; } void dvp_config_interrupt(uint32_t interrupt, uint8_t enable) diff --git a/lib/drivers/include/dvp.h b/lib/drivers/include/dvp.h index e3c43b4d..dd044b8d 100644 --- a/lib/drivers/include/dvp.h +++ b/lib/drivers/include/dvp.h @@ -14,6 +14,7 @@ */ #ifndef _DRIVER_DVP_H #define _DRIVER_DVP_H +#include #ifdef __cplusplus extern "C" { @@ -39,60 +40,60 @@ typedef struct _dvp } __attribute__((packed, aligned(4))) dvp_t; /* DVP Config Register */ -#define DVP_CFG_START_INT_ENABLE 0x00000001 -#define DVP_CFG_FINISH_INT_ENABLE 0x00000002 -#define DVP_CFG_AI_OUTPUT_ENABLE 0x00000004 -#define DVP_CFG_DISPLAY_OUTPUT_ENABLE 0x00000008 -#define DVP_CFG_AUTO_ENABLE 0x00000010 -#define DVP_CFG_BURST_SIZE_4BEATS 0x00000100 -#define DVP_CFG_FORMAT_MASK 0x00000600 -#define DVP_CFG_RGB_FORMAT 0x00000000 -#define DVP_CFG_YUV_FORMAT 0x00000200 -#define DVP_CFG_Y_FORMAT 0x00000600 -#define DVP_CFG_HREF_BURST_NUM_MASK 0x000FF000 +#define DVP_CFG_START_INT_ENABLE 0x00000001U +#define DVP_CFG_FINISH_INT_ENABLE 0x00000002U +#define DVP_CFG_AI_OUTPUT_ENABLE 0x00000004U +#define DVP_CFG_DISPLAY_OUTPUT_ENABLE 0x00000008U +#define DVP_CFG_AUTO_ENABLE 0x00000010U +#define DVP_CFG_BURST_SIZE_4BEATS 0x00000100U +#define DVP_CFG_FORMAT_MASK 0x00000600U +#define DVP_CFG_RGB_FORMAT 0x00000000U +#define DVP_CFG_YUV_FORMAT 0x00000200U +#define DVP_CFG_Y_FORMAT 0x00000600U +#define DVP_CFG_HREF_BURST_NUM_MASK 0x000FF000U #define DVP_CFG_HREF_BURST_NUM(x) ((x) << 12) -#define DVP_CFG_LINE_NUM_MASK 0x3FF00000 +#define DVP_CFG_LINE_NUM_MASK 0x3FF00000U #define DVP_CFG_LINE_NUM(x) ((x) << 20) /* DVP CMOS Config Register */ -#define DVP_CMOS_CLK_DIV_MASK 0x000000FF +#define DVP_CMOS_CLK_DIV_MASK 0x000000FFU #define DVP_CMOS_CLK_DIV(x) ((x) << 0) -#define DVP_CMOS_CLK_ENABLE 0x00000100 -#define DVP_CMOS_RESET 0x00010000 -#define DVP_CMOS_POWER_DOWN 0x01000000 +#define DVP_CMOS_CLK_ENABLE 0x00000100U +#define DVP_CMOS_RESET 0x00010000U +#define DVP_CMOS_POWER_DOWN 0x01000000U /* DVP SCCB Config Register */ -#define DVP_SCCB_BYTE_NUM_MASK 0x00000003 -#define DVP_SCCB_BYTE_NUM_2 0x00000001 -#define DVP_SCCB_BYTE_NUM_3 0x00000002 -#define DVP_SCCB_BYTE_NUM_4 0x00000003 -#define DVP_SCCB_SCL_LCNT_MASK 0x0000FF00 +#define DVP_SCCB_BYTE_NUM_MASK 0x00000003U +#define DVP_SCCB_BYTE_NUM_2 0x00000001U +#define DVP_SCCB_BYTE_NUM_3 0x00000002U +#define DVP_SCCB_BYTE_NUM_4 0x00000003U +#define DVP_SCCB_SCL_LCNT_MASK 0x0000FF00U #define DVP_SCCB_SCL_LCNT(x) ((x) << 8) -#define DVP_SCCB_SCL_HCNT_MASK 0x00FF0000 +#define DVP_SCCB_SCL_HCNT_MASK 0x00FF0000U #define DVP_SCCB_SCL_HCNT(x) ((x) << 16) #define DVP_SCCB_RDATA_BYTE(x) ((x) >> 24) /* DVP SCCB Control Register */ -#define dvp_sccb_write_data_ENABLE 0x00000001 +#define DVP_SCCB_WRITE_DATA_ENABLE 0x00000001U #define DVP_SCCB_DEVICE_ADDRESS(x) ((x) << 0) #define DVP_SCCB_REG_ADDRESS(x) ((x) << 8) #define DVP_SCCB_WDATA_BYTE0(x) ((x) << 16) #define DVP_SCCB_WDATA_BYTE1(x) ((x) << 24) /* DVP AXI Register */ -#define DVP_AXI_GM_MLEN_MASK 0x000000FF -#define DVP_AXI_GM_MLEN_1BYTE 0x00000000 -#define DVP_AXI_GM_MLEN_4BYTE 0x00000003 +#define DVP_AXI_GM_MLEN_MASK 0x000000FFU +#define DVP_AXI_GM_MLEN_1BYTE 0x00000000U +#define DVP_AXI_GM_MLEN_4BYTE 0x00000003U /* DVP STS Register */ -#define DVP_STS_FRAME_START 0x00000001 -#define DVP_STS_FRAME_START_WE 0x00000002 -#define DVP_STS_FRAME_FINISH 0x00000100 -#define DVP_STS_FRAME_FINISH_WE 0x00000200 -#define DVP_STS_DVP_EN 0x00010000 -#define DVP_STS_DVP_EN_WE 0x00020000 -#define DVP_STS_SCCB_EN 0x01000000 -#define DVP_STS_SCCB_EN_WE 0x02000000 +#define DVP_STS_FRAME_START 0x00000001U +#define DVP_STS_FRAME_START_WE 0x00000002U +#define DVP_STS_FRAME_FINISH 0x00000100U +#define DVP_STS_FRAME_FINISH_WE 0x00000200U +#define DVP_STS_DVP_EN 0x00010000U +#define DVP_STS_DVP_EN_WE 0x00020000U +#define DVP_STS_SCCB_EN 0x01000000U +#define DVP_STS_SCCB_EN_WE 0x02000000U /* clang-format on */ typedef enum _dvp_output_mode @@ -108,35 +109,23 @@ extern volatile dvp_t* const dvp; /** * @brief Initialize DVP - * - * @return result - * - 0 Success - * - Other Fail */ -int dvp_init(uint8_t reg_len); +void dvp_init(uint8_t reg_len); /** * @brief Set image format * * @param[in] format The image format - * - * @return result - * - 0 Success - * - Other Fail */ -int dvp_set_image_format(uint32_t format); +void dvp_set_image_format(uint32_t format); /** * @brief Set image size * * @param[in] width The width of image * @param[in] height The height of image - * - * @return result - * - 0 Success - * - Other Fail */ -int dvp_set_image_size(uint32_t width, uint32_t height); +void dvp_set_image_size(uint32_t width, uint32_t height); /** * @brief Set the address of RGB for AI @@ -144,12 +133,8 @@ int dvp_set_image_size(uint32_t width, uint32_t height); * @param[in] r_addr The R address of RGB * @param[in] g_addr The G address of RGB * @param[in] b_addr The B address of RGB - * - * @return result - * - 0 Success - * - Other Fail */ -int dvp_set_ai_addr(uint32_t r_addr, uint32_t g_addr, uint32_t b_addr); +void dvp_set_ai_addr(uint32_t r_addr, uint32_t g_addr, uint32_t b_addr); /** * @brief Set the address of RGB for display @@ -157,50 +142,30 @@ int dvp_set_ai_addr(uint32_t r_addr, uint32_t g_addr, uint32_t b_addr); * @param[in] r_addr The R address of RGB * @param[in] g_addr The G address of RGB * @param[in] b_addr The B address of RGB - * - * @return result - * - 0 Success - * - Other Fail */ -int dvp_set_display_addr(uint32_t addr); +void dvp_set_display_addr(uint32_t addr); /** * @brief The frame start transfer - * - * @return result - * - 0 Success - * - Other Fail */ -int dvp_start_frame(void); +void dvp_start_frame(void); /** * @brief The DVP convert start - * - * @return result - * - 0 Success - * - Other Fail */ void dvp_start_convert(void); /** * @brief The DVP convert finish - * - * @return result - * - 0 Success - * - Other Fail */ -int dvp_finish_convert(void); +void dvp_finish_convert(void); /** * @brief Get the image data * * @note The image data stored in the address of RGB - * - * @return result - * - 0 Success - * - Other Fail */ -int dvp_get_image(void); +void dvp_get_image(void); /** * @brief Use SCCB write register @@ -208,12 +173,8 @@ int dvp_get_image(void); * @param[in] dev_addr The device address * @param[in] reg_addr The register address * @param[in] reg_data The register data - * - * @return result - * - 0 Success - * - Other Fail */ -int dvp_sccb_send_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data); +void dvp_sccb_send_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data); /** * @brief Use SCCB read register From abffe5cfa3286adfb7f25aace70acffbf34352ca Mon Sep 17 00:00:00 2001 From: latyas Date: Mon, 1 Oct 2018 16:38:51 +0800 Subject: [PATCH 24/58] update SHA256 api signatures --- lib/drivers/include/sha256.h | 36 ++++++++++++++++++++++++++++++++++++ lib/drivers/sha256.c | 22 ++++++++++++---------- 2 files changed, 48 insertions(+), 10 deletions(-) diff --git a/lib/drivers/include/sha256.h b/lib/drivers/include/sha256.h index 415c9ee4..e9530893 100644 --- a/lib/drivers/include/sha256.h +++ b/lib/drivers/include/sha256.h @@ -15,6 +15,7 @@ #ifndef _SHA256_H #define _SHA256_H #include +#include #ifdef __cplusplus extern "C" { @@ -49,6 +50,41 @@ typedef struct _sha256_context } buffer; } sha256_context_t; +/** + * @brief Init SHA256 calculation context + * + * @param[in] context SHA256 context object + * + */ +void sha256_init(sha256_context_t *context); + +/** + * @brief Called repeatedly with chunks of the message to be hashed + * + * @param[in] context SHA256 context object + * @param[in] data_buf data chunk to be hashed + * @param[in] buf_len length of data chunk + * + */ +void sha256_update(sha256_context_t *context, const void *data_buf, size_t buf_len); + +/** + * @brief Finish SHA256 hash process, output the result. + * + * @param[in] context SHA256 context object + * @param[out] output The buffer where SHA256 hash will be output + * + */ +void sha256_final(sha256_context_t *context, uint8_t *output); + +/** + * @brief Simple SHA256 hash once. + * + * @param[in] data Data will be hashed + * @param[in] data_len Data length + * @param[out] output Output buffer + * + */ void sha256_hard_calculate(const uint8_t *data, size_t data_len, uint8_t *output); #ifdef __cplusplus diff --git a/lib/drivers/sha256.c b/lib/drivers/sha256.c index 9a33ae97..76cee41b 100644 --- a/lib/drivers/sha256.c +++ b/lib/drivers/sha256.c @@ -13,8 +13,9 @@ * limitations under the License. */ #include -#include -#include +#include "sysctl.h" +#include "sha256.h" +#include "utils.h" #define ROTL(x, n) (((x) << (n)) | ((x) >> (32 - (n)))) #define ROTR(x, n) (((x) >> (n)) | ((x) << (32 - (n)))) @@ -36,32 +37,33 @@ static const uint8_t padding[64] = static inline uint64_t byteswap64(uint64_t x) { - uint32_t a = x >> 32; + uint32_t a = (uint32_t)(x >> 32); uint32_t b = (uint32_t)x; return ((uint64_t)BYTESWAP(b) << 32) | (uint64_t)BYTESWAP(a); } -static void sha256_init(sha256_context_t *context, size_t buf_len) +void sha256_init(sha256_context_t *context) { - size_t padding_len = 0; sysctl_clock_enable(SYSCTL_CLOCK_SHA); sysctl_reset(SYSCTL_RESET_SHA); - padding_len = (buf_len + SHA256_BLOCK_LEN + 8) / SHA256_BLOCK_LEN; sha256->sha_input_ctrl &= (~0x1); - sha256->sha_data_num = padding_len; sha256->sha_status |= SHA256_BIG_ENDIAN; sha256->sha_status |= ENABLE_SHA; context->total_length = 0LL; context->buffer_length = 0L; } -static void sha256_update(sha256_context_t *context, const void *data_buf, size_t buf_len) +void sha256_update(sha256_context_t *context, const void *data_buf, size_t buf_len) { + configASSERT(buf_len <= UINT32_MAX); + const uint8_t* data = data_buf; size_t buffer_bytes_left; size_t bytes_to_copy; uint32_t i; + sha256->sha_data_num = (uint32_t)((buf_len + SHA256_BLOCK_LEN + 8) / SHA256_BLOCK_LEN); + while (buf_len) { buffer_bytes_left = SHA256_BLOCK_LEN - context->buffer_length; @@ -86,7 +88,7 @@ static void sha256_update(sha256_context_t *context, const void *data_buf, size_ } } -static void sha256_final(sha256_context_t *context, uint8_t *output) +void sha256_final(sha256_context_t *context, uint8_t *output) { size_t bytes_to_pad; size_t length_pad; @@ -113,7 +115,7 @@ static void sha256_final(sha256_context_t *context, uint8_t *output) void sha256_hard_calculate(const uint8_t *data, size_t data_len, uint8_t *output) { sha256_context_t sha; - sha256_init(&sha, data_len); + sha256_init(&sha); sha256_update(&sha, data, data_len); sha256_final(&sha, output); } From a3c8e5e19e26b6234bbdecec6bbd8d73cb27b555 Mon Sep 17 00:00:00 2001 From: latyas Date: Mon, 1 Oct 2018 20:24:37 +0800 Subject: [PATCH 25/58] update wdt api signatures --- lib/drivers/wdt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/lib/drivers/wdt.c b/lib/drivers/wdt.c index e811ec57..b99edd3f 100644 --- a/lib/drivers/wdt.c +++ b/lib/drivers/wdt.c @@ -75,7 +75,7 @@ void wdt_clear_interrupt(wdt_device_number_t id) wdt[id]->eoi = wdt[id]->eoi; } -int wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t on_irq) +void wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t on_irq) { wdt_disable(id); wdt_clear_interrupt(id); @@ -90,7 +90,6 @@ int wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t uint8_t m_top = wdt_get_top(id, time_out_ms); wdt_set_timeout(id, m_top); wdt_enable(id); - return 0; } void wdt_stop(wdt_device_number_t id) From 2a5b305838ee1f7b18ad361080112f5fe4395d7c Mon Sep 17 00:00:00 2001 From: latyas Date: Mon, 1 Oct 2018 20:28:50 +0800 Subject: [PATCH 26/58] update wdt api signatures --- lib/drivers/include/wdt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/drivers/include/wdt.h b/lib/drivers/include/wdt.h index 37f4623e..6ba580ee 100644 --- a/lib/drivers/include/wdt.h +++ b/lib/drivers/include/wdt.h @@ -131,7 +131,7 @@ void wdt_feed(wdt_device_number_t id); * @param[in] time_out_ms Wdt trigger time * */ -int wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t on_irq); +void wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t on_irq); /** * @brief Stop wdt From 5c88de27f2b97bc4d80a0154494452d380eb90c8 Mon Sep 17 00:00:00 2001 From: latyas Date: Mon, 1 Oct 2018 20:29:16 +0800 Subject: [PATCH 27/58] update dmac api signatures --- lib/drivers/dmac.c | 22 +++++++++++----------- lib/drivers/include/dmac.h | 11 ++++++----- 2 files changed, 17 insertions(+), 16 deletions(-) diff --git a/lib/drivers/dmac.c b/lib/drivers/dmac.c index 46c9dcb3..c446049a 100644 --- a/lib/drivers/dmac.c +++ b/lib/drivers/dmac.c @@ -354,7 +354,7 @@ static int dmac_set_channel_param(dmac_channel_number_t channel_num, flow_control = DMAC_MEM2PRF_DMA; else if (mem_type_src == 0 && mem_type_dest == 1) flow_control = DMAC_PRF2MEM_DMA; - else if (mem_type_src == 1 && mem_type_dest == 1) + else flow_control = DMAC_MEM2MEM_DMA; /** @@ -583,7 +583,7 @@ void dmac_init(void) /* disable all channel before configure */ } -void list_add(struct list_head_t *new, struct list_head_t *prev, +static void list_add(struct list_head_t *new, struct list_head_t *prev, struct list_head_t *next) { next->prev = new; @@ -592,12 +592,12 @@ void list_add(struct list_head_t *new, struct list_head_t *prev, prev->next = new; } -void list_add_tail(struct list_head_t *new, struct list_head_t *head) +static void list_add_tail(struct list_head_t *new, struct list_head_t *head) { list_add(new, head->prev, head); } -void INIT_LIST_HEAD(struct list_head_t *list) +static void INIT_LIST_HEAD(struct list_head_t *list) { list->next = list; list->prev = list; @@ -697,14 +697,14 @@ void dmac_set_shadow_invalid_flag(dmac_channel_number_t channel_num) } void dmac_set_single_mode(dmac_channel_number_t channel_num, - const void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, - dmac_burst_trans_length_t dmac_burst_size, - dmac_transfer_width_t dmac_trans_width, - uint32_t blockSize) -{ + const void *src, void *dest, dmac_address_increment_t src_inc, + dmac_address_increment_t dest_inc, + dmac_burst_trans_length_t dmac_burst_size, + dmac_transfer_width_t dmac_trans_width, + size_t block_size) { dmac_channel_disable(channel_num); - dmac_set_channel_param(channel_num, src, dest, src_inc,dest_inc, - dmac_burst_size,dmac_trans_width,blockSize); + dmac_set_channel_param(channel_num, src, dest, src_inc, dest_inc, + dmac_burst_size, dmac_trans_width, block_size); dmac_enable(); dmac_chanel_interrupt_clear(channel_num); /* clear interrupt */ dmac_enable_channel_interrupt_status(channel_num); diff --git a/lib/drivers/include/dmac.h b/lib/drivers/include/dmac.h index 76cd8b83..e54171c1 100644 --- a/lib/drivers/include/dmac.h +++ b/lib/drivers/include/dmac.h @@ -1414,14 +1414,15 @@ void dmac_init(void); * @param[in] dest_inc Dest address increase or not * @param[in] dmac_burst_size Dmac burst length * @param[in] dmac_trans_width Dmac transfer data width - * @param[in] blockSize Dmac transfer length + * @param[in] block_size Dmac transfer length * */ void dmac_set_single_mode(dmac_channel_number_t channel_num, - const void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc, - dmac_burst_trans_length_t dmac_burst_size, - dmac_transfer_width_t dmac_trans_width, - uint32_t blockSize); + const void *src, void *dest, dmac_address_increment_t src_inc, + dmac_address_increment_t dest_inc, + dmac_burst_trans_length_t dmac_burst_size, + dmac_transfer_width_t dmac_trans_width, + size_t block_size); /** * @brief Wait for dmac work done From 5276a8616df321aee2647b3c01f4553a9ca99b3c Mon Sep 17 00:00:00 2001 From: latyas Date: Mon, 1 Oct 2018 20:29:33 +0800 Subject: [PATCH 28/58] update i2s api signatures --- lib/drivers/i2s.c | 57 +++++++++++++++++++-------------------- lib/drivers/include/i2s.h | 19 ++++++++++++- 2 files changed, 45 insertions(+), 31 deletions(-) diff --git a/lib/drivers/i2s.c b/lib/drivers/i2s.c index bd7702ba..1303bb0f 100644 --- a/lib/drivers/i2s.c +++ b/lib/drivers/i2s.c @@ -17,6 +17,7 @@ #include "i2s.h" #include "sysctl.h" #include "stdlib.h" +#include "utils.h" volatile i2s_t *const i2s[3] = { @@ -142,21 +143,19 @@ int i2s_set_tx_word_length(i2s_device_number_t device_num, return 0; } -int i2s_master_configure(i2s_device_number_t device_num, - i2s_word_select_cycles_t word_select_size, - i2s_sclk_gating_cycles_t gating_cycles, - i2s_work_mode_t word_mode) +static void i2s_master_configure(i2s_device_number_t device_num, + i2s_word_select_cycles_t word_select_size, + i2s_sclk_gating_cycles_t gating_cycles, + i2s_work_mode_t word_mode) { + configASSERT(!(word_select_size < SCLK_CYCLES_16 || + word_select_size > SCLK_CYCLES_32)); + configASSERT(!(gating_cycles < NO_CLOCK_GATING || + gating_cycles > CLOCK_CYCLES_24)); + ccr_t u_ccr; cer_t u_cer; - if (word_select_size < SCLK_CYCLES_16 || - word_select_size > SCLK_CYCLES_32) - return -1; - if (gating_cycles < NO_CLOCK_GATING || - gating_cycles > CLOCK_CYCLES_24) - return -1; - u_ccr.reg_data = readl(&i2s[device_num]->ccr); u_ccr.ccr.clk_word_size = word_select_size; u_ccr.ccr.clk_gate = gating_cycles; @@ -168,10 +167,9 @@ int i2s_master_configure(i2s_device_number_t device_num, writel(u_cer.reg_data, &i2s[device_num]->cer); /* Clock generation enable */ - return 0; } -int i2s_set_rx_threshold(i2s_device_number_t device_num, +static int i2s_set_rx_threshold(i2s_device_number_t device_num, i2s_fifo_threshold_t threshold, i2s_channel_num_t channel_num) { @@ -301,18 +299,17 @@ int i2s_receive_data(i2s_device_number_t device_num, i2s_channel_num_t channel_n return 0; } -int i2s_receive_data_dma(i2s_device_number_t device_num, uint32_t *buf, - size_t buf_len, dmac_channel_number_t channel_num) +void i2s_receive_data_dma(i2s_device_number_t device_num, uint32_t *buf, + size_t buf_len, dmac_channel_number_t channel_num) { static uint8_t dmac_recv_flag[6] = {0,0,0,0,0,0}; if(dmac_recv_flag[channel_num]) dmac_wait_done(channel_num); else dmac_recv_flag[channel_num] = 1; - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_I2S0_RX_REQ + device_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)channel_num, SYSCTL_DMA_SELECT_I2S0_RX_REQ + device_num * 2); dmac_set_single_mode(channel_num, (void *)(&i2s[device_num]->rxdma), buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, buf_len); - return 0; } int i2s_rx_to_tx(i2s_device_number_t device_src_num, i2s_device_number_t device_dest_num, @@ -323,13 +320,14 @@ int i2s_rx_to_tx(i2s_device_number_t device_src_num, i2s_device_number_t device_ dmac_wait_done(channel_num); else dmac_recv_flag[channel_num] = 1; - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_I2S0_RX_REQ + device_src_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)channel_num, SYSCTL_DMA_SELECT_I2S0_RX_REQ + device_src_num * 2); dmac_set_single_mode(channel_num, (void *)(&i2s[device_src_num]->rxdma), (void *)(&i2s[device_dest_num]->txdma), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, buf_len); return 0; } -int i2s_send_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint8_t *pcm, size_t buf_len, size_t single_length) +int i2s_send_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, const uint8_t *pcm, size_t buf_len, + size_t single_length) { isr_t u_isr; uint32_t left_buffer = 0; @@ -388,13 +386,13 @@ void i2s_send_data_dma(i2s_device_number_t device_num, const void *buf, size_t b dmac_wait_done(channel_num); else dmac_init_flag[channel_num] = 1; - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_I2S0_TX_REQ + device_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)channel_num, SYSCTL_DMA_SELECT_I2S0_TX_REQ + device_num * 2); dmac_set_single_mode(channel_num, buf, (void *)(&i2s[device_num]->txdma), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, buf_len); } -void i2s_parse_voice(uint32_t *buf, uint8_t *pcm, uint32_t length, uint32_t bits_per_sample, - uint8_t track_num, uint32_t *send_len) +void i2s_parse_voice(uint32_t *buf, const uint8_t *pcm, size_t length, size_t bits_per_sample, + uint8_t track_num, size_t *send_len) { uint32_t i,j=0; *send_len = length * 2; @@ -437,14 +435,14 @@ void i2s_parse_voice(uint32_t *buf, uint8_t *pcm, uint32_t length, uint32_t bit } -int i2s_play(i2s_device_number_t device_num,dmac_channel_number_t channel_num, - uint8_t *buf, size_t buf_len, size_t frame, size_t bits_per_sample, uint8_t track_num) +void i2s_play(i2s_device_number_t device_num, dmac_channel_number_t channel_num, + const uint8_t *buf, size_t buf_len, size_t frame, size_t bits_per_sample, uint8_t track_num) { - uint32_t sample_cnt = buf_len / ( bits_per_sample / 8 ) / track_num; - uint32_t frame_cnt = sample_cnt / frame; - uint32_t frame_remain = sample_cnt % frame; + const uint8_t *trans_buf; uint32_t i; - uint8_t *trans_buf; + size_t sample_cnt = buf_len / ( bits_per_sample / 8 ) / track_num; + size_t frame_cnt = sample_cnt / frame; + size_t frame_remain = sample_cnt % frame; if (bits_per_sample == 16 && track_num == 2) { @@ -478,7 +476,7 @@ int i2s_play(i2s_device_number_t device_num,dmac_channel_number_t channel_num, buff[0] = malloc(frame * 2 * sizeof(uint32_t) * 2); buff[1] = buff[0] + frame * 2; uint8_t flag = 0; - uint32_t send_len = 0; + size_t send_len = 0; for (i = 0; i < frame_cnt; i++) { trans_buf = buf + i * frame * (bits_per_sample / 8) * track_num; @@ -494,7 +492,6 @@ int i2s_play(i2s_device_number_t device_num,dmac_channel_number_t channel_num, } free(buff[0]); } - return 0; } void i2s_rx_channel_config(i2s_device_number_t device_num, diff --git a/lib/drivers/include/i2s.h b/lib/drivers/include/i2s.h index 269451db..a6e96559 100644 --- a/lib/drivers/include/i2s.h +++ b/lib/drivers/include/i2s.h @@ -16,6 +16,7 @@ #define _DRIVER_I2S_H #include +#include #include "platform.h" #include "io.h" #include "dmac.h" @@ -650,7 +651,8 @@ void i2s_init(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode, uint32_t * - 0 Success * - Other Fail */ -int i2s_receive_data_dma(i2s_device_number_t device_num, uint32_t *buf, size_t buf_len, dmac_channel_number_t channel_num); +void i2s_receive_data_dma(i2s_device_number_t device_num, uint32_t *buf, size_t buf_len, + dmac_channel_number_t channel_num); /** * @brief Write pcm data to channel_num channel by dma, first wait dmac done @@ -695,6 +697,21 @@ void i2s_tx_channel_config(i2s_device_number_t device_num, i2s_fifo_threshold_t trigger_level, i2s_work_mode_t word_mode); + +/** + * @brief Play PCM format audio + * + * @param[in] device_num The device number + * @param[in] channel_num The channel number + * @param[in] buf PCM data + * @param[in] buf_len PCM data length + * @param[in] frame Transmit amount once + * @param[in] bits_per_sample Sample bit length + * @param[in] track_num Track amount + */ +void i2s_play(i2s_device_number_t device_num, dmac_channel_number_t channel_num, + const uint8_t *buf, size_t buf_len, size_t frame, size_t bits_per_sample, uint8_t track_num); + #ifdef __cplusplus } #endif From acc3b060c51269da7977725c9ec4ef132c23a516 Mon Sep 17 00:00:00 2001 From: latyas Date: Tue, 2 Oct 2018 16:06:10 +0800 Subject: [PATCH 29/58] update spi signature --- lib/drivers/include/spi.h | 44 ++++++++----- lib/drivers/spi.c | 129 +++++++++++++++++++++----------------- 2 files changed, 98 insertions(+), 75 deletions(-) diff --git a/lib/drivers/include/spi.h b/lib/drivers/include/spi.h index 219cc63f..78c788a7 100644 --- a/lib/drivers/include/spi.h +++ b/lib/drivers/include/spi.h @@ -184,8 +184,8 @@ void spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_f * @param[in] instruction_address_trans_mode Spi transfer mode * */ -int spi_config_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length, - uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode); +void spi_config_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length, + uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode); /** * @brief Spi send data @@ -201,7 +201,8 @@ int spi_config_non_standard(spi_device_num_t spi_num, uint32_t instruction_lengt * - 0 Success * - Other Fail */ -int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len); +void spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, + size_t cmd_len, const uint8_t *tx_buff, size_t tx_len); /** * @brief Spi receive data @@ -217,7 +218,8 @@ int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_sele * - 0 Success * - Other Fail */ -int spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +void spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, + size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special receive data @@ -233,7 +235,8 @@ int spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_s * - 0 Success * - Other Fail */ -int spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +void spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, + size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special send data @@ -249,7 +252,8 @@ int spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_s * - 0 Success * - Other Fail */ -int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len); +void spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, + size_t cmd_len, const uint8_t *tx_buff, size_t tx_len); /** * @brief Spi send data by dma @@ -266,8 +270,9 @@ int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_sele * - 0 Success * - Other Fail */ -int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, - const uint8_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len); +void spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, + spi_chip_select_t chip_select, + const uint8_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len); /** * @brief Spi receive data by dma @@ -285,8 +290,10 @@ int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num * - 0 Success * - Other Fail */ -int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +void spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, + dmac_channel_number_t dma_receive_channel_num, + spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, + size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi special send data by dma @@ -303,7 +310,8 @@ int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dm * - 0 Success * - Other Fail */ -int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, spi_chip_select_t chip_select, +void spi_send_data_multiple_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, + spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len); /** @@ -322,8 +330,10 @@ int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_ * - 0 Success * - Other Fail */ -int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len); +void spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, + dmac_channel_number_t dma_receive_channel_num, + spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, + size_t cmd_len, uint8_t *rx_buff, size_t rx_len); /** * @brief Spi fill dma @@ -338,7 +348,8 @@ int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dm * - 0 Success * - Other Fail */ -int spi_fill_data_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *tx_buff, size_t tx_len); +void spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, + const uint32_t *tx_buff, size_t tx_len); /** * @brief Spi normal send by dma @@ -354,8 +365,9 @@ int spi_fill_data_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num * - 0 Success * - Other Fail */ -int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, - const void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width); +void spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, + spi_chip_select_t chip_select, + const void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width); /** * @brief Spi normal send by dma diff --git a/lib/drivers/spi.c b/lib/drivers/spi.c index f77c8db5..f4f8381a 100644 --- a/lib/drivers/spi.c +++ b/lib/drivers/spi.c @@ -109,14 +109,14 @@ void spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_f spi_adapter->spi_ctrlr0 = 0; } -int spi_config_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length, - uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode) +void spi_config_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length, + uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode) { configASSERT(wait_cycles < (1 << 5)); configASSERT(instruction_address_trans_mode < 3); configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); volatile spi_t *spi_handle = spi[spi_num]; - uint32_t inst_l; + uint32_t inst_l = 0; switch (instruction_length) { case 0: @@ -140,7 +140,6 @@ int spi_config_non_standard(spi_device_num_t spi_num, uint32_t instruction_lengt uint32_t addr_l = address_length / 4; spi_handle->spi_ctrlr0 = (wait_cycles << 11) | (inst_l << 8) | (addr_l << 2) | instruction_address_trans_mode; - return 0; } uint32_t spi_set_clk_rate(spi_device_num_t spi_num, uint32_t spi_clk) @@ -159,10 +158,12 @@ uint32_t spi_set_clk_rate(spi_device_num_t spi_num, uint32_t spi_clk) return sysctl_clock_get_freq(SYSCTL_CLOCK_SPI0 + spi_num) / spi_baudr; } -int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len) +void spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, + size_t cmd_len, const uint8_t *tx_buff, size_t tx_len) { - uint32_t index, fifo_len; configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + + size_t index, fifo_len; spi_set_tmod(spi_num, SPI_TMOD_TRANS); volatile spi_t *spi_handle = spi[spi_num]; spi_handle->ssienr = 0x01; @@ -176,7 +177,7 @@ int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_sele for (index = 0; index < fifo_len; index++) spi_handle->dr[0] = *tx_buff++; tx_len -= fifo_len; - spi_handle->ser = 1 << chip_select; + spi_handle->ser = 1U << chip_select; while (tx_len) { fifo_len = 32 - spi_handle->txflr; @@ -189,17 +190,19 @@ int spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_sele ; spi_handle->ser = 0x00; spi_handle->ssienr = 0x00; - return 0; } -int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, - const uint8_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len) +void spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, + spi_chip_select_t chip_select, + const uint8_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_TRANS); volatile spi_t *spi_handle = spi[spi_num]; uint32_t *buf = malloc((cmd_len + tx_len) * sizeof(uint32_t)); int i; + for(i = 0; i < cmd_len; i++) { buf[i] = cmd_buff[i]; @@ -212,10 +215,10 @@ int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num spi_handle->dmacr = 0x2; /*enable dma transmit*/ spi_handle->ssienr = 0x01; - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); dmac_set_single_mode(channel_num, buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len + tx_len); - spi_handle->ser = 1 << chip_select; + spi_handle->ser = 1U << chip_select; dmac_wait_done(channel_num); free((void*)buf); @@ -223,11 +226,11 @@ int spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num ; spi_handle->ser = 0x00; spi_handle->ssienr = 0x00; - return 0; } -int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, - const void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width) +void spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, + spi_chip_select_t chip_select, + const void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); spi_set_tmod(spi_num, SPI_TMOD_TRANS); @@ -254,10 +257,10 @@ int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_handle->dmacr = 0x2; /*enable dma transmit*/ spi_handle->ssienr = 0x01; - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); + sysctl_dma_select((sysctl_dma_channel_t) channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); dmac_set_single_mode(channel_num, buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, tx_len); - spi_handle->ser = 1 << chip_select; + spi_handle->ser = 1U << chip_select; dmac_wait_done(channel_num); free((void*)buf); @@ -265,51 +268,55 @@ int spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t ; spi_handle->ser = 0x00; spi_handle->ssienr = 0x00; - return 0; } -int spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +void spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, + size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { - uint32_t index, fifo_len; configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + + size_t index, fifo_len; spi_set_tmod(spi_num, SPI_TMOD_EEROM); volatile spi_t *spi_handle = spi[spi_num]; - spi_handle->ctrlr1 = rx_len - 1; + spi_handle->ctrlr1 = (uint32_t)(rx_len - 1); spi_handle->ssienr = 0x01; while (cmd_len--) spi_handle->dr[0] = *cmd_buff++; - spi_handle->ser = 1 << chip_select; + spi_handle->ser = 1U << chip_select; while (rx_len) { fifo_len = spi_handle->rxflr; fifo_len = fifo_len < rx_len ? fifo_len : rx_len; for (index = 0; index < fifo_len; index++) - *rx_buff++ = spi_handle->dr[0]; + *rx_buff++ = (uint8_t)spi_handle->dr[0]; rx_len -= fifo_len; } spi_handle->ser = 0x00; spi_handle->ssienr = 0x00; - return 0; } -int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +void spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, + dmac_channel_number_t dma_receive_channel_num, + spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff, + size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); spi_set_tmod(spi_num, SPI_TMOD_EEROM); volatile spi_t *spi_handle = spi[spi_num]; - uint32_t * write_cmd = malloc(sizeof(uint32_t) * (cmd_len + rx_len)); size_t i; + + uint32_t *write_cmd = malloc(sizeof(uint32_t) * (cmd_len + rx_len)); + for (i = 0; i < cmd_len; i++) write_cmd[i] = cmd_buff[i]; - spi_handle->ctrlr1 = rx_len - 1; + spi_handle->ctrlr1 = (uint32_t)(rx_len - 1); spi_handle->dmacr = 0x3; spi_handle->ssienr = 0x01; - spi_handle->ser = 1 << chip_select; + spi_handle->ser = 1U << chip_select; - sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); - sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)dma_send_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)dma_receive_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2); dmac_set_single_mode(dma_receive_channel_num, (void *)(&spi_handle->dr[0]), write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len); @@ -321,43 +328,46 @@ int spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num, dm dmac_wait_done(dma_receive_channel_num); for(i = 0; i < rx_len; i++){ - rx_buff[i] = write_cmd[i]; + rx_buff[i] = (uint8_t)write_cmd[i]; } free(write_cmd); spi_handle->ser = 0x00; spi_handle->ssienr = 0x00; - return 0; } -int spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +void spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, + size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { - uint32_t index, fifo_len; configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + + size_t index, fifo_len; spi_set_tmod(spi_num, SPI_TMOD_RECV); volatile spi_t *spi_handle = spi[spi_num]; - spi_handle->ctrlr1 = rx_len - 1; + spi_handle->ctrlr1 = (uint32_t)(rx_len - 1); spi_handle->ssienr = 0x01; while (cmd_len--) spi_handle->dr[0] = *cmd_buff++; - spi_handle->ser = 1 << chip_select; + spi_handle->ser = 1U << chip_select; while (rx_len) { fifo_len = spi_handle->rxflr; fifo_len = fifo_len < rx_len ? fifo_len : rx_len; for (index = 0; index < fifo_len; index++) - *rx_buff++ = spi_handle->dr[0]; + *rx_buff++ = (uint8_t)spi_handle->dr[0]; rx_len -= fifo_len; } spi_handle->ser = 0x00; spi_handle->ssienr = 0x00; - return 0; } -int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, uint8_t *rx_buff, size_t rx_len) +void spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, + dmac_channel_number_t dma_receive_channel_num, + spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, + size_t cmd_len, uint8_t *rx_buff, size_t rx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_RECV); volatile spi_t *spi_handle = spi[spi_num]; uint32_t * write_cmd = malloc(sizeof(uint32_t) * (cmd_len + rx_len)); @@ -365,13 +375,13 @@ int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dm for (i = 0; i < cmd_len; i++) write_cmd[i] = cmd_buff[i]; - spi_handle->ctrlr1 = rx_len - 1; + spi_handle->ctrlr1 = (uint32_t)(rx_len - 1); spi_handle->dmacr = 0x3; spi_handle->ssienr = 0x01; - spi_handle->ser = 1 << chip_select; + spi_handle->ser = 1U << chip_select; - sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); - sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)dma_send_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)dma_receive_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2); dmac_set_single_mode(dma_receive_channel_num, (void *)(&spi_handle->dr[0]), write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len); @@ -384,18 +394,19 @@ int spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num, dm for(i = 0; i < rx_len; i++) { - rx_buff[i] = write_cmd[i]; + rx_buff[i] = (uint8_t)write_cmd[i]; } free(write_cmd); spi_handle->ser = 0x00; spi_handle->ssienr = 0x00; - return 0; } -int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len) +void spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff, + size_t cmd_len, const uint8_t *tx_buff, size_t tx_len) { - uint32_t index, fifo_len; configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + + size_t index, fifo_len; spi_set_tmod(spi_num, SPI_TMOD_TRANS); volatile spi_t *spi_handle = spi[spi_num]; spi_handle->ssienr = 0x01; @@ -406,7 +417,7 @@ int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_sele for (index = 0; index < fifo_len; index++) spi_handle->dr[0] = *tx_buff++; tx_len -= fifo_len; - spi_handle->ser = 1 << chip_select; + spi_handle->ser = 1U << chip_select; while (tx_len) { fifo_len = 32 - spi_handle->txflr; @@ -419,10 +430,10 @@ int spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_sele ; spi_handle->ser = 0x00; spi_handle->ssienr = 0x00; - return 0; } -int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_t spi_num, spi_chip_select_t chip_select, +void spi_send_data_multiple_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, + spi_chip_select_t chip_select, const uint32_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -442,10 +453,10 @@ int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_ spi_handle->dmacr = 0x2; /*enable dma transmit*/ spi_handle->ssienr = 0x01; - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); dmac_set_single_mode(channel_num, buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len + tx_len); - spi_handle->ser = 1 << chip_select; + spi_handle->ser = 1U << chip_select; dmac_wait_done(channel_num); free((void*)buf); @@ -453,27 +464,27 @@ int spi_send_data_multiple_dma(dmac_channel_number_t channel_num,spi_device_num_ ; spi_handle->ser = 0x00; spi_handle->ssienr = 0x00; - return 0; } -int spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *tx_buff, size_t tx_len) +void spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select, + const uint32_t *tx_buff, size_t tx_len) { configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); + spi_set_tmod(spi_num, SPI_TMOD_TRANS); volatile spi_t *spi_handle = spi[spi_num]; spi_handle->dmacr = 0x2; /*enable dma transmit*/ spi_handle->ssienr = 0x01; - sysctl_dma_select(channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2); dmac_set_single_mode(channel_num, tx_buff, (void *)(&spi_handle->dr[0]), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, tx_len); - spi_handle->ser = 1 << chip_select; + spi_handle->ser = 1U << chip_select; dmac_wait_done(channel_num); while ((spi_handle->sr & 0x05) != 0x04) ; spi_handle->ser = 0x00; spi_handle->ssienr = 0x00; - return 0; } From 797b7b472769f10d370a2fc1269e31367bc8b891 Mon Sep 17 00:00:00 2001 From: latyas Date: Tue, 2 Oct 2018 16:06:50 +0800 Subject: [PATCH 30/58] update rtc function signature --- lib/drivers/rtc.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/lib/drivers/rtc.c b/lib/drivers/rtc.c index ec407485..68097a16 100644 --- a/lib/drivers/rtc.c +++ b/lib/drivers/rtc.c @@ -23,7 +23,7 @@ volatile rtc_t *const rtc = (volatile rtc_t *)RTC_BASE_ADDR; struct tm rtc_date_time; -int rtc_timer_set_mode(rtc_timer_mode_t timer_mode) +void rtc_timer_set_mode(rtc_timer_mode_t timer_mode) { rtc_register_ctrl_t register_ctrl = rtc->register_ctrl; @@ -47,7 +47,6 @@ int rtc_timer_set_mode(rtc_timer_mode_t timer_mode) break; } rtc->register_ctrl = register_ctrl; - return 0; } rtc_timer_mode_t rtc_timer_get_mode(void) @@ -251,12 +250,12 @@ int rtc_timer_set_alarm_tm(const struct tm *tm) return 0; } -int rtc_year_is_leap(int year) +static int rtc_year_is_leap(int year) { return (year % 4 == 0 && year % 100 != 0) || (year % 400 == 0); } -int rtc_get_yday(int year, int month, int day) +static int rtc_get_yday(int year, int month, int day) { static const int days[2][13] = { @@ -268,7 +267,7 @@ int rtc_get_yday(int year, int month, int day) return days[leap][month] + day; } -int rtc_get_wday(int year, int month, int day) +static int rtc_get_wday(int year, int month, int day) { /* Magic method to get weekday */ int weekday = (day += month < 3 ? year-- : year - 2, 23 * month / 9 + day + 4 + year / 4 - year / 100 + year / 400) % 7; From 158af849c3a98d49ad4401a076046758b60ec4e8 Mon Sep 17 00:00:00 2001 From: latyas Date: Tue, 2 Oct 2018 18:32:50 +0800 Subject: [PATCH 31/58] change spi and i2c signature --- lib/drivers/i2c.c | 47 +++++++++++++++++------------- lib/drivers/include/i2c.h | 14 +++++---- lib/drivers/include/spi.h | 7 +++-- lib/drivers/spi.c | 7 +++-- lib/firmware/nt35310.c | 27 +++++++++++------- lib/firmware/sd3068.c | 4 +-- lib/firmware/w25qxx.c | 60 +++++++++++++++++++++++---------------- 7 files changed, 97 insertions(+), 69 deletions(-) diff --git a/lib/drivers/i2c.c b/lib/drivers/i2c.c index 5c719a49..fe3074bd 100644 --- a/lib/drivers/i2c.c +++ b/lib/drivers/i2c.c @@ -35,22 +35,25 @@ static void i2c_clk_init(i2c_device_number_t i2c_num) sysctl_clock_set_threshold(SYSCTL_THRESHOLD_I2C0 + i2c_num, 3); } -void i2c_config(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode) +void i2c_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width, + i2c_bus_speed_mode_t bus_speed_mode) { configASSERT(i2c_num < I2C_MAX_NUM); configASSERT(address_width == 7 || address_width == 10); - i2c_clk_init(i2c_num); + + volatile i2c_t *i2c_adapter = i2c[i2c_num]; int speed_mode = 1; - switch (bus_speed_mode) - { + + i2c_clk_init(i2c_num); + + switch (bus_speed_mode) { case I2C_BS_STANDARD: speed_mode = 1; break; default: break; } - /*set config*/ - volatile i2c_t* i2c_adapter = i2c[i2c_num]; + i2c_adapter->enable = 0; i2c_adapter->con = I2C_CON_MASTER_MODE | I2C_CON_SLAVE_DISABLE | I2C_CON_RESTART_EN | (address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(speed_mode); @@ -68,7 +71,7 @@ int i2c_send_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t s { configASSERT(i2c_num < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[i2c_num]; - uint8_t fifo_len, index; + size_t fifo_len, index; while (send_buf_len) { @@ -82,10 +85,12 @@ int i2c_send_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t s } while (i2c_adapter->status & I2C_STATUS_ACTIVITY) ; + return 0; } -int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len) +void i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, const uint8_t *send_buf, + size_t send_buf_len) { configASSERT(i2c_num < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[i2c_num]; @@ -97,7 +102,7 @@ int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t buf[i] = send_buf[i]; } - sysctl_dma_select(dma_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)dma_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2); dmac_set_single_mode(dma_channel_num, buf, (void*)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, send_buf_len); @@ -109,14 +114,15 @@ int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t if (i2c_adapter->tx_abrt_source != 0) configASSERT(!"source abort"); } - return 0; } -int i2c_receive_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len) +int i2c_recv_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, + size_t receive_buf_len) { - uint8_t fifo_len, index; - uint8_t rx_len = receive_buf_len; configASSERT(i2c_num < I2C_MAX_NUM); + + size_t fifo_len, index; + size_t rx_len = receive_buf_len; volatile i2c_t* i2c_adapter = i2c[i2c_num]; while (send_buf_len) @@ -135,7 +141,7 @@ int i2c_receive_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_ fifo_len = i2c_adapter->rxflr; fifo_len = rx_len < fifo_len ? rx_len : fifo_len; for (index = 0; index < fifo_len; index++) - *receive_buf++ = i2c_adapter->data_cmd; + *receive_buf++ = (uint8_t)i2c_adapter->data_cmd; rx_len -= fifo_len; fifo_len = 8 - i2c_adapter->txflr; fifo_len = receive_buf_len < fifo_len ? receive_buf_len : fifo_len; @@ -148,10 +154,12 @@ int i2c_receive_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_ return 0; } -int i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len) +void i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, + i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, + uint8_t *receive_buf, size_t receive_buf_len) { configASSERT(i2c_num < I2C_MAX_NUM); + volatile i2c_t* i2c_adapter = i2c[i2c_num]; uint32_t* write_cmd = malloc(sizeof(uint32_t) * (send_buf_len + receive_buf_len)); @@ -161,8 +169,8 @@ int i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channe for (i = 0; i < receive_buf_len; i++) write_cmd[i + send_buf_len] = I2C_DATA_CMD_CMD; - sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2); - sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_I2C0_RX_REQ + i2c_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)dma_send_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2); + sysctl_dma_select((sysctl_dma_channel_t)dma_receive_channel_num, SYSCTL_DMA_SELECT_I2C0_RX_REQ + i2c_num * 2); dmac_set_single_mode(dma_receive_channel_num, (void*)(&i2c_adapter->data_cmd), write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, receive_buf_len); @@ -175,10 +183,9 @@ int i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channe for (i = 0; i < receive_buf_len; i++) { - receive_buf[i] = write_cmd[i]; + receive_buf[i] = (uint8_t)write_cmd[i]; } free(write_cmd); - return 0; } diff --git a/lib/drivers/include/i2c.h b/lib/drivers/include/i2c.h index cc8aed57..a6f5461c 100644 --- a/lib/drivers/include/i2c.h +++ b/lib/drivers/include/i2c.h @@ -348,7 +348,8 @@ typedef enum _i2c_bus_speed_mode * @param[in] address_width address width 7bit or 10bit * @param[in] bus_speed_mode i2c rate */ -void i2c_config(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode); +void i2c_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width, + i2c_bus_speed_mode_t bus_speed_mode); /** * @brief I2c send data @@ -375,7 +376,8 @@ int i2c_send_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t s * - 0 Success * - Other Fail */ -int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len); +void i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, const uint8_t *send_buf, + size_t send_buf_len); /** * @brief I2c receive data @@ -390,7 +392,8 @@ int i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t * - 0 Success * - Other Fail */ -int i2c_receive_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len); +int i2c_recv_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, + size_t receive_buf_len); /** * @brief I2c receive data by dma @@ -407,8 +410,9 @@ int i2c_receive_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_ * - 0 Success * - Other Fail */ -int i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, uint8_t *receive_buf, size_t receive_buf_len); +void i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, + i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, + uint8_t *receive_buf, size_t receive_buf_len); #ifdef __cplusplus } diff --git a/lib/drivers/include/spi.h b/lib/drivers/include/spi.h index 78c788a7..17ba63e0 100644 --- a/lib/drivers/include/spi.h +++ b/lib/drivers/include/spi.h @@ -172,7 +172,8 @@ extern volatile spi_t *const spi[4]; * - 0 Success * - Other Fail */ -void spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format, size_t data_bit_length); +void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format, + size_t data_bit_length); /** * @brief Set multiline configuration @@ -184,8 +185,8 @@ void spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_f * @param[in] instruction_address_trans_mode Spi transfer mode * */ -void spi_config_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length, - uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode); +void spi_init_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length, + uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode); /** * @brief Spi send data diff --git a/lib/drivers/spi.c b/lib/drivers/spi.c index f4f8381a..260e37f1 100644 --- a/lib/drivers/spi.c +++ b/lib/drivers/spi.c @@ -58,7 +58,8 @@ static void spi_set_tmod(uint8_t spi_num, uint32_t tmod) set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset); } -void spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format, size_t data_bit_length) +void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format, + size_t data_bit_length) { configASSERT(data_bit_length >= 4 && data_bit_length <= 32); configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -109,8 +110,8 @@ void spi_config(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_f spi_adapter->spi_ctrlr0 = 0; } -void spi_config_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length, - uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode) +void spi_init_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length, + uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode) { configASSERT(wait_cycles < (1 << 5)); configASSERT(instruction_address_trans_mode < 3); diff --git a/lib/firmware/nt35310.c b/lib/firmware/nt35310.c index 33dcfcf9..aa967b1d 100644 --- a/lib/firmware/nt35310.c +++ b/lib/firmware/nt35310.c @@ -71,47 +71,52 @@ void tft_hard_init(void) { init_dcx(); pin_mux_init(); - spi_config(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8); + spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8); } void tft_write_command(uint8_t cmd) { set_dcx_control(); - spi_config(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8); - spi_config_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); + spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8); + spi_init_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT, (uint8_t *)(&cmd), 1,SPI_TRANS_CHAR); } void tft_write_byte(uint8_t *data_buf, uint32_t length) { set_dcx_data(); - spi_config(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8); - spi_config_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); + spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8); + spi_init_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT, data_buf, length, SPI_TRANS_CHAR); } void tft_write_half(uint16_t *data_buf, uint32_t length) { set_dcx_data(); - spi_config(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 16); - spi_config_non_standard(SPI_CHANNEL, 16/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); + spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 16); + spi_init_non_standard(SPI_CHANNEL, 16/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_SHORT); } void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag) { set_dcx_data(); - spi_config(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 32); + spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 32); - spi_config_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); + spi_init_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_INT); } void tft_fill_data(uint32_t *data_buf, uint32_t length) { set_dcx_data(); - spi_config(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 32); - spi_config_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); + spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 32); + spi_init_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); spi_fill_data_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length); } diff --git a/lib/firmware/sd3068.c b/lib/firmware/sd3068.c index 5ccc59cd..823ae9c5 100644 --- a/lib/firmware/sd3068.c +++ b/lib/firmware/sd3068.c @@ -25,7 +25,7 @@ uint32_t i2c_bus_no = 0; void sd3068_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode) { i2c_bus_no = i2c_num; - i2c_config(i2c_num, slave_address, address_width, bus_speed_mode); + i2c_init(i2c_num, slave_address, address_width, bus_speed_mode); } static int sd3068_write_reg(uint8_t reg, uint8_t *data_buf, uint8_t length) @@ -51,7 +51,7 @@ static int sd3068_write_reg_dma(uint8_t reg, uint8_t *data_buf, uint8_t length) static int sd3068_read_reg(uint8_t reg, uint8_t *data_buf, uint8_t length) { - i2c_receive_data(i2c_bus_no, ®, 1, data_buf, length); + i2c_recv_data(i2c_bus_no, ®, 1, data_buf, length); return 0; } diff --git a/lib/firmware/w25qxx.c b/lib/firmware/w25qxx.c index 856f0ce5..852537c6 100644 --- a/lib/firmware/w25qxx.c +++ b/lib/firmware/w25qxx.c @@ -33,14 +33,14 @@ static w25qxx_status_t w25qxx_quad_page_program_dma(uint32_t addr, uint8_t *data static w25qxx_status_t w25qxx_receive_data(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) { - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); spi_receive_data_standard(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); return W25QXX_OK; } static w25qxx_status_t w25qxx_receive_data_dma(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) { - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); spi_receive_data_standard_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); return W25QXX_OK; } @@ -85,7 +85,7 @@ w25qxx_status_t w25qxx_init(uint8_t spi_index, uint8_t spi_ss) { spi_bus_no = spi_index; spi_chip_select = spi_ss; - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); w25qxx_page_program_fun = w25qxx_page_program; w25qxx_read_fun = w25qxx_stand_read_data; return W25QXX_OK; @@ -95,7 +95,7 @@ w25qxx_status_t w25qxx_init_dma(uint8_t spi_index, uint8_t spi_ss) { spi_bus_no = spi_index; spi_chip_select = spi_ss; - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); w25qxx_page_program_fun = w25qxx_page_program_dma; w25qxx_read_fun = w25qxx_stand_read_data; return W25QXX_OK; @@ -354,8 +354,9 @@ static w25qxx_status_t w25qxx_quad_page_program(uint32_t addr, uint8_t *data_buf cmd[0] = QUAD_PAGE_PROGRAM; cmd[1] = addr; w25qxx_write_enable(); - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/, + SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_send_data_enhanced(cmd, 2, data_buf, length); while (w25qxx_is_busy() == W25QXX_BUSY) ; @@ -369,8 +370,9 @@ static w25qxx_status_t w25qxx_quad_page_program_dma(uint32_t addr, uint8_t *data cmd[0] = QUAD_PAGE_PROGRAM; cmd[1] = addr; w25qxx_write_enable_dma(); - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/, + SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_send_data_enhanced_dma(cmd, 2, data_buf, length); while (w25qxx_is_busy_dma() == W25QXX_BUSY) ; @@ -494,35 +496,39 @@ static w25qxx_status_t _w25qxx_read_data(uint32_t addr, uint8_t *data_buf, uint3 *(((uint8_t *)cmd) + 2) = (uint8_t)(addr >> 8); *(((uint8_t *)cmd) + 3) = (uint8_t)(addr >> 0); *(((uint8_t *)cmd) + 4) = 0xFF; - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); w25qxx_receive_data((uint8_t *)cmd, 5, data_buf, length); break; case W25QXX_DUAL: cmd[0] = FAST_READ_DUAL_OUTPUT; cmd[1] = addr; - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); - spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); + spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, + SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); break; case W25QXX_DUAL_FAST: cmd[0] = FAST_READ_DUAL_IO; cmd[1] = addr << 8; - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); - spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); + spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, + SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); break; case W25QXX_QUAD: cmd[0] = FAST_READ_QUAL_OUTPUT; cmd[1] = addr; - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, + SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); break; case W25QXX_QUAD_FAST: cmd[0] = FAST_READ_QUAL_IO; cmd[1] = addr << 8; - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, + SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); break; } @@ -552,29 +558,33 @@ static w25qxx_status_t w25qxx_read_data_dma_less_1000bytes(uint32_t addr, uint8_ case W25QXX_DUAL: cmd[0] = FAST_READ_DUAL_OUTPUT; cmd[1] = addr; - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); - spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); + spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, + SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); break; case W25QXX_DUAL_FAST: cmd[0] = FAST_READ_DUAL_IO; cmd[1] = addr << 8; - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); - spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); + spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, + SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); break; case W25QXX_QUAD: cmd[0] = FAST_READ_QUAL_OUTPUT; cmd[1] = addr; - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, SPI_AITM_STANDARD/*spi address trans mode*/); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, + SPI_AITM_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); break; case W25QXX_QUAD_FAST: cmd[0] = FAST_READ_QUAL_IO; cmd[1] = addr << 8; - spi_config(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_config_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); + spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); + spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, + SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); break; } From 2c4f3a674b81e1ccd9e566ccb157acf6bf0a1f6c Mon Sep 17 00:00:00 2001 From: latyas Date: Tue, 2 Oct 2018 18:40:32 +0800 Subject: [PATCH 32/58] update function signature --- lib/drivers/i2c.c | 6 +++--- lib/drivers/i2s.c | 42 +++++++++++++++++++-------------------- lib/drivers/include/i2c.h | 6 +++--- lib/firmware/sd3068.c | 2 +- 4 files changed, 28 insertions(+), 28 deletions(-) diff --git a/lib/drivers/i2c.c b/lib/drivers/i2c.c index fe3074bd..42c8b59f 100644 --- a/lib/drivers/i2c.c +++ b/lib/drivers/i2c.c @@ -154,9 +154,9 @@ int i2c_recv_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t s return 0; } -void i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, - uint8_t *receive_buf, size_t receive_buf_len) +void i2c_recv_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, + i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, + uint8_t *receive_buf, size_t receive_buf_len) { configASSERT(i2c_num < I2C_MAX_NUM); diff --git a/lib/drivers/i2s.c b/lib/drivers/i2s.c index 1303bb0f..af2f9987 100644 --- a/lib/drivers/i2s.c +++ b/lib/drivers/i2s.c @@ -26,8 +26,8 @@ volatile i2s_t *const i2s[3] = (volatile i2s_t *)I2S2_BASE_ADDR }; -int i2s_receive_channel_enable(i2s_device_number_t device_num, - i2s_channel_num_t channel_num, uint32_t enable) +static int i2s_recv_channel_enable(i2s_device_number_t device_num, + i2s_channel_num_t channel_num, uint32_t enable) { rer_t u_rer; @@ -39,7 +39,7 @@ int i2s_receive_channel_enable(i2s_device_number_t device_num, return 0; } -int i2s_transmit_channel_enable(i2s_device_number_t device_num, +static int i2s_transmit_channel_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint32_t enable) { ter_t u_ter; @@ -53,7 +53,7 @@ int i2s_transmit_channel_enable(i2s_device_number_t device_num, return 0; } -void i2s_receive_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num) +static void i2s_receive_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num) { irer_t u_irer; @@ -62,11 +62,11 @@ void i2s_receive_enable(i2s_device_number_t device_num, i2s_channel_num_t channe writel(u_irer.reg_data, &i2s[device_num]->irer); /* I2S_RECEIVER block enable */ - i2s_receive_channel_enable(device_num, channel_num, 1); + i2s_recv_channel_enable(device_num, channel_num, 1); /* Receive channel enable */ } -void i2s_transimit_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num) +static void i2s_transimit_enable(i2s_device_number_t device_num, i2s_channel_num_t channel_num) { iter_t u_iter; @@ -79,7 +79,7 @@ void i2s_transimit_enable(i2s_device_number_t device_num, i2s_channel_num_t chan /* Transmit channel enable */ } -void i2s_set_enable(i2s_device_number_t device_num, uint32_t enable) +static void i2s_set_enable(i2s_device_number_t device_num, uint32_t enable) { ier_t u_ier; @@ -88,7 +88,7 @@ void i2s_set_enable(i2s_device_number_t device_num, uint32_t enable) writel(u_ier.reg_data, &i2s[device_num]->ier); } -void i2s_disable_block(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode) +static void i2s_disable_block(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode) { irer_t u_irer; iter_t u_iter; @@ -109,7 +109,7 @@ void i2s_disable_block(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode) } } -int i2s_set_rx_word_length(i2s_device_number_t device_num, +static int i2s_set_rx_word_length(i2s_device_number_t device_num, i2s_word_length_t word_length, i2s_channel_num_t channel_num) { @@ -126,7 +126,7 @@ int i2s_set_rx_word_length(i2s_device_number_t device_num, return 0; } -int i2s_set_tx_word_length(i2s_device_number_t device_num, +static int i2s_set_tx_word_length(i2s_device_number_t device_num, i2s_word_length_t word_length, i2s_channel_num_t channel_num) { @@ -169,7 +169,7 @@ static void i2s_master_configure(i2s_device_number_t device_num, } -static int i2s_set_rx_threshold(i2s_device_number_t device_num, +static static int i2s_set_rx_threshold(i2s_device_number_t device_num, i2s_fifo_threshold_t threshold, i2s_channel_num_t channel_num) { @@ -187,7 +187,7 @@ static int i2s_set_rx_threshold(i2s_device_number_t device_num, return 0; } -int i2s_set_tx_threshold(i2s_device_number_t device_num, +static int i2s_set_tx_threshold(i2s_device_number_t device_num, i2s_fifo_threshold_t threshold, i2s_channel_num_t channel_num) { @@ -204,7 +204,7 @@ int i2s_set_tx_threshold(i2s_device_number_t device_num, return 0; } -int i2s_set_mask_interrupt(i2s_device_number_t device_num, +static int i2s_set_mask_interrupt(i2s_device_number_t device_num, i2s_channel_num_t channel_num, uint32_t rx_available_int, uint32_t rx_overrun_int, uint32_t tx_empty_int, uint32_t tx_overrun_int) @@ -236,7 +236,7 @@ int i2s_set_mask_interrupt(i2s_device_number_t device_num, return 0; } -int i2s_transmit_dma_enable(i2s_device_number_t device_num, uint32_t enable) +static int i2s_transmit_dma_enable(i2s_device_number_t device_num, uint32_t enable) { ccr_t u_ccr; @@ -250,7 +250,7 @@ int i2s_transmit_dma_enable(i2s_device_number_t device_num, uint32_t enable) return 0; } -int i2s_receive_dma_enable(i2s_device_number_t device_num, uint32_t enable) +static int i2s_receive_dma_enable(i2s_device_number_t device_num, uint32_t enable) { ccr_t u_ccr; @@ -264,7 +264,7 @@ int i2s_receive_dma_enable(i2s_device_number_t device_num, uint32_t enable) return 0; } -int i2s_transmit_dma_divide(i2s_device_number_t device_num, uint32_t enable) +static int i2s_transmit_dma_divide(i2s_device_number_t device_num, uint32_t enable) { ccr_t u_ccr; @@ -379,7 +379,7 @@ int i2s_send_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, return 0; } -void i2s_send_data_dma(i2s_device_number_t device_num, const void *buf, size_t buf_len, dmac_channel_number_t channel_num) +static void i2s_send_data_dma(i2s_device_number_t device_num, const void *buf, size_t buf_len, dmac_channel_number_t channel_num) { static uint8_t dmac_init_flag[6] = {0,0,0,0,0,0}; if(dmac_init_flag[channel_num]) @@ -391,7 +391,7 @@ void i2s_send_data_dma(i2s_device_number_t device_num, const void *buf, size_t b DMAC_ADDR_NOCHANGE, DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, buf_len); } -void i2s_parse_voice(uint32_t *buf, const uint8_t *pcm, size_t length, size_t bits_per_sample, +static void i2s_parse_voice(uint32_t *buf, const uint8_t *pcm, size_t length, size_t bits_per_sample, uint8_t track_num, size_t *send_len) { uint32_t i,j=0; @@ -501,7 +501,7 @@ void i2s_rx_channel_config(i2s_device_number_t device_num, i2s_fifo_threshold_t trigger_level, i2s_work_mode_t word_mode) { - i2s_receive_channel_enable(device_num, channel_num, 0); + i2s_recv_channel_enable(device_num, channel_num, 0); /* Receive channel disable */ writel(0, &i2s[device_num]->channel[channel_num].ter); @@ -526,7 +526,7 @@ void i2s_rx_channel_config(i2s_device_number_t device_num, readl(&i2s[device_num]->channel[channel_num].ror); readl(&i2s[device_num]->channel[channel_num].tor); - i2s_receive_channel_enable(device_num, channel_num, 1); + i2s_recv_channel_enable(device_num, channel_num, 1); } void i2s_tx_channel_config(i2s_device_number_t device_num, @@ -603,7 +603,7 @@ void i2s_init(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode, uint32_t } else { - i2s_receive_channel_enable(device_num, I2S_CHANNEL_0 + i, 0); + i2s_recv_channel_enable(device_num, I2S_CHANNEL_0 + i, 0); } channel_mask >>= 2; } diff --git a/lib/drivers/include/i2c.h b/lib/drivers/include/i2c.h index a6f5461c..d2bb3f2b 100644 --- a/lib/drivers/include/i2c.h +++ b/lib/drivers/include/i2c.h @@ -410,9 +410,9 @@ int i2c_recv_data(i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t s * - 0 Success * - Other Fail */ -void i2c_receive_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, - i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, - uint8_t *receive_buf, size_t receive_buf_len); +void i2c_recv_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num, + i2c_device_number_t i2c_num, const uint8_t *send_buf, size_t send_buf_len, + uint8_t *receive_buf, size_t receive_buf_len); #ifdef __cplusplus } diff --git a/lib/firmware/sd3068.c b/lib/firmware/sd3068.c index 823ae9c5..3df78267 100644 --- a/lib/firmware/sd3068.c +++ b/lib/firmware/sd3068.c @@ -57,7 +57,7 @@ static int sd3068_read_reg(uint8_t reg, uint8_t *data_buf, uint8_t length) static int sd3068_read_reg_dma(uint8_t reg, uint8_t *data_buf, uint8_t length) { - i2c_receive_data_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, i2c_bus_no, ®, 1, data_buf, length); + i2c_recv_data_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, i2c_bus_no, ®, 1, data_buf, length); return 0; } From 13f70f2f40fdf8c74deed506d374f85d55c53e00 Mon Sep 17 00:00:00 2001 From: jiangxiangbing Date: Tue, 2 Oct 2018 22:28:57 +0800 Subject: [PATCH 33/58] update i2s --- lib/drivers/i2s.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/drivers/i2s.c b/lib/drivers/i2s.c index af2f9987..4fad8efc 100644 --- a/lib/drivers/i2s.c +++ b/lib/drivers/i2s.c @@ -169,7 +169,7 @@ static void i2s_master_configure(i2s_device_number_t device_num, } -static static int i2s_set_rx_threshold(i2s_device_number_t device_num, +static int i2s_set_rx_threshold(i2s_device_number_t device_num, i2s_fifo_threshold_t threshold, i2s_channel_num_t channel_num) { @@ -379,7 +379,7 @@ int i2s_send_data(i2s_device_number_t device_num, i2s_channel_num_t channel_num, return 0; } -static void i2s_send_data_dma(i2s_device_number_t device_num, const void *buf, size_t buf_len, dmac_channel_number_t channel_num) +void i2s_send_data_dma(i2s_device_number_t device_num, const void *buf, size_t buf_len, dmac_channel_number_t channel_num) { static uint8_t dmac_init_flag[6] = {0,0,0,0,0,0}; if(dmac_init_flag[channel_num]) From ca29317aed0e6db8420c8194ade5102ecef96cbe Mon Sep 17 00:00:00 2001 From: latyas Date: Wed, 3 Oct 2018 03:58:29 +0800 Subject: [PATCH 34/58] fix coding style --- lib/drivers/include/gpio_common.h | 4 ++-- lib/firmware/nt35310.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/drivers/include/gpio_common.h b/lib/drivers/include/gpio_common.h index 40e52745..af402f01 100644 --- a/lib/drivers/include/gpio_common.h +++ b/lib/drivers/include/gpio_common.h @@ -37,8 +37,8 @@ typedef enum _gpio_pin_edge typedef enum _gpio_pin_value { - GPIO_PV_Low, - GPIO_PV_High + GPIO_PV_LOW, + GPIO_PV_HIGH } gpio_pin_value_t; #ifdef __cplusplus diff --git a/lib/firmware/nt35310.c b/lib/firmware/nt35310.c index aa967b1d..0c96641f 100644 --- a/lib/firmware/nt35310.c +++ b/lib/firmware/nt35310.c @@ -37,22 +37,22 @@ void init_dcx(void) { fpioa_set_function(DCX_IO, FUNC_GPIOHS0 + DCX_GPIONUM);/*dcx*/ gpiohs_set_drive_mode(DCX_GPIONUM, GPIO_DM_OUTPUT); - gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_High); + gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_HIGH); #ifndef TEST2_0 fpioa_set_function(RESET_IO, FUNC_GPIOHS0 + RESET_GPIONUM);/*reset*/ gpiohs_set_drive_mode(RESET_GPIONUM, GPIO_DM_OUTPUT); - gpiohs_set_pin(RESET_GPIONUM, GPIO_PV_High); + gpiohs_set_pin(RESET_GPIONUM, GPIO_PV_HIGH); #endif } void set_dcx_control(void) { - gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_Low); + gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_LOW); } void set_dcx_data(void) { - gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_High); + gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_HIGH); } void pin_mux_init(void) From 0d6a494138f643edc41d4a78ec9b5a0d5605c561 Mon Sep 17 00:00:00 2001 From: latyas Date: Wed, 3 Oct 2018 03:58:47 +0800 Subject: [PATCH 35/58] rollback sha256 api signatures --- lib/drivers/include/sha256.h | 2 +- lib/drivers/sha256.c | 11 +++++------ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/lib/drivers/include/sha256.h b/lib/drivers/include/sha256.h index e9530893..1d56c92c 100644 --- a/lib/drivers/include/sha256.h +++ b/lib/drivers/include/sha256.h @@ -56,7 +56,7 @@ typedef struct _sha256_context * @param[in] context SHA256 context object * */ -void sha256_init(sha256_context_t *context); +void sha256_init(sha256_context_t *context, size_t buf_len); /** * @brief Called repeatedly with chunks of the message to be hashed diff --git a/lib/drivers/sha256.c b/lib/drivers/sha256.c index 76cee41b..de6368e1 100644 --- a/lib/drivers/sha256.c +++ b/lib/drivers/sha256.c @@ -42,10 +42,13 @@ static inline uint64_t byteswap64(uint64_t x) return ((uint64_t)BYTESWAP(b) << 32) | (uint64_t)BYTESWAP(a); } -void sha256_init(sha256_context_t *context) +void sha256_init(sha256_context_t *context, size_t buf_len) { sysctl_clock_enable(SYSCTL_CLOCK_SHA); sysctl_reset(SYSCTL_RESET_SHA); + + sha256->sha_data_num = (uint32_t)((buf_len + SHA256_BLOCK_LEN + 8) / SHA256_BLOCK_LEN); + sha256->sha_input_ctrl &= (~0x1); sha256->sha_status |= SHA256_BIG_ENDIAN; sha256->sha_status |= ENABLE_SHA; @@ -55,15 +58,11 @@ void sha256_init(sha256_context_t *context) void sha256_update(sha256_context_t *context, const void *data_buf, size_t buf_len) { - configASSERT(buf_len <= UINT32_MAX); - const uint8_t* data = data_buf; size_t buffer_bytes_left; size_t bytes_to_copy; uint32_t i; - sha256->sha_data_num = (uint32_t)((buf_len + SHA256_BLOCK_LEN + 8) / SHA256_BLOCK_LEN); - while (buf_len) { buffer_bytes_left = SHA256_BLOCK_LEN - context->buffer_length; @@ -115,7 +114,7 @@ void sha256_final(sha256_context_t *context, uint8_t *output) void sha256_hard_calculate(const uint8_t *data, size_t data_len, uint8_t *output) { sha256_context_t sha; - sha256_init(&sha); + sha256_init(&sha, data_len); sha256_update(&sha, data, data_len); sha256_final(&sha, output); } From 8bb1ccd7dac9bad9d3b732381d371bffaa4a9041 Mon Sep 17 00:00:00 2001 From: latyas Date: Wed, 3 Oct 2018 16:28:06 +0800 Subject: [PATCH 36/58] update redundent uaths init codes --- lib/drivers/uarths.c | 25 +------------------------ 1 file changed, 1 insertion(+), 24 deletions(-) diff --git a/lib/drivers/uarths.c b/lib/drivers/uarths.c index 8386e86e..c9351193 100644 --- a/lib/drivers/uarths.c +++ b/lib/drivers/uarths.c @@ -23,32 +23,9 @@ volatile uarths_t *const uarths = (volatile uarths_t *)UARTHS_BASE_ADDR; static inline int uarths_putc(char c) { - /* Read core id */ - unsigned long core_id = current_coreid(); - /* Set print data reg */ - volatile uint32_t *reg = (volatile uint32_t *)0x50440080UL; - /* Push data out */ - if (core_id == 0) - { - /* Select core 0 data reg */ - *reg = (0UL << 30) | c; - } - else - { - /* Select core 1 data reg */ - *reg = (1UL << 30) | c; - } - - /* Convert to DOS style (CRLF terminated) */ - if (c == '\n') - { - while (uarths->txdata.full) - continue; - uarths->txdata.data = '\r'; - } while (uarths->txdata.full) continue; - uarths->txdata.data = c; + uarths->txdata.data = (uint8_t)c; return 0; } From 98ed6b599a2e5419ea43b7bdb0623aed7b78294a Mon Sep 17 00:00:00 2001 From: latyas Date: Wed, 3 Oct 2018 17:20:50 +0800 Subject: [PATCH 37/58] update change cpu freq --- lib/drivers/sysctl.c | 37 ++++++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/lib/drivers/sysctl.c b/lib/drivers/sysctl.c index 020a6466..26bd010e 100644 --- a/lib/drivers/sysctl.c +++ b/lib/drivers/sysctl.c @@ -1769,26 +1769,37 @@ void sysctl_set_pll_frequency(uint64_t pll0, uint64_t pll1, uint64_t pll2) uint32_t sysctl_set_cpu_frequency(uint32_t frequency) { + /* 1. Change CPU CLK to XTAL */ sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0); - sysctl->pll0.pll_reset0 = 1; + /* 2. Disable PLL0 output */ + sysctl->pll0.pll_out_en0 = 0; + + /* 3. Turn off PLL0 */ + sysctl->pll0.pll_pwrd0 = 0; + + /* 4. Set PLL0 new value */ uint32_t result = sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, frequency * 2); + + /* 5. Power on PLL0 */ + sysctl->pll0.pll_pwrd0 = 1; + + /* 6. Reset PLL0 */ + /* 6. Release Reset */ + sysctl->pll0.pll_reset0 = 0; + sysctl->pll0.pll_reset0 = 1; sysctl->pll0.pll_reset0 = 0; - while (1) - { - uint32_t lock = sysctl->pll_lock.pll_lock0 & 0x3; - if (lock == 0x3) - { - break; - } - else - { - sysctl->pll_lock.pll_slip_clear0 = 1; - } - } + /* 7. Get lock status, wait PLL0 stable */ + while (sysctl_pll_is_lock(SYSCTL_PLL0) == 0) + sysctl_pll_clear_slip(SYSCTL_PLL0); + + /* 8. Enable PLL0 output */ sysctl->pll0.pll_out_en0 = 1; + + /* 9. Change CPU CLK to PLL0 */ sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); + return result; } From 4e3276d747d3dd210fc9f73178dca2b259fdc0fc Mon Sep 17 00:00:00 2001 From: latyas Date: Mon, 8 Oct 2018 09:11:22 +0800 Subject: [PATCH 38/58] delete init tls --- cmake/compile-flags.cmake | 1 + lib/bsp/entry_user.c | 14 +------------- 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/cmake/compile-flags.cmake b/cmake/compile-flags.cmake index 8ac7d9da..e0aa6204 100644 --- a/cmake/compile-flags.cmake +++ b/cmake/compile-flags.cmake @@ -18,6 +18,7 @@ add_compile_flags(BOTH -ffunction-sections -fdata-sections -fstrict-volatile-bitfields + -fno-zero-initialized-in-bss -Os -ggdb ) diff --git a/lib/bsp/entry_user.c b/lib/bsp/entry_user.c index b2e059ba..b56b164f 100644 --- a/lib/bsp/entry_user.c +++ b/lib/bsp/entry_user.c @@ -25,10 +25,6 @@ #include "syslog.h" #include "uarths.h" -#define PLL0_OUTPUT_FREQ 320000000UL -#define PLL1_OUTPUT_FREQ 160000000UL -#define PLL2_OUTPUT_FREQ 45158400UL - volatile char * const ram = (volatile char*)RAM_BASE_ADDR; extern char _heap_start[]; @@ -63,20 +59,12 @@ void _init_bsp(int core_id, int number_of_cores) if (core_id == 0) { - /* Copy lma data to memory */ - init_lma(); /* Initialize bss data to 0 */ init_bss(); /* Init FPIOA */ - fpioa_init(); - /* PLL init */ - sysctl_set_pll_frequency(PLL0_OUTPUT_FREQ, PLL1_OUTPUT_FREQ, PLL2_OUTPUT_FREQ); +// fpioa_init(); /* Init UART */ uarths_init(); - /* Dmac init */ - dmac_init(); - /* Plic init */ - plic_init(); /* Register finalization function */ atexit(__libc_fini_array); /* Init libc array for C++ */ From cce7bca054482cebbafe36a962dc5710fc0b9336 Mon Sep 17 00:00:00 2001 From: latyas Date: Mon, 8 Oct 2018 09:11:36 +0800 Subject: [PATCH 39/58] update change cpu freq method --- lib/drivers/sysctl.c | 67 ++++++++++++++++++++++++++++++++------------ 1 file changed, 49 insertions(+), 18 deletions(-) diff --git a/lib/drivers/sysctl.c b/lib/drivers/sysctl.c index 26bd010e..d7b59a9c 100644 --- a/lib/drivers/sysctl.c +++ b/lib/drivers/sysctl.c @@ -1744,27 +1744,58 @@ uint32_t sysctl_power_mode_sel(uint8_t power_bank, sysctl_io_power_mode_t io_pow void sysctl_set_pll_frequency(uint64_t pll0, uint64_t pll1, uint64_t pll2) { - sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0); + if (pll0 != 0U) { + /* We need to check PLL0 is enable before we change PLL0's frequency */ + sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0); + + if (sysctl->pll0.pll_out_en0 == 1 && sysctl->pll0.pll_pwrd0 == 1) { + /* PLL0 is enabled, we should disable it first */ + /* Disable PLL0 output */ + sysctl->pll0.pll_out_en0 = 0; + /* Turn off PLL0 */ + sysctl->pll0.pll_pwrd0 = 0; + } - sysctl_pll_enable(SYSCTL_PLL0); - sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, pll0); - while (sysctl_pll_is_lock(SYSCTL_PLL0) == 0) - sysctl_pll_clear_slip(SYSCTL_PLL0); - sysctl_clock_enable(SYSCTL_CLOCK_PLL0); - sysctl->clk_sel0.aclk_divider_sel = 0; - sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); + sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, pll0); + + /* Power on PLL0 */ + sysctl->pll0.pll_pwrd0 = 1; + + /* Reset PLL0 */ + /* Release Reset */ + sysctl->pll0.pll_reset0 = 0; + sysctl->pll0.pll_reset0 = 1; + sysctl->pll0.pll_reset0 = 0; + + /* 7. Get lock status, wait PLL0 stable */ + while (sysctl_pll_is_lock(SYSCTL_PLL0) == 0) + sysctl_pll_clear_slip(SYSCTL_PLL0); + + /* 8. Enable PLL0 output */ + sysctl->pll0.pll_out_en0 = 1; + + sysctl_clock_enable(SYSCTL_CLOCK_PLL0); + sysctl->clk_sel0.aclk_divider_sel = 0; + sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); + } + + if (pll1 != 0U) { + sysctl_pll_enable(SYSCTL_PLL1); + sysctl_pll_set_freq(SYSCTL_PLL1, SYSCTL_SOURCE_IN0, pll1); + while (sysctl_pll_is_lock(SYSCTL_PLL1) == 0) + sysctl_pll_clear_slip(SYSCTL_PLL1); + sysctl_clock_enable(SYSCTL_CLOCK_PLL1); + } + + if (pll2 != 0U) { + sysctl_pll_enable(SYSCTL_PLL2); + sysctl_pll_set_freq(SYSCTL_PLL2, SYSCTL_SOURCE_IN0, pll2); + while (sysctl_pll_is_lock(SYSCTL_PLL2) == 0) + sysctl_pll_clear_slip(SYSCTL_PLL2); + sysctl_clock_enable(SYSCTL_CLOCK_PLL2); + } - sysctl_pll_enable(SYSCTL_PLL1); - sysctl_pll_set_freq(SYSCTL_PLL1, SYSCTL_SOURCE_IN0, pll1); - while (sysctl_pll_is_lock(SYSCTL_PLL1) == 0) - sysctl_pll_clear_slip(SYSCTL_PLL1); - sysctl_clock_enable(SYSCTL_CLOCK_PLL1); - sysctl_pll_enable(SYSCTL_PLL2); - sysctl_pll_set_freq(SYSCTL_PLL2, SYSCTL_SOURCE_IN0, pll2); - while (sysctl_pll_is_lock(SYSCTL_PLL2) == 0) - sysctl_pll_clear_slip(SYSCTL_PLL2); - sysctl_clock_enable(SYSCTL_CLOCK_PLL2); } uint32_t sysctl_set_cpu_frequency(uint32_t frequency) From 74181242a2bbbddef9890afadaefcb4448913b71 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Mon, 8 Oct 2018 15:15:38 +0800 Subject: [PATCH 40/58] Modify "void* data" to "void *data" --- lib/bsp/syscalls.c | 4 ++-- lib/drivers/aes.c | 2 +- lib/drivers/clint.c | 4 ++-- lib/drivers/common.c | 10 +++++----- lib/drivers/fft.c | 4 ++-- lib/drivers/gpio.c | 4 ++-- lib/drivers/gpiohs.c | 8 ++++---- lib/drivers/i2c.c | 12 ++++++------ lib/drivers/include/aes.h | 2 +- lib/drivers/include/clint.h | 12 ++++++------ lib/drivers/include/utils.h | 10 +++++----- lib/drivers/plic.c | 4 ++-- lib/drivers/sha256.c | 2 +- lib/drivers/spi.c | 6 +++--- lib/drivers/utils.c | 10 +++++----- 15 files changed, 47 insertions(+), 47 deletions(-) diff --git a/lib/bsp/syscalls.c b/lib/bsp/syscalls.c index b4b10b29..412dce2d 100644 --- a/lib/bsp/syscalls.c +++ b/lib/bsp/syscalls.c @@ -198,7 +198,7 @@ static ssize_t sys_write(int file, const void *ptr, size_t len) /** * Write to a file. * - * ssize_t write(int file, const void* ptr, size_t len) + * ssize_t write(int file, const void *ptr, size_t len) * * IN : regs[10] = file, regs[11] = ptr, regs[12] = len * OUT: regs[10] = len @@ -286,7 +286,7 @@ static int sys_gettimeofday(struct timeval *tp, void *tzp) /** * Get the current time. Only relatively correct. * - * int gettimeofday(struct timeval* tp, void* tzp) + * int gettimeofday(struct timeval *tp, void *tzp) * * IN : regs[10] = tp * OUT: regs[10] = Upon successful completion, 0 shall be diff --git a/lib/drivers/aes.c b/lib/drivers/aes.c index f77ed3ae..dfcaacca 100644 --- a/lib/drivers/aes.c +++ b/lib/drivers/aes.c @@ -33,7 +33,7 @@ static void aes_write_text(uint32_t text_data) aes->aes_text_data = text_data; } -static void gcm_write_tag(uint32_t* tag) +static void gcm_write_tag(uint32_t *tag) { aes->gcm_in_tag[0] = tag[3]; aes->gcm_in_tag[1] = tag[2]; diff --git a/lib/drivers/clint.c b/lib/drivers/clint.c index 95696092..a1fdc71b 100644 --- a/lib/drivers/clint.c +++ b/lib/drivers/clint.c @@ -130,7 +130,7 @@ int clint_timer_set_single_shot(int single_shot) return 0; } -int clint_timer_register(clint_timer_callback_t callback, void* ctx) +int clint_timer_register(clint_timer_callback_t callback, void *ctx) { /* Read core id */ unsigned long core_id = current_coreid(); @@ -200,7 +200,7 @@ int clint_ipi_clear(size_t core_id) return 0; } -int clint_ipi_register(clint_ipi_callback_t callback, void* ctx) +int clint_ipi_register(clint_ipi_callback_t callback, void *ctx) { /* Read core id */ unsigned long core_id = current_coreid(); diff --git a/lib/drivers/common.c b/lib/drivers/common.c index 005ef743..d21a3b37 100644 --- a/lib/drivers/common.c +++ b/lib/drivers/common.c @@ -16,28 +16,28 @@ #include "encoding.h" #include "utils.h" -void set_bit(volatile uint32_t* bits, uint32_t mask, uint32_t value) +void set_bit(volatile uint32_t *bits, uint32_t mask, uint32_t value) { uint32_t org = (*bits) & ~mask; *bits = org | (value & mask); } -void set_bit_offset(volatile uint32_t* bits, uint32_t mask, size_t offset, uint32_t value) +void set_bit_offset(volatile uint32_t *bits, uint32_t mask, size_t offset, uint32_t value) { set_bit(bits, mask << offset, value << offset); } -void set_gpio_bit(volatile uint32_t* bits, size_t offset, uint32_t value) +void set_gpio_bit(volatile uint32_t *bits, size_t offset, uint32_t value) { set_bit_offset(bits, 1, offset, value); } -uint32_t get_bit(volatile uint32_t* bits, uint32_t mask, size_t offset) +uint32_t get_bit(volatile uint32_t *bits, uint32_t mask, size_t offset) { return ((*bits) & (mask << offset)) >> offset; } -uint32_t get_gpio_bit(volatile uint32_t* bits, size_t offset) +uint32_t get_gpio_bit(volatile uint32_t *bits, size_t offset) { return get_bit(bits, 1, offset); } diff --git a/lib/drivers/fft.c b/lib/drivers/fft.c index 6f4866c9..8b6723d6 100644 --- a/lib/drivers/fft.c +++ b/lib/drivers/fft.c @@ -59,9 +59,9 @@ void fft_complex_uint16_dma(dmac_channel_number_t dma_send_channel_num, dmac_cha fft_init(point, direction, shift, 1, 0, 0); sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_FFT_RX_REQ); sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_FFT_TX_REQ); - dmac_set_single_mode(dma_receive_channel_num, (void*)(&fft->fft_output_fifo), output, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, + dmac_set_single_mode(dma_receive_channel_num, (void *)(&fft->fft_output_fifo), output, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_64, point_num>>1); - dmac_set_single_mode(dma_send_channel_num, input, (void*)(&fft->fft_input_fifo), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, + dmac_set_single_mode(dma_send_channel_num, input, (void *)(&fft->fft_input_fifo), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_64, point_num>>1); dmac_wait_done(dma_receive_channel_num); } diff --git a/lib/drivers/gpio.c b/lib/drivers/gpio.c index 9a051b93..9b8a6c63 100644 --- a/lib/drivers/gpio.c +++ b/lib/drivers/gpio.c @@ -64,7 +64,7 @@ gpio_pin_value_t gpio_get_pin(uint8_t pin) { configASSERT(pin < GPIO_MAX_PINNO); uint32_t dir = get_gpio_bit(gpio->direction.u32, pin); - volatile uint32_t* reg = dir ? gpio->data_output.u32 : gpio->data_input.u32; + volatile uint32_t *reg = dir ? gpio->data_output.u32 : gpio->data_input.u32; return get_gpio_bit(reg, pin); } @@ -72,7 +72,7 @@ void gpio_set_pin(uint8_t pin, gpio_pin_value_t value) { configASSERT(pin < GPIO_MAX_PINNO); uint32_t dir = get_gpio_bit(gpio->direction.u32, pin); - volatile uint32_t* reg = dir ? gpio->data_output.u32 : gpio->data_input.u32; + volatile uint32_t *reg = dir ? gpio->data_output.u32 : gpio->data_input.u32; configASSERT(dir == 1); set_gpio_bit(reg, pin, value); } diff --git a/lib/drivers/gpiohs.c b/lib/drivers/gpiohs.c index b094497b..2829acb5 100644 --- a/lib/drivers/gpiohs.c +++ b/lib/drivers/gpiohs.c @@ -61,8 +61,8 @@ void gpiohs_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode) } fpioa_set_io_pull(io_number, pull); - volatile uint32_t* reg = dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32; - volatile uint32_t* reg_d = !dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32; + volatile uint32_t *reg = dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32; + volatile uint32_t *reg_d = !dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32; set_gpio_bit(reg_d, pin, 0); set_gpio_bit(reg, pin, 1); } @@ -108,9 +108,9 @@ void gpiohs_set_pin_edge(uint8_t pin, gpio_pin_edge_t edge) pin_context[pin].edge = edge; } -int gpiohs_pin_onchange_isr(void* userdata) +int gpiohs_pin_onchange_isr(void *userdata) { - gpiohs_pin_context* ctx = (gpiohs_pin_context*)userdata; + gpiohs_pin_context *ctx = (gpiohs_pin_context *)userdata; size_t pin = ctx->pin; uint32_t rise, fall; switch (ctx->edge) diff --git a/lib/drivers/i2c.c b/lib/drivers/i2c.c index 42c8b59f..a899894c 100644 --- a/lib/drivers/i2c.c +++ b/lib/drivers/i2c.c @@ -95,7 +95,7 @@ void i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_ configASSERT(i2c_num < I2C_MAX_NUM); volatile i2c_t* i2c_adapter = i2c[i2c_num]; - uint32_t* buf = malloc(send_buf_len * sizeof(uint32_t)); + uint32_t *buf = malloc(send_buf_len * sizeof(uint32_t)); int i; for (i = 0; i < send_buf_len; i++) { @@ -103,11 +103,11 @@ void i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_ } sysctl_dma_select((sysctl_dma_channel_t)dma_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2); - dmac_set_single_mode(dma_channel_num, buf, (void*)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, + dmac_set_single_mode(dma_channel_num, buf, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, send_buf_len); dmac_wait_done(dma_channel_num); - free((void*)buf); + free((void *)buf); while (i2c_adapter->status & I2C_STATUS_ACTIVITY) { @@ -162,7 +162,7 @@ void i2c_recv_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_ volatile i2c_t* i2c_adapter = i2c[i2c_num]; - uint32_t* write_cmd = malloc(sizeof(uint32_t) * (send_buf_len + receive_buf_len)); + uint32_t *write_cmd = malloc(sizeof(uint32_t) * (send_buf_len + receive_buf_len)); size_t i; for(i = 0; i < send_buf_len; i++) write_cmd[i] = *send_buf++; @@ -172,10 +172,10 @@ void i2c_recv_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_ sysctl_dma_select((sysctl_dma_channel_t)dma_send_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2); sysctl_dma_select((sysctl_dma_channel_t)dma_receive_channel_num, SYSCTL_DMA_SELECT_I2C0_RX_REQ + i2c_num * 2); - dmac_set_single_mode(dma_receive_channel_num, (void*)(&i2c_adapter->data_cmd), write_cmd, DMAC_ADDR_NOCHANGE, + dmac_set_single_mode(dma_receive_channel_num, (void *)(&i2c_adapter->data_cmd), write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, receive_buf_len); - dmac_set_single_mode(dma_send_channel_num, write_cmd, (void*)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, + dmac_set_single_mode(dma_send_channel_num, write_cmd, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, receive_buf_len + send_buf_len); dmac_wait_done(dma_send_channel_num); diff --git a/lib/drivers/include/aes.h b/lib/drivers/include/aes.h index 25184803..0740a040 100644 --- a/lib/drivers/include/aes.h +++ b/lib/drivers/include/aes.h @@ -112,7 +112,7 @@ typedef struct _aes_param size_t input_key_len; uint8_t *iv; uint8_t iv_len; - uint8_t* gcm_add; + uint8_t *gcm_add; size_t gcm_add_len; aes_cipher_mode_t cipher_mode; uint8_t *output_data; diff --git a/lib/drivers/include/clint.h b/lib/drivers/include/clint.h index 25bcf1ce..3e8b1b1e 100644 --- a/lib/drivers/include/clint.h +++ b/lib/drivers/include/clint.h @@ -134,12 +134,12 @@ extern volatile clint_t* const clint; /** * @brief Definitions for the timer callbacks */ -typedef int (*clint_timer_callback_t)(void* ctx); +typedef int (*clint_timer_callback_t)(void *ctx); /** * @brief Definitions for local interprocessor interrupt callbacks */ -typedef int (*clint_ipi_callback_t)(void* ctx); +typedef int (*clint_ipi_callback_t)(void *ctx); typedef struct _clint_timer_instance { @@ -147,13 +147,13 @@ typedef struct _clint_timer_instance uint64_t cycles; uint64_t single_shot; clint_timer_callback_t callback; - void* ctx; + void *ctx; } clint_timer_instance_t; typedef struct _clint_ipi_instance { clint_ipi_callback_t callback; - void* ctx; + void *ctx; } clint_ipi_instance_t; /** @@ -248,7 +248,7 @@ int clint_timer_set_single_shot(int single_shot); * - 0 Success * - Other Fail */ -int clint_timer_register(clint_timer_callback_t callback, void* ctx); +int clint_timer_register(clint_timer_callback_t callback, void *ctx); /** * @brief Deregister user callback function @@ -319,7 +319,7 @@ int clint_ipi_clear(size_t core_id); * - 0 Success * - Other Fail */ -int clint_ipi_register(clint_ipi_callback_t callback, void* ctx); +int clint_ipi_register(clint_ipi_callback_t callback, void *ctx); /** * @brief Deregister user callback function diff --git a/lib/drivers/include/utils.h b/lib/drivers/include/utils.h index 28cf3df9..4782d2f1 100644 --- a/lib/drivers/include/utils.h +++ b/lib/drivers/include/utils.h @@ -297,7 +297,7 @@ extern "C" { * @param[in] mask mask value * @param[in] value The value to set */ -void set_bit(volatile uint32_t* bits, uint32_t mask, uint32_t value); +void set_bit(volatile uint32_t *bits, uint32_t mask, uint32_t value); /** * @brief Set value by mask @@ -307,7 +307,7 @@ void set_bit(volatile uint32_t* bits, uint32_t mask, uint32_t value); * @param[in] offset Mask's offset * @param[in] value The value to set */ -void set_bit_offset(volatile uint32_t* bits, uint32_t mask, size_t offset, uint32_t value); +void set_bit_offset(volatile uint32_t *bits, uint32_t mask, size_t offset, uint32_t value); /** * @brief Set bit for gpio, only set one bit @@ -316,7 +316,7 @@ void set_bit_offset(volatile uint32_t* bits, uint32_t mask, size_t offset, uint3 * @param[in] idx Offset value * @param[in] value The value to set */ -void set_gpio_bit(volatile uint32_t* bits, size_t idx, uint32_t value); +void set_gpio_bit(volatile uint32_t *bits, size_t idx, uint32_t value); /** * @brief Get bits value of mask @@ -327,7 +327,7 @@ void set_gpio_bit(volatile uint32_t* bits, size_t idx, uint32_t value); * * @return The bits value of mask */ -uint32_t get_bit(volatile uint32_t* bits, uint32_t mask, size_t offset); +uint32_t get_bit(volatile uint32_t *bits, uint32_t mask, size_t offset); /** * @brief Get a bit value by offset @@ -338,7 +338,7 @@ uint32_t get_bit(volatile uint32_t* bits, uint32_t mask, size_t offset); * * @return The bit value */ -uint32_t get_gpio_bit(volatile uint32_t* bits, size_t offset); +uint32_t get_gpio_bit(volatile uint32_t *bits, size_t offset); #ifdef __cplusplus } diff --git a/lib/drivers/plic.c b/lib/drivers/plic.c index 70d8f580..72bed79d 100644 --- a/lib/drivers/plic.c +++ b/lib/drivers/plic.c @@ -24,7 +24,7 @@ volatile plic_t* const plic = (volatile plic_t*)PLIC_BASE_ADDR; typedef struct _plic_instance_t { plic_irq_callback_t callback; - void* ctx; + void *ctx; } plic_instance_t; static plic_instance_t plic_instance[PLIC_NUM_CORES][IRQN_MAX]; @@ -138,7 +138,7 @@ int plic_irq_complete(uint32_t source) return 0; } -void plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void* ctx) +void plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void *ctx) { /* Read core id */ unsigned long core_id = current_coreid(); diff --git a/lib/drivers/sha256.c b/lib/drivers/sha256.c index de6368e1..b3b8ede2 100644 --- a/lib/drivers/sha256.c +++ b/lib/drivers/sha256.c @@ -58,7 +58,7 @@ void sha256_init(sha256_context_t *context, size_t buf_len) void sha256_update(sha256_context_t *context, const void *data_buf, size_t buf_len) { - const uint8_t* data = data_buf; + const uint8_t *data = data_buf; size_t buffer_bytes_left; size_t bytes_to_copy; uint32_t i; diff --git a/lib/drivers/spi.c b/lib/drivers/spi.c index 260e37f1..4d7bfb17 100644 --- a/lib/drivers/spi.c +++ b/lib/drivers/spi.c @@ -221,7 +221,7 @@ void spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_nu DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len + tx_len); spi_handle->ser = 1U << chip_select; dmac_wait_done(channel_num); - free((void*)buf); + free((void *)buf); while ((spi_handle->sr & 0x05) != 0x04) ; @@ -263,7 +263,7 @@ void spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_ DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, tx_len); spi_handle->ser = 1U << chip_select; dmac_wait_done(channel_num); - free((void*)buf); + free((void *)buf); while ((spi_handle->sr & 0x05) != 0x04) ; @@ -459,7 +459,7 @@ void spi_send_data_multiple_dma(dmac_channel_number_t channel_num, spi_device_nu DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len + tx_len); spi_handle->ser = 1U << chip_select; dmac_wait_done(channel_num); - free((void*)buf); + free((void *)buf); while ((spi_handle->sr & 0x05) != 0x04) ; diff --git a/lib/drivers/utils.c b/lib/drivers/utils.c index 005ef743..d21a3b37 100644 --- a/lib/drivers/utils.c +++ b/lib/drivers/utils.c @@ -16,28 +16,28 @@ #include "encoding.h" #include "utils.h" -void set_bit(volatile uint32_t* bits, uint32_t mask, uint32_t value) +void set_bit(volatile uint32_t *bits, uint32_t mask, uint32_t value) { uint32_t org = (*bits) & ~mask; *bits = org | (value & mask); } -void set_bit_offset(volatile uint32_t* bits, uint32_t mask, size_t offset, uint32_t value) +void set_bit_offset(volatile uint32_t *bits, uint32_t mask, size_t offset, uint32_t value) { set_bit(bits, mask << offset, value << offset); } -void set_gpio_bit(volatile uint32_t* bits, size_t offset, uint32_t value) +void set_gpio_bit(volatile uint32_t *bits, size_t offset, uint32_t value) { set_bit_offset(bits, 1, offset, value); } -uint32_t get_bit(volatile uint32_t* bits, uint32_t mask, size_t offset) +uint32_t get_bit(volatile uint32_t *bits, uint32_t mask, size_t offset) { return ((*bits) & (mask << offset)) >> offset; } -uint32_t get_gpio_bit(volatile uint32_t* bits, size_t offset) +uint32_t get_gpio_bit(volatile uint32_t *bits, size_t offset) { return get_bit(bits, 1, offset); } From bb4109dc27d28f6e55e7b2c7282d4839a877f589 Mon Sep 17 00:00:00 2001 From: jiangxiangbing Date: Mon, 8 Oct 2018 20:58:57 +0800 Subject: [PATCH 41/58] update fft aes sha256 --- cmake/compile-flags.cmake | 2 +- lib/drivers/aes.c | 123 ++++++++++++----------------------- lib/drivers/fft.c | 12 ++-- lib/drivers/include/aes.h | 65 +++++++++--------- lib/drivers/include/fft.h | 59 ++++++++++++----- lib/drivers/include/sha256.h | 60 +++++++++++++---- lib/drivers/sha256.c | 61 +++++++++-------- 7 files changed, 204 insertions(+), 178 deletions(-) diff --git a/cmake/compile-flags.cmake b/cmake/compile-flags.cmake index e0aa6204..76f1fead 100644 --- a/cmake/compile-flags.cmake +++ b/cmake/compile-flags.cmake @@ -18,7 +18,7 @@ add_compile_flags(BOTH -ffunction-sections -fdata-sections -fstrict-volatile-bitfields - -fno-zero-initialized-in-bss + -fno-zero-initialized-in-bss -Os -ggdb ) diff --git a/lib/drivers/aes.c b/lib/drivers/aes.c index dfcaacca..3383c81e 100644 --- a/lib/drivers/aes.c +++ b/lib/drivers/aes.c @@ -12,18 +12,20 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#include -#include +#include +#include "sysctl.h" +#include "aes.h" +#include "utils.h" -volatile aes_t* const aes = (volatile aes_t*)AES_BASE_ADDR; +volatile aes_t *const aes = (volatile aes_t *)AES_BASE_ADDR; -void aes_clk_init() +static void aes_clk_init() { sysctl_clock_enable(SYSCTL_CLOCK_AES); sysctl_reset(SYSCTL_RESET_AES); } -static void aes_write_add(uint32_t aad_data) +static void aes_write_aad(uint32_t aad_data) { aes->aes_aad_data = aad_data; } @@ -121,9 +123,15 @@ static uint32_t gcm_check_tag(uint32_t *gcm_tag) } static void aes_init(uint8_t *input_key, size_t input_key_len, uint8_t *iv, - size_t iv_len, uint8_t *gcm_add, aes_cipher_mode_t cipher_mode, - aes_encrypt_sel_t encrypt_sel, size_t gcm_add_len, size_t input_data_len) + size_t iv_len, uint8_t *gcm_aad, aes_cipher_mode_t cipher_mode, + aes_encrypt_sel_t encrypt_sel, size_t gcm_aad_len, size_t input_data_len) { + configASSERT(input_key_len == AES_128 || input_key_len == AES_192 || input_key_len == AES_256); + if (cipher_mode == AES_CBC) + configASSERT(iv_len == 16); + if (cipher_mode == AES_GCM) + configASSERT(iv_len == 12); + size_t remainder, uint32_num, uint8_num, i; uint32_t uint32_data; uint8_t uint8_data[4] = {0}; @@ -136,102 +144,57 @@ static void aes_init(uint8_t *input_key, size_t input_key_len, uint8_t *iv, for (i = 0; i < uint32_num; i++) { if (i < 4) - aes->aes_key[i] = *((uint32_t*)(&input_key[input_key_len - (4 * i) - 4])); - else - aes->aes_key_ext[i - 4] = *((uint32_t*)(&input_key[input_key_len - (4 * i) - 4])); - } - remainder = input_key_len % 4; - if (remainder) - { - switch (remainder) - { - case 1: - uint8_data[0] = input_key[0]; - break; - case 2: - uint8_data[0] = input_key[0]; - uint8_data[1] = input_key[1]; - break; - case 3: - uint8_data[0] = input_key[0]; - uint8_data[1] = input_key[1]; - uint8_data[2] = input_key[2]; - break; - default: - break; - } - if (uint32_num < 4) - aes->aes_key[uint32_num] = *((uint32_t*)(&uint8_data[0])); + aes->aes_key[i] = *((uint32_t *)(&input_key[input_key_len - (4 * i) - 4])); else - aes->aes_key_ext[uint32_num - 4] = *((uint32_t*)(&uint8_data[0])); + aes->aes_key_ext[i - 4] = *((uint32_t *)(&input_key[input_key_len - (4 * i) - 4])); } + uint32_num = iv_len / 4; for (i = 0; i < uint32_num; i++) - aes->aes_iv[i] = *((uint32_t*)(&iv[iv_len - (4 * i) - 4])); - remainder = iv_len % 4; - if (remainder) - { - switch (remainder) - { - case 1: - uint8_data[0] = iv[0]; - break; - case 2: - uint8_data[0] = iv[0]; - uint8_data[1] = iv[1]; - break; - case 3: - uint8_data[0] = iv[0]; - uint8_data[1] = iv[1]; - uint8_data[2] = iv[2]; - break; - default: - break; - } - aes->aes_iv[uint32_num] = *((uint32_t*)(&uint8_data[0])); - } - aes->mode_ctl.kmode = input_key_len / 8 - 2; /* 00:AES_128 01:AES_192 10:AES_256 11:RESERVED */ + aes->aes_iv[i] = *((uint32_t *)(&iv[iv_len - (4 * i) - 4])); + + aes->mode_ctl.kmode = input_key_len / 8 - 2; /* b'00:AES_128 b'01:AES_192 b'10:AES_256 b'11:RESERVED */ aes->mode_ctl.cipher_mode = cipher_mode; aes->encrypt_sel = encrypt_sel; - aes->gb_aad_end_adr = gcm_add_len - 1; - aes->gb_pc_end_adr = padding_len - 1; + aes->gb_aad_num = gcm_aad_len - 1; + aes->gb_pc_num = padding_len - 1; aes->gb_aes_en |= 1; if (cipher_mode == AES_GCM) { - uint32_num = gcm_add_len / 4; + uint32_num = gcm_aad_len / 4; for (i = 0; i < uint32_num; i++) { - uint32_data = *((uint32_t*)(&gcm_add[i * 4])); + uint32_data = *((uint32_t *)(&gcm_aad[i * 4])); while (!aes_get_data_in_flag()) ; - aes_write_add(uint32_data); + aes_write_aad(uint32_data); } uint8_num = 4 * uint32_num; - remainder = gcm_add_len % 4; + remainder = gcm_aad_len % 4; if (remainder) { switch (remainder) { case 1: - uint8_data[0] = gcm_add[uint8_num]; + uint8_data[0] = gcm_aad[uint8_num]; break; case 2: - uint8_data[0] = gcm_add[uint8_num]; - uint8_data[1] = gcm_add[uint8_num + 1]; + uint8_data[0] = gcm_aad[uint8_num]; + uint8_data[1] = gcm_aad[uint8_num + 1]; break; case 3: - uint8_data[0] = gcm_add[uint8_num]; - uint8_data[1] = gcm_add[uint8_num + 1]; - uint8_data[2] = gcm_add[uint8_num + 2]; + uint8_data[0] = gcm_aad[uint8_num]; + uint8_data[1] = gcm_aad[uint8_num + 1]; + uint8_data[2] = gcm_aad[uint8_num + 2]; break; default: break; } - uint32_data = *((uint32_t*)(&uint8_data[0])); + uint32_data = *((uint32_t *)(&uint8_data[0])); while (!aes_get_data_in_flag()) ; - aes_write_add(uint32_data); + aes_write_aad(uint32_data); } } } @@ -246,7 +209,7 @@ static void process_less_80_bytes(uint8_t *input_data, uint8_t *output_data, siz uint32_num = input_data_len / 4; for (i = 0; i < uint32_num; i++) { - uint32_data = *((uint32_t*)(&input_data[i * 4])); + uint32_data = *((uint32_t *)(&input_data[i * 4])); while (!aes_get_data_in_flag()) ; aes_write_text(uint32_data); @@ -272,7 +235,7 @@ static void process_less_80_bytes(uint8_t *input_data, uint8_t *output_data, siz default: break; } - uint32_data = *((uint32_t*)(&uint8_data[0])); + uint32_data = *((uint32_t *)(&uint8_data[0])); while (!aes_get_data_in_flag()) ; aes_write_text(uint32_data); @@ -292,13 +255,13 @@ static void process_less_80_bytes(uint8_t *input_data, uint8_t *output_data, siz { while (!aes_get_data_out_flag()) ; - *((uint32_t*)(&output_data[i * 4])) = aes_read_out_data(); + *((uint32_t *)(&output_data[i * 4])) = aes_read_out_data(); } if ((cipher_mode == AES_GCM) && (remainder)) { while (!aes_get_data_out_flag()) ; - *((uint32_t*)(&uint8_data[0])) = aes_read_out_data(); + *((uint32_t *)(&uint8_data[0])) = aes_read_out_data(); switch (remainder) { case 1: @@ -341,8 +304,8 @@ void aes_hard_decrypt(aes_param_t *param) { padding_len = ((padding_len + 15) / 16) * 16; } - aes_init(param->input_key, param->input_key_len, param->iv, param->iv_len, param->gcm_add, - param->cipher_mode, AES_HARD_DECRYPTION, param->gcm_add_len, param->input_data_len); + aes_init(param->input_key, param->input_key_len, param->iv, param->iv_len, param->gcm_aad, + param->cipher_mode, AES_HARD_DECRYPTION, param->gcm_aad_len, param->input_data_len); aes_process(param->input_data, param->output_data, padding_len, param->cipher_mode); if (param->cipher_mode == AES_GCM) { @@ -353,8 +316,8 @@ void aes_hard_decrypt(aes_param_t *param) void aes_hard_encrypt(aes_param_t *param) { - aes_init(param->input_key, param->input_key_len, param->iv, param->iv_len, param->gcm_add, - param->cipher_mode, AES_HARD_ENCRYPTION, param->gcm_add_len, param->input_data_len); + aes_init(param->input_key, param->input_key_len, param->iv, param->iv_len, param->gcm_aad, + param->cipher_mode, AES_HARD_ENCRYPTION, param->gcm_aad_len, param->input_data_len); aes_process(param->input_data, param->output_data, param->input_data_len, param->cipher_mode); if (param->cipher_mode == AES_GCM) { diff --git a/lib/drivers/fft.c b/lib/drivers/fft.c index 8b6723d6..bad33496 100644 --- a/lib/drivers/fft.c +++ b/lib/drivers/fft.c @@ -13,17 +13,17 @@ * limitations under the License. */ #include -#include -#include -#include -#include +#include "dmac.h" +#include "utils.h" +#include "sysctl.h" +#include "fft.h" static volatile fft_t *const fft = (volatile fft_t *)FFT_BASE_ADDR; static void fft_init(uint8_t point, uint8_t mode, uint16_t shift, uint8_t is_dma, uint8_t input_mode, uint8_t data_mode) { - fft->fft_ctrl.fft_point = point; /* 0:512, 1:256, 2:128, 3:64 */ - fft->fft_ctrl.fft_mode = mode; /* 1: fft, 0: ifft */ + fft->fft_ctrl.fft_point = point; + fft->fft_ctrl.fft_mode = mode; fft->fft_ctrl.fft_shift = shift; fft->fft_ctrl.dma_send = is_dma; fft->fft_ctrl.fft_enable = 1; diff --git a/lib/drivers/include/aes.h b/lib/drivers/include/aes.h index 0740a040..ea4cb469 100644 --- a/lib/drivers/include/aes.h +++ b/lib/drivers/include/aes.h @@ -44,13 +44,17 @@ typedef enum _aes_encrypt_sel typedef struct _aes_mode_ctl { - /* set the first bit and second bit 00:ecb; 01:cbc,10：aes_gcm */ + /* [2:0]:000:ecb; 001:cbc,010:gcm */ uint32_t cipher_mode : 3; - /* [4:3]:00:128; 01:192; 10:256;11:reserved*/ + /* [4:3]:00:aes-128; 01:aes-192; 10:aes-256;11:reserved*/ uint32_t kmode : 2; - uint32_t endian : 6; - uint32_t stream_mode : 3; - uint32_t reserved : 18; + /* [6:5]:input key order 1：little endian; 0: big endian */ + uint32_t key_order : 2; + /* [8:7]:input data order 1：little endian; 0: big endian */ + uint32_t input_order : 2; + /* [10:9]:output data order 1：little endian; 0: big endian */ + uint32_t output_order : 2; + uint32_t reserved : 21; } __attribute__((packed, aligned(4))) aes_mode_ctl_t; /** @@ -58,49 +62,50 @@ typedef struct _aes_mode_ctl */ typedef struct _aes { + /* (0x00) customer key.1st~4th byte key */ uint32_t aes_key[4]; - /* 0: encrption ; 1: dencrption */ + /* (0x10) 0: encryption; 1: decryption */ uint32_t encrypt_sel; - /** - * [1:0], Set the first bit and second bit 00:ecb; 01:cbc; - * 10,11：aes_gcm - */ + /* (0x14) aes mode reg */ aes_mode_ctl_t mode_ctl; + /* (0x18) Initialisation Vector */ uint32_t aes_iv[4]; - /* aes interrupt enable */ + /* (0x28) input data endian;1:little endian; 0:big endian */ uint32_t aes_endian; - /* aes interrupt flag */ + /* (0x2c) calculate status. 1:finish; 0:not finish */ uint32_t aes_finish; - /* gcm add data begin address */ + /* (0x30) aes out data to dma 0:cpu 1:dma */ uint32_t dma_sel; - /* gcm add data end address */ - uint32_t gb_aad_end_adr; - /* gcm plantext/ciphter text data begin address */ - uint32_t gb_pc_ini_adr; - /* gcm plantext/ciphter text data end address */ - uint32_t gb_pc_end_adr; - /* gcm plantext/ciphter text data */ + /* (0x34) gcm Additional authenticated data number */ + uint32_t gb_aad_num; + uint32_t reserved; + /* (0x3c) aes plantext/ciphter text input data number */ + uint32_t gb_pc_num; + /* (0x40) aes plantext/ciphter text input data */ uint32_t aes_text_data; - /* AAD data */ + /* (0x44) Additional authenticated data */ uint32_t aes_aad_data; /** - * [1:0],00:check not finish; 01: check fail; 10: check success;11: - * reversed + * (0x48) [1:0],b'00:check not finish; b'01:check fail; b'10:check success; + * b'11:reversed */ uint32_t tag_chk; - /* data can input flag 1: data can input; 0 : data cannot input */ + /* (0x4c) data can input flag. 1: data can input; 0 : data cannot input */ uint32_t data_in_flag; - /* gcm input tag for compare with the calculate tag */ + /* (0x50) gcm input tag for compare with the calculate tag */ uint32_t gcm_in_tag[4]; - /* gcm plantext/ciphter text data */ + /* (0x60) aes plantext/ciphter text output data */ uint32_t aes_out_data; + /* (0x64) aes module enable */ uint32_t gb_aes_en; - /* data can output flag 1: data ready 0: data not ready */ + /* (0x68) data can output flag 1: data ready 0: data not ready */ uint32_t data_out_flag; - /* allow tag input when use GCM */ + /* (0x6c) allow tag input when use gcm */ uint32_t tag_in_flag; + /* (0x70) clear tag_chk */ uint32_t tag_clear; uint32_t gcm_out_tag[4]; + /* (0x84) customer key for aes-192 aes-256.5th~8th byte key */ uint32_t aes_key_ext[4]; } __attribute__((packed, aligned(4))) aes_t; @@ -112,8 +117,8 @@ typedef struct _aes_param size_t input_key_len; uint8_t *iv; uint8_t iv_len; - uint8_t *gcm_add; - size_t gcm_add_len; + uint8_t *gcm_aad; + size_t gcm_aad_len; aes_cipher_mode_t cipher_mode; uint8_t *output_data; uint8_t *gcm_tag; diff --git a/lib/drivers/include/fft.h b/lib/drivers/include/fft.h index 07502495..e179503b 100644 --- a/lib/drivers/include/fft.h +++ b/lib/drivers/include/fft.h @@ -68,16 +68,15 @@ typedef enum _fft_direction * */ - /** - * @brief input data fifo + * @brief The calculation data is input through this register * * No. 0 Register (0x00) */ -typedef struct _fft_fft_input_fifo +typedef struct _fft_input_fifo { uint64_t fft_input_fifo : 64; -} __attribute__((packed, aligned(8))) fft_fft_input_fifo_t; +} __attribute__((packed, aligned(8))) fft_input_fifo_t; /** * @brief fft ctrl reg @@ -86,12 +85,25 @@ typedef struct _fft_fft_input_fifo */ typedef struct _fft_fft_ctrl { + /** + *FFT calculation data length: + *b'000:512 point; b'001:256 point; b'010:128 point; b'011:64 point; + */ uint64_t fft_point : 3; + /* FFT mode: b'0:FFT b'1:IFFT */ uint64_t fft_mode : 1; + /* Corresponding to the nine layer butterfly shift operation, 0x0: does not shift; 0x1: shift 1st layer. ...*/ uint64_t fft_shift : 9; + /* FFT enable: b'0:disable b'1:enable */ uint64_t fft_enable : 1; + /* FFT DMA enable: b'0:disable b'1:enable */ uint64_t dma_send : 1; + /** + *Input data arrangement: b'00:RIRI; b'01:only real part exist, RRRR; + *b'10:First input the real part and then input the imaginary part. + */ uint64_t fft_input_mode : 2; + /* Effective width of input data. b'0:64bit effective; b'1:32bit effective */ uint64_t fft_data_mode : 1; uint64_t reserved : 46; } __attribute__((packed, aligned(8))) fft_fft_ctrl_t; @@ -103,8 +115,11 @@ typedef struct _fft_fft_ctrl */ typedef struct _fft_fifo_ctrl { + /* Response memory initialization flag.b'1:initialization */ uint64_t resp_fifo_flush_n : 1; + /* Command memory initialization flag.b'1:initialization */ uint64_t cmd_fifo_flush_n : 1; + /* Output interface memory initialization flag.b'1:initialization */ uint64_t gs_fifo_flush_n : 1; uint64_t reserved : 61; } __attribute__((packed, aligned(8))) fft_fifo_ctrl_t; @@ -116,6 +131,11 @@ typedef struct _fft_fifo_ctrl */ typedef struct _fft_intr_mask { + /** + *FFT return status set. + *b'0:FFT returns to the state after completion. + *b'1:FFT does not return to the state after completion + */ uint64_t fft_done_mask : 1; uint64_t reserved : 63; } __attribute__((packed, aligned(8))) fft_intr_mask_t; @@ -127,6 +147,7 @@ typedef struct _fft_intr_mask */ typedef struct _fft_intr_clear { + /* The interrupt state clears. b'1:clear current interrupt request */ uint64_t fft_done_clear : 1; uint64_t reserved1 : 63; } __attribute__((packed, aligned(8))) fft_intr_clear_t; @@ -136,32 +157,36 @@ typedef struct _fft_intr_clear * * No. 5 Register (0x28) */ -typedef struct _fft_fft_status +typedef struct _fft_status { + /* FFT calculation state.b'0:not completed; b'1:completed */ uint64_t fft_done_status : 1; uint64_t reserved1 : 63; -} __attribute__((packed, aligned(8))) fft_fft_status_t; +} __attribute__((packed, aligned(8))) fft_status_t; /** - * @brief fft_status_raw + * @brief fft status raw * * No. 6 Register (0x30) */ -typedef struct _fft_fft_status_raw +typedef struct _fft_status_raw { + /* FFT calculation state. b'1:done */ uint64_t fft_done_status_raw : 1; - uint64_t reserved : 63; -} __attribute__((packed, aligned(8))) fft_fft_status_raw_t; + /* FFT calculation state. b'1:working */ + uint64_t fft_work_status_raw : 1; + uint64_t reserved : 62; +} __attribute__((packed, aligned(8))) fft_status_raw_t; /** - * @brief fft_output_fifo + * @brief Output of FFT calculation data through this register * * No. 7 Register (0x38) */ -typedef struct _fft_fft_output_fifo +typedef struct _fft_output_fifo { uint64_t fft_output_fifo : 64; -} __attribute__((packed, aligned(8))) fft_fft_output_fifo_t; +} __attribute__((packed, aligned(8))) fft_output_fifo_t; /** * @brief Fast Fourier transform (FFT) algorithm accelerator object @@ -177,7 +202,7 @@ typedef struct _fft_fft_output_fifo typedef struct _fft { /* No. 0 (0x00): input data fifo */ - fft_fft_input_fifo_t fft_input_fifo; + fft_input_fifo_t fft_input_fifo; /* No. 1 (0x08): fft ctrl reg */ fft_fft_ctrl_t fft_ctrl; /* No. 2 (0x10): fifo ctrl */ @@ -187,11 +212,11 @@ typedef struct _fft /* No. 4 (0x20): interrupt clear */ fft_intr_clear_t intr_clear; /* No. 5 (0x28): fft status reg */ - fft_fft_status_t fft_status; + fft_status_t fft_status; /* No. 6 (0x30): fft_status_raw */ - fft_fft_status_raw_t fft_status_raw; + fft_status_raw_t fft_status_raw; /* No. 7 (0x38): fft_output_fifo */ - fft_fft_output_fifo_t fft_output_fifo; + fft_output_fifo_t fft_output_fifo; } __attribute__((packed, aligned(8))) fft_t; diff --git a/lib/drivers/include/sha256.h b/lib/drivers/include/sha256.h index 1d56c92c..19047f6d 100644 --- a/lib/drivers/include/sha256.h +++ b/lib/drivers/include/sha256.h @@ -21,28 +21,62 @@ extern "C" { #endif -#define ENABLE_SHA 1 -#define SHA256_BIG_ENDIAN (0x1 << 16) +#define ENABLE_SHA (0x1) +#define SHA256_BIG_ENDIAN (0x1) #define SHA256_HASH_LEN 32 #define SHA256_HASH_WORDS 8 -#define SHA256_BLOCK_LEN 64L +#define SHA256_BLOCK_LEN 64LL + +typedef struct _sha_num_reg +{ + /* The total amount of data calculated by SHA256 is set by this register, and the smallest unit is 512bit. */ + uint32_t sha_data_cnt : 16; + /* currently calculated block number. 512bit=1block*/ + uint32_t sha_data_num : 16; +} __attribute__((packed, aligned(4))) sha_num_reg_t; + +typedef struct _sha_function_reg_0 +{ + /* write:SHA256 enable register. read:Calculation completed flag */ + uint32_t sha_en : 1; + uint32_t reserved00 : 7; + /* SHA256 calculation overflow flag */ + uint32_t sha_overflow : 1; + uint32_t reserved01 : 7; + /* Endian setting; b'0:little endian b'1:big endian */ + uint32_t sha_endian : 1; + uint32_t reserved02 : 15; +} __attribute__((packed, aligned(4))) sha_function_reg_0_t; + +typedef struct _sha_function_reg_1 +{ + /* Sha and DMA handshake signals enable.b'1:enable;b'0:disable */ + uint32_t dma_en : 1; + uint32_t reserved10 : 7; + /* b'1:sha256 fifo is full; b'0:not full */ + uint32_t fifo_in_full : 1; + uint32_t reserved11 : 23; +} __attribute__((packed, aligned(4))) sha_function_reg_1_t; typedef struct _sha256 { + /* Calculated sha256 return value. */ uint32_t sha_result[8]; + /* SHA256 input data from this register. */ uint32_t sha_data_in1; - uint32_t sha_data_in2; - uint32_t sha_data_num; - uint32_t sha_status; - uint32_t reserved0; - uint32_t sha_input_ctrl; + uint32_t reselved0; + sha_num_reg_t sha_num_reg; + /* */ + sha_function_reg_0_t sha_function_reg_0; + uint32_t reserved1; + sha_function_reg_1_t sha_function_reg_1; } __attribute__((packed, aligned(4))) sha256_t; typedef struct _sha256_context { - size_t total_length; - size_t buffer_length; + size_t total_len; + size_t buffer_len; union { uint32_t words[16]; @@ -56,7 +90,7 @@ typedef struct _sha256_context * @param[in] context SHA256 context object * */ -void sha256_init(sha256_context_t *context, size_t buf_len); +void sha256_init(sha256_context_t *context, size_t input_len); /** * @brief Called repeatedly with chunks of the message to be hashed @@ -66,7 +100,7 @@ void sha256_init(sha256_context_t *context, size_t buf_len); * @param[in] buf_len length of data chunk * */ -void sha256_update(sha256_context_t *context, const void *data_buf, size_t buf_len); +void sha256_update(sha256_context_t *context, const void *input, size_t input_len); /** * @brief Finish SHA256 hash process, output the result. @@ -85,7 +119,7 @@ void sha256_final(sha256_context_t *context, uint8_t *output); * @param[out] output Output buffer * */ -void sha256_hard_calculate(const uint8_t *data, size_t data_len, uint8_t *output); +void sha256_hard_calculate(const uint8_t *input, size_t input_len, uint8_t *output); #ifdef __cplusplus } diff --git a/lib/drivers/sha256.c b/lib/drivers/sha256.c index b3b8ede2..974c3ade 100644 --- a/lib/drivers/sha256.c +++ b/lib/drivers/sha256.c @@ -42,47 +42,46 @@ static inline uint64_t byteswap64(uint64_t x) return ((uint64_t)BYTESWAP(b) << 32) | (uint64_t)BYTESWAP(a); } -void sha256_init(sha256_context_t *context, size_t buf_len) +void sha256_init(sha256_context_t *context, size_t input_len) { sysctl_clock_enable(SYSCTL_CLOCK_SHA); sysctl_reset(SYSCTL_RESET_SHA); - sha256->sha_data_num = (uint32_t)((buf_len + SHA256_BLOCK_LEN + 8) / SHA256_BLOCK_LEN); - - sha256->sha_input_ctrl &= (~0x1); - sha256->sha_status |= SHA256_BIG_ENDIAN; - sha256->sha_status |= ENABLE_SHA; - context->total_length = 0LL; - context->buffer_length = 0L; + sha256->sha_num_reg.sha_data_cnt = (uint32_t)((input_len + SHA256_BLOCK_LEN + 8) / SHA256_BLOCK_LEN); + sha256->sha_function_reg_1.dma_en = 0x0; + sha256->sha_function_reg_0.sha_endian = SHA256_BIG_ENDIAN; + sha256->sha_function_reg_0.sha_en = ENABLE_SHA; + context->total_len = 0LL; + context->buffer_len = 0LL; } -void sha256_update(sha256_context_t *context, const void *data_buf, size_t buf_len) +void sha256_update(sha256_context_t *context, const void *input, size_t input_len) { - const uint8_t *data = data_buf; + const uint8_t *data = input; size_t buffer_bytes_left; size_t bytes_to_copy; uint32_t i; - while (buf_len) + while (input_len) { - buffer_bytes_left = SHA256_BLOCK_LEN - context->buffer_length; + buffer_bytes_left = SHA256_BLOCK_LEN - context->buffer_len; bytes_to_copy = buffer_bytes_left; - if (bytes_to_copy > buf_len) - bytes_to_copy = buf_len; - memcpy(&context->buffer.bytes[context->buffer_length], data, bytes_to_copy); - context->total_length += bytes_to_copy * 8; - context->buffer_length += bytes_to_copy; + if (bytes_to_copy > input_len) + bytes_to_copy = input_len; + memcpy(&context->buffer.bytes[context->buffer_len], data, bytes_to_copy); + context->total_len += bytes_to_copy * 8LL; + context->buffer_len += bytes_to_copy; data += bytes_to_copy; - buf_len -= bytes_to_copy; - if (context->buffer_length == SHA256_BLOCK_LEN) + input_len -= bytes_to_copy; + if (context->buffer_len == SHA256_BLOCK_LEN) { for (i = 0; i < 16; i++) { - while (sha256->sha_input_ctrl & (1 << 8)) + while (sha256->sha_function_reg_1.fifo_in_full) ; sha256->sha_data_in1 = context->buffer.words[i]; } - context->buffer_length = 0L; + context->buffer_len = 0LL; } } } @@ -93,29 +92,29 @@ void sha256_final(sha256_context_t *context, uint8_t *output) size_t length_pad; uint32_t i; - bytes_to_pad = 120 - context->buffer_length; - if (bytes_to_pad > 64) - bytes_to_pad -= 64; - length_pad = BYTESWAP64(context->total_length); + bytes_to_pad = 120LL - context->buffer_len; + if (bytes_to_pad > 64LL) + bytes_to_pad -= 64LL; + length_pad = BYTESWAP64(context->total_len); sha256_update(context, padding, bytes_to_pad); - sha256_update(context, &length_pad, 8); - while (!(sha256->sha_status & 0x01)) + sha256_update(context, &length_pad, 8LL); + while (!(sha256->sha_function_reg_0.sha_en)) ; if (output) { for (i = 0; i < SHA256_HASH_WORDS; i++) { - *((uint32_t*)output) = sha256->sha_result[SHA256_HASH_WORDS - i - 1]; + *((uint32_t *)output) = sha256->sha_result[SHA256_HASH_WORDS - i - 1]; output += 4; } } } -void sha256_hard_calculate(const uint8_t *data, size_t data_len, uint8_t *output) +void sha256_hard_calculate(const uint8_t *input, size_t input_len, uint8_t *output) { sha256_context_t sha; - sha256_init(&sha, data_len); - sha256_update(&sha, data, data_len); + sha256_init(&sha, input_len); + sha256_update(&sha, input, input_len); sha256_final(&sha, output); } From fbba8ca2c5aae1c7d76766ea9d5dd0094d8a5ec4 Mon Sep 17 00:00:00 2001 From: jiangxiangbing Date: Mon, 8 Oct 2018 21:35:13 +0800 Subject: [PATCH 42/58] fix sha256 LL --- lib/drivers/include/sha256.h | 2 +- lib/drivers/sha256.c | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/lib/drivers/include/sha256.h b/lib/drivers/include/sha256.h index 19047f6d..df6e5670 100644 --- a/lib/drivers/include/sha256.h +++ b/lib/drivers/include/sha256.h @@ -26,7 +26,7 @@ extern "C" { #define SHA256_HASH_LEN 32 #define SHA256_HASH_WORDS 8 -#define SHA256_BLOCK_LEN 64LL +#define SHA256_BLOCK_LEN 64L typedef struct _sha_num_reg { diff --git a/lib/drivers/sha256.c b/lib/drivers/sha256.c index 974c3ade..362149b2 100644 --- a/lib/drivers/sha256.c +++ b/lib/drivers/sha256.c @@ -51,8 +51,8 @@ void sha256_init(sha256_context_t *context, size_t input_len) sha256->sha_function_reg_1.dma_en = 0x0; sha256->sha_function_reg_0.sha_endian = SHA256_BIG_ENDIAN; sha256->sha_function_reg_0.sha_en = ENABLE_SHA; - context->total_len = 0LL; - context->buffer_len = 0LL; + context->total_len = 0L; + context->buffer_len = 0L; } void sha256_update(sha256_context_t *context, const void *input, size_t input_len) @@ -69,7 +69,7 @@ void sha256_update(sha256_context_t *context, const void *input, size_t input_le if (bytes_to_copy > input_len) bytes_to_copy = input_len; memcpy(&context->buffer.bytes[context->buffer_len], data, bytes_to_copy); - context->total_len += bytes_to_copy * 8LL; + context->total_len += bytes_to_copy * 8L; context->buffer_len += bytes_to_copy; data += bytes_to_copy; input_len -= bytes_to_copy; @@ -81,7 +81,7 @@ void sha256_update(sha256_context_t *context, const void *input, size_t input_le ; sha256->sha_data_in1 = context->buffer.words[i]; } - context->buffer_len = 0LL; + context->buffer_len = 0L; } } } @@ -92,12 +92,12 @@ void sha256_final(sha256_context_t *context, uint8_t *output) size_t length_pad; uint32_t i; - bytes_to_pad = 120LL - context->buffer_len; - if (bytes_to_pad > 64LL) - bytes_to_pad -= 64LL; + bytes_to_pad = 120L - context->buffer_len; + if (bytes_to_pad > 64L) + bytes_to_pad -= 64L; length_pad = BYTESWAP64(context->total_len); sha256_update(context, padding, bytes_to_pad); - sha256_update(context, &length_pad, 8LL); + sha256_update(context, &length_pad, 8L); while (!(sha256->sha_function_reg_0.sha_en)) ; if (output) From a9fbd46d2875dcc172e1832328d00c1930e5919f Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Tue, 9 Oct 2018 10:31:23 +0800 Subject: [PATCH 43/58] Modify sysctl func --- lib/bsp/entry_user.c | 2 - lib/drivers/clint.c | 2 +- lib/drivers/dvp.c | 2 +- lib/drivers/include/sysctl.h | 121 ++++++++----------- lib/drivers/rtc.c | 2 +- lib/drivers/sysctl.c | 206 ++++++++++++++------------------- lib/firmware/include/nt35310.h | 6 + lib/firmware/nt35310.c | 8 +- 8 files changed, 146 insertions(+), 203 deletions(-) diff --git a/lib/bsp/entry_user.c b/lib/bsp/entry_user.c index b56b164f..2b670eac 100644 --- a/lib/bsp/entry_user.c +++ b/lib/bsp/entry_user.c @@ -61,8 +61,6 @@ void _init_bsp(int core_id, int number_of_cores) { /* Initialize bss data to 0 */ init_bss(); - /* Init FPIOA */ -// fpioa_init(); /* Init UART */ uarths_init(); /* Register finalization function */ diff --git a/lib/drivers/clint.c b/lib/drivers/clint.c index a1fdc71b..4b59a428 100644 --- a/lib/drivers/clint.c +++ b/lib/drivers/clint.c @@ -60,7 +60,7 @@ int clint_timer_stop(void) uint64_t clint_timer_get_freq(void) { /* The clock is divided by CLINT_CLOCK_DIV */ - return sysctl_get_freq() / CLINT_CLOCK_DIV; + return sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV; } int clint_timer_start(uint64_t interval, int single_shot) diff --git a/lib/drivers/dvp.c b/lib/drivers/dvp.c index 7a901ec1..f1b66a25 100644 --- a/lib/drivers/dvp.c +++ b/lib/drivers/dvp.c @@ -114,7 +114,7 @@ static void dvp_io_init(void) fpioa_set_function(21, FUNC_CMOS_PCLK); fpioa_set_function(22, FUNC_SCCB_SCLK); fpioa_set_function(23, FUNC_SCCB_SDA); - sysctl_spi0_dvp_data_set(1); + sysctl_set_spi0_dvp_data(1); } static void dvp_reset(void) diff --git a/lib/drivers/include/sysctl.h b/lib/drivers/include/sysctl.h index 54b31e8e..1f33ca6c 100644 --- a/lib/drivers/include/sysctl.h +++ b/lib/drivers/include/sysctl.h @@ -176,6 +176,7 @@ typedef enum _sysctl_clock_t SYSCTL_CLOCK_RTC, SYSCTL_CLOCK_ACLK = 40, SYSCTL_CLOCK_HCLK, + SYSCTL_CLOCK_IN0, SYSCTL_CLOCK_MAX } sysctl_clock_t; @@ -235,7 +236,7 @@ typedef enum _sysctl_threshold_t /** * @brief System controller reset control id */ -typedef enum _sysctl_reset_e +typedef enum _sysctl_reset_t { SYSCTL_RESET_SOC, SYSCTL_RESET_ROM, @@ -269,10 +270,26 @@ typedef enum _sysctl_reset_e SYSCTL_RESET_MAX = 31 } sysctl_reset_t; +typedef enum _sysctl_power_bank +{ + SYSCTL_POWER_BANK0, + SYSCTL_POWER_BANK1, + SYSCTL_POWER_BANK2, + SYSCTL_POWER_BANK3, + SYSCTL_POWER_BANK4, + SYSCTL_POWER_BANK5, + SYSCTL_POWER_BANK6, + SYSCTL_POWER_BANK7, + SYSCTL_POWER_BANK_MAX, +} sysctl_power_mode_t; + +/** + * @brief System controller reset control id + */ typedef enum _io_power_mode { - POWER_V33, - POWER_V18 + SYSCTL_POWER_V33, + SYSCTL_POWER_V18 } sysctl_io_power_mode_t; /** @@ -739,7 +756,6 @@ typedef struct _sysctl_power_sel uint32_t reserved : 24; } __attribute__((packed, aligned(4))) sysctl_power_sel_t; - /** * @brief System controller object * @@ -819,6 +835,25 @@ typedef struct _sysctl uint32_t resv31; } __attribute__((packed, aligned(4))) sysctl_t; +/** + * @brief Abstruct PLL struct + */ +typedef struct _sysctl_general_pll +{ + uint32_t clkr : 4; + uint32_t clkf : 6; + uint32_t clkod : 4; + uint32_t bwadj : 6; + uint32_t pll_reset : 1; + uint32_t pll_pwrd : 1; + uint32_t pll_intfb : 1; + uint32_t pll_bypass : 1; + uint32_t pll_test : 1; + uint32_t pll_out_en : 1; + uint32_t pll_ckin_sel : 2; + uint32_t reserved : 4; +} __attribute__((packed, aligned(4))) sysctl_general_pll_t; + /** * @brief System controller object instanse */ @@ -892,15 +927,6 @@ int sysctl_clock_set_clock_select(sysctl_clock_select_t which, int select); */ int sysctl_clock_get_clock_select(sysctl_clock_select_t which); -/** - * @brief Get clock source frequency - * - * @param[in] input The input clock source - * - * @return The frequency of clock source - */ -uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_t input); - /** * @brief Get PLL frequency * @@ -910,17 +936,6 @@ uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_t input); */ uint32_t sysctl_pll_get_freq(sysctl_pll_t pll); -/** - * @brief Set PLL frequency and input clock - * - * @param[in] pll The PLL id - * @param[in] sel The selected PLL input clock - * @param[in] freq The frequency - * - * @return The frequency of PLL - */ -uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uint32_t freq); - /** * @brief Get base clock frequency by clock id * @@ -937,42 +952,6 @@ uint32_t sysctl_clock_get_freq(sysctl_clock_t clock); */ void sysctl_reset(sysctl_reset_t reset); -/** - * @brief Get git commit id - * - * @return The 4 bytes git commit id - */ -uint32_t sysctl_get_git_id(void); - -/** - * @brief Get base clock frequency, default is 26MHz - * - * @return The base clock frequency - */ -uint32_t sysctl_get_freq(void); - -/** - * @brief Get pll lock status - * - * @param[in] pll The pll id - * - * @return The lock status - * - 1 Pll is lock - * - 0 Pll have lost lock - */ -int sysctl_pll_is_lock(sysctl_pll_t pll); - -/** - * @brief Clear pll lock status - * - * @param[in] pll The pll id - * - * @return Result - * - 0 Success - * - Other Fail - */ -int sysctl_pll_clear_slip(sysctl_pll_t pll); - /** * @brief Enable the PLL and power on with reset * @@ -1007,15 +986,6 @@ int sysctl_pll_disable(sysctl_pll_t pll); */ int sysctl_dma_select(sysctl_dma_channel_t channel, sysctl_dma_select_t select); -/** - * @brief Fast set all PLL and CPU clock - * - * @return Result - * - 0 Success - * - Other Fail - */ -uint32_t sysctl_pll_fast_enable_pll(void); - /** * @brief Set SPI0_D0-D7 DVP_D0-D7 as spi and dvp data pin * @@ -1025,7 +995,7 @@ uint32_t sysctl_pll_fast_enable_pll(void); * - 0 Success * - Other Fail */ -uint32_t sysctl_spi0_dvp_data_set(uint8_t en); +uint32_t sysctl_set_spi0_dvp_data(uint8_t en); /** * @brief Set io power mode @@ -1037,20 +1007,23 @@ uint32_t sysctl_spi0_dvp_data_set(uint8_t en); * - 0 Success * - Other Fail */ -uint32_t sysctl_power_mode_sel(uint8_t power_bank, sysctl_io_power_mode_t io_power_mode); +void sysctl_set_power_mode(sysctl_power_mode_t power_bank, sysctl_io_power_mode_t io_power_mode); /** * @brief Set frequency of CPU - * @param[in] frequency The desired frequency in Hz + * @param[in] freq The desired frequency in Hz * * @return The actual frequency of CPU after set */ -uint32_t sysctl_set_cpu_frequency(uint32_t frequency); +uint32_t sysctl_cpu_set_freq(uint32_t freq); /** * @brief Init PLL freqency + * @param[in] pll The PLL id + * @param[in] pll_freq The desired frequency in Hz + */ -void sysctl_set_pll_frequency(uint64_t pll0, uint64_t pll1, uint64_t pll2); +uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, uint32_t pll_freq); /** * @brief Enable interrupt diff --git a/lib/drivers/rtc.c b/lib/drivers/rtc.c index 68097a16..c16d5a10 100644 --- a/lib/drivers/rtc.c +++ b/lib/drivers/rtc.c @@ -577,7 +577,7 @@ int rtc_init(void) rtc_protect_set(0); /* Set RTC clock frequency */ rtc_timer_set_clock_frequency( - sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0) + sysctl_clock_get_freq(SYSCTL_CLOCK_IN0) ); rtc_timer_set_clock_count_value(1); diff --git a/lib/drivers/sysctl.c b/lib/drivers/sysctl.c index d7b59a9c..627fb184 100644 --- a/lib/drivers/sysctl.c +++ b/lib/drivers/sysctl.c @@ -403,8 +403,16 @@ int sysctl_clock_disable(sysctl_clock_t clock) int sysctl_clock_set_threshold(sysctl_threshold_t which, int threshold) { + int result = 0; switch (which) { + /* + * These threshold is 2 bit width + */ + case SYSCTL_THRESHOLD_ACLK: + sysctl->clk_sel0.aclk_divider_sel = (uint8_t)threshold & 0x03; + break; + /* * These threshold is 3 bit width */ @@ -500,10 +508,10 @@ int sysctl_clock_set_threshold(sysctl_threshold_t which, int threshold) break; default: + result = -1; break; } - - return 0; + return result; } int sysctl_clock_get_threshold(sysctl_threshold_t which) @@ -606,6 +614,7 @@ int sysctl_clock_get_threshold(sysctl_threshold_t which) int sysctl_clock_set_clock_select(sysctl_clock_select_t which, int select) { + int result = 0; switch (which) { /* @@ -647,10 +656,11 @@ int sysctl_clock_set_clock_select(sysctl_clock_select_t which, int select) break; default: + result = -1; break; } - return 0; + return result; } int sysctl_clock_get_clock_select(sysctl_clock_select_t which) @@ -721,7 +731,6 @@ uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_t input) case SYSCTL_SOURCE_ACLK: result = sysctl_clock_get_freq(SYSCTL_CLOCK_ACLK); break; - default: result = 0; break; @@ -729,7 +738,7 @@ uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_t input) return result; } -int sysctl_pll_is_lock(sysctl_pll_t pll) +static int sysctl_pll_is_lock(sysctl_pll_t pll) { /* * All bit enable means PLL lock @@ -772,7 +781,7 @@ int sysctl_pll_is_lock(sysctl_pll_t pll) return 0; } -int sysctl_pll_clear_slip(sysctl_pll_t pll) +static int sysctl_pll_clear_slip(sysctl_pll_t pll) { if (pll >= SYSCTL_PLL_MAX) return -1; @@ -960,7 +969,7 @@ uint32_t sysctl_pll_get_freq(sysctl_pll_t pll) case SYSCTL_PLL2: /* - * Get input frequency accroding select register + * Get input freq accroding select register */ select = sysctl->pll2.pll_ckin_sel2; if (select < sizeof(get_source_pll2)) @@ -978,14 +987,14 @@ uint32_t sysctl_pll_get_freq(sysctl_pll_t pll) } /* - * Get final PLL output frequency + * Get final PLL output freq * FOUT = FIN / NR * NF / OD */ freq_out = (double)freq_in / (double)nr * (double)nf / (double)od; return freq_out; } -uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uint32_t freq) +static uint32_t sysctl_pll_source_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uint32_t freq) { uint32_t freq_in = 0; @@ -1006,7 +1015,7 @@ uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uin return 0; freq_in = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); /* - * Check input clock frequency + * Check input clock freq */ if (freq_in == 0) return 0; @@ -1019,7 +1028,7 @@ uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uin if (source < sizeof(get_select_pll2)) freq_in = sysctl_clock_source_get_freq(source); /* - * Check input clock frequency + * Check input clock freq */ if (freq_in == 0) return 0; @@ -1076,12 +1085,7 @@ uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uin val = fout / fin; terr = 0.5 / ((double)(nf_max / 2)); first = firstx = 1; - if (terr == -1) - { - printf("NR\tNF\tOD\tNB\tFvco\t\terror\n"); - printf("------------------------------------------------------\n"); - } - else if (terr != -2) + if (terr != -2) { first = 0; if (terr == 0) @@ -1183,16 +1187,14 @@ uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uin x_nb = nb; x_fvco = fvco; x_err = err; - first = firstx = 0; - merr = fabs(err); + first = firstx = 0; + merr = fabs(err); if (terr != -1) continue; - printf("%d\t%lld\t%d\t%d\t%e\t%#+g\n", nrx, nfx, no, nb, fvco, err); } } if (!found) { - printf("Error: No workable settings found.\n"); return 0; } @@ -1204,29 +1206,9 @@ uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uin err = x_err; if ((terr != -2) && (fabs(err) >= terr * (1 - 1e-6))) { - printf("Error: No appropriate ratio found.\n"); return 0; } -#ifdef CONFIG_PLL_DEBUG_ENABLE - printf("NR = %d\n", nrx); - printf("NF = %lld\n", nfx); - printf("OD = %d\n", no); - printf("NB = %d\n", nb); - - printf("\n"); - printf("Fin = %g\n", fin); - printf("Fvco = %g\n", fvco); - printf("Fout = %g\n", fvco / no); - printf("error = %+g\n", err); - - printf("\n"); - printf("CLKR[3:0] = %02x\n", nrx - 1); - printf("CLKF[5:0] = %02x\n", (unsigned int)nfx - 1); - printf("CLKOD[3:0] = %02x\n", no - 1); - printf("BWADJ[5:0] = %02x\n", nb - 1); -#endif /* CONFIG_PLL_DEBUG_ENABLE */ - /* * Begin write PLL registers' value, * Using atomic write method. @@ -1290,6 +1272,13 @@ uint32_t sysctl_clock_get_freq(sysctl_clock_t clock) switch (clock) { + /* + * The clock IN0 + */ + case SYSCTL_CLOCK_IN0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + break; + /* * These clock directly under PLL clock domain * They are using gated divider. @@ -1604,7 +1593,7 @@ uint32_t sysctl_clock_get_freq(sysctl_clock_t clock) result = source; break; case SYSCTL_CLOCK_RTC: - source = sysctl_clock_get_freq(SYSCTL_CLOCK_APB1); + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); result = source; break; @@ -1727,111 +1716,90 @@ uint32_t sysctl_pll_fast_enable_pll(void) return 0; } -uint32_t sysctl_spi0_dvp_data_set(uint8_t en) +uint32_t sysctl_set_spi0_dvp_data(uint8_t en) { sysctl->misc.spi_dvp_data_enable = en; return 0; } -uint32_t sysctl_power_mode_sel(uint8_t power_bank, sysctl_io_power_mode_t io_power_mode) +void sysctl_set_power_mode(sysctl_power_mode_t power_bank, sysctl_io_power_mode_t io_power_mode) { if(io_power_mode) *((uint32_t *)(&sysctl->power_sel)) |= (1 << power_bank); else *((uint32_t *)(&sysctl->power_sel)) &= ~(1 << power_bank); - return 0; } -void sysctl_set_pll_frequency(uint64_t pll0, uint64_t pll1, uint64_t pll2) +uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, uint32_t pll_freq) { - if (pll0 != 0U) { - /* We need to check PLL0 is enable before we change PLL0's frequency */ - sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0); + if(pll_freq == 0) + return 0; - if (sysctl->pll0.pll_out_en0 == 1 && sysctl->pll0.pll_pwrd0 == 1) { - /* PLL0 is enabled, we should disable it first */ - /* Disable PLL0 output */ - sysctl->pll0.pll_out_en0 = 0; - /* Turn off PLL0 */ - sysctl->pll0.pll_pwrd0 = 0; - } + volatile sysctl_general_pll_t *v_pll_t; + switch(pll) + { + case SYSCTL_PLL0: + v_pll_t = (sysctl_general_pll_t *)(&sysctl->pll0); + break; + case SYSCTL_PLL1: + v_pll_t = (sysctl_general_pll_t *)(&sysctl->pll1); + break; + case SYSCTL_PLL2: + v_pll_t = (sysctl_general_pll_t *)(&sysctl->pll2); + break; + default: + return 0; + break; + } - sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, pll0); + /* 1. Change CPU CLK to XTAL */ + if(pll == SYSCTL_PLL0) + sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0); - /* Power on PLL0 */ - sysctl->pll0.pll_pwrd0 = 1; + /* 2. Disable PLL output */ + v_pll_t->pll_out_en = 0; - /* Reset PLL0 */ - /* Release Reset */ - sysctl->pll0.pll_reset0 = 0; - sysctl->pll0.pll_reset0 = 1; - sysctl->pll0.pll_reset0 = 0; + /* 3. Turn off PLL */ + v_pll_t->pll_pwrd = 0; - /* 7. Get lock status, wait PLL0 stable */ - while (sysctl_pll_is_lock(SYSCTL_PLL0) == 0) - sysctl_pll_clear_slip(SYSCTL_PLL0); + /* 4. Set PLL new value */ + uint32_t result; + if(pll == SYSCTL_PLL2) + result = sysctl_pll_source_set_freq(pll, v_pll_t->pll_ckin_sel, pll_freq); + else + result = sysctl_pll_source_set_freq(pll, SYSCTL_SOURCE_IN0, pll_freq); - /* 8. Enable PLL0 output */ - sysctl->pll0.pll_out_en0 = 1; + /* 5. Power on PLL */ + v_pll_t->pll_pwrd = 1; - sysctl_clock_enable(SYSCTL_CLOCK_PLL0); - sysctl->clk_sel0.aclk_divider_sel = 0; - sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); - } + /* 6. Reset PLL then Release Reset*/ + v_pll_t->pll_reset = 0; + v_pll_t->pll_reset = 1; + /* wait 100ns */ + asm volatile ("nop"); + asm volatile ("nop"); + v_pll_t->pll_reset = 0; - if (pll1 != 0U) { - sysctl_pll_enable(SYSCTL_PLL1); - sysctl_pll_set_freq(SYSCTL_PLL1, SYSCTL_SOURCE_IN0, pll1); - while (sysctl_pll_is_lock(SYSCTL_PLL1) == 0) - sysctl_pll_clear_slip(SYSCTL_PLL1); - sysctl_clock_enable(SYSCTL_CLOCK_PLL1); - } + /* 7. Get lock status, wait PLL stable */ + while (sysctl_pll_is_lock(pll) == 0) + sysctl_pll_clear_slip(pll); - if (pll2 != 0U) { - sysctl_pll_enable(SYSCTL_PLL2); - sysctl_pll_set_freq(SYSCTL_PLL2, SYSCTL_SOURCE_IN0, pll2); - while (sysctl_pll_is_lock(SYSCTL_PLL2) == 0) - sysctl_pll_clear_slip(SYSCTL_PLL2); - sysctl_clock_enable(SYSCTL_CLOCK_PLL2); - } + /* 8. Enable PLL output */ + v_pll_t->pll_out_en = 1; + /* 9. Change CPU CLK to PLL */ + if(pll == SYSCTL_PLL0) + sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); + return result; } -uint32_t sysctl_set_cpu_frequency(uint32_t frequency) +uint32_t sysctl_cpu_set_freq(uint32_t freq) { - /* 1. Change CPU CLK to XTAL */ - sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0); - - /* 2. Disable PLL0 output */ - sysctl->pll0.pll_out_en0 = 0; - - /* 3. Turn off PLL0 */ - sysctl->pll0.pll_pwrd0 = 0; - - /* 4. Set PLL0 new value */ - uint32_t result = sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, frequency * 2); - - /* 5. Power on PLL0 */ - sysctl->pll0.pll_pwrd0 = 1; - - /* 6. Reset PLL0 */ - /* 6. Release Reset */ - sysctl->pll0.pll_reset0 = 0; - sysctl->pll0.pll_reset0 = 1; - sysctl->pll0.pll_reset0 = 0; - - /* 7. Get lock status, wait PLL0 stable */ - while (sysctl_pll_is_lock(SYSCTL_PLL0) == 0) - sysctl_pll_clear_slip(SYSCTL_PLL0); - - /* 8. Enable PLL0 output */ - sysctl->pll0.pll_out_en0 = 1; - - /* 9. Change CPU CLK to PLL0 */ - sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); + if(freq == 0) + return 0; - return result; + return sysctl_pll_set_freq(SYSCTL_PLL0, (sysctl->clk_sel0.aclk_divider_sel + 1) * 2 * freq); } void sysctl_enable_irq(void) diff --git a/lib/firmware/include/nt35310.h b/lib/firmware/include/nt35310.h index c92add77..dfeb38c0 100644 --- a/lib/firmware/include/nt35310.h +++ b/lib/firmware/include/nt35310.h @@ -95,7 +95,13 @@ #define DIGITAL_GAMMA_CTL2 0xE3 #define INTERFACE_CTL 0xF6 +/*#define BOARD_KD233*/ + +#ifdef BOARD_KD233 #define DCX_IO (8) +#else +#define DCX_IO (34) +#endif #define RESET_IO (30) #define RESET_GPIONUM (3) #define DCX_GPIONUM (2) diff --git a/lib/firmware/nt35310.c b/lib/firmware/nt35310.c index 0c96641f..8a6dcbb3 100644 --- a/lib/firmware/nt35310.c +++ b/lib/firmware/nt35310.c @@ -31,14 +31,12 @@ #define _SPI(x, y) __SPI(x, y) #define SPI(x) _SPI(SPI_CHANNEL, x) -#define TEST2_0 - void init_dcx(void) { fpioa_set_function(DCX_IO, FUNC_GPIOHS0 + DCX_GPIONUM);/*dcx*/ gpiohs_set_drive_mode(DCX_GPIONUM, GPIO_DM_OUTPUT); gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_HIGH); -#ifndef TEST2_0 +#ifndef BOARD_KD233 fpioa_set_function(RESET_IO, FUNC_GPIOHS0 + RESET_GPIONUM);/*reset*/ gpiohs_set_drive_mode(RESET_GPIONUM, GPIO_DM_OUTPUT); gpiohs_set_pin(RESET_GPIONUM, GPIO_PV_HIGH); @@ -57,14 +55,14 @@ void set_dcx_data(void) void pin_mux_init(void) { -#ifndef TEST2_0 +#ifndef BOARD_KD233 fpioa_set_function(31, SPI_SS); fpioa_set_function(32, SPI(SCLK)); #else fpioa_set_function(6, SPI_SS); fpioa_set_function(7, SPI(SCLK)); #endif - sysctl_spi0_dvp_data_set(1); + sysctl_set_spi0_dvp_data(1); } void tft_hard_init(void) From caf0a29345597b720d47a1ddba962f7fca607371 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Tue, 9 Oct 2018 11:02:52 +0800 Subject: [PATCH 44/58] Modify sysctl_power_bank_t, add pll waiting time of reset --- lib/drivers/include/sysctl.h | 4 ++-- lib/drivers/sysctl.c | 8 +++++++- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/lib/drivers/include/sysctl.h b/lib/drivers/include/sysctl.h index 1f33ca6c..059e329d 100644 --- a/lib/drivers/include/sysctl.h +++ b/lib/drivers/include/sysctl.h @@ -281,7 +281,7 @@ typedef enum _sysctl_power_bank SYSCTL_POWER_BANK6, SYSCTL_POWER_BANK7, SYSCTL_POWER_BANK_MAX, -} sysctl_power_mode_t; +} sysctl_power_bank_t; /** * @brief System controller reset control id @@ -1007,7 +1007,7 @@ uint32_t sysctl_set_spi0_dvp_data(uint8_t en); * - 0 Success * - Other Fail */ -void sysctl_set_power_mode(sysctl_power_mode_t power_bank, sysctl_io_power_mode_t io_power_mode); +void sysctl_set_power_mode(sysctl_power_bank_t power_bank, sysctl_io_power_mode_t io_power_mode); /** * @brief Set frequency of CPU diff --git a/lib/drivers/sysctl.c b/lib/drivers/sysctl.c index 627fb184..1c57fe48 100644 --- a/lib/drivers/sysctl.c +++ b/lib/drivers/sysctl.c @@ -847,6 +847,8 @@ int sysctl_pll_enable(sysctl_pll_t pll) */ sysctl->pll0.pll_reset0 = 0; sysctl->pll0.pll_reset0 = 1; + asm volatile ("nop"); + asm volatile ("nop"); sysctl->pll0.pll_reset0 = 0; break; @@ -866,6 +868,8 @@ int sysctl_pll_enable(sysctl_pll_t pll) */ sysctl->pll1.pll_reset1 = 0; sysctl->pll1.pll_reset1 = 1; + asm volatile ("nop"); + asm volatile ("nop"); sysctl->pll1.pll_reset1 = 0; break; @@ -885,6 +889,8 @@ int sysctl_pll_enable(sysctl_pll_t pll) */ sysctl->pll2.pll_reset2 = 0; sysctl->pll2.pll_reset2 = 1; + asm volatile ("nop"); + asm volatile ("nop"); sysctl->pll2.pll_reset2 = 0; break; @@ -1722,7 +1728,7 @@ uint32_t sysctl_set_spi0_dvp_data(uint8_t en) return 0; } -void sysctl_set_power_mode(sysctl_power_mode_t power_bank, sysctl_io_power_mode_t io_power_mode) +void sysctl_set_power_mode(sysctl_power_bank_t power_bank, sysctl_io_power_mode_t io_power_mode) { if(io_power_mode) *((uint32_t *)(&sysctl->power_sel)) |= (1 << power_bank); From 40dc8718b9739edc9676d559f3315d831a5d31de Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Tue, 9 Oct 2018 11:26:18 +0800 Subject: [PATCH 45/58] Modify SYSCTL_CLOCK_SELECT_PLL3_BYPASS to SYSCTL_CLOCK_SELECT_PLL2_BYPASS --- lib/drivers/include/sysctl.h | 2 +- lib/drivers/sysctl.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/drivers/include/sysctl.h b/lib/drivers/include/sysctl.h index 059e329d..c3d382ba 100644 --- a/lib/drivers/include/sysctl.h +++ b/lib/drivers/include/sysctl.h @@ -187,7 +187,7 @@ typedef enum _sysctl_clock_select_t { SYSCTL_CLOCK_SELECT_PLL0_BYPASS, SYSCTL_CLOCK_SELECT_PLL1_BYPASS, - SYSCTL_CLOCK_SELECT_PLL3_BYPASS, + SYSCTL_CLOCK_SELECT_PLL2_BYPASS, SYSCTL_CLOCK_SELECT_PLL2, SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_CLOCK_SELECT_SPI3, diff --git a/lib/drivers/sysctl.c b/lib/drivers/sysctl.c index 1c57fe48..106f7335 100644 --- a/lib/drivers/sysctl.c +++ b/lib/drivers/sysctl.c @@ -626,7 +626,7 @@ int sysctl_clock_set_clock_select(sysctl_clock_select_t which, int select) case SYSCTL_CLOCK_SELECT_PLL1_BYPASS: sysctl->pll1.pll_bypass1 = select & 0x01; break; - case SYSCTL_CLOCK_SELECT_PLL3_BYPASS: + case SYSCTL_CLOCK_SELECT_PLL2_BYPASS: sysctl->pll2.pll_bypass2 = select & 0x01; break; case SYSCTL_CLOCK_SELECT_ACLK: @@ -678,7 +678,7 @@ int sysctl_clock_get_clock_select(sysctl_clock_select_t which) case SYSCTL_CLOCK_SELECT_PLL1_BYPASS: clock_select = (int)sysctl->pll1.pll_bypass1; break; - case SYSCTL_CLOCK_SELECT_PLL3_BYPASS: + case SYSCTL_CLOCK_SELECT_PLL2_BYPASS: clock_select = (int)sysctl->pll2.pll_bypass2; break; case SYSCTL_CLOCK_SELECT_PLL2: From fe4666c71006169f4771eaf7a5337c2524e9509f Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Tue, 9 Oct 2018 15:01:52 +0800 Subject: [PATCH 46/58] Modify _io_power_mode to _sysctl_io_power_mode --- lib/drivers/include/sysctl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/drivers/include/sysctl.h b/lib/drivers/include/sysctl.h index c3d382ba..be394d0f 100644 --- a/lib/drivers/include/sysctl.h +++ b/lib/drivers/include/sysctl.h @@ -286,7 +286,7 @@ typedef enum _sysctl_power_bank /** * @brief System controller reset control id */ -typedef enum _io_power_mode +typedef enum _sysctl_io_power_mode { SYSCTL_POWER_V33, SYSCTL_POWER_V18 From 336dac0efbe977580e464949e4f752335575678f Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Tue, 9 Oct 2018 15:19:59 +0800 Subject: [PATCH 47/58] Update dvp --- lib/drivers/dvp.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/lib/drivers/dvp.c b/lib/drivers/dvp.c index f1b66a25..0aaaba52 100644 --- a/lib/drivers/dvp.c +++ b/lib/drivers/dvp.c @@ -103,20 +103,6 @@ uint8_t dvp_sccb_receive_data(uint8_t dev_addr, uint16_t reg_addr) return (uint8_t) DVP_SCCB_RDATA_BYTE(dvp->sccb_cfg); } -static void dvp_io_init(void) -{ - /* Init DVP IO map and function settings */ - fpioa_set_function(15, FUNC_CMOS_RST); - fpioa_set_function(17, FUNC_CMOS_PWDN); - fpioa_set_function(20, FUNC_CMOS_XCLK); - fpioa_set_function(18, FUNC_CMOS_VSYNC); - fpioa_set_function(19, FUNC_CMOS_HREF); - fpioa_set_function(21, FUNC_CMOS_PCLK); - fpioa_set_function(22, FUNC_SCCB_SCLK); - fpioa_set_function(23, FUNC_SCCB_SDA); - sysctl_set_spi0_dvp_data(1); -} - static void dvp_reset(void) { /* First power down */ @@ -139,7 +125,6 @@ void dvp_init(uint8_t reg_len) sysctl_reset(SYSCTL_RESET_DVP); dvp->cmos_cfg &= (~DVP_CMOS_CLK_DIV_MASK); dvp->cmos_cfg |= DVP_CMOS_CLK_DIV(0) | DVP_CMOS_CLK_ENABLE; - dvp_io_init(); dvp_sccb_clk_init(); dvp_reset(); } From c86775d0948ea893b30b3e575306342b7db34ee9 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Tue, 9 Oct 2018 15:25:10 +0800 Subject: [PATCH 48/58] Delete firmware --- lib/firmware/include/font.h | 366 ----------------- lib/firmware/include/lcd.h | 82 ---- lib/firmware/include/nt35310.h | 121 ------ lib/firmware/include/ov2640.h | 26 -- lib/firmware/include/ov5640.h | 43 -- lib/firmware/include/ov5640cfg.h | 287 -------------- lib/firmware/include/sd3068.h | 48 --- lib/firmware/include/w25qxx.h | 113 ------ lib/firmware/lcd.c | 210 ---------- lib/firmware/nt35310.c | 120 ------ lib/firmware/ov2640.c | 243 ------------ lib/firmware/ov5640.c | 82 ---- lib/firmware/sd3068.c | 206 ---------- lib/firmware/w25qxx.c | 654 ------------------------------- 14 files changed, 2601 deletions(-) delete mode 100644 lib/firmware/include/font.h delete mode 100644 lib/firmware/include/lcd.h delete mode 100644 lib/firmware/include/nt35310.h delete mode 100644 lib/firmware/include/ov2640.h delete mode 100644 lib/firmware/include/ov5640.h delete mode 100644 lib/firmware/include/ov5640cfg.h delete mode 100644 lib/firmware/include/sd3068.h delete mode 100644 lib/firmware/include/w25qxx.h delete mode 100644 lib/firmware/lcd.c delete mode 100644 lib/firmware/nt35310.c delete mode 100644 lib/firmware/ov2640.c delete mode 100644 lib/firmware/ov5640.c delete mode 100644 lib/firmware/sd3068.c delete mode 100644 lib/firmware/w25qxx.c diff --git a/lib/firmware/include/font.h b/lib/firmware/include/font.h deleted file mode 100644 index 4e7c010b..00000000 --- a/lib/firmware/include/font.h +++ /dev/null @@ -1,366 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _FONT_H_ -#define _FONT_H_ - -#include - -uint8_t const ascii0816[] = -{ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x81, 0xA5, 0x81, 0x81, 0xBD, - 0x99, 0x81, 0x81, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0xFF, - 0xDB, 0xFF, 0xFF, 0xC3, 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0x3E, 0x66, - 0x66, 0x66, 0x66, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x7E, 0xDB, 0xDB, 0xDB, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x06, 0x7E, 0xDB, 0xDB, 0xF3, 0x7E, 0x60, 0xC0, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x30, 0x60, 0x60, 0x7C, 0x60, - 0x60, 0x60, 0x30, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, - 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFE, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x7E, 0x18, - 0x18, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, - 0x18, 0x0C, 0x06, 0x0C, 0x18, 0x30, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x0C, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0C, 0x00, 0x7E, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x1B, 0x1B, 0x18, 0x18, 0x18, - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, - 0x18, 0x18, 0x18, 0x18, 0xD8, 0xD8, 0xD8, 0x70, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x7E, 0x00, 0x18, 0x18, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x76, 0xDC, 0x00, - 0x76, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x6C, 0x6C, - 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0C, 0x0C, - 0x0C, 0x0C, 0x0C, 0xEC, 0x6C, 0x6C, 0x3C, 0x1C, 0x00, 0x00, 0x00, 0x00, - 0x00, 0xD8, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xD8, 0x30, 0x60, 0xC8, 0xF8, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00}; - -#endif - diff --git a/lib/firmware/include/lcd.h b/lib/firmware/include/lcd.h deleted file mode 100644 index 248491ab..00000000 --- a/lib/firmware/include/lcd.h +++ /dev/null @@ -1,82 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _LCD_H_ -#define _LCD_H_ - -#include - -/* clang-format off */ -#define LCD_X_MAX (240) -#define LCD_Y_MAX (320) - -#define BLACK 0x0000 -#define NAVY 0x000F -#define DARKGREEN 0x03E0 -#define DARKCYAN 0x03EF -#define MAROON 0x7800 -#define PURPLE 0x780F -#define OLIVE 0x7BE0 -#define LIGHTGREY 0xC618 -#define DARKGREY 0x7BEF -#define BLUE 0x001F -#define GREEN 0x07E0 -#define CYAN 0x07FF -#define RED 0xF800 -#define MAGENTA 0xF81F -#define YELLOW 0xFFE0 -#define WHITE 0xFFFF -#define ORANGE 0xFD20 -#define GREENYELLOW 0xAFE5 -#define PINK 0xF81F -#define USER_COLOR 0xAA55 -/* clang-format on */ - -typedef enum _lcd_dir -{ - DIR_XY_RLUD = 0x00, - DIR_YX_RLUD = 0x20, - DIR_XY_LRUD = 0x40, - DIR_YX_LRUD = 0x60, - DIR_XY_RLDU = 0x80, - DIR_YX_RLDU = 0xA0, - DIR_XY_LRDU = 0xC0, - DIR_YX_LRDU = 0xE0, - DIR_XY_MASK = 0x20, - DIR_MASK = 0xE0, -} lcd_dir_t; - -typedef struct _lcd_ctl -{ - uint8_t mode; - uint8_t dir; - uint16_t width; - uint16_t height; -} lcd_ctl_t; - -int lcd_busy(void); -void lcd_polling_enable(void); -void lcd_interrupt_enable(void); -void lcd_init(void); -void lcd_clear(uint16_t color); -void lcd_set_direction(lcd_dir_t dir); -void lcd_set_area(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); -void lcd_draw_point(uint16_t x, uint16_t y, uint16_t color); -void lcd_draw_string(uint16_t x, uint16_t y, char *str, uint16_t color); -void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr); -void lcd_draw_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t width, uint16_t color); -void lcd_ram_draw_string(char *str, uint32_t *ptr, uint16_t font_color, uint16_t bg_color); - -#endif - diff --git a/lib/firmware/include/nt35310.h b/lib/firmware/include/nt35310.h deleted file mode 100644 index dfeb38c0..00000000 --- a/lib/firmware/include/nt35310.h +++ /dev/null @@ -1,121 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _NT35310_H_ -#define _NT35310_H_ - -#include - -/* clang-format off */ -#define NO_OPERATION 0x00 -#define SOFTWARE_RESET 0x01 -#define READ_ID 0x04 -#define READ_STATUS 0x09 -#define READ_POWER_MODE 0x0A -#define READ_MADCTL 0x0B -#define READ_PIXEL_FORMAT 0x0C -#define READ_IMAGE_FORMAT 0x0D -#define READ_SIGNAL_MODE 0x0E -#define READ_SELT_DIAG_RESULT 0x0F -#define SLEEP_ON 0x10 -#define SLEEP_OFF 0x11 -#define PARTIAL_DISPALY_ON 0x12 -#define NORMAL_DISPALY_ON 0x13 -#define INVERSION_DISPALY_OFF 0x20 -#define INVERSION_DISPALY_ON 0x21 -#define GAMMA_SET 0x26 -#define DISPALY_OFF 0x28 -#define DISPALY_ON 0x29 -#define HORIZONTAL_ADDRESS_SET 0x2A -#define VERTICAL_ADDRESS_SET 0x2B -#define MEMORY_WRITE 0x2C -#define COLOR_SET 0x2D -#define MEMORY_READ 0x2E -#define PARTIAL_AREA 0x30 -#define VERTICAL_SCROL_DEFINE 0x33 -#define TEAR_EFFECT_LINE_OFF 0x34 -#define TEAR_EFFECT_LINE_ON 0x35 -#define MEMORY_ACCESS_CTL 0x36 -#define VERTICAL_SCROL_S_ADD 0x37 -#define IDLE_MODE_OFF 0x38 -#define IDLE_MODE_ON 0x39 -#define PIXEL_FORMAT_SET 0x3A -#define WRITE_MEMORY_CONTINUE 0x3C -#define READ_MEMORY_CONTINUE 0x3E -#define SET_TEAR_SCANLINE 0x44 -#define GET_SCANLINE 0x45 -#define WRITE_BRIGHTNESS 0x51 -#define READ_BRIGHTNESS 0x52 -#define WRITE_CTRL_DISPALY 0x53 -#define READ_CTRL_DISPALY 0x54 -#define WRITE_BRIGHTNESS_CTL 0x55 -#define READ_BRIGHTNESS_CTL 0x56 -#define WRITE_MIN_BRIGHTNESS 0x5E -#define READ_MIN_BRIGHTNESS 0x5F -#define READ_ID1 0xDA -#define READ_ID2 0xDB -#define READ_ID3 0xDC -#define RGB_IF_SIGNAL_CTL 0xB0 -#define NORMAL_FRAME_CTL 0xB1 -#define IDLE_FRAME_CTL 0xB2 -#define PARTIAL_FRAME_CTL 0xB3 -#define INVERSION_CTL 0xB4 -#define BLANK_PORCH_CTL 0xB5 -#define DISPALY_FUNCTION_CTL 0xB6 -#define ENTRY_MODE_SET 0xB7 -#define BACKLIGHT_CTL1 0xB8 -#define BACKLIGHT_CTL2 0xB9 -#define BACKLIGHT_CTL3 0xBA -#define BACKLIGHT_CTL4 0xBB -#define BACKLIGHT_CTL5 0xBC -#define BACKLIGHT_CTL7 0xBE -#define BACKLIGHT_CTL8 0xBF -#define POWER_CTL1 0xC0 -#define POWER_CTL2 0xC1 -#define VCOM_CTL1 0xC5 -#define VCOM_CTL2 0xC7 -#define NV_MEMORY_WRITE 0xD0 -#define NV_MEMORY_PROTECT_KEY 0xD1 -#define NV_MEMORY_STATUS_READ 0xD2 -#define READ_ID4 0xD3 -#define POSITIVE_GAMMA_CORRECT 0xE0 -#define NEGATIVE_GAMMA_CORRECT 0xE1 -#define DIGITAL_GAMMA_CTL1 0xE2 -#define DIGITAL_GAMMA_CTL2 0xE3 -#define INTERFACE_CTL 0xF6 - -/*#define BOARD_KD233*/ - -#ifdef BOARD_KD233 -#define DCX_IO (8) -#else -#define DCX_IO (34) -#endif -#define RESET_IO (30) -#define RESET_GPIONUM (3) -#define DCX_GPIONUM (2) - -#define SPI_CHANNEL 0 -#define SPI_SLAVE_SELECT 3 -/* clang-format on */ - -void tft_hard_init(void); -void tft_write_command(uint8_t cmd); -void tft_write_byte(uint8_t *data_buf, uint32_t length); -void tft_write_half(uint16_t *data_buf, uint32_t length); -void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag); -void tft_fill_data(uint32_t *data_buf, uint32_t length); - -#endif - diff --git a/lib/firmware/include/ov2640.h b/lib/firmware/include/ov2640.h deleted file mode 100644 index 941142ea..00000000 --- a/lib/firmware/include/ov2640.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _OV2640_H -#define _OV2640_H - -#include - -#define OV2640_ADDR 0x60 - -int ov2640_init(void); -int ov2640_read_id(uint16_t *manuf_id, uint16_t *device_id); - -#endif /* _OV2640_H */ - diff --git a/lib/firmware/include/ov5640.h b/lib/firmware/include/ov5640.h deleted file mode 100644 index 74805961..00000000 --- a/lib/firmware/include/ov5640.h +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _OV5640_H -#define _OV5640_H - -#include - -#define OV5640_ID 0X5640 -#define OV5640_ADDR 0X78 -#define OV5640_CHIPIDH 0X300A -#define OV5640_CHIPIDL 0X300B - -#define XSIZE 320 -#define YSIZE 240 -#define LCD_GRAM_ADDRESS 0x60020000 - -#define QQVGA_160_120 0 -#define QCIF_176_144 1 -#define QVGA_320_240 2 -#define WQVGA_400_240 3 -#define CIF_352_288 4 - -#define jpeg_buf_size (30*1024) - -uint8_t ov5640_wr_reg(uint16_t reg, uint8_t data); -uint8_t ov5640_rd_reg(uint16_t reg); -uint8_t ov5640_init(void); -void ov5640_flash_lamp(uint8_t sw); - -#endif - diff --git a/lib/firmware/include/ov5640cfg.h b/lib/firmware/include/ov5640cfg.h deleted file mode 100644 index 62154882..00000000 --- a/lib/firmware/include/ov5640cfg.h +++ /dev/null @@ -1,287 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _OV5640CFG_H -#define _OV5640CFG_H - -#include "ov5640.h" - -const uint16_t ov5640_init_reg_tbl[][2]= -{ - /* 24MHz input clock, 24MHz PCLK */ - 0x3008, 0x42, /* software power down, bit[6] */ - 0x3103, 0x03, /* system clock from PLL, bit[1] */ - 0x3017, 0xff, /* FREX, Vsync, HREF, PCLK, D[9:6] output enable */ - 0x3018, 0xff, /* D[5:0], GPIO[1:0] output enable */ - 0x3034, 0x1a, /* MIPI 10-bit*/ - 0x3035, 0x41, /* PLL */ - 0x3036, 0x40, /* PLL */ - 0x3037, 0x13, /* PLL root divider, bit[4], PLL pre-divider, bit[3:0] */ - 0x3108, 0x01, /* PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2] */ - /* SCLK root divider, bit[1:0] */ - 0x3630, 0x36, - 0x3631, 0x0e, - 0x3632, 0xe2, - 0x3633, 0x12, - 0x3621, 0xe0, - 0x3704, 0xa0, - 0x3703, 0x5a, - 0x3715, 0x78, - 0x3717, 0x01, - 0x370b, 0x60, - 0x3705, 0x1a, - 0x3905, 0x02, - 0x3906, 0x10, - 0x3901, 0x0a, - 0x3731, 0x12, - 0x3600, 0x08, /* VCM control */ - 0x3601, 0x33, /* VCM control */ - 0x302d, 0x60, /* system control */ - 0x3620, 0x52, - 0x371b, 0x20, - 0x471c, 0x50, - 0x3a13, 0x43, /* pre-gain = 1.047x */ - 0x3a18, 0x00, /* gain ceiling */ - 0x3a19, 0xf8, /* gain ceiling = 15.5x */ - 0x3635, 0x13, - 0x3636, 0x03, - 0x3634, 0x40, - 0x3622, 0x01, - /* 50/60Hz detection 50/60Hz */ - 0x3c01, 0x34, /* Band auto, bit[7] */ - 0x3c04, 0x28, /* threshold low sum */ - 0x3c05, 0x98, /* threshold high sum */ - 0x3c06, 0x00, /* light meter 1 threshold[15:8] */ - 0x3c07, 0x07, /* light meter 1 threshold[7:0] */ - 0x3c08, 0x00, /* light meter 2 threshold[15:8] */ - 0x3c09, 0x1c, /* light meter 2 threshold[7:0] */ - 0x3c0a, 0x9c, /* sample number[15:8] */ - 0x3c0b, 0x40, /* sample number[7:0] */ - 0x3810, 0x00, /* Timing Hoffset[11:8] */ - 0x3811, 0x10, /* Timing Hoffset[7:0] */ - 0x3812, 0x00, /* Timing Voffset[10:8] */ - 0x3708, 0x64, - 0x4001, 0x02, /* BLC start from line 2 */ - 0x4005, 0x1a, /* BLC always update */ - 0x3000, 0x00, /* enable blocks */ - 0x3004, 0xff, /* enable clocks */ - 0x300e, 0x58, /* MIPI power down, DVP enable */ - 0x302e, 0x00, - 0x4300, 0x61, - 0X501F, 0x01, - 0x3820, 0x46, /* flip */ - 0x3821, 0x00, /* mirror */ - 0x3800, 0x00, /* HS */ - 0x3801, 0x00, /* HS */ - 0x3802, 0x00, /* VS */ - 0x3803, 0x00, /* VS */ - 0x3804, 0x0a, /* HW (HE) */ - 0x3805, 0x3f, /* HW (HE) */ - 0x3806, 0x06, /* VH (VE) */ - 0x3807, 0xa9, /* VH (VE) */ - 0x3814, 0x31, /* timing X inc */ - 0x3815, 0x31, /* timing Y inc */ - 0x3808, 0x01, /* DVPHO */ - 0x3809, 0x40, /* DVPHO */ - 0x380a, 0x00, /* DVPVO */ - 0x380b, 0xF0, /* DVPVO */ - 0x380c, 0x05, /* HTS */ - 0x380d, 0xF8, /* HTS */ - 0x380e, 0x03, /* VTS */ - 0x380f, 0x84, /* VTS */ - 0x3810, 0x00, /* HTS */ - 0x3811, 0x00, /* HTS */ - 0x3812, 0x00, /* VTS */ - 0x3813, 0x00, /* VTS */ - 0x3618, 0x00, - 0x3612, 0x29, - 0x3709, 0x52, - 0x370c, 0x03, - 0x3a02, 0x02, /* 60Hz max exposure */ - 0x3a03, 0xe0, /* 60Hz max exposure */ - 0x3a14, 0x02, /* 50Hz max exposure */ - 0x3a15, 0xe0, /* 50Hz max exposure */ - 0x4004, 0x02, /* BLC line number */ - 0x3002, 0x1c, /* reset JFIFO, SFIFO, JPG */ - 0x3006, 0xc3, /* disable clock of JPEG2x, JPEG */ - 0x4713, 0x03, /* JPEG mode 3 */ - 0x4407, 0x04, /* Quantization scale */ - 0x460b, 0x37, - 0x460c, 0x20, - 0x4837, 0x16, /* MIPI global timing */ - 0x3824, 0x04, /* PCLK manual divider */ - 0x5001, 0xA3, /* SDE on, scale on, UV average off, color matrix on, AWB on */ - 0x3503, 0x00, /* AEC/AGC on */ - 0x440e, 0x00, - 0x5000, 0xa7, /* Lenc on, raw gamma on, BPC on, WPC on, CIP on */ - /* AEC target*/ - 0x3a0f, 0x30, /* stable range in high */ - 0x3a10, 0x28, /* stable range in low */ - 0x3a1b, 0x30, /* stable range out high */ - 0x3a1e, 0x26, /* stable range out low */ - 0x3a11, 0x60, /* fast zone high */ - 0x3a1f, 0x14, /* fast zone low */ - /* Lens correction for */ - 0x5800, 0x23, - 0x5801, 0x14, - 0x5802, 0x0f, - 0x5803, 0x0f, - 0x5804, 0x12, - 0x5805, 0x26, - 0x5806, 0x0c, - 0x5807, 0x08, - 0x5808, 0x05, - 0x5809, 0x05, - 0x580a, 0x08, - 0x580b, 0x0d, - 0x580c, 0x08, - 0x580d, 0x03, - 0x580e, 0x00, - 0x580f, 0x00, - 0x5810, 0x03, - 0x5811, 0x09, - 0x5812, 0x07, - 0x5813, 0x03, - 0x5814, 0x00, - 0x5815, 0x01, - 0x5816, 0x03, - 0x5817, 0x08, - 0x5818, 0x0d, - 0x5819, 0x08, - 0x581a, 0x05, - 0x581b, 0x06, - 0x581c, 0x08, - 0x581d, 0x0e, - 0x581e, 0x29, - 0x581f, 0x17, - 0x5820, 0x11, - 0x5821, 0x11, - 0x5822, 0x15, - 0x5823, 0x28, - 0x5824, 0x46, - 0x5825, 0x26, - 0x5826, 0x08, - 0x5827, 0x26, - 0x5828, 0x64, - 0x5829, 0x26, - 0x582a, 0x24, - 0x582b, 0x22, - 0x582c, 0x24, - 0x582d, 0x24, - 0x582e, 0x06, - 0x582f, 0x22, - 0x5830, 0x40, - 0x5831, 0x42, - 0x5832, 0x24, - 0x5833, 0x26, - 0x5834, 0x24, - 0x5835, 0x22, - 0x5836, 0x22, - 0x5837, 0x26, - 0x5838, 0x44, - 0x5839, 0x24, - 0x583a, 0x26, - 0x583b, 0x28, - 0x583c, 0x42, - 0x583d, 0xce, /* lenc BR offset */ - /* AWB */ - 0x5180, 0xff, /* AWB B block */ - 0x5181, 0xf2, /* AWB control */ - 0x5182, 0x00, /* [7:4] max local counter, [3:0] max fast counter */ - 0x5183, 0x14, /* AWB advanced */ - 0x5184, 0x25, - 0x5185, 0x24, - 0x5186, 0x09, - 0x5187, 0x09, - 0x5188, 0x09, - 0x5189, 0x75, - 0x518a, 0x54, - 0x518b, 0xe0, - 0x518c, 0xb2, - 0x518d, 0x42, - 0x518e, 0x3d, - 0x518f, 0x56, - 0x5190, 0x46, - 0x5191, 0xf8, /* AWB top limit */ - 0x5192, 0x04, /* AWB bottom limit */ - 0x5193, 0x70, /* red limit */ - 0x5194, 0xf0, /* green limit */ - 0x5195, 0xf0, /* blue limit */ - 0x5196, 0x03, /* AWB control*/ - 0x5197, 0x01, /* local limit */ - 0x5198, 0x04, - 0x5199, 0x12, - 0x519a, 0x04, - 0x519b, 0x00, - 0x519c, 0x06, - 0x519d, 0x82, - 0x519e, 0x38, /* AWB control */ - /* Gamma */ - 0x5480, 0x01, /* Gamma bias plus on, bit[0] */ - 0x5481, 0x08, - 0x5482, 0x14, - 0x5483, 0x28, - 0x5484, 0x51, - 0x5485, 0x65, - 0x5486, 0x71, - 0x5487, 0x7d, - 0x5488, 0x87, - 0x5489, 0x91, - 0x548a, 0x9a, - 0x548b, 0xaa, - 0x548c, 0xb8, - 0x548d, 0xcd, - 0x548e, 0xdd, - 0x548f, 0xea, - 0x5490, 0x1d, - /* color matrix */ - 0x5381, 0x1e, /* CMX1 for Y */ - 0x5382, 0x5b, /* CMX2 for Y */ - 0x5383, 0x08, /* CMX3 for Y */ - 0x5384, 0x0a, /* CMX4 for U */ - 0x5385, 0x7e, /* CMX5 for U */ - 0x5386, 0x88, /* CMX6 for U */ - 0x5387, 0x7c, /* CMX7 for V */ - 0x5388, 0x6c, /* CMX8 for V */ - 0x5389, 0x10, /* CMX9 for V */ - 0x538a, 0x01, /* sign[9] */ - 0x538b, 0x98, /* sign[8:1] */ - /* UV adjust UV */ - 0x5580, 0x06, /* saturation on, bit[1] */ - 0x5583, 0x40, - 0x5584, 0x10, - 0x5589, 0x10, - 0x558a, 0x00, - 0x558b, 0xf8, - 0x501d, 0x40, /* enable manual offset of contrast */ - /* CIP */ - 0x5300, 0x08, /* CIP sharpen MT threshold 1 */ - 0x5301, 0x30, /* CIP sharpen MT threshold 2 */ - 0x5302, 0x10, /* CIP sharpen MT offset 1 */ - 0x5303, 0x00, /* CIP sharpen MT offset 2 */ - 0x5304, 0x08, /* CIP DNS threshold 1 */ - 0x5305, 0x30, /* CIP DNS threshold 2 */ - 0x5306, 0x08, /* CIP DNS offset 1 */ - 0x5307, 0x16, /* CIP DNS offset 2 */ - 0x5309, 0x08, /* CIP sharpen TH threshold 1 */ - 0x530a, 0x30, /* CIP sharpen TH threshold 2 */ - 0x530b, 0x04, /* CIP sharpen TH offset 1 */ - 0x530c, 0x06, /* CIP sharpen TH offset 2 */ - 0x5025, 0x00, - 0x3008, 0x02, /* wake up from standby, bit[6] */ - 0x4740, 0X21, /*VSYNC active HIGH */ -}; - -#endif - diff --git a/lib/firmware/include/sd3068.h b/lib/firmware/include/sd3068.h deleted file mode 100644 index dfa7df36..00000000 --- a/lib/firmware/include/sd3068.h +++ /dev/null @@ -1,48 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _SD3068_H -#define _SD3068_H - -#include -#include "i2c.h" - -#define SD3068_ADDR 0x32 -#define SD3068_ADDR_LENTH 7 - -typedef struct _sd_time -{ - uint32_t year:6; - uint32_t month:4; - uint32_t day:5; - uint32_t hour:5; - uint32_t min:6; - uint32_t sec:6; -} __attribute__((packed, aligned(4))) sd_time_t; - -void sd3068_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode); -int sd3068_write_enable(void); -int sd3068_write_disable(void); -int sd3068_set_time(sd_time_t time); -int sd3068_get_time(sd_time_t *time); -int sd3068_write_data(uint8_t addr, uint8_t *data_buf, uint8_t length); -int sd3068_read_data(uint8_t addr, uint8_t *data_buf, uint8_t length); -int sd3068_set_time_dma(sd_time_t time); -int sd3068_write_enable_dma(void); -int sd3068_get_time_dma(sd_time_t *time); -int sd3068_read_data_dma(uint8_t addr, uint8_t *data_buf, uint8_t length); -int sd3068_write_data_dma(uint8_t addr, uint8_t *data_buf, uint8_t length); - -#endif - diff --git a/lib/firmware/include/w25qxx.h b/lib/firmware/include/w25qxx.h deleted file mode 100644 index 9e4de40a..00000000 --- a/lib/firmware/include/w25qxx.h +++ /dev/null @@ -1,113 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _W25QXX_H -#define _W25QXX_H - -#include - -/* clang-format off */ -#define DATALENGTH 8 - -#define SPI_SLAVE_SELECT (0x01) - -#define w25qxx_FLASH_PAGE_SIZE 256 -#define w25qxx_FLASH_SECTOR_SIZE 4096 -#define w25qxx_FLASH_PAGE_NUM_PER_SECTOR 16 -#define w25qxx_FLASH_CHIP_SIZE (16777216 UL) - -#define WRITE_ENABLE 0x06 -#define WRITE_DISABLE 0x04 -#define READ_REG1 0x05 -#define READ_REG2 0x35 -#define READ_REG3 0x15 -#define WRITE_REG1 0x01 -#define WRITE_REG2 0x31 -#define WRITE_REG3 0x11 -#define READ_DATA 0x03 -#define FAST_READ 0x0B -#define FAST_READ_DUAL_OUTPUT 0x3B -#define FAST_READ_QUAL_OUTPUT 0x6B -#define FAST_READ_DUAL_IO 0xBB -#define FAST_READ_QUAL_IO 0xEB -#define DUAL_READ_RESET 0xFFFF -#define QUAL_READ_RESET 0xFF -#define PAGE_PROGRAM 0x02 -#define QUAD_PAGE_PROGRAM 0x32 -#define SECTOR_ERASE 0x20 -#define BLOCK_32K_ERASE 0x52 -#define BLOCK_64K_ERASE 0xD8 -#define CHIP_ERASE 0x60 -#define READ_ID 0x90 -#define ENABLE_QPI 0x38 -#define EXIT_QPI 0xFF -#define ENABLE_RESET 0x66 -#define RESET_DEVICE 0x99 - -#define REG1_BUSY_MASK 0x01 -#define REG2_QUAL_MASK 0x02 - -#define LETOBE(x) ((x >> 24) | ((x & 0x00FF0000) >> 8) | ((x & 0x0000FF00) << 8) | (x << 24)) -/* clang-format on */ - -/** - * @brief w25qxx operating status enumerate - */ -typedef enum _w25qxx_status -{ - W25QXX_OK = 0, - W25QXX_BUSY, - W25QXX_ERROR, -} w25qxx_status_t; - -/** - * @brief w25qxx read operating enumerate - */ -typedef enum _w25qxx_read -{ - W25QXX_STANDARD = 0, - W25QXX_STANDARD_FAST, - W25QXX_DUAL, - W25QXX_DUAL_FAST, - W25QXX_QUAD, - W25QXX_QUAD_FAST, -} w25qxx_read_t; - -w25qxx_status_t w25qxx_init(uint8_t spi_index, uint8_t spi_ss); -w25qxx_status_t w25qxx_is_busy(void); -w25qxx_status_t w25qxx_chip_erase(void); -w25qxx_status_t w25qxx_enable_quad_mode(void); -w25qxx_status_t w25qxx_disable_quad_mode(void); -w25qxx_status_t w25qxx_sector_erase(uint32_t addr); -w25qxx_status_t w25qxx_32k_block_erase(uint32_t addr); -w25qxx_status_t w25qxx_64k_block_erase(uint32_t addr); -w25qxx_status_t w25qxx_read_status_reg1(uint8_t *reg_data); -w25qxx_status_t w25qxx_read_status_reg2(uint8_t *reg_data); -w25qxx_status_t w25qxx_write_status_reg(uint8_t reg1_data, uint8_t reg2_data); -w25qxx_status_t w25qxx_read_id(uint8_t *manuf_id, uint8_t *device_id); -w25qxx_status_t w25qxx_write_data(uint32_t addr, uint8_t *data_buf, uint32_t length); -w25qxx_status_t w25qxx_write_data_direct(uint32_t addr, uint8_t *data_buf, uint32_t length); -w25qxx_status_t w25qxx_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length, w25qxx_read_t mode); -w25qxx_status_t w25qxx_enable_xip_mode(void); -w25qxx_status_t w25qxx_disable_xip_mode(void); -w25qxx_status_t w25qxx_read_id_dma(uint8_t *manuf_id, uint8_t *device_id); -w25qxx_status_t w25qxx_sector_erase_dma(uint32_t addr); -w25qxx_status_t w25qxx_init_dma(uint8_t spi_index, uint8_t spi_ss); -w25qxx_status_t w25qxx_write_data_direct_dma(uint32_t addr, uint8_t *data_buf, uint32_t length); -w25qxx_status_t w25qxx_read_data_dma(uint32_t addr, uint8_t *data_buf, uint32_t length, w25qxx_read_t mode); -w25qxx_status_t w25qxx_is_busy_dma(void); -w25qxx_status_t w25qxx_enable_quad_mode_dma(void); - -#endif - diff --git a/lib/firmware/lcd.c b/lib/firmware/lcd.c deleted file mode 100644 index 30f62b8a..00000000 --- a/lib/firmware/lcd.c +++ /dev/null @@ -1,210 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "lcd.h" -#include "nt35310.h" -#include "font.h" -#include "utils.h" -#include "sleep.h" - -static lcd_ctl_t lcd_ctl; - -void lcd_polling_enable(void) -{ - lcd_ctl.mode = 0; -} - -void lcd_interrupt_enable(void) -{ - lcd_ctl.mode = 1; - -} - -void lcd_init(void) -{ - uint8_t data = 0; - - tft_hard_init(); - /*soft reset*/ - tft_write_command(SOFTWARE_RESET); - msleep(100); - /*exit sleep*/ - tft_write_command(SLEEP_OFF); - msleep(100); - /*pixel format*/ - tft_write_command(PIXEL_FORMAT_SET); - data = 0x55; - tft_write_byte(&data, 1); - lcd_set_direction(DIR_XY_RLUD); - /*display on*/ - tft_write_command(DISPALY_ON); - lcd_polling_enable(); -} - -void lcd_set_direction(lcd_dir_t dir) -{ - lcd_ctl.dir = dir; - if (dir & DIR_XY_MASK) - { - lcd_ctl.width = LCD_Y_MAX - 1; - lcd_ctl.height = LCD_X_MAX - 1; - } - else - { - lcd_ctl.width = LCD_X_MAX - 1; - lcd_ctl.height = LCD_Y_MAX - 1; - } - - tft_write_command(MEMORY_ACCESS_CTL); - tft_write_byte((uint8_t *)&dir, 1); -} - -void lcd_set_area(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) -{ - uint8_t data[4] = {0}; - - data[0] = (uint8_t)(x1 >> 8); - data[1] = (uint8_t)(x1); - data[2] = (uint8_t)(x2 >> 8); - data[3] = (uint8_t)(x2); - tft_write_command(HORIZONTAL_ADDRESS_SET); - tft_write_byte(data, 4); - - data[0] = (uint8_t)(y1 >> 8); - data[1] = (uint8_t)(y1); - data[2] = (uint8_t)(y2 >> 8); - data[3] = (uint8_t)(y2); - tft_write_command(VERTICAL_ADDRESS_SET); - tft_write_byte(data, 4); - - tft_write_command(MEMORY_WRITE); -} - -void lcd_draw_point(uint16_t x, uint16_t y, uint16_t color) -{ - lcd_set_area(x, y, x, y); - tft_write_half(&color, 1); -} - -void lcd_draw_char(uint16_t x, uint16_t y, char c, uint16_t color) -{ - uint8_t i = 0; - uint8_t j = 0; - uint8_t data = 0; - - for (i = 0; i < 16; i++) - { - data = ascii0816[c * 16 + i]; - for (j = 0; j < 8; j++) - { - if (data & 0x80) - lcd_draw_point(x + j, y, color); - data <<= 1; - } - y++; - } -} - -void lcd_draw_string(uint16_t x, uint16_t y, char *str, uint16_t color) -{ - while (*str) - { - lcd_draw_char(x, y, *str, color); - str++; - x += 8; - } -} - -void lcd_ram_draw_string(char *str, uint32_t *ptr, uint16_t font_color, uint16_t bg_color) -{ - uint8_t i = 0; - uint8_t j = 0; - uint8_t data = 0; - uint8_t *pdata = NULL; - uint16_t width = 0; - uint32_t *pixel = NULL; - - width = 4 * strlen(str); - while (*str) - { - pdata = (uint8_t *)&ascii0816[(*str) * 16]; - for (i = 0; i < 16; i++) - { - data = *pdata++; - pixel = ptr + i * width; - for (j = 0; j < 4; j++) - { - switch (data >> 6) - { - case 0: - *pixel = ((uint32_t)bg_color << 16) | bg_color; - break; - case 1: - *pixel = ((uint32_t)bg_color << 16) | font_color; - break; - case 2: - *pixel = ((uint32_t)font_color << 16) | bg_color; - break; - case 3: - *pixel = ((uint32_t)font_color << 16) | font_color; - break; - default: - *pixel = 0; - break; - } - data <<= 2; - pixel++; - } - } - str++; - ptr += 4; - } -} - -void lcd_clear(uint16_t color) -{ - uint32_t data = ((uint32_t)color << 16) | (uint32_t)color; - - lcd_set_area(0, 0, lcd_ctl.width, lcd_ctl.height); - tft_fill_data(&data, LCD_X_MAX * LCD_Y_MAX / 2); -} - -void lcd_draw_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t width, uint16_t color) -{ - uint32_t data_buf[640] = {0}; - uint32_t *p = data_buf; - uint32_t data = color; - uint32_t index = 0; - - data = (data << 16) | data; - for (index = 0; index < 160 * width; index++) - *p++ = data; - - lcd_set_area(x1, y1, x2, y1 + width - 1); - tft_write_word(data_buf, ((x2 - x1 + 1) * width + 1) / 2, 0); - lcd_set_area(x1, y2 - width + 1, x2, y2); - tft_write_word(data_buf, ((x2 - x1 + 1) * width + 1) / 2, 0); - lcd_set_area(x1, y1, x1 + width - 1, y2); - tft_write_word(data_buf, ((y2 - y1 + 1) * width + 1) / 2, 0); - lcd_set_area(x2 - width + 1, y1, x2, y2); - tft_write_word(data_buf, ((y2 - y1 + 1) * width + 1) / 2, 0); -} - -void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr) -{ - lcd_set_area(x1, y1, x1 + width - 1, y1 + height - 1); - tft_write_word(ptr, width * height / 2, lcd_ctl.mode ? 2 : 0); -} - diff --git a/lib/firmware/nt35310.c b/lib/firmware/nt35310.c deleted file mode 100644 index 8a6dcbb3..00000000 --- a/lib/firmware/nt35310.c +++ /dev/null @@ -1,120 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "nt35310.h" -#include "sysctl.h" -#include "fpioa.h" -#include "gpiohs.h" -#include "spi.h" -#include "dmac.h" -#include "plic.h" -#include - -#define __SPI_SYSCTL(x, y) SYSCTL_##x##_SPI##y -#define _SPI_SYSCTL(x, y) __SPI_SYSCTL(x, y) -#define SPI_SYSCTL(x) _SPI_SYSCTL(x, SPI_CHANNEL) -#define __SPI_SS(x, y) FUNC_SPI##x##_SS##y -#define _SPI_SS(x, y) __SPI_SS(x, y) -#define SPI_SS _SPI_SS(SPI_CHANNEL, SPI_SLAVE_SELECT) -#define __SPI(x, y) FUNC_SPI##x##_##y -#define _SPI(x, y) __SPI(x, y) -#define SPI(x) _SPI(SPI_CHANNEL, x) - -void init_dcx(void) -{ - fpioa_set_function(DCX_IO, FUNC_GPIOHS0 + DCX_GPIONUM);/*dcx*/ - gpiohs_set_drive_mode(DCX_GPIONUM, GPIO_DM_OUTPUT); - gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_HIGH); -#ifndef BOARD_KD233 - fpioa_set_function(RESET_IO, FUNC_GPIOHS0 + RESET_GPIONUM);/*reset*/ - gpiohs_set_drive_mode(RESET_GPIONUM, GPIO_DM_OUTPUT); - gpiohs_set_pin(RESET_GPIONUM, GPIO_PV_HIGH); -#endif -} - -void set_dcx_control(void) -{ - gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_LOW); -} - -void set_dcx_data(void) -{ - gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_HIGH); -} - -void pin_mux_init(void) -{ -#ifndef BOARD_KD233 - fpioa_set_function(31, SPI_SS); - fpioa_set_function(32, SPI(SCLK)); -#else - fpioa_set_function(6, SPI_SS); - fpioa_set_function(7, SPI(SCLK)); -#endif - sysctl_set_spi0_dvp_data(1); -} - -void tft_hard_init(void) -{ - init_dcx(); - pin_mux_init(); - spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8); -} - -void tft_write_command(uint8_t cmd) -{ - set_dcx_control(); - spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8); - spi_init_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, - SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT, (uint8_t *)(&cmd), 1,SPI_TRANS_CHAR); -} - -void tft_write_byte(uint8_t *data_buf, uint32_t length) -{ - set_dcx_data(); - spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8); - spi_init_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, - SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT, data_buf, length, SPI_TRANS_CHAR); -} - -void tft_write_half(uint16_t *data_buf, uint32_t length) -{ - set_dcx_data(); - spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 16); - spi_init_non_standard(SPI_CHANNEL, 16/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, - SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_SHORT); -} - -void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag) -{ - set_dcx_data(); - spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 32); - - spi_init_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, - SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_INT); -} - -void tft_fill_data(uint32_t *data_buf, uint32_t length) -{ - set_dcx_data(); - spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 32); - spi_init_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, - SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_fill_data_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length); -} - diff --git a/lib/firmware/ov2640.c b/lib/firmware/ov2640.c deleted file mode 100644 index 418be00b..00000000 --- a/lib/firmware/ov2640.c +++ /dev/null @@ -1,243 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "ov2640.h" -#include "dvp.h" -#include "plic.h" - -/* QVGA Window Size */ -static const uint8_t ov2640_config[][2] = -{ - {0xff, 0x00}, - {0x2c, 0xff}, - {0x2e, 0xdf}, - {0xff, 0x01}, - {0x3c, 0x32}, - {0x11, 0x00}, - {0x09, 0x00}, - {0x04, 0x28}, - {0x13, 0xe5}, - {0x14, 0xa8}, - {0x15, 0x00}, - {0x2c, 0x0c}, - {0x33, 0x78}, - {0x3a, 0x33}, - {0x3b, 0xfb}, - {0x3e, 0x00}, - {0x43, 0x11}, - {0x16, 0x10}, - {0x39, 0x92}, - {0x35, 0xda}, - {0x22, 0x1a}, - {0x23, 0x00}, - {0x34, 0xc0}, - {0x06, 0x88}, - {0x07, 0xc0}, - {0x0d, 0x87}, - {0x0e, 0x41}, - {0x4c, 0x00}, - {0x48, 0x00}, - {0x5b, 0x00}, - {0x42, 0x03}, - {0x4a, 0x81}, - {0x21, 0x99}, - {0x24, 0x40}, - {0x25, 0x38}, - {0x26, 0x82}, - {0x5c, 0x00}, - {0x63, 0x00}, - {0x61, 0x70}, - {0x62, 0x80}, - {0x7c, 0x05}, - {0x20, 0x80}, - {0x28, 0x30}, - {0x6c, 0x00}, - {0x6d, 0x80}, - {0x6e, 0x00}, - {0x70, 0x02}, - {0x71, 0x94}, - {0x73, 0xc1}, - {0x0c, 0x3c}, - {0x5d, 0x55}, - {0x5e, 0x7d}, - {0x5f, 0x7d}, - {0x60, 0x55}, - {0x12, 0x40}, - {0x32, 0xC9}, - {0x17, 0x11}, - {0x18, 0x43}, - {0x19, 0x00}, - {0x1a, 0x97}, - {0x32, 0x09}, - {0x37, 0x42}, - {0x4f, 0xbb}, - {0x50, 0x9c}, - {0x6d, 0x80}, - {0x35, 0x88}, - {0x22, 0x0a}, - {0x6d, 0x80}, - {0x3d, 0xe1}, - {0xff, 0x00}, - {0xe5, 0x7f}, - {0xf9, 0xc0}, - {0x41, 0x24}, - {0x44, 0x06}, - {0xe0, 0x14}, - {0x76, 0xff}, - {0x33, 0xa0}, - {0x42, 0x20}, - {0x43, 0x18}, - {0x4c, 0x00}, - {0x87, 0xd0}, - {0x88, 0x3f}, - {0xd7, 0x03}, - {0xd9, 0x10}, - {0xd3, 0x82}, - {0xc8, 0x08}, - {0xc9, 0x80}, - {0x7c, 0x00}, - {0x7d, 0x00}, - {0x7c, 0x03}, - {0x7d, 0x48}, - {0x7d, 0x48}, - {0x7c, 0x08}, - {0x7d, 0x20}, - {0x7d, 0x10}, - {0x7d, 0x0e}, - {0x90, 0x00}, - {0x91, 0x0e}, - {0x91, 0x1a}, - {0x91, 0x31}, - {0x91, 0x5a}, - {0x91, 0x69}, - {0x91, 0x75}, - {0x91, 0x7e}, - {0x91, 0x88}, - {0x91, 0x8f}, - {0x91, 0x96}, - {0x91, 0xa3}, - {0x91, 0xaf}, - {0x91, 0xc4}, - {0x91, 0xd7}, - {0x91, 0xe8}, - {0x91, 0x20}, - {0x92, 0x00}, - {0x93, 0x06}, - {0x93, 0xe3}, - {0x93, 0x03}, - {0x93, 0x03}, - {0x93, 0x00}, - {0x93, 0x02}, - {0x93, 0x00}, - {0x93, 0x00}, - {0x93, 0x00}, - {0x93, 0x00}, - {0x93, 0x00}, - {0x93, 0x00}, - {0x93, 0x00}, - {0x96, 0x00}, - {0x97, 0x08}, - {0x97, 0x19}, - {0x97, 0x02}, - {0x97, 0x0c}, - {0x97, 0x24}, - {0x97, 0x30}, - {0x97, 0x28}, - {0x97, 0x26}, - {0x97, 0x02}, - {0x97, 0x98}, - {0x97, 0x80}, - {0x97, 0x00}, - {0x97, 0x00}, - {0xa4, 0x00}, - {0xa8, 0x00}, - {0xc5, 0x11}, - {0xc6, 0x51}, - {0xbf, 0x80}, - {0xc7, 0x10}, - {0xb6, 0x66}, - {0xb8, 0xa5}, - {0xb7, 0x64}, - {0xb9, 0x7c}, - {0xb3, 0xaf}, - {0xb4, 0x97}, - {0xb5, 0xff}, - {0xb0, 0xc5}, - {0xb1, 0x94}, - {0xb2, 0x0f}, - {0xc4, 0x5c}, - {0xa6, 0x00}, - {0xa7, 0x20}, - {0xa7, 0xd8}, - {0xa7, 0x1b}, - {0xa7, 0x31}, - {0xa7, 0x00}, - {0xa7, 0x18}, - {0xa7, 0x20}, - {0xa7, 0xd8}, - {0xa7, 0x19}, - {0xa7, 0x31}, - {0xa7, 0x00}, - {0xa7, 0x18}, - {0xa7, 0x20}, - {0xa7, 0xd8}, - {0xa7, 0x19}, - {0xa7, 0x31}, - {0xa7, 0x00}, - {0xa7, 0x18}, - {0xe0, 0x04}, - {0xc0, 0x64}, - {0xc1, 0x4b}, - {0x86, 0x3d}, - {0x50, 0x80}, - {0x51, 0xc8}, - {0x52, 0x96}, - {0x53, 0x00}, - {0x54, 0x00}, - {0x55, 0x00}, - {0x57, 0x00}, - {0x5a, 0x50}, - {0x5b, 0x3c}, - {0x5c, 0x00}, - {0xd3, 0x04}, - {0xe0, 0x00}, - {0xc3, 0xef}, - {0x7f, 0x00}, - {0xda, 0x08}, - {0xe5, 0x1f}, - {0xe1, 0x67}, - {0xdd, 0x7f}, - {0x05, 0x00}, - {0x98, 0x00}, - {0x99, 0x00}, - {0x00, 0x00}, -}; - -int ov2640_init(void) -{ - uint16_t index = 0; - for (index = 0; ov2640_config[index][0]; index++) - dvp_sccb_send_data(OV2640_ADDR, ov2640_config[index][0], ov2640_config[index][1]); - return 0; -} - -int ov2640_read_id(uint16_t *manuf_id, uint16_t *device_id) -{ - dvp_sccb_send_data(OV2640_ADDR, 0xFF, 0x01); - *manuf_id = (dvp_sccb_receive_data(OV2640_ADDR, 0x1C) << 8) | dvp_sccb_receive_data(OV2640_ADDR, 0x1D); - *device_id = (dvp_sccb_receive_data(OV2640_ADDR, 0x0A) << 8) | dvp_sccb_receive_data(OV2640_ADDR, 0x0B); - return 0; -} - diff --git a/lib/firmware/ov5640.c b/lib/firmware/ov5640.c deleted file mode 100644 index 6b8250b2..00000000 --- a/lib/firmware/ov5640.c +++ /dev/null @@ -1,82 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "ov5640.h" -#include "ov5640cfg.h" -#include -#include "ov2640.h" -#include "dvp.h" -#include "plic.h" - -extern void mdelay(uint32_t ms); - -void hal_delay(uint32_t delay) -{ - mdelay(delay); -} - -uint8_t ov5640_wr_reg(uint16_t reg,uint8_t data) -{ - dvp_sccb_send_data(OV5640_ADDR, reg, data); - return 0; -} - -uint8_t ov5640_rd_reg(uint16_t reg) -{ - return dvp_sccb_receive_data(OV5640_ADDR, reg); -} - -uint8_t ov5640_init(void) -{ - uint16_t i = 0; - uint16_t reg = 0; - - reg = ov5640_rd_reg(OV5640_CHIPIDH); - reg <<= 8; - reg |= ov5640_rd_reg(OV5640_CHIPIDL); - printf("ID: %X \r\n", reg); - if(reg != OV5640_ID) - { - printf("ID: %d \r\n", reg); - return 1; - } - - ov5640_wr_reg(0x3103,0X11); /*system clock from pad, bit[1]*/ - ov5640_wr_reg(0X3008,0X82); - hal_delay(10); - - for(i = 0; i -#include "sd3068.h" -#include "fpioa.h" -#include "utils.h" -#include "sysctl.h" -#include -#include - -uint32_t i2c_bus_no = 0; - -void sd3068_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode) -{ - i2c_bus_no = i2c_num; - i2c_init(i2c_num, slave_address, address_width, bus_speed_mode); -} - -static int sd3068_write_reg(uint8_t reg, uint8_t *data_buf, uint8_t length) -{ - uint8_t *buf = malloc(length + 1); - buf[0] = reg; - memcpy(buf + 1, data_buf, length); - i2c_send_data(i2c_bus_no, buf, length + 1); - free(buf); - return 0; -} - -static int sd3068_write_reg_dma(uint8_t reg, uint8_t *data_buf, uint8_t length) -{ - - uint8_t *buf = malloc(length + 1); - buf[0] = reg; - memcpy(buf + 1, data_buf, length); - i2c_send_data_dma(DMAC_CHANNEL0, i2c_bus_no, buf, length + 1); - free(buf); - return 0; -} - -static int sd3068_read_reg(uint8_t reg, uint8_t *data_buf, uint8_t length) -{ - i2c_recv_data(i2c_bus_no, ®, 1, data_buf, length); - return 0; -} - -static int sd3068_read_reg_dma(uint8_t reg, uint8_t *data_buf, uint8_t length) -{ - i2c_recv_data_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, i2c_bus_no, ®, 1, data_buf, length); - return 0; -} - -static uint8_t hex2bcd(uint8_t data) -{ - return data / 10 * 16 + data % 10; -} - -static uint8_t bcd2hex(uint8_t data) -{ - return data / 16 * 10 + data % 16; -} - -int sd3068_write_enable(void) -{ - uint8_t data[2] = {0}; - - data[0] = 0xFF; - data[1] = 0x80; - sd3068_write_reg(0x10, &data[1], 1); - sd3068_write_reg(0x0F, &data[0], 1); - - return 0; -} - -int sd3068_write_enable_dma(void) -{ - uint8_t data[2] = {0}; - - data[0] = 0xFF; - data[1] = 0x80; - sd3068_write_reg_dma(0x10, &data[1], 1); - sd3068_write_reg_dma(0x0F, &data[0], 1); - - return 0; -} - -int sd3068_write_disable(void) -{ - uint8_t data[2] = {0}; - - data[0] = 0x7B; - data[1] = 0; - sd3068_write_reg(0x0F, data, 2); - - return 0; -} - -int sd3068_write_data(uint8_t addr, uint8_t *data_buf, uint8_t length) -{ - addr = ((addr <= 69) ? addr : 69); - length = ((length <= 70 - addr) ? length : 70 - addr); - sd3068_write_reg(0x2C + addr, data_buf, length); - - return 0; -} - -int sd3068_write_data_dma(uint8_t addr, uint8_t *data_buf, uint8_t length) -{ - addr = ((addr <= 69) ? addr : 69); - length = ((length <= 70 - addr) ? length : 70 - addr); - sd3068_write_reg_dma(0x2C + addr, data_buf, length); - - return 0; -} - -int sd3068_read_data(uint8_t addr, uint8_t *data_buf, uint8_t length) -{ - addr = ((addr <= 69) ? addr : 69); - length = ((length <= 70 - addr) ? length : 70 - addr); - sd3068_read_reg(0x2C + addr, data_buf, length); - - return 0; -} - -int sd3068_read_data_dma(uint8_t addr, uint8_t *data_buf, uint8_t length) -{ - addr = ((addr <= 69) ? addr : 69); - length = length <= 70 - addr ? length : 70 - addr; - sd3068_read_reg_dma(0x2C + addr, data_buf, length); - - return 0; -} - -int sd3068_set_time(sd_time_t time) -{ - uint8_t data[7] = {0}; - - data[0] = hex2bcd(time.sec); - data[1] = hex2bcd(time.min); - data[2] = hex2bcd(time.hour) | 0x80; - data[3] = hex2bcd(5); - data[4] = hex2bcd(time.day); - data[5] = hex2bcd(time.month); - data[6] = hex2bcd(time.year); - sd3068_write_reg(0x00, data, 7); - - return 0; -} - -int sd3068_set_time_dma(sd_time_t time) -{ - uint8_t data[7] = {0}; - - data[0] = hex2bcd(time.sec); - data[1] = hex2bcd(time.min); - data[2] = hex2bcd(time.hour) | 0x80; - data[3] = hex2bcd(5); - data[4] = hex2bcd(time.day); - data[5] = hex2bcd(time.month); - data[6] = hex2bcd(time.year); - sd3068_write_reg_dma(0x00, data, 7); - - return 0; -} - -int sd3068_get_time(sd_time_t *time) -{ - uint8_t data[7] = {0}; - - sd3068_read_reg(0x00, data, 7); - time->sec = bcd2hex(data[0]); - time->min = bcd2hex(data[1]); - time->hour = bcd2hex(data[2] & 0x7F); - time->day = bcd2hex(data[4]); - time->month = bcd2hex(data[5]); - time->year = bcd2hex(data[6]); - - return 0; -} - -int sd3068_get_time_dma(sd_time_t *time) -{ - uint8_t data[7] = {0}; - - sd3068_read_reg_dma(0x00, data, 7); - time->sec = bcd2hex(data[0]); - time->min = bcd2hex(data[1]); - time->hour = bcd2hex(data[2] & 0x7F); - time->day = bcd2hex(data[4]); - time->month = bcd2hex(data[5]); - time->year = bcd2hex(data[6]); - - return 0; -} - diff --git a/lib/firmware/w25qxx.c b/lib/firmware/w25qxx.c deleted file mode 100644 index 852537c6..00000000 --- a/lib/firmware/w25qxx.c +++ /dev/null @@ -1,654 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "w25qxx.h" -#include "fpioa.h" -#include "spi.h" -#include "sysctl.h" -#include "dmac.h" - -uint32_t spi_bus_no = 0; -uint32_t spi_chip_select = 0; -static volatile spi_t *spi_handle; - -w25qxx_status_t (*w25qxx_page_program_fun)(uint32_t addr, uint8_t *data_buf, uint32_t length); -w25qxx_status_t (*w25qxx_read_fun)(uint32_t addr, uint8_t *data_buf, uint32_t length); -static w25qxx_status_t w25qxx_stand_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length); -static w25qxx_status_t w25qxx_quad_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length); -static w25qxx_status_t w25qxx_page_program(uint32_t addr, uint8_t *data_buf, uint32_t length); -static w25qxx_status_t w25qxx_quad_page_program(uint32_t addr, uint8_t *data_buf, uint32_t length); -static w25qxx_status_t w25qxx_page_program_dma(uint32_t addr, uint8_t *data_buf, uint32_t length); -static w25qxx_status_t w25qxx_quad_page_program_dma(uint32_t addr, uint8_t *data_buf, uint32_t length); - -static w25qxx_status_t w25qxx_receive_data(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) -{ - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); - spi_receive_data_standard(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_receive_data_dma(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) -{ - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); - spi_receive_data_standard_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_send_data(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) -{ - spi_send_data_standard(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_send_data_dma(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) -{ - spi_send_data_standard_dma(DMAC_CHANNEL0, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_receive_data_enhanced(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) -{ - spi_receive_data_multiple(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_receive_data_enhanced_dma(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len) -{ - spi_receive_data_multiple_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len); - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_send_data_enhanced(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) -{ - spi_send_data_multiple(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_send_data_enhanced_dma(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len) -{ - spi_send_data_multiple_dma(DMAC_CHANNEL0, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len); - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_init(uint8_t spi_index, uint8_t spi_ss) -{ - spi_bus_no = spi_index; - spi_chip_select = spi_ss; - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); - w25qxx_page_program_fun = w25qxx_page_program; - w25qxx_read_fun = w25qxx_stand_read_data; - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_init_dma(uint8_t spi_index, uint8_t spi_ss) -{ - spi_bus_no = spi_index; - spi_chip_select = spi_ss; - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); - w25qxx_page_program_fun = w25qxx_page_program_dma; - w25qxx_read_fun = w25qxx_stand_read_data; - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_read_id(uint8_t *manuf_id, uint8_t *device_id) -{ - uint8_t cmd[4] = {READ_ID, 0x00, 0x00, 0x00}; - uint8_t data[2] = {0}; - - w25qxx_receive_data(cmd, 4, data, 2); - *manuf_id = data[0]; - *device_id = data[1]; - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_read_id_dma(uint8_t *manuf_id, uint8_t *device_id) -{ - uint8_t cmd[4] = {READ_ID, 0x00, 0x00, 0x00}; - uint8_t data[2] = {0}; - - w25qxx_receive_data_dma(cmd, 4, data, 2); - *manuf_id = data[0]; - *device_id = data[1]; - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_write_enable(void) -{ - uint8_t cmd[1] = {WRITE_ENABLE}; - - w25qxx_send_data(cmd, 1, 0, 0); - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_write_enable_dma(void) -{ - uint8_t cmd[1] = {WRITE_ENABLE}; - - w25qxx_send_data_dma(cmd, 1, 0, 0); - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_write_status_reg(uint8_t reg1_data, uint8_t reg2_data) -{ - uint8_t cmd[3] = {WRITE_REG1, reg1_data, reg2_data}; - - w25qxx_write_enable(); - w25qxx_send_data(cmd, 3, 0, 0); - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_write_status_reg_dma(uint8_t reg1_data, uint8_t reg2_data) -{ - uint8_t cmd[3] = {WRITE_REG1, reg1_data, reg2_data}; - - w25qxx_write_enable_dma(); - w25qxx_send_data_dma(cmd, 3, 0, 0); - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_read_status_reg1(uint8_t *reg_data) -{ - uint8_t cmd[1] = {READ_REG1}; - uint8_t data[1] = {0}; - - w25qxx_receive_data(cmd, 1, data, 1); - *reg_data = data[0]; - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_read_status_reg1_dma(uint8_t *reg_data) -{ - uint8_t cmd[1] = {READ_REG1}; - uint8_t data[1] = {0}; - - w25qxx_receive_data_dma(cmd, 1, data, 1); - *reg_data = data[0]; - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_read_status_reg2(uint8_t *reg_data) -{ - uint8_t cmd[1] = {READ_REG2}; - uint8_t data[1] = {0}; - - w25qxx_receive_data(cmd, 1, data, 1); - *reg_data = data[0]; - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_read_status_reg2_dma(uint8_t *reg_data) -{ - uint8_t cmd[1] = {READ_REG2}; - uint8_t data[1] = {0}; - - w25qxx_receive_data_dma(cmd, 1, data, 1); - *reg_data = data[0]; - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_is_busy(void) -{ - uint8_t status = 0; - - w25qxx_read_status_reg1(&status); - if (status & REG1_BUSY_MASK) - return W25QXX_BUSY; - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_is_busy_dma(void) -{ - uint8_t status = 0; - - w25qxx_read_status_reg1_dma(&status); - if (status & REG1_BUSY_MASK) - return W25QXX_BUSY; - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_sector_erase(uint32_t addr) -{ - uint8_t cmd[4] = {SECTOR_ERASE}; - - cmd[1] = (uint8_t)(addr >> 16); - cmd[2] = (uint8_t)(addr >> 8); - cmd[3] = (uint8_t)(addr); - w25qxx_write_enable(); - w25qxx_send_data(cmd, 4, 0, 0); - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_sector_erase_dma(uint32_t addr) -{ - uint8_t cmd[4] = {SECTOR_ERASE}; - - cmd[1] = (uint8_t)(addr >> 16); - cmd[2] = (uint8_t)(addr >> 8); - cmd[3] = (uint8_t)(addr); - w25qxx_write_enable_dma(); - w25qxx_send_data_dma(cmd, 4, 0, 0); - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_32k_block_erase(uint32_t addr) -{ - uint8_t cmd[4] = {BLOCK_32K_ERASE}; - - cmd[1] = (uint8_t)(addr >> 16); - cmd[2] = (uint8_t)(addr >> 8); - cmd[3] = (uint8_t)(addr); - w25qxx_write_enable(); - w25qxx_send_data(cmd, 4, 0, 0); - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_64k_block_erase(uint32_t addr) -{ - uint8_t cmd[4] = {BLOCK_64K_ERASE}; - - cmd[1] = (uint8_t)(addr >> 16); - cmd[2] = (uint8_t)(addr >> 8); - cmd[3] = (uint8_t)(addr); - w25qxx_write_enable(); - w25qxx_send_data(cmd, 4, 0, 0); - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_chip_erase(void) -{ - uint8_t cmd[1] = {CHIP_ERASE}; - - w25qxx_write_enable(); - w25qxx_send_data(cmd, 1, 0, 0); - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_enable_quad_mode(void) -{ - uint8_t reg_data = 0; - - w25qxx_read_status_reg2(®_data); - if (!(reg_data & REG2_QUAL_MASK)) - { - reg_data |= REG2_QUAL_MASK; - w25qxx_write_status_reg(0x00, reg_data); - } - w25qxx_page_program_fun = w25qxx_quad_page_program; - w25qxx_read_fun = w25qxx_quad_read_data; - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_enable_quad_mode_dma(void) -{ - uint8_t reg_data = 0; - - w25qxx_read_status_reg2_dma(®_data); - if (!(reg_data & REG2_QUAL_MASK)) - { - reg_data |= REG2_QUAL_MASK; - w25qxx_write_status_reg_dma(0x00, reg_data); - } - w25qxx_page_program_fun = w25qxx_quad_page_program_dma; - w25qxx_read_fun = w25qxx_quad_read_data; - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_disable_quad_mode(void) -{ - uint8_t reg_data = 0; - - w25qxx_read_status_reg2(®_data); - if (reg_data & REG2_QUAL_MASK) - { - reg_data &= (~REG2_QUAL_MASK); - w25qxx_write_status_reg(0x00, reg_data); - } - w25qxx_page_program_fun = w25qxx_page_program; - w25qxx_read_fun = w25qxx_stand_read_data; - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_page_program(uint32_t addr, uint8_t *data_buf, uint32_t length) -{ - uint8_t cmd[4] = {PAGE_PROGRAM}; - - cmd[1] = (uint8_t)(addr >> 16); - cmd[2] = (uint8_t)(addr >> 8); - cmd[3] = (uint8_t)(addr); - w25qxx_write_enable(); - w25qxx_send_data(cmd, 4, data_buf, length); - while (w25qxx_is_busy() == W25QXX_BUSY) - ; - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_page_program_dma(uint32_t addr, uint8_t *data_buf, uint32_t length) -{ - uint8_t cmd[4] = {PAGE_PROGRAM}; - - cmd[1] = (uint8_t)(addr >> 16); - cmd[2] = (uint8_t)(addr >> 8); - cmd[3] = (uint8_t)(addr); - w25qxx_write_enable_dma(); - w25qxx_send_data_dma(cmd, 4, data_buf, length); - while (w25qxx_is_busy_dma() == W25QXX_BUSY) - ; - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_quad_page_program(uint32_t addr, uint8_t *data_buf, uint32_t length) -{ - uint32_t cmd[2] = {0}; - - cmd[0] = QUAD_PAGE_PROGRAM; - cmd[1] = addr; - w25qxx_write_enable(); - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/, - SPI_AITM_STANDARD/*spi address trans mode*/); - w25qxx_send_data_enhanced(cmd, 2, data_buf, length); - while (w25qxx_is_busy() == W25QXX_BUSY) - ; - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_quad_page_program_dma(uint32_t addr, uint8_t *data_buf, uint32_t length) -{ - uint32_t cmd[2] = {0}; - - cmd[0] = QUAD_PAGE_PROGRAM; - cmd[1] = addr; - w25qxx_write_enable_dma(); - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/, - SPI_AITM_STANDARD/*spi address trans mode*/); - w25qxx_send_data_enhanced_dma(cmd, 2, data_buf, length); - while (w25qxx_is_busy_dma() == W25QXX_BUSY) - ; - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_sector_program(uint32_t addr, uint8_t *data_buf) -{ - uint8_t index = 0; - - for (index = 0; index < w25qxx_FLASH_PAGE_NUM_PER_SECTOR; index++) - { - w25qxx_page_program_fun(addr, data_buf, w25qxx_FLASH_PAGE_SIZE); - addr += w25qxx_FLASH_PAGE_SIZE; - data_buf += w25qxx_FLASH_PAGE_SIZE; - } - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_write_data(uint32_t addr, uint8_t *data_buf, uint32_t length) -{ - uint32_t sector_addr = 0; - uint32_t sector_offset = 0; - uint32_t sector_remain = 0; - uint32_t write_len = 0; - uint32_t index = 0; - uint8_t *pread = NULL; - uint8_t *pwrite = NULL; - uint8_t swap_buf[w25qxx_FLASH_SECTOR_SIZE] = {0}; - - while (length) - { - sector_addr = addr & (~(w25qxx_FLASH_SECTOR_SIZE - 1)); - sector_offset = addr & (w25qxx_FLASH_SECTOR_SIZE - 1); - sector_remain = w25qxx_FLASH_SECTOR_SIZE - sector_offset; - write_len = ((length < sector_remain) ? length : sector_remain); - w25qxx_read_fun(sector_addr, swap_buf, w25qxx_FLASH_SECTOR_SIZE); - pread = swap_buf + sector_offset; - pwrite = data_buf; - for (index = 0; index < write_len; index++) - { - if ((*pwrite) != ((*pwrite) & (*pread))) - { - w25qxx_sector_erase(sector_addr); - while (w25qxx_is_busy() == W25QXX_BUSY) - ; - break; - } - pwrite++; - pread++; - } - if (write_len == w25qxx_FLASH_SECTOR_SIZE) - { - w25qxx_sector_program(sector_addr, data_buf); - } - else - { - pread = swap_buf + sector_offset; - pwrite = data_buf; - for (index = 0; index < write_len; index++) - *pread++ = *pwrite++; - w25qxx_sector_program(sector_addr, swap_buf); - } - length -= write_len; - addr += write_len; - data_buf += write_len; - } - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_write_data_direct(uint32_t addr, uint8_t *data_buf, uint32_t length) -{ - uint32_t page_remain = 0; - uint32_t write_len = 0; - - while (length) - { - page_remain = w25qxx_FLASH_PAGE_SIZE - (addr & (w25qxx_FLASH_PAGE_SIZE - 1)); - write_len = ((length < page_remain) ? length : page_remain); - w25qxx_page_program_fun(addr, data_buf, write_len); - length -= write_len; - addr += write_len; - data_buf += write_len; - } - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_write_data_direct_dma(uint32_t addr, uint8_t *data_buf, uint32_t length) -{ - uint32_t page_remain = 0; - uint32_t write_len = 0; - - while (length) - { - page_remain = w25qxx_FLASH_PAGE_SIZE - (addr & (w25qxx_FLASH_PAGE_SIZE - 1)); - write_len = ((length < page_remain) ? length : page_remain); - w25qxx_page_program_fun(addr, data_buf, write_len); - length -= write_len; - addr += write_len; - data_buf += write_len; - } - return W25QXX_OK; -} - -static w25qxx_status_t _w25qxx_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length, w25qxx_read_t mode) -{ - uint32_t cmd[2] = {0}; - - switch (mode) - { - case W25QXX_STANDARD: - *(((uint8_t *)cmd) + 0) = READ_DATA; - *(((uint8_t *)cmd) + 1) = (uint8_t)(addr >> 16); - *(((uint8_t *)cmd) + 2) = (uint8_t)(addr >> 8); - *(((uint8_t *)cmd) + 3) = (uint8_t)(addr >> 0); - w25qxx_receive_data((uint8_t *)cmd, 4, data_buf, length); - break; - case W25QXX_STANDARD_FAST: - *(((uint8_t *)cmd) + 0) = FAST_READ; - *(((uint8_t *)cmd) + 1) = (uint8_t)(addr >> 16); - *(((uint8_t *)cmd) + 2) = (uint8_t)(addr >> 8); - *(((uint8_t *)cmd) + 3) = (uint8_t)(addr >> 0); - *(((uint8_t *)cmd) + 4) = 0xFF; - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH); - w25qxx_receive_data((uint8_t *)cmd, 5, data_buf, length); - break; - case W25QXX_DUAL: - cmd[0] = FAST_READ_DUAL_OUTPUT; - cmd[1] = addr; - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); - spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, - SPI_AITM_STANDARD/*spi address trans mode*/); - w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); - break; - case W25QXX_DUAL_FAST: - cmd[0] = FAST_READ_DUAL_IO; - cmd[1] = addr << 8; - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); - spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, - SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); - w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); - break; - case W25QXX_QUAD: - cmd[0] = FAST_READ_QUAL_OUTPUT; - cmd[1] = addr; - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, - SPI_AITM_STANDARD/*spi address trans mode*/); - w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); - break; - case W25QXX_QUAD_FAST: - cmd[0] = FAST_READ_QUAL_IO; - cmd[1] = addr << 8; - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, - SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); - w25qxx_receive_data_enhanced(cmd, 2, data_buf, length); - break; - } - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_read_data_dma_less_1000bytes(uint32_t addr, uint8_t *data_buf, uint32_t length, w25qxx_read_t mode) -{ - uint32_t cmd[2] = {0}; - - switch (mode) { - case W25QXX_STANDARD: - *(((uint8_t *)cmd) + 0) = READ_DATA; - *(((uint8_t *)cmd) + 1) = (uint8_t)(addr >> 16); - *(((uint8_t *)cmd) + 2) = (uint8_t)(addr >> 8); - *(((uint8_t *)cmd) + 3) = (uint8_t)(addr >> 0); - w25qxx_receive_data_dma((uint8_t *)cmd, 4, data_buf, length); - break; - case W25QXX_STANDARD_FAST: - *(((uint8_t *)cmd) + 0) = FAST_READ; - *(((uint8_t *)cmd) + 1) = (uint8_t)(addr >> 16); - *(((uint8_t *)cmd) + 2) = (uint8_t)(addr >> 8); - *(((uint8_t *)cmd) + 3) = (uint8_t)(addr >> 0); - *(((uint8_t *)cmd) + 4) = 0xFF; - w25qxx_receive_data_dma((uint8_t *)cmd, 5, data_buf, length); - break; - case W25QXX_DUAL: - cmd[0] = FAST_READ_DUAL_OUTPUT; - cmd[1] = addr; - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); - spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, - SPI_AITM_STANDARD/*spi address trans mode*/); - w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); - break; - case W25QXX_DUAL_FAST: - cmd[0] = FAST_READ_DUAL_IO; - cmd[1] = addr << 8; - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH); - spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, - SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); - w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); - break; - case W25QXX_QUAD: - cmd[0] = FAST_READ_QUAL_OUTPUT; - cmd[1] = addr; - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/, - SPI_AITM_STANDARD/*spi address trans mode*/); - w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); - break; - case W25QXX_QUAD_FAST: - cmd[0] = FAST_READ_QUAL_IO; - cmd[1] = addr << 8; - spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH); - spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/, - SPI_AITM_ADDR_STANDARD/*spi address trans mode*/); - w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length); - break; - } - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length, w25qxx_read_t mode) -{ - uint32_t len = 0; - - while (length) - { - len = ((length >= 0x010000) ? 0x010000 : length); - _w25qxx_read_data(addr, data_buf, len, mode); - addr += len; - data_buf += len; - length -= len; - } - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_read_data_dma(uint32_t addr, uint8_t *data_buf, uint32_t length, w25qxx_read_t mode) -{ - uint32_t len = 0; - - while (length) - { - len = ((length >= 0x010000) ? 0x010000 : length); - w25qxx_read_data_dma_less_1000bytes(addr, data_buf, len, mode); - addr += len; - data_buf += len; - length -= len; - } - return W25QXX_OK; -} - -static w25qxx_status_t w25qxx_stand_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length) -{ - return w25qxx_read_data(addr, data_buf, length, W25QXX_STANDARD_FAST); -} - -static w25qxx_status_t w25qxx_quad_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length) -{ - return w25qxx_read_data(addr, data_buf, length, W25QXX_QUAD_FAST); -} - -w25qxx_status_t w25qxx_enable_xip_mode(void) -{ - if (spi_handle != spi[3]) - return W25QXX_ERROR; - - spi_handle->xip_ctrl = (0x01 << 29) | (0x02 << 26) | (0x01 << 23) | (0x01 << 22) | (0x04 << 13) | - (0x01 << 12) | (0x02 << 9) | (0x06 << 4) | (0x01 << 2) | 0x02; - spi_handle->xip_incr_inst = 0xEB; - spi_handle->xip_mode_bits = 0x00; - spi_handle->xip_ser = 0x01; - spi_handle->ssienr = 0x01; - sysctl->peri.spi3_xip_en = 1; - return W25QXX_OK; -} - -w25qxx_status_t w25qxx_disable_xip_mode(void) -{ - sysctl->peri.spi3_xip_en = 0; - return W25QXX_OK; -} - From a2701b86ef0fb807fbab4a70ddde8e5c9a51f074 Mon Sep 17 00:00:00 2001 From: jiangxiangbing Date: Tue, 9 Oct 2018 20:58:39 +0800 Subject: [PATCH 49/58] update AES API --- lib/drivers/aes.c | 211 +++++++++++++++++++------- lib/drivers/include/aes.h | 301 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 444 insertions(+), 68 deletions(-) diff --git a/lib/drivers/aes.c b/lib/drivers/aes.c index 3383c81e..ddd84d31 100644 --- a/lib/drivers/aes.c +++ b/lib/drivers/aes.c @@ -68,7 +68,31 @@ static uint32_t gcm_get_tag_chk(void) return aes->tag_chk; } -static void gcm_get_tag(uint8_t *gcm_tag) +static void gcm_clear_chk_tag(void) +{ + aes->tag_clear = 0; +} + +static uint32_t gcm_check_tag(uint32_t *gcm_tag) +{ + while (!gcm_get_tag_in_flag()) + ; + gcm_write_tag(gcm_tag); + while (!gcm_get_tag_chk()) + ; + if (gcm_get_tag_chk() == 0x2) + { + gcm_clear_chk_tag(); + return 1; + } + else + { + gcm_clear_chk_tag(); + return 0; + } +} + +void gcm_get_tag(uint8_t *gcm_tag) { uint32_t uint32_tag; uint8_t i = 0; @@ -96,42 +120,14 @@ static void gcm_get_tag(uint8_t *gcm_tag) gcm_tag[i++] = (uint8_t)((uint32_tag >> 16) & 0xff); gcm_tag[i++] = (uint8_t)((uint32_tag >> 8) & 0xff); gcm_tag[i++] = (uint8_t)((uint32_tag)&0xff); -} -static void gcm_clear_chk_tag(void) -{ - aes->tag_clear = 0; + gcm_check_tag((uint32_t *)gcm_tag); } -static uint32_t gcm_check_tag(uint32_t *gcm_tag) -{ - while (!gcm_get_tag_in_flag()) - ; - gcm_write_tag(gcm_tag); - while (!gcm_get_tag_chk()) - ; - if (gcm_get_tag_chk() == 0x2) - { - gcm_clear_chk_tag(); - return 1; - } - else - { - gcm_clear_chk_tag(); - return 0; - } -} -static void aes_init(uint8_t *input_key, size_t input_key_len, uint8_t *iv, - size_t iv_len, uint8_t *gcm_aad, aes_cipher_mode_t cipher_mode, - aes_encrypt_sel_t encrypt_sel, size_t gcm_aad_len, size_t input_data_len) +void aes_init(uint8_t *input_key, size_t input_key_len, uint8_t *iv,size_t iv_len, uint8_t *gcm_aad, + aes_cipher_mode_t cipher_mode, aes_encrypt_sel_t encrypt_sel, size_t gcm_aad_len, size_t input_data_len) { - configASSERT(input_key_len == AES_128 || input_key_len == AES_192 || input_key_len == AES_256); - if (cipher_mode == AES_CBC) - configASSERT(iv_len == 16); - if (cipher_mode == AES_GCM) - configASSERT(iv_len == 12); - size_t remainder, uint32_num, uint8_num, i; uint32_t uint32_data; uint8_t uint8_data[4] = {0}; @@ -282,7 +278,7 @@ static void process_less_80_bytes(uint8_t *input_data, uint8_t *output_data, siz } } -static void aes_process(uint8_t *input_data, uint8_t *output_data, size_t input_data_len, aes_cipher_mode_t cipher_mode) +void aes_process(uint8_t *input_data, uint8_t *output_data, size_t input_data_len, aes_cipher_mode_t cipher_mode) { size_t temp_len = 0; uint32_t i = 0; @@ -297,32 +293,135 @@ static void aes_process(uint8_t *input_data, uint8_t *output_data, size_t input_ process_less_80_bytes(&input_data[i * 80], &output_data[i * 80], temp_len, cipher_mode); } -void aes_hard_decrypt(aes_param_t *param) +void aes_ecb128_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data) { - size_t padding_len = param->input_data_len; - if (param->cipher_mode == AES_CBC || param->cipher_mode == AES_ECB) - { - padding_len = ((padding_len + 15) / 16) * 16; - } - aes_init(param->input_key, param->input_key_len, param->iv, param->iv_len, param->gcm_aad, - param->cipher_mode, AES_HARD_DECRYPTION, param->gcm_aad_len, param->input_data_len); - aes_process(param->input_data, param->output_data, padding_len, param->cipher_mode); - if (param->cipher_mode == AES_GCM) - { - gcm_get_tag(param->gcm_tag); - gcm_check_tag((uint32_t *)param->gcm_tag); - } + size_t padding_len = ((input_len + 15) / 16) * 16; + aes_init(input_key, AES_128, NULL, 0L, NULL, AES_ECB, AES_HARD_DECRYPTION, 0L, input_len); + aes_process(input_data, output_data, padding_len, AES_ECB); } -void aes_hard_encrypt(aes_param_t *param) +void aes_ecb128_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data) { - aes_init(param->input_key, param->input_key_len, param->iv, param->iv_len, param->gcm_aad, - param->cipher_mode, AES_HARD_ENCRYPTION, param->gcm_aad_len, param->input_data_len); - aes_process(param->input_data, param->output_data, param->input_data_len, param->cipher_mode); - if (param->cipher_mode == AES_GCM) - { - gcm_get_tag(param->gcm_tag); - gcm_check_tag((uint32_t *)param->gcm_tag); - } + size_t padding_len = ((input_len + 15) / 16) * 16; + aes_init(input_key, AES_128, NULL, 0L, NULL, AES_ECB, AES_HARD_ENCRYPTION, 0L, input_len); + aes_process(input_data, output_data, padding_len, AES_ECB); +} + +void aes_ecb192_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data) +{ + size_t padding_len = ((input_len + 15) / 16) * 16; + aes_init(input_key, AES_192, NULL, 0L, NULL, AES_ECB, AES_HARD_DECRYPTION, 0L, input_len); + aes_process(input_data, output_data, padding_len, AES_ECB); +} + +void aes_ecb192_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data) +{ + size_t padding_len = ((input_len + 15) / 16) * 16; + aes_init(input_key, AES_192, NULL, 0L, NULL, AES_ECB, AES_HARD_ENCRYPTION, 0L, input_len); + aes_process(input_data, output_data, padding_len, AES_ECB); +} + +void aes_ecb256_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data) +{ + size_t padding_len = ((input_len + 15) / 16) * 16; + aes_init(input_key, AES_256, NULL, 0L, NULL, AES_ECB, AES_HARD_DECRYPTION, 0L, input_len); + aes_process(input_data, output_data, padding_len, AES_ECB); +} + +void aes_ecb256_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data) +{ + size_t padding_len = ((input_len + 15) / 16) * 16; + aes_init(input_key, AES_256, NULL, 0L, NULL, AES_ECB, AES_HARD_ENCRYPTION, 0L, input_len); + aes_process(input_data, output_data, padding_len, AES_ECB); +} + +void aes_cbc128_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data) +{ + size_t padding_len = ((input_len + 15) / 16) * 16; + aes_init(context->input_key, AES_128, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_DECRYPTION, 0L, input_len); + aes_process(input_data, output_data, padding_len, AES_CBC); +} + +void aes_cbc128_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data) +{ + size_t padding_len = ((input_len + 15) / 16) * 16; + aes_init(context->input_key, AES_128, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_ENCRYPTION, 0L, input_len); + aes_process(input_data, output_data, padding_len, AES_CBC); +} + +void aes_cbc192_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data) +{ + size_t padding_len = ((input_len + 15) / 16) * 16; + aes_init(context->input_key, AES_192, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_DECRYPTION, 0L, input_len); + aes_process(input_data, output_data, padding_len, AES_CBC); +} + +void aes_cbc192_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data) +{ + size_t padding_len = ((input_len + 15) / 16) * 16; + aes_init(context->input_key, AES_192, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_ENCRYPTION, 0L, input_len); + aes_process(input_data, output_data, padding_len, AES_CBC); +} + +void aes_cbc256_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data) +{ + size_t padding_len = ((input_len + 15) / 16) * 16; + aes_init(context->input_key, AES_256, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_DECRYPTION, 0L, input_len); + aes_process(input_data, output_data, padding_len, AES_CBC); +} + +void aes_cbc256_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data) +{ + size_t padding_len = ((input_len + 15) / 16) * 16; + aes_init(context->input_key, AES_256, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_ENCRYPTION, 0L, input_len); + aes_process(input_data, output_data, padding_len, AES_CBC); +} + +void aes_gcm128_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag) +{ + aes_init(context->input_key, AES_128, context->iv, IV_LEN_96, context->gcm_aad, + AES_GCM, AES_HARD_DECRYPTION, context->gcm_aad_len, input_len); + aes_process(input_data, output_data, input_len, AES_GCM); + gcm_get_tag(gcm_tag); +} + +void aes_gcm128_hard_encrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag) +{ + aes_init(context->input_key, AES_128, context->iv, IV_LEN_96, context->gcm_aad, + AES_GCM, AES_HARD_ENCRYPTION, context->gcm_aad_len, input_len); + aes_process(input_data, output_data, input_len, AES_GCM); + gcm_get_tag(gcm_tag); +} + +void aes_gcm192_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag) +{ + aes_init(context->input_key, AES_192, context->iv, IV_LEN_96, context->gcm_aad, + AES_GCM, AES_HARD_DECRYPTION, context->gcm_aad_len, input_len); + aes_process(input_data, output_data, input_len, AES_GCM); + gcm_get_tag(gcm_tag); +} + +void aes_gcm192_hard_encrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag) +{ + aes_init(context->input_key, AES_192, context->iv, IV_LEN_96, context->gcm_aad, + AES_GCM, AES_HARD_ENCRYPTION, context->gcm_aad_len, input_len); + aes_process(input_data, output_data, input_len, AES_GCM); + gcm_get_tag(gcm_tag); +} + +void aes_gcm256_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag) +{ + aes_init(context->input_key, AES_256, context->iv, IV_LEN_96, context->gcm_aad, + AES_GCM, AES_HARD_DECRYPTION, context->gcm_aad_len, input_len); + aes_process(input_data, output_data, input_len, AES_GCM); + gcm_get_tag(gcm_tag); +} + +void aes_gcm256_hard_encrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag) +{ + aes_init(context->input_key, AES_256, context->iv, IV_LEN_96, context->gcm_aad, + AES_GCM, AES_HARD_ENCRYPTION, context->gcm_aad_len, input_len); + aes_process(input_data, output_data, input_len, AES_GCM); + gcm_get_tag(gcm_tag); } diff --git a/lib/drivers/include/aes.h b/lib/drivers/include/aes.h index ea4cb469..0cbac8e9 100644 --- a/lib/drivers/include/aes.h +++ b/lib/drivers/include/aes.h @@ -36,6 +36,12 @@ typedef enum _aes_kmode AES_256 = 32, } aes_kmode_t; +typedef enum _aes_iv_len +{ + IV_LEN_96 = 12, + IV_LEN_128 = 16, +} aes_iv_len_t; + typedef enum _aes_encrypt_sel { AES_HARD_ENCRYPTION = 0, @@ -68,7 +74,7 @@ typedef struct _aes uint32_t encrypt_sel; /* (0x14) aes mode reg */ aes_mode_ctl_t mode_ctl; - /* (0x18) Initialisation Vector */ + /* (0x18) Initialisation Vector. GCM support 96bit. CBC support 128bit */ uint32_t aes_iv[4]; /* (0x28) input data endian;1:little endian; 0:big endian */ uint32_t aes_endian; @@ -109,23 +115,294 @@ typedef struct _aes uint32_t aes_key_ext[4]; } __attribute__((packed, aligned(4))) aes_t; -typedef struct _aes_param +typedef struct _gcm_context { - uint8_t *input_data; - size_t input_data_len; + /* The buffer holding the encryption or decryption key. */ uint8_t *input_key; - size_t input_key_len; + /* The initialization vector. must be 96 bit */ uint8_t *iv; - uint8_t iv_len; + /* The buffer holding the Additional authenticated data. or NULL */ uint8_t *gcm_aad; + /* The length of the Additional authenticated data. or 0L */ size_t gcm_aad_len; - aes_cipher_mode_t cipher_mode; - uint8_t *output_data; - uint8_t *gcm_tag; -} aes_param_t; +} gcm_context_t; + +typedef struct _cbc_context +{ + /* The buffer holding the encryption or decryption key. */ + uint8_t *input_key; + /* The initialization vector. must be 128 bit */ + uint8_t *iv; +} cbc_context_t; -void aes_hard_decrypt(aes_param_t *param); -void aes_hard_encrypt(aes_param_t *param); +/** + * @brief AES-ECB-128 decryption + * + * @param[in] input_key The decryption key. must be 16bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + */ +void aes_ecb128_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data); + +/** + * @brief AES-ECB-128 encryption + * + * @param[in] input_key The encryption key. must be 16bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + */ +void aes_ecb128_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data); + +/** + * @brief AES-ECB-192 decryption + * + * @param[in] input_key The decryption key. must be 24bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + */ +void aes_ecb192_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data); + +/** + * @brief AES-ECB-192 encryption + * + * @param[in] input_key The encryption key. must be 24bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + */ +void aes_ecb192_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data); + +/** + * @brief AES-ECB-256 decryption + * + * @param[in] input_key The decryption key. must be 32bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + */ +void aes_ecb256_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data); + +/** + * @brief AES-ECB-256 encryption + * + * @param[in] input_key The encryption key. must be 32bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + */ +void aes_ecb256_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data); + +/** + * @brief AES-CBC-128 decryption + * + * @param[in] context The cbc context to use for encryption or decryption. + * @param[in] input_key The decryption key. must be 16bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + */ +void aes_cbc128_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data); + +/** + * @brief AES-CBC-128 encryption + * + * @param[in] context The cbc context to use for encryption or decryption. + * @param[in] input_key The encryption key. must be 16bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + */ +void aes_cbc128_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data); + +/** + * @brief AES-CBC-192 decryption + * + * @param[in] context The cbc context to use for encryption or decryption. + * @param[in] input_key The decryption key. must be 24bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + */ +void aes_cbc192_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data); + +/** + * @brief AES-CBC-192 encryption + * + * @param[in] context The cbc context to use for encryption or decryption. + * @param[in] input_key The encryption key. must be 24bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + */ +void aes_cbc192_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data); + +/** + * @brief AES-CBC-256 decryption + * + * @param[in] context The cbc context to use for encryption or decryption. + * @param[in] input_key The decryption key. must be 32bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + */ +void aes_cbc256_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data); + +/** + * @brief AES-CBC-256 encryption + * + * @param[in] context The cbc context to use for encryption or decryption. + * @param[in] input_key The encryption key. must be 32bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + */ +void aes_cbc256_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data); + +/** + * @brief AES-GCM-128 decryption + * + * @param[in] context The gcm context to use for encryption or decryption. + * @param[in] input_key The decryption key. must be 16bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + * @param[out] gcm_tag The buffer for holding the tag.The length of the tag must be 4 bytes. + */ +void aes_gcm128_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag); + +/** + * @brief AES-GCM-128 encryption + * + * @param[in] context The gcm context to use for encryption or decryption. + * @param[in] input_key The encryption key. must be 16bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + * @param[out] gcm_tag The buffer for holding the tag.The length of the tag must be 4 bytes. + */ +void aes_gcm128_hard_encrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag); + +/** + * @brief AES-GCM-192 decryption + * + * @param[in] context The gcm context to use for encryption or decryption. + * @param[in] input_key The decryption key. must be 24bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + * @param[out] gcm_tag The buffer for holding the tag.The length of the tag must be 4 bytes. + */ +void aes_gcm192_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag); + +/** + * @brief AES-GCM-192 encryption + * + * @param[in] context The gcm context to use for encryption or decryption. + * @param[in] input_key The encryption key. must be 24bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + * @param[out] gcm_tag The buffer for holding the tag.The length of the tag must be 4 bytes. + */ +void aes_gcm192_hard_encrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag); + +/** + * @brief AES-GCM-256 decryption + * + * @param[in] context The gcm context to use for encryption or decryption. + * @param[in] input_key The decryption key. must be 32bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + * @param[out] gcm_tag The buffer for holding the tag.The length of the tag must be 4 bytes. + */ +void aes_gcm256_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag); + +/** + * @brief AES-GCM-256 encryption + * + * @param[in] context The gcm context to use for encryption or decryption. + * @param[in] input_key The encryption key. must be 32bytes. + * @param[in] input_data The buffer holding the input data. + * @param[in] input_len The length of a data unit in bytes. + * This can be any length between 16 bytes and 2^31 bytes inclusive + * (between 1 and 2^27 block cipher blocks). + * @param[out] output_data The buffer holding the output data. + * @param[out] gcm_tag The buffer for holding the tag.The length of the tag must be 4 bytes. + */ +void aes_gcm256_hard_encrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag); + +/** + * @brief This function initializes the AES hard module. + * + * @param[in] input_key The buffer holding the encryption or decryption key. + * @param[in] input_key_len The length of the input_key.must be 16bytes || 24bytes || 32bytes. + * @param[in] iv The initialization vector. + * @param[in] iv_len The length of the iv.GCM must be 12bytes. CBC must be 16bytes. ECB set 0L. + * @param[in] gcm_aad The buffer holding the Additional authenticated data. or NULL + * @param[in] cipher_mode Cipher Modes.must be AES_CBC || AES_ECB || AES_GCM. + * Other cipher modes, please look forward to the next generation of kendryte. + * @param[in] encrypt_sel The operation to perform:encryption or decryption. + * @param[in] gcm_aad_len The length of the gcm_aad. + * @param[in] input_data_len The length of the input_data. + */ +void aes_init(uint8_t *input_key, size_t input_key_len, uint8_t *iv,size_t iv_len, uint8_t *gcm_aad, + aes_cipher_mode_t cipher_mode, aes_encrypt_sel_t encrypt_sel, size_t gcm_aad_len, size_t input_data_len); + +/** + * @brief This function feeds an input buffer into an encryption or decryption operation. + * + * @param[in] input_data The buffer holding the input data. + * @param[out] output_data The buffer holding the output data. + * @param[in] input_data_len The length of the input_data. + * @param[in] cipher_mode Cipher Modes.must be AES_CBC || AES_ECB || AES_GCM. + * Other cipher modes, please look forward to the next generation of kendryte. + */ +void aes_process(uint8_t *input_data, uint8_t *output_data, size_t input_data_len, aes_cipher_mode_t cipher_mode); + +/** + * @brief This function get the gcm tag to verify. + * + * @param[out] gcm_tag The buffer holding the gcm tag.The length of the tag must be 16bytes. + */ +void gcm_get_tag(uint8_t *gcm_tag); #ifdef __cplusplus } From 428707d3ad9b4176bde25f631bc8c2441e4ae2dc Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Tue, 9 Oct 2018 21:05:20 +0800 Subject: [PATCH 50/58] Spi add endian, i2c add clk rate --- lib/drivers/i2c.c | 22 ++++++++++------------ lib/drivers/include/i2c.h | 4 ++-- lib/drivers/include/spi.h | 3 ++- lib/drivers/spi.c | 3 ++- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/lib/drivers/i2c.c b/lib/drivers/i2c.c index a899894c..857979a0 100644 --- a/lib/drivers/i2c.c +++ b/lib/drivers/i2c.c @@ -36,29 +36,27 @@ static void i2c_clk_init(i2c_device_number_t i2c_num) } void i2c_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width, - i2c_bus_speed_mode_t bus_speed_mode) + uint32_t i2c_clk) { configASSERT(i2c_num < I2C_MAX_NUM); configASSERT(address_width == 7 || address_width == 10); volatile i2c_t *i2c_adapter = i2c[i2c_num]; - int speed_mode = 1; i2c_clk_init(i2c_num); - switch (bus_speed_mode) { - case I2C_BS_STANDARD: - speed_mode = 1; - break; - default: - break; - } + uint32_t v_i2c_freq = sysctl_clock_get_freq(SYSCTL_CLOCK_I2C0 + i2c_num); + uint16_t v_period_clk_cnt = v_i2c_freq / i2c_clk / 2; + + if(v_period_clk_cnt == 0) + v_period_clk_cnt = 1; i2c_adapter->enable = 0; i2c_adapter->con = I2C_CON_MASTER_MODE | I2C_CON_SLAVE_DISABLE | I2C_CON_RESTART_EN | - (address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(speed_mode); - i2c_adapter->ss_scl_hcnt = I2C_SS_SCL_HCNT_COUNT(37); - i2c_adapter->ss_scl_lcnt = I2C_SS_SCL_LCNT_COUNT(40); + (address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(1); + i2c_adapter->ss_scl_hcnt = I2C_SS_SCL_HCNT_COUNT(v_period_clk_cnt); + i2c_adapter->ss_scl_lcnt = I2C_SS_SCL_LCNT_COUNT(v_period_clk_cnt); + i2c_adapter->tar = I2C_TAR_ADDRESS(slave_address); i2c_adapter->intr_mask = 0; i2c_adapter->dma_cr = 0x3; diff --git a/lib/drivers/include/i2c.h b/lib/drivers/include/i2c.h index d2bb3f2b..a6a2e444 100644 --- a/lib/drivers/include/i2c.h +++ b/lib/drivers/include/i2c.h @@ -346,10 +346,10 @@ typedef enum _i2c_bus_speed_mode * @param[in] i2c_num i2c number * @param[in] slave_address i2c slave device address * @param[in] address_width address width 7bit or 10bit - * @param[in] bus_speed_mode i2c rate + * @param[in] i2c_clk i2c clk rate */ void i2c_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width, - i2c_bus_speed_mode_t bus_speed_mode); + uint32_t i2c_clk); /** * @brief I2c send data diff --git a/lib/drivers/include/spi.h b/lib/drivers/include/spi.h index 17ba63e0..ef10613d 100644 --- a/lib/drivers/include/spi.h +++ b/lib/drivers/include/spi.h @@ -167,13 +167,14 @@ extern volatile spi_t *const spi[4]; * @param[in] mode Spi mode * @param[in] frame_format Spi frame format * @param[in] data_bit_length Spi data bit length + * @param[in] endian 0:little-endian 1:big-endian * * @return Result * - 0 Success * - Other Fail */ void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format, - size_t data_bit_length); + size_t data_bit_length, uint32_t endian); /** * @brief Set multiline configuration diff --git a/lib/drivers/spi.c b/lib/drivers/spi.c index 4d7bfb17..45fb4acd 100644 --- a/lib/drivers/spi.c +++ b/lib/drivers/spi.c @@ -59,7 +59,7 @@ static void spi_set_tmod(uint8_t spi_num, uint32_t tmod) } void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format, - size_t data_bit_length) + size_t data_bit_length, uint32_t endian) { configASSERT(data_bit_length >= 4 && data_bit_length <= 32); configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2); @@ -108,6 +108,7 @@ void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_for spi_adapter->ssienr = 0x00; spi_adapter->ctrlr0 = (work_mode << 6) | (frame_format << frf_offset) | ((data_bit_length - 1) << dfs_offset); spi_adapter->spi_ctrlr0 = 0; + spi_adapter->endian = endian; } void spi_init_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length, From 2fb3a8ddd57bd121e93c106fc222ad174b0880d9 Mon Sep 17 00:00:00 2001 From: jiangxiangbing Date: Tue, 9 Oct 2018 21:23:01 +0800 Subject: [PATCH 51/58] aes test pass --- lib/drivers/aes.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/lib/drivers/aes.c b/lib/drivers/aes.c index ddd84d31..5fc3696d 100644 --- a/lib/drivers/aes.c +++ b/lib/drivers/aes.c @@ -302,9 +302,8 @@ void aes_ecb128_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t inp void aes_ecb128_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data) { - size_t padding_len = ((input_len + 15) / 16) * 16; aes_init(input_key, AES_128, NULL, 0L, NULL, AES_ECB, AES_HARD_ENCRYPTION, 0L, input_len); - aes_process(input_data, output_data, padding_len, AES_ECB); + aes_process(input_data, output_data, input_len, AES_ECB); } void aes_ecb192_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data) @@ -316,9 +315,8 @@ void aes_ecb192_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t inp void aes_ecb192_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data) { - size_t padding_len = ((input_len + 15) / 16) * 16; aes_init(input_key, AES_192, NULL, 0L, NULL, AES_ECB, AES_HARD_ENCRYPTION, 0L, input_len); - aes_process(input_data, output_data, padding_len, AES_ECB); + aes_process(input_data, output_data, input_len, AES_ECB); } void aes_ecb256_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data) @@ -330,9 +328,8 @@ void aes_ecb256_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t inp void aes_ecb256_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data) { - size_t padding_len = ((input_len + 15) / 16) * 16; aes_init(input_key, AES_256, NULL, 0L, NULL, AES_ECB, AES_HARD_ENCRYPTION, 0L, input_len); - aes_process(input_data, output_data, padding_len, AES_ECB); + aes_process(input_data, output_data, input_len, AES_ECB); } void aes_cbc128_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data) @@ -344,9 +341,8 @@ void aes_cbc128_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t void aes_cbc128_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data) { - size_t padding_len = ((input_len + 15) / 16) * 16; aes_init(context->input_key, AES_128, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_ENCRYPTION, 0L, input_len); - aes_process(input_data, output_data, padding_len, AES_CBC); + aes_process(input_data, output_data, input_len, AES_CBC); } void aes_cbc192_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data) @@ -358,9 +354,8 @@ void aes_cbc192_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t void aes_cbc192_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data) { - size_t padding_len = ((input_len + 15) / 16) * 16; aes_init(context->input_key, AES_192, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_ENCRYPTION, 0L, input_len); - aes_process(input_data, output_data, padding_len, AES_CBC); + aes_process(input_data, output_data, input_len, AES_CBC); } void aes_cbc256_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data) @@ -372,9 +367,8 @@ void aes_cbc256_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t void aes_cbc256_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data) { - size_t padding_len = ((input_len + 15) / 16) * 16; aes_init(context->input_key, AES_256, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_ENCRYPTION, 0L, input_len); - aes_process(input_data, output_data, padding_len, AES_CBC); + aes_process(input_data, output_data, input_len, AES_CBC); } void aes_gcm128_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag) From 1e4949e4541a02a20580e365dadf062bbd0ca806 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Tue, 9 Oct 2018 21:29:53 +0800 Subject: [PATCH 52/58] Fix get SYSCTL_SOURCE_IN0 bug --- lib/drivers/sysctl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/drivers/sysctl.c b/lib/drivers/sysctl.c index 106f7335..d0850589 100644 --- a/lib/drivers/sysctl.c +++ b/lib/drivers/sysctl.c @@ -1283,6 +1283,7 @@ uint32_t sysctl_clock_get_freq(sysctl_clock_t clock) */ case SYSCTL_CLOCK_IN0: source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + result = source; break; /* From 2fa2a5bd57856d5f53b442deadf645020bdde400 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Tue, 9 Oct 2018 21:38:49 +0800 Subject: [PATCH 53/58] Add wdt clear interrupt --- lib/drivers/include/wdt.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/lib/drivers/include/wdt.h b/lib/drivers/include/wdt.h index 6ba580ee..70a102d0 100644 --- a/lib/drivers/include/wdt.h +++ b/lib/drivers/include/wdt.h @@ -141,6 +141,14 @@ void wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t */ void wdt_stop(wdt_device_number_t id); +/** + * @brief Clear wdt interrupt + * + * @param[in] id Wdt id 0 or 1 + * + */ +void wdt_clear_interrupt(wdt_device_number_t id); + #ifdef __cplusplus } #endif From aeb2380869f97933de012b68338de52cdbb96f5a Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Wed, 10 Oct 2018 11:08:27 +0800 Subject: [PATCH 54/58] Add register_core1 --- lib/bsp/entry_user.c | 37 ++++++++++++++++++++++++++----------- lib/bsp/include/bsp.h | 7 +++++++ lib/bsp/include/entry.h | 10 ++++++++++ src/hello_world/main.c | 2 +- 4 files changed, 44 insertions(+), 12 deletions(-) create mode 100644 lib/bsp/include/bsp.h diff --git a/lib/bsp/entry_user.c b/lib/bsp/entry_user.c index 2b670eac..10c495c7 100644 --- a/lib/bsp/entry_user.c +++ b/lib/bsp/entry_user.c @@ -25,13 +25,15 @@ #include "syslog.h" #include "uarths.h" +extern volatile uint64_t g_wake_up[2]; + +core_instance_t core1_instance; + volatile char * const ram = (volatile char*)RAM_BASE_ADDR; extern char _heap_start[]; extern char _heap_end[]; -extern volatile uint64_t g_wake_up[2]; - void thread_entry(int core_id) { while (!atomic_read(&g_wake_up[core_id])); @@ -43,6 +45,16 @@ void core_enable(int core_id) atomic_set(&g_wake_up[core_id], 1); } +int register_core1(core_function func, void *ctx) +{ + if(func == NULL) + return -1; + core1_instance.callback = func; + core1_instance.ctx = ctx; + core_enable(1); + return 0; +} + int __attribute__((weak)) os_entry(int core_id, int number_of_cores, int (*user_main)(int, char**)) { /* Call main if there is no OS */ @@ -68,19 +80,22 @@ void _init_bsp(int core_id, int number_of_cores) /* Init libc array for C++ */ __libc_init_array(); } - else - { - thread_entry(core_id); - } + int ret = 0; if (core_id == 0) { - /* Enable Core 1 to run main */ - core_enable(1); + core1_instance.callback = NULL; + core1_instance.ctx = NULL; + ret = os_entry(core_id, number_of_cores, main); + } + else + { + thread_entry(core_id); + if(core1_instance.callback == NULL) + asm volatile ("wfi"); + else + ret = core1_instance.callback(core1_instance.ctx); } - - int ret = os_entry(core_id, number_of_cores, main); - exit(ret); } diff --git a/lib/bsp/include/bsp.h b/lib/bsp/include/bsp.h new file mode 100644 index 00000000..deecc671 --- /dev/null +++ b/lib/bsp/include/bsp.h @@ -0,0 +1,7 @@ +#ifndef _KENDRYTE_BSP_H +#define _KENDRYTE_BSP_H +#include "atomic.h" +#include "entry.h" +#include "sleep.h" +#include "encoding.h" +#endif \ No newline at end of file diff --git a/lib/bsp/include/entry.h b/lib/bsp/include/entry.h index 2aded614..e9ab5b9a 100644 --- a/lib/bsp/include/entry.h +++ b/lib/bsp/include/entry.h @@ -23,6 +23,16 @@ extern "C" { #endif +typedef int (*core_function)(void *ctx); + +typedef struct _core_instance_t +{ + core_function callback; + void *ctx; +} core_instance_t; + +int register_core1(core_function func, void *ctx); + static inline void init_lma(void) { extern unsigned int _data_lma; diff --git a/src/hello_world/main.c b/src/hello_world/main.c index c505db98..f3c1b7c3 100644 --- a/src/hello_world/main.c +++ b/src/hello_world/main.c @@ -14,7 +14,7 @@ */ #include #include "sleep.h" -#include "encoding.h" +#include "bsp.h" int main() { uint64_t core_id = current_coreid(); From b0d6a2c8c4c06b9310eaaddf5992b4497673c108 Mon Sep 17 00:00:00 2001 From: jiangxiangbing Date: Wed, 10 Oct 2018 11:46:20 +0800 Subject: [PATCH 55/58] fix sha256 --- lib/drivers/sha256.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/drivers/sha256.c b/lib/drivers/sha256.c index 362149b2..2200911b 100644 --- a/lib/drivers/sha256.c +++ b/lib/drivers/sha256.c @@ -32,7 +32,7 @@ static const uint8_t padding[64] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static inline uint64_t byteswap64(uint64_t x) From 8c71c7946bb8ac418def48f01c5b04f74eec0963 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Wed, 10 Oct 2018 12:11:01 +0800 Subject: [PATCH 56/58] Update hello_world --- src/hello_world/main.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/src/hello_world/main.c b/src/hello_world/main.c index f3c1b7c3..74dfeff7 100644 --- a/src/hello_world/main.c +++ b/src/hello_world/main.c @@ -13,21 +13,20 @@ * limitations under the License. */ #include -#include "sleep.h" #include "bsp.h" + +int core1_function(void *ctx) +{ + uint64_t core = current_coreid(); + printf("Core %ld Hello world\n", core); + while(1); +} + + int main() { - uint64_t core_id = current_coreid(); - if (core_id == 0) - { - printf("Core 0 Hello, world!\n"); - } - else - { - msleep(100); - printf("Core 1 Hello, world!\n"); - } - while (1) - ; - return 0; + uint64_t core = current_coreid(); + printf("Core %ld Hello world\n", core); + register_core1(core1_function, NULL); + while(1); } From ba9ff3f30ef385f1165e8f3f6743d6ec82fe9146 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Wed, 10 Oct 2018 15:56:17 +0800 Subject: [PATCH 57/58] Add fpioa_init, delete unused code of syscall --- lib/bsp/entry_user.c | 2 ++ lib/bsp/syscalls.c | 10 ---------- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/lib/bsp/entry_user.c b/lib/bsp/entry_user.c index 10c495c7..0b44fae8 100644 --- a/lib/bsp/entry_user.c +++ b/lib/bsp/entry_user.c @@ -75,6 +75,8 @@ void _init_bsp(int core_id, int number_of_cores) init_bss(); /* Init UART */ uarths_init(); + /* Init FPIOA */ + fpioa_init(); /* Register finalization function */ atexit(__libc_fini_array); /* Init libc array for C++ */ diff --git a/lib/bsp/syscalls.c b/lib/bsp/syscalls.c index 412dce2d..ccd05f2a 100644 --- a/lib/bsp/syscalls.c +++ b/lib/bsp/syscalls.c @@ -106,14 +106,6 @@ void __attribute__((noreturn)) sys_exit(int code) unsigned long core_id = current_coreid(); /* First print some diagnostic information. */ LOGW(TAG, "sys_exit called by core %ld with 0x%lx\n", core_id, (uint64_t)code); - /* Write exit register to pause netlist simulation */ - volatile uint32_t *reg = (volatile uint32_t *)0x50440080UL; - /* Write stop bit and write back */ - *reg = (1UL << 31); - - /* Send 0 to uart */ - uarths_putchar(0); - while (1) continue; } @@ -125,8 +117,6 @@ static int sys_nosys(long a0, long a1, long a2, long a3, long a4, long a5, unsig UNUSED(a5); LOGE(TAG, "Unsupported syscall %ld: a0=%lx, a1=%lx, a2=%lx!\n", n, a0, a1, a2); - /* Send 0 to uart */ - uarths_putchar(0); while (1) continue; return -ENOSYS; From b32e6046e50bacab4de56ce2f781ede77a897838 Mon Sep 17 00:00:00 2001 From: zhaozhongxiang Date: Wed, 10 Oct 2018 17:51:25 +0800 Subject: [PATCH 58/58] Modify fpioa fpioa_get_io_by_function --- lib/bsp/config/fpioa_cfg.c | 29 ------------------------- lib/bsp/config/fpioa_cfg.h | 42 ------------------------------------- lib/drivers/fpioa.c | 2 +- lib/drivers/gpio.c | 2 +- lib/drivers/gpiohs.c | 2 +- lib/drivers/include/fpioa.h | 2 +- 6 files changed, 4 insertions(+), 75 deletions(-) delete mode 100644 lib/bsp/config/fpioa_cfg.c delete mode 100644 lib/bsp/config/fpioa_cfg.h diff --git a/lib/bsp/config/fpioa_cfg.c b/lib/bsp/config/fpioa_cfg.c deleted file mode 100644 index 4235efb9..00000000 --- a/lib/bsp/config/fpioa_cfg.c +++ /dev/null @@ -1,29 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#include "fpioa_cfg.h" - -const fpioa_cfg_t g_fpioa_cfg = -{ - .version = 1, - .io_count = FPIOA_NUM_IO, - .io_functions = - { - [0] = FUNC_JTAG_TCLK, - - } -}; - diff --git a/lib/bsp/config/fpioa_cfg.h b/lib/bsp/config/fpioa_cfg.h deleted file mode 100644 index 59d6e7c4..00000000 --- a/lib/bsp/config/fpioa_cfg.h +++ /dev/null @@ -1,42 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef _FPIOA_CFG_H -#define _FPIOA_CFG_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct _fpioa_cfg -{ - uint32_t version; - uint32_t io_count; - fpioa_function_t io_functions[FPIOA_NUM_IO]; -} fpioa_cfg_t; - -extern const fpioa_cfg_t g_fpioa_cfg; -int fpioa_get_io_by_func(fpioa_function_t function); - - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/lib/drivers/fpioa.c b/lib/drivers/fpioa.c index c47681c0..a57732e4 100644 --- a/lib/drivers/fpioa.c +++ b/lib/drivers/fpioa.c @@ -5385,7 +5385,7 @@ int fpioa_set_tie_value(fpioa_function_t function, int value) return 0; } -int fpioa_get_io_by_func(fpioa_function_t function) +int fpioa_get_io_by_function(fpioa_function_t function) { int index = 0; for (index = 0; index < FPIOA_NUM_IO; index++) diff --git a/lib/drivers/gpio.c b/lib/drivers/gpio.c index 9b8a6c63..ba996d8f 100644 --- a/lib/drivers/gpio.c +++ b/lib/drivers/gpio.c @@ -28,7 +28,7 @@ int gpio_init(void) void gpio_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode) { configASSERT(pin < GPIO_MAX_PINNO); - int io_number = fpioa_get_io_by_func(FUNC_GPIO0 + pin); + int io_number = fpioa_get_io_by_function(FUNC_GPIO0 + pin); configASSERT(io_number > 0); fpioa_pull_t pull; diff --git a/lib/drivers/gpiohs.c b/lib/drivers/gpiohs.c index 2829acb5..951bd0ba 100644 --- a/lib/drivers/gpiohs.c +++ b/lib/drivers/gpiohs.c @@ -32,7 +32,7 @@ gpiohs_pin_context pin_context[32]; void gpiohs_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode) { configASSERT(pin < GPIOHS_MAX_PINNO); - int io_number = fpioa_get_io_by_func(FUNC_GPIOHS0 + pin); + int io_number = fpioa_get_io_by_function(FUNC_GPIOHS0 + pin); configASSERT(io_number > 0); fpioa_pull_t pull; diff --git a/lib/drivers/include/fpioa.h b/lib/drivers/include/fpioa.h index 873eb47d..90d8993d 100644 --- a/lib/drivers/include/fpioa.h +++ b/lib/drivers/include/fpioa.h @@ -990,7 +990,7 @@ int fpioa_get_io_driving(int number); * - -1 Fail * - Other The IO number */ -int fpioa_get_io_by_func(fpioa_function_t function); +int fpioa_get_io_by_function(fpioa_function_t function); #ifdef __cplusplus