diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..aa34a4f2 --- /dev/null +++ b/.gitignore @@ -0,0 +1,10 @@ +/ports/stm8/build-sdcc +/ports/stm8/build-cosmic +/ports/stm8/build-iar +/ports/stm8/Debug +/ports/stm8/Release +/ports/stm8_oss/build-sdcc +/ports/stm8_oss/build-cosmic +/ports/stm8_oss/build-iar +/ports/stm8_oss/Debug +/ports/stm8_oss/Release diff --git a/ports/stm8/atomthreads-sample-cosmic.dep b/ports/stm8/atomthreads-sample-cosmic.dep new file mode 100644 index 00000000..9b202316 --- /dev/null +++ b/ports/stm8/atomthreads-sample-cosmic.dep @@ -0,0 +1,50 @@ +; STMicroelectronics dependencies file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Root.Kernel...\..\kernel\atomkernel.c.Config.0] +ExternDep= ..\..\kernel\atomkernel.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8s-periphs\stm8s_type.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" + +[Root.Kernel...\..\kernel\atomkernel.c.Config.1] +ExternDep= ..\..\kernel\atomkernel.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8s-periphs\stm8s_type.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" + +[Root.Kernel...\..\kernel\atommutex.c.Config.1] +ExternDep= ..\..\kernel\atommutex.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8s-periphs\stm8s_type.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../kernel\atommutex.h + +[Root.Kernel...\..\kernel\atomqueue.c.Config.1] +ExternDep= ..\..\kernel\atomqueue.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\string.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8s-periphs\stm8s_type.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../kernel\atomqueue.h + +[Root.Kernel...\..\kernel\atomsem.c.Config.1] +ExternDep= ..\..\kernel\atomsem.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8s-periphs\stm8s_type.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../kernel\atomsem.h + +[Root.Kernel...\..\kernel\atomtimer.c.Config.1] +ExternDep= ..\..\kernel\atomtimer.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8s-periphs\stm8s_type.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" + +[Root.Peripherals.stm8s-periphs\stm8s_clk.c.Config.1] +ExternDep= stm8s-periphs\stm8s_clk.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" stm8s-periphs\stm8s_clk.h stm8s-periphs\stm8s.h stm8s-periphs\stm8s_type.h stm8s_conf.h stm8s-periphs\stm8s_gpio.h stm8s-periphs\stm8s_tim1.h stm8s-periphs\stm8s_uart2.h + +[Root.Peripherals.stm8s-periphs\stm8s_uart2.c.Config.1] +ExternDep= stm8s-periphs\stm8s_uart2.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" stm8s-periphs\stm8s_uart2.h stm8s-periphs\stm8s.h stm8s-periphs\stm8s_type.h stm8s_conf.h stm8s-periphs\stm8s_clk.h stm8s-periphs\stm8s_gpio.h stm8s-periphs\stm8s_tim1.h + +[Root.Peripherals.stm8s-periphs\stm8s_gpio.c.Config.1] +ExternDep= stm8s-periphs\stm8s_gpio.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" stm8s-periphs\stm8s_gpio.h stm8s-periphs\stm8s.h stm8s-periphs\stm8s_type.h stm8s_conf.h stm8s-periphs\stm8s_clk.h stm8s-periphs\stm8s_tim1.h stm8s-periphs\stm8s_uart2.h + +[Root.Peripherals.stm8s-periphs\stm8s_tim1.c.Config.1] +ExternDep= stm8s-periphs\stm8s_tim1.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" stm8s-periphs\stm8s_tim1.h stm8s-periphs\stm8s.h stm8s-periphs\stm8s_type.h stm8s_conf.h stm8s-periphs\stm8s_clk.h stm8s-periphs\stm8s_gpio.h stm8s-periphs\stm8s_uart2.h + +[Root.Port...\..\tests\sem4.c.Config.1] +ExternDep= ..\..\tests\sem4.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8s-periphs\stm8s_type.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../tests\atomtests.h atomport-tests.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdio.h" ../../kernel\atomsem.h + +[Root.Port.uart.c.Config.1] +ExternDep= uart.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdio.h" stm8s-periphs\stm8s.h stm8s-periphs\stm8s_type.h stm8s_conf.h stm8s-periphs\stm8s_clk.h stm8s-periphs\stm8s_gpio.h stm8s-periphs\stm8s_tim1.h stm8s-periphs\stm8s_uart2.h ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../kernel\atommutex.h uart.h + +[Root.Port.tests-main.c.Config.1] +ExternDep= tests-main.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdio.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8s-periphs\stm8s_type.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" atomport-private.h atomport-tests.h ../../tests\atomtests.h uart.h stm8s-periphs\stm8s.h stm8s_conf.h stm8s-periphs\stm8s_clk.h stm8s-periphs\stm8s_gpio.h stm8s-periphs\stm8s_tim1.h stm8s-periphs\stm8s_uart2.h + +[Root.Port.atomport.c.Config.1] +ExternDep= atomport.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8s-periphs\stm8s_type.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" atomport-private.h stm8s-periphs\stm8s_tim1.h stm8s-periphs\stm8s.h stm8s_conf.h stm8s-periphs\stm8s_clk.h stm8s-periphs\stm8s_gpio.h stm8s-periphs\stm8s_uart2.h + +[Root.Port.stm8_interrupt_vector.c.Config.1] +ExternDep= stm8_interrupt_vector.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" atomport-private.h \ No newline at end of file diff --git a/ports/stm8/atomthreads-sample-cosmic.stp b/ports/stm8/atomthreads-sample-cosmic.stp index e96b4752..f0b728b6 100644 --- a/ports/stm8/atomthreads-sample-cosmic.stp +++ b/ports/stm8/atomthreads-sample-cosmic.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Program Files\COSMIC\CXSTM8_16K +String.102.0=C:\Program Files\COSMIC\FSE_Compilers String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -144,7 +144,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Program Files\COSMIC\CXSTM8_16K +String.102.0=C:\Program Files\COSMIC\FSE_Compilers String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -467,7 +467,7 @@ PathName=stm8s-periphs\stm8s_type.h [Root.Port] ElemType=Folder PathName=Port -Child=Root.Port...\..\tests\sem1.c +Child=Root.Port...\..\tests\sem4.c Config.0=Root.Port.Config.0 Config.1=Root.Port.Config.1 @@ -537,9 +537,9 @@ String.4.0= String.5.0= String.6.0=2010,2,9,1,12,48 -[Root.Port...\..\tests\sem1.c] +[Root.Port...\..\tests\sem4.c] ElemType=File -PathName=..\..\tests\sem1.c +PathName=..\..\tests\sem4.c Next=Root.Port.uart.h [Root.Port.uart.h] diff --git a/ports/stm8/atomthreads-sample-raisonance.dep b/ports/stm8/atomthreads-sample-raisonance.dep new file mode 100644 index 00000000..bfafb3ef --- /dev/null +++ b/ports/stm8/atomthreads-sample-raisonance.dep @@ -0,0 +1,8 @@ +; STMicroelectronics dependencies file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Root.Kernel...\..\kernel\atomkernel.c.Config.0] +ExternDep=..\..\kernel\atomkernel.c \ No newline at end of file diff --git a/ports/stm8/atomthreads-sample-raisonance.stp b/ports/stm8/atomthreads-sample-raisonance.stp index 4aeec96c..e113eaf1 100644 --- a/ports/stm8/atomthreads-sample-raisonance.stp +++ b/ports/stm8/atomthreads-sample-raisonance.stp @@ -63,7 +63,7 @@ String.100.4=Raisonance String.101.0=Raisonance String.102.0=C:\Program Files\Raisonance\Ride String.103.0=bin -String.104.0=INC\ST7;INC +String.104.0=INC\STM8;INC\ST7;INC String.105.0=LIB\ST7 String.106.0=Debug String.107.0=$(ProjectSFile).elf @@ -131,7 +131,7 @@ String.100.4=Raisonance String.101.0=Raisonance String.102.0=C:\Program Files\Raisonance\Ride String.103.0=bin -String.104.0=INC\ST7;INC +String.104.0=INC\STM8;INC\ST7;INC String.105.0=LIB\ST7 String.106.0=Release String.107.0=$(ProjectSFile).elf diff --git a/ports/stm8/atomthreads-sample-stvd.stw b/ports/stm8/atomthreads-sample-stvd.stw index 38c50c02..ff4267db 100644 --- a/ports/stm8/atomthreads-sample-stvd.stw +++ b/ports/stm8/atomthreads-sample-stvd.stw @@ -12,5 +12,5 @@ Filename=atomthreads-sample-raisonance.stp Dependencies= [Options] ActiveProject=atomthreads-cosmic -ActiveConfig=Debug +ActiveConfig=Release AddSortedElements=0 diff --git a/ports/stm8/atomthreads-sample-stvd.wed b/ports/stm8/atomthreads-sample-stvd.wed new file mode 100644 index 00000000..1bdeb66a --- /dev/null +++ b/ports/stm8/atomthreads-sample-stvd.wed @@ -0,0 +1,1248 @@ + +[WorkState_v1_2] +ptn_Child1=DockState +ptn_Child2=ToolBarMgr +ptn_Child3=Frames + +[WorkState_v1_2.DockState] +Bars=33 +ScreenCX=1920 +ScreenCY=976 +ptn_Child1=Bar-0 +ptn_Child2=Bar-1 +ptn_Child3=Bar-2 +ptn_Child4=Bar-3 +ptn_Child5=Bar-4 +ptn_Child6=Bar-5 +ptn_Child7=Bar-6 +ptn_Child8=Bar-7 +ptn_Child9=Bar-8 +ptn_Child10=Bar-9 +ptn_Child11=Bar-10 +ptn_Child12=Bar-11 +ptn_Child13=Bar-12 +ptn_Child14=Bar-13 +ptn_Child15=Bar-14 +ptn_Child16=Bar-15 +ptn_Child17=Bar-16 +ptn_Child18=Bar-17 +ptn_Child19=Bar-18 +ptn_Child20=Bar-19 +ptn_Child21=Bar-20 +ptn_Child22=Bar-21 +ptn_Child23=Bar-22 +ptn_Child24=Bar-23 +ptn_Child25=Bar-24 +ptn_Child26=Bar-25 +ptn_Child27=Bar-26 +ptn_Child28=Bar-27 +ptn_Child29=Bar-28 +ptn_Child30=Bar-29 +ptn_Child31=Bar-30 +ptn_Child32=Bar-31 +ptn_Child33=Bar-32 + +[WorkState_v1_2.DockState.Bar-0] +BarID=59419 +Bars=20 +Bar#0=0 +Bar#1=59647 +Bar#2=0 +Bar#3=59392 +Bar#4=59396 +Bar#5=59400 +Bar#6=124939 +Bar#7=0 +Bar#8=124960 +Bar#9=0 +Bar#10=0 +Bar#11=59399 +Bar#12=59398 +Bar#13=59401 +Bar#14=124933 +Bar#15=124938 +Bar#16=0 +Bar#17=32768 +Bar#18=0 +Bar#19=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-1] +BarID=32768 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=978 +Style=12110 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=8192 +TypeID=0 +ClassName=SECControlBar +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-2] +BarID=59422 +Bars=9 +Bar#0=0 +Bar#1=5707 +Bar#2=5706 +Bar#3=5710 +Bar#4=5704 +Bar#5=5721 +Bar#6=0 +Bar#7=32769 +Bar#8=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-3] +BarID=32769 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=978 +Style=36686 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 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+MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=150 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=4096 +TypeID=0 +ClassName=SECControlBar +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-6] +BarID=59421 +Bars=12 +Bar#0=0 +Bar#1=0 +Bar#2=5701 +Bar#3=0 +Bar#4=73539 +Bar#5=0 +Bar#6=35103 +Bar#7=35102 +Bar#8=35101 +Bar#9=35100 +Bar#10=32771 +Bar#11=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-7] +BarID=32771 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=20302 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=150 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=16384 +TypeID=0 +ClassName=SECControlBar +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-8] +BarID=59647 +MRUWidth=412 +Docking=True +MRUDockID=59419 +MRUDockLeftPos=-1 +MRUDockTopPos=-1 +MRUDockRightPos=1919 +MRUDockBottomPos=28 +MRUFloatStyle=8196 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=12220 +ExStyle=131980 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=429 +MRUFloatCY=27 +MRUHorzDockCX=1920 +MRUHorzDockCY=29 +MRUVertDockCX=72 +MRUVertDockCY=527 +MRUDockingState=0 +DockingStyle=61440 +TypeID=14947 +ClassName=SECMDIMenuBar +WindowName=Menu bar +ResourceID=0 +ptn_Child1=ToolBarInfoEx + +[WorkState_v1_2.DockState.Bar-8.ToolBarInfoEx] +Title=Menu bar +Buttons=BAAAAAAIAACAAAAAAIAADAAAAAAIAAEAAAAAAIAAFAAAAAAIAAGAAAAAAIAAHAAAAAAIAAIAAAAAAIAAJAAAAAAIAAKAAAAAAIAA + +[WorkState_v1_2.DockState.Bar-9] +BarID=59392 +YPos=28 +Docking=True +MRUDockID=0 +MRUDockLeftPos=8 +MRUDockTopPos=28 +MRUDockRightPos=156 +MRUDockBottomPos=58 +MRUFloatStyle=8196 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=12212 +ExStyle=131852 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=184352 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=148 +MRUHorzDockCY=30 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=61440 +TypeID=14946 +ClassName=SECCustomToolBar +WindowName=File +ResourceID=0 +ptn_Child1=ToolBarInfoEx + +[WorkState_v1_2.DockState.Bar-9.ToolBarInfoEx] +Title=File +Buttons=AABOAAAAAAGPDBAAAAAAAIIBAAAAAAAAAAAAAAAADABOAAAAAAAAAAAAAAAAHABOAAAAAA + +[WorkState_v1_2.DockState.Bar-10] +BarID=59396 +XPos=221 +YPos=28 +MRUWidth=566 +Docking=True +MRUDockID=59419 +MRUDockLeftPos=221 +MRUDockTopPos=28 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+WindowName=Workspace +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-19] +BarID=5721 +XPos=1 +YPos=5 +Docking=True +MRUDockID=0 +MRUDockLeftPos=1 +MRUDockTopPos=5 +MRUDockRightPos=1920 +MRUDockBottomPos=155 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=36756 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=1919 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=COutputControlBar +WindowName=Output +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-20] +BarID=5701 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=20356 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=150 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CNewDisassControlBar +WindowName=Disassembly +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-21] +BarID=5704 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=36612 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=500000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CRegisterControlBar +WindowName=Registers +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-22] +BarID=35100 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 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+WindowName=Memory #2 +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-24] +BarID=35102 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=20356 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=150 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CNewDumpControlBar +WindowName=Memory #3 +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-25] +BarID=35103 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=20356 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=150 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CNewDumpControlBar +WindowName=Memory #4 +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-26] +BarID=5708 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=8068 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=500000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=248 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CSoftBkControlBar +WindowName=Instruction Breakpoints +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-27] +BarID=5710 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=36740 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=666665 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CWatchControlBar +WindowName=Watch +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-28] +BarID=5706 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=36612 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=750000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CStackControlBar +WindowName=Call Stack +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-29] +BarID=5707 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=36612 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=800000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CLocalsControlBar +WindowName=Local Variables +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-30] +BarID=59423 +Horz=True +Floating=True +XPos=227 +YPos=72 +Bars=3 +Bar#0=0 +Bar#1=59403 +Bar#2=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-31] +BarID=59423 +Horz=True +Floating=True +XPos=716 +YPos=193 +Bars=3 +Bar#0=0 +Bar#1=59402 +Bar#2=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-32] +BarID=59423 +Horz=True +Floating=True +XPos=1101 +YPos=72 +Bars=3 +Bar#0=0 +Bar#1=59397 +Bar#2=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.ToolBarMgr] +ToolTips=True +CoolLook=True +LargeButtons=False + +[WorkState_v1_2.Frames] +ptn_Child1=MainFrame +ptn_Child2=ChildFrames + +[WorkState_v1_2.Frames.MainFrame] +WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPABAAAAAADAAAAAAMLEAAAAAPMCAAAAA +Title=ST Visual Develop - atomthreads-sample-stvd.stw* + +[WorkState_v1_2.Frames.ChildFrames] diff --git a/ports/stm8/atomthreads.lkf b/ports/stm8/atomthreads.lkf index 44e02bbe..e5b21f1e 100644 --- a/ports/stm8/atomthreads.lkf +++ b/ports/stm8/atomthreads.lkf @@ -32,15 +32,16 @@ build-cosmic\atomqueue.o build-cosmic\atomsem.o build-cosmic\atomtimer.o build-cosmic\stm8s_clk.o +build-cosmic\stm8s_uart2.o build-cosmic\stm8s_gpio.o build-cosmic\stm8s_tim1.o -build-cosmic\stm8s_uart2.o +# Caller passes in test application object name as param1 +# MUST BE PLACED HERE +@1 +build-cosmic\uart.o build-cosmic\tests-main.o build-cosmic\atomport.o -build-cosmic\uart.o build-cosmic\atomport-asm-cosmic.o -# Caller passes in test application object name as param1 -@1 # diff --git a/ports/stm8/cosmic.mak b/ports/stm8/cosmic.mak index 56e148d9..01761cf7 100644 --- a/ports/stm8/cosmic.mak +++ b/ports/stm8/cosmic.mak @@ -3,7 +3,7 @@ ############ # Set up build environment (using GNU Make) -# set PATH=%PATH%;C:\Program Files\GNU_MAKE;C:\Program Files\COSMIC\CXSTM8_16K +# set PATH=%PATH%;C:\Program Files\GNU_MAKE;C:\Program Files\COSMIC\FSE_Compilers\CXSTM8 # set MAKE_MODE=DOS # Build all test applications: @@ -14,7 +14,7 @@ KERNEL_DIR=../../kernel TESTS_DIR=../../tests PERIPHS_DIR=stm8s-periphs -LIBS_DIR="C:\Program Files\COSMIC\CXSTM8_16K\Lib" +LIBS_DIR="C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\Lib" CC=cxstm8 ASM=castm8 LINK=clnk diff --git a/ports/stm8/iar.mak b/ports/stm8/iar.mak index ae1f7fd8..35048392 100644 --- a/ports/stm8/iar.mak +++ b/ports/stm8/iar.mak @@ -3,7 +3,7 @@ ############ # Set up build environment (using GNU Make) -# set PATH=%PATH%;C:\Program Files\GNU_MAKE;C:\Program Files\IAR Systems\Embedded Workbench 6.0\stm8\bin +# set PATH=%PATH%;C:\Program Files\GNU_MAKE;C:\Program Files\IAR Systems\Embedded Workbench 8.3\stm8\bin # set MAKE_MODE=DOS # Build all test applications: @@ -11,7 +11,7 @@ # Location of build tools and atomthreads sources -EWSTM8_DIR=C:\Program Files\IAR Systems\Embedded Workbench 6.0\stm8 +EWSTM8_DIR=C:\Program Files\IAR Systems\Embedded Workbench 8.3\stm8 KERNEL_DIR=../../kernel TESTS_DIR=../../tests PERIPHS_DIR=stm8s-periphs diff --git a/ports/stm8/run_tests.sh b/ports/stm8/run_tests.sh new file mode 100755 index 00000000..4a8a6996 --- /dev/null +++ b/ports/stm8/run_tests.sh @@ -0,0 +1,22 @@ +#!/bin/bash + +# change to current working directory +cd `dirname $0` + +# SDCC test +echo "" +echo "run SDCC " $1 +stm8flash -c stlink -p stm8s105c6 -w build-sdcc/$1.ihx +miniterm /dev/ttyUSB0 9600 + +# Cosmic test +echo "" +echo "run Cosmic" $1 +stm8flash -c stlink -p stm8s105c6 -w build-cosmic/$1.s19 +miniterm /dev/ttyUSB0 9600 + +# IAR test +echo "" +echo "run IAR" $1 +stm8flash -c stlink -p stm8s105c6 -w build-iar/$1.s19 +miniterm /dev/ttyUSB0 9600 diff --git a/ports/stm8/test-matrix.ods b/ports/stm8/test-matrix.ods new file mode 100644 index 00000000..f46caf48 Binary files /dev/null and b/ports/stm8/test-matrix.ods differ diff --git a/ports/stm8_oss/Doxyfile b/ports/stm8_oss/Doxyfile new file mode 100644 index 00000000..c810a829 --- /dev/null +++ b/ports/stm8_oss/Doxyfile @@ -0,0 +1,1161 @@ +# Doxyfile 1.3.9.1 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project +# +# All text after a hash (#) is considered a comment and will be ignored +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" ") + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded +# by quotes) that should identify the project. + +PROJECT_NAME = atomthreads + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. If left blank the current directory will be used. + +OUTPUT_DIRECTORY = doxygen-stm8 + +# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create +# 4096 sub-directories (in 2 levels) under the output directory of each output +# format and will distribute the generated files over these directories. +# Enabling this option can be useful when feeding doxygen a huge amount of source +# files, where putting all generated files in the same directory would otherwise +# cause performance problems for the file system. + +CREATE_SUBDIRS = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# The default language is English, other supported languages are: +# Brazilian, Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, +# Dutch, Finnish, French, German, Greek, Hungarian, Italian, Japanese, +# Japanese-en (Japanese with English messages), Korean, Korean-en, Norwegian, +# Polish, Portuguese, Romanian, Russian, Serbian, Slovak, Slovene, Spanish, +# Swedish, and Ukrainian. + +OUTPUT_LANGUAGE = English + +# This tag can be used to specify the encoding used in the generated output. +# The encoding is not always determined by the language that is chosen, +# but also whether or not the output is meant for Windows or non-Windows users. +# In case there is a difference, setting the USE_WINDOWS_ENCODING tag to YES +# forces the Windows encoding (this is the default for the Windows binary), +# whereas setting the tag to NO uses a Unix-style encoding (the default for +# all platforms other than Windows). + +USE_WINDOWS_ENCODING = NO + +# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will +# include brief member descriptions after the members that are listed in +# the file and class documentation (similar to JavaDoc). +# Set to NO to disable this. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend +# the brief description of a member or function before the detailed description. +# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator +# that is used to form the text in various listings. Each string +# in this list, if found as the leading text of the brief description, will be +# stripped from the text and the result after processing the whole list, is used +# as the annotated text. Otherwise, the brief description is used as-is. If left +# blank, the following values are used ("$name" is automatically replaced with the +# name of the entity): "The $name class" "The $name widget" "The $name file" +# "is" "provides" "specifies" "contains" "represents" "a" "an" "the" + +ABBREVIATE_BRIEF = + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# Doxygen will generate a detailed section even if there is only a brief +# description. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all inherited +# members of a class in the documentation of that class as if those members were +# ordinary class members. Constructors, destructors and assignment operators of +# the base classes will not be shown. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full +# path before files name in the file list and in the header files. If set +# to NO the shortest path that makes the file name unique will be used. + +FULL_PATH_NAMES = YES + +# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag +# can be used to strip a user-defined part of the path. Stripping is +# only done if one of the specified strings matches the left-hand part of +# the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the +# path to strip. + +STRIP_FROM_PATH = + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of +# the path mentioned in the documentation of a class, which tells +# the reader which header file to include in order to use a class. +# If left blank only the name of the header file containing the class +# definition is used. Otherwise one should specify the include paths that +# are normally passed to the compiler using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter +# (but less readable) file names. This can be useful is your file systems +# doesn't support long names like on DOS, Mac, or CD-ROM. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen +# will interpret the first line (until the first dot) of a JavaDoc-style +# comment as the brief description. If set to NO, the JavaDoc +# comments will behave just like the Qt-style comments (thus requiring an +# explicit @brief command for a brief description. + +JAVADOC_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen +# treat a multi-line C++ special comment block (i.e. a block of //! or /// +# comments) as a brief description. This used to be the default behaviour. +# The new default is to treat a multi-line C++ comment block as a detailed +# description. Set this tag to YES if you prefer the old behaviour instead. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the DETAILS_AT_TOP tag is set to YES then Doxygen +# will output the detailed description near the top, like JavaDoc. +# If set to NO, the detailed description appears after the member +# documentation. + +DETAILS_AT_TOP = NO + +# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented +# member inherits the documentation from any documented member that it +# re-implements. + +INHERIT_DOCS = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. +# Doxygen uses this value to replace tabs by spaces in code fragments. + +TAB_SIZE = 4 + +# This tag can be used to specify a number of aliases that acts +# as commands in the documentation. An alias has the form "name=value". +# For example adding "sideeffect=\par Side Effects:\n" will allow you to +# put the command \sideeffect (or @sideeffect) in the documentation, which +# will result in a user-defined paragraph with heading "Side Effects:". +# You can put \n's in the value part of an alias to insert newlines. + +ALIASES = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources +# only. Doxygen will then generate output that is more tailored for C. +# For instance, some of the names that are used will be different. The list +# of all members will be omitted, etc. + +OPTIMIZE_OUTPUT_FOR_C = YES + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java sources +# only. Doxygen will then generate output that is more tailored for Java. +# For instance, namespaces will be presented as packages, qualified scopes +# will look different, etc. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = YES + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = YES + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. When set to YES local +# methods, which are defined in the implementation section but not in +# the interface are included in the documentation. +# If set to NO (the default) only methods in the interface are included. + +EXTRACT_LOCAL_METHODS = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. + +CASE_SENSE_NAMES = YES + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = NO + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or define consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and defines in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = YES + +# If the sources in your project are distributed over multiple directories +# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy +# in the documentation. + +SHOW_DIRECTORIES = YES + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx *.hpp +# *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm + +FILE_PATTERNS = + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = NO + +# The EXCLUDE tag can be used to specify files and/or directories that should +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used select whether or not files or directories +# that are symbolic links (a Unix filesystem feature) are excluded from the input. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. + +EXCLUDE_PATTERNS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. If FILTER_PATTERNS is specified, this tag will be +# ignored. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER +# is applied to all files. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES (the default) +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = YES + +# If the REFERENCES_RELATION tag is set to YES (the default) +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = YES + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = NO + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# stylesheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = + +# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, +# files or namespaces will be aligned in HTML using tables. If set to +# NO a bullet list will be used. + +HTML_ALIGN_MEMBERS = YES + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compressed HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index at +# top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. + +DISABLE_INDEX = NO + +# This tag can be used to set the number of enum values (range [1..20]) +# that doxygen will group on one line in the generated HTML documentation. + +ENUM_VALUES_PER_LINE = 4 + +# If the GENERATE_TREEVIEW tag is set to YES, a side panel will be +# generated containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+, +# Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are +# probably better off using the HTML help feature. + +GENERATE_TREEVIEW = NO + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = NO + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, a4wide, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4wide + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = NO + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = NO + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = NO + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load stylesheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = NO + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. This is useful +# if you want to understand what is going on. On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = NO + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_PREDEFINED tags. + +EXPAND_ONLY_PREDEF = NO + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# in the INCLUDE_PATH (see below) will be search if a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. + +PREDEFINED = + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all function-like macros that are alone +# on a line, have an all uppercase name, and do not end with a semicolon. Such +# function macros are typically used for boiler-plate code, and will confuse the +# parser if not removed. + +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base or +# super classes. Setting the tag to NO turns the diagrams off. Note that this +# option is superseded by the HAVE_DOT option below. This is only a fallback. It is +# recommended to install and use dot, since it yields more powerful graphs. + +CLASS_DIAGRAMS = YES + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = NO + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# the CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = NO + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = YES + +# If the CALL_GRAPH and HAVE_DOT tags are set to YES then doxygen will +# generate a call dependency graph for every global function or class method. +# Note that enabling this option will significantly increase the time of a run. +# So in most cases it will be better to enable call graphs for selected +# functions only using the \callgraph command. + +CALL_GRAPH = NO + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are png, jpg, or gif +# If left blank png will be used. + +DOT_IMAGE_FORMAT = png + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found on the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + +# The MAX_DOT_GRAPH_WIDTH tag can be used to set the maximum allowed width +# (in pixels) of the graphs generated by dot. If a graph becomes larger than +# this value, doxygen will try to truncate the graph, so that it fits within +# the specified constraint. Beware that most browsers cannot cope with very +# large images. + +MAX_DOT_GRAPH_WIDTH = 1024 + +# The MAX_DOT_GRAPH_HEIGHT tag can be used to set the maximum allows height +# (in pixels) of the graphs generated by dot. If a graph becomes larger than +# this value, doxygen will try to truncate the graph, so that it fits within +# the specified constraint. Beware that most browsers cannot cope with very +# large images. + +MAX_DOT_GRAPH_HEIGHT = 1024 + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes that +# lay further from the root node will be omitted. Note that setting this option to +# 1 or 2 may greatly reduce the computation time needed for large code bases. Also +# note that a graph may be further truncated if the graph's image dimensions are +# not sufficient to fit the graph (see MAX_DOT_GRAPH_WIDTH and MAX_DOT_GRAPH_HEIGHT). +# If 0 is used for the depth value (the default), the graph is not depth-constrained. + +MAX_DOT_GRAPH_DEPTH = 0 + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to the search engine +#--------------------------------------------------------------------------- + +# The SEARCHENGINE tag specifies whether or not a search engine should be +# used. If set to NO the values of all tags below this one will be ignored. + +SEARCHENGINE = NO diff --git a/ports/stm8_oss/README b/ports/stm8_oss/README new file mode 100644 index 00000000..0468d4cb --- /dev/null +++ b/ports/stm8_oss/README @@ -0,0 +1,202 @@ +--------------------------------------------------------------------------- + +Library: Atomthreads +Author: Kelvin Lawson +Website: http://atomthreads.com +License: BSD Revised + +--------------------------------------------------------------------------- + +STM8 PORT + +This folder contains a port of the Atomthreads real time kernel for the +STM8 processor architecture. These instructions cover compiler-agnostic +aspects of usage of Atomthreads. + +All of the cross-platform kernel code is contained in the top-level +'kernel' folder, while ports to specific CPU architectures are contained in +the 'ports' folder tree. A port to a CPU architecture can comprise just one +or two modules which provide the architecture-specific functionality, such +as the context-switch routine which saves and restores processor registers +on a thread switch. In this case, the kernel port is split into two files: + + * atomport.c: Those functions which can be written in C + * atomport-asm-*.s: Main register save/restore assembler routines + +Each Atomthreads port requires also a header file which describes various +architecture-specific details such as appropriate types for 8-bit, 16-bit +etc variables, the port's system tick frequency, and macros for performing +interrupt lockouts / critical sections: + + * atomport.h: Port-specific header required by the kernel for each port + +A few additional source files are also included here: + + * tests-main.c: Main application file (used for launching automated tests) + * uart.c: UART wrapper to allow use of stdio/printf() + * stm8-include/STM8*.h: OSS device headers from https://github.com/gicking/STM8_headers + * stm8-include/config.h: device selection and some project settings + +Atomthreads includes a suite of automated tests which prove the key OS +functionality, and can be used with any architecture ports. This port +provides an easy mechanism for building, downloading and running the test +suite to prove the OS on your target. + +The port was carried out and tested on an STM8S105C6 running within an +STM8S-Discovery board, and supports the SDCC, Cosmic and IAR compiler +tools. It is possible to use it with other processors in the STM8 range, as +well as other hardware platforms and compilers, with minimal changes. +Platform and compiler specific code has been kept to an absolute minimum. + +This README covers the compiler-agnostic aspects of usage of Atomthreads. + +Instructions for users of particular compilers are available in README-SDCC, +README-IAR and README-COSMIC. + +--------------------------------------------------------------------------- + +STM8S-DISCOVERY SPECIFICS + +There are very minimal board-specific aspects to the STM8 port so it is +trivial to run Atomthreads on other STM8 platforms. + +Device selection and some project settings are in files in stm8-include. +Currently several STM8S and STM8L devices have been tested. + +The test applications make use of a LED to indicate test pass/fail status. +This is currently configured to use a bit in GPIOD, which on the Discovery +board maps to the board's only LED. You may change the port and register +bit in tests-main.c to utilise a different pin on other hardware platforms. +You may also completely omit the LED flashing in the test application if +you prefer to use the UART for monitoring test status. + +The test applications also make use of the UART to print out pass/fail +indications and other information. For this you should connect a serial +cable to the Discovery board via the external pin connectors. Use of +a UART is not required if you prefer to use the LED or some other method +of notifying test pass/fail status. + +To connect a serial cable to the Discovery you will need to connect to +the following pins on the external connectors: + Vcc: CN2 pin 8 + GND: CN2 pin 7 + UART RX: CN4 pin 11 (connect to TX at the PC end) + UART TX: CN4 pin 10 (connect to RX at the PC end) +Note that the board uses TTL levels so you may need to use a level +converter. External level converters may need to be powered using +a Vdd of 5v, which can be achieved by positioning JP1 on the Discovery. + +The STM8 device on the Discovery only offers UART2. If you are using a +different device or wish to use an alternative UART then you must change +the stm8-include/config.h file. + +If you are using a CPU other than the STM8S105C6 you should change the +PART macro from "STM8S105" to your target CPU. This can be changed in the +*.mak Makefiles. If you are using the STVD project it should be changed in +the project preprocessor settings for both Debug and Release builds. You +may also wish to enable any CPU peripherals which you wish to use in the +stm8-include/config.h file. + +--------------------------------------------------------------------------- + +RAM FOOTPRINT & STACK USAGE + +The Atomthreads kernel is written in well-structured pure C which is highly +portable and not targeted at any particular compiler or CPU architecture. +For this reason it is not highly optimised for the STM8 architecture, and +by its nature will likely have a higher text and data footprint than an +RTOS targeted at the STM8 architecture only. The emphasis here is on +C-based portable, readable and maintainable code which can run on any CPU +architecture, from the 8-bitters up. + +A good rule of thumb when using Atomthreads on the STM8 architecture is +that a minimum of 1KB RAM is required in order to support an application +with 4 or 5 threads and the idle thread. If a minimum of approximately +128 bytes per thread stack is acceptable then you will benefit from the +easy-to-read, portable implementation of an RTOS herein. + +The major consumer of RAM when using Atomthreads is your thread stacks. +Functionality that is shared between several kernel modules is farmed out +to separate functions, resulting in readable and maintainable code but +with some associated stack cost of calling out to subroutines. Further, +each thread stack is used for saving its own registers on a context +switch, and there is no separate interrupt stack which means that each +thread stack has to be able to cope with the maximum stack usage of the +kernel (and application) interrupt handlers. + +Clearly the stack requirement for each thread depends on what your +application code does, and what memory model is used etc, but generally +you should find that 128 bytes is enough to allow for the thread to be +switched out (and thus save its registers) while deep within a kernel +or application call stack, and similarly enough to provide stack for +interrupt handlers interrupting while the thread is deep within a kernel +or application call stack. You will need to increase this depending on +what level of stack the application code in question requires. + +At this time the maximum stack consumed by the test threads within the +automated test modules is 95 bytes of stack, and the main test thread has +been seen to consume 163 bytes of stack. At this time the queue9 test is +the largest consumer of test thread stack (95 bytes) and the sem1 test +consumes the largest main thread stack (137 bytes). If your applications +have large amounts of local data or call several subroutines then you may +find that you need larger than 128 bytes. + +You may monitor the stack usage of your application threads during runtime +by defining the macro ATOM_STACK_CHECKING and calling +atomThreadStackCheck(). This macro is defined by default in the Makefile +so that the automated test modules can check for stack overflows, but you +may wish to undefine this in your application Makefiles when you are happy +that the stack usage is acceptable. Enabling ATOM_STACK_CHECKING will +increase the size of your threads' TCBs slightly, and will incur a minor +CPU cycles overhead whenever threads are created due to prefilling the +thread stack with a known value. + +With careful consideration and few threads it would be possible to use +a platform with 512 bytes RAM, but not all of the automated test suite +would run on such a platform (some of the test modules use 6 threads: a +main thread together with 4 test threads and the idle thread). + + +--------------------------------------------------------------------------- + +INTERRUPT HANDLING + +Interrupt handlers use the stack of the thread which was running when the +interrupt occurred. If no thread rescheduling occurs during the ISR then +on exit from the ISR any data stacked by the ISR on the thread's stack is +popped off the stack and execution of the thread resumes. If a reschedule +during the ISR causes a context switch to a new thread, then the ISR's +data will remain on the thread's stack until the thread is scheduled back +in. + +Interrupt priorities (via the ITC_SPRx registers) are left in their +default power-on state, which disables interrupt nesting. Kernel changes +may be required to support interrupt nesting. + +Note that the STM8 programming manual currently describes the following +feature: + + "Fast interrupt handling through alternate register files (up to 4 + contexts) with standard stack compatible mode (for real time OS + kernels)" + +This feature was implemented by ST in the core but has to date never been +included in any STM8 products. If it is included in future products then +you will need to put the device in the stack compatible mode described. + + +--------------------------------------------------------------------------- + +WRITING NEW INTERRUPT HANDLERS + +All interrupt handlers which will call out to the OS kernel and potentially +cause a thread switch must call atomIntEnter() and atomIntExit(). An +example of this can be seen in the timer tick ISR in atomport.c. + +You may also implement fast interrupt handlers in the system which do not +call atomIntEnter()/atomIntExit(), however these ISRs cannot perform OS +functions such as posting semaphores or effecting a thread switch. + + +--------------------------------------------------------------------------- + diff --git a/ports/stm8_oss/README-COSMIC b/ports/stm8_oss/README-COSMIC new file mode 100644 index 00000000..ecbfe410 --- /dev/null +++ b/ports/stm8_oss/README-COSMIC @@ -0,0 +1,301 @@ +--------------------------------------------------------------------------- + +Library: Atomthreads +Author: Kelvin Lawson +Website: http://atomthreads.com +License: BSD Revised + +--------------------------------------------------------------------------- + +STM8 PORT - COSMIC COMPILER + +This folder contains a port of the Atomthreads real time kernel for the +STM8 processor architecture. These instructions cover usage of Atomthreads +with the Cosmic compiler (CXSTM8). + +Compiler-agnostic aspects of the usage of Atomthreads can be found in README. + +Instructions for users of the other compilers are available in README-SDCC, +and README-IAR. + +--------------------------------------------------------------------------- + +STM8 DEVICE HEADERS + +The folder stm8-include contains: + - config.h for device selection and some project settings + - (some) open-source device headers from https://github.com/gicking/STM8_headers + These replace the proprietary headers/drivers by STM from the original STM8 port + +--------------------------------------------------------------------------- + +PREREQUISITES + +The port works out-of-the-box with the Cosmic compiler tools for building. +Applications are generated in .s19 form and can be programmed with any +supporting programming software, including the free STVP (visual +programmer tool). At this time there does not appear to be a command-line +programmer application suitable for use with STM8. + +The Cosmic compiler and STVP are currently Windows-only applications. For +users of other operating systems the Cosmic compiler may work in +environments like Wine, but the USB programming tools are less likely to +be supported. Both the compiler and the USB programming tool for +STM8S-Discovery (STVP) can, however, be run successfully within a VM such +as VirtualBox. + +The core software prerequisites are therefore: + * Cosmic STM8 compiler + * Programming software (e.g. ST's STVP tool) + +Optionally, application build, program and debug can be carried out +using ST's visual debug tool, STVD. + +Use with alternative compiler tools may require some modification, but you +can easily replace STVP by your own favourite programmer if required. + + +--------------------------------------------------------------------------- + +MEMORY MODEL + +The sample build configurations use the Cosmic modsl0 memory model. This +places all data outside of the short 0x0-0x255 page0 area, which allows +large data blocks such as thread stacks to fit. You could instead use the +more efficient mods0 memory model which places data in the short page0 +area, and force large data areas like thread stacks outside of page0 by +adding @near modifiers or specifying data areas by the linker file etc. + +The default configuration is modsl0 (place outside of page0) to allow for +the most portable application compilation, with the option of optimising +this by placing data in page0 if desired. There is no requirement that you +compile your applications using the modsl0 memory model. + + +--------------------------------------------------------------------------- + +BUILDING THE SOURCE + +You may build Atomthreads using whichever build environment you desire. For +your convenience we provide both a ready-rolled Makefile-based build system +and an STVD visual debugger project. The STVD project permits easy +building, programming and debugging, but does not easily support building +a wide range of application builds within the same project, which is +useful for building the numerous automated tests. For the automated tests +you may find it easier to use the Makefile which automatically builds all +automated tests. + + +--------------------------------------------------------------------------- + +BUILD VIA STVD PROJECT + +For building applications using STVD you can use the sample workspace +project file atomthreads-sample-cosmic.stp directly. This builds a sample +full application which runs the "sem1" automated test. Applications can be +downloaded directly to the target hardware (e.g. STM8S-Discovery) and run +via the integrated debugger. Press the exclamation button to run, and +confirm that the LED flashes once per second (if running on an +STM8S-Discovery) to ensure that the test has passed. + +This is also a good starting point for building your own applications: +simply modify the file tests-main.c which starts the test application. +You can run any of the other automated tests by replacing the file sem1.c +within the project by another of the tests within the atomthreads tests +folder. This is rather painful using a GUI interface due to the large +number of test files, and you may prefer to use the Makefile-based system +instead which builds all automated tests in one command. + + +--------------------------------------------------------------------------- + +BUILD VIA MAKEFILE + +A Makefile is also provided for building the kernel, port and automated +tests. This is particularly useful for building the automated tests +because many different independent applications need to be built which is +not easily achieved within the STVD environment. + +For a Windows system you can obtain a Make application suitable for use +with the Cosmic compiler from: + + * http://www.cosmic-software.com/comp_utils/GNU_Make.zip + +Assuming you install the above into C:\Program Files\GNU_MAKE, you +should set up your environment variables as follows: + + * set PATH=%PATH%;C:\Program Files\GNU_MAKE;C:\Program Files\COSMIC\CXSTM8_16K + * set MAKE_MODE=DOS + + +The full build is carried out using simply: + + * make -f cosmic.mak + +All objects are built into the 'build-cosmic' folder under ports/stm8. The +build process builds separate target applications for each automated test, +and appropriate .stm8 or .s19 files can be found in the build folder ready +for downloading to and running on the target. Because of the limited +resources on the STM8, and the large amount of automated tests, each test +is built and run as a separate application. + + +All built objects etc can be cleaned using: + + * make -f cosmic.mak clean + + +The Atomthreads sources are documented using Doxygen markup. You can build +both the kernel and STM8 port documentation from this folder using: + + * make -f cosmic.mak doxygen + + +--------------------------------------------------------------------------- + +PROGRAMMING MAKEFILE-BUILT APPLICATIONS TO THE TARGET DEVICE + +When developing within STVD, programs can be downloaded directly to the +target. If, however, you are building applications separately using a +Makefile or similar, then you are not able to program the application +using STVD. None of the tools delivered by ST appear to be designed to +cater for those who build applications externally, but it is possible using +STVP. + +The following development workflow can be used (note that these settings +apply to the STM8S-Discovery): + + * Build app using Makefile. + * Open STVP and configure to use Swim ST-Link for CPU STM8105C6. + * Open application .s19 file and program using "Program All Tabs". + +Unfortunately STVP does not have a command to reset and start the CPU +running, but it can be forced into doing so by reconfiguring the +programmer: + + * Select "Configure ST Visual Programmer" from the Configure menu. + +Your application should now be programmed and running. + +If you wish to program and run another application then you can open and +program it in STVP, then use the Configure menu again to reset the +device and start it running. + +Other programming tools may exist but are not apparent in the toolset +delivered for use the STM8S Discovery platform. + +--------------------------------------------------------------------------- + +RUNNING THE AUTOMATED TESTS + +Atomthreads contains a set of generic kernel tests which can be run on any +port to prove that all core functionality is working on your target. + +The full set of tests can be found in the top-level 'tests' folder. The +Makefile builds each of these tests as independent applications in the +'build' folder. Run them individually using the STVP process described +above. For example to run the 'kern1.c' test use STVP to program and run +it. + +You may also build the tests using the STVD project, but to run each +different test you must manually remove the previous test module (e.g. +kern1.c) and replace it with one of other tests, which can be quite time +consuming compared to building all tests in one command via the Makefile. + +To view the test results, watch the LED on the STM8S-Discovery. This will +flash once per second if the test passed, and once every 1/8 second if the +test failed. + +If you wish to use the UART, connect a serial debug cable to your target +platform (defaults to 9600bps 8N1). On starting, the test applications +print out "Go" on the UART. Once the test is complete they will print +out "Pass" or "Fail", along with other information if the test failed. + +Most of the tests complete within a few seconds, but some (particularly +the stress tests) can take several seconds, so be patient. + +The full suite of tests endeavours to exercise as much of the kernel code +as possible, and can be used for quick confirmation of core OS +functionality if you ever need to make a change to the kernel or port. + +The test application main() is contained in tests-main.c. This initialises +the OS, creates a main thread, and calls out to the test modules. It also +initialises the UART driver for use by stdout. + + +--------------------------------------------------------------------------- + +WRITING APPLICATIONS + +The easiest way to start a new application which utilises the Atomthreads +scheduler is to base your main application startup on tests-main.c. This +initialises the OS, sets up a UART and calls out to the test module entry +functions. You can generally simply replace the call to the test modules by +a call to your own application startup code. + +Projects developed within STVD can be started using the sample project +atomthreads-sample-cosmic.stp. If you wish to create your own STVD project +from scratch, then you should ensure you change the project settings for +both Debug and Release builds as follows: + +* Toolset: "STM8 Cosmic" +* MCU Selection: Appropriate for your platform (STM8S10C56 for Discovery) +* C Compiler Memory Model: "+modsl0" +* C Compiler Preprocessor Definitions: CPU part (e.g. "STM8S105") +* C Compiler Preprocessor Definitions: Enable thread stack checking if + desired by adding "ATOM_STACK_CHECKING", for example the full + preprocessor line for Discovery might be: "STM8S105 ATOM_STACK_CHECKING" +* Linker Input: Zero Page from 0x2 to 0xFF (allows NULL-pointer checks by + preventing the linker from using address 0x0. +* Linker Input: Ram from 0x100 to 0x7BF (if you wish to allow 0x100 to + 0x7BF for application usage, and 0x7C0 to 0x7FF for startup stack. + + +--------------------------------------------------------------------------- + +COSMIC COMPILER VIRTUAL REGISTERS + +The STM8 has only very few CPU registers, so the Cosmic compiler augments +them with three "virtual" registers, which are simply locations in fast +memory. These registers are called c_x, c_y and c_lreg. + +The Atomthreads context switch for Cosmic/STM8 takes advantage of the fact +that all CPU and virtual registers are automatically saved on the stack by +the compiler when calling out to C functions (and even then only if +necessary). + +For cooperative context switches (where a thread calls an OS kernel +function to schedule itself out), any of these registers which should be +preserved across the function call are automatically saved on the stack by +the compiler before the context switch is even called. This means that no +CPU or virtual registers actually have to be saved in the context switch +routine, making cooperative switches potentially very cheap if few +registers must be preserved. + +For preemptive switches (where an ISR has interrupted a thread and wishes +to switch to a new thread), the interrupt handler prologue automatically +saves all CPU registers (actually done automatically by the CPU) and all +of the virtual registers. In this case all registers must always be saved +because the ISR has no knowledge of what registers the interrupted thread +was using, so we cannot take advantage of the potential for saving fewer +than the full set of registers that we achieve with cooperative switches. +With the Cosmic compiler, interrupt handlers that call out to C functions +(as would happen on a thread switch) always save the CPU registers (done by +the CPU in fact) and the virtual registers c_x and c_y. For the Atomthreads +port we force interrupt handlers to also save the virtual register c_lreg. +This is to ensure that the interrupted thread's c_lreg value is preserved +across a thread switch, but also ensures that longs can be used within the +OS kernel code called by interrupt handlers (c_lreg is used by the compiler +for handling longs and floats). + +An alternative scheme would be to not save c_lreg in all interrupt +handlers and instead save it in the context-switch function. This would +allow interrupt handlers to avoid saving the 4-byte c_lreg on the stack, +but it would mean that any OS kernel code called by interrupt handlers +could not deal with longs, which would be an unfortunate burden on the +core portable OS code just for the benefit of this one architecture and +compiler. It would also mean that c_lreg is always saved unnecessarily +for every cooperative context switch. + + +--------------------------------------------------------------------------- diff --git a/ports/stm8_oss/README-IAR b/ports/stm8_oss/README-IAR new file mode 100644 index 00000000..dee04b93 --- /dev/null +++ b/ports/stm8_oss/README-IAR @@ -0,0 +1,279 @@ +--------------------------------------------------------------------------- + +Library: Atomthreads +Author: Kelvin Lawson +Website: http://atomthreads.com +License: BSD Revised + +--------------------------------------------------------------------------- + +STM8 PORT - IAR COMPILER + +This folder contains a port of the Atomthreads real time kernel for the +STM8 processor architecture. These instructions cover usage of Atomthreads +with the IAR Embedded Workbench compiler (EWSTM8). + +Compiler-agnostic aspects of the usage of Atomthreads can be found in README. + +Instructions for users of the other compilers are available in README-SDCC and +README-COSMIC. + +--------------------------------------------------------------------------- + +STM8 DEVICE HEADERS + +The folder stm8-include contains: + - config.h for device selection and some project settings + - (some) open-source device headers from https://github.com/gicking/STM8_headers + These replace the proprietary headers/drivers by STM from the original STM8 port + +--------------------------------------------------------------------------- + +PREREQUISITES + +The port works out-of-the-box with the IAR compiler tools for building. +Applications are generated in ELF format and can be programmed and debugged +using the IAR Embedded Workbench GUI or the free STVP (visual programmer +tool). At this time there does not appear to be a command-line programmer +application suitable for use with STM8. + +IAR Embedded Workbench for STM8 is a Windows-only application. For +users of other operating systems the IAR tools may work in environments +like Wine, but the USB programming tools are less likely to be supported. +Embedded Workbench for STM8 can, however, be run successfully within a VM +such as VirtualBox, including USB download and debug. + +The core software prerequisites are therefore: + * IAR Embedded Workbench STM8 + +Use with alternative compiler tools may require some modification, but you +can easily replace the EWSTM8 IDE by your own favourite programmer if +required (e.g. STVP). + + +--------------------------------------------------------------------------- + +BUILDING THE SOURCE + +You may build Atomthreads using whichever build environment you desire. For +your convenience we provide both a ready-rolled Makefile-based build system +and an Embedded Workbench (EWSTM8) project. The EWSTM8 project permits easy +building, programming and debugging, but does not easily support building +a wide range of application builds within the same project, which is +useful for building the numerous automated tests. For the automated tests +you may find it easier to use the Makefile which automatically builds all +automated tests. + + +--------------------------------------------------------------------------- + +BUILD VIA EWSTM8 PROJECT + +For building applications using the EWSTM8 IDE you can use the sample +project file atomthreads-sample-iar.ewp. This builds a sample full +application which runs the "sem1" automated test. Applications can be +downloaded directly to the target hardware (e.g. STM8S-Discovery) and run +via the integrated debugger. You can start the application running, and +confirm that the LED flashes once per second (if running on an +STM8S-Discovery) to ensure that the test has passed. + +This is also a good starting point for building your own applications: +simply modify the file tests-main.c which starts the test application. +You can run any of the other automated tests by replacing the file sem1.c +within the project by another of the tests within the atomthreads tests +folder. This is rather painful using a GUI interface due to the large +number of test files, and you may prefer to use the Makefile-based system +instead which builds all automated tests in one command. + + +--------------------------------------------------------------------------- + +BUILD VIA MAKEFILE + +A Makefile is also provided for building the kernel, port and automated +tests. This is particularly useful for building the automated tests +because many different independent applications need to be built which is +not easily achieved within the EWSTM8 environment. + +For a Windows system you can obtain a Make application suitable for use +with the IAR compiler from: + + * http://www.cosmic-software.com/comp_utils/GNU_Make.zip + +Assuming you install the above into C:\Program Files\GNU_MAKE, you +should set up your environment variables as follows: + + * set PATH=%PATH%;C:\Program Files\GNU_MAKE;C:\Program Files\IAR Systems\Embedded Workbench 6.0\stm8\bin + * set MAKE_MODE=DOS + + +The full build is carried out using simply: + + * make -f iar.mak + +All objects are built into the 'build-iar' folder under ports/stm8. The +build process builds separate target applications for each automated test, +and appropriate .elf or .s19 files can be found in the build folder ready +for downloading to and running on the target. Because of the limited +resources on the STM8, and the large amount of automated tests, each test +is built and run as a separate application. + + +All built objects etc can be cleaned using: + + * make -f iar.mak clean + + +The Atomthreads sources are documented using Doxygen markup. You can build +both the kernel and STM8 port documentation from this folder using: + + * make -f iar.mak doxygen + + +--------------------------------------------------------------------------- + +PROGRAMMING MAKEFILE-BUILT APPLICATIONS TO THE TARGET DEVICE + +When developing within EWSTM8, programs can be downloaded directly to the +target. If, however, you are building applications separately using a +Makefile or similar, then you are not able to program the application +using EWSTM8. None of the tools delivered by ST appear to be designed to +cater for those who build applications externally, but it is possible using +STVP. + +The following development workflow can be used (note that these settings +apply to the STM8S-Discovery): + + * Build app using Makefile. + * Open STVP and configure to use Swim ST-Link for CPU STM8105C6. + * Open application .s19 file and program using "Program All Tabs". + +Unfortunately STVP does not have a command to reset and start the CPU +running, but it can be forced into doing so by reconfiguring the +programmer: + + * Select "Configure ST Visual Programmer" from the Configure menu. + +Your application should now be programmed and running. + +If you wish to program and run another application then you can open and +program it in STVP, then use the Configure menu again to reset the +device and start it running. + +Other programming tools may exist but are not apparent in the toolset +delivered for use the STM8S Discovery platform. + +--------------------------------------------------------------------------- + +RUNNING THE AUTOMATED TESTS + +Atomthreads contains a set of generic kernel tests which can be run on any +port to prove that all core functionality is working on your target. + +The full set of tests can be found in the top-level 'tests' folder. The +Makefile builds each of these tests as independent applications in the +'build' folder. Run them individually using the STVP process described +above. For example to run the 'kern1.c' test use STVP to program and run +it. + +You may also build the tests using the EWSTM8 project, but to run each +different test you must manually remove the previous test module (e.g. +kern1.c) and replace it with one of other tests, which can be quite time +consuming compared to building all tests in one command via the Makefile. + +To view the test results, watch the LED on the STM8S-Discovery. This will +flash once per second if the test passed, and once every 1/8 second if the +test failed. + +If you wish to use the UART, connect a serial debug cable to your target +platform (defaults to 9600bps 8N1). On starting, the test applications +print out "Go" on the UART. Once the test is complete they will print +out "Pass" or "Fail", along with other information if the test failed. + +Most of the tests complete within a few seconds, but some (particularly +the stress tests) can take several seconds, so be patient. + +The full suite of tests endeavours to exercise as much of the kernel code +as possible, and can be used for quick confirmation of core OS +functionality if you ever need to make a change to the kernel or port. + +The test application main() is contained in tests-main.c. This initialises +the OS, creates a main thread, and calls out to the test modules. It also +initialises the UART driver for use by stdout. + + +--------------------------------------------------------------------------- + +WRITING APPLICATIONS + +The easiest way to start a new application which utilises the Atomthreads +scheduler is to base your main application startup on tests-main.c. This +initialises the OS, sets up a UART and calls out to the test module entry +functions. You can generally simply replace the call to the test modules by +a call to your own application startup code. + +Projects developed within EWSTM8 can be started using the sample project +atomthreads-sample-iar.ewp. If you wish to create your own EWSTM8 project +from scratch, then you should ensure you change the project settings for +both Debug and Release builds as follows: + +* General Options -> Target -> Device: CPU part (e.g. "STM8S105C6") +* C/C++ Compiler -> Diagnostics: Suppress "Pa050" +* C/C++ Compiler -> Preprocessor -> Defined Symbols: + CPU part (e.g. "STM8S105") + Thread stack-checking if required ("ATOM_STACK_CHECKING") + For example "STM8S105, ATOM_STACK_CHECKING" +* Assembler -> Diagnostics: Suppress "Pa050" +* Repeat above for Debug and Release projects (you may want to + disable ATOM_STACK_CHECKING for Release builds). + +Other options you may wish to change: + +* Tools -> Options -> Editor -> EOL Characters: "Preserve". This preserves + the line endings, bearing in mind that the Atomthreads kernels works + with many host operating system toolchains. +* Options -> Debugger -> "ST Link" (e.g. for STM8S Discovery) + +Add the .C and .S modules from the following folders: +* kernel +* ports/stm8 +* ports/stm8s-periphs + +Set include paths as appropriate. + + +--------------------------------------------------------------------------- + +IAR COMPILER VIRTUAL REGISTERS + +The STM8 has only very few CPU registers, so the IAR compiler augments +them with sixteen "virtual" registers, which are simply locations in fast +memory. These registers are called ?b0 to ?b15. + +The Atomthreads context switch for IAR/STM8 takes advantage of the fact +that all CPU and most virtual registers are automatically saved on the +stack by the compiler when calling out to C functions (and even then only +if necessary). Only the virtual registers ?b8 to ?b15 are expected to be +preserved by called functions, so these are the only registers that +callers to the context switch routine will not automatically save if +necessary. + +For cooperative context switches (where a thread calls an OS kernel +function to schedule itself out), most registers will therefore already +be saved on a thread's stack if necessary. Only ?b8 to ?b15 actually have +to be saved in the context switch routine, making cooperative switches +potentially very cheap if few registers must be preserved. + +For preemptive switches (where an ISR has interrupted a thread and wishes +to switch to a new thread), the interrupt handler prologue automatically +saves all CPU registers (actually done automatically by the CPU) and the +virtual registers ?b0 to ?b7. Still only the registers ?b8 to ?b15 have to +be saved by the context-switch routine, but in this case ?b0 to ?b7 and the +CPU registers are always saved on the thread's stack by the ISR prologue. +This is because the ISR has no knowledge of what registers the interrupted +thread was using, so we cannot take advantage of the potential for saving +fewer than the full set of registers that we achieve with cooperative +switches. + + +--------------------------------------------------------------------------- diff --git a/ports/stm8_oss/README-SDCC b/ports/stm8_oss/README-SDCC new file mode 100644 index 00000000..23f18cc0 --- /dev/null +++ b/ports/stm8_oss/README-SDCC @@ -0,0 +1,72 @@ +--------------------------------------------------------------------------- + +Author: Dr. Philipp Klaus Krause + +Update: Georg Icking-Konert for OSS device headers & omit Raisonance + +--------------------------------------------------------------------------- + +STM8 PORT - SMALL DEVICE C COMPILER + +This folder contains a port of the Atomthreads real time kernel for the +STM8 processor architecture. These instructions cover usage of Atomthreads +with the Small Device C Compiler (SDCC). + +This README covers usage of Atomthreads with SDCC. +Instructions for users of the other compilers are available in README-COSMIC +and README-IAR. + +--------------------------------------------------------------------------- + +STM8 DEVICE HEADERS + +The folder stm8-include contains: + - config.h for device selection and some project settings + - (some) open-source device headers from https://github.com/gicking/STM8_headers + These replace the proprietary headers/drivers by STM from the original STM8 port + +--------------------------------------------------------------------------- + +PREREQUISITES + +The port works out-of-the-box with SDCC and GNU make for +building. + + * SDCC 3.6.0 or later + * Programming software (e.g. stm8flash or stm8gal) + + +--------------------------------------------------------------------------- + +BUILD VIA MAKEFILE + + * make -f sdcc.mak + +All objects are built into the 'build-sdcc' folder under ports/stm8. +The build process builds separate target applications for each automated +test, and appropriate .ihx files can be found in the build folder +ready for downloading to and running on the target. Because of the limited +resources on the STM8, and the large amount of automated tests, each test +is built and run as a separate application. + +All built objects etc can be cleaned using: + + * make -f sdcc.mak clean + +The Atomthreads sources are documented using Doxygen markup. You can build +both the kernel and STM8 port documentation from this folder using: + + * make -f sdcc.mak doxygen + + +--------------------------------------------------------------------------- + +PROGRAMMING MAKEFILE-BUILT APPLICATIONS TO THE TARGET DEVICE + +Applications can be written onto the STM8 board using: + + * SWIM: stm8flash -c stlink -p stm8s105c6 -w + + * Bootloader: stm8gal -p -V 1 -w + +--------------------------------------------------------------------------- diff --git a/ports/stm8_oss/atomport-asm-cosmic.s b/ports/stm8_oss/atomport-asm-cosmic.s new file mode 100644 index 00000000..7e9e2c28 --- /dev/null +++ b/ports/stm8_oss/atomport-asm-cosmic.s @@ -0,0 +1,364 @@ +; +; Copyright (c) 2010, Atomthreads Project. All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; Modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; 3. No personal names or organizations' names associated with the +; Atomthreads project may be used to endorse or promote products +; derived from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; + + +; Cosmic assembler routines + + +; Export functions to other modules +xdef _archContextSwitch, _archFirstThreadRestore + + +; \b archContextSwitch +; +; Architecture-specific context switch routine. +; +; Note that interrupts are always locked out when this routine is +; called. For cooperative switches, the scheduler will have entered +; a critical region. For preemptions (called from an ISR), the +; ISR will have disabled interrupts on entry. +; +; @param[in] old_tcb_ptr Pointer to the thread being scheduled out +; @param[in] new_tcb_ptr Pointer to the thread being scheduled in +; +; @return None +; +; void archContextSwitch (ATOM_TCB *old_tcb_ptr, ATOM_TCB *new_tcb_ptr) +_archContextSwitch: + + ; Parameter locations (Cosmic calling convention): + ; old_tcb_ptr = X register (word-width) + ; new_tcb_ptr = stack (word-width) + + ; STM8 CPU Registers: + ; + ; A, X, Y: Standard working registers + ; SP: Stack pointer + ; PC: Program counter + ; CC: Code condition register + ; + ; Cosmic compiler virtual registers: + ; + ; c_x, c_y: Scratch memory areas saved by ISRs + ; c_lreg: Scratch memory area only saved by ISRs with @svlreg + ; + ; If this is a cooperative context switch (a thread has called us + ; to schedule itself out), the Cosmic compiler will have saved any + ; of the registers which it does not want us to clobber. There are + ; no registers which are expected to retain their value across a + ; function call, hence for cooperative context switches with this + ; compiler we do not actually need to save any registers at all. + ; + ; If we were called from an interrupt routine (because a thread + ; is being preemptively scheduled out), the situation is exactly + ; the same. Any ISR which calls out to a subroutine will have + ; similarly saved all registers which it needs us not to clobber + ; which in the case of this compiler is all registers. Again, we + ; do not need to save any registers because no registers are + ; expected to be unclobbered by a subroutine. Note that it is + ; necessary to add the @svlreg modifier to ISRs which call out to + ; the OS in order to force a save of c_lreg. The rest of the CPU + ; registers and the c_x and c_y virtual registers are, however, + ; always saved by ISRs which call out to C subroutines. + ; + ; This is an unusual context switch routine, because it does not + ; need to actually save any registers. Instead, the act of + ; calling this function causes all registers which must not be + ; clobbered to be saved on the stack anyway in the case of + ; cooperative context switches. For preemptive switches, the + ; interrupt service routine which calls out to here also causes + ; all registers to be saved in a similar fashion. + + ; We do have to do some work in here though: we need to store + ; the current stack pointer to the current thread's TCB, and + ; switch in the new thread by taking the stack pointer from + ; the new thread's TCB and making that our new stack pointer. + + ; The parameter pointing to the the old TCB (a word-width + ; pointer) is still untouched in the X register. + + ; Store current stack pointer as first entry in old_tcb_ptr + ldw Y, SP ; Move current stack pointer into Y register + ldw (X), Y ; Store current stack pointer at first offset in TCB + + + ; At this point, all of the current thread's context has been saved + ; so we no longer care about keeping the contents of any registers. + ; We do still need the first two bytes on the current thread's stack, + ; however, which contain new_tcb_ptr (a pointer to the TCB of the + ; thread which we wish to switch in). + ; + ; Our stack frame now contains all registers (if this is a preemptive + ; switch due to an interrupt handler) or those registers which the + ; calling function did not wish to be clobbered (if this is a + ; cooperative context switch). It also contains the return address + ; which will be either a function called via an ISR (for preemptive + ; switches) or a function called from thread context (for cooperative + ; switches). Finally, the stack also contains the aforementioned + ; word which is the new_tcb_ptr parameter passed via the stack. + ; + ; In addition, the thread's stack pointer (after context-save) is + ; stored in the thread's TCB. + + ; We are now ready to restore the new thread's context. In most + ; architecture ports we would typically switch our stack pointer + ; to the new thread's stack pointer, and pop all of its context + ; off the stack, before returning to the caller (the original + ; caller when the new thread was last scheduled out). In this + ; port, however, we do not need to actually restore any + ; registers here because none are saved when we switch out (at + ; least not by this function). We switch to the new thread's + ; stack pointer and then return to the original caller, which + ; will restore any registers which had to be saved. + + ; Get the new thread's stack pointer off the TCB (new_tcb_ptr). + ; new_tcb_ptr is still stored in the previous thread's stack. + ; We are free to use any registers here. + + ; Pull the new_tcb_ptr parameter from the stack into X register + ldw X,($3,SP) + + ; Pull the first entry out of new_tcb_ptr (the new thread's + ; stack pointer) into X register. + ldw X,(X) + + ; Switch our current stack pointer to that of the new thread. + ldw SP,X + + ; Normally we would start restoring registers from the new + ; thread's stack here, but we don't save/restore any. We're + ; almost done. + + ; The return address on the stack will now be the new thread's return + ; address - i.e. although we just entered this function from a + ; function called by the old thread, now that we have restored the new + ; thread's stack, we actually return from this function to wherever + ; the new thread was when it was previously scheduled out. This could + ; be either a regular C routine if the new thread previously scheduled + ; itself out cooperatively, or it could be an ISR if this new thread was + ; previously preempted (on exiting the ISR, execution will return to + ; wherever the new thread was originally interrupted). + + ; Return to the caller. Note that we always use a regular RET here + ; because this is a subroutine regardless of whether we were called + ; during an ISR or by a thread cooperatively switching out. The + ; difference between RET and IRET on the STM8 architecture is that + ; RET only pops the return address off the stack, while IRET also + ; pops from the stack all of the CPU registers saved when the ISR + ; started, including restoring the interrupt-enable bits from the CC + ; register. + ; + ; It is important that whenever we call this function (whether from + ; an ISR for preemptive switches or from thread context for + ; cooperative switches) interrupts are always disabled. This means + ; that whichever method by which we leave this routine we always + ; have to reenable interrupts, so we can use the same context-switch + ; routine for preemptive and cooperative switches. + ; + ; The possible call/return paths are as follows: + ; + ; Scenario 1 (cooperative -> cooperative): + ; Thread A: cooperatively switches out + ; * Thread A relinquishes control / cooperatively switches out + ; * Interrupts already disabled by kernel for cooperative reschedules + ; * Partial register context saved by calling function + ; * Call here at thread context + ; * Switch to Thread B + ; Thread B (was previously cooperatively switched out): + ; * Stack context for Thread B contains its return address + ; * Return to function which was called at thread context + ; * Interrupts are reenabled by CRITICAL_END() call in kernel + ; * Return to Thread B application code + ; + ; Scenario 2 (preemptive -> preemptive): + ; Thread A: preemptively switches out + ; * ISR occurs + ; * Interrupts disabled by CPU at ISR entry (assume no nesting allowed) + ; * Full register context saved by CPU at ISR entry + ; * Call here at ISR context + ; * Switch to Thread B + ; Thread B (was previously preemptively switched out): + ; * Stack context for Thread B contains its return address + ; and all context saved by the CPU on ISR entry + ; * Return to function which was called at ISR context + ; * Eventually returns to calling ISR which calls IRET + ; * IRET performs full register context restore + ; * IRET reenables interrupts + ; * Return to Thread B application code + ; + ; Scenario 3 (cooperative -> preemptive): + ; Thread A: cooperatively switches out + ; * Thread A relinquishes control / cooperatively switches out + ; * Interrupts already disabled by kernel for cooperative reschedules + ; * Partial register context saved by calling function + ; * Call here at thread context + ; * Switch to Thread B + ; Thread B (was previously preemptively switched out): + ; * Stack context for Thread B contains its return address + ; and all context saved by the CPU on ISR entry + ; * Return to function which was called at ISR context + ; * Eventually returns to calling ISR which calls IRET + ; * IRET performs full register context restore + ; * IRET reenables interrupts + ; * Return to Thread B application code + ; + ; Scenario 4 (preemptive -> cooperative): + ; Thread A: preemptively switches out + ; * ISR occurs + ; * Interrupts disabled by CPU at ISR entry (assume no nesting allowed) + ; * Full register context saved by CPU at ISR entry + ; * Call here at ISR context + ; * Switch to Thread B + ; Thread B (was previously cooperatively switched out): + ; * Stack context for Thread B contains its return address + ; * Return to function which was called at thread context + ; * Interrupts are reenabled by CRITICAL_END() call in kernel + ; * Return to Thread B application code + ; + ; The above shows that it does not matter whether we are rescheduling + ; from/to thread context or ISR context. It is perfectly valid to + ; enter here at ISR context but leave via a thread which previously + ; cooperatively switched out because: + ; 1. Although the CPU handles ISRs differently by automatically + ; stacking all 6 CPU registers, and restoring them on an IRET, + ; we handle this because we switch the stack pointer to a + ; different thread's stack. Because the stack pointer is + ; switched, it does not matter that on entry via ISRs more + ; registers are saved on the original thread's stack than entries + ; via non-ISRs. Those extra registers will be restored properly + ; by an IRET when the thread is eventually scheduled back in + ; (which could be a long way off). This assumes that the CPU does + ; not have hidden behaviour that occurs on interrupts, and we can + ; in fact trick it into leaving via another thread's call stack, + ; and performing the IRET much later. + ; 2. Although the CPU handles ISRs differently by setting the CC + ; register interrupt-enable bits on entry/exit, we handle this + ; anyway by always assuming interrupts are disabled on entry + ; and exit regardless of the call path. + + ; Return from subroutine + ret + + +; \b archFirstThreadRestore +; +; Architecture-specific function to restore and start the first thread. +; This is called by atomOSStart() when the OS is starting. Its job is to +; restore the context for the first thread and start running at its +; entry point. +; +; All new threads have a stack context pre-initialised with suitable +; data for being restored by either this function or the normal +; function used for scheduling threads in, archContextSwitch(). Only +; the first thread run by the system is launched via this function, +; after which all other new threads will first be run by +; archContextSwitch(). +; +; Typically ports will implement something similar here to the +; latter half of archContextSwitch(). In this port the context +; switch does not restore many registers, and instead relies on the +; fact that returning from any function which called +; archContextSwitch() will restore any of the necessary registers. +; For new threads which have never been run there is no calling +; function which will restore context on return, therefore we +; do not restore many register values here. It is not necessary +; for the new threads to have initialised values for the scratch +; registers A, X and Y or the code condition register CC which +; leaves SP and PC. SP is restored because this is always needed to +; switch to a new thread's stack context. It is not necessary to +; restore PC, because the thread's entry point is in the stack +; context (when this function returns using RET the PC is +; automatically changed to the thread's entry point because the +; entry point is stored in the preinitialised stack). +; +; When new threads are started interrupts must be enabled, so there +; is some scope for enabling interrupts in the CC here. It must be +; done for all new threads, however, not just the first thread, so +; we use a different system. We instead use a thread shell routine +; which all functions run when they are first started, and +; interrupts are enabled in there. This allows us to avoid having +; to enable interrupts both in here and in the normal context +; switch routine (archContextSwitch()). For the normal context +; switch routine we would otherwise need to pass in notification of +; and implement special handling for the first time a thread is +; restored. +; +; In summary, first threads do not require a set of CPU registers +; to be initialised to known values, so we only set SP to the new +; thread's stack pointer. PC is restored for free because the RET +; call at the end of this function pops the return address off the +; stack. +; +; Note that you can create more than one thread before starting +; the OS - only one thread is restored using this function, so +; all other threads are actually restored by archContextSwitch(). +; This is another reminder that the initial context set up by +; archThreadContextInit() must look the same whether restored by +; archFirstThreadRestore() or archContextSwitch(). +; +; @param[in] new_tcb_ptr Pointer to the thread being scheduled in +; +; @return None +; +; void archFirstThreadRestore (ATOM_TCB *new_tcb_ptr) +_archFirstThreadRestore: + + ; Parameter locations: + ; new_tcb_ptr = X register (word-width) + + ; As described above, first thread restores in this port do not + ; expect any initial register context to be pre-initialised in + ; the thread's stack area. The thread's initial stack need only + ; contain the thread's initial entry point, and we do not even + ; "restore" that within this function. We leave the thread's entry + ; point in the stack, and RET at the end of the function pops it + ; off and "returns" to the entry point as if we were called from + ; there. + ; + ; The one thing we do need to set in here, though, is the thread's + ; stack pointer. This is available from the passed thread TCB + ; structure. + + ; Get the new thread's stack pointer off the TCB (new_tcb_ptr). + ; new_tcb_ptr is stored in the parameter register X. The stack + ; pointer it conveniently located at the top of the TCB so no + ; indexing is required to pull it out. + ldw X,(X) + + ; Switch our current stack pointer to that of the new thread. + ldw SP,X + + ; The "return address" left on the stack now will be the new + ; thread's entry point. RET will take us there as if we had + ; actually been there before calling this subroutine, whereas + ; the return address was actually set up by archThreadContextInit(). + ret + + + end diff --git a/ports/stm8_oss/atomport-asm-iar.s b/ports/stm8_oss/atomport-asm-iar.s new file mode 100644 index 00000000..1c79d1d6 --- /dev/null +++ b/ports/stm8_oss/atomport-asm-iar.s @@ -0,0 +1,396 @@ +; +; Copyright (c) 2010, Atomthreads Project. All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; Modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; 3. No personal names or organizations' names associated with the +; Atomthreads project may be used to endorse or promote products +; derived from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; + + +; IAR assembler routines + + + NAME ATOMPORTASM + SECTION .near_func.text:code + +; Get definitions for virtual registers used by the compiler +#include "vregs.inc" + + +; \b archContextSwitch +; +; Architecture-specific context switch routine. +; +; Note that interrupts are always locked out when this routine is +; called. For cooperative switches, the scheduler will have entered +; a critical region. For preemptions (called from an ISR), the +; ISR will have disabled interrupts on entry. +; +; @param[in] old_tcb_ptr Pointer to the thread being scheduled out +; @param[in] new_tcb_ptr Pointer to the thread being scheduled in +; +; @return None +; +; void archContextSwitch (ATOM_TCB *old_tcb_ptr, ATOM_TCB *new_tcb_ptr) + PUBLIC archContextSwitch +archContextSwitch: + + ; Parameter locations (IAR calling convention): + ; old_tcb_ptr = X register (word-width) + ; new_tcb_ptr = Y register (word-width) + + ; STM8 CPU Registers: + ; + ; A, X, Y: Standard working registers + ; SP: Stack pointer + ; PC: Program counter + ; CC: Code condition register + ; + ; IAR compiler virtual registers + ; + ; ?b0 - ?b7: Scratch registers + ; ?b8 - ?b15: Preserved registers + ; + ; The basic scheme is that some registers will already be saved + ; onto the stack if the caller wishes them not to be clobbered. + ; We only need to context-switch additional registers which the + ; caller does not expect to be modified in a subroutine. + ; + ; If this is a cooperative context switch (a thread has called us + ; to schedule itself out), the IAR compiler will have saved any + ; of the registers which it does not want us to clobber. For IAR + ; only virtual registers ?b8 to ?b15 are expected to retain their + ; value across a function call, hence for cooperative context + ; switches with this compiler we only need to save ?b8 to ?b15. + ; + ; If we were called from an interrupt routine (because a thread + ; is being preemptively scheduled out), the situation is exactly + ; the same. Any ISR which calls out to a subroutine will have + ; similarly saved all registers which it needs us not to clobber, + ; leaving only ?b8 to ?b15 which must be saved. + ; + ; The Cosmic compiler version of this context switch routine + ; does not require any registers to be saved/restored, whereas + ; this IAR equivalent reqires that 8 of the virtual registers + ; are. + + ; We also have to do a little more work in here: we need to store + ; the current stack pointer to the current thread's TCB, and + ; switch in the new thread by taking the stack pointer from + ; the new thread's TCB and making that our new stack pointer. + + ; (IAR) Compiler will have already saved any scratch registers + ; (A, X, Y, CC, and ?b0 to ?b7) which it needs before calling here + ; for cooperative switches. So these will already be on the stack + ; and do not need to be context-switched. The same goes for + ; __interrupt functions (i.e. preemptive switches): with the IAR + ; compiler A, X, Y and CC will already be saved by interrupt handlers + ; (those are actually automatically done by the CPU), and (because + ; we call out from interrupt handlers to C kernel code (e.g. + ; atomIntExit()) before calling here for a context-switch, the + ; compiler will also have saved ?b0 to ?b7. This is because those + ; called C functions cannot know they were called from an interrupt + ; and will assume that they have ?b0 to ?b7 available as scratch + ; registers. Either way (cooperative or interrupt/preemptive) we + ; know that the only registers which must be preserved that are not + ; already on the stack-frame are ?b8 to ?b15. + PUSH ?b8 + PUSH ?b9 + PUSH ?b10 + PUSH ?b11 + PUSH ?b12 + PUSH ?b13 + PUSH ?b14 + PUSH ?b15 + + ; The parameter pointing to the the old TCB (a word-width + ; pointer) is still untouched in the X register. + + ; (IAR) Take a copy of the new_tcb_ptr parameter from Y-reg in + ; a temporary (?b0) register. We need to use Y briefly for SP + ; access. + ldw ?b0, Y + + ; Store current stack pointer as first entry in old_tcb_ptr + ldw Y, SP ; Move current stack pointer into Y register + ldw (X), Y ; Store current stack pointer at first offset in TCB + + + ; At this point, all of the current thread's context has been saved + ; so we no longer care about keeping the contents of any registers + ; except ?b0 which contains our passed new_tcb_ptr parameter (a + ; pointer to the TCB of the thread which we wish to switch in). + ; + ; Our stack frame now contains all registers which need to be + ; preserved or context-switched. It also contains the return address + ; which will be either a function called via an ISR (for preemptive + ; switches) or a function called from thread context (for cooperative + ; switches). + ; + ; In addition, the thread's stack pointer (after context-save) is + ; stored in the thread's TCB. + + ; We are now ready to restore the new thread's context. We switch + ; our stack pointer to the new thread's stack pointer, and pop its + ; context off the stack, before returning to the caller (the + ; original caller when the new thread was last scheduled out). + + ; Get the new thread's stack pointer off the TCB (new_tcb_ptr). + ; We kept a copy of new_tcb_ptr earlier in ?b0, copy it into X. + ldw X,?b0 + + ; Pull the first entry out of new_tcb_ptr (the new thread's + ; stack pointer) into X register. + ldw X,(X) + + ; Switch our current stack pointer to that of the new thread. + ldw SP,X + + ; (IAR) We only save/restore ?b8 to ?b15 + POP ?b15 + POP ?b14 + POP ?b13 + POP ?b12 + POP ?b11 + POP ?b10 + POP ?b9 + POP ?b8 + + ; The return address on the stack will now be the new thread's return + ; address - i.e. although we just entered this function from a + ; function called by the old thread, now that we have restored the new + ; thread's stack, we actually return from this function to wherever + ; the new thread was when it was previously scheduled out. This could + ; be either a regular C routine if the new thread previously scheduled + ; itself out cooperatively, or it could be an ISR if this new thread was + ; previously preempted (on exiting the ISR, execution will return to + ; wherever the new thread was originally interrupted). + + ; Return to the caller. Note that we always use a regular RET here + ; because this is a subroutine regardless of whether we were called + ; during an ISR or by a thread cooperatively switching out. The + ; difference between RET and IRET on the STM8 architecture is that + ; RET only pops the return address off the stack, while IRET also + ; pops from the stack all of the CPU registers saved when the ISR + ; started, including restoring the interrupt-enable bits from the CC + ; register. + ; + ; It is important that whenever we call this function (whether from + ; an ISR for preemptive switches or from thread context for + ; cooperative switches) interrupts are always disabled. This means + ; that whichever method by which we leave this routine we always + ; have to reenable interrupts, so we can use the same context-switch + ; routine for preemptive and cooperative switches. + ; + ; The possible call/return paths are as follows: + ; + ; Scenario 1 (cooperative -> cooperative): + ; Thread A: cooperatively switches out + ; * Thread A relinquishes control / cooperatively switches out + ; * Interrupts already disabled by kernel for cooperative reschedules + ; * Partial register context saved by calling function + ; * Call here at thread context + ; * Switch to Thread B + ; Thread B (was previously cooperatively switched out): + ; * Stack context for Thread B contains its return address + ; * Return to function which was called at thread context + ; * Interrupts are reenabled by CRITICAL_END() call in kernel + ; * Return to Thread B application code + ; + ; Scenario 2 (preemptive -> preemptive): + ; Thread A: preemptively switches out + ; * ISR occurs + ; * Interrupts disabled by CPU at ISR entry (assume no nesting allowed) + ; * Full register context saved by CPU at ISR entry + ; * Call here at ISR context + ; * Switch to Thread B + ; Thread B (was previously preemptively switched out): + ; * Stack context for Thread B contains its return address + ; and all context saved by the CPU on ISR entry + ; * Return to function which was called at ISR context + ; * Eventually returns to calling ISR which calls IRET + ; * IRET performs full register context restore + ; * IRET reenables interrupts + ; * Return to Thread B application code + ; + ; Scenario 3 (cooperative -> preemptive): + ; Thread A: cooperatively switches out + ; * Thread A relinquishes control / cooperatively switches out + ; * Interrupts already disabled by kernel for cooperative reschedules + ; * Partial register context saved by calling function + ; * Call here at thread context + ; * Switch to Thread B + ; Thread B (was previously preemptively switched out): + ; * Stack context for Thread B contains its return address + ; and all context saved by the CPU on ISR entry + ; * Return to function which was called at ISR context + ; * Eventually returns to calling ISR which calls IRET + ; * IRET performs full register context restore + ; * IRET reenables interrupts + ; * Return to Thread B application code + ; + ; Scenario 4 (preemptive -> cooperative): + ; Thread A: preemptively switches out + ; * ISR occurs + ; * Interrupts disabled by CPU at ISR entry (assume no nesting allowed) + ; * Full register context saved by CPU at ISR entry + ; * Call here at ISR context + ; * Switch to Thread B + ; Thread B (was previously cooperatively switched out): + ; * Stack context for Thread B contains its return address + ; * Return to function which was called at thread context + ; * Interrupts are reenabled by CRITICAL_END() call in kernel + ; * Return to Thread B application code + ; + ; The above shows that it does not matter whether we are rescheduling + ; from/to thread context or ISR context. It is perfectly valid to + ; enter here at ISR context but leave via a thread which previously + ; cooperatively switched out because: + ; 1. Although the CPU handles ISRs differently by automatically + ; stacking all 6 CPU registers, and restoring them on an IRET, + ; we handle this because we switch the stack pointer to a + ; different thread's stack. Because the stack pointer is + ; switched, it does not matter that on entry via ISRs more + ; registers are saved on the original thread's stack than entries + ; via non-ISRs. Those extra registers will be restored properly + ; by an IRET when the thread is eventually scheduled back in + ; (which could be a long way off). This assumes that the CPU does + ; not have hidden behaviour that occurs on interrupts, and we can + ; in fact trick it into leaving via another thread's call stack, + ; and performing the IRET much later. + ; 2. Although the CPU handles ISRs differently by setting the CC + ; register interrupt-enable bits on entry/exit, we handle this + ; anyway by always assuming interrupts are disabled on entry + ; and exit regardless of the call path. + + ; Return from subroutine + ret + + +; \b archFirstThreadRestore +; +; Architecture-specific function to restore and start the first thread. +; This is called by atomOSStart() when the OS is starting. Its job is to +; restore the context for the first thread and start running at its +; entry point. +; +; All new threads have a stack context pre-initialised with suitable +; data for being restored by either this function or the normal +; function used for scheduling threads in, archContextSwitch(). Only +; the first thread run by the system is launched via this function, +; after which all other new threads will first be run by +; archContextSwitch(). +; +; Typically ports will implement something similar here to the +; latter half of archContextSwitch(). In this port the context +; switch does not restore many registers, and instead relies on the +; fact that returning from any function which called +; archContextSwitch() will restore any of the necessary registers. +; For new threads which have never been run there is no calling +; function which will restore context on return, therefore we +; do not restore many register values here. It is not necessary +; for the new threads to have initialised values for the scratch +; registers A, X and Y or the code condition register CC which +; leaves SP and PC. SP is restored because this is always needed to +; switch to a new thread's stack context. It is not necessary to +; restore PC, because the thread's entry point is in the stack +; context (when this function returns using RET the PC is +; automatically changed to the thread's entry point because the +; entry point is stored in the preinitialised stack). +; +; When new threads are started interrupts must be enabled, so there +; is some scope for enabling interrupts in the CC here. It must be +; done for all new threads, however, not just the first thread, so +; we use a different system. We instead use a thread shell routine +; which all functions run when they are first started, and +; interrupts are enabled in there. This allows us to avoid having +; to enable interrupts both in here and in the normal context +; switch routine (archContextSwitch()). For the normal context +; switch routine we would otherwise need to pass in notification of +; and implement special handling for the first time a thread is +; restored. +; +; In summary, first threads do not require a set of CPU registers +; to be initialised to known values, so we only set SP to the new +; thread's stack pointer. PC is restored for free because the RET +; call at the end of this function pops the return address off the +; stack. +; +; Note that you can create more than one thread before starting +; the OS - only one thread is restored using this function, so +; all other threads are actually restored by archContextSwitch(). +; This is another reminder that the initial context set up by +; archThreadContextInit() must look the same whether restored by +; archFirstThreadRestore() or archContextSwitch(). +; +; @param[in] new_tcb_ptr Pointer to the thread being scheduled in +; +; @return None +; +; void archFirstThreadRestore (ATOM_TCB *new_tcb_ptr) + PUBLIC archFirstThreadRestore +archFirstThreadRestore: + ; Parameter locations: + ; new_tcb_ptr = X register (word-width) + + ; As described above, first thread restores in this port do not + ; expect any initial register context to be pre-initialised in + ; the thread's stack area. The thread's initial stack need only + ; contain the thread's initial entry point, and we do not even + ; "restore" that within this function. We leave the thread's entry + ; point in the stack, and RET at the end of the function pops it + ; off and "returns" to the entry point as if we were called from + ; there. + ; + ; The one thing we do need to set in here, though, is the thread's + ; stack pointer. This is available from the passed thread TCB + ; structure. + + ; Get the new thread's stack pointer off the TCB (new_tcb_ptr). + ; new_tcb_ptr is stored in the parameter register X. The stack + ; pointer it conveniently located at the top of the TCB so no + ; indexing is required to pull it out. + ldw X,(X) + + ; Switch our current stack pointer to that of the new thread. + ldw SP,X + + ; (IAR) We only context switch ?b8 to ?b15 + POP ?b15 + POP ?b14 + POP ?b13 + POP ?b12 + POP ?b11 + POP ?b10 + POP ?b9 + POP ?b8 + + ; The "return address" left on the stack now will be the new + ; thread's entry point. RET will take us there as if we had + ; actually been there before calling this subroutine, whereas + ; the return address was actually set up by archThreadContextInit(). + ret + + + end diff --git a/ports/stm8_oss/atomport-asm-sdcc.s b/ports/stm8_oss/atomport-asm-sdcc.s new file mode 100644 index 00000000..816f7bbe --- /dev/null +++ b/ports/stm8_oss/atomport-asm-sdcc.s @@ -0,0 +1,48 @@ +; Copyright (c) 2016 Dr. Philipp Klaus Krause + +; Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: + +; The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +.area CODE + +; uint8_t get_cc(void); +_get_cc:: + push cc + pop a + ret + +; void set_cc(uint8_t); +_set_cc:: + ld a, (3, sp) + push a + pop cc + ret + +; void archContextSwitch (ATOM_TCB *old_tcb_ptr, ATOM_TCB *new_tcb_ptr) +_archContextSwitch:: + + ; save context + ldw x, (3, sp) + ldw y, sp + ldw (x), y + + ; restore context + ldw x, (5, sp) + ldw x, (x) + ldw sp, x + + ret + +; void archFirstThreadRestore (ATOM_TCB *new_tcb_ptr) +_archFirstThreadRestore:: + + ; restore context + ldw x, (3, sp) + ldw x, (x) + ldw sp, x + + ret + diff --git a/ports/stm8_oss/atomport-private.h b/ports/stm8_oss/atomport-private.h new file mode 100644 index 00000000..50663e51 --- /dev/null +++ b/ports/stm8_oss/atomport-private.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_PRIVATE_H +#define __ATOM_PORT_PRIVATE_H + + +// device selection and project settings +#include "config.h" + +// Cosmic compiler +#if defined(__CSMC__) + #define FAR @far + #define NEAR @near + #define TINY @tiny + +// IAR compiler +#elif defined(__ICCSTM8__) + #define FAR __far + #define NEAR __near + #define TINY __tiny + +// SDCC compiler +#elif defined(__SDCC) + #define FAR + #define NEAR + #define TINY + +// unsupported compiler -> stop +#else + #error: compiler not supported +#endif + + +/** + * Compiler-specific modifier to prevent some functions from saving + * and restoring registers on entry and exit, if the function is + * known to never complete (e.g. thread entry points). + * Reduces stack usage on supporting compilers. + */ +#ifdef __IAR_SYSTEMS_ICC__ + #define NO_REG_SAVE __task +#else + #define NO_REG_SAVE +#endif + + +/** + * Compiler-specific modifiers for interrupt handler functions. + * + * COSMIC: Uses @interrupt modifier for interrupt handlers. We + * also force all interrupts to save c_lreg, a separate memory + * area which Cosmic uses for longs and floats. This memory + * area must be saved by interrupt handlers for context + * switch purposes, and to avoid making it impossible to use + * longs in any OS kernel code accessed by interrupt handlers. + */ +// not required here. ISR_HANDLER() is defined in device header file + + +/* Function prototypes */ +void archInitSystemTickTimer (void); + +#if defined(__CSMC__) + #if defined(USE_TIM2) + @svlreg ISR_HANDLER(TIM2_SystemTickISR, TIM2_ISR_VECTOR); + #elif defined(USE_TIM4) + @svlreg ISR_HANDLER(TIM4_SystemTickISR, TIM4_ISR_VECTOR); + #else + #error select TIM2 or TIM4 in stm8-include/config.h + #endif +#else + #if defined(USE_TIM2) + ISR_HANDLER(TIM2_SystemTickISR, TIM2_ISR_VECTOR); + #elif defined(USE_TIM4) + ISR_HANDLER(TIM4_SystemTickISR, TIM4_ISR_VECTOR); + #else + #error select TIM2 or TIM4 in stm8-include/config.h + #endif +#endif + +#endif /* __ATOM_PORT_PRIVATE_H */ diff --git a/ports/stm8_oss/atomport-tests.h b/ports/stm8_oss/atomport-tests.h new file mode 100644 index 00000000..51dfbf7f --- /dev/null +++ b/ports/stm8_oss/atomport-tests.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_TESTS_H +#define __ATOM_PORT_TESTS_H + +/* Include Atomthreads kernel API */ +#include "atom.h" + +/* Prerequisite include for ATOMLOG() macro (via printf) */ +#include + +/* Logger macro for viewing test results */ +#define ATOMLOG printf + +/* + * String location macro: for platforms which need to place strings in + * alternative locations. Not used on this platform. + */ +#define _STR + +/* Default thread stack size (in bytes) */ +#define TEST_THREAD_STACK_SIZE 192 + +/* Uncomment to enable logging of stack usage to UART */ +#define TESTS_LOG_STACK_USAGE + +/** + * IAR EWSTM8: Ignore warnings on volatile ordering thrown up + * by ATOMLOG() statements in the test modules. + */ +#ifdef __IAR_SYSTEMS_ICC__ + #pragma diag_suppress=Pa082 +#endif + + +#endif /* __ATOM_PORT_TESTS_H */ + diff --git a/ports/stm8_oss/atomport.c b/ports/stm8_oss/atomport.c new file mode 100644 index 00000000..a2e177ff --- /dev/null +++ b/ports/stm8_oss/atomport.c @@ -0,0 +1,503 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "atom.h" +#include "atomport-private.h" +#include "config.h" + + +/** Forward declarations */ +static NO_REG_SAVE void thread_shell (void); + + +/** + * \b thread_shell + * + * Shell routine which is used to call all thread entry points. + * + * This routine is called whenever a new thread is starting, and is + * responsible for taking the entry point parameter off the TCB + * and passing this into the thread entry point, as well as enabling + * interrupts. + * + * This is an optional function for a port, because interrupts could + * be enabled by the first-thread and normal context restore routines, + * but that would require special handling in the normal context + * switch routine (archContextSwitch()) that is only needed the first + * time a thread is started. A much neater method is to direct all + * threads through this shell routine first, so that interrupts will + * always be enabled at thread startup, and no special first-time-run + * handling is required in the context restore routines (i.e. we + * don't affect normal context switch times just for the benefit of + * the first time a thread is restored by adding extra complication + * to the thread restore routines). + * + * Other ports are free to implement whatever scheme they wish. In + * particular if you save all necessary registers (including the + * interrupt enable register) on a context switch then you need not + * worry about any special requirements for starting threads for the + * first time because you can preinitialise the stack context with + * a suitable register value that will enable interrupts. + * + * If the compiler supports it, stack space can be saved by preventing + * the function from saving registers on entry. This is because we + * are called directly by the context-switch assembler, and know that + * threads cannot return from here. The NO_REG_SAVE macro is used to + * denote such functions in a compiler-agnostic way, though not all + * compilers support it. + * + * @return None + */ +static NO_REG_SAVE void thread_shell (void) +{ + ATOM_TCB *curr_tcb; + + /* Get the TCB of the thread being started */ + curr_tcb = atomCurrentContext(); + + /** + * Enable interrupts - these will not be enabled when a thread + * is first restored. + */ + ENABLE_INTERRUPTS(); + + /* Call the thread entry point */ + if (curr_tcb && curr_tcb->entry_point) + { + curr_tcb->entry_point(curr_tcb->entry_param); + } + + /* Not reached - threads should never return from the entry point */ + +} + + +/** + * \b archThreadContextInit + * + * Architecture-specific thread context initialisation routine. + * + * This function must set up a thread's context ready for restoring + * and running the thread via archFirstThreadRestore() or + * archContextSwitch(). + * + * (COSMIC & SDCC) On this port we take advantage of the fact + * that when the context switch routine is called these compilers will + * automatically stack all registers which should not be clobbered. + * This means that the context switch need only save and restore the + * stack pointer, which is stored in the thread's TCB. Because of + * this, it is not necessary to prefill a new thread's stack with any + * register values here. The only entry we need to make in the stack + * is the thread's entry point - this is not exactly restored when + * the thread is context switched in, but rather is popped off the + * stack by the context switch routine's RET call. That is used to + * direct the program counter to our thread's entry point - we are + * faking a return to a caller which never actually existed. + * + * (IAR) The IAR compiler works around the lack of CPU registers on + * STM8 by allocating some space in low SRAM which is used for + * "virtual" registers. The compiler uses these like normal CPU + * registers, and hence their values must be preserved when + * context-switching between threads. Some of these (?b8 to ?b15) + * are expected to be preserved by called functions, and hence we + * actually need to save/restore those registers (unlike the rest + * of the virtual registers and the standard CPU registers). We + * therefore must prefill the stack with values for ?b8 to ?b15 + * here. + * + * We could pre-initialise the stack so that the RET call goes + * directly to the thread entry point, with the thread entry + * parameter filled in. On this architecture, however, we use an + * outer thread shell routine which is used to call all threads. + * The thread entry point and parameter are stored in the thread's + * TCB which the thread shell uses to make the actual call to the + * entry point. We don't therefore need to store the actual thread + * entry and parameter within the stack. + * + * Note that interrupts must be enabled the first time a thread is + * run. On some architectures this might be done by setting an + * initial value for the interrupt-enable register within the stack + * area. In this port, however, we use the thread shell to enable + * interrupts at the start of any thread. + * + * @param[in] tcb_ptr Pointer to the TCB of the thread being created + * @param[in] stack_top Pointer to the top of the new thread's stack + * @param[in] entry_point Pointer to the thread entry point function + * @param[in] entry_param Parameter to be passed to the thread entry point + * + * @return None + */ +void archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(uint32_t), uint32_t entry_param) +{ + uint8_t *stack_ptr; + + /** Start at stack top */ + stack_ptr = (uint8_t *)stack_top; + + /** + * The thread restore routines will perform a RET which expects to + * find the address of the calling routine on the stack. In this case + * (the first time a thread is run) we "return" to the entry point for + * the thread. That is, we store the thread entry point in the + * place that RET will look for the return address: the stack. + * + * Note that we are using the thread_shell() routine to start all + * threads, so we actually store the address of thread_shell() + * here. Other ports may store the real thread entry point here + * and call it directly from the thread restore routines. + * + * Because we are filling the stack from top to bottom, this goes + * on the stack first (at the top). + */ + *stack_ptr-- = (uint8_t)((uint16_t)thread_shell & 0xFF); + *stack_ptr-- = (uint8_t)(((uint16_t)thread_shell >> 8) & 0xFF); + + /** + * Because we are using a threa./STM8S105K6d shell which is responsible for + * calling the real entry point, it also passes the parameters + * to entry point and we need not stack the entry parameter here. + * + * Other ports may wish to store entry_param in the appropriate + * parameter registers when creating a thread's context, + * particularly if that port saves those registers anyway. + */ + + /** + * (IAR) Set up initial values for ?b8 to ?b15. + */ +#if defined(__IAR_SYSTEMS_ICC__) + *stack_ptr-- = 0; // ?b8 + *stack_ptr-- = 0; // ?b9 + *stack_ptr-- = 0; // ?b10 + *stack_ptr-- = 0; // ?b11 + *stack_ptr-- = 0; // ?b12 + *stack_ptr-- = 0; // ?b13 + *stack_ptr-- = 0; // ?b14 + *stack_ptr-- = 0; // ?b15 +#endif + + /** + * (COSMIC & SDCC) We do not initialise any registers via the + * initial stack context at all. + */ + + /** + * All thread context has now been initialised. All that is left + * is to save the current stack pointer to the thread's TCB so + * that it knows where to start looking when the thread is started. + */ + tcb_ptr->sp_save_ptr = stack_ptr; + +} + + +/** + * \b archInitSystemTickTimer + * + * Initialise the system tick timer for a 1ms overflow. + Uses TIM2 (16-bit) or TIM4 (8-bit), selection is via stm8-include/config.h. + TIM4 is "cheap" and available in most STM8, but requires tweaking and increases ISR load. + * + * @return None + */ +void archInitSystemTickTimer ( void ) +{ + #if defined(USE_TIM2) + + uint16_t ARR; + + // output during compile + #warning using TIM2 + + // for low-power device activate TIM2 clock + #if defined(FAMILY_STM8L) + sfr_CLK.PCKENR1.PCKEN10 = 1; + #endif + + // stop the timer + sfr_TIM2.CR1.CEN = 0; + + // auto-reload value buffered + sfr_TIM2.CR1.ARPE = 1; + + // fMaster = 16MHz + #if (FSYS_FREQ == 16000000L) + + // set clock to 16Mhz/2^6 = 250kHz -> 4us tick + sfr_TIM2.PSCR.PSC = 6; + + // set autoreload value to specified period (1ms = 250*4us) + ARR = (uint16_t) PERIOD_THREADS * (uint16_t) 250; + sfr_TIM2.ARRH.byte = (uint8_t) (ARR >> 8); + sfr_TIM2.ARRL.byte = (uint8_t) (ARR); + + // fMaster = 20MHz + #elif (FSYS_FREQ == 20000000L) + + // set clock to 20Mhz/2^5 = 625kHz -> 1.6us tick + sfr_TIM2.PSCR.PSC = 5; + + // set autoreload value to specified period (1ms = 625*1.6us) + ARR = (uint16_t) PERIOD_THREADS * (uint16_t) 625; + sfr_TIM2.ARRH.byte = (uint8_t) (ARR >> 8); + sfr_TIM2.ARRL.byte = (uint8_t) (ARR); + + // fMaster = 24MHz + #elif (FSYS_FREQ == 24000000L) + + // set clock to 24Mhz/2^5 = 750kHz -> 1.333us tick + sfr_TIM2.PSCR.PSC = 5; + + // set autoreload value to specified period (1ms = 750*1.333us) + ARR = (uint16_t) PERIOD_THREADS * (uint16_t) 750; + sfr_TIM2.ARRH.byte = (uint8_t) (ARR >> 8); + sfr_TIM2.ARRL.byte = (uint8_t) (ARR); + + // FSYS_FREQ not yet supported -> add manually + #else + #error FSYS_FREQ not yet supported -> add manually + #endif + + // clear counter + sfr_TIM2.CNTRH.byte = 0x00; + sfr_TIM2.CNTRL.byte = 0x00; + + // clear pending events + sfr_TIM2.EGR.byte = 0x00; + + // enable timer 2 update interrupt + sfr_TIM2.IER.UIE = 1; + + // start the timer + sfr_TIM2.CR1.CEN = 1; + + + #elif defined(USE_TIM4) + + // output during compile + #warning using TIM4 + + // for low-power device activate TIM4 clock + #if defined(FAMILY_STM8L) + sfr_CLK.PCKENR1.PCKEN12 = 1; + #endif + + // stop the timer + sfr_TIM4.CR1.CEN = 0; + + // clear counter + sfr_TIM4.CNTR.byte = 0x00; + + // auto-reload value buffered + sfr_TIM4.CR1.ARPE = 1; + + // clear pending events + sfr_TIM4.EGR.byte = 0x00; + + // fMaster = 16MHz + #if (FSYS_FREQ == 16000000L) + + // set clock to 16Mhz/2^6 = 250kHz -> 4us period + sfr_TIM4.PSCR.PSC = 6; + + // set autoreload value for 1ms (=250*4us) + sfr_TIM4.ARR.byte = 250; + + // fMaster = 20MHz + #elif (FSYS_FREQ == 20000000L) + + // set clock to 20Mhz/2^7 = 156,25kHz -> 6.4us period + sfr_TIM4.PSCR.PSC = 7; + + // set autoreload value for 1ms (=156.25*6.4us) + // account for fractional ARR in ISR + sfr_TIM4.ARR.byte = 156; + + // fMaster = 24MHz + #elif (FSYS_FREQ == 24000000L) + + // set clock to 24Mhz/2^7 = 187.5kHz -> 5.33us period + sfr_TIM4.PSCR.PSC = 7; + + // set autoreload value for 1ms (=187.5*5.33us) + // account for fractional ARR in ISR + sfr_TIM4.ARR.byte = 187; + + // FSYS_FREQ not yet supported -> add manually + #else + #error FSYS_FREQ not yet supported -> add manually + #endif + + // enable timer 4 interrupt + sfr_TIM4.IER.UIE = 1; + + // start the timer + sfr_TIM4.CR1.CEN = 1; + + #else + #error select TIM2 or TIM4 in stm8-include/config.h + #endif + +} // archInitSystemTickTimer + + +/** + * + * System tick ISR. + * + * This is responsible for regularly calling the OS system tick handler. + * The system tick handler checks if any timer callbacks are necessary, + * and runs the scheduler. + * + * The CPU automatically saves all registers before calling out to an + * interrupt handler like this. + * + * The system may decide to schedule in a new thread during the call to + * atomTimerTick(), in which case the program counter will be redirected + * to the new thread's running location during atomIntExit(). This ISR + * function will not actually complete until the thread we interrupted is + * scheduled back in, at which point the end of this function will be + * reached (after atomIntExit()) and the IRET call by the compiler will + * return us to the interrupted thread as if we hadn't run any other + * thread in the meantime. In other words the interrupted thread can be + * scheduled out by atomIntExit() and several threads could run before we + * actually reach the end of this function. When this function does + * finally complete, the return address (the PC of the thread which was + * interrupted) will be on the interrupted thread's stack because it was + * saved on there by the CPU when the interrupt triggered. + * + * As with all interrupts, the ISR should call atomIntEnter() and + * atomIntExit() on entry and exit. This serves two purposes: + * + * a) To notify the OS that it is running in interrupt context + * b) To defer the scheduler until after the ISR is completed + * + * We defer all scheduling decisions until after the ISR has completed + * in case the interrupt handler makes more than one thread ready. + * + * @return None + */ + +// 16-bit timer TIM2 ISR requires no tweaking for >1ms systic +#if defined(USE_TIM2) + #if defined(__CSMC__) + @svlreg ISR_HANDLER(TIM2_SystemTickISR, TIM2_ISR_VECTOR) + #else + ISR_HANDLER(TIM2_SystemTickISR, TIM2_ISR_VECTOR) + #endif +{ + // clear timer 2 interrupt flag + TIM2_ISR_UIF = 0; + + // debug + //LED_PORT.ODR.byte ^= LED_PIN; + + /* Call the interrupt entry routine */ + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); + +} // TIM2_SystemTickISR + + +// 8-bit timer TIM4 has limited period of ~1ms and requires tweaking +#elif defined(USE_TIM4) + #if defined(__CSMC__) + @svlreg ISR_HANDLER(TIM4_SystemTickISR, TIM4_ISR_VECTOR) + #else + ISR_HANDLER(TIM4_SystemTickISR, TIM4_ISR_VECTOR) + #endif +{ + static uint8_t count_period = 0; // for calling atomthreads scheduler every N ms +#if (FSYS_FREQ != 16000000L) + static uint8_t count_fractional = 0; // only required for fractional reload value +#endif + + // clear timer 4 interrupt flag + TIM4_ISR_UIF = 0; + + // debug + //LED_PORT.ODR.byte ^= LED_PIN; + +// 16MHz -> reload=250 -> no correction required +#if (FSYS_FREQ == 16000000L) + // dummy + +// 20MHz -> reload=156.25 -> every 4th cycle +#elif (FSYS_FREQ == 20000000L) + if ((++count_fractional) == 4) + { + count_fractional = 0; + sfr_TIM4.ARR.byte = 157; + } + else + sfr_TIM4.ARR.byte = 156; + +// 20MHz -> reload=187.5 -> every 2nd cycle +#elif (FSYS_FREQ == 24000000L) + if ((++count_fractional) == 2) + { + count_fractional = 0; + sfr_TIM4.ARR.byte = 188; + } + else + sfr_TIM4.ARR.byte = 187; + +// FSYS_FREQ not yet supported -> add manually +#else + #error FSYS_FREQ not yet supported -> add manually +#endif + + + // atomthread period has passed -> handle threads + if ((++count_period) == PERIOD_THREADS) + { + // reset counter + count_period = 0; + + /* Call the interrupt entry routine */ + atomIntEnter(); + + /* Call the OS system tick handler */ + atomTimerTick(); + + /* Call the interrupt exit routine */ + atomIntExit(TRUE); + } + +} // TIM4_SystemTickISR + +#else + #error select TIM2 or TIM4 in stm8-include/config.h +#endif diff --git a/ports/stm8_oss/atomport.h b/ports/stm8_oss/atomport.h new file mode 100644 index 00000000..8a680be3 --- /dev/null +++ b/ports/stm8_oss/atomport.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * Copyright (c) 2016, Dr. Philipp Klaus Krause. + * Copyright (c) 2020, Georg Icking-Konert. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_H +#define __ATOM_PORT_H + + +#include "config.h" +#if defined(__IAR_SYSTEMS_ICC__) + #include "intrinsics.h" +#endif + +/* Definition of NULL is available from stddef.h on this platform */ +#include + +/* Required number of system ticks per second (normally 100 for 10ms tick) */ +#define SYSTEM_TICKS_PER_SEC 100 + +/** + * Architecture-specific types. + */ +#if defined(__CSMC__) /* Cosmic does not have the C99 stdint.h header*/ + #define int8_t signed char + #define int16_t signed short + #define int32_t signed long + #define uint8_t unsigned char + #define uint16_t unsigned short + #define uint32_t unsigned long +#else + #include +#endif +#define POINTER void * + +/* Size of each stack entry / stack alignment size (8 bits on STM8) */ +#define STACK_ALIGN_SIZE sizeof(uint8_t) + +/** + * Critical region protection: this should disable interrupts + * to protect OS data structures during modification. It must + * allow nested calls, which means that interrupts should only + * be re-enabled when the outer CRITICAL_END() is reached. + */ + +/* COSMIC: Use inline assembler */ +#if defined(__CSMC__) + #define CRITICAL_STORE uint8_t ccr + #define CRITICAL_START() _asm ("push CC\npop a\nld (X),A\nsim", &ccr) + #define CRITICAL_END() _asm ("ld A,(X)\npush A\npop CC", &ccr) + +/* IAR: Use intrinsics */ +#elif defined(__IAR_SYSTEMS_ICC__) + #define CRITICAL_STORE __istate_t _istate + #define CRITICAL_START() _istate = __get_interrupt_state(); __disable_interrupt() + #define CRITICAL_END() __set_interrupt_state(_istate) + +/* SDCC: Use custom function */ +#elif defined(__SDCC_stm8) + uint8_t get_cc(void); + void set_cc(uint8_t); + #define CRITICAL_STORE uint8_t ccr + #define CRITICAL_START() ccr = get_cc(); __asm__("sim") + #define CRITICAL_END() set_cc(ccr) +#endif + +/* Uncomment to enable stack-checking */ +/* #define ATOM_STACK_CHECKING */ + + +#endif /* __ATOM_PORT_H */ diff --git a/ports/stm8_oss/atomthreads-sample-cosmic.dep b/ports/stm8_oss/atomthreads-sample-cosmic.dep new file mode 100644 index 00000000..f972d80b --- /dev/null +++ b/ports/stm8_oss/atomthreads-sample-cosmic.dep @@ -0,0 +1,65 @@ +; STMicroelectronics dependencies file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Root.Kernel...\..\kernel\atomkernel.c.Config.0] +ExternDep= ..\..\kernel\atomkernel.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" + +[Root.Kernel...\..\kernel\atomkernel.c.Config.1] +ExternDep= ..\..\kernel\atomkernel.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" + +[Root.Kernel...\..\kernel\atommutex.c.Config.0] +ExternDep= ..\..\kernel\atommutex.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../kernel\atommutex.h + +[Root.Kernel...\..\kernel\atommutex.c.Config.1] +ExternDep= ..\..\kernel\atommutex.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../kernel\atommutex.h + +[Root.Kernel...\..\kernel\atomqueue.c.Config.0] +ExternDep= ..\..\kernel\atomqueue.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\string.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../kernel\atomqueue.h + +[Root.Kernel...\..\kernel\atomqueue.c.Config.1] +ExternDep= ..\..\kernel\atomqueue.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\string.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../kernel\atomqueue.h + +[Root.Kernel...\..\kernel\atomsem.c.Config.0] +ExternDep= ..\..\kernel\atomsem.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../kernel\atomsem.h + +[Root.Kernel...\..\kernel\atomsem.c.Config.1] +ExternDep= ..\..\kernel\atomsem.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../kernel\atomsem.h + +[Root.Kernel...\..\kernel\atomtimer.c.Config.0] +ExternDep= ..\..\kernel\atomtimer.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" + +[Root.Kernel...\..\kernel\atomtimer.c.Config.1] +ExternDep= ..\..\kernel\atomtimer.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" + +[Root.Port...\..\tests\sem4.c.Config.0] +ExternDep= ..\..\tests\sem4.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../tests\atomtests.h atomport-tests.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdio.h" ../../kernel\atomsem.h + +[Root.Port...\..\tests\sem4.c.Config.1] +ExternDep= ..\..\tests\sem4.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../tests\atomtests.h atomport-tests.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdio.h" ../../kernel\atomsem.h + +[Root.Port.uart.c.Config.0] +ExternDep= uart.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdio.h" stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../kernel\atommutex.h uart.h + +[Root.Port.uart.c.Config.1] +ExternDep= uart.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdio.h" stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" ../../kernel\atommutex.h uart.h + +[Root.Port.tests-main.c.Config.0] +ExternDep= tests-main.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdio.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" atomport-private.h atomport-tests.h ../../tests\atomtests.h uart.h + +[Root.Port.tests-main.c.Config.1] +ExternDep= tests-main.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdio.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" atomport-private.h atomport-tests.h ../../tests\atomtests.h uart.h + +[Root.Port.atomport.c.Config.0] +ExternDep= atomport.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" atomport-private.h + +[Root.Port.atomport.c.Config.1] +ExternDep= atomport.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" ../../kernel\atom.h ../../kernel\atomtimer.h atomport.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stddef.h" atomport-private.h + +[Root.Port.stm8_interrupt_vector.c.Config.0] +ExternDep= stm8_interrupt_vector.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" atomport-private.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" + +[Root.Port.stm8_interrupt_vector.c.Config.1] +ExternDep= stm8_interrupt_vector.c "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\modsl0.h" atomport-private.h stm8-include\config.h stm8-include\STM8S105K6.h "C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\HSTM8\stdint.h" \ No newline at end of file diff --git a/ports/stm8_oss/atomthreads-sample-cosmic.stp b/ports/stm8_oss/atomthreads-sample-cosmic.stp new file mode 100644 index 00000000..13f036ef --- /dev/null +++ b/ports/stm8_oss/atomthreads-sample-cosmic.stp @@ -0,0 +1,552 @@ +; STMicroelectronics Project file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Project] +Name=atomthreads-cosmic +Toolset=STM8 Cosmic + +[Config] +0=Config.0 +1=Config.1 + +[Config.0] +ConfigName=Debug +Target=$(ProjectSFile).elf +OutputFolder=Debug +Debug=$(TargetFName) + +[Config.1] +ConfigName=Release +Target=$(ProjectSFile).elf +OutputFolder=Release +Debug=$(TargetFName) + +[Root] +ElemType=Project +PathName=atomthreads-cosmic +Child=Root.Kernel +Config.0=Root.Config.0 +Config.1=Root.Config.1 + +[Root.Config.0] +Settings.0.0=Root.Config.0.Settings.0 +Settings.0.1=Root.Config.0.Settings.1 +Settings.0.2=Root.Config.0.Settings.2 +Settings.0.3=Root.Config.0.Settings.3 +Settings.0.4=Root.Config.0.Settings.4 +Settings.0.5=Root.Config.0.Settings.5 +Settings.0.6=Root.Config.0.Settings.6 +Settings.0.7=Root.Config.0.Settings.7 +Settings.0.8=Root.Config.0.Settings.8 + +[Root.Config.1] +Settings.1.0=Root.Config.1.Settings.0 +Settings.1.1=Root.Config.1.Settings.1 +Settings.1.2=Root.Config.1.Settings.2 +Settings.1.3=Root.Config.1.Settings.3 +Settings.1.4=Root.Config.1.Settings.4 +Settings.1.5=Root.Config.1.Settings.5 +Settings.1.6=Root.Config.1.Settings.6 +Settings.1.7=Root.Config.1.Settings.7 +Settings.1.8=Root.Config.1.Settings.8 + +[Root.Config.0.Settings.0] +String.6.0=2010,2,9,1,12,48 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=STM8 Cosmic +String.102.0=C:\Program Files\COSMIC\FSE_Compilers +String.103.0= +String.104.0=Hstm8 +String.105.0=Lib +String.106.0=Debug +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.0.Settings.1] +String.6.0=2010,2,9,1,12,48 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\..\kernel;stm8s-periphs;stm8-include;..\..\tests; + +[Root.Config.0.Settings.2] +String.2.0= +String.6.0=2010,2,9,1,12,48 +String.100.0=STM8S105C6 + +[Root.Config.0.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -istm8-include +modsl0 -customDebCompat -customOpt -no +split -customC-pp -customLst -l -dSTM8S105 -dATOM_STACK_CHECKING -istm8s-periphs -i../../kernel -i../../tests $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,27,22,48,49 + +[Root.Config.0.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l -u $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,2,10,1,16,38 + +[Root.Config.0.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,2,9,1,12,48 +String.8.0= + +[Root.Config.0.Settings.6] +String.2.0=Running Linker +String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeInteger -fakeOutFile$(ProjectSFile).elf -fakeRunConv -fakeStartupcrtsi0.sm8 -fakeAutoGen -fakeVectFilestm8_interrupt_vector.c -fakeVectAddr0x8000 -customMapFile -customMapFile-m$(OutputPath)$(TargetSName).map -customMapAddress -customCfgFile $(OutputPath)$(TargetSName).lkf +String.3.1=cvdwarf $(OutputPath)$(TargetSName).sm8 +String.4.0=$(OutputPath)$(TargetFName) +String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map +String.6.0=2010,3,9,0,24,9 +String.100.0= +String.101.0=crtsi.st7 +String.102.0=+seg .const -b 0x8080 -m 0x7f80 -n .const -it +String.102.1=+seg .text -a .const -n .text +String.102.2=+seg .eeprom -b 0x4000 -m 0x400 -n .eeprom +String.102.3=+seg .bsct -b 0x2 -m 0xfe -n .bsct +String.102.4=+seg .ubsct -a .bsct -n .ubsct +String.102.5=+seg .bit -a .ubsct -n .bit -id +String.102.6=+seg .share -a .bit -n .share -is +String.102.7=+seg .data -b 0x100 -m 0x6c0 -n .data +String.102.8=+seg .bss -a .data -n .bss +String.103.0=Code,Constants[0x8080-0xffff]=.const,.text +String.103.1=Eeprom[0x4000-0x43ff]=.eeprom +String.103.2=Zero Page[0x2-0xff]=.bsct,.ubsct,.bit,.share +String.103.3=Ram[0x100-0x7bf]=.data,.bss +String.104.0=0x7ff +String.105.0=libisl0.sm8;libm0.sm8 +Int.0=0 +Int.1=0 + +[Root.Config.0.Settings.7] +String.2.0=Running Post-Build step +String.3.0=chex -o $(OutputPath)$(TargetSName).s19 $(OutputPath)$(TargetSName).sm8 +String.6.0=2010,2,9,1,12,48 + +[Root.Config.0.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,2,9,1,12,48 + +[Root.Config.1.Settings.0] +String.6.0=2010,2,9,1,12,50 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=STM8 Cosmic +String.102.0=C:\Program Files\COSMIC\FSE_Compilers +String.103.0= +String.104.0=Hstm8 +String.105.0=Lib +String.106.0=Release +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.1.Settings.1] +String.6.0=2010,2,9,1,12,48 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\..\kernel;stm8s-periphs;stm8-include;..\..\tests; + +[Root.Config.1.Settings.2] +String.2.0= +String.6.0=2010,2,9,1,12,48 +String.100.0=STM8S105C6 + +[Root.Config.1.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -istm8-include +modsl0 -customOpt +split -customC-pp -dSTM8S105 -dATOM_STACK_CHECKING -istm8s-periphs -i../../kernel -i../../tests $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,27,22,48,49 + +[Root.Config.1.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,2,9,1,12,48 + +[Root.Config.1.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,2,9,1,12,48 +String.8.0= + +[Root.Config.1.Settings.6] +String.2.0=Running Linker +String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeInteger -fakeOutFile$(ProjectSFile).elf -fakeRunConv -fakeStartupcrtsi0.sm8 -fakeAutoGen -fakeVectFilestm8_interrupt_vector.c -fakeVectAddr0x8000 -customMapAddress -customCfgFile $(OutputPath)$(TargetSName).lkf +String.3.1=cvdwarf $(OutputPath)$(TargetSName).sm8 +String.4.0=$(OutputPath)$(TargetFName) +String.5.0=$(OutputPath)$(ProjectSFile).elf +String.6.0=2010,5,27,22,49,45 +String.100.0= +String.101.0=crtsi.st7 +String.102.0=+seg .const -b 0x8080 -m 0x7f80 -n .const -it +String.102.1=+seg .text -a .const -n .text +String.102.2=+seg .eeprom -b 0x4000 -m 0x400 -n .eeprom +String.102.3=+seg .bsct -b 0x2 -m 0xfe -n .bsct +String.102.4=+seg .ubsct -a .bsct -n .ubsct +String.102.5=+seg .bit -a .ubsct -n .bit -id +String.102.6=+seg .share -a .bit -n .share -is +String.102.7=+seg .data -b 0x100 -m 0x6c0 -n .data +String.102.8=+seg .bss -a .data -n .bss +String.103.0=Code,Constants[0x8080-0xffff]=.const,.text +String.103.1=Eeprom[0x4000-0x43ff]=.eeprom +String.103.2=Zero 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$PROJ_DIR$\..\..\kernel\atomtimer.c + + + $PROJ_DIR$\..\..\kernel\atomtimer.h + + + Debug + + + Release + + + + stm8 + + $PROJ_DIR$\atomport-asm-iar.s + + + $PROJ_DIR$\atomport-private.h + + + $PROJ_DIR$\atomport-tests.h + + + $PROJ_DIR$\atomport.c + + + $PROJ_DIR$\atomport.h + + + $PROJ_DIR$\stm8s_conf.h + + + $PROJ_DIR$\tests-main.c + + + $PROJ_DIR$\uart.c + + + $PROJ_DIR$\uart.h + + + Debug + + + Release + + + + stm8-include + + $PROJ_DIR$\stm8-include\config.h + + + $PROJ_DIR$\stm8-include\STM8S105C6.h + + + $PROJ_DIR$\stm8-include\STM8S105K6.h + + + $PROJ_DIR$\stm8-include\STM8S207MB.h + + + Debug + + + Release + + + + tests + + $PROJ_DIR$\..\..\tests\atomtests.h + + + $PROJ_DIR$\..\..\tests\sem1.c + + + Debug + + + Release + + + diff --git a/ports/stm8_oss/atomthreads-sample-iar.eww b/ports/stm8_oss/atomthreads-sample-iar.eww new file mode 100644 index 00000000..892262b2 --- /dev/null +++ b/ports/stm8_oss/atomthreads-sample-iar.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\atomthreads-sample-iar.ewp + + + diff --git a/ports/stm8_oss/atomthreads-sample-raisonance.stp b/ports/stm8_oss/atomthreads-sample-raisonance.stp new file mode 100644 index 00000000..4aeec96c --- /dev/null +++ b/ports/stm8_oss/atomthreads-sample-raisonance.stp @@ -0,0 +1,545 @@ +; STMicroelectronics Project file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Project] +Name=atomthreads-raisonance +Toolset=Raisonance + +[Config] +0=Config.0 +1=Config.1 + +[Config.0] +ConfigName=Debug +Target=$(ProjectSFile).elf +OutputFolder=Debug +Debug=$(TargetFName) + +[Config.1] +ConfigName=Release +Target=$(ProjectSFile).elf +OutputFolder=Release +Debug=$(TargetFName) + +[Root] +ElemType=Project +PathName=atomthreads-raisonance +Child=Root.Kernel +Config.0=Root.Config.0 +Config.1=Root.Config.1 + +[Root.Config.0] +Settings.0.0=Root.Config.0.Settings.0 +Settings.0.1=Root.Config.0.Settings.1 +Settings.0.2=Root.Config.0.Settings.2 +Settings.0.3=Root.Config.0.Settings.3 +Settings.0.4=Root.Config.0.Settings.4 +Settings.0.5=Root.Config.0.Settings.5 +Settings.0.6=Root.Config.0.Settings.6 +Settings.0.7=Root.Config.0.Settings.7 +Settings.0.8=Root.Config.0.Settings.8 + +[Root.Config.1] +Settings.1.0=Root.Config.1.Settings.0 +Settings.1.1=Root.Config.1.Settings.1 +Settings.1.2=Root.Config.1.Settings.2 +Settings.1.3=Root.Config.1.Settings.3 +Settings.1.4=Root.Config.1.Settings.4 +Settings.1.5=Root.Config.1.Settings.5 +Settings.1.6=Root.Config.1.Settings.6 +Settings.1.7=Root.Config.1.Settings.7 +Settings.1.8=Root.Config.1.Settings.8 + +[Root.Config.0.Settings.0] +String.6.0=2010,2,10,16,13,19 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=Raisonance +String.102.0=C:\Program Files\Raisonance\Ride +String.103.0=bin +String.104.0=INC\ST7;INC +String.105.0=LIB\ST7 +String.106.0=Debug +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.0.Settings.1] +String.6.0=2010,2,10,16,13,19 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\..\kernel;stm8s-periphs;..\..\tests; + +[Root.Config.0.Settings.2] +String.2.0= +String.6.0=2010,2,10,16,13,19 +String.100.0=STM8S105C6 + +[Root.Config.0.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customSizeOpt -CustomOptimOT(7,SIZE) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(stm8s-periphs) PIN(../../kernel) PIN(../../tests) DF(STM8S105) DF(ATOM_STACK_CHECKING) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,2,11,13,56,23 + +[Root.Config.0.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT DEBUG 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+String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,6,22,22,17 + +[Root.Kernel.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,6,21,37,36 + +[Root.Kernel.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,6,21,35,47 + +[Root.Kernel...\..\kernel\atom.h] +ElemType=File +PathName=..\..\kernel\atom.h +Next=Root.Kernel...\..\kernel\atomkernel.c + +[Root.Kernel...\..\kernel\atomkernel.c] +ElemType=File +PathName=..\..\kernel\atomkernel.c +Next=Root.Kernel...\..\kernel\atommutex.c + +[Root.Kernel...\..\kernel\atommutex.c] +ElemType=File +PathName=..\..\kernel\atommutex.c +Next=Root.Kernel...\..\kernel\atommutex.h + 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PIN(../../kernel) PIN(../../tests) DF(STM8S105) DF(ATOM_STACK_CHECKING) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,6,22,22,17 + +[Root.Peripherals.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT DEBUG +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,6,21,35,47 + +[Root.Peripherals.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,6,21,35,47 + +[Root.Peripherals.Config.1.Settings.0] +String.6.0=2010,6,6,21,35,47 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Peripherals.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSizeOpt -CustomOptimOT(7,SIZE) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB -CustomAutoReloc @$(OutputPath)$(TargetSName).areloc PIN(stm8s-periphs) PIN(../../kernel) PIN(../../tests) DF(STM8S105) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,6,22,22,17 + +[Root.Peripherals.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,6,21,37,36 + +[Root.Peripherals.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,6,21,35,47 + +[Root.Peripherals.stm8s-periphs\stm8s_clk.c] +ElemType=File +PathName=stm8s-periphs\stm8s_clk.c +Next=Root.Peripherals.stm8s-periphs\stm8s_uart2.h + +[Root.Peripherals.stm8s-periphs\stm8s_uart2.h] +ElemType=File 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+[Root.Peripherals.stm8s-periphs\stm8s_clk.h] +ElemType=File +PathName=stm8s-periphs\stm8s_clk.h +Next=Root.Peripherals.stm8s-periphs\stm8s.h + +[Root.Peripherals.stm8s-periphs\stm8s.h] +ElemType=File +PathName=stm8s-periphs\stm8s.h +Next=Root.Peripherals.stm8s-periphs\stm8s_type.h + +[Root.Peripherals.stm8s-periphs\stm8s_type.h] +ElemType=File +PathName=stm8s-periphs\stm8s_type.h + +[Root.Port] +ElemType=Folder +PathName=Port +Child=Root.Port.atomport-asm-raisonance.asm +Config.0=Root.Port.Config.0 +Config.1=Root.Port.Config.1 + +[Root.Port.Config.0] +Settings.0.0=Root.Port.Config.0.Settings.0 +Settings.0.1=Root.Port.Config.0.Settings.1 +Settings.0.2=Root.Port.Config.0.Settings.2 +Settings.0.3=Root.Port.Config.0.Settings.3 + +[Root.Port.Config.1] +Settings.1.0=Root.Port.Config.1.Settings.0 +Settings.1.1=Root.Port.Config.1.Settings.1 +Settings.1.2=Root.Port.Config.1.Settings.2 +Settings.1.3=Root.Port.Config.1.Settings.3 + +[Root.Port.Config.0.Settings.0] +String.6.0=2010,6,6,21,35,47 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Port.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(stm8s-periphs) PIN(../../kernel) PIN(../../tests) DF(STM8S105) DF(ATOM_STACK_CHECKING) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,6,22,22,17 + +[Root.Port.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT DEBUG +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,6,21,35,47 + +[Root.Port.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,6,21,35,47 + +[Root.Port.Config.1.Settings.0] +String.6.0=2010,6,6,21,35,47 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Port.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSizeOpt -CustomOptimOT(7,SIZE) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB -CustomAutoReloc @$(OutputPath)$(TargetSName).areloc PIN(stm8s-periphs) PIN(../../kernel) PIN(../../tests) DF(STM8S105) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,6,22,22,17 + +[Root.Port.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,6,21,37,36 + +[Root.Port.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,6,21,35,47 + +[Root.Port.atomport-asm-raisonance.asm] +ElemType=File +PathName=atomport-asm-raisonance.asm +Next=Root.Port...\..\tests\sem1.c + +[Root.Port...\..\tests\sem1.c] +ElemType=File +PathName=..\..\tests\sem1.c +Next=Root.Port.uart.h + +[Root.Port.uart.h] +ElemType=File +PathName=uart.h +Next=Root.Port.uart.c + +[Root.Port.uart.c] +ElemType=File +PathName=uart.c +Next=Root.Port.atomport-tests.h + +[Root.Port.atomport-tests.h] +ElemType=File +PathName=atomport-tests.h +Next=Root.Port.tests-main.c + +[Root.Port.tests-main.c] +ElemType=File +PathName=tests-main.c +Next=Root.Port.atomport-private.h + +[Root.Port.atomport-private.h] +ElemType=File +PathName=atomport-private.h +Next=Root.Port.atomport.h + +[Root.Port.atomport.h] +ElemType=File +PathName=atomport.h +Next=Root.Port.stm8s_conf.h + +[Root.Port.stm8s_conf.h] +ElemType=File +PathName=stm8s_conf.h +Next=Root.Port.atomport.c + +[Root.Port.atomport.c] +ElemType=File +PathName=atomport.c \ No newline at end of file diff --git a/ports/stm8_oss/atomthreads-sample-stvd.stw b/ports/stm8_oss/atomthreads-sample-stvd.stw new file mode 100644 index 00000000..62c38e0a --- /dev/null +++ b/ports/stm8_oss/atomthreads-sample-stvd.stw @@ -0,0 +1,12 @@ +; STMicroelectronics Workspace file + +[Version] +Keyword=ST7Workspace-V0.7 + +[Project0] +Filename=atomthreads-sample-cosmic.stp +Dependencies= +[Options] +ActiveProject=atomthreads-cosmic +ActiveConfig=Release +AddSortedElements=0 diff --git a/ports/stm8_oss/atomthreads-sample-stvd.wdb b/ports/stm8_oss/atomthreads-sample-stvd.wdb new file mode 100644 index 00000000..2c490a1c --- /dev/null +++ b/ports/stm8_oss/atomthreads-sample-stvd.wdb @@ -0,0 +1,1313 @@ + +[WorkState_v1_2] +ptn_Child1=DockState +ptn_Child2=ToolBarMgr + +[WorkState_v1_2.DockState] +Bars=35 +ScreenCX=1920 +ScreenCY=976 +ptn_Child1=Bar-0 +ptn_Child2=Bar-1 +ptn_Child3=Bar-2 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+DockingStyle=61440 +TypeID=0 +ClassName=CNewDumpControlBar +WindowName=Memory #4 +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-26] +BarID=5708 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=8 +MRUDockTopPos=26 +MRUDockRightPos=8 +MRUDockBottomPos=26 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=8068 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=500000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=303 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CSoftBkControlBar +WindowName=Instruction Breakpoints +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-27] +BarID=5710 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=8 +MRUDockTopPos=26 +MRUDockRightPos=8 +MRUDockBottomPos=26 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=36740 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=666665 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CWatchControlBar +WindowName=Watch +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-28] +BarID=5706 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=8 +MRUDockTopPos=26 +MRUDockRightPos=8 +MRUDockBottomPos=26 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=36612 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=750000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CStackControlBar +WindowName=Call Stack +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-29] +BarID=5707 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=8 +MRUDockTopPos=26 +MRUDockRightPos=8 +MRUDockBottomPos=26 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=36612 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=800000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CLocalsControlBar +WindowName=Local Variables +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-30] +BarID=8002 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=8 +MRUDockTopPos=26 +MRUDockRightPos=7864343 +MRUDockBottomPos=465186 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=978 +Style=36740 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=666665 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CAddedControlBar +WindowName=Core Registers +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-31] +BarID=8003 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=8 +MRUDockTopPos=26 +MRUDockRightPos=8 +MRUDockBottomPos=26 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=36740 +ExStyle=69393 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=750000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=CAddedControlBar +WindowName=Peripheral Registers +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-32] +BarID=59423 +Horz=True +Floating=True +XPos=227 +YPos=72 +Bars=3 +Bar#0=0 +Bar#1=59403 +Bar#2=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-33] +BarID=59423 +Horz=True +Floating=True +XPos=716 +YPos=193 +Bars=3 +Bar#0=0 +Bar#1=59402 +Bar#2=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-34] +BarID=59423 +Horz=True +Floating=True +XPos=1101 +YPos=72 +Bars=3 +Bar#0=0 +Bar#1=59397 +Bar#2=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.ToolBarMgr] +ToolTips=True +CoolLook=True +LargeButtons=False diff --git a/ports/stm8_oss/atomthreads-sample-stvd.wed b/ports/stm8_oss/atomthreads-sample-stvd.wed new file mode 100644 index 00000000..3c783ec4 --- /dev/null +++ b/ports/stm8_oss/atomthreads-sample-stvd.wed @@ -0,0 +1,1274 @@ +[WorkState_v1-Edit.Breakpoints] +Break0=TypeFile, ..\..\tests\sem4.c, 151, 0, 0, 1, + +[WorkState_v1_2] +ptn_Child1=DockState +ptn_Child2=ToolBarMgr +ptn_Child3=Frames + +[WorkState_v1_2.DockState] +Bars=33 +ScreenCX=1920 +ScreenCY=976 +ptn_Child1=Bar-0 +ptn_Child2=Bar-1 +ptn_Child3=Bar-2 +ptn_Child4=Bar-3 +ptn_Child5=Bar-4 +ptn_Child6=Bar-5 +ptn_Child7=Bar-6 +ptn_Child8=Bar-7 +ptn_Child9=Bar-8 +ptn_Child10=Bar-9 +ptn_Child11=Bar-10 +ptn_Child12=Bar-11 +ptn_Child13=Bar-12 +ptn_Child14=Bar-13 +ptn_Child15=Bar-14 +ptn_Child16=Bar-15 +ptn_Child17=Bar-16 +ptn_Child18=Bar-17 +ptn_Child19=Bar-18 +ptn_Child20=Bar-19 +ptn_Child21=Bar-20 +ptn_Child22=Bar-21 +ptn_Child23=Bar-22 +ptn_Child24=Bar-23 +ptn_Child25=Bar-24 +ptn_Child26=Bar-25 +ptn_Child27=Bar-26 +ptn_Child28=Bar-27 +ptn_Child29=Bar-28 +ptn_Child30=Bar-29 +ptn_Child31=Bar-30 +ptn_Child32=Bar-31 +ptn_Child33=Bar-32 + +[WorkState_v1_2.DockState.Bar-0] +BarID=59419 +Bars=20 +Bar#0=0 +Bar#1=59647 +Bar#2=0 +Bar#3=59392 +Bar#4=59396 +Bar#5=59400 +Bar#6=124939 +Bar#7=0 +Bar#8=124960 +Bar#9=0 +Bar#10=0 +Bar#11=59399 +Bar#12=59398 +Bar#13=59401 +Bar#14=124933 +Bar#15=124938 +Bar#16=0 +Bar#17=32768 +Bar#18=0 +Bar#19=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-1] +BarID=32768 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=978 +Style=12110 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=8192 +TypeID=0 +ClassName=SECControlBar +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-2] +BarID=59422 +Bars=9 +Bar#0=0 +Bar#1=5707 +Bar#2=5706 +Bar#3=5710 +Bar#4=5704 +Bar#5=5721 +Bar#6=0 +Bar#7=32769 +Bar#8=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-3] +BarID=32769 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=978 +Style=36686 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=150 +MRUVertDockCX=300 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=32768 +TypeID=0 +ClassName=SECControlBar +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-4] +BarID=59420 +Bars=6 +Bar#0=0 +Bar#1=5708 +Bar#2=5720 +Bar#3=0 +Bar#4=32770 +Bar#5=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-5] +BarID=32770 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=8014 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=150 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=4096 +TypeID=0 +ClassName=SECControlBar +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-6] +BarID=59421 +Bars=12 +Bar#0=0 +Bar#1=0 +Bar#2=5701 +Bar#3=0 +Bar#4=73539 +Bar#5=0 +Bar#6=35103 +Bar#7=35102 +Bar#8=35101 +Bar#9=35100 +Bar#10=32771 +Bar#11=0 +Style=0 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=0 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=0 +MRUHorzDockCY=0 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=0 +TypeID=0 +ClassName= +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-7] +BarID=32771 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=10 +MRUDockTopPos=30 +MRUDockRightPos=10 +MRUDockBottomPos=30 +MRUFloatStyle=4 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=20302 +ExStyle=0 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=150 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=16384 +TypeID=0 +ClassName=SECControlBar +WindowName= +ResourceID=0 + +[WorkState_v1_2.DockState.Bar-8] +BarID=59647 +MRUWidth=412 +Docking=True +MRUDockID=59419 +MRUDockLeftPos=-1 +MRUDockTopPos=-1 +MRUDockRightPos=1919 +MRUDockBottomPos=28 +MRUFloatStyle=8196 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=12220 +ExStyle=131980 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=429 +MRUFloatCY=27 +MRUHorzDockCX=1920 +MRUHorzDockCY=29 +MRUVertDockCX=72 +MRUVertDockCY=527 +MRUDockingState=0 +DockingStyle=61440 +TypeID=14947 +ClassName=SECMDIMenuBar +WindowName=Menu bar +ResourceID=0 +ptn_Child1=ToolBarInfoEx + +[WorkState_v1_2.DockState.Bar-8.ToolBarInfoEx] +Title=Menu bar +Buttons=BAAAAAAIAACAAAAAAIAADAAAAAAIAAEAAAAAAIAAFAAAAAAIAAGAAAAAAIAAHAAAAAAIAAIAAAAAAIAAJAAAAAAIAAKAAAAAAIAA + +[WorkState_v1_2.DockState.Bar-9] +BarID=59392 +YPos=28 +Docking=True +MRUDockID=0 +MRUDockLeftPos=8 +MRUDockTopPos=28 +MRUDockRightPos=156 +MRUDockBottomPos=58 +MRUFloatStyle=8196 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=12212 +ExStyle=131852 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=184352 +MRUFloatCX=0 +MRUFloatCY=0 +MRUHorzDockCX=148 +MRUHorzDockCY=30 +MRUVertDockCX=0 +MRUVertDockCY=0 +MRUDockingState=0 +DockingStyle=61440 +TypeID=14946 +ClassName=SECCustomToolBar +WindowName=File +ResourceID=0 +ptn_Child1=ToolBarInfoEx + +[WorkState_v1_2.DockState.Bar-9.ToolBarInfoEx] +Title=File +Buttons=AABOAAAAAAGPDBAAAAAAAIIBAAAAAAAAAAAAAAAADABOAAAAAAAAAAAAAAAAHABOAAAAAA + +[WorkState_v1_2.DockState.Bar-10] +BarID=59396 +XPos=221 +YPos=28 +MRUWidth=566 +Docking=True +MRUDockID=59419 +MRUDockLeftPos=221 +MRUDockTopPos=28 +MRUDockRightPos=804 +MRUDockBottomPos=58 +MRUFloatStyle=8196 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=12212 +ExStyle=131852 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=631295 +MRUFloatCX=580 +MRUFloatCY=30 +MRUHorzDockCX=583 +MRUHorzDockCY=30 +MRUVertDockCX=158 +MRUVertDockCY=142 +MRUDockingState=0 +DockingStyle=61440 +TypeID=14946 +ClassName=SECCustomToolBar +WindowName=Edit +ResourceID=0 +ptn_Child1=ToolBarInfoEx + +[WorkState_v1_2.DockState.Bar-10.ToolBarInfoEx] +Title=Edit +Buttons=LCBOAAAAAAMCBOAAAAAAAAAAAAAAAADCBOAAAAAACCBOAAAAAAFCBOAAAAAAAAAAAAAAAAECBOAAAACAGJAAEFEBAAAAAAAAAAAAAAAAPJAIAAAAAAAAAAAAAAAAJAJBAAAAAACAJBAAAAAAIAJBAAAAAAAAJBAAAAAAAAAAAAAAAAKFEBAAAAAALFEBAAAAAAMFEBAAAAAANFEBAAAAAAAAAAAAAAAAOFEBAAAAAA + +[WorkState_v1_2.DockState.Bar-11] +BarID=59397 +Visible=False +XPos=-2 +MRUWidth=246 +Docking=True +MRUDockID=59419 +MRUDockLeftPos=1278 +MRUDockTopPos=54 +MRUDockRightPos=1541 +MRUDockBottomPos=84 +MRUFloatStyle=8192 +MRUFloatXPos=1094 +MRUFloatYPos=51 +Style=12213 +ExStyle=131852 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=1000000 +MRUFloatCX=260 +MRUFloatCY=30 +MRUHorzDockCX=263 +MRUHorzDockCY=30 +MRUVertDockCX=31 +MRUVertDockCY=247 +MRUDockingState=0 +DockingStyle=61440 +TypeID=14946 +ClassName=SECCustomToolBar +WindowName=View +ResourceID=0 +ptn_Child1=ToolBarInfoEx + +[WorkState_v1_2.DockState.Bar-11.ToolBarInfoEx] +Title=View +Buttons=IFGBAAAAAAJFGBAAAAAAAAAAAAAAAAFEGBAAAAAAIEGBAAAAAAMBJIAAAAAAMEGBAAAAAAAAAAAAAAAAOEGBAAAAAAKEGBAAAAAALEGBAAAAAAPEGBAAAAAA + +[WorkState_v1_2.DockState.Bar-12] +BarID=59398 +XPos=569 +YPos=58 +MRUWidth=339 +Docking=True +MRUDockID=59419 +MRUDockLeftPos=569 +MRUDockTopPos=58 +MRUDockRightPos=925 +MRUDockBottomPos=88 +MRUFloatStyle=8196 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=12212 +ExStyle=131852 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=127407 +MRUFloatCX=356 +MRUFloatCY=30 +MRUHorzDockCX=356 +MRUHorzDockCY=30 +MRUVertDockCX=108 +MRUVertDockCY=115 +MRUDockingState=0 +DockingStyle=61440 +TypeID=14946 +ClassName=SECCustomToolBar +WindowName=Project +ResourceID=0 +ptn_Child1=ToolBarInfoEx + +[WorkState_v1_2.DockState.Bar-12.ToolBarInfoEx] +Title=Project +Buttons=KAAIAAAACAEGAAMAAIAAAACAEGAAAAAAAAAAAABBAIAAAAAACBAIAAAAAADBAIAAAAAAAAAAAAAAAAGBAIAAAAAAAAAAAAAAAACHIBAAAAAA + +[WorkState_v1_2.DockState.Bar-13] +BarID=59399 +XPos=0 +YPos=58 +MRUWidth=385 +Docking=True +MRUDockID=59419 +MRUDockLeftPos=8 +MRUDockTopPos=58 +MRUDockRightPos=410 +MRUDockBottomPos=88 +MRUFloatStyle=8196 +MRUFloatXPos=-1 +MRUFloatYPos=0 +Style=12212 +ExStyle=131852 +PrevFloating=False +MDIChild=False +AutoHide=False +AutoHidePinned=False +LastAlignedDocking=0 +PctWidth=714187 +MRUFloatCX=402 +MRUFloatCY=30 +MRUHorzDockCX=402 +MRUHorzDockCY=30 +MRUVertDockCX=31 +MRUVertDockCY=372 +MRUDockingState=0 +DockingStyle=61440 +TypeID=14946 +ClassName=SECCustomToolBar +WindowName=Debug +ResourceID=0 +ptn_Child1=ToolBarInfoEx + +[WorkState_v1_2.DockState.Bar-13.ToolBarInfoEx] +Title=Debug +Buttons=HKAIAAAAAAIKAIAAAAAAAAAAAAAAAAADKBAAAAAAAAAAAAAAAAGPKBAAAAAAEPKBAAAAAAFPKBAAAAAAHPKBAAAAAAAAAAAAAAAAMPKBAAAAAAAAAAAAAAAAIPKBAAAAAAJPKBAAAAAANPKBAAAAAAOPKBAAAAAAKPKBAAAAAALPKBAAAAAAAAAAAAAAAABDKBAAAAAA + +[WorkState_v1_2.DockState.Bar-14] +BarID=59400 +XPos=885 +YPos=28 +MRUWidth=23 +Docking=True +MRUDockID=59419 +MRUDockLeftPos=885 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+[WorkState_v1_2.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=..\..\tests\sem4.c +DocumentString= +DocTemplateIndex=0 +WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPIPPPPPPPCOPPPPPPGJAAAAAAGJAAAAAAFHFAAAAANDCAAAAA +IsActiveChildFrame=True +IsFrameVisible=True + +[WorkState_v1_2.Frames.ChildFrames.Document-1] +ptn_Child1=ViewFrame-0 + +[WorkState_v1_2.Frames.ChildFrames.Document-1.ViewFrame-0] +DocPathName=tests-main.c +DocumentString= +DocTemplateIndex=0 +WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPIPPPPPPPCOPPPPPPJBAAAAAAJBAAAAAADOEAAAAALKBAAAAA +IsActiveChildFrame=False +IsFrameVisible=True diff --git a/ports/stm8_oss/atomthreads.lkf b/ports/stm8_oss/atomthreads.lkf new file mode 100644 index 00000000..667f5411 --- /dev/null +++ b/ports/stm8_oss/atomthreads.lkf @@ -0,0 +1,66 @@ +# Segment configuration +# +# Segment Code,Constants: ++seg .const -b 0x8080 -m 0x7f80 -n .const -it ++seg .text -a .const -n .text +# Segment Eeprom: ++seg .eeprom -b 0x4000 -m 0x400 -n .eeprom +# Segment Zero Page (this deliberately avoids 0x0 to avoid +# NULL pointers to real data): ++seg .bsct -b 0x2 -m 0xfe -n .bsct ++seg .ubsct -a .bsct -n .ubsct ++seg .bit -a .ubsct -n .bit -id ++seg .share -a .bit -n .share -is +# Segment Ram (allow up to RAMTOP-64 to be used for data +# sections, leaving 64 bytes for the startup stack): ++seg .data -b 0x100 -m 0x6c0 -n .data ++seg .bss -a .data -n .bss +# + + +# Startup file +# +crtsi0.sm8 +# + + +# Object files list - section reserved for STVD +# +build-cosmic\atomkernel.o +build-cosmic\atommutex.o +build-cosmic\atomqueue.o +build-cosmic\atomsem.o +build-cosmic\atomtimer.o +build-cosmic\uart.o +# Caller passes in test application object name as param1 +# must be before tests-main.o +@1 +build-cosmic\tests-main.o +build-cosmic\atomport.o +build-cosmic\atomport-asm-cosmic.o +# + + +# Library list +# +libis0.sm8 +#libisl0.sm8 +libm0.sm8 +# + + +# Interrupt vectors file +# ++seg .const -b 0x8000 -k +build-cosmic\stm8_interrupt_vector.o +# + +# Defines +# ++def __endzp=@.ubsct # end of uninitialized zpage ++def __memory=@.bss # end of bss segment ++def __startmem=@.bss ++def __endmem=0x7bf +#+def __endmem=0x5ff ++def __stack=0x7ff +# diff --git a/ports/stm8_oss/cosmic.mak b/ports/stm8_oss/cosmic.mak new file mode 100644 index 00000000..de7dbc71 --- /dev/null +++ b/ports/stm8_oss/cosmic.mak @@ -0,0 +1,120 @@ +############ +# Settings # +############ + +# Set up build environment (using GNU Make) +# set PATH=%PATH%;C:\Program Files\GNU_MAKE;C:\Program Files\COSMIC\FSE_Compilers\CXSTM8 +# set MAKE_MODE=DOS + +# Build all test applications: +# make -f cosmic.mak + + +# Location of build tools and atomthreads sources +KERNEL_DIR=../../kernel +TESTS_DIR=../../tests +PERIPHS_DIR=stm8-include +LIBS_DIR="C:\Program Files\COSMIC\FSE_Compilers\CXSTM8\Lib" +CC=cxstm8 +ASM=castm8 +LINK=clnk +CHEX=chex + +# CPU part number +PART=STM8S105 + +# Enable stack-checking +STACK_CHECK=true + +# Directory for built objects +BUILD_DIR=build-cosmic + +# Port/application object files +APP_OBJECTS = atomport.o tests-main.o stm8_interrupt_vector.o uart.o +APP_ASM_OBJECTS = atomport-asm-cosmic.o + +# STM8S Peripheral driver object files +PERIPH_OBJECTS = + +# Kernel object files +KERNEL_OBJECTS = atomkernel.o atomsem.o atommutex.o atomtimer.o atomqueue.o + +# Collection of built objects (excluding test applications) +ALL_OBJECTS = $(APP_OBJECTS) $(APP_ASM_OBJECTS) $(PERIPH_OBJECTS) $(KERNEL_OBJECTS) +BUILT_OBJECTS = $(patsubst %,$(BUILD_DIR)/%,$(ALL_OBJECTS)) + +# Test object files (dealt with separately as only one per application build) +TEST_OBJECTS = $(notdir $(patsubst %.c,%.o,$(wildcard $(TESTS_DIR)/*.c))) + +# Target application filenames (.elf and .hex) for each test object +TEST_STM8S = $(patsubst %.o,%.stm8,$(TEST_OBJECTS)) +TEST_S19S = $(patsubst %.o,%.s19,$(TEST_OBJECTS)) + +# Search build/output directory for dependencies +vpath %.o .\$(BUILD_DIR) +vpath %.elf .\$(BUILD_DIR) +vpath %.hex .\$(BUILD_DIR) + +# Compiler/Assembler flags +CFLAGS=+modsl0 +split -pp -d$(PART) +DBG_CFLAGS=+modsl0 +split +debug -pxp -no -pp -l -d$(PART) +ASMFLAGS= +DBG_ASMFLAGS=-xx -u + +# Enable stack-checking (disable if not required) +ifeq ($(STACK_CHECK),true) +CFLAGS += -dATOM_STACK_CHECKING +DBG_CFLAGS += -dATOM_STACK_CHECKING +endif + + +################# +# Build targets # +################# + +# All tests +all: $(BUILD_DIR) $(TEST_S19S) cosmic.mak + +# Make build/output directory +$(BUILD_DIR): + mkdir $(BUILD_DIR) + +# Test HEX files (one application build for each test) +$(TEST_S19S): %.s19: %.stm8 + @echo Building $@ + $(CHEX) -fm -o $(BUILD_DIR)/$@ $(BUILD_DIR)/$< + +# Test ELF files (one application build for each test) +$(TEST_STM8S): %.stm8: %.o $(KERNEL_OBJECTS) $(PERIPH_OBJECTS) $(APP_OBJECTS) $(APP_ASM_OBJECTS) + $(LINK) -l$(LIBS_DIR) -o $(BUILD_DIR)/$@ -m $(BUILD_DIR)/$(basename $@).map atomthreads.lkf $(BUILD_DIR)/$(notdir $<) + +# Kernel objects builder +$(KERNEL_OBJECTS): %.o: $(KERNEL_DIR)/%.c + $(CC) $(CFLAGS) -i. -i$(PERIPHS_DIR) -co$(BUILD_DIR) $< + +# Test objects builder +$(TEST_OBJECTS): %.o: $(TESTS_DIR)/%.c + $(CC) $(CFLAGS) -i. -i$(KERNEL_DIR) -i$(PERIPHS_DIR) -co$(BUILD_DIR) $< + +# Peripheral objects builder +$(PERIPH_OBJECTS): %.o: $(PERIPHS_DIR)/%.c + $(CC) $(CFLAGS) -i. -i$(PERIPHS_DIR) -co$(BUILD_DIR) $< + +# Application C objects builder +$(APP_OBJECTS): %.o: ./%.c + $(CC) $(CFLAGS) -i. -i$(KERNEL_DIR) -i$(TESTS_DIR) -i$(PERIPHS_DIR) -co$(BUILD_DIR) $< + +# Application asm objects builder +$(APP_ASM_OBJECTS): %.o: ./%.s + $(ASM) $(ASMFLAGS) -i. -i$(KERNEL_DIR) -o$(BUILD_DIR)/$(notdir $@) $< + +# Clean +clean: + rm -f *.o *.elf *.map *.hex *.bin *.lst *.stm8 *.s19 + rm -rf doxygen-kernel + rm -rf doxygen-stm8 + rm -rf build-cosmic + +doxygen: + doxygen $(KERNEL_DIR)/Doxyfile + doxygen ./Doxyfile diff --git a/ports/stm8_oss/iar.mak b/ports/stm8_oss/iar.mak new file mode 100644 index 00000000..99d073d3 --- /dev/null +++ b/ports/stm8_oss/iar.mak @@ -0,0 +1,137 @@ +############ +# Settings # +############ + +# Set up build environment (using GNU Make) +# set PATH=%PATH%;C:\Program Files\GNU_MAKE;C:\Program Files\IAR Systems\Embedded Workbench 8.3\stm8\bin +# set MAKE_MODE=DOS + +# Build all test applications: +# make -f iar.mak + + +# Location of build tools and atomthreads sources +EWSTM8_DIR=C:\Program Files\IAR Systems\Embedded Workbench 8.3\stm8 +KERNEL_DIR=../../kernel +TESTS_DIR=../../tests +PERIPHS_DIR=stm8-include +CC=iccstm8 +ASM=iasmstm8 +LINK=ilinkstm8 +HEX=ielftool + +# CPU part number +PART=STM8S105 + +# Enable stack-checking +STACK_CHECK=true + +# Directory for built objects +BUILD_DIR=build-iar + +# Port/application object files +APP_OBJECTS = atomport.o tests-main.o uart.o +APP_ASM_OBJECTS = atomport-asm-iar.o + +# STM8S Peripheral driver object files +PERIPH_OBJECTS = + +# Kernel object files +KERNEL_OBJECTS = atomkernel.o atomsem.o atommutex.o atomtimer.o atomqueue.o + +# Collection of built objects (excluding test applications) +ALL_OBJECTS = $(APP_OBJECTS) $(APP_ASM_OBJECTS) $(PERIPH_OBJECTS) $(KERNEL_OBJECTS) +BUILT_OBJECTS = $(patsubst %,$(BUILD_DIR)/%,$(ALL_OBJECTS)) + +# Test object files (dealt with separately as only one per application build) +TEST_OBJECTS = $(notdir $(patsubst %.c,%.o,$(wildcard $(TESTS_DIR)/*.c))) + +# Target application filenames (.elf) for each test object +TEST_ELFS = $(patsubst %.o,%.elf,$(TEST_OBJECTS)) +TEST_S19S = $(patsubst %.o,%.s19,$(TEST_OBJECTS)) + +# Search build/output directory for dependencies +vpath %.o .\$(BUILD_DIR) +vpath %.elf .\$(BUILD_DIR) +vpath %.hex .\$(BUILD_DIR) + +# Compiler/Assembler flags +CFLAGS=-e -Oh --code_model small --data_model medium \ + --dlib_config "$(EWSTM8_DIR)\lib\dlstm8smn.h" -D NDEBUG -D $(PART) \ + --diag_suppress Pa050 +DBG_CFLAGS=-e -Ol --no_cse --no_unroll --no_inline --no_code_motion --no_tbaa \ + --no_cross_call --debug --code_model small --data_model medium \ + --dlib_config "$(EWSTM8_DIR)\lib\dlstm8smn.h" -D $(PART) \ + --diag_suppress Pa050 + +ASMFLAGS=-M'<>' -ld $(BUILD_DIR)\list --diag_suppress Pa050 --code_model small \ + --data_model medium +DBG_ASMFLAGS=-M'<>' -r -ld $(BUILD_DIR)\list --diag_suppress Pa050 --code_model small \ + --data_model medium + +LINKFLAGS=--redirect _Printf=_PrintfSmall --redirect _Scanf=_ScanfSmall \ + --config "$(EWSTM8_DIR)\config\lnkstm8s105c6.icf" --config_def \ + _CSTACK_SIZE=0x100 --config_def _HEAP_SIZE=0x100 \ + --entry __iar_program_start +DBG_LINKFLAGS=--redirect _Printf=_PrintfSmall --redirect _Scanf=_ScanfSmall \ + --config "$(EWSTM8_DIR)\config\lnkstm8s105c6.icf" --config_def \ + _CSTACK_SIZE=0x100 --config_def _HEAP_SIZE=0x100 \ + --entry __iar_program_start + +# Enable stack-checking (disable if not required) +ifeq ($(STACK_CHECK),true) +CFLAGS += -D ATOM_STACK_CHECKING +DBG_CFLAGS += -D ATOM_STACK_CHECKING +endif + + +################# +# Build targets # +################# + +# All tests +all: $(BUILD_DIR) $(TEST_S19S) iar.mak + +# Make build/output directory +$(BUILD_DIR): + mkdir $(BUILD_DIR) + +# Test HEX files (one application build for each test) +$(TEST_S19S): %.s19: %.elf + @echo Building $@ + $(HEX) $(BUILD_DIR)/$(notdir $<) $(BUILD_DIR)/$@ --srec + +# Test ELF files (one application build for each test) +$(TEST_ELFS): %.elf: %.o $(KERNEL_OBJECTS) $(PERIPH_OBJECTS) $(APP_OBJECTS) $(APP_ASM_OBJECTS) + $(LINK) $(BUILD_DIR)/$(notdir $<) $(BUILT_OBJECTS) $(LINKFLAGS) -o $(BUILD_DIR)/$@ + +# Kernel objects builder +$(KERNEL_OBJECTS): %.o: $(KERNEL_DIR)/%.c + $(CC) $< $(CFLAGS) -I . -I $(PERIPHS_DIR) -o $(BUILD_DIR) + +# Test objects builder +$(TEST_OBJECTS): %.o: $(TESTS_DIR)/%.c + $(CC) $< $(CFLAGS) -I . -I $(KERNEL_DIR) -I $(PERIPHS_DIR) -o $(BUILD_DIR) + +# Peripheral objects builder +$(PERIPH_OBJECTS): %.o: $(PERIPHS_DIR)/%.c + $(CC) $< $(CFLAGS) -I . -I $(PERIPHS_DIR) -o $(BUILD_DIR) + +# Application C objects builder +$(APP_OBJECTS): %.o: ./%.c + $(CC) $< $(CFLAGS) -I $(KERNEL_DIR) -I $(TESTS_DIR) -I $(PERIPHS_DIR) -o $(BUILD_DIR) + +# Application asm objects builder +$(APP_ASM_OBJECTS): %.o: ./%.s + $(ASM) $< $(ASMFLAGS) -I $(KERNEL_DIR) -o $(BUILD_DIR)/$(notdir $@) + +# Clean +clean: + rm -f *.o *.elf *.map *.hex *.bin *.lst *.stm8 *.s19 *.out + rm -rf doxygen-kernel + rm -rf doxygen-stm8 + rm -rf build-iar + +doxygen: + doxygen $(KERNEL_DIR)/Doxyfile + doxygen ./Doxyfile diff --git a/ports/stm8_oss/run_tests.sh b/ports/stm8_oss/run_tests.sh new file mode 100755 index 00000000..a2a5dadd --- /dev/null +++ b/ports/stm8_oss/run_tests.sh @@ -0,0 +1,29 @@ +#!/bin/bash + +# change to current working directory +cd `dirname $0` + +# SDCC test +echo "" +echo "run SDCC " $1 +stm8flash -c stlink -p stm8s105c6 -w build-sdcc/$1.ihx # STM8S Discovery +#stm8flash -c stlinkv2 -p stm8l152c6 -w build-sdcc/$1.ihx # STM8L Discovery +#stm8gal -p /dev/ttyUSB0 -V 0 -R 0 -w build-sdcc/$1.ihx # Sduino / muBoard +miniterm /dev/ttyUSB0 9600 +exit + +# Cosmic test +echo "" +echo "run Cosmic" $1 +stm8flash -c stlink -p stm8s105c6 -w build-cosmic/$1.s19 # STM8S Discovery +#stm8flash -c stlinkv2 -p stm8l152c6 -w build-cosmic/$1.ihx # STM8L Discovery +#stm8gal -p /dev/ttyUSB0 -V 0 -w build-cosmic/$1.ihx # Sduino / muBoard +miniterm /dev/ttyUSB0 9600 + +# IAR test +echo "" +echo "run IAR" $1 +stm8flash -c stlink -p stm8s105c6 -w build-iar/$1.s19 # STM8S Discovery +#stm8flash -c stlinkv2 -p stm8l152c6 -w build-cosmic/$1.ihx # STM8L Discovery +#stm8gal -p /dev/ttyUSB0 -V 0 -w build-cosmic/$1.ihx # Sduino / muBoard +miniterm /dev/ttyUSB0 9600 diff --git a/ports/stm8_oss/sdcc.mak b/ports/stm8_oss/sdcc.mak new file mode 100644 index 00000000..cfc97b87 --- /dev/null +++ b/ports/stm8_oss/sdcc.mak @@ -0,0 +1,106 @@ +KERNEL_DIR=../../kernel +TESTS_DIR=../../tests +PERIPHS_DIR=stm8-include + +CC=sdcc +ASM=sdasstm8 +LINK=sdcc + +# CPU part number +PART=STM8S105 + +# Enable stack-checking +STACK_CHECK=true + +# Directory for built objects +BUILD_DIR=build-sdcc + +# Port/application object files +APP_OBJECTS = atomport.rel tests-main.rel uart.rel +APP_ASM_OBJECTS = atomport-asm-sdcc.rel + +# STM8S Peripheral driver object files +PERIPH_OBJECTS = + +# Kernel object files +KERNEL_OBJECTS = atomkernel.rel atomsem.rel atommutex.rel atomtimer.rel atomqueue.rel + +# Collection of built objects (excluding test applications) +ALL_OBJECTS = $(APP_OBJECTS) $(APP_ASM_OBJECTS) $(PERIPH_OBJECTS) $(KERNEL_OBJECTS) +BUILT_OBJECTS = $(patsubst %,$(BUILD_DIR)/%,$(ALL_OBJECTS)) + +# Test object files (dealt with separately as only one per application build) +TEST_OBJECTS = $(notdir $(patsubst %.c,%.rel,$(wildcard $(TESTS_DIR)/*.c))) + +# Target application filenames (.elf) for each test object +TEST_HEXS = $(patsubst %.rel,%.ihx,$(TEST_OBJECTS)) +TEST_ELFS = $(patsubst %.rel,%.elf,$(TEST_OBJECTS)) + +# Search build/output directory for dependencies +vpath %.rel .\$(BUILD_DIR) +vpath %.elf .\$(BUILD_DIR) +vpath %.hex .\$(BUILD_DIR) + +# Compiler/Assembler flags +CFLAGS= -mstm8 -c -D $(PART) --opt-code-size +DBG_CFLAGS= -mstm8 -c -D $(PART) --opt-code-size +ASMFLAGS= -loff +DBG_ASMFLAGS= -loff +LINKFLAGS= -mstm8 +DBG_LINKFLAGS= --debug -mstm8 + +# Enable stack-checking (disable if not required) +ifeq ($(STACK_CHECK),true) +CFLAGS += -D ATOM_STACK_CHECKING +DBG_CFLAGS += --debug -D ATOM_STACK_CHECKING +endif + +################# +# Build targets # +################# + +# All tests +all: $(BUILD_DIR) $(TEST_HEXS) sdcc.mak + +# Make build/output directory +$(BUILD_DIR): + mkdir $(BUILD_DIR) + +# Test HEX files (one application build for each test) +$(TEST_HEXS): %.ihx: %.rel $(KERNEL_OBJECTS) $(PERIPH_OBJECTS) $(APP_OBJECTS) $(APP_ASM_OBJECTS) + $(LINK) $(BUILD_DIR)/$(notdir $<) $(BUILT_OBJECTS) $(LINKFLAGS) -o $(BUILD_DIR)/$@ + +# Test ELF files (one application build for each test) +$(TEST_ELFS): %.elf: %.rel $(KERNEL_OBJECTS) $(PERIPH_OBJECTS) $(APP_OBJECTS) $(APP_ASM_OBJECTS) + $(LINK) $(BUILD_DIR)/$(notdir $<) $(BUILT_OBJECTS) $(LINKFLAGS) --out-fmt-elf -o $(BUILD_DIR)/$@ + +# Kernel objects builder +$(KERNEL_OBJECTS): %.rel: $(KERNEL_DIR)/%.c + $(CC) $< $(CFLAGS) -I . -I $(PERIPHS_DIR) -o $(BUILD_DIR)/$*.rel + +# Test objects builder +$(TEST_OBJECTS): %.rel: $(TESTS_DIR)/%.c + $(CC) $< $(CFLAGS) -I . -I $(KERNEL_DIR) -I $(PERIPHS_DIR) -o $(BUILD_DIR)/$*.rel + +# Peripheral objects builder +$(PERIPH_OBJECTS): %.rel: $(PERIPHS_DIR)/%.c + $(CC) $< $(CFLAGS) -I . -I $(PERIPHS_DIR) -o $(BUILD_DIR)/$*.rel + +# Application C objects builder +$(APP_OBJECTS): %.rel: ./%.c + $(CC) $< $(CFLAGS) -I . -I $(KERNEL_DIR) -I $(TESTS_DIR) -I $(PERIPHS_DIR) -o $(BUILD_DIR)/$*.rel + +# Application asm objects builder +$(APP_ASM_OBJECTS): %.rel: ./%.s + $(ASM) $(ASMFLAGS) $(BUILD_DIR)/$(notdir $@) $< + +# Clean +clean: + rm -f *.o *.elf *.map *.hex *.bin *.lst *.stm8 *.s19 + rm -rf doxygen-kernel + rm -rf doxygen-stm8 + rm -rf build-sdcc + +doxygen: + doxygen $(KERNEL_DIR)/Doxyfile + doxygen ./Doxyfile diff --git a/ports/stm8_oss/stm8-include/STM8L152C6.h b/ports/stm8_oss/stm8-include/STM8L152C6.h new file mode 100644 index 00000000..f5549a44 --- /dev/null +++ b/ports/stm8_oss/stm8-include/STM8L152C6.h @@ -0,0 +1,7946 @@ +/*------------------------------------------------------------------------- + + STM8L152C6.h - Device Declarations + + STM8L/STM8AL, medium density with ROM bootloader + + Copyright (C) 2020, Georg Icking-Konert + + Ultra-low-power 8-bit MCU with 32 Kbytes Flash, 16 MHz CPU, integrated EEPROM + + datasheet: https://www.st.com/resource/en/datasheet/stm8l152c6.pdf + reference: RM0031 https://www.st.com/content/ccc/resource/technical/document/reference_manual/2e/3b/8c/8f/60/af/4b/2c/CD00218714.pdf/files/CD00218714.pdf/jcr:content/translations/en.CD00218714.pdf + + MIT License + + Copyright (c) 2020 Georg Icking-Konert + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. + +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- + MODULE DEFINITION FOR MULTIPLE INCLUSION +-------------------------------------------------------------------------*/ +#ifndef STM8L152C6_H +#define STM8L152C6_H + +// DEVICE NAME +#define DEVICE_STM8L152C6 + +// DEVICE FAMILY +#define FAMILY_STM8L + +// required for C++ +#ifdef __cplusplus + extern "C" { +#endif + + +/*------------------------------------------------------------------------- + INCLUDE FILES +-------------------------------------------------------------------------*/ +#include + + +/*------------------------------------------------------------------------- + COMPILER SPECIFIC SETTINGS +-------------------------------------------------------------------------*/ + +// Cosmic compiler +#if defined(__CSMC__) + + // macros to unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) @far @interrupt void func(void) ///< handler for interrupt service routine + #define ISR_HANDLER_TRAP(func) void @far @interrupt func(void) ///< handler for trap service routine + + // definition of inline functions + #define INLINE @inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() _asm("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() _asm("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() _asm("rim") ///< enable interrupt handling + #define TRIGGER_TRAP _asm("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() _asm("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() _asm("halt") ///< put controller to HALT mode + #define SW_RESET() _asm("dc.b $75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + + +// IAR Compiler +#elif defined(__ICCSTM8__) + + // include intrinsic functions + #include + + // macros to unify ISR declaration and implementation + #define STRINGVECTOR(x) #x + #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) + #define ISR_HANDLER( a, b ) \ + _Pragma( VECTOR_ID( (b)+2 ) ) \ + __interrupt void (a)( void ) + #define ISR_HANDLER_TRAP(a) \ + _Pragma( VECTOR_ID( 1 ) ) \ + __interrupt void (a) (void) + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __no_operation() ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __disable_interrupt() ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __enable_interrupt() ///< enable interrupt handling + #define TRIGGER_TRAP __trap() ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __wait_for_interrupt() ///< stop code execution and wait for interrupt + #define ENTER_HALT() __halt() ///< put controller to HALT mode + #define SW_RESET() __asm("dc8 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned char ///< data type in bit structs (deviating from C90 standard) + + +// SDCC compiler +#elif defined(__SDCC) + + // store SDCC version in preprocessor friendly way + #define SDCC_VERSION (__SDCC_VERSION_MAJOR * 10000 \ + + __SDCC_VERSION_MINOR * 100 \ + + __SDCC_VERSION_PATCH) + + // unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) void func(void) __interrupt(irq) ///< handler for interrupt service routine + #if SDCC_VERSION >= 30403 // traps require >=v3.4.3 + #define ISR_HANDLER_TRAP(func) void func() __trap ///< handler for trap service routine + #else + #error traps require SDCC >=3.4.3. Please update! + #endif + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __asm__("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __asm__("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __asm__("rim") ///< enable interrupt handling + #define TRIGGER_TRAP __asm__("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __asm__("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() __asm__("halt") ///< put controller to HALT mode + #define SW_RESET() __asm__(".db 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + +// unsupported compiler -> stop +#else + #error: compiler not supported +#endif + + +/*------------------------------------------------------------------------- + FOR CONVENIENT PIN ACCESS +-------------------------------------------------------------------------*/ + +#define PIN0 0x01 +#define PIN1 0x02 +#define PIN2 0x04 +#define PIN3 0x08 +#define PIN4 0x10 +#define PIN5 0x20 +#define PIN6 0x40 +#define PIN7 0x80 + + +/*------------------------------------------------------------------------- + DEVICE MEMORY (size in bytes) +-------------------------------------------------------------------------*/ + +// RAM +#define RAM_ADDR_START 0x000000 +#define RAM_ADDR_END 0x0007FF +#define RAM_SIZE 2048 + + +// EEPROM +#define EEPROM_ADDR_START 0x001000 +#define EEPROM_ADDR_END 0x0013FF +#define EEPROM_SIZE 1024 + + +// OPTION +#define OPTION_ADDR_START 0x004800 +#define OPTION_ADDR_END 0x0048FF +#define OPTION_SIZE 256 + + +// SFR1 +#define SFR1_ADDR_START 0x005000 +#define SFR1_ADDR_END 0x0057FF +#define SFR1_SIZE 2048 + + +// BOOTROM +#define BOOTROM_ADDR_START 0x006000 +#define BOOTROM_ADDR_END 0x0067FF +#define BOOTROM_SIZE 2048 + + +// SFR2 +#define SFR2_ADDR_START 0x007F00 +#define SFR2_ADDR_END 0x007FFF +#define SFR2_SIZE 256 + + +// FLASH +#define FLASH_ADDR_START 0x008000 +#define FLASH_ADDR_END 0x00FFFF +#define FLASH_SIZE 32768 + + +// MEMORY WIDTH (>32kB flash exceeds 16bit, as flash starts at 0x8000) +#define FLASH_ADDR_WIDTH 16 ///< width of address space +#define FLASH_POINTER_T uint16_t ///< address variable type + + +/*------------------------------------------------------------------------- + UNIQUE IDENTIFIER (size in bytes) +-------------------------------------------------------------------------*/ + +#define UID_ADDR_START 0x4926 ///< start address of unique identifier +#define UID_SIZE 12 ///< size of unique identifier [B] +#define UID(N) (*((uint8_t*) (UID_ADDR_START+N))) ///< read unique identifier byte N + + +/*------------------------------------------------------------------------- + ISR Vector Table (SDCC, IAR) + Notes: + - IAR has an IRQ offset of +2 compared to datasheet and below numbers + - Cosmic uses a separate, device specific file 'stm8_interrupt_vector.c' + - different interrupt sources may share the same IRQ +-------------------------------------------------------------------------*/ + +// interrupt IRQ +#define _TLI_VECTOR_ 0 +#define _FLASH_EOP_VECTOR_ 1 ///< FLASH_EOP interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.EOP, priority: ITC_SPR1.VECT1SPR +#define _FLASH_WR_PG_DIS_VECTOR_ 1 ///< FLASH_WR_PG_DIS interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.WR_PG_DIS, priority: ITC_SPR1.VECT1SPR +#define _DMA1_CH0_HT_VECTOR_ 2 ///< DMA1_CH0_HT interrupt vector: enable: DMA1_C0CR.HTIE, pending: DMA1_C0SPR.HTIF, priority: ITC_SPR1.VECT2SPR +#define _DMA1_CH0_TC_VECTOR_ 2 ///< DMA1_CH0_TC interrupt vector: enable: DMA1_C0CR.TCIE, pending: DMA1_C0SPR.TCIF, priority: ITC_SPR1.VECT2SPR +#define _DMA1_CH1_HT_VECTOR_ 2 ///< DMA1_CH1_HT interrupt vector: enable: DMA1_C1CR.HTIE, pending: DMA1_C1SPR.HTIF, priority: ITC_SPR1.VECT2SPR +#define _DMA1_CH1_TC_VECTOR_ 2 ///< DMA1_CH1_TC interrupt vector: enable: DMA1_C1CR.TCIE, pending: DMA1_C1SPR.TCIF, priority: ITC_SPR1.VECT2SPR +#define _DMA1_CH2_HT_VECTOR_ 3 ///< DMA1_CH2_HT interrupt vector: enable: DMA1_C2CR.HTIE, pending: DMA1_C2SPR.HTIF, priority: ITC_SPR1.VECT3SPR +#define _DMA1_CH2_TC_VECTOR_ 3 ///< DMA1_CH2_TC interrupt vector: enable: DMA1_C2CR.TCIE, pending: DMA1_C2SPR.TCIF, priority: ITC_SPR1.VECT3SPR +#define _DMA1_CH3_HT_VECTOR_ 3 ///< DMA1_CH3_HT interrupt vector: enable: DMA1_C3CR.HTIE, pending: DMA1_C3SPR.HTIF, priority: ITC_SPR1.VECT3SPR +#define _DMA1_CH3_TC_VECTOR_ 3 ///< DMA1_CH3_TC interrupt vector: enable: DMA1_C3CR.TCIE, pending: DMA1_C3SPR.TCIF, priority: ITC_SPR1.VECT3SPR +#define _RTC_ALARM_VECTOR_ 4 ///< RTC_ALARM interrupt vector: enable: RTC_CR2.ALRAIE, pending: RTC_ISR2.ALRAF, priority: ITC_SPR2.VECT4SPR +#define _RTC_WAKEUP_VECTOR_ 4 ///< RTC_WAKEUP interrupt vector: enable: RTC_CR2.WUTIE, pending: RTC_ISR2.WUTF, priority: ITC_SPR2.VECT4SPR +#define _EXTIE_VECTOR_ 5 ///< EXTIE interrupt vector: enable: EXTI_CR3.PEIS, pending: EXTI_SR2.PEF, priority: ITC_SPR2.VECT5SPR +#define _EXTIF_VECTOR_ 5 ///< EXTIF interrupt vector: enable: EXTI_CR3.PFIS, pending: EXTI_SR2.PFF, priority: ITC_SPR2.VECT5SPR +#define _EXTIPVD_VECTOR_ 5 ///< EXTIPVD interrupt vector: enable: PWR_CSR1.PVDE, pending: PWR_CSR1.PVDIF, priority: ITC_SPR2.VECT5SPR +#define _EXTIB_VECTOR_ 6 ///< EXTIB interrupt vector: enable: EXTI_CR3.PBIS, pending: EXTI_SR2.PBF, priority: ITC_SPR2.VECT6SPR +#define _EXTID_VECTOR_ 7 ///< EXTID interrupt vector: enable: EXTI_CR3.PDIS, pending: EXTI_SR2.PDF, priority: ITC_SPR2.VECT7SPR +#define _EXTI0_VECTOR_ 8 ///< EXTI0 interrupt vector: enable: EXTI_CR1.P0IS, pending: EXTI_SR1.P0F, priority: ITC_SPR3.VECT8SPR +#define _EXTI1_VECTOR_ 9 ///< EXTI1 interrupt vector: enable: EXTI_CR1.P1IS, pending: EXTI_SR1.P1F, priority: ITC_SPR3.VECT9SPR +#define _EXTI2_VECTOR_ 10 ///< EXTI2 interrupt vector: enable: EXTI_CR1.P2IS, pending: EXTI_SR1.P2F, priority: ITC_SPR3.VECT10SPR +#define _EXTI3_VECTOR_ 11 ///< EXTI3 interrupt vector: enable: EXTI_CR1.P3IS, pending: EXTI_SR1.P3F, priority: ITC_SPR3.VECT11SPR +#define _EXTI4_VECTOR_ 12 ///< EXTI4 interrupt vector: enable: EXTI_CR2.P4IS, pending: EXTI_SR1.P4F, priority: ITC_SPR4.VECT12SPR +#define _EXTI5_VECTOR_ 13 ///< EXTI5 interrupt vector: enable: EXTI_CR2.P5IS, pending: EXTI_SR1.P5F, priority: ITC_SPR4.VECT13SPR +#define _EXTI6_VECTOR_ 14 ///< EXTI6 interrupt vector: enable: EXTI_CR2.P6IS, pending: EXTI_SR1.P6F, priority: ITC_SPR4.VECT14SPR +#define _EXTI7_VECTOR_ 15 ///< EXTI7 interrupt vector: enable: EXTI_CR2.P7IS, pending: EXTI_SR1.P7F, priority: ITC_SPR4.VECT15SPR +#define _LCD_SOF_VECTOR_ 16 ///< LCD_SOF interrupt vector: enable: LCD_CR3.SOFIE, pending: LCD_CR3.SOF, priority: ITC_SPR4.VECT16SPR +#define _CLK_CSS_VECTOR_ 17 ///< CLK_CSS interrupt vector: enable: CLK_CSSR.CSSDIE, pending: CLK_CSSR.CSSD, priority: ITC_SPR4.VECT17SPR +#define _CLK_SWITCH_VECTOR_ 17 ///< CLK_SWITCH interrupt vector: enable: CLK_SWCR.SWIEN, pending: CLK_SWCR.SWIF, priority: ITC_SPR4.VECT17SPR +#define _TIM1_BIF_VECTOR_ 17 ///< TIM1_BIF interrupt vector: enable: TIM1_IER.BIE, pending: TIM1_SR1.BIF, priority: ITC_SPR4.VECT17SPR +#define _ADC1_AWD_VECTOR_ 18 ///< ADC1_AWD interrupt vector: enable: ADC1_CR1.AWDIE, pending: ADC1_SR.AWD, priority: ITC_SPR5.VECT18SPR +#define _ADC1_EOC_VECTOR_ 18 ///< ADC1_EOC interrupt vector: enable: ADC1_CR1.EOCIE, pending: ADC1_SR.EOC, priority: ITC_SPR5.VECT18SPR +#define _ADC1_OVER_VECTOR_ 18 ///< ADC1_OVER interrupt vector: enable: ADC1_CR1.OVERIE, pending: ADC1_SR.OVER, priority: ITC_SPR5.VECT18SPR +#define _COMP_EF1_VECTOR_ 18 ///< COMP_EF1 interrupt vector: enable: COMP_CSR1.IE1, pending: COMP_CSR1.EF1, priority: ITC_SPR5.VECT18SPR +#define _COMP_EF2_VECTOR_ 18 ///< COMP_EF2 interrupt vector: enable: COMP_CSR2.IE2, pending: COMP_CSR2.EF2, priority: ITC_SPR5.VECT18SPR +#define _TIM2_BIF_VECTOR_ 19 ///< TIM2_BIF interrupt vector: enable: TIM2_IER.BIE, pending: TIM2_SR1.BIF, priority: ITC_SPR5.VECT19SPR +#define _TIM2_OVR_UIF_VECTOR_ 19 ///< TIM2_OVR_UIF interrupt vector: enable: TIM2_IER.UIE, pending: TIM2_SR1.UIF, priority: ITC_SPR5.VECT19SPR +#define _TIM2_TIF_VECTOR_ 19 ///< TIM2_TIF interrupt vector: enable: TIM2_IER.TIE, pending: TIM2_SR1.TIF, priority: ITC_SPR5.VECT19SPR +#define _TIM2_CAPCOM_CC1IF_VECTOR_ 20 ///< TIM2_CAPCOM_CC1IF interrupt vector: enable: TIM2_IER.CC1IE, pending: TIM2_SR1.CC1IF, priority: ITC_SPR6.VECT20SPR +#define _TIM2_CAPCOM_CC2IF_VECTOR_ 20 ///< TIM2_CAPCOM_CC2IF interrupt vector: enable: TIM2_IER.CC2IE, pending: TIM2_SR1.CC2IF, priority: ITC_SPR6.VECT20SPR +#define _TIM3_BIF_VECTOR_ 21 ///< TIM3_BIF interrupt vector: enable: TIM3_IER.BIE, pending: TIM3_SR1.BIF, priority: ITC_SPR5.VECT21SPR +#define _TIM3_OVR_UIF_VECTOR_ 21 ///< TIM3_OVR_UIF interrupt vector: enable: TIM3_IER.UIE, pending: TIM3_SR1.UIF, priority: ITC_SPR5.VECT21SPR +#define _TIM3_TIF_VECTOR_ 21 ///< TIM3_TIF interrupt vector: enable: TIM3_IER.TIE, pending: TIM3_SR1.TIF, priority: ITC_SPR5.VECT21SPR +#define _TIM3_CAPCOM_CC1IF_VECTOR_ 22 ///< TIM3_CAPCOM_CC1IF interrupt vector: enable: TIM3_IER.CC1IE, pending: TIM3_SR1.CC1IF, priority: ITC_SPR6.VECT22SPR +#define _TIM3_CAPCOM_CC2IF_VECTOR_ 22 ///< TIM3_CAPCOM_CC2IF interrupt vector: enable: TIM3_IER.CC2IE, pending: TIM3_SR1.CC2IF, priority: ITC_SPR6.VECT22SPR +#define _TIM1_OVR_UIF_VECTOR_ 23 ///< TIM1_OVR_UIF interrupt vector: enable: TIM1_IER.UIE, pending: TIM1_SR1.UIF, priority: ITC_SPR6.VECT23SPR +#define _TIM1_TIF_VECTOR_ 23 ///< TIM1_TIF interrupt vector: enable: TIM1_IER.TIE, pending: TIM1_SR1.TIF, priority: ITC_SPR6.VECT23SPR +#define _TIM1_CAPCOM_CC1IF_VECTOR_ 24 ///< TIM1_CAPCOM_CC1IF interrupt vector: enable: TIM1_IER.CC1IE, pending: TIM1_SR1.CC1IF, priority: ITC_SPR6.VECT24SPR +#define _TIM1_CAPCOM_CC2IF_VECTOR_ 24 ///< TIM1_CAPCOM_CC2IF interrupt vector: enable: TIM1_IER.CC2IE, pending: TIM1_SR1.CC2IF, priority: ITC_SPR6.VECT24SPR +#define _TIM1_CAPCOM_CC3IF_VECTOR_ 24 ///< TIM1_CAPCOM_CC3IF interrupt vector: enable: TIM1_IER.CC3IE, pending: TIM1_SR1.CC2IF, priority: ITC_SPR6.VECT24SPR +#define _TIM1_CAPCOM_CC4IF_VECTOR_ 24 ///< TIM1_CAPCOM_CC4IF interrupt vector: enable: TIM1_IER.CC4IE, pending: TIM1_SR1.CC4IF, priority: ITC_SPR6.VECT24SPR +#define _TIM1_CAPCOM_COMIF_VECTOR_ 24 ///< TIM1_CAPCOM_COMIF interrupt vector: enable: TIM1_IER.COMIE, pending: TIM1_SR1.COMIF, priority: ITC_SPR6.VECT24SPR +#define _TIM4_TIF_VECTOR_ 25 ///< TIM4_TIF interrupt vector: enable: TIM4_IER.TIE, pending: TIM4_SR1.TIF, priority: ITC_SPR7.VECT25SPR +#define _TIM4_UIF_VECTOR_ 25 ///< TIM4_UIF interrupt vector: enable: TIM4_IER.UIE, pending: TIM4_SR1.UIF, priority: ITC_SPR7.VECT25SPR +#define _SPI_MODF_VECTOR_ 26 ///< SPI_MODF interrupt vector: enable: SPI1_ICR.ERRIE, pending: SPI1_SR.MODF, priority: ITC_SPR7.VECT26SPR +#define _SPI_OVR_VECTOR_ 26 ///< SPI_OVR interrupt vector: enable: SPI1_ICR.ERRIE, pending: SPI1_SR.OVR, priority: ITC_SPR7.VECT26SPR +#define _SPI_RXNE_VECTOR_ 26 ///< SPI_RXNE interrupt vector: enable: SPI1_ICR.RXIE, pending: SPI1_SR.RXNE, priority: ITC_SPR7.VECT26SPR +#define _SPI_TXE_VECTOR_ 26 ///< SPI_TXE interrupt vector: enable: SPI1_ICR.TXIE, pending: SPI1_SR.TXE, priority: ITC_SPR7.VECT26SPR +#define _SPI_WKUP_VECTOR_ 26 ///< SPI_WKUP interrupt vector: enable: SPI1_ICR.WKIE, pending: SPI1_SR.WKUP, priority: ITC_SPR7.VECT26SPR +#define _USART_T_TC_VECTOR_ 27 ///< USART_T_TC interrupt vector: enable: USART1_CR2.TCIEN, pending: USART1_SR.TC, priority: ITC_SPR7.VECT27SPR +#define _USART_T_TXE_VECTOR_ 27 ///< USART_T_TXE interrupt vector: enable: USART1_CR2.TIEN, pending: USART1_SR.TXE, priority: ITC_SPR7.VECT27SPR +#define _USART_R_IDLE_VECTOR_ 28 ///< USART_R_IDLE interrupt vector: enable: USART1_CR2.ILIEN, pending: USART1_SR.IDLE, priority: ITC_SPR7.VECT28SPR +#define _USART_R_OR_VECTOR_ 28 ///< USART_R_OR interrupt vector: enable: USART1_CR2.RIEN, pending: USART1_SR.OR, priority: ITC_SPR7.VECT28SPR +#define _USART_R_PE_VECTOR_ 28 ///< USART_R_PE interrupt vector: enable: USART1_CR1.PIEN, pending: USART1_SR.PE, priority: ITC_SPR7.VECT28SPR +#define _USART_R_RXNE_VECTOR_ 28 ///< USART_R_RXNE interrupt vector: enable: USART1_CR2.RIEN, pending: USART1_SR.RXNE, priority: ITC_SPR7.VECT28SPR +#define _I2C_ADD10_VECTOR_ 29 ///< I2C_ADD10 interrupt vector: enable: I2C1_ITR.ITEVTEN, pending: I2C1_SR1.ADD10, priority: ITC_SPR8.VECT29SPR +#define _I2C_ADDR_VECTOR_ 29 ///< I2C_ADDR interrupt vector: enable: I2C1_ITR.ITEVTEN, pending: I2C1_SR1.ADDR, priority: ITC_SPR8.VECT29SPR +#define _I2C_AF_VECTOR_ 29 ///< I2C_AF interrupt vector: enable: I2C1_ITR.ITERREN, pending: I2C1_SR2.AF, priority: ITC_SPR8.VECT29SPR +#define _I2C_ARLO_VECTOR_ 29 ///< I2C_ARLO interrupt vector: enable: I2C1_ITR.ITERREN, pending: I2C1_SR2.ARLO, priority: ITC_SPR8.VECT29SPR +#define _I2C_BERR_VECTOR_ 29 ///< I2C_BERR interrupt vector: enable: I2C1_ITR.ITERREN, pending: I2C1_SR2.BERR, priority: ITC_SPR8.VECT29SPR +#define _I2C_BTF_VECTOR_ 29 ///< I2C_BTF interrupt vector: enable: I2C1_ITR.ITEVTEN, pending: I2C1_SR1.BTF, priority: ITC_SPR8.VECT29SPR +#define _I2C_OVR_VECTOR_ 29 ///< I2C_OVR interrupt vector: enable: I2C1_ITR.ITERREN, pending: I2C1_SR2.OVR, priority: ITC_SPR8.VECT29SPR +#define _I2C_RXNE_VECTOR_ 29 ///< I2C_RXNE interrupt vector: enable: I2C1_ITR.ITBUFEN, pending: I2C1_SR1.RXNE, priority: ITC_SPR8.VECT29SPR +#define _I2C_SB_VECTOR_ 29 ///< I2C_SB interrupt vector: enable: I2C1_ITR.ITEVTEN, pending: I2C1_SR1.SB, priority: ITC_SPR8.VECT29SPR +#define _I2C_STOPF_VECTOR_ 29 ///< I2C_STOPF interrupt vector: enable: I2C1_ITR.ITEVTEN, pending: I2C1_SR1.STOPF, priority: ITC_SPR8.VECT29SPR +#define _I2C_TXE_VECTOR_ 29 ///< I2C_TXE interrupt vector: enable: I2C1_ITR.ITBUFEN, pending: I2C1_SR1.TXE, priority: ITC_SPR8.VECT29SPR +#define _I2C_WUFH_VECTOR_ 29 ///< I2C_WUFH interrupt vector: enable: I2C1_ITR.ITEVTEN, pending: I2C1_SR2.WUFH, priority: ITC_SPR8.VECT29SPR + + +/*------------------------------------------------------------------------- + DEFINITION OF STM8 PERIPHERAL REGISTERS +-------------------------------------------------------------------------*/ + +//------------------------ +// Module ADC1 +//------------------------ + +/** struct containing ADC1 module registers */ +typedef struct { + + /** ADC1 configuration register 1 (CR1 at 0x5340) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS ADON : 1; // bit 0 + BITS START : 1; // bit 1 + BITS CONT : 1; // bit 2 + BITS EOCIE : 1; // bit 3 + BITS AWDIE : 1; // bit 4 + BITS RES : 2; // bits 5-6 + BITS OVERIE : 1; // bit 7 + }; // CR1 bitfield + + /// register _ADC1_CR1 reset value + #define sfr_ADC1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** ADC1 configuration register 2 (CR2 at 0x5341) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SMTP1 : 3; // bits 0-2 + BITS EXTSEL0 : 1; // bit 3 + BITS EXTSEL1 : 1; // bit 4 + BITS TRIG_EDGE0 : 1; // bit 5 + BITS TRIG_EDGE1 : 1; // bit 6 + BITS PRESC : 1; // bit 7 + }; // CR2 bitfield + + /// register _ADC1_CR2 reset value + #define sfr_ADC1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** ADC1 configuration register 3 (CR3 at 0x5342) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS CHSEL : 5; // bits 0-4 + BITS SMTP2 : 3; // bits 5-7 + }; // CR3 bitfield + + /// register _ADC1_CR3 reset value + #define sfr_ADC1_CR3_RESET_VALUE ((uint8_t) 0x1F) + + } CR3; + + + /** ADC1 status register (SR at 0x5343) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS EOC : 1; // bit 0 + BITS AWD : 1; // bit 1 + BITS OVER : 1; // bit 2 + BITS : 5; // 5 bits + }; // SR bitfield + + /// register _ADC1_SR reset value + #define sfr_ADC1_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + + + /** ADC1 data register high (DRH at 0x5344) */ + union { + + /// bytewise access to DRH + uint8_t byte; + + /// bitwise access to register DRH + struct { + BITS CONV_DATA8 : 1; // bit 0 + BITS CONV_DATA9 : 1; // bit 1 + BITS CONV_DATA10 : 1; // bit 2 + BITS CONV_DATA11 : 1; // bit 3 + BITS : 4; // 4 bits + }; // DRH bitfield + + /// register _ADC1_DRH reset value + #define sfr_ADC1_DRH_RESET_VALUE ((uint8_t) 0x00) + + } DRH; + + + /** ADC1 data register low (DRL at 0x5345) */ + union { + + /// bytewise access to DRL + uint8_t byte; + + /// bitwise access to register DRL + struct { + BITS CONV_DATA0 : 1; // bit 0 + BITS CONV_DATA1 : 1; // bit 1 + BITS CONV_DATA2 : 1; // bit 2 + BITS CONV_DATA3 : 1; // bit 3 + BITS CONV_DATA4 : 1; // bit 4 + BITS CONV_DATA5 : 1; // bit 5 + BITS CONV_DATA6 : 1; // bit 6 + BITS CONV_DATA7 : 1; // bit 7 + }; // DRL bitfield + + /// register _ADC1_DRL reset value + #define sfr_ADC1_DRL_RESET_VALUE ((uint8_t) 0x00) + + } DRL; + + + /** ADC1 high threshold register high (HTRH at 0x5346) */ + union { + + /// bytewise access to HTRH + uint8_t byte; + + /// bitwise access to register HTRH + struct { + BITS HT8 : 1; // bit 0 + BITS HT9 : 1; // bit 1 + BITS HT10 : 1; // bit 2 + BITS HT11 : 1; // bit 3 + BITS : 4; // 4 bits + }; // HTRH bitfield + + /// register _ADC1_HTRH reset value + #define sfr_ADC1_HTRH_RESET_VALUE ((uint8_t) 0x0F) + + } HTRH; + + + /** ADC1 high threshold register low (HTRL at 0x5347) */ + union { + + /// bytewise access to HTRL + uint8_t byte; + + /// bitwise access to register HTRL + struct { + BITS HT0 : 1; // bit 0 + BITS HT1 : 1; // bit 1 + BITS HT2 : 1; // bit 2 + BITS HT3 : 1; // bit 3 + BITS HT4 : 1; // bit 4 + BITS HT5 : 1; // bit 5 + BITS HT6 : 1; // bit 6 + BITS HT7 : 1; // bit 7 + }; // HTRL bitfield + + /// register _ADC1_HTRL reset value + #define sfr_ADC1_HTRL_RESET_VALUE ((uint8_t) 0xFF) + + } HTRL; + + + /** ADC1 low threshold register high (LTRH at 0x5348) */ + union { + + /// bytewise access to LTRH + uint8_t byte; + + /// bitwise access to register LTRH + struct { + BITS LT8 : 1; // bit 0 + BITS LT9 : 1; // bit 1 + BITS LT10 : 1; // bit 2 + BITS LT11 : 1; // bit 3 + BITS : 4; // 4 bits + }; // LTRH bitfield + + /// register _ADC1_LTRH reset value + #define sfr_ADC1_LTRH_RESET_VALUE ((uint8_t) 0x00) + + } LTRH; + + + /** ADC1 low threshold register low (LTRL at 0x5349) */ + union { + + /// bytewise access to LTRL + uint8_t byte; + + /// bitwise access to register LTRL + struct { + BITS LT0 : 1; // bit 0 + BITS LT1 : 1; // bit 1 + BITS LT2 : 1; // bit 2 + BITS LT3 : 1; // bit 3 + BITS LT4 : 1; // bit 4 + BITS LT5 : 1; // bit 5 + BITS LT6 : 1; // bit 6 + BITS LT7 : 1; // bit 7 + }; // LTRL bitfield + + /// register _ADC1_LTRL reset value + #define sfr_ADC1_LTRL_RESET_VALUE ((uint8_t) 0x00) + + } LTRL; + + + /** ADC1 channel sequence 1 register (SQR1 at 0x534a) */ + union { + + /// bytewise access to SQR1 + uint8_t byte; + + /// bitwise access to register SQR1 + struct { + BITS CHSEL_S24 : 1; // bit 0 + BITS CHSEL_S25 : 1; // bit 1 + BITS CHSEL_S26 : 1; // bit 2 + BITS CHSEL_S27 : 1; // bit 3 + BITS CHSEL_S28 : 1; // bit 4 + BITS CHSEL_S29 : 1; // bit 5 + BITS : 1; // 1 bit + BITS DMAOFF : 1; // bit 7 + }; // SQR1 bitfield + + /// register _ADC1_SQR1 reset value + #define sfr_ADC1_SQR1_RESET_VALUE ((uint8_t) 0x00) + + } SQR1; + + + /** ADC1 channel sequence 2 register (SQR2 at 0x534b) */ + union { + + /// bytewise access to SQR2 + uint8_t byte; + + /// bitwise access to register SQR2 + struct { + BITS CHSEL_S16 : 1; // bit 0 + BITS CHSEL_S17 : 1; // bit 1 + BITS CHSEL_S18 : 1; // bit 2 + BITS CHSEL_S19 : 1; // bit 3 + BITS CHSEL_S20 : 1; // bit 4 + BITS CHSEL_S21 : 1; // bit 5 + BITS CHSEL_S22 : 1; // bit 6 + BITS CHSEL_S23 : 1; // bit 7 + }; // SQR2 bitfield + + /// register _ADC1_SQR2 reset value + #define sfr_ADC1_SQR2_RESET_VALUE ((uint8_t) 0x00) + + } SQR2; + + + /** ADC1 channel sequence 3 register (SQR3 at 0x534c) */ + union { + + /// bytewise access to SQR3 + uint8_t byte; + + /// bitwise access to register SQR3 + struct { + BITS CHSEL_S8 : 1; // bit 0 + BITS CHSEL_S9 : 1; // bit 1 + BITS CHSEL_S10 : 1; // bit 2 + BITS CHSEL_S11 : 1; // bit 3 + BITS CHSEL_S12 : 1; // bit 4 + BITS CHSEL_S13 : 1; // bit 5 + BITS CHSEL_S14 : 1; // bit 6 + BITS CHSEL_S15 : 1; // bit 7 + }; // SQR3 bitfield + + /// register _ADC1_SQR3 reset value + #define sfr_ADC1_SQR3_RESET_VALUE ((uint8_t) 0x00) + + } SQR3; + + + /** ADC1 channel sequence 4 register (SQR4 at 0x534d) */ + union { + + /// bytewise access to SQR4 + uint8_t byte; + + /// bitwise access to register SQR4 + struct { + BITS CHSEL_S0 : 1; // bit 0 + BITS CHSEL_S1 : 1; // bit 1 + BITS CHSEL_S2 : 1; // bit 2 + BITS CHSEL_S3 : 1; // bit 3 + BITS CHSEL_S4 : 1; // bit 4 + BITS CHSEL_S5 : 1; // bit 5 + BITS CHSEL_S6 : 1; // bit 6 + BITS CHSEL_S7 : 1; // bit 7 + }; // SQR4 bitfield + + /// register _ADC1_SQR4 reset value + #define sfr_ADC1_SQR4_RESET_VALUE ((uint8_t) 0x00) + + } SQR4; + + + /** ADC1 trigger disable 1 (TRIGR1 at 0x534e) */ + union { + + /// bytewise access to TRIGR1 + uint8_t byte; + + /// bitwise access to register TRIGR1 + struct { + BITS TRIG24 : 1; // bit 0 + BITS TRIG25 : 1; // bit 1 + BITS TRIG26 : 1; // bit 2 + BITS TRIG27 : 1; // bit 3 + BITS VREFINTON : 1; // bit 4 + BITS TSON : 1; // bit 5 + BITS : 2; // 2 bits + }; // TRIGR1 bitfield + + /// register _ADC1_TRIGR1 reset value + #define sfr_ADC1_TRIGR1_RESET_VALUE ((uint8_t) 0x00) + + } TRIGR1; + + + /** ADC1 trigger disable 2 (TRIGR2 at 0x534f) */ + union { + + /// bytewise access to TRIGR2 + uint8_t byte; + + /// bitwise access to register TRIGR2 + struct { + BITS TRIG16 : 1; // bit 0 + BITS TRIG17 : 1; // bit 1 + BITS TRIG18 : 1; // bit 2 + BITS TRIG19 : 1; // bit 3 + BITS TRIG20 : 1; // bit 4 + BITS TRIG21 : 1; // bit 5 + BITS TRIG22 : 1; // bit 6 + BITS TRIG23 : 1; // bit 7 + }; // TRIGR2 bitfield + + /// register _ADC1_TRIGR2 reset value + #define sfr_ADC1_TRIGR2_RESET_VALUE ((uint8_t) 0x00) + + } TRIGR2; + + + /** ADC1 trigger disable 3 (TRIGR3 at 0x5350) */ + union { + + /// bytewise access to TRIGR3 + uint8_t byte; + + /// bitwise access to register TRIGR3 + struct { + BITS TRIG8 : 1; // bit 0 + BITS TRIG9 : 1; // bit 1 + BITS TRIG10 : 1; // bit 2 + BITS TRIG11 : 1; // bit 3 + BITS TRIG12 : 1; // bit 4 + BITS TRIG13 : 1; // bit 5 + BITS TRIG14 : 1; // bit 6 + BITS TRIG15 : 1; // bit 7 + }; // TRIGR3 bitfield + + /// register _ADC1_TRIGR3 reset value + #define sfr_ADC1_TRIGR3_RESET_VALUE ((uint8_t) 0x00) + + } TRIGR3; + + + /** ADC1 trigger disable 4 (TRIGR4 at 0x5351) */ + union { + + /// bytewise access to TRIGR4 + uint8_t byte; + + /// bitwise access to register TRIGR4 + struct { + BITS TRIG0 : 1; // bit 0 + BITS TRIG1 : 1; // bit 1 + BITS TRIG2 : 1; // bit 2 + BITS TRIG3 : 1; // bit 3 + BITS TRIG4 : 1; // bit 4 + BITS TRIG5 : 1; // bit 5 + BITS TRIG6 : 1; // bit 6 + BITS TRIG7 : 1; // bit 7 + }; // TRIGR4 bitfield + + /// register _ADC1_TRIGR4 reset value + #define sfr_ADC1_TRIGR4_RESET_VALUE ((uint8_t) 0x00) + + } TRIGR4; + +} ADC1_t; + +/// access to ADC1 SFR registers +#define sfr_ADC1 (*((ADC1_t*) 0x5340)) + + +//------------------------ +// Module BEEP +//------------------------ + +/** struct containing BEEP module registers */ +typedef struct { + + /** BEEP control/status register 1 (CSR1 at 0x50f0) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// bitwise access to register CSR1 + struct { + BITS MSR : 1; // bit 0 + BITS : 7; // 7 bits + }; // CSR1 bitfield + + /// register _BEEP_CSR1 reset value + #define sfr_BEEP_CSR1_RESET_VALUE ((uint8_t) 0x00) + + } CSR1; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** BEEP control/status register 2 (CSR2 at 0x50f3) */ + union { + + /// bytewise access to CSR2 + uint8_t byte; + + /// bitwise access to register CSR2 + struct { + BITS BEEPDIV : 5; // bits 0-4 + BITS BEEPEN : 1; // bit 5 + BITS BEEPSEL : 2; // bits 6-7 + }; // CSR2 bitfield + + /// register _BEEP_CSR2 reset value + #define sfr_BEEP_CSR2_RESET_VALUE ((uint8_t) 0x1F) + + } CSR2; + +} BEEP_t; + +/// access to BEEP SFR registers +#define sfr_BEEP (*((BEEP_t*) 0x50f0)) + + +//------------------------ +// Module CLK +//------------------------ + +/** struct containing CLK module registers */ +typedef struct { + + /** Clock master divider register (CKDIVR at 0x50c0) */ + union { + + /// bytewise access to CKDIVR + uint8_t byte; + + /// bitwise access to register CKDIVR + struct { + BITS CKM : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // CKDIVR bitfield + + /// register _CLK_CKDIVR reset value + #define sfr_CLK_CKDIVR_RESET_VALUE ((uint8_t) 0x03) + + } CKDIVR; + + + /** Clock RTC register (CRTCR at 0x50c1) */ + union { + + /// bytewise access to CRTCR + uint8_t byte; + + /// bitwise access to register CRTCR + struct { + BITS RTCSWBSY : 1; // bit 0 + BITS RTCSEL0 : 1; // bit 1 + BITS RTCSEL1 : 1; // bit 2 + BITS RTCSEL2 : 1; // bit 3 + BITS RTCSEL3 : 1; // bit 4 + BITS RTCDIV0 : 1; // bit 5 + BITS RTCDIV1 : 1; // bit 6 + BITS RTCDIV2 : 1; // bit 7 + }; // CRTCR bitfield + + /// register _CLK_CRTCR reset value + #define sfr_CLK_CRTCR_RESET_VALUE ((uint8_t) 0x00) + + } CRTCR; + + + /** Internal clock control register (ICKCR at 0x50c2) */ + union { + + /// bytewise access to ICKCR + uint8_t byte; + + /// bitwise access to register ICKCR + struct { + BITS HSION : 1; // bit 0 + BITS HSIRDY : 1; // bit 1 + BITS LSION : 1; // bit 2 + BITS LSIRDY : 1; // bit 3 + BITS SAHALT : 1; // bit 4 + BITS FHWU : 1; // bit 5 + BITS BEEPAHALT : 1; // bit 6 + BITS : 1; // 1 bit + }; // ICKCR bitfield + + /// register _CLK_ICKCR reset value + #define sfr_CLK_ICKCR_RESET_VALUE ((uint8_t) 0x11) + + } ICKCR; + + + /** Peripheral clock gating register 1 (PCKENR1 at 0x50c3) */ + union { + + /// bytewise access to PCKENR1 + uint8_t byte; + + /// bitwise access to register PCKENR1 + struct { + BITS PCKEN10 : 1; // bit 0 + BITS PCKEN11 : 1; // bit 1 + BITS PCKEN12 : 1; // bit 2 + BITS PCKEN13 : 1; // bit 3 + BITS PCKEN14 : 1; // bit 4 + BITS PCKEN15 : 1; // bit 5 + BITS PCKEN16 : 1; // bit 6 + BITS PCKEN17 : 1; // bit 7 + }; // PCKENR1 bitfield + + /// register _CLK_PCKENR1 reset value + #define sfr_CLK_PCKENR1_RESET_VALUE ((uint8_t) 0x00) + + } PCKENR1; + + + /** Peripheral clock gating register 2 (PCKENR2 at 0x50c4) */ + union { + + /// bytewise access to PCKENR2 + uint8_t byte; + + /// bitwise access to register PCKENR2 + struct { + BITS PCKEN20 : 1; // bit 0 + BITS PCKEN21 : 1; // bit 1 + BITS PCKEN22 : 1; // bit 2 + BITS PCKEN23 : 1; // bit 3 + BITS PCKEN24 : 1; // bit 4 + BITS PCKEN25 : 1; // bit 5 + BITS : 1; // 1 bit + BITS PCKEN27 : 1; // bit 7 + }; // PCKENR2 bitfield + + /// register _CLK_PCKENR2 reset value + #define sfr_CLK_PCKENR2_RESET_VALUE ((uint8_t) 0x80) + + } PCKENR2; + + + /** Configurable clock control register (CCOR at 0x50c5) */ + union { + + /// bytewise access to CCOR + uint8_t byte; + + /// bitwise access to register CCOR + struct { + BITS CCOSWBSY : 1; // bit 0 + BITS CCOSEL : 4; // bits 1-4 + BITS CCODIV : 3; // bits 5-7 + }; // CCOR bitfield + + /// register _CLK_CCOR reset value + #define sfr_CLK_CCOR_RESET_VALUE ((uint8_t) 0x00) + + } CCOR; + + + /** External clock control register (ECKR at 0x50c6) */ + union { + + /// bytewise access to ECKR + uint8_t byte; + + /// bitwise access to register ECKR + struct { + BITS HSEON : 1; // bit 0 + BITS HSERDY : 1; // bit 1 + BITS LSEON : 1; // bit 2 + BITS LSERDY : 1; // bit 3 + BITS HSEBYP : 1; // bit 4 + BITS LSEBYP : 1; // bit 5 + BITS : 2; // 2 bits + }; // ECKR bitfield + + /// register _CLK_ECKR reset value + #define sfr_CLK_ECKR_RESET_VALUE ((uint8_t) 0x00) + + } ECKR; + + + /** Clock master status register (SCSR at 0x50c7) */ + union { + + /// bytewise access to SCSR + uint8_t byte; + + /// bitwise access to register SCSR + struct { + BITS CKM : 8; // bits 0-7 + }; // SCSR bitfield + + /// register _CLK_SCSR reset value + #define sfr_CLK_SCSR_RESET_VALUE ((uint8_t) 0x01) + + } SCSR; + + + /** Clock master switch register (SWR at 0x50c8) */ + union { + + /// bytewise access to SWR + uint8_t byte; + + /// bitwise access to register SWR + struct { + BITS SWI : 8; // bits 0-7 + }; // SWR bitfield + + /// register _CLK_SWR reset value + #define sfr_CLK_SWR_RESET_VALUE ((uint8_t) 0x01) + + } SWR; + + + /** Clock switch control register (SWCR at 0x50c9) */ + union { + + /// bytewise access to SWCR + uint8_t byte; + + /// bitwise access to register SWCR + struct { + BITS SWBSY : 1; // bit 0 + BITS SWEN : 1; // bit 1 + BITS SWIEN : 1; // bit 2 + BITS SWIF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SWCR bitfield + + /// register _CLK_SWCR reset value + #define sfr_CLK_SWCR_RESET_VALUE ((uint8_t) 0x00) + + } SWCR; + + + /** Clock security system register (CSSR at 0x50ca) */ + union { + + /// bytewise access to CSSR + uint8_t byte; + + /// bitwise access to register CSSR + struct { + BITS CSSEN : 1; // bit 0 + BITS AUX : 1; // bit 1 + BITS CSSDIE : 1; // bit 2 + BITS CSSD : 1; // bit 3 + BITS CSSDGON : 1; // bit 4 + BITS : 3; // 3 bits + }; // CSSR bitfield + + /// register _CLK_CSSR reset value + #define sfr_CLK_CSSR_RESET_VALUE ((uint8_t) 0x00) + + } CSSR; + + + /** Clock BEEP register (CBEEPR at 0x50cb) */ + union { + + /// bytewise access to CBEEPR + uint8_t byte; + + /// bitwise access to register CBEEPR + struct { + BITS BEEPSWBSY : 1; // bit 0 + BITS CLKBEEPSEL0 : 1; // bit 1 + BITS CLKBEEPSEL1 : 1; // bit 2 + BITS : 5; // 5 bits + }; // CBEEPR bitfield + + /// register _CLK_CBEEPR reset value + #define sfr_CLK_CBEEPR_RESET_VALUE ((uint8_t) 0x00) + + } CBEEPR; + + + /** HSI calibration register (HSICALR at 0x50cc) */ + union { + + /// bytewise access to HSICALR + uint8_t byte; + + /// bitwise access to register HSICALR + struct { + BITS HSICAL : 8; // bits 0-7 + }; // HSICALR bitfield + + /// register _CLK_HSICALR reset value + #define sfr_CLK_HSICALR_RESET_VALUE ((uint8_t) 0x00) + + } HSICALR; + + + /** HSI clock calibration trimming register (HSITRIMR at 0x50cd) */ + union { + + /// bytewise access to HSITRIMR + uint8_t byte; + + /// bitwise access to register HSITRIMR + struct { + BITS HSITRIM : 8; // bits 0-7 + }; // HSITRIMR bitfield + + /// register _CLK_HSITRIMR reset value + #define sfr_CLK_HSITRIMR_RESET_VALUE ((uint8_t) 0x00) + + } HSITRIMR; + + + /** HSI unlock register (HSIUNLCKR at 0x50ce) */ + union { + + /// bytewise access to HSIUNLCKR + uint8_t byte; + + /// bitwise access to register HSIUNLCKR + struct { + BITS HSIUNLCK : 8; // bits 0-7 + }; // HSIUNLCKR bitfield + + /// register _CLK_HSIUNLCKR reset value + #define sfr_CLK_HSIUNLCKR_RESET_VALUE ((uint8_t) 0x00) + + } HSIUNLCKR; + + + /** Main regulator control status register (REGCSR at 0x50cf) */ + union { + + /// bytewise access to REGCSR + uint8_t byte; + + /// bitwise access to register REGCSR + struct { + BITS REGREADY : 1; // bit 0 + BITS REGOFF : 1; // bit 1 + BITS HSIPD : 1; // bit 2 + BITS LSIPD : 1; // bit 3 + BITS HSEPD : 1; // bit 4 + BITS LSEPD : 1; // bit 5 + BITS EEBUSY : 1; // bit 6 + BITS EEREADY : 1; // bit 7 + }; // REGCSR bitfield + + /// register _CLK_REGCSR reset value + #define sfr_CLK_REGCSR_RESET_VALUE ((uint8_t) 0x38) + + } REGCSR; + +} CLK_t; + +/// access to CLK SFR registers +#define sfr_CLK (*((CLK_t*) 0x50c0)) + + +//------------------------ +// Module COMP +//------------------------ + +/** struct containing COMP module registers */ +typedef struct { + + /** Comparator control and status register 1 (CSR1 at 0x5440) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// bitwise access to register CSR1 + struct { + BITS CMP1 : 2; // bits 0-1 + BITS STE : 1; // bit 2 + BITS CMP1OUT : 1; // bit 3 + BITS EF1 : 1; // bit 4 + BITS IE1 : 1; // bit 5 + BITS : 2; // 2 bits + }; // CSR1 bitfield + + /// register _COMP_CSR1 reset value + #define sfr_COMP_CSR1_RESET_VALUE ((uint8_t) 0x00) + + } CSR1; + + + /** Comparator control and status register 2 (CSR2 at 0x5441) */ + union { + + /// bytewise access to CSR2 + uint8_t byte; + + /// bitwise access to register CSR2 + struct { + BITS CMP2 : 2; // bits 0-1 + BITS SPEED : 1; // bit 2 + BITS CMP2OUT : 1; // bit 3 + BITS EF2 : 1; // bit 4 + BITS IE2 : 1; // bit 5 + BITS : 2; // 2 bits + }; // CSR2 bitfield + + /// register _COMP_CSR2 reset value + #define sfr_COMP_CSR2_RESET_VALUE ((uint8_t) 0x00) + + } CSR2; + + + /** Comparator control and status register 3 (CSR3 at 0x5442) */ + union { + + /// bytewise access to CSR3 + uint8_t byte; + + /// bitwise access to register CSR3 + struct { + BITS VREFOUTEN : 1; // bit 0 + BITS WNDWE : 1; // bit 1 + BITS VREFEN : 1; // bit 2 + BITS INSEL : 3; // bits 3-5 + BITS OUTSEL : 2; // bits 6-7 + }; // CSR3 bitfield + + /// register _COMP_CSR3 reset value + #define sfr_COMP_CSR3_RESET_VALUE ((uint8_t) 0x00) + + } CSR3; + + + /** Comparator control and status register 4 (CSR4 at 0x5443) */ + union { + + /// bytewise access to CSR4 + uint8_t byte; + + /// bitwise access to register CSR4 + struct { + BITS INVTRIG : 3; // bits 0-2 + BITS NINVTRIG : 3; // bits 3-5 + BITS : 2; // 2 bits + }; // CSR4 bitfield + + /// register _COMP_CSR4 reset value + #define sfr_COMP_CSR4_RESET_VALUE ((uint8_t) 0x00) + + } CSR4; + + + /** Comparator control and status register 5 (CSR5 at 0x5444) */ + union { + + /// bytewise access to CSR5 + uint8_t byte; + + /// bitwise access to register CSR5 + struct { + BITS VREFTRIG : 3; // bits 0-2 + BITS DACTRIG : 3; // bits 3-5 + BITS : 2; // 2 bits + }; // CSR5 bitfield + + /// register _COMP_CSR5 reset value + #define sfr_COMP_CSR5_RESET_VALUE ((uint8_t) 0x00) + + } CSR5; + +} COMP_t; + +/// access to COMP SFR registers +#define sfr_COMP (*((COMP_t*) 0x5440)) + + +//------------------------ +// Module CPU +//------------------------ + +/** struct containing CPU module registers */ +typedef struct { + + /** Accumulator (A at 0x7f00) */ + union { + + /// bytewise access to A + uint8_t byte; + + /// skip bitwise access to register A + + /// register _CPU_A reset value + #define sfr_CPU_A_RESET_VALUE ((uint8_t) 0x00) + + } A; + + + /** Program counter extended (PCE at 0x7f01) */ + union { + + /// bytewise access to PCE + uint8_t byte; + + /// skip bitwise access to register PCE + + /// register _CPU_PCE reset value + #define sfr_CPU_PCE_RESET_VALUE ((uint8_t) 0x00) + + } PCE; + + + /** Program counter high (PCH at 0x7f02) */ + union { + + /// bytewise access to PCH + uint8_t byte; + + /// skip bitwise access to register PCH + + /// register _CPU_PCH reset value + #define sfr_CPU_PCH_RESET_VALUE ((uint8_t) 0x00) + + } PCH; + + + /** Program counter low (PCL at 0x7f03) */ + union { + + /// bytewise access to PCL + uint8_t byte; + + /// skip bitwise access to register PCL + + /// register _CPU_PCL reset value + #define sfr_CPU_PCL_RESET_VALUE ((uint8_t) 0x00) + + } PCL; + + + /** X index register high (XH at 0x7f04) */ + union { + + /// bytewise access to XH + uint8_t byte; + + /// skip bitwise access to register XH + + /// register _CPU_XH reset value + #define sfr_CPU_XH_RESET_VALUE ((uint8_t) 0x00) + + } XH; + + + /** X index register low (XL at 0x7f05) */ + union { + + /// bytewise access to XL + uint8_t byte; + + /// skip bitwise access to register XL + + /// register _CPU_XL reset value + #define sfr_CPU_XL_RESET_VALUE ((uint8_t) 0x00) + + } XL; + + + /** Y index register high (YH at 0x7f06) */ + union { + + /// bytewise access to YH + uint8_t byte; + + /// skip bitwise access to register YH + + /// register _CPU_YH reset value + #define sfr_CPU_YH_RESET_VALUE ((uint8_t) 0x00) + + } YH; + + + /** Y index register low (YL at 0x7f07) */ + union { + + /// bytewise access to YL + uint8_t byte; + + /// skip bitwise access to register YL + + /// register _CPU_YL reset value + #define sfr_CPU_YL_RESET_VALUE ((uint8_t) 0x00) + + } YL; + + + /** Stack pointer high (SPH at 0x7f08) */ + union { + + /// bytewise access to SPH + uint8_t byte; + + /// skip bitwise access to register SPH + + /// register _CPU_SPH reset value + #define sfr_CPU_SPH_RESET_VALUE ((uint8_t) 0x03) + + } SPH; + + + /** Stack pointer low (SPL at 0x7f09) */ + union { + + /// bytewise access to SPL + uint8_t byte; + + /// skip bitwise access to register SPL + + /// register _CPU_SPL reset value + #define sfr_CPU_SPL_RESET_VALUE ((uint8_t) 0xFF) + + } SPL; + + + /** Condition code register (CCR at 0x7f0a) */ + union { + + /// bytewise access to CCR + uint8_t byte; + + /// bitwise access to register CCR + struct { + BITS C : 1; // bit 0 + BITS Z : 1; // bit 1 + BITS N : 1; // bit 2 + BITS I0 : 1; // bit 3 + BITS H : 1; // bit 4 + BITS I1 : 1; // bit 5 + BITS : 1; // 1 bit + BITS V : 1; // bit 7 + }; // CCR bitfield + + /// register _CPU_CCR reset value + #define sfr_CPU_CCR_RESET_VALUE ((uint8_t) 0x28) + + } CCR; + + + /// Reserved register (85B) + uint8_t Reserved_1[85]; + + + /** Global configuration register (CFG_GCR at 0x7f60) */ + union { + + /// bytewise access to CFG_GCR + uint8_t byte; + + /// bitwise access to register CFG_GCR + struct { + BITS SWD : 1; // bit 0 + BITS AL : 1; // bit 1 + BITS : 6; // 6 bits + }; // CFG_GCR bitfield + + /// register _CPU_CFG_GCR reset value + #define sfr_CPU_CFG_GCR_RESET_VALUE ((uint8_t) 0x00) + + } CFG_GCR; + +} CPU_t; + +/// access to CPU SFR registers +#define sfr_CPU (*((CPU_t*) 0x7f00)) + + +//------------------------ +// Module DAC +//------------------------ + +/** struct containing DAC module registers */ +typedef struct { + + /** DAC control register 1 (CR1 at 0x5380) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS EN : 1; // bit 0 + BITS BOFF : 1; // bit 1 + BITS TEN : 1; // bit 2 + BITS TSEL : 3; // bits 3-5 + BITS : 2; // 2 bits + }; // CR1 bitfield + + /// register _DAC_CR1 reset value + #define sfr_DAC_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** DAC control register 2 (CR2 at 0x5381) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS : 4; // 4 bits + BITS DMAEN : 1; // bit 4 + BITS DMAUDRIE : 1; // bit 5 + BITS : 2; // 2 bits + }; // CR2 bitfield + + /// register _DAC_CR2 reset value + #define sfr_DAC_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** DAC software trigger register (SWTRIGR at 0x5384) */ + union { + + /// bytewise access to SWTRIGR + uint8_t byte; + + /// bitwise access to register SWTRIGR + struct { + BITS SWTRIG : 1; // bit 0 + BITS : 7; // 7 bits + }; // SWTRIGR bitfield + + /// register _DAC_SWTRIGR reset value + #define sfr_DAC_SWTRIGR_RESET_VALUE ((uint8_t) 0x00) + + } SWTRIGR; + + + /** DAC status register (SR at 0x5385) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS DMAUDR : 1; // bit 0 + BITS : 7; // 7 bits + }; // SR bitfield + + /// register _DAC_SR reset value + #define sfr_DAC_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + + + /// Reserved register (2B) + uint8_t Reserved_2[2]; + + + /** DAC right aligned data holding register high (RDHRH at 0x5388) */ + union { + + /// bytewise access to RDHRH + uint8_t byte; + + /// bitwise access to register RDHRH + struct { + BITS RDHRH : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // RDHRH bitfield + + /// register _DAC_RDHRH reset value + #define sfr_DAC_RDHRH_RESET_VALUE ((uint8_t) 0x00) + + } RDHRH; + + + /** DAC right aligned data holding register low (RDHRL at 0x5389) */ + union { + + /// bytewise access to RDHRL + uint8_t byte; + + /// bitwise access to register RDHRL + struct { + BITS RDHRL : 8; // bits 0-7 + }; // RDHRL bitfield + + /// register _DAC_RDHRL reset value + #define sfr_DAC_RDHRL_RESET_VALUE ((uint8_t) 0x00) + + } RDHRL; + + + /// Reserved register (2B) + uint8_t Reserved_3[2]; + + + /** DAC left aligned data holding register high (LDHRH at 0x538c) */ + union { + + /// bytewise access to LDHRH + uint8_t byte; + + /// bitwise access to register LDHRH + struct { + BITS LDHRH : 8; // bits 0-7 + }; // LDHRH bitfield + + /// register _DAC_LDHRH reset value + #define sfr_DAC_LDHRH_RESET_VALUE ((uint8_t) 0x00) + + } LDHRH; + + + /** DAC left aligned data holding register low (LDHRL at 0x538d) */ + union { + + /// bytewise access to LDHRL + uint8_t byte; + + /// bitwise access to register LDHRL + struct { + BITS : 4; // 4 bits + BITS LDHRL : 4; // bits 4-7 + }; // LDHRL bitfield + + /// register _DAC_LDHRL reset value + #define sfr_DAC_LDHRL_RESET_VALUE ((uint8_t) 0x00) + + } LDHRL; + + + /// Reserved register (2B) + uint8_t Reserved_4[2]; + + + /** DAC 8-bit data holding register (DHR8 at 0x5390) */ + union { + + /// bytewise access to DHR8 + uint8_t byte; + + /// bitwise access to register DHR8 + struct { + BITS DHR8 : 8; // bits 0-7 + }; // DHR8 bitfield + + /// register _DAC_DHR8 reset value + #define sfr_DAC_DHR8_RESET_VALUE ((uint8_t) 0x00) + + } DHR8; + + + /// Reserved register (27B) + uint8_t Reserved_5[27]; + + + /** DAC data output register high (DORH at 0x53ac) */ + union { + + /// bytewise access to DORH + uint8_t byte; + + /// bitwise access to register DORH + struct { + BITS DORH : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // DORH bitfield + + /// register _DAC_DORH reset value + #define sfr_DAC_DORH_RESET_VALUE ((uint8_t) 0x00) + + } DORH; + + + /** DAC data output register low (DORL at 0x53ad) */ + union { + + /// bytewise access to DORL + uint8_t byte; + + /// bitwise access to register DORL + struct { + BITS DORL : 8; // bits 0-7 + }; // DORL bitfield + + /// register _DAC_DORL reset value + #define sfr_DAC_DORL_RESET_VALUE ((uint8_t) 0x00) + + } DORL; + +} DAC_t; + +/// access to DAC SFR registers +#define sfr_DAC (*((DAC_t*) 0x5380)) + + +//------------------------ +// Module DM +//------------------------ + +/** struct containing DM module registers */ +typedef struct { + + /** DM breakpoint 1 register extended byte (BK1RE at 0x7f90) */ + union { + + /// bytewise access to BK1RE + uint8_t byte; + + /// skip bitwise access to register BK1RE + + /// register _DM_BK1RE reset value + #define sfr_DM_BK1RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RE; + + + /** DM breakpoint 1 register high byte (BK1RH at 0x7f91) */ + union { + + /// bytewise access to BK1RH + uint8_t byte; + + /// skip bitwise access to register BK1RH + + /// register _DM_BK1RH reset value + #define sfr_DM_BK1RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RH; + + + /** DM breakpoint 1 register low byte (BK1RL at 0x7f92) */ + union { + + /// bytewise access to BK1RL + uint8_t byte; + + /// skip bitwise access to register BK1RL + + /// register _DM_BK1RL reset value + #define sfr_DM_BK1RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RL; + + + /** DM breakpoint 2 register extended byte (BK2RE at 0x7f93) */ + union { + + /// bytewise access to BK2RE + uint8_t byte; + + /// skip bitwise access to register BK2RE + + /// register _DM_BK2RE reset value + #define sfr_DM_BK2RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RE; + + + /** DM breakpoint 2 register high byte (BK2RH at 0x7f94) */ + union { + + /// bytewise access to BK2RH + uint8_t byte; + + /// skip bitwise access to register BK2RH + + /// register _DM_BK2RH reset value + #define sfr_DM_BK2RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RH; + + + /** DM breakpoint 2 register low byte (BK2RL at 0x7f95) */ + union { + + /// bytewise access to BK2RL + uint8_t byte; + + /// skip bitwise access to register BK2RL + + /// register _DM_BK2RL reset value + #define sfr_DM_BK2RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RL; + + + /** DM Debug module control register 1 (CR1 at 0x7f96) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// skip bitwise access to register CR1 + + /// register _DM_CR1 reset value + #define sfr_DM_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** DM Debug module control register 2 (CR2 at 0x7f97) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// skip bitwise access to register CR2 + + /// register _DM_CR2 reset value + #define sfr_DM_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** DM Debug module control/status register 1 (CSR1 at 0x7f98) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// skip bitwise access to register CSR1 + + /// register _DM_CSR1 reset value + #define sfr_DM_CSR1_RESET_VALUE ((uint8_t) 0x10) + + } CSR1; + + + /** DM Debug module control/status register 2 (CSR2 at 0x7f99) */ + union { + + /// bytewise access to CSR2 + uint8_t byte; + + /// skip bitwise access to register CSR2 + + /// register _DM_CSR2 reset value + #define sfr_DM_CSR2_RESET_VALUE ((uint8_t) 0x00) + + } CSR2; + + + /** DM enable function register (ENFCTR at 0x7f9a) */ + union { + + /// bytewise access to ENFCTR + uint8_t byte; + + /// skip bitwise access to register ENFCTR + + /// register _DM_ENFCTR reset value + #define sfr_DM_ENFCTR_RESET_VALUE ((uint8_t) 0xFF) + + } ENFCTR; + +} DM_t; + +/// access to DM SFR registers +#define sfr_DM (*((DM_t*) 0x7f90)) + + +//------------------------ +// Module DMA1 +//------------------------ + +/** struct containing DMA1 module registers */ +typedef struct { + + /** DMA1 global configuration & status register (GCSR at 0x5070) */ + union { + + /// bytewise access to GCSR + uint8_t byte; + + /// bitwise access to register GCSR + struct { + BITS GEN : 1; // bit 0 + BITS GB : 1; // bit 1 + BITS TO : 6; // bits 2-7 + }; // GCSR bitfield + + /// register _DMA1_GCSR reset value + #define sfr_DMA1_GCSR_RESET_VALUE ((uint8_t) 0xFC) + + } GCSR; + + + /** DMA1 global interrupt register 1 (GIR1 at 0x5071) */ + union { + + /// bytewise access to GIR1 + uint8_t byte; + + /// bitwise access to register GIR1 + struct { + BITS IFC0 : 1; // bit 0 + BITS IFC1 : 1; // bit 1 + BITS IFC2 : 1; // bit 2 + BITS IFC3 : 1; // bit 3 + BITS : 4; // 4 bits + }; // GIR1 bitfield + + /// register _DMA1_GIR1 reset value + #define sfr_DMA1_GIR1_RESET_VALUE ((uint8_t) 0x00) + + } GIR1; + + + /// Reserved register (3B) + uint8_t Reserved_1[3]; + + + /** DMA1 channel 0 configuration register (C0CR at 0x5075) */ + union { + + /// bytewise access to C0CR + uint8_t byte; + + /// bitwise access to register C0CR + struct { + BITS EN : 1; // bit 0 + BITS TCIE : 1; // bit 1 + BITS HTIE : 1; // bit 2 + BITS DIR : 1; // bit 3 + BITS CIRC : 1; // bit 4 + BITS MINCDEC : 1; // bit 5 + BITS : 2; // 2 bits + }; // C0CR bitfield + + /// register _DMA1_C0CR reset value + #define sfr_DMA1_C0CR_RESET_VALUE ((uint8_t) 0x00) + + } C0CR; + + + /** DMA1 channel 0 status (C0SPR at 0x5076) */ + union { + + /// bytewise access to C0SPR + uint8_t byte; + + /// bitwise access to register C0SPR + struct { + BITS : 1; // 1 bit + BITS TCIF : 1; // bit 1 + BITS HTIF : 1; // bit 2 + BITS TSIZE : 1; // bit 3 + BITS PL0 : 1; // bit 4 + BITS PL1 : 1; // bit 5 + BITS PEND : 1; // bit 6 + BITS BUSY : 1; // bit 7 + }; // C0SPR bitfield + + /// register _DMA1_C0SPR reset value + #define sfr_DMA1_C0SPR_RESET_VALUE ((uint8_t) 0x00) + + } C0SPR; + + + /** DMA1 number of data to transfer register (channel 0) (C0NDTR at 0x5077) */ + union { + + /// bytewise access to C0NDTR + uint8_t byte; + + /// bitwise access to register C0NDTR + struct { + BITS NDT0 : 1; // bit 0 + BITS NDT1 : 1; // bit 1 + BITS NDT2 : 1; // bit 2 + BITS NDT3 : 1; // bit 3 + BITS NDT4 : 1; // bit 4 + BITS NDT5 : 1; // bit 5 + BITS NDT6 : 1; // bit 6 + BITS NDT7 : 1; // bit 7 + }; // C0NDTR bitfield + + /// register _DMA1_C0NDTR reset value + #define sfr_DMA1_C0NDTR_RESET_VALUE ((uint8_t) 0x00) + + } C0NDTR; + + + /** DMA1 peripheral address high register (channel 0) (C0PARH at 0x5078) */ + union { + + /// bytewise access to C0PARH + uint8_t byte; + + /// bitwise access to register C0PARH + struct { + BITS PA8 : 1; // bit 0 + BITS PA9 : 1; // bit 1 + BITS PA10 : 1; // bit 2 + BITS PA11 : 1; // bit 3 + BITS PA12 : 1; // bit 4 + BITS PA13 : 1; // bit 5 + BITS PA14 : 1; // bit 6 + BITS PA15 : 1; // bit 7 + }; // C0PARH bitfield + + /// register _DMA1_C0PARH reset value + #define sfr_DMA1_C0PARH_RESET_VALUE ((uint8_t) 0x52) + + } C0PARH; + + + /** DMA1 peripheral address low register (channel 0) (C0PARL at 0x5079) */ + union { + + /// bytewise access to C0PARL + uint8_t byte; + + /// bitwise access to register C0PARL + struct { + BITS PA0 : 1; // bit 0 + BITS PA1 : 1; // bit 1 + BITS PA2 : 1; // bit 2 + BITS PA3 : 1; // bit 3 + BITS PA4 : 1; // bit 4 + BITS PA5 : 1; // bit 5 + BITS PA6 : 1; // bit 6 + BITS PA7 : 1; // bit 7 + }; // C0PARL bitfield + + /// register _DMA1_C0PARL reset value + #define sfr_DMA1_C0PARL_RESET_VALUE ((uint8_t) 0x00) + + } C0PARL; + + + /// Reserved register (1B) + uint8_t Reserved_2[1]; + + + /** DMA1 memory 0 address high register (channel 0) (C0M0ARH at 0x507b) */ + union { + + /// bytewise access to C0M0ARH + uint8_t byte; + + /// bitwise access to register C0M0ARH + struct { + BITS M0A8 : 1; // bit 0 + BITS M0A9 : 1; // bit 1 + BITS M0A10 : 1; // bit 2 + BITS M0A11 : 1; // bit 3 + BITS M0A12 : 1; // bit 4 + BITS M0A13 : 1; // bit 5 + BITS M0A14 : 1; // bit 6 + BITS M0A15 : 1; // bit 7 + }; // C0M0ARH bitfield + + /// register _DMA1_C0M0ARH reset value + #define sfr_DMA1_C0M0ARH_RESET_VALUE ((uint8_t) 0x00) + + } C0M0ARH; + + + /** DMA1 memory 0 address low register (channel 0) (C0M0ARL at 0x507c) */ + union { + + /// bytewise access to C0M0ARL + uint8_t byte; + + /// bitwise access to register C0M0ARL + struct { + BITS M0A0 : 1; // bit 0 + BITS M0A1 : 1; // bit 1 + BITS M0A2 : 1; // bit 2 + BITS M0A3 : 1; // bit 3 + BITS M0A4 : 1; // bit 4 + BITS M0A5 : 1; // bit 5 + BITS M0A6 : 1; // bit 6 + BITS M0A7 : 1; // bit 7 + }; // C0M0ARL bitfield + + /// register _DMA1_C0M0ARL reset value + #define sfr_DMA1_C0M0ARL_RESET_VALUE ((uint8_t) 0x00) + + } C0M0ARL; + + + /// Reserved register (2B) + uint8_t Reserved_3[2]; + + + /** DMA1 channel 1 configuration register (C1CR at 0x507f) */ + union { + + /// bytewise access to C1CR + uint8_t byte; + + /// bitwise access to register C1CR + struct { + BITS EN : 1; // bit 0 + BITS TCIE : 1; // bit 1 + BITS HTIE : 1; // bit 2 + BITS DIR : 1; // bit 3 + BITS CIRC : 1; // bit 4 + BITS MINCDEC : 1; // bit 5 + BITS : 2; // 2 bits + }; // C1CR bitfield + + /// register _DMA1_C1CR reset value + #define sfr_DMA1_C1CR_RESET_VALUE ((uint8_t) 0x00) + + } C1CR; + + + /** DMA1 channel 1 status (C1SPR at 0x5080) */ + union { + + /// bytewise access to C1SPR + uint8_t byte; + + /// bitwise access to register C1SPR + struct { + BITS : 1; // 1 bit + BITS TCIF : 1; // bit 1 + BITS HTIF : 1; // bit 2 + BITS TSIZE : 1; // bit 3 + BITS PL0 : 1; // bit 4 + BITS PL1 : 1; // bit 5 + BITS PEND : 1; // bit 6 + BITS BUSY : 1; // bit 7 + }; // C1SPR bitfield + + /// register _DMA1_C1SPR reset value + #define sfr_DMA1_C1SPR_RESET_VALUE ((uint8_t) 0x00) + + } C1SPR; + + + /** DMA1 number of data to transfer register (channel 1) (C1NDTR at 0x5081) */ + union { + + /// bytewise access to C1NDTR + uint8_t byte; + + /// bitwise access to register C1NDTR + struct { + BITS NDT0 : 1; // bit 0 + BITS NDT1 : 1; // bit 1 + BITS NDT2 : 1; // bit 2 + BITS NDT3 : 1; // bit 3 + BITS NDT4 : 1; // bit 4 + BITS NDT5 : 1; // bit 5 + BITS NDT6 : 1; // bit 6 + BITS NDT7 : 1; // bit 7 + }; // C1NDTR bitfield + + /// register _DMA1_C1NDTR reset value + #define sfr_DMA1_C1NDTR_RESET_VALUE ((uint8_t) 0x00) + + } C1NDTR; + + + /** DMA1 peripheral address high register (channel 1) (C1PARH at 0x5082) */ + union { + + /// bytewise access to C1PARH + uint8_t byte; + + /// bitwise access to register C1PARH + struct { + BITS PA8 : 1; // bit 0 + BITS PA9 : 1; // bit 1 + BITS PA10 : 1; // bit 2 + BITS PA11 : 1; // bit 3 + BITS PA12 : 1; // bit 4 + BITS PA13 : 1; // bit 5 + BITS PA14 : 1; // bit 6 + BITS PA15 : 1; // bit 7 + }; // C1PARH bitfield + + /// register _DMA1_C1PARH reset value + #define sfr_DMA1_C1PARH_RESET_VALUE ((uint8_t) 0x52) + + } C1PARH; + + + /** DMA1 peripheral address low register (channel 1) (C1PARL at 0x5083) */ + union { + + /// bytewise access to C1PARL + uint8_t byte; + + /// bitwise access to register C1PARL + struct { + BITS PA0 : 1; // bit 0 + BITS PA1 : 1; // bit 1 + BITS PA2 : 1; // bit 2 + BITS PA3 : 1; // bit 3 + BITS PA4 : 1; // bit 4 + BITS PA5 : 1; // bit 5 + BITS PA6 : 1; // bit 6 + BITS PA7 : 1; // bit 7 + }; // C1PARL bitfield + + /// register _DMA1_C1PARL reset value + #define sfr_DMA1_C1PARL_RESET_VALUE ((uint8_t) 0x00) + + } C1PARL; + + + /// Reserved register (1B) + uint8_t Reserved_4[1]; + + + /** DMA1 memory 0 address high register (channel 1) (C1M0ARH at 0x5085) */ + union { + + /// bytewise access to C1M0ARH + uint8_t byte; + + /// bitwise access to register C1M0ARH + struct { + BITS M0A8 : 1; // bit 0 + BITS M0A9 : 1; // bit 1 + BITS M0A10 : 1; // bit 2 + BITS M0A11 : 1; // bit 3 + BITS M0A12 : 1; // bit 4 + BITS M0A13 : 1; // bit 5 + BITS M0A14 : 1; // bit 6 + BITS M0A15 : 1; // bit 7 + }; // C1M0ARH bitfield + + /// register _DMA1_C1M0ARH reset value + #define sfr_DMA1_C1M0ARH_RESET_VALUE ((uint8_t) 0x00) + + } C1M0ARH; + + + /** DMA1 memory 0 address low register (channel 1) (C1M0ARL at 0x5086) */ + union { + + /// bytewise access to C1M0ARL + uint8_t byte; + + /// bitwise access to register C1M0ARL + struct { + BITS M0A0 : 1; // bit 0 + BITS M0A1 : 1; // bit 1 + BITS M0A2 : 1; // bit 2 + BITS M0A3 : 1; // bit 3 + BITS M0A4 : 1; // bit 4 + BITS M0A5 : 1; // bit 5 + BITS M0A6 : 1; // bit 6 + BITS M0A7 : 1; // bit 7 + }; // C1M0ARL bitfield + + /// register _DMA1_C1M0ARL reset value + #define sfr_DMA1_C1M0ARL_RESET_VALUE ((uint8_t) 0x00) + + } C1M0ARL; + + + /// Reserved register (2B) + uint8_t Reserved_5[2]; + + + /** DMA1 channel 2 configuration register (C2CR at 0x5089) */ + union { + + /// bytewise access to C2CR + uint8_t byte; + + /// bitwise access to register C2CR + struct { + BITS EN : 1; // bit 0 + BITS TCIE : 1; // bit 1 + BITS HTIE : 1; // bit 2 + BITS DIR : 1; // bit 3 + BITS CIRC : 1; // bit 4 + BITS MINCDEC : 1; // bit 5 + BITS : 2; // 2 bits + }; // C2CR bitfield + + /// register _DMA1_C2CR reset value + #define sfr_DMA1_C2CR_RESET_VALUE ((uint8_t) 0x00) + + } C2CR; + + + /** DMA1 channel 2 status (C2SPR at 0x508a) */ + union { + + /// bytewise access to C2SPR + uint8_t byte; + + /// bitwise access to register C2SPR + struct { + BITS : 1; // 1 bit + BITS TCIF : 1; // bit 1 + BITS HTIF : 1; // bit 2 + BITS TSIZE : 1; // bit 3 + BITS PL0 : 1; // bit 4 + BITS PL1 : 1; // bit 5 + BITS PEND : 1; // bit 6 + BITS BUSY : 1; // bit 7 + }; // C2SPR bitfield + + /// register _DMA1_C2SPR reset value + #define sfr_DMA1_C2SPR_RESET_VALUE ((uint8_t) 0x00) + + } C2SPR; + + + /** DMA1 number of data to transfer register (channel 2) (C2NDTR at 0x508b) */ + union { + + /// bytewise access to C2NDTR + uint8_t byte; + + /// bitwise access to register C2NDTR + struct { + BITS NDT0 : 1; // bit 0 + BITS NDT1 : 1; // bit 1 + BITS NDT2 : 1; // bit 2 + BITS NDT3 : 1; // bit 3 + BITS NDT4 : 1; // bit 4 + BITS NDT5 : 1; // bit 5 + BITS NDT6 : 1; // bit 6 + BITS NDT7 : 1; // bit 7 + }; // C2NDTR bitfield + + /// register _DMA1_C2NDTR reset value + #define sfr_DMA1_C2NDTR_RESET_VALUE ((uint8_t) 0x00) + + } C2NDTR; + + + /** DMA1 peripheral address high register (channel 2) (C2PARH at 0x508c) */ + union { + + /// bytewise access to C2PARH + uint8_t byte; + + /// bitwise access to register C2PARH + struct { + BITS PA8 : 1; // bit 0 + BITS PA9 : 1; // bit 1 + BITS PA10 : 1; // bit 2 + BITS PA11 : 1; // bit 3 + BITS PA12 : 1; // bit 4 + BITS PA13 : 1; // bit 5 + BITS PA14 : 1; // bit 6 + BITS PA15 : 1; // bit 7 + }; // C2PARH bitfield + + /// register _DMA1_C2PARH reset value + #define sfr_DMA1_C2PARH_RESET_VALUE ((uint8_t) 0x52) + + } C2PARH; + + + /** DMA1 peripheral address low register (channel 2) (C2PARL at 0x508d) */ + union { + + /// bytewise access to C2PARL + uint8_t byte; + + /// bitwise access to register C2PARL + struct { + BITS PA0 : 1; // bit 0 + BITS PA1 : 1; // bit 1 + BITS PA2 : 1; // bit 2 + BITS PA3 : 1; // bit 3 + BITS PA4 : 1; // bit 4 + BITS PA5 : 1; // bit 5 + BITS PA6 : 1; // bit 6 + BITS PA7 : 1; // bit 7 + }; // C2PARL bitfield + + /// register _DMA1_C2PARL reset value + #define sfr_DMA1_C2PARL_RESET_VALUE ((uint8_t) 0x00) + + } C2PARL; + + + /// Reserved register (1B) + uint8_t Reserved_6[1]; + + + /** DMA1 memory 0 address high register (channel 2) (C2M0ARH at 0x508f) */ + union { + + /// bytewise access to C2M0ARH + uint8_t byte; + + /// bitwise access to register C2M0ARH + struct { + BITS M0A8 : 1; // bit 0 + BITS M0A9 : 1; // bit 1 + BITS M0A10 : 1; // bit 2 + BITS M0A11 : 1; // bit 3 + BITS M0A12 : 1; // bit 4 + BITS M0A13 : 1; // bit 5 + BITS M0A14 : 1; // bit 6 + BITS M0A15 : 1; // bit 7 + }; // C2M0ARH bitfield + + /// register _DMA1_C2M0ARH reset value + #define sfr_DMA1_C2M0ARH_RESET_VALUE ((uint8_t) 0x00) + + } C2M0ARH; + + + /** DMA1 memory 0 address low register (channel 2) (C2M0ARL at 0x5090) */ + union { + + /// bytewise access to C2M0ARL + uint8_t byte; + + /// bitwise access to register C2M0ARL + struct { + BITS M0A0 : 1; // bit 0 + BITS M0A1 : 1; // bit 1 + BITS M0A2 : 1; // bit 2 + BITS M0A3 : 1; // bit 3 + BITS M0A4 : 1; // bit 4 + BITS M0A5 : 1; // bit 5 + BITS M0A6 : 1; // bit 6 + BITS M0A7 : 1; // bit 7 + }; // C2M0ARL bitfield + + /// register _DMA1_C2M0ARL reset value + #define sfr_DMA1_C2M0ARL_RESET_VALUE ((uint8_t) 0x00) + + } C2M0ARL; + + + /// Reserved register (2B) + uint8_t Reserved_7[2]; + + + /** DMA1 channel 3 configuration register (C3CR at 0x5093) */ + union { + + /// bytewise access to C3CR + uint8_t byte; + + /// bitwise access to register C3CR + struct { + BITS EN : 1; // bit 0 + BITS TCIE : 1; // bit 1 + BITS HTIE : 1; // bit 2 + BITS DIR : 1; // bit 3 + BITS CIRC : 1; // bit 4 + BITS MINCDEC : 1; // bit 5 + BITS MEM : 1; // bit 6 + BITS : 1; // 1 bit + }; // C3CR bitfield + + /// register _DMA1_C3CR reset value + #define sfr_DMA1_C3CR_RESET_VALUE ((uint8_t) 0x00) + + } C3CR; + + + /** DMA1 channel 3 status (C3SPR at 0x5094) */ + union { + + /// bytewise access to C3SPR + uint8_t byte; + + /// bitwise access to register C3SPR + struct { + BITS : 1; // 1 bit + BITS TCIF : 1; // bit 1 + BITS HTIF : 1; // bit 2 + BITS TSIZE : 1; // bit 3 + BITS PL0 : 1; // bit 4 + BITS PL1 : 1; // bit 5 + BITS PEND : 1; // bit 6 + BITS BUSY : 1; // bit 7 + }; // C3SPR bitfield + + /// register _DMA1_C3SPR reset value + #define sfr_DMA1_C3SPR_RESET_VALUE ((uint8_t) 0x00) + + } C3SPR; + + + /** DMA1 number of data to transfer register (channel 3) (C3NDTR at 0x5095) */ + union { + + /// bytewise access to C3NDTR + uint8_t byte; + + /// bitwise access to register C3NDTR + struct { + BITS NDT0 : 1; // bit 0 + BITS NDT1 : 1; // bit 1 + BITS NDT2 : 1; // bit 2 + BITS NDT3 : 1; // bit 3 + BITS NDT4 : 1; // bit 4 + BITS NDT5 : 1; // bit 5 + BITS NDT6 : 1; // bit 6 + BITS NDT7 : 1; // bit 7 + }; // C3NDTR bitfield + + /// register _DMA1_C3NDTR reset value + #define sfr_DMA1_C3NDTR_RESET_VALUE ((uint8_t) 0x00) + + } C3NDTR; + + + /** DMA1 peripheral address high register (channel 3) (C3PARH_C3M1ARH at 0x5096) */ + union { + + /// bytewise access to C3PARH_C3M1ARH + uint8_t byte; + + /// bitwise access to register C3PARH + struct { + BITS PA8 : 1; // bit 0 + BITS PA9 : 1; // bit 1 + BITS PA10 : 1; // bit 2 + BITS PA11 : 1; // bit 3 + BITS PA12 : 1; // bit 4 + BITS PA13 : 1; // bit 5 + BITS PA14 : 1; // bit 6 + BITS PA15 : 1; // bit 7 + }; // C3PARH bitfield + + /// register _DMA1_C3PARH reset value + #define sfr_DMA1_C3PARH_RESET_VALUE ((uint8_t) 0x40) + + + /// bitwise access to register C3M1ARH + struct { + BITS M1A8 : 1; // bit 0 + BITS M1A9 : 1; // bit 1 + BITS M1A10 : 1; // bit 2 + BITS M1A11 : 1; // bit 3 + BITS M1A12 : 1; // bit 4 + BITS M1A13 : 1; // bit 5 + BITS M1A14 : 1; // bit 6 + BITS M1A15 : 1; // bit 7 + }; // C3M1ARH bitfield + + /// register _DMA1_C3M1ARH reset value + #define sfr_DMA1_C3M1ARH_RESET_VALUE ((uint8_t) 0x40) + + } C3PARH_C3M1ARH; + + + /** DMA1 peripheral address low register (channel 3) (C3PARL_C3M1ARL at 0x5097) */ + union { + + /// bytewise access to C3PARL_C3M1ARL + uint8_t byte; + + /// bitwise access to register C3PARL + struct { + BITS PA0 : 1; // bit 0 + BITS PA1 : 1; // bit 1 + BITS PA2 : 1; // bit 2 + BITS PA3 : 1; // bit 3 + BITS PA4 : 1; // bit 4 + BITS PA5 : 1; // bit 5 + BITS PA6 : 1; // bit 6 + BITS PA7 : 1; // bit 7 + }; // C3PARL bitfield + + /// register _DMA1_C3PARL reset value + #define sfr_DMA1_C3PARL_RESET_VALUE ((uint8_t) 0x00) + + + /// bitwise access to register C3M1ARL + struct { + BITS M1A0 : 1; // bit 0 + BITS M1A1 : 1; // bit 1 + BITS M1A2 : 1; // bit 2 + BITS M1A3 : 1; // bit 3 + BITS M1A4 : 1; // bit 4 + BITS M1A5 : 1; // bit 5 + BITS M1A6 : 1; // bit 6 + BITS M1A7 : 1; // bit 7 + }; // C3M1ARL bitfield + + /// register _DMA1_C3M1ARL reset value + #define sfr_DMA1_C3M1ARL_RESET_VALUE ((uint8_t) 0x00) + + } C3PARL_C3M1ARL; + + + /// Reserved register (1B) + uint8_t Reserved_8[1]; + + + /** DMA1 memory 0 address high register (channel 3) (C3M0ARH at 0x5099) */ + union { + + /// bytewise access to C3M0ARH + uint8_t byte; + + /// bitwise access to register C3M0ARH + struct { + BITS M0A8 : 1; // bit 0 + BITS M0A9 : 1; // bit 1 + BITS M0A10 : 1; // bit 2 + BITS M0A11 : 1; // bit 3 + BITS M0A12 : 1; // bit 4 + BITS M0A13 : 1; // bit 5 + BITS M0A14 : 1; // bit 6 + BITS M0A15 : 1; // bit 7 + }; // C3M0ARH bitfield + + /// register _DMA1_C3M0ARH reset value + #define sfr_DMA1_C3M0ARH_RESET_VALUE ((uint8_t) 0x00) + + } C3M0ARH; + + + /** DMA1 memory 0 address low register (channel 3) (C3M0ARL at 0x509a) */ + union { + + /// bytewise access to C3M0ARL + uint8_t byte; + + /// bitwise access to register C3M0ARL + struct { + BITS M0A0 : 1; // bit 0 + BITS M0A1 : 1; // bit 1 + BITS M0A2 : 1; // bit 2 + BITS M0A3 : 1; // bit 3 + BITS M0A4 : 1; // bit 4 + BITS M0A5 : 1; // bit 5 + BITS M0A6 : 1; // bit 6 + BITS M0A7 : 1; // bit 7 + }; // C3M0ARL bitfield + + /// register _DMA1_C3M0ARL reset value + #define sfr_DMA1_C3M0ARL_RESET_VALUE ((uint8_t) 0x00) + + } C3M0ARL; + +} DMA1_t; + +/// access to DMA1 SFR registers +#define sfr_DMA1 (*((DMA1_t*) 0x5070)) + + +//------------------------ +// Module FLASH +//------------------------ + +/** struct containing FLASH module registers */ +typedef struct { + + /** Flash control register 1 (CR1 at 0x5050) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS FIX : 1; // bit 0 + BITS IE : 1; // bit 1 + BITS WAITM : 1; // bit 2 + BITS EEPM : 1; // bit 3 + BITS : 4; // 4 bits + }; // CR1 bitfield + + /// register _FLASH_CR1 reset value + #define sfr_FLASH_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Flash control register 2 (CR2 at 0x5051) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS FPRG : 1; // bit 4 + BITS ERASE : 1; // bit 5 + BITS WPRG : 1; // bit 6 + BITS OPT : 1; // bit 7 + }; // CR2 bitfield + + /// register _FLASH_CR2 reset value + #define sfr_FLASH_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** Flash program memory unprotection key register (PUKR at 0x5052) */ + union { + + /// bytewise access to PUKR + uint8_t byte; + + /// bitwise access to register PUKR + struct { + BITS MASS_PRG : 8; // bits 0-7 + }; // PUKR bitfield + + /// register _FLASH_PUKR reset value + #define sfr_FLASH_PUKR_RESET_VALUE ((uint8_t) 0x00) + + } PUKR; + + + /** Data EEPROM unprotection key register (DUKR at 0x5053) */ + union { + + /// bytewise access to DUKR + uint8_t byte; + + /// bitwise access to register DUKR + struct { + BITS MASS_DATA : 8; // bits 0-7 + }; // DUKR bitfield + + /// register _FLASH_DUKR reset value + #define sfr_FLASH_DUKR_RESET_VALUE ((uint8_t) 0x00) + + } DUKR; + + + /** Flash in-application programming status register (IAPSR at 0x5054) */ + union { + + /// bytewise access to IAPSR + uint8_t byte; + + /// bitwise access to register IAPSR + struct { + BITS WR_PG_DIS : 1; // bit 0 + BITS PUL : 1; // bit 1 + BITS EOP : 1; // bit 2 + BITS DUL : 1; // bit 3 + BITS : 2; // 2 bits + BITS HVOFF : 1; // bit 6 + BITS : 1; // 1 bit + }; // IAPSR bitfield + + /// register _FLASH_IAPSR reset value + #define sfr_FLASH_IAPSR_RESET_VALUE ((uint8_t) 0x00) + + } IAPSR; + +} FLASH_t; + +/// access to FLASH SFR registers +#define sfr_FLASH (*((FLASH_t*) 0x5050)) + + +//------------------------ +// Module I2C1 +//------------------------ + +/** struct containing I2C1 module registers */ +typedef struct { + + /** I2C1 control register 1 (CR1 at 0x5210) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PE : 1; // bit 0 + BITS SMBUS : 1; // bit 1 + BITS : 1; // 1 bit + BITS SMBTYPE : 1; // bit 3 + BITS ENARP : 1; // bit 4 + BITS ENPEC : 1; // bit 5 + BITS ENGC : 1; // bit 6 + BITS NOSTRETCH : 1; // bit 7 + }; // CR1 bitfield + + /// register _I2C1_CR1 reset value + #define sfr_I2C1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** I2C1 control register 2 (CR2 at 0x5211) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS START : 1; // bit 0 + BITS STOP : 1; // bit 1 + BITS ACK : 1; // bit 2 + BITS POS : 1; // bit 3 + BITS PEC : 1; // bit 4 + BITS ALERT : 1; // bit 5 + BITS : 1; // 1 bit + BITS SWRST : 1; // bit 7 + }; // CR2 bitfield + + /// register _I2C1_CR2 reset value + #define sfr_I2C1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** I2C1 frequency register (FREQR at 0x5212) */ + union { + + /// bytewise access to FREQR + uint8_t byte; + + /// bitwise access to register FREQR + struct { + BITS FREQ : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // FREQR bitfield + + /// register _I2C1_FREQR reset value + #define sfr_I2C1_FREQR_RESET_VALUE ((uint8_t) 0x00) + + } FREQR; + + + /** I2C1 own address register low (OARL at 0x5213) */ + union { + + /// bytewise access to OARL + uint8_t byte; + + /// bitwise access to register OARL + struct { + BITS ADD0 : 1; // bit 0 + BITS ADD1 : 1; // bit 1 + BITS ADD2 : 1; // bit 2 + BITS ADD3 : 1; // bit 3 + BITS ADD4 : 1; // bit 4 + BITS ADD5 : 1; // bit 5 + BITS ADD6 : 1; // bit 6 + BITS ADD7 : 1; // bit 7 + }; // OARL bitfield + + /// register _I2C1_OARL reset value + #define sfr_I2C1_OARL_RESET_VALUE ((uint8_t) 0x00) + + } OARL; + + + /** I2C1 own address register high (OARH at 0x5214) */ + union { + + /// bytewise access to OARH + uint8_t byte; + + /// bitwise access to register OARH + struct { + BITS : 1; // 1 bit + BITS ADD8 : 1; // bit 1 + BITS ADD9 : 1; // bit 2 + BITS : 3; // 3 bits + BITS ADDCONF : 1; // bit 6 + BITS ADDMODE : 1; // bit 7 + }; // OARH bitfield + + /// register _I2C1_OARH reset value + #define sfr_I2C1_OARH_RESET_VALUE ((uint8_t) 0x00) + + } OARH; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** I2C1 data register (DR at 0x5216) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _I2C1_DR reset value + #define sfr_I2C1_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** I2C1 status register 1 (SR1 at 0x5217) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS SB : 1; // bit 0 + BITS ADDR : 1; // bit 1 + BITS BTF : 1; // bit 2 + BITS ADD10 : 1; // bit 3 + BITS STOPF : 1; // bit 4 + BITS : 1; // 1 bit + BITS RXNE : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR1 bitfield + + /// register _I2C1_SR1 reset value + #define sfr_I2C1_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** I2C1 status register 2 (SR2 at 0x5218) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS BERR : 1; // bit 0 + BITS ARLO : 1; // bit 1 + BITS AF : 1; // bit 2 + BITS OVR : 1; // bit 3 + BITS PECERR : 1; // bit 4 + BITS WUFH : 1; // bit 5 + BITS TIMEOUT : 1; // bit 6 + BITS SMBALERT : 1; // bit 7 + }; // SR2 bitfield + + /// register _I2C1_SR2 reset value + #define sfr_I2C1_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** I2C1 status register 3 (SR3 at 0x5219) */ + union { + + /// bytewise access to SR3 + uint8_t byte; + + /// bitwise access to register SR3 + struct { + BITS MSL : 1; // bit 0 + BITS BUSY : 1; // bit 1 + BITS TRA : 1; // bit 2 + BITS : 1; // 1 bit + BITS GENCALL : 1; // bit 4 + BITS SMBDEFAULT : 1; // bit 5 + BITS SMBHOST : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR3 bitfield + + /// register _I2C1_SR3 reset value + #define sfr_I2C1_SR3_RESET_VALUE ((uint8_t) 0x00) + + } SR3; + + + /** I2C1 interrupt control register (ITR at 0x521a) */ + union { + + /// bytewise access to ITR + uint8_t byte; + + /// bitwise access to register ITR + struct { + BITS ITERREN : 1; // bit 0 + BITS ITEVTEN : 1; // bit 1 + BITS ITBUFEN : 1; // bit 2 + BITS DMAEN : 1; // bit 3 + BITS LAST : 1; // bit 4 + BITS : 3; // 3 bits + }; // ITR bitfield + + /// register _I2C1_ITR reset value + #define sfr_I2C1_ITR_RESET_VALUE ((uint8_t) 0x00) + + } ITR; + + + /** I2C1 clock control register low (CCRL at 0x521b) */ + union { + + /// bytewise access to CCRL + uint8_t byte; + + /// bitwise access to register CCRL + struct { + BITS CCR0 : 1; // bit 0 + BITS CCR1 : 1; // bit 1 + BITS CCR2 : 1; // bit 2 + BITS CCR3 : 1; // bit 3 + BITS CCR4 : 1; // bit 4 + BITS CCR5 : 1; // bit 5 + BITS CCR6 : 1; // bit 6 + BITS CCR7 : 1; // bit 7 + }; // CCRL bitfield + + /// register _I2C1_CCRL reset value + #define sfr_I2C1_CCRL_RESET_VALUE ((uint8_t) 0x00) + + } CCRL; + + + /** I2C1 clock control register high (CCRH at 0x521c) */ + union { + + /// bytewise access to CCRH + uint8_t byte; + + /// bitwise access to register CCRH + struct { + BITS CCR8 : 1; // bit 0 + BITS CCR9 : 1; // bit 1 + BITS CCR10 : 1; // bit 2 + BITS CCR11 : 1; // bit 3 + BITS : 2; // 2 bits + BITS DUTY : 1; // bit 6 + BITS F_S : 1; // bit 7 + }; // CCRH bitfield + + /// register _I2C1_CCRH reset value + #define sfr_I2C1_CCRH_RESET_VALUE ((uint8_t) 0x00) + + } CCRH; + + + /** I2C1 TRISE register (TRISER at 0x521d) */ + union { + + /// bytewise access to TRISER + uint8_t byte; + + /// bitwise access to register TRISER + struct { + BITS TRISE : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // TRISER bitfield + + /// register _I2C1_TRISER reset value + #define sfr_I2C1_TRISER_RESET_VALUE ((uint8_t) 0x02) + + } TRISER; + + + /** I2C1 packet error checking register (PECR at 0x521e) */ + union { + + /// bytewise access to PECR + uint8_t byte; + + /// bitwise access to register PECR + struct { + BITS PEC : 8; // bits 0-7 + }; // PECR bitfield + + /// register _I2C1_PECR reset value + #define sfr_I2C1_PECR_RESET_VALUE ((uint8_t) 0x00) + + } PECR; + +} I2C1_t; + +/// access to I2C1 SFR registers +#define sfr_I2C1 (*((I2C1_t*) 0x5210)) + + +//------------------------ +// Module IRTIM +//------------------------ + +/** struct containing IRTIM module registers */ +typedef struct { + + /** Infra-red control register (CR at 0x52ff) */ + union { + + /// bytewise access to CR + uint8_t byte; + + /// bitwise access to register CR + struct { + BITS IR_EN : 1; // bit 0 + BITS HS_EN : 1; // bit 1 + BITS : 6; // 6 bits + }; // CR bitfield + + /// register _IRTIM_CR reset value + #define sfr_IRTIM_CR_RESET_VALUE ((uint8_t) 0x00) + + } CR; + +} IRTIM_t; + +/// access to IRTIM SFR registers +#define sfr_IRTIM (*((IRTIM_t*) 0x52ff)) + + +//------------------------ +// Module ITC_EXTI +//------------------------ + +/** struct containing ITC_EXTI module registers */ +typedef struct { + + /** External interrupt control register 1 (CR1 at 0x50a0) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS P0IS : 2; // bits 0-1 + BITS P1IS : 2; // bits 2-3 + BITS P2IS : 2; // bits 4-5 + BITS P3IS : 2; // bits 6-7 + }; // CR1 bitfield + + /// register _ITC_EXTI_CR1 reset value + #define sfr_ITC_EXTI_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** External interrupt control register 2 (CR2 at 0x50a1) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS P4IS : 2; // bits 0-1 + BITS P5IS : 2; // bits 2-3 + BITS P6IS : 2; // bits 4-5 + BITS P7IS : 2; // bits 6-7 + }; // CR2 bitfield + + /// register _ITC_EXTI_CR2 reset value + #define sfr_ITC_EXTI_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** External interrupt control register 3 (CR3 at 0x50a2) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS PBIS : 2; // bits 0-1 + BITS PDIS : 2; // bits 2-3 + BITS PEIS : 2; // bits 4-5 + BITS PFIS : 2; // bits 6-7 + }; // CR3 bitfield + + /// register _ITC_EXTI_CR3 reset value + #define sfr_ITC_EXTI_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** External interrupt status register 1 (SR1 at 0x50a3) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS P0F : 1; // bit 0 + BITS P1F : 1; // bit 1 + BITS P2F : 1; // bit 2 + BITS P3F : 1; // bit 3 + BITS P4F : 1; // bit 4 + BITS P5F : 1; // bit 5 + BITS P6F : 1; // bit 6 + BITS P7F : 1; // bit 7 + }; // SR1 bitfield + + /// register _ITC_EXTI_SR1 reset value + #define sfr_ITC_EXTI_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** External interrupt status register 2 (SR2 at 0x50a4) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS PBF : 1; // bit 0 + BITS PDF : 1; // bit 1 + BITS PEF : 1; // bit 2 + BITS PFF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SR2 bitfield + + /// register _ITC_EXTI_SR2 reset value + #define sfr_ITC_EXTI_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** External interrupt port select register (CONF at 0x50a5) */ + union { + + /// bytewise access to CONF + uint8_t byte; + + /// bitwise access to register CONF + struct { + BITS PBLIS : 1; // bit 0 + BITS PBHIS : 1; // bit 1 + BITS PDLIS : 1; // bit 2 + BITS PDHIS : 1; // bit 3 + BITS PELIS : 1; // bit 4 + BITS PEHIS : 1; // bit 5 + BITS PFLIS : 1; // bit 6 + BITS PFES : 1; // bit 7 + }; // CONF bitfield + + /// register _ITC_EXTI_CONF reset value + #define sfr_ITC_EXTI_CONF_RESET_VALUE ((uint8_t) 0x00) + + } CONF; + +} ITC_EXTI_t; + +/// access to ITC_EXTI SFR registers +#define sfr_ITC_EXTI (*((ITC_EXTI_t*) 0x50a0)) + + +//------------------------ +// Module ITC_SPR +//------------------------ + +/** struct containing ITC_SPR module registers */ +typedef struct { + + /** Interrupt Software priority register 1 (SPR1 at 0x7f70) */ + union { + + /// bytewise access to SPR1 + uint8_t byte; + + /// bitwise access to register SPR1 + struct { + BITS VECT0SPR : 2; // bits 0-1 + BITS VECT1SPR : 2; // bits 2-3 + BITS VECT2SPR : 2; // bits 4-5 + BITS VECT3SPR : 2; // bits 6-7 + }; // SPR1 bitfield + + /// register _ITC_SPR_SPR1 reset value + #define sfr_ITC_SPR_SPR1_RESET_VALUE ((uint8_t) 0xFF) + + } SPR1; + + + /** Interrupt Software priority register 2 (SPR2 at 0x7f71) */ + union { + + /// bytewise access to SPR2 + uint8_t byte; + + /// bitwise access to register SPR2 + struct { + BITS VECT4SPR : 2; // bits 0-1 + BITS VECT5SPR : 2; // bits 2-3 + BITS VECT6SPR : 2; // bits 4-5 + BITS VECT7SPR : 2; // bits 6-7 + }; // SPR2 bitfield + + /// register _ITC_SPR_SPR2 reset value + #define sfr_ITC_SPR_SPR2_RESET_VALUE ((uint8_t) 0xFF) + + } SPR2; + + + /** Interrupt Software priority register 3 (SPR3 at 0x7f72) */ + union { + + /// bytewise access to SPR3 + uint8_t byte; + + /// bitwise access to register SPR3 + struct { + BITS VECT8SPR : 2; // bits 0-1 + BITS VECT9SPR : 2; // bits 2-3 + BITS VECT10SPR : 2; // bits 4-5 + BITS VECT11SPR : 2; // bits 6-7 + }; // SPR3 bitfield + + /// register _ITC_SPR_SPR3 reset value + #define sfr_ITC_SPR_SPR3_RESET_VALUE ((uint8_t) 0xFF) + + } SPR3; + + + /** Interrupt Software priority register 4 (SPR4 at 0x7f73) */ + union { + + /// bytewise access to SPR4 + uint8_t byte; + + /// bitwise access to register SPR4 + struct { + BITS VECT12SPR : 2; // bits 0-1 + BITS VECT13SPR : 2; // bits 2-3 + BITS VECT14SPR : 2; // bits 4-5 + BITS VECT15SPR : 2; // bits 6-7 + }; // SPR4 bitfield + + /// register _ITC_SPR_SPR4 reset value + #define sfr_ITC_SPR_SPR4_RESET_VALUE ((uint8_t) 0xFF) + + } SPR4; + + + /** Interrupt Software priority register 5 (SPR5 at 0x7f74) */ + union { + + /// bytewise access to SPR5 + uint8_t byte; + + /// bitwise access to register SPR5 + struct { + BITS VECT16SPR : 2; // bits 0-1 + BITS VECT17SPR : 2; // bits 2-3 + BITS VECT18SPR : 2; // bits 4-5 + BITS VECT19SPR : 2; // bits 6-7 + }; // SPR5 bitfield + + /// register _ITC_SPR_SPR5 reset value + #define sfr_ITC_SPR_SPR5_RESET_VALUE ((uint8_t) 0xFF) + + } SPR5; + + + /** Interrupt Software priority register 6 (SPR6 at 0x7f75) */ + union { + + /// bytewise access to SPR6 + uint8_t byte; + + /// bitwise access to register SPR6 + struct { + BITS VECT20SPR : 2; // bits 0-1 + BITS VECT21SPR : 2; // bits 2-3 + BITS VECT22SPR : 2; // bits 4-5 + BITS VECT23SPR : 2; // bits 6-7 + }; // SPR6 bitfield + + /// register _ITC_SPR_SPR6 reset value + #define sfr_ITC_SPR_SPR6_RESET_VALUE ((uint8_t) 0xFF) + + } SPR6; + + + /** Interrupt Software priority register 7 (SPR7 at 0x7f76) */ + union { + + /// bytewise access to SPR7 + uint8_t byte; + + /// bitwise access to register SPR7 + struct { + BITS VECT24SPR : 2; // bits 0-1 + BITS VECT25SPR : 2; // bits 2-3 + BITS VECT26SPR : 2; // bits 4-5 + BITS VECT27SPR : 2; // bits 6-7 + }; // SPR7 bitfield + + /// register _ITC_SPR_SPR7 reset value + #define sfr_ITC_SPR_SPR7_RESET_VALUE ((uint8_t) 0xFF) + + } SPR7; + + + /** Interrupt Software priority register 8 (SPR8 at 0x7f77) */ + union { + + /// bytewise access to SPR8 + uint8_t byte; + + /// bitwise access to register SPR8 + struct { + BITS VECT28SPR : 2; // bits 0-1 + BITS VECT29SPR : 2; // bits 2-3 + BITS : 4; // 4 bits + }; // SPR8 bitfield + + /// register _ITC_SPR_SPR8 reset value + #define sfr_ITC_SPR_SPR8_RESET_VALUE ((uint8_t) 0xFF) + + } SPR8; + +} ITC_SPR_t; + +/// access to ITC_SPR SFR registers +#define sfr_ITC_SPR (*((ITC_SPR_t*) 0x7f70)) + + +//------------------------ +// Module IWDG +//------------------------ + +/** struct containing IWDG module registers */ +typedef struct { + + /** IWDG key register (KR at 0x50e0) */ + union { + + /// bytewise access to KR + uint8_t byte; + + /// bitwise access to register KR + struct { + BITS KEY0 : 1; // bit 0 + BITS KEY1 : 1; // bit 1 + BITS KEY2 : 1; // bit 2 + BITS KEY3 : 1; // bit 3 + BITS KEY4 : 1; // bit 4 + BITS KEY5 : 1; // bit 5 + BITS KEY6 : 1; // bit 6 + BITS KEY7 : 1; // bit 7 + }; // KR bitfield + + /// register _IWDG_KR reset value + #define sfr_IWDG_KR_RESET_VALUE ((uint8_t) 0x00) + + } KR; + + + /** IWDG prescaler register (PR at 0x50e1) */ + union { + + /// bytewise access to PR + uint8_t byte; + + /// bitwise access to register PR + struct { + BITS PR : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PR bitfield + + /// register _IWDG_PR reset value + #define sfr_IWDG_PR_RESET_VALUE ((uint8_t) 0x00) + + } PR; + + + /** IWDG reload register (RLR at 0x50e2) */ + union { + + /// bytewise access to RLR + uint8_t byte; + + /// bitwise access to register RLR + struct { + BITS RL : 8; // bits 0-7 + }; // RLR bitfield + + /// register _IWDG_RLR reset value + #define sfr_IWDG_RLR_RESET_VALUE ((uint8_t) 0xFF) + + } RLR; + +} IWDG_t; + +/// access to IWDG SFR registers +#define sfr_IWDG (*((IWDG_t*) 0x50e0)) + + +//------------------------ +// Module LCD +//------------------------ + +/** struct containing LCD module registers */ +typedef struct { + + /** LCD control register 1 (CR1 at 0x5400) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS B2 : 1; // bit 0 + BITS DUTY0 : 1; // bit 1 + BITS DUTY1 : 1; // bit 2 + BITS BLINKF0 : 1; // bit 3 + BITS BLINKF1 : 1; // bit 4 + BITS BLINKF2 : 1; // bit 5 + BITS BLINK0 : 1; // bit 6 + BITS BLINK1 : 1; // bit 7 + }; // CR1 bitfield + + /// register _LCD_CR1 reset value + #define sfr_LCD_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** LCD control register 2 (CR2 at 0x5401) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS VSEL : 1; // bit 0 + BITS CC0 : 1; // bit 1 + BITS CC1 : 1; // bit 2 + BITS CC2 : 1; // bit 3 + BITS HD : 1; // bit 4 + BITS PON0 : 1; // bit 5 + BITS PON1 : 1; // bit 6 + BITS PON2 : 1; // bit 7 + }; // CR2 bitfield + + /// register _LCD_CR2 reset value + #define sfr_LCD_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** LCD control register 3 (CR3 at 0x5402) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS DEAD0 : 1; // bit 0 + BITS DEAD1 : 1; // bit 1 + BITS DEAD2 : 1; // bit 2 + BITS SOFC : 1; // bit 3 + BITS SOF : 1; // bit 4 + BITS SOFIE : 1; // bit 5 + BITS LCDEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR3 bitfield + + /// register _LCD_CR3 reset value + #define sfr_LCD_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** LCD frequency selection register (FRQ at 0x5403) */ + union { + + /// bytewise access to FRQ + uint8_t byte; + + /// bitwise access to register FRQ + struct { + BITS DIV0 : 1; // bit 0 + BITS DIV1 : 1; // bit 1 + BITS DIV2 : 1; // bit 2 + BITS DIV3 : 1; // bit 3 + BITS PS0 : 1; // bit 4 + BITS PS1 : 1; // bit 5 + BITS PS2 : 1; // bit 6 + BITS PS3 : 1; // bit 7 + }; // FRQ bitfield + + /// register _LCD_FRQ reset value + #define sfr_LCD_FRQ_RESET_VALUE ((uint8_t) 0x00) + + } FRQ; + + + /** LCD Port mask register 0 (PM0 at 0x5404) */ + union { + + /// bytewise access to PM0 + uint8_t byte; + + /// bitwise access to register PM0 + struct { + BITS SEG00 : 1; // bit 0 + BITS SEG01 : 1; // bit 1 + BITS SEG02 : 1; // bit 2 + BITS SEG03 : 1; // bit 3 + BITS SEG04 : 1; // bit 4 + BITS SEG05 : 1; // bit 5 + BITS SEG06 : 1; // bit 6 + BITS SEG07 : 1; // bit 7 + }; // PM0 bitfield + + /// register _LCD_PM0 reset value + #define sfr_LCD_PM0_RESET_VALUE ((uint8_t) 0x00) + + } PM0; + + + /** LCD Port mask register 1 (PM1 at 0x5405) */ + union { + + /// bytewise access to PM1 + uint8_t byte; + + /// bitwise access to register PM1 + struct { + BITS SEG08 : 1; // bit 0 + BITS SEG09 : 1; // bit 1 + BITS SEG10 : 1; // bit 2 + BITS SEG11 : 1; // bit 3 + BITS SEG12 : 1; // bit 4 + BITS SEG13 : 1; // bit 5 + BITS SEG14 : 1; // bit 6 + BITS SEG15 : 1; // bit 7 + }; // PM1 bitfield + + /// register _LCD_PM1 reset value + #define sfr_LCD_PM1_RESET_VALUE ((uint8_t) 0x00) + + } PM1; + + + /** LCD Port mask register 2 (PM2 at 0x5406) */ + union { + + /// bytewise access to PM2 + uint8_t byte; + + /// bitwise access to register PM2 + struct { + BITS SEG16 : 1; // bit 0 + BITS SEG17 : 1; // bit 1 + BITS SEG18 : 1; // bit 2 + BITS SEG19 : 1; // bit 3 + BITS SEG20 : 1; // bit 4 + BITS SEG21 : 1; // bit 5 + BITS SEG22 : 1; // bit 6 + BITS SEG23 : 1; // bit 7 + }; // PM2 bitfield + + /// register _LCD_PM2 reset value + #define sfr_LCD_PM2_RESET_VALUE ((uint8_t) 0x00) + + } PM2; + + + /** LCD Port mask register 3 (PM3 at 0x5407) */ + union { + + /// bytewise access to PM3 + uint8_t byte; + + /// bitwise access to register PM3 + struct { + BITS SEG24 : 1; // bit 0 + BITS SEG25 : 1; // bit 1 + BITS SEG26 : 1; // bit 2 + BITS SEG27 : 1; // bit 3 + BITS : 4; // 4 bits + }; // PM3 bitfield + + /// register _LCD_PM3 reset value + #define sfr_LCD_PM3_RESET_VALUE ((uint8_t) 0x00) + + } PM3; + + + /// Reserved register (4B) + uint8_t Reserved_1[4]; + + + /** LCD display memory 0 (RAM0 at 0x540c) */ + union { + + /// bytewise access to RAM0 + uint8_t byte; + + /// bitwise access to register RAM0 + struct { + BITS S000 : 1; // bit 0 + BITS S001 : 1; // bit 1 + BITS S002 : 1; // bit 2 + BITS S003 : 1; // bit 3 + BITS S004 : 1; // bit 4 + BITS S005 : 1; // bit 5 + BITS S006 : 1; // bit 6 + BITS S007 : 1; // bit 7 + }; // RAM0 bitfield + + /// register _LCD_RAM0 reset value + #define sfr_LCD_RAM0_RESET_VALUE ((uint8_t) 0x00) + + } RAM0; + + + /** LCD display memory 1 (RAM1 at 0x540d) */ + union { + + /// bytewise access to RAM1 + uint8_t byte; + + /// bitwise access to register RAM1 + struct { + BITS S008 : 1; // bit 0 + BITS S009 : 1; // bit 1 + BITS S010 : 1; // bit 2 + BITS S011 : 1; // bit 3 + BITS S012 : 1; // bit 4 + BITS S013 : 1; // bit 5 + BITS S014 : 1; // bit 6 + BITS S015 : 1; // bit 7 + }; // RAM1 bitfield + + /// register _LCD_RAM1 reset value + #define sfr_LCD_RAM1_RESET_VALUE ((uint8_t) 0x00) + + } RAM1; + + + /** LCD display memory 2 (RAM2 at 0x540e) */ + union { + + /// bytewise access to RAM2 + uint8_t byte; + + /// bitwise access to register RAM2 + struct { + BITS S016 : 1; // bit 0 + BITS S017 : 1; // bit 1 + BITS S018 : 1; // bit 2 + BITS S019 : 1; // bit 3 + BITS S020 : 1; // bit 4 + BITS S021 : 1; // bit 5 + BITS S022 : 1; // bit 6 + BITS S023 : 1; // bit 7 + }; // RAM2 bitfield + + /// register _LCD_RAM2 reset value + #define sfr_LCD_RAM2_RESET_VALUE ((uint8_t) 0x00) + + } RAM2; + + + /** LCD display memory 3 (RAM3 at 0x540f) */ + union { + + /// bytewise access to RAM3 + uint8_t byte; + + /// bitwise access to register RAM3 + struct { + BITS S024 : 1; // bit 0 + BITS S025 : 1; // bit 1 + BITS S026 : 1; // bit 2 + BITS S027 : 1; // bit 3 + BITS S100 : 1; // bit 4 + BITS S101 : 1; // bit 5 + BITS S102 : 1; // bit 6 + BITS S103 : 1; // bit 7 + }; // RAM3 bitfield + + /// register _LCD_RAM3 reset value + #define sfr_LCD_RAM3_RESET_VALUE ((uint8_t) 0x00) + + } RAM3; + + + /** LCD display memory 4 (RAM4 at 0x5410) */ + union { + + /// bytewise access to RAM4 + uint8_t byte; + + /// bitwise access to register RAM4 + struct { + BITS S104 : 1; // bit 0 + BITS S105 : 1; // bit 1 + BITS S106 : 1; // bit 2 + BITS S107 : 1; // bit 3 + BITS S108 : 1; // bit 4 + BITS S109 : 1; // bit 5 + BITS S110 : 1; // bit 6 + BITS S111 : 1; // bit 7 + }; // RAM4 bitfield + + /// register _LCD_RAM4 reset value + #define sfr_LCD_RAM4_RESET_VALUE ((uint8_t) 0x00) + + } RAM4; + + + /** LCD display memory 5 (RAM5 at 0x5411) */ + union { + + /// bytewise access to RAM5 + uint8_t byte; + + /// bitwise access to register RAM5 + struct { + BITS S112 : 1; // bit 0 + BITS S113 : 1; // bit 1 + BITS S114 : 1; // bit 2 + BITS S115 : 1; // bit 3 + BITS S116 : 1; // bit 4 + BITS S117 : 1; // bit 5 + BITS S118 : 1; // bit 6 + BITS S119 : 1; // bit 7 + }; // RAM5 bitfield + + /// register _LCD_RAM5 reset value + #define sfr_LCD_RAM5_RESET_VALUE ((uint8_t) 0x00) + + } RAM5; + + + /** LCD display memory 6 (RAM6 at 0x5412) */ + union { + + /// bytewise access to RAM6 + uint8_t byte; + + /// bitwise access to register RAM6 + struct { + BITS S120 : 1; // bit 0 + BITS S121 : 1; // bit 1 + BITS S122 : 1; // bit 2 + BITS S123 : 1; // bit 3 + BITS S124 : 1; // bit 4 + BITS S125 : 1; // bit 5 + BITS S126 : 1; // bit 6 + BITS S127 : 1; // bit 7 + }; // RAM6 bitfield + + /// register _LCD_RAM6 reset value + #define sfr_LCD_RAM6_RESET_VALUE ((uint8_t) 0x00) + + } RAM6; + + + /** LCD display memory 7 (RAM7 at 0x5413) */ + union { + + /// bytewise access to RAM7 + uint8_t byte; + + /// bitwise access to register RAM7 + struct { + BITS S200 : 1; // bit 0 + BITS S201 : 1; // bit 1 + BITS S202 : 1; // bit 2 + BITS S203 : 1; // bit 3 + BITS S204 : 1; // bit 4 + BITS S205 : 1; // bit 5 + BITS S206 : 1; // bit 6 + BITS S207 : 1; // bit 7 + }; // RAM7 bitfield + + /// register _LCD_RAM7 reset value + #define sfr_LCD_RAM7_RESET_VALUE ((uint8_t) 0x00) + + } RAM7; + + + /** LCD display memory 8 (RAM8 at 0x5414) */ + union { + + /// bytewise access to RAM8 + uint8_t byte; + + /// bitwise access to register RAM8 + struct { + BITS S208 : 1; // bit 0 + BITS S209 : 1; // bit 1 + BITS S210 : 1; // bit 2 + BITS S211 : 1; // bit 3 + BITS S212 : 1; // bit 4 + BITS S213 : 1; // bit 5 + BITS S214 : 1; // bit 6 + BITS S215 : 1; // bit 7 + }; // RAM8 bitfield + + /// register _LCD_RAM8 reset value + #define sfr_LCD_RAM8_RESET_VALUE ((uint8_t) 0x00) + + } RAM8; + + + /** LCD display memory 9 (RAM9 at 0x5415) */ + union { + + /// bytewise access to RAM9 + uint8_t byte; + + /// bitwise access to register RAM9 + struct { + BITS S216 : 1; // bit 0 + BITS S217 : 1; // bit 1 + BITS S218 : 1; // bit 2 + BITS S219 : 1; // bit 3 + BITS S220 : 1; // bit 4 + BITS S221 : 1; // bit 5 + BITS S222 : 1; // bit 6 + BITS S223 : 1; // bit 7 + }; // RAM9 bitfield + + /// register _LCD_RAM9 reset value + #define sfr_LCD_RAM9_RESET_VALUE ((uint8_t) 0x00) + + } RAM9; + + + /** LCD display memory 10 (RAM10 at 0x5416) */ + union { + + /// bytewise access to RAM10 + uint8_t byte; + + /// bitwise access to register RAM10 + struct { + BITS S224 : 1; // bit 0 + BITS S225 : 1; // bit 1 + BITS S226 : 1; // bit 2 + BITS S227 : 1; // bit 3 + BITS S300 : 1; // bit 4 + BITS S301 : 1; // bit 5 + BITS S302 : 1; // bit 6 + BITS S303 : 1; // bit 7 + }; // RAM10 bitfield + + /// register _LCD_RAM10 reset value + #define sfr_LCD_RAM10_RESET_VALUE ((uint8_t) 0x00) + + } RAM10; + + + /** LCD display memory 11 (RAM11 at 0x5417) */ + union { + + /// bytewise access to RAM11 + uint8_t byte; + + /// bitwise access to register RAM11 + struct { + BITS S304 : 1; // bit 0 + BITS S305 : 1; // bit 1 + BITS S306 : 1; // bit 2 + BITS S307 : 1; // bit 3 + BITS S308 : 1; // bit 4 + BITS S309 : 1; // bit 5 + BITS S310 : 1; // bit 6 + BITS S311 : 1; // bit 7 + }; // RAM11 bitfield + + /// register _LCD_RAM11 reset value + #define sfr_LCD_RAM11_RESET_VALUE ((uint8_t) 0x00) + + } RAM11; + + + /** LCD display memory 12 (RAM12 at 0x5418) */ + union { + + /// bytewise access to RAM12 + uint8_t byte; + + /// bitwise access to register RAM12 + struct { + BITS S312 : 1; // bit 0 + BITS S313 : 1; // bit 1 + BITS S314 : 1; // bit 2 + BITS S315 : 1; // bit 3 + BITS S316 : 1; // bit 4 + BITS S317 : 1; // bit 5 + BITS S318 : 1; // bit 6 + BITS S319 : 1; // bit 7 + }; // RAM12 bitfield + + /// register _LCD_RAM12 reset value + #define sfr_LCD_RAM12_RESET_VALUE ((uint8_t) 0x00) + + } RAM12; + + + /** LCD display memory 13 (RAM13 at 0x5419) */ + union { + + /// bytewise access to RAM13 + uint8_t byte; + + /// bitwise access to register RAM13 + struct { + BITS S320 : 1; // bit 0 + BITS S321 : 1; // bit 1 + BITS S322 : 1; // bit 2 + BITS S323 : 1; // bit 3 + BITS S324 : 1; // bit 4 + BITS S325 : 1; // bit 5 + BITS S326 : 1; // bit 6 + BITS S327 : 1; // bit 7 + }; // RAM13 bitfield + + /// register _LCD_RAM13 reset value + #define sfr_LCD_RAM13_RESET_VALUE ((uint8_t) 0x00) + + } RAM13; + +} LCD_t; + +/// access to LCD SFR registers +#define sfr_LCD (*((LCD_t*) 0x5400)) + + +//------------------------ +// Module OPT +//------------------------ + +/** struct containing OPT module registers */ +typedef struct { + + /** Read-out protection (ROP) (OPT0 at 0x4800) */ + union { + + /// bytewise access to OPT0 + uint8_t byte; + + /// skip bitwise access to register OPT0 + + /// register _OPT_OPT0 reset value + #define sfr_OPT_OPT0_RESET_VALUE ((uint8_t) 0xAA) + + } OPT0; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** User boot code (UBC) (OPT1 at 0x4802) */ + union { + + /// bytewise access to OPT1 + uint8_t byte; + + /// skip bitwise access to register OPT1 + + /// register _OPT_OPT1 reset value + #define sfr_OPT_OPT1_RESET_VALUE ((uint8_t) 0x00) + + } OPT1; + + + /// Reserved register (5B) + uint8_t Reserved_2[5]; + + + /** Watchdog option (OPT3 at 0x4808) */ + union { + + /// bytewise access to OPT3 + uint8_t byte; + + /// skip bitwise access to register OPT3 + + /// register _OPT_OPT3 reset value + #define sfr_OPT_OPT3_RESET_VALUE ((uint8_t) 0x00) + + } OPT3; + + + /** Clock option (OPT4 at 0x4809) */ + union { + + /// bytewise access to OPT4 + uint8_t byte; + + /// skip bitwise access to register OPT4 + + /// register _OPT_OPT4 reset value + #define sfr_OPT_OPT4_RESET_VALUE ((uint8_t) 0x00) + + } OPT4; + + + /** Brownout reset (BOR) (OPT5 at 0x480a) */ + union { + + /// bytewise access to OPT5 + uint8_t byte; + + /// skip bitwise access to register OPT5 + + /// register _OPT_OPT5 reset value + #define sfr_OPT_OPT5_RESET_VALUE ((uint8_t) 0x00) + + } OPT5; + + + /** Bootloader (high byte) (OPTBL_H at 0x480b) */ + union { + + /// bytewise access to OPTBL_H + uint8_t byte; + + /// skip bitwise access to register OPTBL_H + + /// register _OPT_OPTBL_H reset value + #define sfr_OPT_OPTBL_H_RESET_VALUE ((uint8_t) 0x00) + + } OPTBL_H; + + + /** Bootloader (low byte) (OPTBL_L at 0x480c) */ + union { + + /// bytewise access to OPTBL_L + uint8_t byte; + + /// skip bitwise access to register OPTBL_L + + /// register _OPT_OPTBL_L reset value + #define sfr_OPT_OPTBL_L_RESET_VALUE ((uint8_t) 0x00) + + } OPTBL_L; + +} OPT_t; + +/// access to OPT SFR registers +#define sfr_OPT (*((OPT_t*) 0x4800)) + + +//------------------------ +// Module PWR +//------------------------ + +/** struct containing PWR module registers */ +typedef struct { + + /** Power control and status register 1 (CSR1 at 0x50b2) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// bitwise access to register CSR1 + struct { + BITS PVDE : 1; // bit 0 + BITS PLS : 3; // bits 1-3 + BITS PVDIEN : 1; // bit 4 + BITS PVDIF : 1; // bit 5 + BITS PVDOF : 1; // bit 6 + BITS : 1; // 1 bit + }; // CSR1 bitfield + + /// register _PWR_CSR1 reset value + #define sfr_PWR_CSR1_RESET_VALUE ((uint8_t) 0x00) + + } CSR1; + + + /** Power control and status register 2 (CSR2 at 0x50b3) */ + union { + + /// bytewise access to CSR2 + uint8_t byte; + + /// bitwise access to register CSR2 + struct { + BITS VREFINTF : 1; // bit 0 + BITS ULP : 1; // bit 1 + BITS FWU : 1; // bit 2 + BITS : 5; // 5 bits + }; // CSR2 bitfield + + /// register _PWR_CSR2 reset value + #define sfr_PWR_CSR2_RESET_VALUE ((uint8_t) 0x00) + + } CSR2; + +} PWR_t; + +/// access to PWR SFR registers +#define sfr_PWR (*((PWR_t*) 0x50b2)) + + +//------------------------ +// Module PORT +//------------------------ + +/** struct containing PORTA module registers */ +typedef struct { + + /** Port A data output latch register (ODR at 0x5000) */ + union { + + /// bytewise access to ODR + uint8_t byte; + + /// bitwise access to register ODR + struct { + BITS ODR0 : 1; // bit 0 + BITS ODR1 : 1; // bit 1 + BITS ODR2 : 1; // bit 2 + BITS ODR3 : 1; // bit 3 + BITS ODR4 : 1; // bit 4 + BITS ODR5 : 1; // bit 5 + BITS ODR6 : 1; // bit 6 + BITS ODR7 : 1; // bit 7 + }; // ODR bitfield + + /// register _PORT_ODR reset value + #define sfr_PORT_ODR_RESET_VALUE ((uint8_t) 0x00) + + } ODR; + + + /** Port A input pin value register (IDR at 0x5001) */ + union { + + /// bytewise access to IDR + uint8_t byte; + + /// bitwise access to register IDR + struct { + BITS IDR0 : 1; // bit 0 + BITS IDR1 : 1; // bit 1 + BITS IDR2 : 1; // bit 2 + BITS IDR3 : 1; // bit 3 + BITS IDR4 : 1; // bit 4 + BITS IDR5 : 1; // bit 5 + BITS IDR6 : 1; // bit 6 + BITS IDR7 : 1; // bit 7 + }; // IDR bitfield + + /// register _PORT_IDR reset value + #define sfr_PORT_IDR_RESET_VALUE ((uint8_t) 0x00) + + } IDR; + + + /** Port A data direction register (DDR at 0x5002) */ + union { + + /// bytewise access to DDR + uint8_t byte; + + /// bitwise access to register DDR + struct { + BITS DDR0 : 1; // bit 0 + BITS DDR1 : 1; // bit 1 + BITS DDR2 : 1; // bit 2 + BITS DDR3 : 1; // bit 3 + BITS DDR4 : 1; // bit 4 + BITS DDR5 : 1; // bit 5 + BITS DDR6 : 1; // bit 6 + BITS DDR7 : 1; // bit 7 + }; // DDR bitfield + + /// register _PORT_DDR reset value + #define sfr_PORT_DDR_RESET_VALUE ((uint8_t) 0x00) + + } DDR; + + + /** Port A control register 1 (CR1 at 0x5003) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS C10 : 1; // bit 0 + BITS C11 : 1; // bit 1 + BITS C12 : 1; // bit 2 + BITS C13 : 1; // bit 3 + BITS C14 : 1; // bit 4 + BITS C15 : 1; // bit 5 + BITS C16 : 1; // bit 6 + BITS C17 : 1; // bit 7 + }; // CR1 bitfield + + /// register _PORT_CR1 reset value + #define sfr_PORT_CR1_RESET_VALUE ((uint8_t) 0x01) + + } CR1; + + + /** Port A control register 2 (CR2 at 0x5004) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS C20 : 1; // bit 0 + BITS C21 : 1; // bit 1 + BITS C22 : 1; // bit 2 + BITS C23 : 1; // bit 3 + BITS C24 : 1; // bit 4 + BITS C25 : 1; // bit 5 + BITS C26 : 1; // bit 6 + BITS C27 : 1; // bit 7 + }; // CR2 bitfield + + /// register _PORT_CR2 reset value + #define sfr_PORT_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + +} PORT_t; + +/// access to PORTA SFR registers +#define sfr_PORTA (*((PORT_t*) 0x5000)) + + +/// access to PORTB SFR registers +#define sfr_PORTB (*((PORT_t*) 0x5005)) + + +/// access to PORTC SFR registers +#define sfr_PORTC (*((PORT_t*) 0x500a)) + + +/// access to PORTD SFR registers +#define sfr_PORTD (*((PORT_t*) 0x500f)) + + +/// access to PORTE SFR registers +#define sfr_PORTE (*((PORT_t*) 0x5014)) + + +/// access to PORTF SFR registers +#define sfr_PORTF (*((PORT_t*) 0x5019)) + + +//------------------------ +// Module REMAP +//------------------------ + +/** struct containing REMAP module registers */ +typedef struct { + + /** Remapping register 1 (SYSCFG_RMPCR1 at 0x509e) */ + union { + + /// bytewise access to SYSCFG_RMPCR1 + uint8_t byte; + + /// bitwise access to register SYSCFG_RMPCR1 + struct { + BITS ADC1DMA_REMAP : 2; // bits 0-1 + BITS TIM4DMA_REMAP : 2; // bits 2-3 + BITS USART1TR_REMAP : 2; // bits 4-5 + BITS USART1CK_REMAP : 1; // bit 6 + BITS SPI1_REMAP : 1; // bit 7 + }; // SYSCFG_RMPCR1 bitfield + + /// register _REMAP_SYSCFG_RMPCR1 reset value + #define sfr_REMAP_SYSCFG_RMPCR1_RESET_VALUE ((uint8_t) 0x00) + + } SYSCFG_RMPCR1; + + + /** Remapping register 2 (SYSCFG_RMPCR2 at 0x509f) */ + union { + + /// bytewise access to SYSCFG_RMPCR2 + uint8_t byte; + + /// bitwise access to register SYSCFG_RMPCR2 + struct { + BITS ADC1TRIG_REMAP : 1; // bit 0 + BITS TIM2TRIG_REMAP : 1; // bit 1 + BITS TIM3TRIG_REMAP : 1; // bit 2 + BITS TIM2TRIGLSE_REMAP : 1; // bit 3 + BITS TIM3TRIGLSE_REMAP : 1; // bit 4 + BITS : 3; // 3 bits + }; // SYSCFG_RMPCR2 bitfield + + /// register _REMAP_SYSCFG_RMPCR2 reset value + #define sfr_REMAP_SYSCFG_RMPCR2_RESET_VALUE ((uint8_t) 0x00) + + } SYSCFG_RMPCR2; + +} REMAP_t; + +/// access to REMAP SFR registers +#define sfr_REMAP (*((REMAP_t*) 0x509e)) + + +//------------------------ +// Module RI +//------------------------ + +/** struct containing RI module registers */ +typedef struct { + + /** Timer input capture routing register 1 (ICR1 at 0x5431) */ + union { + + /// bytewise access to ICR1 + uint8_t byte; + + /// bitwise access to register ICR1 + struct { + BITS IC2CS : 5; // bits 0-4 + BITS : 3; // 3 bits + }; // ICR1 bitfield + + /// register _RI_ICR1 reset value + #define sfr_RI_ICR1_RESET_VALUE ((uint8_t) 0x00) + + } ICR1; + + + /** Timer input capture routing register 2 (ICR2 at 0x5432) */ + union { + + /// bytewise access to ICR2 + uint8_t byte; + + /// bitwise access to register ICR2 + struct { + BITS IC3CS : 5; // bits 0-4 + BITS : 3; // 3 bits + }; // ICR2 bitfield + + /// register _RI_ICR2 reset value + #define sfr_RI_ICR2_RESET_VALUE ((uint8_t) 0x00) + + } ICR2; + + + /** I/O input register 1 (IOIR1 at 0x5433) */ + union { + + /// bytewise access to IOIR1 + uint8_t byte; + + /// bitwise access to register IOIR1 + struct { + BITS CH1I : 1; // bit 0 + BITS CH4I : 1; // bit 1 + BITS CH7I : 1; // bit 2 + BITS CH10I : 1; // bit 3 + BITS CH13I : 1; // bit 4 + BITS CH16I : 1; // bit 5 + BITS CH19I : 1; // bit 6 + BITS CH22I : 1; // bit 7 + }; // IOIR1 bitfield + + /// register _RI_IOIR1 reset value + #define sfr_RI_IOIR1_RESET_VALUE ((uint8_t) 0x00) + + } IOIR1; + + + /** I/O input register 2 (IOIR2 at 0x5434) */ + union { + + /// bytewise access to IOIR2 + uint8_t byte; + + /// bitwise access to register IOIR2 + struct { + BITS CH2I : 1; // bit 0 + BITS CH5I : 1; // bit 1 + BITS CH8I : 1; // bit 2 + BITS CH11I : 1; // bit 3 + BITS CH14I : 1; // bit 4 + BITS CH17I : 1; // bit 5 + BITS CH20I : 1; // bit 6 + BITS CH23I : 1; // bit 7 + }; // IOIR2 bitfield + + /// register _RI_IOIR2 reset value + #define sfr_RI_IOIR2_RESET_VALUE ((uint8_t) 0x00) + + } IOIR2; + + + /** I/O input register 3 (IOIR3 at 0x5435) */ + union { + + /// bytewise access to IOIR3 + uint8_t byte; + + /// bitwise access to register IOIR3 + struct { + BITS CH3I : 1; // bit 0 + BITS CH6I : 1; // bit 1 + BITS CH9I : 1; // bit 2 + BITS CH12I : 1; // bit 3 + BITS CH15I : 1; // bit 4 + BITS CH18I : 1; // bit 5 + BITS CH21I : 1; // bit 6 + BITS CH24I : 1; // bit 7 + }; // IOIR3 bitfield + + /// register _RI_IOIR3 reset value + #define sfr_RI_IOIR3_RESET_VALUE ((uint8_t) 0x00) + + } IOIR3; + + + /** I/O control mode register 1 (IOCMR1 at 0x5436) */ + union { + + /// bytewise access to IOCMR1 + uint8_t byte; + + /// bitwise access to register IOCMR1 + struct { + BITS CH1M : 1; // bit 0 + BITS CH4M : 1; // bit 1 + BITS CH7M : 1; // bit 2 + BITS CH10M : 1; // bit 3 + BITS CH13M : 1; // bit 4 + BITS CH16M : 1; // bit 5 + BITS CH19M : 1; // bit 6 + BITS CH22M : 1; // bit 7 + }; // IOCMR1 bitfield + + /// register _RI_IOCMR1 reset value + #define sfr_RI_IOCMR1_RESET_VALUE ((uint8_t) 0x00) + + } IOCMR1; + + + /** I/O control mode register 2 (IOCMR2 at 0x5437) */ + union { + + /// bytewise access to IOCMR2 + uint8_t byte; + + /// bitwise access to register IOCMR2 + struct { + BITS CH2M : 1; // bit 0 + BITS CH5M : 1; // bit 1 + BITS CH8M : 1; // bit 2 + BITS CH11M : 1; // bit 3 + BITS CH14M : 1; // bit 4 + BITS CH17M : 1; // bit 5 + BITS CH20M : 1; // bit 6 + BITS CH23M : 1; // bit 7 + }; // IOCMR2 bitfield + + /// register _RI_IOCMR2 reset value + #define sfr_RI_IOCMR2_RESET_VALUE ((uint8_t) 0x00) + + } IOCMR2; + + + /** I/O control mode register 3 (IOCMR3 at 0x5438) */ + union { + + /// bytewise access to IOCMR3 + uint8_t byte; + + /// bitwise access to register IOCMR3 + struct { + BITS CH3M : 1; // bit 0 + BITS CH6M : 1; // bit 1 + BITS CH9M : 1; // bit 2 + BITS CH12M : 1; // bit 3 + BITS CH53M : 1; // bit 4 + BITS CH18M : 1; // bit 5 + BITS CH21M : 1; // bit 6 + BITS CH24M : 1; // bit 7 + }; // IOCMR3 bitfield + + /// register _RI_IOCMR3 reset value + #define sfr_RI_IOCMR3_RESET_VALUE ((uint8_t) 0x00) + + } IOCMR3; + + + /** I/O switch register 1 (IOSR1 at 0x5439) */ + union { + + /// bytewise access to IOSR1 + uint8_t byte; + + /// bitwise access to register IOSR1 + struct { + BITS CH1E : 1; // bit 0 + BITS CH4E : 1; // bit 1 + BITS CH7E : 1; // bit 2 + BITS CH10E : 1; // bit 3 + BITS CH13E : 1; // bit 4 + BITS CH16E : 1; // bit 5 + BITS CH19E : 1; // bit 6 + BITS CH22E : 1; // bit 7 + }; // IOSR1 bitfield + + /// register _RI_IOSR1 reset value + #define sfr_RI_IOSR1_RESET_VALUE ((uint8_t) 0x00) + + } IOSR1; + + + /** I/O switch register 2 (IOSR2 at 0x543a) */ + union { + + /// bytewise access to IOSR2 + uint8_t byte; + + /// bitwise access to register IOSR2 + struct { + BITS CH2E : 1; // bit 0 + BITS CH5E : 1; // bit 1 + BITS CH8E : 1; // bit 2 + BITS CH11E : 1; // bit 3 + BITS CH14E : 1; // bit 4 + BITS CH17E : 1; // bit 5 + BITS CH20E : 1; // bit 6 + BITS CH23E : 1; // bit 7 + }; // IOSR2 bitfield + + /// register _RI_IOSR2 reset value + #define sfr_RI_IOSR2_RESET_VALUE ((uint8_t) 0x00) + + } IOSR2; + + + /** I/O switch register 3 (IOSR3 at 0x543b) */ + union { + + /// bytewise access to IOSR3 + uint8_t byte; + + /// bitwise access to register IOSR3 + struct { + BITS CH3E : 1; // bit 0 + BITS CH6E : 1; // bit 1 + BITS CH9E : 1; // bit 2 + BITS CH12E : 1; // bit 3 + BITS CH15E : 1; // bit 4 + BITS CH18E : 1; // bit 5 + BITS CH21E : 1; // bit 6 + BITS CH24E : 1; // bit 7 + }; // IOSR3 bitfield + + /// register _RI_IOSR3 reset value + #define sfr_RI_IOSR3_RESET_VALUE ((uint8_t) 0x00) + + } IOSR3; + + + /** I/O group control register (IOGCR at 0x543c) */ + union { + + /// bytewise access to IOGCR + uint8_t byte; + + /// bitwise access to register IOGCR + struct { + BITS IOM1 : 2; // bits 0-1 + BITS IOM2 : 2; // bits 2-3 + BITS IOM3 : 2; // bits 4-5 + BITS : 2; // 2 bits + }; // IOGCR bitfield + + /// register _RI_IOGCR reset value + #define sfr_RI_IOGCR_RESET_VALUE ((uint8_t) 0x3F) + + } IOGCR; + + + /** Analog switch register 1 (ASCR1 at 0x543d) */ + union { + + /// bytewise access to ASCR1 + uint8_t byte; + + /// bitwise access to register ASCR1 + struct { + BITS AS0 : 1; // bit 0 + BITS AS1 : 1; // bit 1 + BITS AS2 : 1; // bit 2 + BITS AS3 : 1; // bit 3 + BITS AS4 : 1; // bit 4 + BITS AS5 : 1; // bit 5 + BITS AS6 : 1; // bit 6 + BITS AS7 : 1; // bit 7 + }; // ASCR1 bitfield + + /// register _RI_ASCR1 reset value + #define sfr_RI_ASCR1_RESET_VALUE ((uint8_t) 0x00) + + } ASCR1; + + + /** Analog switch register 2 (ASCR2 at 0x543e) */ + union { + + /// bytewise access to ASCR2 + uint8_t byte; + + /// bitwise access to register ASCR2 + struct { + BITS AS8 : 1; // bit 0 + BITS : 5; // 5 bits + BITS AS14 : 1; // bit 6 + BITS : 1; // 1 bit + }; // ASCR2 bitfield + + /// register _RI_ASCR2 reset value + #define sfr_RI_ASCR2_RESET_VALUE ((uint8_t) 0x00) + + } ASCR2; + + + /** Resistor control register 1 (RCR at 0x543f) */ + union { + + /// bytewise access to RCR + uint8_t byte; + + /// bitwise access to register RCR + struct { + BITS KPU10 : 1; // bit 0 + BITS KPU400 : 1; // bit 1 + BITS KPD10 : 1; // bit 2 + BITS KPD400 : 1; // bit 3 + BITS : 4; // 4 bits + }; // RCR bitfield + + /// register _RI_RCR reset value + #define sfr_RI_RCR_RESET_VALUE ((uint8_t) 0x00) + + } RCR; + +} RI_t; + +/// access to RI SFR registers +#define sfr_RI (*((RI_t*) 0x5431)) + + +//------------------------ +// Module RST +//------------------------ + +/** struct containing RST module registers */ +typedef struct { + + /** Reset control register (CR at 0x50b0) */ + union { + + /// bytewise access to CR + uint8_t byte; + + /// bitwise access to register CR + struct { + BITS RSTPIN_KEY : 8; // bits 0-7 + }; // CR bitfield + + /// register _RST_CR reset value + #define sfr_RST_CR_RESET_VALUE ((uint8_t) 0x00) + + } CR; + + + /** Reset status register (SR at 0x50b1) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS PORF : 1; // bit 0 + BITS IWDGF : 1; // bit 1 + BITS ILLOPF : 1; // bit 2 + BITS SWIMF : 1; // bit 3 + BITS WWDGF : 1; // bit 4 + BITS BORF : 1; // bit 5 + BITS : 2; // 2 bits + }; // SR bitfield + + /// register _RST_SR reset value + #define sfr_RST_SR_RESET_VALUE ((uint8_t) 0x01) + + } SR; + +} RST_t; + +/// access to RST SFR registers +#define sfr_RST (*((RST_t*) 0x50b0)) + + +//------------------------ +// Module RTC +//------------------------ + +/** struct containing RTC module registers */ +typedef struct { + + /** Time register 1 (TR1 at 0x5140) */ + union { + + /// bytewise access to TR1 + uint8_t byte; + + /// bitwise access to register TR1 + struct { + BITS SU : 4; // bits 0-3 + BITS ST : 4; // bits 4-7 + }; // TR1 bitfield + + /// register _RTC_TR1 reset value + #define sfr_RTC_TR1_RESET_VALUE ((uint8_t) 0x00) + + } TR1; + + + /** Time register 2 (TR2 at 0x5141) */ + union { + + /// bytewise access to TR2 + uint8_t byte; + + /// bitwise access to register TR2 + struct { + BITS MNU : 4; // bits 0-3 + BITS MNT : 4; // bits 4-7 + }; // TR2 bitfield + + /// register _RTC_TR2 reset value + #define sfr_RTC_TR2_RESET_VALUE ((uint8_t) 0x00) + + } TR2; + + + /** Time register 3 (TR3 at 0x5142) */ + union { + + /// bytewise access to TR3 + uint8_t byte; + + /// bitwise access to register TR3 + struct { + BITS HU : 4; // bits 0-3 + BITS HT : 2; // bits 4-5 + BITS PM : 1; // bit 6 + BITS : 1; // 1 bit + }; // TR3 bitfield + + /// register _RTC_TR3 reset value + #define sfr_RTC_TR3_RESET_VALUE ((uint8_t) 0x00) + + } TR3; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** Date register 1 (DR1 at 0x5144) */ + union { + + /// bytewise access to DR1 + uint8_t byte; + + /// bitwise access to register DR1 + struct { + BITS DU : 4; // bits 0-3 + BITS DT : 2; // bits 4-5 + BITS : 2; // 2 bits + }; // DR1 bitfield + + /// register _RTC_DR1 reset value + #define sfr_RTC_DR1_RESET_VALUE ((uint8_t) 0x01) + + } DR1; + + + /** Date register 2 (DR2 at 0x5145) */ + union { + + /// bytewise access to DR2 + uint8_t byte; + + /// bitwise access to register DR2 + struct { + BITS MU : 4; // bits 0-3 + BITS MT : 1; // bit 4 + BITS WDU : 3; // bits 5-7 + }; // DR2 bitfield + + /// register _RTC_DR2 reset value + #define sfr_RTC_DR2_RESET_VALUE ((uint8_t) 0x21) + + } DR2; + + + /** Date register 3 (DR3 at 0x5146) */ + union { + + /// bytewise access to DR3 + uint8_t byte; + + /// bitwise access to register DR3 + struct { + BITS YU : 4; // bits 0-3 + BITS YT : 4; // bits 4-7 + }; // DR3 bitfield + + /// register _RTC_DR3 reset value + #define sfr_RTC_DR3_RESET_VALUE ((uint8_t) 0x00) + + } DR3; + + + /// Reserved register (1B) + uint8_t Reserved_2[1]; + + + /** Control register 1 (CR1 at 0x5148) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS WUCKSEL : 4; // bits 0-3 + BITS : 1; // 1 bit + BITS RATIO : 1; // bit 5 + BITS FMT : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR1 bitfield + + /// register _RTC_CR1 reset value + #define sfr_RTC_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Control register 2 (CR2 at 0x5149) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS ALRAE : 1; // bit 0 + BITS : 1; // 1 bit + BITS WUTE : 1; // bit 2 + BITS : 1; // 1 bit + BITS ALRAIE : 1; // bit 4 + BITS : 1; // 1 bit + BITS WUTIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _RTC_CR2 reset value + #define sfr_RTC_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** Control register 3 (CR3 at 0x514a) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS ADD1H : 1; // bit 0 + BITS SUB1H : 1; // bit 1 + BITS BCK : 1; // bit 2 + BITS : 1; // 1 bit + BITS POL : 1; // bit 4 + BITS OSEL : 2; // bits 5-6 + BITS COE : 1; // bit 7 + }; // CR3 bitfield + + /// register _RTC_CR3 reset value + #define sfr_RTC_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /// Reserved register (1B) + uint8_t Reserved_3[1]; + + + /** Initialization and status register 1 (ISR1 at 0x514c) */ + union { + + /// bytewise access to ISR1 + uint8_t byte; + + /// bitwise access to register ISR1 + struct { + BITS ALRAWF : 1; // bit 0 + BITS RECALPF : 1; // bit 1 + BITS WUTWF : 1; // bit 2 + BITS SHPF : 1; // bit 3 + BITS INITS : 1; // bit 4 + BITS RSF : 1; // bit 5 + BITS INITF : 1; // bit 6 + BITS INIT : 1; // bit 7 + }; // ISR1 bitfield + + /// register _RTC_ISR1 reset value + #define sfr_RTC_ISR1_RESET_VALUE ((uint8_t) 0x00) + + } ISR1; + + + /** Initialization and Status register 2 (ISR2 at 0x514d) */ + union { + + /// bytewise access to ISR2 + uint8_t byte; + + /// bitwise access to register ISR2 + struct { + BITS ALRAF : 1; // bit 0 + BITS : 1; // 1 bit + BITS WUTF : 1; // bit 2 + BITS : 2; // 2 bits + BITS TAMP1F : 1; // bit 5 + BITS TAMP2F : 1; // bit 6 + BITS TAMP3F : 1; // bit 7 + }; // ISR2 bitfield + + /// register _RTC_ISR2 reset value + #define sfr_RTC_ISR2_RESET_VALUE ((uint8_t) 0x00) + + } ISR2; + + + /// Reserved register (2B) + uint8_t Reserved_4[2]; + + + /** Synchronous prescaler register high (SPRERH at 0x5150) */ + union { + + /// bytewise access to SPRERH + uint8_t byte; + + /// bitwise access to register SPRERH + struct { + BITS PREDIV_S8 : 1; // bit 0 + BITS PREDIV_S9 : 1; // bit 1 + BITS PREDIV_S10 : 1; // bit 2 + BITS PREDIV_S11 : 1; // bit 3 + BITS PREDIV_S12 : 1; // bit 4 + BITS : 3; // 3 bits + }; // SPRERH bitfield + + /// register _RTC_SPRERH reset value + #define sfr_RTC_SPRERH_RESET_VALUE ((uint8_t) 0x00) + + } SPRERH; + + + /** Synchronous prescaler register low (SPRERL at 0x5151) */ + union { + + /// bytewise access to SPRERL + uint8_t byte; + + /// bitwise access to register SPRERL + struct { + BITS PREDIV_S0 : 1; // bit 0 + BITS PREDIV_S1 : 1; // bit 1 + BITS PREDIV_S2 : 1; // bit 2 + BITS PREDIV_S3 : 1; // bit 3 + BITS PREDIV_S4 : 1; // bit 4 + BITS PREDIV_S5 : 1; // bit 5 + BITS PREDIV_S6 : 1; // bit 6 + BITS PREDIV_S7 : 1; // bit 7 + }; // SPRERL bitfield + + /// register _RTC_SPRERL reset value + #define sfr_RTC_SPRERL_RESET_VALUE ((uint8_t) 0xFF) + + } SPRERL; + + + /** Asynchronous prescaler register (APRER at 0x5152) */ + union { + + /// bytewise access to APRER + uint8_t byte; + + /// bitwise access to register APRER + struct { + BITS PREDIV_A : 7; // bits 0-6 + BITS : 1; // 1 bit + }; // APRER bitfield + + /// register _RTC_APRER reset value + #define sfr_RTC_APRER_RESET_VALUE ((uint8_t) 0x7F) + + } APRER; + + + /// Reserved register (1B) + uint8_t Reserved_5[1]; + + + /** Wakeup timer register high (WUTRH at 0x5154) */ + union { + + /// bytewise access to WUTRH + uint8_t byte; + + /// bitwise access to register WUTRH + struct { + BITS WUT8 : 1; // bit 0 + BITS WUT9 : 1; // bit 1 + BITS WUT10 : 1; // bit 2 + BITS WUT11 : 1; // bit 3 + BITS WUT12 : 1; // bit 4 + BITS WUT13 : 1; // bit 5 + BITS WUT14 : 1; // bit 6 + BITS WUT15 : 1; // bit 7 + }; // WUTRH bitfield + + /// register _RTC_WUTRH reset value + #define sfr_RTC_WUTRH_RESET_VALUE ((uint8_t) 0xFF) + + } WUTRH; + + + /** Wakeup timer register low (WUTRL at 0x5155) */ + union { + + /// bytewise access to WUTRL + uint8_t byte; + + /// bitwise access to register WUTRL + struct { + BITS WUT0 : 1; // bit 0 + BITS WUT1 : 1; // bit 1 + BITS WUT2 : 1; // bit 2 + BITS WUT3 : 1; // bit 3 + BITS WUT4 : 1; // bit 4 + BITS WUT5 : 1; // bit 5 + BITS WUT6 : 1; // bit 6 + BITS WUT7 : 1; // bit 7 + }; // WUTRL bitfield + + /// register _RTC_WUTRL reset value + #define sfr_RTC_WUTRL_RESET_VALUE ((uint8_t) 0xFF) + + } WUTRL; + + + /// Reserved register (3B) + uint8_t Reserved_6[3]; + + + /** Write protection register (WPR at 0x5159) */ + union { + + /// bytewise access to WPR + uint8_t byte; + + /// skip bitwise access to register WPR + + /// register _RTC_WPR reset value + #define sfr_RTC_WPR_RESET_VALUE ((uint8_t) 0x00) + + } WPR; + + + /// Reserved register (2B) + uint8_t Reserved_7[2]; + + + /** Alarm A register 1 (ALRMAR1 at 0x515c) */ + union { + + /// bytewise access to ALRMAR1 + uint8_t byte; + + /// bitwise access to register ALRMAR1 + struct { + BITS ALSU : 4; // bits 0-3 + BITS ALST : 3; // bits 4-6 + BITS MSK1 : 1; // bit 7 + }; // ALRMAR1 bitfield + + /// register _RTC_ALRMAR1 reset value + #define sfr_RTC_ALRMAR1_RESET_VALUE ((uint8_t) 0x00) + + } ALRMAR1; + + + /** Alarm A register 2 (ALRMAR2 at 0x515d) */ + union { + + /// bytewise access to ALRMAR2 + uint8_t byte; + + /// bitwise access to register ALRMAR2 + struct { + BITS ALMNU : 4; // bits 0-3 + BITS ALMNT : 3; // bits 4-6 + BITS MSK2 : 1; // bit 7 + }; // ALRMAR2 bitfield + + /// register _RTC_ALRMAR2 reset value + #define sfr_RTC_ALRMAR2_RESET_VALUE ((uint8_t) 0x00) + + } ALRMAR2; + + + /** Alarm A register 3 (ALRMAR3 at 0x515e) */ + union { + + /// bytewise access to ALRMAR3 + uint8_t byte; + + /// bitwise access to register ALRMAR3 + struct { + BITS ALHU : 4; // bits 0-3 + BITS ALHT : 2; // bits 4-5 + BITS PM : 1; // bit 6 + BITS MSK3 : 1; // bit 7 + }; // ALRMAR3 bitfield + + /// register _RTC_ALRMAR3 reset value + #define sfr_RTC_ALRMAR3_RESET_VALUE ((uint8_t) 0x00) + + } ALRMAR3; + + + /** Alarm A register 4 (ALRMAR4 at 0x515f) */ + union { + + /// bytewise access to ALRMAR4 + uint8_t byte; + + /// bitwise access to register ALRMAR4 + struct { + BITS ALDU : 4; // bits 0-3 + BITS ALDT : 2; // bits 4-5 + BITS WDSEL : 1; // bit 6 + BITS MSK4 : 1; // bit 7 + }; // ALRMAR4 bitfield + + /// register _RTC_ALRMAR4 reset value + #define sfr_RTC_ALRMAR4_RESET_VALUE ((uint8_t) 0x00) + + } ALRMAR4; + +} RTC_t; + +/// access to RTC SFR registers +#define sfr_RTC (*((RTC_t*) 0x5140)) + + +//------------------------ +// Module SPI1 +//------------------------ + +/** struct containing SPI1 module registers */ +typedef struct { + + /** SPI1 control register 1 (CR1 at 0x5200) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CPHA : 1; // bit 0 + BITS CPOL : 1; // bit 1 + BITS MSTR : 1; // bit 2 + BITS BR : 3; // bits 3-5 + BITS SPE : 1; // bit 6 + BITS LSBFIRST : 1; // bit 7 + }; // CR1 bitfield + + /// register _SPI1_CR1 reset value + #define sfr_SPI1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** SPI1 control register 2 (CR2 at 0x5201) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SSI : 1; // bit 0 + BITS SSM : 1; // bit 1 + BITS RXONLY : 1; // bit 2 + BITS : 1; // 1 bit + BITS CRCNEXT : 1; // bit 4 + BITS CRCEN : 1; // bit 5 + BITS BDOE : 1; // bit 6 + BITS BDM : 1; // bit 7 + }; // CR2 bitfield + + /// register _SPI1_CR2 reset value + #define sfr_SPI1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** SPI1 interrupt control register (ICR at 0x5202) */ + union { + + /// bytewise access to ICR + uint8_t byte; + + /// bitwise access to register ICR + struct { + BITS RXDMAEN : 1; // bit 0 + BITS TXDMAEN : 1; // bit 1 + BITS : 2; // 2 bits + BITS WKIE : 1; // bit 4 + BITS ERRIE : 1; // bit 5 + BITS RXIE : 1; // bit 6 + BITS TXIE : 1; // bit 7 + }; // ICR bitfield + + /// register _SPI1_ICR reset value + #define sfr_SPI1_ICR_RESET_VALUE ((uint8_t) 0x00) + + } ICR; + + + /** SPI1 status register (SR at 0x5203) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS RXNE : 1; // bit 0 + BITS TXE : 1; // bit 1 + BITS : 1; // 1 bit + BITS WKUP : 1; // bit 3 + BITS CRCERR : 1; // bit 4 + BITS MODF : 1; // bit 5 + BITS OVR : 1; // bit 6 + BITS BSY : 1; // bit 7 + }; // SR bitfield + + /// register _SPI1_SR reset value + #define sfr_SPI1_SR_RESET_VALUE ((uint8_t) 0x02) + + } SR; + + + /** SPI1 data register (DR at 0x5204) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _SPI1_DR reset value + #define sfr_SPI1_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** SPI1 CRC polynomial register (CRCPR at 0x5205) */ + union { + + /// bytewise access to CRCPR + uint8_t byte; + + /// bitwise access to register CRCPR + struct { + BITS CRCPOLY : 8; // bits 0-7 + }; // CRCPR bitfield + + /// register _SPI1_CRCPR reset value + #define sfr_SPI1_CRCPR_RESET_VALUE ((uint8_t) 0x07) + + } CRCPR; + + + /** SPI1 Rx CRC register (RXCRCR at 0x5206) */ + union { + + /// bytewise access to RXCRCR + uint8_t byte; + + /// bitwise access to register RXCRCR + struct { + BITS RXCRC : 8; // bits 0-7 + }; // RXCRCR bitfield + + /// register _SPI1_RXCRCR reset value + #define sfr_SPI1_RXCRCR_RESET_VALUE ((uint8_t) 0x00) + + } RXCRCR; + + + /** SPI1 Tx CRC register (TXCRCR at 0x5207) */ + union { + + /// bytewise access to TXCRCR + uint8_t byte; + + /// bitwise access to register TXCRCR + struct { + BITS TXCRC : 7; // bits 0-6 + BITS : 1; // 1 bit + }; // TXCRCR bitfield + + /// register _SPI1_TXCRCR reset value + #define sfr_SPI1_TXCRCR_RESET_VALUE ((uint8_t) 0x00) + + } TXCRCR; + +} SPI1_t; + +/// access to SPI1 SFR registers +#define sfr_SPI1 (*((SPI1_t*) 0x5200)) + + +//------------------------ +// Module SWIM +//------------------------ + +/** struct containing SWIM module registers */ +typedef struct { + + /** SWIM control status register (CSR at 0x7f80) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// skip bitwise access to register CSR + + /// register _SWIM_CSR reset value + #define sfr_SWIM_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + +} SWIM_t; + +/// access to SWIM SFR registers +#define sfr_SWIM (*((SWIM_t*) 0x7f80)) + + +//------------------------ +// Module TIM1 +//------------------------ + +/** struct containing TIM1 module registers */ +typedef struct { + + /** TIM1 control register 1 (CR1 at 0x52b0) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS DIR : 1; // bit 4 + BITS CMS : 2; // bits 5-6 + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM1_CR1 reset value + #define sfr_TIM1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM1 control register 2 (CR2 at 0x52b1) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS CCPC : 1; // bit 0 + BITS : 1; // 1 bit + BITS COMS : 1; // bit 2 + BITS CCDS : 1; // bit 3 + BITS MMS : 3; // bits 4-6 + BITS TI1S : 1; // bit 7 + }; // CR2 bitfield + + /// register _TIM1_CR2 reset value + #define sfr_TIM1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** TIM1 Slave mode control register (SMCR at 0x52b2) */ + union { + + /// bytewise access to SMCR + uint8_t byte; + + /// bitwise access to register SMCR + struct { + BITS SMS : 3; // bits 0-2 + BITS OCCS : 1; // bit 3 + BITS TS : 3; // bits 4-6 + BITS MSM : 1; // bit 7 + }; // SMCR bitfield + + /// register _TIM1_SMCR reset value + #define sfr_TIM1_SMCR_RESET_VALUE ((uint8_t) 0x00) + + } SMCR; + + + /** TIM1 external trigger register (ETR at 0x52b3) */ + union { + + /// bytewise access to ETR + uint8_t byte; + + /// bitwise access to register ETR + struct { + BITS ETF : 4; // bits 0-3 + BITS ETPS : 2; // bits 4-5 + BITS ECE : 1; // bit 6 + BITS ETP : 1; // bit 7 + }; // ETR bitfield + + /// register _TIM1_ETR reset value + #define sfr_TIM1_ETR_RESET_VALUE ((uint8_t) 0x00) + + } ETR; + + + /** TIM1 DMA1 request enable register (DER at 0x52b4) */ + union { + + /// bytewise access to DER + uint8_t byte; + + /// bitwise access to register DER + struct { + BITS UDE : 1; // bit 0 + BITS CC1DE : 1; // bit 1 + BITS CC2DE : 1; // bit 2 + BITS CC3DE : 1; // bit 3 + BITS CC4DE : 1; // bit 4 + BITS COMDE : 1; // bit 5 + BITS : 2; // 2 bits + }; // DER bitfield + + /// register _TIM1_DER reset value + #define sfr_TIM1_DER_RESET_VALUE ((uint8_t) 0x00) + + } DER; + + + /** TIM1 Interrupt enable register (IER at 0x52b5) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS CC4IE : 1; // bit 4 + BITS COMIE : 1; // bit 5 + BITS TIE : 1; // bit 6 + BITS BIE : 1; // bit 7 + }; // IER bitfield + + /// register _TIM1_IER reset value + #define sfr_TIM1_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM1 status register 1 (SR1 at 0x52b6) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS CC4IF : 1; // bit 4 + BITS COMIF : 1; // bit 5 + BITS TIF : 1; // bit 6 + BITS BIF : 1; // bit 7 + }; // SR1 bitfield + + /// register _TIM1_SR1 reset value + #define sfr_TIM1_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM1 status register 2 (SR2 at 0x52b7) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS CC4OF : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR2 bitfield + + /// register _TIM1_SR2 reset value + #define sfr_TIM1_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM1 event generation register (EGR at 0x52b8) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS CC4G : 1; // bit 4 + BITS COMG : 1; // bit 5 + BITS TG : 1; // bit 6 + BITS BG : 1; // bit 7 + }; // EGR bitfield + + /// register _TIM1_EGR reset value + #define sfr_TIM1_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM1 Capture/Compare mode register 1 (CCMR1 at 0x52b9) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS OC1FE : 1; // bit 2 + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS OC1CE : 1; // bit 7 + }; // CCMR1 bitfield + + /// register _TIM1_CCMR1 reset value + #define sfr_TIM1_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM1 Capture/Compare mode register 2 (CCMR2 at 0x52ba) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS OC2FE : 1; // bit 2 + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS OC2CE : 1; // bit 7 + }; // CCMR2 bitfield + + /// register _TIM1_CCMR2 reset value + #define sfr_TIM1_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM1 Capture/Compare mode register 3 (CCMR3 at 0x52bb) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS OC3FE : 1; // bit 2 + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS OC3CE : 1; // bit 7 + }; // CCMR3 bitfield + + /// register _TIM1_CCMR3 reset value + #define sfr_TIM1_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM1 Capture/Compare mode register 4 (CCMR4 at 0x52bc) */ + union { + + /// bytewise access to CCMR4 + uint8_t byte; + + /// bitwise access to register CCMR4 + struct { + BITS CC4S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC4PE : 1; // bit 3 + BITS OC4M : 3; // bits 4-6 + BITS OC4CE : 1; // bit 7 + }; // CCMR4 bitfield + + /// register _TIM1_CCMR4 reset value + #define sfr_TIM1_CCMR4_RESET_VALUE ((uint8_t) 0x00) + + } CCMR4; + + + /** TIM1 Capture/Compare enable register 1 (CCER1 at 0x52bd) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS CC1NE : 1; // bit 2 + BITS CC1NP : 1; // bit 3 + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS CC2NE : 1; // bit 6 + BITS CC2NP : 1; // bit 7 + }; // CCER1 bitfield + + /// register _TIM1_CCER1 reset value + #define sfr_TIM1_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM1 Capture/Compare enable register 2 (CCER2 at 0x52be) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS CC3NE : 1; // bit 2 + BITS CC3NP : 1; // bit 3 + BITS CC4E : 1; // bit 4 + BITS CC4P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER2 bitfield + + /// register _TIM1_CCER2 reset value + #define sfr_TIM1_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM1 counter high (CNTRH at 0x52bf) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT8 : 1; // bit 0 + BITS CNT9 : 1; // bit 1 + BITS CNT10 : 1; // bit 2 + BITS CNT11 : 1; // bit 3 + BITS CNT12 : 1; // bit 4 + BITS CNT13 : 1; // bit 5 + BITS CNT14 : 1; // bit 6 + BITS CNT15 : 1; // bit 7 + }; // CNTRH bitfield + + /// register _TIM1_CNTRH reset value + #define sfr_TIM1_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM1 counter low (CNTRL at 0x52c0) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT0 : 1; // bit 0 + BITS CNT1 : 1; // bit 1 + BITS CNT2 : 1; // bit 2 + BITS CNT3 : 1; // bit 3 + BITS CNT4 : 1; // bit 4 + BITS CNT5 : 1; // bit 5 + BITS CNT6 : 1; // bit 6 + BITS CNT7 : 1; // bit 7 + }; // CNTRL bitfield + + /// register _TIM1_CNTRL reset value + #define sfr_TIM1_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM1 prescaler register high (PSCRH at 0x52c1) */ + union { + + /// bytewise access to PSCRH + uint8_t byte; + + /// bitwise access to register PSCRH + struct { + BITS PSC8 : 1; // bit 0 + BITS PSC9 : 1; // bit 1 + BITS PSC10 : 1; // bit 2 + BITS PSC11 : 1; // bit 3 + BITS PSC12 : 1; // bit 4 + BITS PSC13 : 1; // bit 5 + BITS PSC14 : 1; // bit 6 + BITS PSC15 : 1; // bit 7 + }; // PSCRH bitfield + + /// register _TIM1_PSCRH reset value + #define sfr_TIM1_PSCRH_RESET_VALUE ((uint8_t) 0x00) + + } PSCRH; + + + /** TIM1 prescaler register low (PSCRL at 0x52c2) */ + union { + + /// bytewise access to PSCRL + uint8_t byte; + + /// bitwise access to register PSCRL + struct { + BITS PSC0 : 1; // bit 0 + BITS PSC1 : 1; // bit 1 + BITS PSC2 : 1; // bit 2 + BITS PSC3 : 1; // bit 3 + BITS PSC4 : 1; // bit 4 + BITS PSC5 : 1; // bit 5 + BITS PSC6 : 1; // bit 6 + BITS PSC7 : 1; // bit 7 + }; // PSCRL bitfield + + /// register _TIM1_PSCRL reset value + #define sfr_TIM1_PSCRL_RESET_VALUE ((uint8_t) 0x00) + + } PSCRL; + + + /** TIM1 Auto-reload register high (ARRH at 0x52c3) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR8 : 1; // bit 0 + BITS ARR9 : 1; // bit 1 + BITS ARR10 : 1; // bit 2 + BITS ARR11 : 1; // bit 3 + BITS ARR12 : 1; // bit 4 + BITS ARR13 : 1; // bit 5 + BITS ARR14 : 1; // bit 6 + BITS ARR15 : 1; // bit 7 + }; // ARRH bitfield + + /// register _TIM1_ARRH reset value + #define sfr_TIM1_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM1 Auto-reload register low (ARRL at 0x52c4) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR0 : 1; // bit 0 + BITS ARR1 : 1; // bit 1 + BITS ARR2 : 1; // bit 2 + BITS ARR3 : 1; // bit 3 + BITS ARR4 : 1; // bit 4 + BITS ARR5 : 1; // bit 5 + BITS ARR6 : 1; // bit 6 + BITS ARR7 : 1; // bit 7 + }; // ARRL bitfield + + /// register _TIM1_ARRL reset value + #define sfr_TIM1_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM1 Repetition counter register (RCR at 0x52c5) */ + union { + + /// bytewise access to RCR + uint8_t byte; + + /// bitwise access to register RCR + struct { + BITS REP : 8; // bits 0-7 + }; // RCR bitfield + + /// register _TIM1_RCR reset value + #define sfr_TIM1_RCR_RESET_VALUE ((uint8_t) 0x00) + + } RCR; + + + /** TIM1 Capture/Compare register 1 high (CCR1H at 0x52c6) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR18 : 1; // bit 0 + BITS CCR19 : 1; // bit 1 + BITS CCR110 : 1; // bit 2 + BITS CCR111 : 1; // bit 3 + BITS CCR112 : 1; // bit 4 + BITS CCR113 : 1; // bit 5 + BITS CCR114 : 1; // bit 6 + BITS CCR115 : 1; // bit 7 + }; // CCR1H bitfield + + /// register _TIM1_CCR1H reset value + #define sfr_TIM1_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM1 Capture/Compare register 1 low (CCR1L at 0x52c7) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR10 : 1; // bit 0 + BITS CCR11 : 1; // bit 1 + BITS CCR12 : 1; // bit 2 + BITS CCR13 : 1; // bit 3 + BITS CCR14 : 1; // bit 4 + BITS CCR15 : 1; // bit 5 + BITS CCR16 : 1; // bit 6 + BITS CCR17 : 1; // bit 7 + }; // CCR1L bitfield + + /// register _TIM1_CCR1L reset value + #define sfr_TIM1_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM1 Capture/Compare register 2 high (CCR2H at 0x52c8) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR28 : 1; // bit 0 + BITS CCR29 : 1; // bit 1 + BITS CCR210 : 1; // bit 2 + BITS CCR211 : 1; // bit 3 + BITS CCR212 : 1; // bit 4 + BITS CCR213 : 1; // bit 5 + BITS CCR214 : 1; // bit 6 + BITS CCR215 : 1; // bit 7 + }; // CCR2H bitfield + + /// register _TIM1_CCR2H reset value + #define sfr_TIM1_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM1 Capture/Compare register 2 low (CCR2L at 0x52c9) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR20 : 1; // bit 0 + BITS CCR21 : 1; // bit 1 + BITS CCR22 : 1; // bit 2 + BITS CCR23 : 1; // bit 3 + BITS CCR24 : 1; // bit 4 + BITS CCR25 : 1; // bit 5 + BITS CCR26 : 1; // bit 6 + BITS CCR27 : 1; // bit 7 + }; // CCR2L bitfield + + /// register _TIM1_CCR2L reset value + #define sfr_TIM1_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM1 Capture/Compare register 3 high (CCR3H at 0x52ca) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR38 : 1; // bit 0 + BITS CCR39 : 1; // bit 1 + BITS CCR310 : 1; // bit 2 + BITS CCR311 : 1; // bit 3 + BITS CCR312 : 1; // bit 4 + BITS CCR313 : 1; // bit 5 + BITS CCR314 : 1; // bit 6 + BITS CCR315 : 1; // bit 7 + }; // CCR3H bitfield + + /// register _TIM1_CCR3H reset value + #define sfr_TIM1_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM1 Capture/Compare register 3 low (CCR3L at 0x52cb) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR30 : 1; // bit 0 + BITS CCR31 : 1; // bit 1 + BITS CCR32 : 1; // bit 2 + BITS CCR33 : 1; // bit 3 + BITS CCR34 : 1; // bit 4 + BITS CCR35 : 1; // bit 5 + BITS CCR36 : 1; // bit 6 + BITS CCR37 : 1; // bit 7 + }; // CCR3L bitfield + + /// register _TIM1_CCR3L reset value + #define sfr_TIM1_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + + + /** TIM1 Capture/Compare register 4 high (CCR4H at 0x52cc) */ + union { + + /// bytewise access to CCR4H + uint8_t byte; + + /// bitwise access to register CCR4H + struct { + BITS CCR48 : 1; // bit 0 + BITS CCR49 : 1; // bit 1 + BITS CCR410 : 1; // bit 2 + BITS CCR411 : 1; // bit 3 + BITS CCR412 : 1; // bit 4 + BITS CCR413 : 1; // bit 5 + BITS CCR414 : 1; // bit 6 + BITS CCR415 : 1; // bit 7 + }; // CCR4H bitfield + + /// register _TIM1_CCR4H reset value + #define sfr_TIM1_CCR4H_RESET_VALUE ((uint8_t) 0x00) + + } CCR4H; + + + /** TIM1 Capture/Compare register 4 low (CCR4L at 0x52cd) */ + union { + + /// bytewise access to CCR4L + uint8_t byte; + + /// bitwise access to register CCR4L + struct { + BITS CCR40 : 1; // bit 0 + BITS CCR41 : 1; // bit 1 + BITS CCR42 : 1; // bit 2 + BITS CCR43 : 1; // bit 3 + BITS CCR44 : 1; // bit 4 + BITS CCR45 : 1; // bit 5 + BITS CCR46 : 1; // bit 6 + BITS CCR47 : 1; // bit 7 + }; // CCR4L bitfield + + /// register _TIM1_CCR4L reset value + #define sfr_TIM1_CCR4L_RESET_VALUE ((uint8_t) 0x00) + + } CCR4L; + + + /** TIM1 break register (BKR at 0x52ce) */ + union { + + /// bytewise access to BKR + uint8_t byte; + + /// bitwise access to register BKR + struct { + BITS LOCK : 2; // bits 0-1 + BITS OSSI : 1; // bit 2 + BITS OSSR : 1; // bit 3 + BITS BKE : 1; // bit 4 + BITS BKP : 1; // bit 5 + BITS AOE : 1; // bit 6 + BITS MOE : 1; // bit 7 + }; // BKR bitfield + + /// register _TIM1_BKR reset value + #define sfr_TIM1_BKR_RESET_VALUE ((uint8_t) 0x00) + + } BKR; + + + /** TIM1 dead-time register (DTR at 0x52cf) */ + union { + + /// bytewise access to DTR + uint8_t byte; + + /// bitwise access to register DTR + struct { + BITS DTG : 8; // bits 0-7 + }; // DTR bitfield + + /// register _TIM1_DTR reset value + #define sfr_TIM1_DTR_RESET_VALUE ((uint8_t) 0x00) + + } DTR; + + + /** TIM1 output idle state register (OISR at 0x52d0) */ + union { + + /// bytewise access to OISR + uint8_t byte; + + /// bitwise access to register OISR + struct { + BITS OIS1 : 1; // bit 0 + BITS OIS1N : 1; // bit 1 + BITS OIS2 : 1; // bit 2 + BITS OIS2N : 1; // bit 3 + BITS OIS3 : 1; // bit 4 + BITS OIS3N : 1; // bit 5 + BITS : 2; // 2 bits + }; // OISR bitfield + + /// register _TIM1_OISR reset value + #define sfr_TIM1_OISR_RESET_VALUE ((uint8_t) 0x00) + + } OISR; + + + /** DMA1 control register 1 (DCR1 at 0x52d1) */ + union { + + /// bytewise access to DCR1 + uint8_t byte; + + /// bitwise access to register DCR1 + struct { + BITS DBA : 5; // bits 0-4 + BITS : 3; // 3 bits + }; // DCR1 bitfield + + /// register _TIM1_DCR1 reset value + #define sfr_TIM1_DCR1_RESET_VALUE ((uint8_t) 0x00) + + } DCR1; + + + /** TIM1 DMA1 control register 2 (DCR2 at 0x52d2) */ + union { + + /// bytewise access to DCR2 + uint8_t byte; + + /// bitwise access to register DCR2 + struct { + BITS DBL : 5; // bits 0-4 + BITS : 3; // 3 bits + }; // DCR2 bitfield + + /// register _TIM1_DCR2 reset value + #define sfr_TIM1_DCR2_RESET_VALUE ((uint8_t) 0x00) + + } DCR2; + + + /** TIM1 DMA1 address for burst mode (DMA1R at 0x52d3) */ + union { + + /// bytewise access to DMA1R + uint8_t byte; + + /// bitwise access to register DMA1R + struct { + BITS DMAB : 8; // bits 0-7 + }; // DMA1R bitfield + + /// register _TIM1_DMA1R reset value + #define sfr_TIM1_DMA1R_RESET_VALUE ((uint8_t) 0x00) + + } DMA1R; + +} TIM1_t; + +/// access to TIM1 SFR registers +#define sfr_TIM1 (*((TIM1_t*) 0x52b0)) + + +//------------------------ +// Module TIM2 +//------------------------ + +/** struct containing TIM2 module registers */ +typedef struct { + + /** TIM2 control register 1 (CR1 at 0x5250) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS DIR : 1; // bit 4 + BITS CMS : 2; // bits 5-6 + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM2_CR1 reset value + #define sfr_TIM2_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM2 control register 2 (CR2 at 0x5251) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS : 3; // 3 bits + BITS CCDS : 1; // bit 3 + BITS MMS : 3; // bits 4-6 + BITS TI1S : 1; // bit 7 + }; // CR2 bitfield + + /// register _TIM2_CR2 reset value + #define sfr_TIM2_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** TIM2 Slave mode control register (SMCR at 0x5252) */ + union { + + /// bytewise access to SMCR + uint8_t byte; + + /// bitwise access to register SMCR + struct { + BITS SMS : 3; // bits 0-2 + BITS : 1; // 1 bit + BITS TS : 3; // bits 4-6 + BITS MSM : 1; // bit 7 + }; // SMCR bitfield + + /// register _TIM2_SMCR reset value + #define sfr_TIM2_SMCR_RESET_VALUE ((uint8_t) 0x00) + + } SMCR; + + + /** TIM2 external trigger register (ETR at 0x5253) */ + union { + + /// bytewise access to ETR + uint8_t byte; + + /// bitwise access to register ETR + struct { + BITS ETF : 4; // bits 0-3 + BITS ETPS : 2; // bits 4-5 + BITS ECE : 1; // bit 6 + BITS ETP : 1; // bit 7 + }; // ETR bitfield + + /// register _TIM2_ETR reset value + #define sfr_TIM2_ETR_RESET_VALUE ((uint8_t) 0x00) + + } ETR; + + + /** TIM2 DMA1 request enable register (DER at 0x5254) */ + union { + + /// bytewise access to DER + uint8_t byte; + + /// bitwise access to register DER + struct { + BITS UDE : 1; // bit 0 + BITS CC1DE : 1; // bit 1 + BITS CC2DE : 1; // bit 2 + BITS : 5; // 5 bits + }; // DER bitfield + + /// register _TIM2_DER reset value + #define sfr_TIM2_DER_RESET_VALUE ((uint8_t) 0x00) + + } DER; + + + /** TIM2 interrupt enable register (IER at 0x5255) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS : 3; // 3 bits + BITS TIE : 1; // bit 6 + BITS BIE : 1; // bit 7 + }; // IER bitfield + + /// register _TIM2_IER reset value + #define sfr_TIM2_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM2 status register 1 (SR1 at 0x5256) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS : 3; // 3 bits + BITS TIF : 1; // bit 6 + BITS BIF : 1; // bit 7 + }; // SR1 bitfield + + /// register _TIM2_SR1 reset value + #define sfr_TIM2_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM2 status register 2 (SR2 at 0x5257) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS : 5; // 5 bits + }; // SR2 bitfield + + /// register _TIM2_SR2 reset value + #define sfr_TIM2_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM2 event generation register (EGR at 0x5258) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS : 3; // 3 bits + BITS TG : 1; // bit 6 + BITS BG : 1; // bit 7 + }; // EGR bitfield + + /// register _TIM2_EGR reset value + #define sfr_TIM2_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM2 capture/compare mode register 1 (CCMR1 at 0x5259) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS OC1FE : 1; // bit 2 + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM2_CCMR1 reset value + #define sfr_TIM2_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM2 capture/compare mode register 2 (CCMR2 at 0x525a) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS OC2FE : 1; // bit 2 + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM2_CCMR2 reset value + #define sfr_TIM2_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM2 capture/compare enable register 1 (CCER1 at 0x525b) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM2_CCER1 reset value + #define sfr_TIM2_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM2 counter high (CNTRH at 0x525c) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT8 : 1; // bit 0 + BITS CNT9 : 1; // bit 1 + BITS CNT10 : 1; // bit 2 + BITS CNT11 : 1; // bit 3 + BITS CNT12 : 1; // bit 4 + BITS CNT13 : 1; // bit 5 + BITS CNT14 : 1; // bit 6 + BITS CNT15 : 1; // bit 7 + }; // CNTRH bitfield + + /// register _TIM2_CNTRH reset value + #define sfr_TIM2_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM2 counter low (CNTRL at 0x525d) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT0 : 1; // bit 0 + BITS CNT1 : 1; // bit 1 + BITS CNT2 : 1; // bit 2 + BITS CNT3 : 1; // bit 3 + BITS CNT4 : 1; // bit 4 + BITS CNT5 : 1; // bit 5 + BITS CNT6 : 1; // bit 6 + BITS CNT7 : 1; // bit 7 + }; // CNTRL bitfield + + /// register _TIM2_CNTRL reset value + #define sfr_TIM2_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM2 prescaler register (PSCR at 0x525e) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PSCR bitfield + + /// register _TIM2_PSCR reset value + #define sfr_TIM2_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM2 auto-reload register high (ARRH at 0x525f) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR8 : 1; // bit 0 + BITS ARR9 : 1; // bit 1 + BITS ARR10 : 1; // bit 2 + BITS ARR11 : 1; // bit 3 + BITS ARR12 : 1; // bit 4 + BITS ARR13 : 1; // bit 5 + BITS ARR14 : 1; // bit 6 + BITS ARR15 : 1; // bit 7 + }; // ARRH bitfield + + /// register _TIM2_ARRH reset value + #define sfr_TIM2_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM2 auto-reload register low (ARRL at 0x5260) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR0 : 1; // bit 0 + BITS ARR1 : 1; // bit 1 + BITS ARR2 : 1; // bit 2 + BITS ARR3 : 1; // bit 3 + BITS ARR4 : 1; // bit 4 + BITS ARR5 : 1; // bit 5 + BITS ARR6 : 1; // bit 6 + BITS ARR7 : 1; // bit 7 + }; // ARRL bitfield + + /// register _TIM2_ARRL reset value + #define sfr_TIM2_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM2 capture/compare register 1 high (CCR1H at 0x5261) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR18 : 1; // bit 0 + BITS CCR19 : 1; // bit 1 + BITS CCR110 : 1; // bit 2 + BITS CCR111 : 1; // bit 3 + BITS CCR112 : 1; // bit 4 + BITS CCR113 : 1; // bit 5 + BITS CCR114 : 1; // bit 6 + BITS CCR115 : 1; // bit 7 + }; // CCR1H bitfield + + /// register _TIM2_CCR1H reset value + #define sfr_TIM2_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM2 capture/compare register 1 low (CCR1L at 0x5262) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR10 : 1; // bit 0 + BITS CCR11 : 1; // bit 1 + BITS CCR12 : 1; // bit 2 + BITS CCR13 : 1; // bit 3 + BITS CCR14 : 1; // bit 4 + BITS CCR15 : 1; // bit 5 + BITS CCR16 : 1; // bit 6 + BITS CCR17 : 1; // bit 7 + }; // CCR1L bitfield + + /// register _TIM2_CCR1L reset value + #define sfr_TIM2_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM2 capture/compare register 2 high (CCR2H at 0x5263) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR28 : 1; // bit 0 + BITS CCR29 : 1; // bit 1 + BITS CCR210 : 1; // bit 2 + BITS CCR211 : 1; // bit 3 + BITS CCR212 : 1; // bit 4 + BITS CCR213 : 1; // bit 5 + BITS CCR214 : 1; // bit 6 + BITS CCR215 : 1; // bit 7 + }; // CCR2H bitfield + + /// register _TIM2_CCR2H reset value + #define sfr_TIM2_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM2 capture/compare register 2 low (CCR2L at 0x5264) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR10 : 1; // bit 0 + BITS CCR11 : 1; // bit 1 + BITS CCR12 : 1; // bit 2 + BITS CCR13 : 1; // bit 3 + BITS CCR14 : 1; // bit 4 + BITS CCR15 : 1; // bit 5 + BITS CCR16 : 1; // bit 6 + BITS CCR17 : 1; // bit 7 + }; // CCR2L bitfield + + /// register _TIM2_CCR2L reset value + #define sfr_TIM2_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM2 break register (BKR at 0x5265) */ + union { + + /// bytewise access to BKR + uint8_t byte; + + /// bitwise access to register BKR + struct { + BITS LOCK : 2; // bits 0-1 + BITS OSSI : 1; // bit 2 + BITS : 1; // 1 bit + BITS BKE : 1; // bit 4 + BITS BKP : 1; // bit 5 + BITS AOE : 1; // bit 6 + BITS MOE : 1; // bit 7 + }; // BKR bitfield + + /// register _TIM2_BKR reset value + #define sfr_TIM2_BKR_RESET_VALUE ((uint8_t) 0x00) + + } BKR; + + + /** TIM2 output idle state register (OISR at 0x5266) */ + union { + + /// bytewise access to OISR + uint8_t byte; + + /// bitwise access to register OISR + struct { + BITS OIS1 : 1; // bit 0 + BITS : 1; // 1 bit + BITS OIS2 : 1; // bit 2 + BITS : 5; // 5 bits + }; // OISR bitfield + + /// register _TIM2_OISR reset value + #define sfr_TIM2_OISR_RESET_VALUE ((uint8_t) 0x00) + + } OISR; + +} TIM2_t; + +/// access to TIM2 SFR registers +#define sfr_TIM2 (*((TIM2_t*) 0x5250)) + + +//------------------------ +// Module TIM3 +//------------------------ + +/** struct containing TIM3 module registers */ +typedef struct { + + /** TIM3 control register 1 (CR1 at 0x5280) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS DIR : 1; // bit 4 + BITS CMS : 2; // bits 5-6 + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM3_CR1 reset value + #define sfr_TIM3_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM3 control register 2 (CR2 at 0x5281) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS : 3; // 3 bits + BITS CCDS : 1; // bit 3 + BITS MMS : 3; // bits 4-6 + BITS TI1S : 1; // bit 7 + }; // CR2 bitfield + + /// register _TIM3_CR2 reset value + #define sfr_TIM3_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** TIM3 Slave mode control register (SMCR at 0x5282) */ + union { + + /// bytewise access to SMCR + uint8_t byte; + + /// bitwise access to register SMCR + struct { + BITS SMS : 3; // bits 0-2 + BITS : 1; // 1 bit + BITS TS : 3; // bits 4-6 + BITS MSM : 1; // bit 7 + }; // SMCR bitfield + + /// register _TIM3_SMCR reset value + #define sfr_TIM3_SMCR_RESET_VALUE ((uint8_t) 0x00) + + } SMCR; + + + /** TIM3 external trigger register (ETR at 0x5283) */ + union { + + /// bytewise access to ETR + uint8_t byte; + + /// bitwise access to register ETR + struct { + BITS ETF : 4; // bits 0-3 + BITS ETPS : 2; // bits 4-5 + BITS ECE : 1; // bit 6 + BITS ETP : 1; // bit 7 + }; // ETR bitfield + + /// register _TIM3_ETR reset value + #define sfr_TIM3_ETR_RESET_VALUE ((uint8_t) 0x00) + + } ETR; + + + /** TIM3 DMA1 request enable register (DER at 0x5284) */ + union { + + /// bytewise access to DER + uint8_t byte; + + /// bitwise access to register DER + struct { + BITS UDE : 1; // bit 0 + BITS CC1DE : 1; // bit 1 + BITS CC2DE : 1; // bit 2 + BITS : 5; // 5 bits + }; // DER bitfield + + /// register _TIM3_DER reset value + #define sfr_TIM3_DER_RESET_VALUE ((uint8_t) 0x00) + + } DER; + + + /** TIM3 interrupt enable register (IER at 0x5285) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS : 3; // 3 bits + BITS TIE : 1; // bit 6 + BITS BIE : 1; // bit 7 + }; // IER bitfield + + /// register _TIM3_IER reset value + #define sfr_TIM3_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM3 status register 1 (SR1 at 0x5286) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS : 3; // 3 bits + BITS TIF : 1; // bit 6 + BITS BIF : 1; // bit 7 + }; // SR1 bitfield + + /// register _TIM3_SR1 reset value + #define sfr_TIM3_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM3 status register 2 (SR2 at 0x5287) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS : 5; // 5 bits + }; // SR2 bitfield + + /// register _TIM3_SR2 reset value + #define sfr_TIM3_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM3 event generation register (EGR at 0x5288) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS : 3; // 3 bits + BITS TG : 1; // bit 6 + BITS BG : 1; // bit 7 + }; // EGR bitfield + + /// register _TIM3_EGR reset value + #define sfr_TIM3_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM3 Capture/Compare mode register 1 (CCMR1 at 0x5289) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS OC1FE : 1; // bit 2 + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM3_CCMR1 reset value + #define sfr_TIM3_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM3 Capture/Compare mode register 2 (CCMR2 at 0x528a) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS OC2FE : 1; // bit 2 + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM3_CCMR2 reset value + #define sfr_TIM3_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM3 Capture/Compare enable register 1 (CCER1 at 0x528b) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM3_CCER1 reset value + #define sfr_TIM3_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM3 counter high (CNTRH at 0x528c) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT8 : 1; // bit 0 + BITS CNT9 : 1; // bit 1 + BITS CNT10 : 1; // bit 2 + BITS CNT11 : 1; // bit 3 + BITS CNT12 : 1; // bit 4 + BITS CNT13 : 1; // bit 5 + BITS CNT14 : 1; // bit 6 + BITS CNT15 : 1; // bit 7 + }; // CNTRH bitfield + + /// register _TIM3_CNTRH reset value + #define sfr_TIM3_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM3 counter low (CNTRL at 0x528d) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT0 : 1; // bit 0 + BITS CNT1 : 1; // bit 1 + BITS CNT2 : 1; // bit 2 + BITS CNT3 : 1; // bit 3 + BITS CNT4 : 1; // bit 4 + BITS CNT5 : 1; // bit 5 + BITS CNT6 : 1; // bit 6 + BITS CNT7 : 1; // bit 7 + }; // CNTRL bitfield + + /// register _TIM3_CNTRL reset value + #define sfr_TIM3_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM3 prescaler register (PSCR at 0x528e) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PSCR bitfield + + /// register _TIM3_PSCR reset value + #define sfr_TIM3_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM3 Auto-reload register high (ARRH at 0x528f) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR8 : 1; // bit 0 + BITS ARR9 : 1; // bit 1 + BITS ARR10 : 1; // bit 2 + BITS ARR11 : 1; // bit 3 + BITS ARR12 : 1; // bit 4 + BITS ARR13 : 1; // bit 5 + BITS ARR14 : 1; // bit 6 + BITS ARR15 : 1; // bit 7 + }; // ARRH bitfield + + /// register _TIM3_ARRH reset value + #define sfr_TIM3_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM3 Auto-reload register low (ARRL at 0x5290) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR0 : 1; // bit 0 + BITS ARR1 : 1; // bit 1 + BITS ARR2 : 1; // bit 2 + BITS ARR3 : 1; // bit 3 + BITS ARR4 : 1; // bit 4 + BITS ARR5 : 1; // bit 5 + BITS ARR6 : 1; // bit 6 + BITS ARR7 : 1; // bit 7 + }; // ARRL bitfield + + /// register _TIM3_ARRL reset value + #define sfr_TIM3_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM3 Capture/Compare register 1 high (CCR1H at 0x5291) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR18 : 1; // bit 0 + BITS CCR19 : 1; // bit 1 + BITS CCR110 : 1; // bit 2 + BITS CCR111 : 1; // bit 3 + BITS CCR112 : 1; // bit 4 + BITS CCR113 : 1; // bit 5 + BITS CCR114 : 1; // bit 6 + BITS CCR115 : 1; // bit 7 + }; // CCR1H bitfield + + /// register _TIM3_CCR1H reset value + #define sfr_TIM3_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM3 Capture/Compare register 1 low (CCR1L at 0x5292) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR10 : 1; // bit 0 + BITS CCR11 : 1; // bit 1 + BITS CCR12 : 1; // bit 2 + BITS CCR13 : 1; // bit 3 + BITS CCR14 : 1; // bit 4 + BITS CCR15 : 1; // bit 5 + BITS CCR16 : 1; // bit 6 + BITS CCR17 : 1; // bit 7 + }; // CCR1L bitfield + + /// register _TIM3_CCR1L reset value + #define sfr_TIM3_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM3 Capture/Compare register 2 high (CCR2H at 0x5293) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR28 : 1; // bit 0 + BITS CCR29 : 1; // bit 1 + BITS CCR210 : 1; // bit 2 + BITS CCR211 : 1; // bit 3 + BITS CCR212 : 1; // bit 4 + BITS CCR213 : 1; // bit 5 + BITS CCR214 : 1; // bit 6 + BITS CCR215 : 1; // bit 7 + }; // CCR2H bitfield + + /// register _TIM3_CCR2H reset value + #define sfr_TIM3_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM3 Capture/Compare register 2 low (CCR2L at 0x5294) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR10 : 1; // bit 0 + BITS CCR11 : 1; // bit 1 + BITS CCR12 : 1; // bit 2 + BITS CCR13 : 1; // bit 3 + BITS CCR14 : 1; // bit 4 + BITS CCR15 : 1; // bit 5 + BITS CCR16 : 1; // bit 6 + BITS CCR17 : 1; // bit 7 + }; // CCR2L bitfield + + /// register _TIM3_CCR2L reset value + #define sfr_TIM3_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM3 break register (BKR at 0x5295) */ + union { + + /// bytewise access to BKR + uint8_t byte; + + /// bitwise access to register BKR + struct { + BITS LOCK : 2; // bits 0-1 + BITS OSSI : 1; // bit 2 + BITS : 1; // 1 bit + BITS BKE : 1; // bit 4 + BITS BKP : 1; // bit 5 + BITS AOE : 1; // bit 6 + BITS MOE : 1; // bit 7 + }; // BKR bitfield + + /// register _TIM3_BKR reset value + #define sfr_TIM3_BKR_RESET_VALUE ((uint8_t) 0x00) + + } BKR; + + + /** TIM3 output idle state register (OISR at 0x5296) */ + union { + + /// bytewise access to OISR + uint8_t byte; + + /// bitwise access to register OISR + struct { + BITS OIS1 : 1; // bit 0 + BITS : 1; // 1 bit + BITS OIS2 : 1; // bit 2 + BITS : 5; // 5 bits + }; // OISR bitfield + + /// register _TIM3_OISR reset value + #define sfr_TIM3_OISR_RESET_VALUE ((uint8_t) 0x00) + + } OISR; + +} TIM3_t; + +/// access to TIM3 SFR registers +#define sfr_TIM3 (*((TIM3_t*) 0x5280)) + + +//------------------------ +// Module TIM4 +//------------------------ + +/** struct containing TIM4 module registers */ +typedef struct { + + /** TIM4 control register 1 (CR1 at 0x52e0) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM4_CR1 reset value + #define sfr_TIM4_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM4 control register 2 (CR2 at 0x52e1) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS : 4; // 4 bits + BITS MMS : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _TIM4_CR2 reset value + #define sfr_TIM4_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** TIM4 Slave mode control register (SMCR at 0x52e2) */ + union { + + /// bytewise access to SMCR + uint8_t byte; + + /// bitwise access to register SMCR + struct { + BITS SMS : 3; // bits 0-2 + BITS : 1; // 1 bit + BITS TS : 3; // bits 4-6 + BITS MSM : 1; // bit 7 + }; // SMCR bitfield + + /// register _TIM4_SMCR reset value + #define sfr_TIM4_SMCR_RESET_VALUE ((uint8_t) 0x00) + + } SMCR; + + + /** TIM4 DMA1 request enable register (DER at 0x52e3) */ + union { + + /// bytewise access to DER + uint8_t byte; + + /// bitwise access to register DER + struct { + BITS UDE : 1; // bit 0 + BITS : 7; // 7 bits + }; // DER bitfield + + /// register _TIM4_DER reset value + #define sfr_TIM4_DER_RESET_VALUE ((uint8_t) 0x00) + + } DER; + + + /** TIM4 Interrupt enable register (IER at 0x52e4) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM4_IER reset value + #define sfr_TIM4_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM4 status register 1 (SR1 at 0x52e5) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR1 bitfield + + /// register _TIM4_SR1 reset value + #define sfr_TIM4_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM4 Event generation register (EGR at 0x52e6) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS : 5; // 5 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM4_EGR reset value + #define sfr_TIM4_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM4 counter (CNTR at 0x52e7) */ + union { + + /// bytewise access to CNTR + uint8_t byte; + + /// bitwise access to register CNTR + struct { + BITS CNT0 : 1; // bit 0 + BITS CNT1 : 1; // bit 1 + BITS CNT2 : 1; // bit 2 + BITS CNT3 : 1; // bit 3 + BITS CNT4 : 1; // bit 4 + BITS CNT5 : 1; // bit 5 + BITS CNT6 : 1; // bit 6 + BITS CNT7 : 1; // bit 7 + }; // CNTR bitfield + + /// register _TIM4_CNTR reset value + #define sfr_TIM4_CNTR_RESET_VALUE ((uint8_t) 0x00) + + } CNTR; + + + /** TIM4 prescaler register (PSCR at 0x52e8) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // PSCR bitfield + + /// register _TIM4_PSCR reset value + #define sfr_TIM4_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM4 Auto-reload register (ARR at 0x52e9) */ + union { + + /// bytewise access to ARR + uint8_t byte; + + /// bitwise access to register ARR + struct { + BITS ARR0 : 1; // bit 0 + BITS ARR1 : 1; // bit 1 + BITS ARR2 : 1; // bit 2 + BITS ARR3 : 1; // bit 3 + BITS ARR4 : 1; // bit 4 + BITS ARR5 : 1; // bit 5 + BITS ARR6 : 1; // bit 6 + BITS ARR7 : 1; // bit 7 + }; // ARR bitfield + + /// register _TIM4_ARR reset value + #define sfr_TIM4_ARR_RESET_VALUE ((uint8_t) 0x00) + + } ARR; + +} TIM4_t; + +/// access to TIM4 SFR registers +#define sfr_TIM4 (*((TIM4_t*) 0x52e0)) + + +//------------------------ +// Module USART1 +//------------------------ + +/** struct containing USART1 module registers */ +typedef struct { + + /** USART1 status register (SR at 0x5230) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS PE : 1; // bit 0 + BITS FE : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS OR : 1; // bit 3 + BITS IDLE : 1; // bit 4 + BITS RXNE : 1; // bit 5 + BITS TC : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR bitfield + + /// register _USART1_SR reset value + #define sfr_USART1_SR_RESET_VALUE ((uint8_t) 0xC0) + + } SR; + + + /** USART1 data register (DR at 0x5231) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _USART1_DR reset value + #define sfr_USART1_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** USART1 baud rate register 1 (BRR1 at 0x5232) */ + union { + + /// bytewise access to BRR1 + uint8_t byte; + + /// bitwise access to register BRR1 + struct { + BITS USART_DIV4 : 1; // bit 0 + BITS USART_DIV5 : 1; // bit 1 + BITS USART_DIV6 : 1; // bit 2 + BITS USART_DIV7 : 1; // bit 3 + BITS USART_DIV8 : 1; // bit 4 + BITS USART_DIV9 : 1; // bit 5 + BITS USART_DIV10 : 1; // bit 6 + BITS USART_DIV11 : 1; // bit 7 + }; // BRR1 bitfield + + /// register _USART1_BRR1 reset value + #define sfr_USART1_BRR1_RESET_VALUE ((uint8_t) 0x00) + + } BRR1; + + + /** USART1 baud rate register 2 (BRR2 at 0x5233) */ + union { + + /// bytewise access to BRR2 + uint8_t byte; + + /// bitwise access to register BRR2 + struct { + BITS USART_DIV0 : 1; // bit 0 + BITS USART_DIV1 : 1; // bit 1 + BITS USART_DIV2 : 1; // bit 2 + BITS USART_DIV3 : 1; // bit 3 + BITS USART_DIV12 : 1; // bit 4 + BITS USART_DIV13 : 1; // bit 5 + BITS USART_DIV14 : 1; // bit 6 + BITS USART_DIV15 : 1; // bit 7 + }; // BRR2 bitfield + + /// register _USART1_BRR2 reset value + #define sfr_USART1_BRR2_RESET_VALUE ((uint8_t) 0x00) + + } BRR2; + + + /** USART1 control register 1 (CR1 at 0x5234) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PIEN : 1; // bit 0 + BITS PS : 1; // bit 1 + BITS PCEN : 1; // bit 2 + BITS WAKE : 1; // bit 3 + BITS M : 1; // bit 4 + BITS USARTD : 1; // bit 5 + BITS T8 : 1; // bit 6 + BITS R8 : 1; // bit 7 + }; // CR1 bitfield + + /// register _USART1_CR1 reset value + #define sfr_USART1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** USART1 control register 2 (CR2 at 0x5235) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SBK : 1; // bit 0 + BITS RWU : 1; // bit 1 + BITS REN : 1; // bit 2 + BITS TEN : 1; // bit 3 + BITS ILIEN : 1; // bit 4 + BITS RIEN : 1; // bit 5 + BITS TCIEN : 1; // bit 6 + BITS TIEN : 1; // bit 7 + }; // CR2 bitfield + + /// register _USART1_CR2 reset value + #define sfr_USART1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** USART1 control register 3 (CR3 at 0x5236) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS LBCL : 1; // bit 0 + BITS CPHA : 1; // bit 1 + BITS CPOL : 1; // bit 2 + BITS CLKEN : 1; // bit 3 + BITS STOP0 : 1; // bit 4 + BITS STOP1 : 1; // bit 5 + BITS : 2; // 2 bits + }; // CR3 bitfield + + /// register _USART1_CR3 reset value + #define sfr_USART1_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** USART1 control register 4 (CR4 at 0x5237) */ + union { + + /// bytewise access to CR4 + uint8_t byte; + + /// bitwise access to register CR4 + struct { + BITS ADD0 : 1; // bit 0 + BITS ADD1 : 1; // bit 1 + BITS ADD2 : 1; // bit 2 + BITS ADD3 : 1; // bit 3 + BITS : 4; // 4 bits + }; // CR4 bitfield + + /// register _USART1_CR4 reset value + #define sfr_USART1_CR4_RESET_VALUE ((uint8_t) 0x00) + + } CR4; + + + /** USART1 control register 5 (CR5 at 0x5238) */ + union { + + /// bytewise access to CR5 + uint8_t byte; + + /// bitwise access to register CR5 + struct { + BITS EIE : 1; // bit 0 + BITS IREN : 1; // bit 1 + BITS IRLP : 1; // bit 2 + BITS HDSEL : 1; // bit 3 + BITS NACK : 1; // bit 4 + BITS SCEN : 1; // bit 5 + BITS DMAR : 1; // bit 6 + BITS DMAT : 1; // bit 7 + }; // CR5 bitfield + + /// register _USART1_CR5 reset value + #define sfr_USART1_CR5_RESET_VALUE ((uint8_t) 0x00) + + } CR5; + + + /** USART1 guard time register (GTR at 0x5239) */ + union { + + /// bytewise access to GTR + uint8_t byte; + + /// bitwise access to register GTR + struct { + BITS GT : 8; // bits 0-7 + }; // GTR bitfield + + /// register _USART1_GTR reset value + #define sfr_USART1_GTR_RESET_VALUE ((uint8_t) 0x00) + + } GTR; + + + /** USART1 prescaler register (PSCR at 0x523a) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCR bitfield + + /// register _USART1_PSCR reset value + #define sfr_USART1_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + +} USART1_t; + +/// access to USART1 SFR registers +#define sfr_USART1 (*((USART1_t*) 0x5230)) + + +//------------------------ +// Module WFE +//------------------------ + +/** struct containing WFE module registers */ +typedef struct { + + /** WFE control register 1 (CR1 at 0x50a6) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS TIM2_EV0 : 1; // bit 0 + BITS TIM2_EV1 : 1; // bit 1 + BITS TIM1_EV0 : 1; // bit 2 + BITS TIM1_EV1 : 1; // bit 3 + BITS EXTI_EV0 : 1; // bit 4 + BITS EXTI_EV1 : 1; // bit 5 + BITS EXTI_EV2 : 1; // bit 6 + BITS EXTI_EV3 : 1; // bit 7 + }; // CR1 bitfield + + /// register _WFE_CR1 reset value + #define sfr_WFE_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** WFE control register 2 (CR2 at 0x50a7) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS EXTI_EV4 : 1; // bit 0 + BITS EXTI_EV5 : 1; // bit 1 + BITS EXTI_EV6 : 1; // bit 2 + BITS EXTI_EV7 : 1; // bit 3 + BITS EXTI_EVB : 1; // bit 4 + BITS EXTI_EVD : 1; // bit 5 + BITS EXTI_EVF : 1; // bit 6 + BITS ADC1_COMP_EV : 1; // bit 7 + }; // CR2 bitfield + + /// register _WFE_CR2 reset value + #define sfr_WFE_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** WFE control register 3 (CR3 at 0x50a8) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS TIM3_EV0 : 1; // bit 0 + BITS TIM3_EV1 : 1; // bit 1 + BITS TIM4_EV : 1; // bit 2 + BITS SPI1_EV : 1; // bit 3 + BITS I2C1_EV : 1; // bit 4 + BITS USART1_EV : 1; // bit 5 + BITS DMA1CH01_EV : 1; // bit 6 + BITS DMA1CH23_EV : 1; // bit 7 + }; // CR3 bitfield + + /// register _WFE_CR3 reset value + #define sfr_WFE_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + +} WFE_t; + +/// access to WFE SFR registers +#define sfr_WFE (*((WFE_t*) 0x50a6)) + + +//------------------------ +// Module WWDG +//------------------------ + +/** struct containing WWDG module registers */ +typedef struct { + + /** WWDG control register (CR at 0x50d3) */ + union { + + /// bytewise access to CR + uint8_t byte; + + /// bitwise access to register CR + struct { + BITS T0 : 1; // bit 0 + BITS T1 : 1; // bit 1 + BITS T2 : 1; // bit 2 + BITS T3 : 1; // bit 3 + BITS T4 : 1; // bit 4 + BITS T5 : 1; // bit 5 + BITS T6 : 1; // bit 6 + BITS T7 : 1; // bit 7 + }; // CR bitfield + + /// register _WWDG_CR reset value + #define sfr_WWDG_CR_RESET_VALUE ((uint8_t) 0x7F) + + } CR; + + + /** WWDR window register (WR at 0x50d4) */ + union { + + /// bytewise access to WR + uint8_t byte; + + /// bitwise access to register WR + struct { + BITS W0 : 1; // bit 0 + BITS W1 : 1; // bit 1 + BITS W2 : 1; // bit 2 + BITS W3 : 1; // bit 3 + BITS W4 : 1; // bit 4 + BITS W5 : 1; // bit 5 + BITS W6 : 1; // bit 6 + BITS W7 : 1; // bit 7 + }; // WR bitfield + + /// register _WWDG_WR reset value + #define sfr_WWDG_WR_RESET_VALUE ((uint8_t) 0x7F) + + } WR; + +} WWDG_t; + +/// access to WWDG SFR registers +#define sfr_WWDG (*((WWDG_t*) 0x50d3)) + + +// undefine local macros +#undef BITS + +// required for C++ +#ifdef __cplusplus + } // extern "C" +#endif + +/*------------------------------------------------------------------------- + END OF MODULE DEFINITION FOR MULTIPLE INLUSION +-------------------------------------------------------------------------*/ +#endif // STM8L152C6_H diff --git a/ports/stm8_oss/stm8-include/STM8S105C6.h b/ports/stm8_oss/stm8-include/STM8S105C6.h new file mode 100644 index 00000000..5665013d --- /dev/null +++ b/ports/stm8_oss/stm8-include/STM8S105C6.h @@ -0,0 +1,4922 @@ +/*------------------------------------------------------------------------- + + STM8S105C6.h - Device Declarations + + STM8S/STM8AF, medium density with ROM bootloader + + Copyright (C) 2020, Georg Icking-Konert + + Mainstream Access line 8-bit MCU with 32 Kbytes Flash, 16 MHz CPU, integrated EEPROM + + datasheet: https://www.st.com/resource/en/datasheet/stm8s105c6.pdf + reference: RM0016 https://www.st.com/content/ccc/resource/technical/document/reference_manual/9a/1b/85/07/ca/eb/4f/dd/CD00190271.pdf/files/CD00190271.pdf/jcr:content/translations/en.CD00190271.pdf + + MIT License + + Copyright (c) 2020 Georg Icking-Konert + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. + +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- + MODULE DEFINITION FOR MULTIPLE INCLUSION +-------------------------------------------------------------------------*/ +#ifndef STM8S105C6_H +#define STM8S105C6_H + +// DEVICE NAME +#define DEVICE_STM8S105C6 + +// DEVICE FAMILY +#define FAMILY_STM8S + +// required for C++ +#ifdef __cplusplus + extern "C" { +#endif + + +/*------------------------------------------------------------------------- + INCLUDE FILES +-------------------------------------------------------------------------*/ +#include + + +/*------------------------------------------------------------------------- + COMPILER SPECIFIC SETTINGS +-------------------------------------------------------------------------*/ + +// Cosmic compiler +#if defined(__CSMC__) + + // macros to unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) @far @interrupt void func(void) ///< handler for interrupt service routine + #define ISR_HANDLER_TRAP(func) void @far @interrupt func(void) ///< handler for trap service routine + + // definition of inline functions + #define INLINE @inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() _asm("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() _asm("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() _asm("rim") ///< enable interrupt handling + #define TRIGGER_TRAP _asm("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() _asm("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() _asm("halt") ///< put controller to HALT mode + #define SW_RESET() _asm("dc.b $75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + + +// IAR Compiler +#elif defined(__ICCSTM8__) + + // include intrinsic functions + #include + + // macros to unify ISR declaration and implementation + #define STRINGVECTOR(x) #x + #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) + #define ISR_HANDLER( a, b ) \ + _Pragma( VECTOR_ID( (b)+2 ) ) \ + __interrupt void (a)( void ) + #define ISR_HANDLER_TRAP(a) \ + _Pragma( VECTOR_ID( 1 ) ) \ + __interrupt void (a) (void) + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __no_operation() ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __disable_interrupt() ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __enable_interrupt() ///< enable interrupt handling + #define TRIGGER_TRAP __trap() ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __wait_for_interrupt() ///< stop code execution and wait for interrupt + #define ENTER_HALT() __halt() ///< put controller to HALT mode + #define SW_RESET() __asm("dc8 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned char ///< data type in bit structs (deviating from C90 standard) + + +// SDCC compiler +#elif defined(__SDCC) + + // store SDCC version in preprocessor friendly way + #define SDCC_VERSION (__SDCC_VERSION_MAJOR * 10000 \ + + __SDCC_VERSION_MINOR * 100 \ + + __SDCC_VERSION_PATCH) + + // unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) void func(void) __interrupt(irq) ///< handler for interrupt service routine + #if SDCC_VERSION >= 30403 // traps require >=v3.4.3 + #define ISR_HANDLER_TRAP(func) void func() __trap ///< handler for trap service routine + #else + #error traps require SDCC >=3.4.3. Please update! + #endif + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __asm__("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __asm__("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __asm__("rim") ///< enable interrupt handling + #define TRIGGER_TRAP __asm__("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __asm__("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() __asm__("halt") ///< put controller to HALT mode + #define SW_RESET() __asm__(".db 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + +// unsupported compiler -> stop +#else + #error: compiler not supported +#endif + + +/*------------------------------------------------------------------------- + FOR CONVENIENT PIN ACCESS +-------------------------------------------------------------------------*/ + +#define PIN0 0x01 +#define PIN1 0x02 +#define PIN2 0x04 +#define PIN3 0x08 +#define PIN4 0x10 +#define PIN5 0x20 +#define PIN6 0x40 +#define PIN7 0x80 + + +/*------------------------------------------------------------------------- + DEVICE MEMORY (size in bytes) +-------------------------------------------------------------------------*/ + +// RAM +#define RAM_ADDR_START 0x000000 +#define RAM_ADDR_END 0x0007FF +#define RAM_SIZE 2048 + + +// FLASH +#define FLASH_ADDR_START 0x008000 +#define FLASH_ADDR_END 0x00FFFF +#define FLASH_SIZE 32768 + + +// SFR1 +#define SFR1_ADDR_START 0x005000 +#define SFR1_ADDR_END 0x0057FF +#define SFR1_SIZE 2048 + + +// SFR2 +#define SFR2_ADDR_START 0x007F00 +#define SFR2_ADDR_END 0x007FFF +#define SFR2_SIZE 256 + + +// BOOTROM +#define BOOTROM_ADDR_START 0x006000 +#define BOOTROM_ADDR_END 0x0067FF +#define BOOTROM_SIZE 2048 + + +// EEPROM +#define EEPROM_ADDR_START 0x004000 +#define EEPROM_ADDR_END 0x0043FF +#define EEPROM_SIZE 1024 + + +// OPTION +#define OPTION_ADDR_START 0x004800 +#define OPTION_ADDR_END 0x00487F +#define OPTION_SIZE 128 + + +// MEMORY WIDTH (>32kB flash exceeds 16bit, as flash starts at 0x8000) +#define FLASH_ADDR_WIDTH 16 ///< width of address space +#define FLASH_POINTER_T uint16_t ///< address variable type + + +/*------------------------------------------------------------------------- + UNIQUE IDENTIFIER (size in bytes) +-------------------------------------------------------------------------*/ + +#define UID_ADDR_START 0x48CD ///< start address of unique identifier +#define UID_SIZE 12 ///< size of unique identifier [B] +#define UID(N) (*((uint8_t*) (UID_ADDR_START+N))) ///< read unique identifier byte N + + +/*------------------------------------------------------------------------- + ISR Vector Table (SDCC, IAR) + Notes: + - IAR has an IRQ offset of +2 compared to datasheet and below numbers + - Cosmic uses a separate, device specific file 'stm8_interrupt_vector.c' + - different interrupt sources may share the same IRQ +-------------------------------------------------------------------------*/ + +// interrupt IRQ +#define _TLI_VECTOR_ 0 +#define _AWU_VECTOR_ 1 ///< AWU interrupt vector: enable: AWU_CSR1.AWUEN, pending: AWU_CSR1.AWUF, priority: ITC_SPR1.VECT1SPR +#define _CLK_CSS_VECTOR_ 2 ///< CLK_CSS interrupt vector: enable: CLK_CSSR.CSSDIE, pending: CLK_CSSR.CSSD, priority: ITC_SPR1.VECT2SPR +#define _CLK_SWITCH_VECTOR_ 2 ///< CLK_SWITCH interrupt vector: enable: CLK_SWCR.SWIEN, pending: CLK_SWCR.SWIF, priority: ITC_SPR1.VECT2SPR +#define _EXTI0_VECTOR_ 3 ///< EXTI0 interrupt vector: enable: PA_CR2.C20, pending: PA_IDR.IDR0, priority: ITC_SPR1.VECT3SPR +#define _EXTI1_VECTOR_ 4 ///< EXTI1 interrupt vector: enable: PB_CR2.C20, pending: PB_IDR.IDR0, priority: ITC_SPR2.VECT4SPR +#define _EXTI2_VECTOR_ 5 ///< EXTI2 interrupt vector: enable: PC_CR2.C20, pending: PC_IDR.IDR0, priority: ITC_SPR2.VECT5SPR +#define _EXTI3_VECTOR_ 6 ///< EXTI3 interrupt vector: enable: PD_CR2.C20, pending: PD_IDR.IDR0, priority: ITC_SPR2.VECT6SPR +#define _EXTI4_VECTOR_ 7 ///< EXTI4 interrupt vector: enable: PE_CR2.C20, pending: PE_IDR.IDR0, priority: ITC_SPR2.VECT7SPR +#define _SPI_CRCERR_VECTOR_ 10 ///< SPI_CRCERR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.CRCERR, priority: ITC_SPR3.VECT10SPR +#define _SPI_MODF_VECTOR_ 10 ///< SPI_MODF interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.MODF, priority: ITC_SPR3.VECT10SPR +#define _SPI_OVR_VECTOR_ 10 ///< SPI_OVR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.OVR, priority: ITC_SPR3.VECT10SPR +#define _SPI_RXNE_VECTOR_ 10 ///< SPI_RXNE interrupt vector: enable: SPI_ICR.RXIE, pending: SPI_SR.RXNE, priority: ITC_SPR3.VECT10SPR +#define _SPI_TXE_VECTOR_ 10 ///< SPI_TXE interrupt vector: enable: SPI_ICR.TXIE, pending: SPI_SR.TXE, priority: ITC_SPR3.VECT10SPR +#define _SPI_WKUP_VECTOR_ 10 ///< SPI_WKUP interrupt vector: enable: SPI_ICR.WKIE, pending: SPI_SR.WKUP, priority: ITC_SPR3.VECT10SPR +#define _TIM1_OVR_BIF_VECTOR_ 11 ///< TIM1_OVR_BIF interrupt vector: enable: TIM1_IER.BIE, pending: TIM1_SR1.BIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_OVR_TIF_VECTOR_ 11 ///< TIM1_OVR_TIF interrupt vector: enable: TIM1_IER.TIE, pending: TIM1_SR1.TIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_OVR_UIF_VECTOR_ 11 ///< TIM1_OVR_UIF interrupt vector: enable: TIM1_IER.UIE, pending: TIM1_SR1.UIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_CAPCOM_CC1IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC1IF interrupt vector: enable: TIM1_IER.CC1IE, pending: TIM1_SR1.CC1IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC2IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC2IF interrupt vector: enable: TIM1_IER.CC2IE, pending: TIM1_SR1.CC2IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC3IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC3IF interrupt vector: enable: TIM1_IER.CC3IE, pending: TIM1_SR1.CC3IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC4IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC4IF interrupt vector: enable: TIM1_IER.CC4IE, pending: TIM1_SR1.CC4IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_COMIF_VECTOR_ 12 ///< TIM1_CAPCOM_COMIF interrupt vector: enable: TIM1_IER.COMIE, pending: TIM1_SR1.COMIF, priority: ITC_SPR4.VECT12SPR +#define _TIM2_OVR_UIF_VECTOR_ 13 ///< TIM2_OVR_UIF interrupt vector: enable: TIM2_IER.UIE, pending: TIM2_SR1.UIF, priority: ITC_SPR4.VECT13SPR +#define _TIM3_OVR_UIF_VECTOR_ 15 ///< TIM3_OVR_UIF interrupt vector: enable: TIM3_IER.UIE, pending: TIM3_SR1.UIF, priority: ITC_SPR4.VECT15SPR +#define _TIM2_CAPCOM_CC1IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC1IF interrupt vector: enable: TIM2_IER.CC1IE, pending: TIM2_SR1.CC1IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_CC2IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC2IF interrupt vector: enable: TIM2_IER.CC2IE, pending: TIM2_SR1.CC2IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_CC3IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC3IF interrupt vector: enable: TIM2_IER.CC3IE, pending: TIM2_SR1.CC3IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_TIF_VECTOR_ 14 ///< TIM2_CAPCOM_TIF interrupt vector: enable: TIM2_IER.TIE, pending: TIM2_SR1.TIF, priority: ITC_SPR4.VECT14SPR +#define _TIM3_CAPCOM_CC1IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC1IF interrupt vector: enable: TIM3_IER.CC1IE, pending: TIM3_SR1.CC1IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_CC2IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC2IF interrupt vector: enable: TIM3_IER.CC2IE, pending: TIM3_SR1.CC2IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_CC3IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC3IF interrupt vector: enable: TIM3_IER.CC3IE, pending: TIM3_SR1.CC3IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_TIF_VECTOR_ 16 ///< TIM3_CAPCOM_TIF interrupt vector: enable: TIM3_IER.TIE, pending: TIM3_SR1.TIF, priority: ITC_SPR5.VECT16SPR +#define _I2C_ADD10_VECTOR_ 19 ///< I2C_ADD10 interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADD10, priority: ITC_SPR5.VECT19SPR +#define _I2C_ADDR_VECTOR_ 19 ///< I2C_ADDR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADDR, priority: ITC_SPR5.VECT19SPR +#define _I2C_AF_VECTOR_ 19 ///< I2C_AF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.AF, priority: ITC_SPR5.VECT19SPR +#define _I2C_ARLO_VECTOR_ 19 ///< I2C_ARLO interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.ARLO, priority: ITC_SPR5.VECT19SPR +#define _I2C_BERR_VECTOR_ 19 ///< I2C_BERR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.BERR, priority: ITC_SPR5.VECT19SPR +#define _I2C_BTF_VECTOR_ 19 ///< I2C_BTF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.BTF, priority: ITC_SPR5.VECT19SPR +#define _I2C_OVR_VECTOR_ 19 ///< I2C_OVR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.OVR, priority: ITC_SPR5.VECT19SPR +#define _I2C_RXNE_VECTOR_ 19 ///< I2C_RXNE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.RXNE, priority: ITC_SPR5.VECT19SPR +#define _I2C_SB_VECTOR_ 19 ///< I2C_SB interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.SB, priority: ITC_SPR5.VECT19SPR +#define _I2C_STOPF_VECTOR_ 19 ///< I2C_STOPF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.STOPF, priority: ITC_SPR5.VECT19SPR +#define _I2C_TXE_VECTOR_ 19 ///< I2C_TXE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.TXE, priority: ITC_SPR5.VECT19SPR +#define _I2C_WUFH_VECTOR_ 19 ///< I2C_WUFH interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.WUFH, priority: ITC_SPR5.VECT19SPR +#define _UART2_T_TC_VECTOR_ 20 ///< UART2_T_TC interrupt vector: enable: UART2_CR2.TCIEN, pending: UART2_SR.TC, priority: ITC_SPR6.VECT20SPR +#define _UART2_T_TXE_VECTOR_ 20 ///< UART2_T_TXE interrupt vector: enable: UART2_CR2.TIEN, pending: UART2_SR.TXE, priority: ITC_SPR6.VECT20SPR +#define _UART2_R_IDLE_VECTOR_ 21 ///< UART2_R_IDLE interrupt vector: enable: UART2_CR2.ILIEN, pending: UART2_SR.IDLE, priority: ITC_SPR6.VECT21SPR +#define _UART2_R_LBDF_VECTOR_ 21 ///< UART2_R_LBDF interrupt vector: enable: UART2_CR4.LBDIEN, pending: UART2_CR4.LBDF, priority: ITC_SPR6.VECT21SPR +#define _UART2_R_OR_VECTOR_ 21 ///< UART2_R_OR interrupt vector: enable: UART2_CR2.RIEN, pending: UART2_SR.OR_LHE, priority: ITC_SPR6.VECT21SPR +#define _UART2_R_PE_VECTOR_ 21 ///< UART2_R_PE interrupt vector: enable: UART2_CR1.PIEN, pending: UART2_SR.PE, priority: ITC_SPR6.VECT21SPR +#define _UART2_R_RXNE_VECTOR_ 21 ///< UART2_R_RXNE interrupt vector: enable: UART2_CR2.RIEN, pending: UART2_SR.RXNE, priority: ITC_SPR6.VECT21SPR +#define _ADC1_AWDG_VECTOR_ 22 ///< ADC1_AWDG interrupt vector: enable: ADC_CSR.AWDIE, pending: ADC_CSR.AWD, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS0_VECTOR_ 22 ///< ADC1_AWS0 interrupt vector: enable: ADC_AWCRL.AWEN0, pending: ADC_AWSRL.AWS0, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS1_VECTOR_ 22 ///< ADC1_AWS1 interrupt vector: enable: ADC_AWCRL.AWEN1, pending: ADC_AWSRL.AWS1, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS2_VECTOR_ 22 ///< ADC1_AWS2 interrupt vector: enable: ADC_AWCRL.AWEN2, pending: ADC_AWSRL.AWS2, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS3_VECTOR_ 22 ///< ADC1_AWS3 interrupt vector: enable: ADC_AWCRL.AWEN3, pending: ADC_AWSRL.AWS3, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS4_VECTOR_ 22 ///< ADC1_AWS4 interrupt vector: enable: ADC_AWCRL.AWEN4, pending: ADC_AWSRL.AWS4, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS5_VECTOR_ 22 ///< ADC1_AWS5 interrupt vector: enable: ADC_AWCRL.AWEN5, pending: ADC_AWSRL.AWS5, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS6_VECTOR_ 22 ///< ADC1_AWS6 interrupt vector: enable: ADC_AWCRL.AWEN6, pending: ADC_AWSRL.AWS6, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS7_VECTOR_ 22 ///< ADC1_AWS7 interrupt vector: enable: ADC_AWCRL.AWEN7, pending: ADC_AWSRL.AWS7, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS8_VECTOR_ 22 ///< ADC1_AWS8 interrupt vector: enable: ADC_AWCRH.AWEN8, pending: ADC_AWSRH.AWS8, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS9_VECTOR_ 22 ///< ADC1_AWS9 interrupt vector: enable: ADC_AWCRH.AWEN9, pending: ADC_AWSRH.AWS9, priority: ITC_SPR6.VECT22SPR +#define _ADC1_EOC_VECTOR_ 22 ///< ADC1_EOC interrupt vector: enable: ADC_CSR.EOCIE, pending: ADC_CSR.EOC, priority: ITC_SPR6.VECT22SPR +#define _TIM4_OVR_UIF_VECTOR_ 23 ///< TIM4_OVR_UIF interrupt vector: enable: TIM4_IER.UIE, pending: TIM4_SR.UIF, priority: ITC_SPR6.VECT23SPR +#define _FLASH_EOP_VECTOR_ 24 ///< FLASH_EOP interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.EOP, priority: ITC_SPR6.VECT24SPR +#define _FLASH_WR_PG_DIS_VECTOR_ 24 ///< FLASH_WR_PG_DIS interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.WR_PG_DIS, priority: ITC_SPR6.VECT24SPR + + +/*------------------------------------------------------------------------- + DEFINITION OF STM8 PERIPHERAL REGISTERS +-------------------------------------------------------------------------*/ + +//------------------------ +// Module ADC1 +//------------------------ + +/** struct containing ADC1 module registers */ +typedef struct { + + /** ADC data buffer registers (DB0RH at 0x53e0) */ + union { + + /// bytewise access to DB0RH + uint8_t byte; + + /// bitwise access to register DB0RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB0RH bitfield + + /// register _ADC1_DB0RH reset value + #define sfr_ADC1_DB0RH_RESET_VALUE ((uint8_t) 0x00) + + } DB0RH; + + + /** ADC data buffer registers (DB0RL at 0x53e1) */ + union { + + /// bytewise access to DB0RL + uint8_t byte; + + /// bitwise access to register DB0RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB0RL bitfield + + /// register _ADC1_DB0RL reset value + #define sfr_ADC1_DB0RL_RESET_VALUE ((uint8_t) 0x00) + + } DB0RL; + + + /** ADC data buffer registers (DB1RH at 0x53e2) */ + union { + + /// bytewise access to DB1RH + uint8_t byte; + + /// bitwise access to register DB1RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB1RH bitfield + + /// register _ADC1_DB1RH reset value + #define sfr_ADC1_DB1RH_RESET_VALUE ((uint8_t) 0x00) + + } DB1RH; + + + /** ADC data buffer registers (DB1RL at 0x53e3) */ + union { + + /// bytewise access to DB1RL + uint8_t byte; + + /// bitwise access to register DB1RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB1RL bitfield + + /// register _ADC1_DB1RL reset value + #define sfr_ADC1_DB1RL_RESET_VALUE ((uint8_t) 0x00) + + } DB1RL; + + + /** ADC data buffer registers (DB2RH at 0x53e4) */ + union { + + /// bytewise access to DB2RH + uint8_t byte; + + /// bitwise access to register DB2RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB2RH bitfield + + /// register _ADC1_DB2RH reset value + #define sfr_ADC1_DB2RH_RESET_VALUE ((uint8_t) 0x00) + + } DB2RH; + + + /** ADC data buffer registers (DB2RL at 0x53e5) */ + union { + + /// bytewise access to DB2RL + uint8_t byte; + + /// bitwise access to register DB2RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB2RL bitfield + + /// register _ADC1_DB2RL reset value + #define sfr_ADC1_DB2RL_RESET_VALUE ((uint8_t) 0x00) + + } DB2RL; + + + /** ADC data buffer registers (DB3RH at 0x53e6) */ + union { + + /// bytewise access to DB3RH + uint8_t byte; + + /// bitwise access to register DB3RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB3RH bitfield + + /// register _ADC1_DB3RH reset value + #define sfr_ADC1_DB3RH_RESET_VALUE ((uint8_t) 0x00) + + } DB3RH; + + + /** ADC data buffer registers (DB3RL at 0x53e7) */ + union { + + /// bytewise access to DB3RL + uint8_t byte; + + /// bitwise access to register DB3RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB3RL bitfield + + /// register _ADC1_DB3RL reset value + #define sfr_ADC1_DB3RL_RESET_VALUE ((uint8_t) 0x00) + + } DB3RL; + + + /** ADC data buffer registers (DB4RH at 0x53e8) */ + union { + + /// bytewise access to DB4RH + uint8_t byte; + + /// bitwise access to register DB4RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB4RH bitfield + + /// register _ADC1_DB4RH reset value + #define sfr_ADC1_DB4RH_RESET_VALUE ((uint8_t) 0x00) + + } DB4RH; + + + /** ADC data buffer registers (DB4RL at 0x53e9) */ + union { + + /// bytewise access to DB4RL + uint8_t byte; + + /// bitwise access to register DB4RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB4RL bitfield + + /// register _ADC1_DB4RL reset value + #define sfr_ADC1_DB4RL_RESET_VALUE ((uint8_t) 0x00) + + } DB4RL; + + + /** ADC data buffer registers (DB5RH at 0x53ea) */ + union { + + /// bytewise access to DB5RH + uint8_t byte; + + /// bitwise access to register DB5RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB5RH bitfield + + /// register _ADC1_DB5RH reset value + #define sfr_ADC1_DB5RH_RESET_VALUE ((uint8_t) 0x00) + + } DB5RH; + + + /** ADC data buffer registers (DB5RL at 0x53eb) */ + union { + + /// bytewise access to DB5RL + uint8_t byte; + + /// bitwise access to register DB5RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB5RL bitfield + + /// register _ADC1_DB5RL reset value + #define sfr_ADC1_DB5RL_RESET_VALUE ((uint8_t) 0x00) + + } DB5RL; + + + /** ADC data buffer registers (DB6RH at 0x53ec) */ + union { + + /// bytewise access to DB6RH + uint8_t byte; + + /// bitwise access to register DB6RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB6RH bitfield + + /// register _ADC1_DB6RH reset value + #define sfr_ADC1_DB6RH_RESET_VALUE ((uint8_t) 0x00) + + } DB6RH; + + + /** ADC data buffer registers (DB6RL at 0x53ed) */ + union { + + /// bytewise access to DB6RL + uint8_t byte; + + /// bitwise access to register DB6RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB6RL bitfield + + /// register _ADC1_DB6RL reset value + #define sfr_ADC1_DB6RL_RESET_VALUE ((uint8_t) 0x00) + + } DB6RL; + + + /** ADC data buffer registers (DB7RH at 0x53ee) */ + union { + + /// bytewise access to DB7RH + uint8_t byte; + + /// bitwise access to register DB7RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB7RH bitfield + + /// register _ADC1_DB7RH reset value + #define sfr_ADC1_DB7RH_RESET_VALUE ((uint8_t) 0x00) + + } DB7RH; + + + /** ADC data buffer registers (DB7RL at 0x53ef) */ + union { + + /// bytewise access to DB7RL + uint8_t byte; + + /// bitwise access to register DB7RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB7RL bitfield + + /// register _ADC1_DB7RL reset value + #define sfr_ADC1_DB7RL_RESET_VALUE ((uint8_t) 0x00) + + } DB7RL; + + + /** ADC data buffer registers (DB8RH at 0x53f0) */ + union { + + /// bytewise access to DB8RH + uint8_t byte; + + /// bitwise access to register DB8RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB8RH bitfield + + /// register _ADC1_DB8RH reset value + #define sfr_ADC1_DB8RH_RESET_VALUE ((uint8_t) 0x00) + + } DB8RH; + + + /** ADC data buffer registers (DB8RL at 0x53f1) */ + union { + + /// bytewise access to DB8RL + uint8_t byte; + + /// bitwise access to register DB8RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB8RL bitfield + + /// register _ADC1_DB8RL reset value + #define sfr_ADC1_DB8RL_RESET_VALUE ((uint8_t) 0x00) + + } DB8RL; + + + /** ADC data buffer registers (DB9RH at 0x53f2) */ + union { + + /// bytewise access to DB9RH + uint8_t byte; + + /// bitwise access to register DB9RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB9RH bitfield + + /// register _ADC1_DB9RH reset value + #define sfr_ADC1_DB9RH_RESET_VALUE ((uint8_t) 0x00) + + } DB9RH; + + + /** ADC data buffer registers (DB9RL at 0x53f3) */ + union { + + /// bytewise access to DB9RL + uint8_t byte; + + /// bitwise access to register DB9RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB9RL bitfield + + /// register _ADC1_DB9RL reset value + #define sfr_ADC1_DB9RL_RESET_VALUE ((uint8_t) 0x00) + + } DB9RL; + + + /// Reserved register (12B) + uint8_t Reserved_1[12]; + + + /** ADC control/status register (CSR at 0x5400) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// bitwise access to register CSR + struct { + BITS CH : 4; // bits 0-3 + BITS AWDIE : 1; // bit 4 + BITS EOCIE : 1; // bit 5 + BITS AWD : 1; // bit 6 + BITS EOC : 1; // bit 7 + }; // CSR bitfield + + /// register _ADC1_CSR reset value + #define sfr_ADC1_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + + + /** ADC configuration register 1 (CR1 at 0x5401) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS ADON : 1; // bit 0 + BITS CONT : 1; // bit 1 + BITS : 2; // 2 bits + BITS SPSEL : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR1 bitfield + + /// register _ADC1_CR1 reset value + #define sfr_ADC1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** ADC configuration register 2 (CR2 at 0x5402) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS : 1; // 1 bit + BITS SCAN : 1; // bit 1 + BITS : 1; // 1 bit + BITS ALIGN : 1; // bit 3 + BITS EXTSEL : 2; // bits 4-5 + BITS EXTTRIG : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _ADC1_CR2 reset value + #define sfr_ADC1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** ADC configuration register 3 (CR3 at 0x5403) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS : 6; // 6 bits + BITS OVR : 1; // bit 6 + BITS DBUF : 1; // bit 7 + }; // CR3 bitfield + + /// register _ADC1_CR3 reset value + #define sfr_ADC1_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** ADC data register high (DRH at 0x5404) */ + union { + + /// bytewise access to DRH + uint8_t byte; + + /// bitwise access to register DRH + struct { + BITS DH : 8; // bits 0-7 + }; // DRH bitfield + + /// register _ADC1_DRH reset value + #define sfr_ADC1_DRH_RESET_VALUE ((uint8_t) 0x00) + + } DRH; + + + /** ADC data register low (DRL at 0x5405) */ + union { + + /// bytewise access to DRL + uint8_t byte; + + /// bitwise access to register DRL + struct { + BITS DL : 8; // bits 0-7 + }; // DRL bitfield + + /// register _ADC1_DRL reset value + #define sfr_ADC1_DRL_RESET_VALUE ((uint8_t) 0x00) + + } DRL; + + + /** ADC Schmitt trigger disable register high (TDRH at 0x5406) */ + union { + + /// bytewise access to TDRH + uint8_t byte; + + /// bitwise access to register TDRH + struct { + BITS TD : 8; // bits 0-7 + }; // TDRH bitfield + + /// register _ADC1_TDRH reset value + #define sfr_ADC1_TDRH_RESET_VALUE ((uint8_t) 0x00) + + } TDRH; + + + /** ADC Schmitt trigger disable register low (TDRL at 0x5407) */ + union { + + /// bytewise access to TDRL + uint8_t byte; + + /// bitwise access to register TDRL + struct { + BITS TL : 8; // bits 0-7 + }; // TDRL bitfield + + /// register _ADC1_TDRL reset value + #define sfr_ADC1_TDRL_RESET_VALUE ((uint8_t) 0x00) + + } TDRL; + + + /** ADC high threshold register high (HTRH at 0x5408) */ + union { + + /// bytewise access to HTRH + uint8_t byte; + + /// bitwise access to register HTRH + struct { + BITS HT : 8; // bits 0-7 + }; // HTRH bitfield + + /// register _ADC1_HTRH reset value + #define sfr_ADC1_HTRH_RESET_VALUE ((uint8_t) 0x03) + + } HTRH; + + + /** ADC high threshold register low (HTRL at 0x5409) */ + union { + + /// bytewise access to HTRL + uint8_t byte; + + /// bitwise access to register HTRL + struct { + BITS HT : 2; // bits 0-1 + BITS : 6; // 6 bits + }; // HTRL bitfield + + /// register _ADC1_HTRL reset value + #define sfr_ADC1_HTRL_RESET_VALUE ((uint8_t) 0xFF) + + } HTRL; + + + /** ADC low threshold register high (LTRH at 0x540a) */ + union { + + /// bytewise access to LTRH + uint8_t byte; + + /// bitwise access to register LTRH + struct { + BITS LT : 8; // bits 0-7 + }; // LTRH bitfield + + /// register _ADC1_LTRH reset value + #define sfr_ADC1_LTRH_RESET_VALUE ((uint8_t) 0x00) + + } LTRH; + + + /** ADC low threshold register low (LTRL at 0x540b) */ + union { + + /// bytewise access to LTRL + uint8_t byte; + + /// bitwise access to register LTRL + struct { + BITS LT : 2; // bits 0-1 + BITS : 6; // 6 bits + }; // LTRL bitfield + + /// register _ADC1_LTRL reset value + #define sfr_ADC1_LTRL_RESET_VALUE ((uint8_t) 0x00) + + } LTRL; + + + /** ADC analog watchdog status register high (AWSRH at 0x540c) */ + union { + + /// bytewise access to AWSRH + uint8_t byte; + + /// bitwise access to register AWSRH + struct { + BITS AWS8 : 1; // bit 0 + BITS AWS9 : 1; // bit 1 + BITS : 6; // 6 bits + }; // AWSRH bitfield + + /// register _ADC1_AWSRH reset value + #define sfr_ADC1_AWSRH_RESET_VALUE ((uint8_t) 0x00) + + } AWSRH; + + + /** ADC analog watchdog status register low (AWSRL at 0x540d) */ + union { + + /// bytewise access to AWSRL + uint8_t byte; + + /// bitwise access to register AWSRL + struct { + BITS AWS0 : 1; // bit 0 + BITS AWS1 : 1; // bit 1 + BITS AWS2 : 1; // bit 2 + BITS AWS3 : 1; // bit 3 + BITS AWS4 : 1; // bit 4 + BITS AWS5 : 1; // bit 5 + BITS AWS6 : 1; // bit 6 + BITS AWS7 : 1; // bit 7 + }; // AWSRL bitfield + + /// register _ADC1_AWSRL reset value + #define sfr_ADC1_AWSRL_RESET_VALUE ((uint8_t) 0x00) + + } AWSRL; + + + /** ADC analog watchdog control register high (AWCRH at 0x540e) */ + union { + + /// bytewise access to AWCRH + uint8_t byte; + + /// bitwise access to register AWCRH + struct { + BITS AWEN8 : 1; // bit 0 + BITS AWEN9 : 1; // bit 1 + BITS : 6; // 6 bits + }; // AWCRH bitfield + + /// register _ADC1_AWCRH reset value + #define sfr_ADC1_AWCRH_RESET_VALUE ((uint8_t) 0x00) + + } AWCRH; + + + /** ADC analog watchdog control register low (AWCRL at 0x540f) */ + union { + + /// bytewise access to AWCRL + uint8_t byte; + + /// bitwise access to register AWCRL + struct { + BITS AWEN0 : 1; // bit 0 + BITS AWEN1 : 1; // bit 1 + BITS AWEN2 : 1; // bit 2 + BITS AWEN3 : 1; // bit 3 + BITS AWEN4 : 1; // bit 4 + BITS AWEN5 : 1; // bit 5 + BITS AWEN6 : 1; // bit 6 + BITS AWEN7 : 1; // bit 7 + }; // AWCRL bitfield + + /// register _ADC1_AWCRL reset value + #define sfr_ADC1_AWCRL_RESET_VALUE ((uint8_t) 0x00) + + } AWCRL; + +} ADC1_t; + +/// access to ADC1 SFR registers +#define sfr_ADC1 (*((ADC1_t*) 0x53e0)) + + +//------------------------ +// Module AWU +//------------------------ + +/** struct containing AWU module registers */ +typedef struct { + + /** AWU control/status register 1 (CSR1 at 0x50f0) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// bitwise access to register CSR1 + struct { + BITS MSR : 1; // bit 0 + BITS : 3; // 3 bits + BITS AWUEN : 1; // bit 4 + BITS AWUF : 1; // bit 5 + BITS : 2; // 2 bits + }; // CSR1 bitfield + + /// register _AWU_CSR1 reset value + #define sfr_AWU_CSR1_RESET_VALUE ((uint8_t) 0x00) + + } CSR1; + + + /** AWU asynchronous prescaler buffer register (APR at 0x50f1) */ + union { + + /// bytewise access to APR + uint8_t byte; + + /// bitwise access to register APR + struct { + BITS APR : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // APR bitfield + + /// register _AWU_APR reset value + #define sfr_AWU_APR_RESET_VALUE ((uint8_t) 0x3F) + + } APR; + + + /** AWU timebase selection register (TBR at 0x50f2) */ + union { + + /// bytewise access to TBR + uint8_t byte; + + /// bitwise access to register TBR + struct { + BITS AWUTB : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // TBR bitfield + + /// register _AWU_TBR reset value + #define sfr_AWU_TBR_RESET_VALUE ((uint8_t) 0x00) + + } TBR; + +} AWU_t; + +/// access to AWU SFR registers +#define sfr_AWU (*((AWU_t*) 0x50f0)) + + +//------------------------ +// Module BEEP +//------------------------ + +/** struct containing BEEP module registers */ +typedef struct { + + /** BEEP control/status register (CSR at 0x50f3) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// bitwise access to register CSR + struct { + BITS BEEPDIV : 5; // bits 0-4 + BITS BEEPEN : 1; // bit 5 + BITS BEEPSEL : 2; // bits 6-7 + }; // CSR bitfield + + /// register _BEEP_CSR reset value + #define sfr_BEEP_CSR_RESET_VALUE ((uint8_t) 0x1F) + + } CSR; + +} BEEP_t; + +/// access to BEEP SFR registers +#define sfr_BEEP (*((BEEP_t*) 0x50f3)) + + +//------------------------ +// Module CLK +//------------------------ + +/** struct containing CLK module registers */ +typedef struct { + + /** Internal clock control register (ICKR at 0x50c0) */ + union { + + /// bytewise access to ICKR + uint8_t byte; + + /// bitwise access to register ICKR + struct { + BITS HSIEN : 1; // bit 0 + BITS HSIRDY : 1; // bit 1 + BITS FHW : 1; // bit 2 + BITS LSIEN : 1; // bit 3 + BITS LSIRDY : 1; // bit 4 + BITS REGAH : 1; // bit 5 + BITS : 2; // 2 bits + }; // ICKR bitfield + + /// register _CLK_ICKR reset value + #define sfr_CLK_ICKR_RESET_VALUE ((uint8_t) 0x01) + + } ICKR; + + + /** External clock control register (ECKR at 0x50c1) */ + union { + + /// bytewise access to ECKR + uint8_t byte; + + /// bitwise access to register ECKR + struct { + BITS HSEEN : 1; // bit 0 + BITS HSERDY : 1; // bit 1 + BITS : 6; // 6 bits + }; // ECKR bitfield + + /// register _CLK_ECKR reset value + #define sfr_CLK_ECKR_RESET_VALUE ((uint8_t) 0x00) + + } ECKR; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** Clock master status register (CMSR at 0x50c3) */ + union { + + /// bytewise access to CMSR + uint8_t byte; + + /// bitwise access to register CMSR + struct { + BITS CKM : 8; // bits 0-7 + }; // CMSR bitfield + + /// register _CLK_CMSR reset value + #define sfr_CLK_CMSR_RESET_VALUE ((uint8_t) 0xE1) + + } CMSR; + + + /** Clock master switch register (SWR at 0x50c4) */ + union { + + /// bytewise access to SWR + uint8_t byte; + + /// bitwise access to register SWR + struct { + BITS SWI : 8; // bits 0-7 + }; // SWR bitfield + + /// register _CLK_SWR reset value + #define sfr_CLK_SWR_RESET_VALUE ((uint8_t) 0xE1) + + } SWR; + + + /** Clock switch control register (SWCR at 0x50c5) */ + union { + + /// bytewise access to SWCR + uint8_t byte; + + /// bitwise access to register SWCR + struct { + BITS SWBSY : 1; // bit 0 + BITS SWEN : 1; // bit 1 + BITS SWIEN : 1; // bit 2 + BITS SWIF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SWCR bitfield + + /// register _CLK_SWCR reset value + #define sfr_CLK_SWCR_RESET_VALUE ((uint8_t) 0x00) + + } SWCR; + + + /** Clock divider register (CKDIVR at 0x50c6) */ + union { + + /// bytewise access to CKDIVR + uint8_t byte; + + /// bitwise access to register CKDIVR + struct { + BITS CPUDIV : 3; // bits 0-2 + BITS HSIDIV : 2; // bits 3-4 + BITS : 3; // 3 bits + }; // CKDIVR bitfield + + /// register _CLK_CKDIVR reset value + #define sfr_CLK_CKDIVR_RESET_VALUE ((uint8_t) 0x18) + + } CKDIVR; + + + /** Peripheral clock gating register 1 (PCKENR1 at 0x50c7) */ + union { + + /// bytewise access to PCKENR1 + uint8_t byte; + + /// bitwise access to register PCKENR1 + struct { + BITS PCKEN : 8; // bits 0-7 + }; // PCKENR1 bitfield + + /// register _CLK_PCKENR1 reset value + #define sfr_CLK_PCKENR1_RESET_VALUE ((uint8_t) 0xFF) + + } PCKENR1; + + + /** Clock security system register (CSSR at 0x50c8) */ + union { + + /// bytewise access to CSSR + uint8_t byte; + + /// bitwise access to register CSSR + struct { + BITS CSSEN : 1; // bit 0 + BITS AUX : 1; // bit 1 + BITS CSSDIE : 1; // bit 2 + BITS CSSD : 1; // bit 3 + BITS : 4; // 4 bits + }; // CSSR bitfield + + /// register _CLK_CSSR reset value + #define sfr_CLK_CSSR_RESET_VALUE ((uint8_t) 0x00) + + } CSSR; + + + /** Configurable clock control register (CCOR at 0x50c9) */ + union { + + /// bytewise access to CCOR + uint8_t byte; + + /// bitwise access to register CCOR + struct { + BITS CCOEN : 1; // bit 0 + BITS CCOSEL : 4; // bits 1-4 + BITS CCORDY : 1; // bit 5 + BITS CC0BSY : 1; // bit 6 + BITS : 1; // 1 bit + }; // CCOR bitfield + + /// register _CLK_CCOR reset value + #define sfr_CLK_CCOR_RESET_VALUE ((uint8_t) 0x00) + + } CCOR; + + + /** Peripheral clock gating register 2 (PCKENR2 at 0x50ca) */ + union { + + /// bytewise access to PCKENR2 + uint8_t byte; + + /// bitwise access to register PCKENR2 + struct { + BITS PCKEN2 : 8; // bits 0-7 + }; // PCKENR2 bitfield + + /// register _CLK_PCKENR2 reset value + #define sfr_CLK_PCKENR2_RESET_VALUE ((uint8_t) 0xFF) + + } PCKENR2; + + + /** CAN clock control register (CANCCR at 0x50cb) */ + union { + + /// bytewise access to CANCCR + uint8_t byte; + + /// bitwise access to register CANCCR + struct { + BITS CANDIV : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // CANCCR bitfield + + /// register _CLK_CANCCR reset value + #define sfr_CLK_CANCCR_RESET_VALUE ((uint8_t) 0x00) + + } CANCCR; + + + /** HSI clock calibration trimming register (HSITRIMR at 0x50cc) */ + union { + + /// bytewise access to HSITRIMR + uint8_t byte; + + /// bitwise access to register HSITRIMR + struct { + BITS HSITRIM : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // HSITRIMR bitfield + + /// register _CLK_HSITRIMR reset value + #define sfr_CLK_HSITRIMR_RESET_VALUE ((uint8_t) 0x00) + + } HSITRIMR; + + + /** SWIM clock control register (SWIMCCR at 0x50cd) */ + union { + + /// bytewise access to SWIMCCR + uint8_t byte; + + /// bitwise access to register SWIMCCR + struct { + BITS SWIMCLK : 1; // bit 0 + BITS : 7; // 7 bits + }; // SWIMCCR bitfield + + /// register _CLK_SWIMCCR reset value + #define sfr_CLK_SWIMCCR_RESET_VALUE ((uint8_t) 0x00) + + } SWIMCCR; + +} CLK_t; + +/// access to CLK SFR registers +#define sfr_CLK (*((CLK_t*) 0x50c0)) + + +//------------------------ +// Module CPU +//------------------------ + +/** struct containing CPU module registers */ +typedef struct { + + /** Accumulator (A at 0x7f00) */ + union { + + /// bytewise access to A + uint8_t byte; + + /// skip bitwise access to register A + + /// register _CPU_A reset value + #define sfr_CPU_A_RESET_VALUE ((uint8_t) 0x00) + + } A; + + + /** Program counter extended (PCE at 0x7f01) */ + union { + + /// bytewise access to PCE + uint8_t byte; + + /// skip bitwise access to register PCE + + /// register _CPU_PCE reset value + #define sfr_CPU_PCE_RESET_VALUE ((uint8_t) 0x00) + + } PCE; + + + /** Program counter high (PCH at 0x7f02) */ + union { + + /// bytewise access to PCH + uint8_t byte; + + /// skip bitwise access to register PCH + + /// register _CPU_PCH reset value + #define sfr_CPU_PCH_RESET_VALUE ((uint8_t) 0x00) + + } PCH; + + + /** Program counter low (PCL at 0x7f03) */ + union { + + /// bytewise access to PCL + uint8_t byte; + + /// skip bitwise access to register PCL + + /// register _CPU_PCL reset value + #define sfr_CPU_PCL_RESET_VALUE ((uint8_t) 0x00) + + } PCL; + + + /** X index register high (XH at 0x7f04) */ + union { + + /// bytewise access to XH + uint8_t byte; + + /// skip bitwise access to register XH + + /// register _CPU_XH reset value + #define sfr_CPU_XH_RESET_VALUE ((uint8_t) 0x00) + + } XH; + + + /** X index register low (XL at 0x7f05) */ + union { + + /// bytewise access to XL + uint8_t byte; + + /// skip bitwise access to register XL + + /// register _CPU_XL reset value + #define sfr_CPU_XL_RESET_VALUE ((uint8_t) 0x00) + + } XL; + + + /** Y index register high (YH at 0x7f06) */ + union { + + /// bytewise access to YH + uint8_t byte; + + /// skip bitwise access to register YH + + /// register _CPU_YH reset value + #define sfr_CPU_YH_RESET_VALUE ((uint8_t) 0x00) + + } YH; + + + /** Y index register low (YL at 0x7f07) */ + union { + + /// bytewise access to YL + uint8_t byte; + + /// skip bitwise access to register YL + + /// register _CPU_YL reset value + #define sfr_CPU_YL_RESET_VALUE ((uint8_t) 0x00) + + } YL; + + + /** Stack pointer high (SPH at 0x7f08) */ + union { + + /// bytewise access to SPH + uint8_t byte; + + /// skip bitwise access to register SPH + + /// register _CPU_SPH reset value + #define sfr_CPU_SPH_RESET_VALUE ((uint8_t) 0x07) + + } SPH; + + + /** Stack pointer low (SPL at 0x7f09) */ + union { + + /// bytewise access to SPL + uint8_t byte; + + /// skip bitwise access to register SPL + + /// register _CPU_SPL reset value + #define sfr_CPU_SPL_RESET_VALUE ((uint8_t) 0xFF) + + } SPL; + + + /** Condition code register (CCR at 0x7f0a) */ + union { + + /// bytewise access to CCR + uint8_t byte; + + /// bitwise access to register CCR + struct { + BITS C : 1; // bit 0 + BITS Z : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS I0 : 1; // bit 3 + BITS H : 1; // bit 4 + BITS I1 : 1; // bit 5 + BITS : 1; // 1 bit + BITS V : 1; // bit 7 + }; // CCR bitfield + + /// register _CPU_CCR reset value + #define sfr_CPU_CCR_RESET_VALUE ((uint8_t) 0x28) + + } CCR; + + + /// Reserved register (85B) + uint8_t Reserved_1[85]; + + + /** Global configuration register (CFG_GCR at 0x7f60) */ + union { + + /// bytewise access to CFG_GCR + uint8_t byte; + + /// bitwise access to register CFG_GCR + struct { + BITS SWO : 1; // bit 0 + BITS AL : 1; // bit 1 + BITS : 6; // 6 bits + }; // CFG_GCR bitfield + + /// register _CPU_CFG_GCR reset value + #define sfr_CPU_CFG_GCR_RESET_VALUE ((uint8_t) 0x00) + + } CFG_GCR; + +} CPU_t; + +/// access to CPU SFR registers +#define sfr_CPU (*((CPU_t*) 0x7f00)) + + +//------------------------ +// Module DM +//------------------------ + +/** struct containing DM module registers */ +typedef struct { + + /** DM breakpoint 1 register extended byte (BK1RE at 0x7f90) */ + union { + + /// bytewise access to BK1RE + uint8_t byte; + + /// skip bitwise access to register BK1RE + + /// register _DM_BK1RE reset value + #define sfr_DM_BK1RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RE; + + + /** DM breakpoint 1 register high byte (BK1RH at 0x7f91) */ + union { + + /// bytewise access to BK1RH + uint8_t byte; + + /// skip bitwise access to register BK1RH + + /// register _DM_BK1RH reset value + #define sfr_DM_BK1RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RH; + + + /** DM breakpoint 1 register low byte (BK1RL at 0x7f92) */ + union { + + /// bytewise access to BK1RL + uint8_t byte; + + /// skip bitwise access to register BK1RL + + /// register _DM_BK1RL reset value + #define sfr_DM_BK1RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RL; + + + /** DM breakpoint 2 register extended byte (BK2RE at 0x7f93) */ + union { + + /// bytewise access to BK2RE + uint8_t byte; + + /// skip bitwise access to register BK2RE + + /// register _DM_BK2RE reset value + #define sfr_DM_BK2RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RE; + + + /** DM breakpoint 2 register high byte (BK2RH at 0x7f94) */ + union { + + /// bytewise access to BK2RH + uint8_t byte; + + /// skip bitwise access to register BK2RH + + /// register _DM_BK2RH reset value + #define sfr_DM_BK2RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RH; + + + /** DM breakpoint 2 register low byte (BK2RL at 0x7f95) */ + union { + + /// bytewise access to BK2RL + uint8_t byte; + + /// skip bitwise access to register BK2RL + + /// register _DM_BK2RL reset value + #define sfr_DM_BK2RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RL; + + + /** DM debug module control register 1 (CR1 at 0x7f96) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// skip bitwise access to register CR1 + + /// register _DM_CR1 reset value + #define sfr_DM_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** DM debug module control register 2 (CR2 at 0x7f97) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// skip bitwise access to register CR2 + + /// register _DM_CR2 reset value + #define sfr_DM_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** DM debug module control/status register 1 (CSR1 at 0x7f98) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// skip bitwise access to register CSR1 + + /// register _DM_CSR1 reset value + #define sfr_DM_CSR1_RESET_VALUE ((uint8_t) 0x10) + + } CSR1; + + + /** DM debug module control/status register 2 (CSR2 at 0x7f99) */ + union { + + /// bytewise access to CSR2 + uint8_t byte; + + /// skip bitwise access to register CSR2 + + /// register _DM_CSR2 reset value + #define sfr_DM_CSR2_RESET_VALUE ((uint8_t) 0x00) + + } CSR2; + + + /** DM enable function register (ENFCTR at 0x7f9a) */ + union { + + /// bytewise access to ENFCTR + uint8_t byte; + + /// skip bitwise access to register ENFCTR + + /// register _DM_ENFCTR reset value + #define sfr_DM_ENFCTR_RESET_VALUE ((uint8_t) 0xFF) + + } ENFCTR; + +} DM_t; + +/// access to DM SFR registers +#define sfr_DM (*((DM_t*) 0x7f90)) + + +//------------------------ +// Module FLASH +//------------------------ + +/** struct containing FLASH module registers */ +typedef struct { + + /** Flash control register 1 (CR1 at 0x505a) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS FIX : 1; // bit 0 + BITS IE : 1; // bit 1 + BITS AHALT : 1; // bit 2 + BITS HALT : 1; // bit 3 + BITS : 4; // 4 bits + }; // CR1 bitfield + + /// register _FLASH_CR1 reset value + #define sfr_FLASH_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Flash control register 2 (CR2 at 0x505b) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS FPRG : 1; // bit 4 + BITS ERASE : 1; // bit 5 + BITS WPRG : 1; // bit 6 + BITS OPT : 1; // bit 7 + }; // CR2 bitfield + + /// register _FLASH_CR2 reset value + #define sfr_FLASH_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** Flash complementary control register 2 (NCR2 at 0x505c) */ + union { + + /// bytewise access to NCR2 + uint8_t byte; + + /// bitwise access to register NCR2 + struct { + BITS NPRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS NFPRG : 1; // bit 4 + BITS NERASE : 1; // bit 5 + BITS NWPRG : 1; // bit 6 + BITS NOPT : 1; // bit 7 + }; // NCR2 bitfield + + /// register _FLASH_NCR2 reset value + #define sfr_FLASH_NCR2_RESET_VALUE ((uint8_t) 0xFF) + + } NCR2; + + + /** Flash protection register (FPR at 0x505d) */ + union { + + /// bytewise access to FPR + uint8_t byte; + + /// bitwise access to register FPR + struct { + BITS WPB0 : 1; // bit 0 + BITS WPB1 : 1; // bit 1 + BITS WPB2 : 1; // bit 2 + BITS WPB3 : 1; // bit 3 + BITS WPB4 : 1; // bit 4 + BITS WPB5 : 1; // bit 5 + BITS : 2; // 2 bits + }; // FPR bitfield + + /// register _FLASH_FPR reset value + #define sfr_FLASH_FPR_RESET_VALUE ((uint8_t) 0x00) + + } FPR; + + + /** Flash complementary protection register (NFPR at 0x505e) */ + union { + + /// bytewise access to NFPR + uint8_t byte; + + /// bitwise access to register NFPR + struct { + BITS NWPB0 : 1; // bit 0 + BITS NWPB1 : 1; // bit 1 + BITS NWPB2 : 1; // bit 2 + BITS NWPB3 : 1; // bit 3 + BITS NWPB4 : 1; // bit 4 + BITS NWPB5 : 1; // bit 5 + BITS : 2; // 2 bits + }; // NFPR bitfield + + /// register _FLASH_NFPR reset value + #define sfr_FLASH_NFPR_RESET_VALUE ((uint8_t) 0xFF) + + } NFPR; + + + /** Flash in-application programming status register (IAPSR at 0x505f) */ + union { + + /// bytewise access to IAPSR + uint8_t byte; + + /// bitwise access to register IAPSR + struct { + BITS WR_PG_DIS : 1; // bit 0 + BITS PUL : 1; // bit 1 + BITS EOP : 1; // bit 2 + BITS DUL : 1; // bit 3 + BITS : 2; // 2 bits + BITS HVOFF : 1; // bit 6 + BITS : 1; // 1 bit + }; // IAPSR bitfield + + /// register _FLASH_IAPSR reset value + #define sfr_FLASH_IAPSR_RESET_VALUE ((uint8_t) 0x00) + + } IAPSR; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** Flash program memory unprotection register (PUKR at 0x5062) */ + union { + + /// bytewise access to PUKR + uint8_t byte; + + /// bitwise access to register PUKR + struct { + BITS MASS_PRG : 8; // bits 0-7 + }; // PUKR bitfield + + /// register _FLASH_PUKR reset value + #define sfr_FLASH_PUKR_RESET_VALUE ((uint8_t) 0x00) + + } PUKR; + + + /// Reserved register (1B) + uint8_t Reserved_2[1]; + + + /** Data EEPROM unprotection register (DUKR at 0x5064) */ + union { + + /// bytewise access to DUKR + uint8_t byte; + + /// bitwise access to register DUKR + struct { + BITS MASS_DATA : 8; // bits 0-7 + }; // DUKR bitfield + + /// register _FLASH_DUKR reset value + #define sfr_FLASH_DUKR_RESET_VALUE ((uint8_t) 0x00) + + } DUKR; + +} FLASH_t; + +/// access to FLASH SFR registers +#define sfr_FLASH (*((FLASH_t*) 0x505a)) + + +//------------------------ +// Module I2C +//------------------------ + +/** struct containing I2C module registers */ +typedef struct { + + /** I2C control register 1 (CR1 at 0x5210) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PE : 1; // bit 0 + BITS : 5; // 5 bits + BITS ENGC : 1; // bit 6 + BITS NOSTRETCH : 1; // bit 7 + }; // CR1 bitfield + + /// register _I2C_CR1 reset value + #define sfr_I2C_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** I2C control register 2 (CR2 at 0x5211) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS START : 1; // bit 0 + BITS STOP : 1; // bit 1 + BITS ACK : 1; // bit 2 + BITS POS : 1; // bit 3 + BITS : 3; // 3 bits + BITS SWRST : 1; // bit 7 + }; // CR2 bitfield + + /// register _I2C_CR2 reset value + #define sfr_I2C_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** I2C frequency register (FREQR at 0x5212) */ + union { + + /// bytewise access to FREQR + uint8_t byte; + + /// bitwise access to register FREQR + struct { + BITS FREQ : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // FREQR bitfield + + /// register _I2C_FREQR reset value + #define sfr_I2C_FREQR_RESET_VALUE ((uint8_t) 0x00) + + } FREQR; + + + /** I2C Own address register low (OARL at 0x5213) */ + union { + + /// bytewise access to OARL + uint8_t byte; + + /// bitwise access to register OARL + struct { + BITS ADD0 : 1; // bit 0 + BITS ADD : 7; // bits 1-7 + }; // OARL bitfield + + /// register _I2C_OARL reset value + #define sfr_I2C_OARL_RESET_VALUE ((uint8_t) 0x00) + + } OARL; + + + /** I2C own address register high (OARH at 0x5214) */ + union { + + /// bytewise access to OARH + uint8_t byte; + + /// bitwise access to register OARH + struct { + BITS : 1; // 1 bit + BITS ADD : 2; // bits 1-2 + BITS : 3; // 3 bits + BITS ADDCONF : 1; // bit 6 + BITS ADDMODE : 1; // bit 7 + }; // OARH bitfield + + /// register _I2C_OARH reset value + #define sfr_I2C_OARH_RESET_VALUE ((uint8_t) 0x00) + + } OARH; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** I2C data register (DR at 0x5216) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _I2C_DR reset value + #define sfr_I2C_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** I2C status register 1 (SR1 at 0x5217) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS SB : 1; // bit 0 + BITS ADDR : 1; // bit 1 + BITS BTF : 1; // bit 2 + BITS ADD10 : 1; // bit 3 + BITS STOPF : 1; // bit 4 + BITS : 1; // 1 bit + BITS RXNE : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR1 bitfield + + /// register _I2C_SR1 reset value + #define sfr_I2C_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** I2C status register 2 (SR2 at 0x5218) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS BERR : 1; // bit 0 + BITS ARLO : 1; // bit 1 + BITS AF : 1; // bit 2 + BITS OVR : 1; // bit 3 + BITS : 1; // 1 bit + BITS WUFH : 1; // bit 5 + BITS : 2; // 2 bits + }; // SR2 bitfield + + /// register _I2C_SR2 reset value + #define sfr_I2C_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** I2C status register 3 (SR3 at 0x5219) */ + union { + + /// bytewise access to SR3 + uint8_t byte; + + /// bitwise access to register SR3 + struct { + BITS MSL : 1; // bit 0 + BITS BUSY : 1; // bit 1 + BITS TRA : 1; // bit 2 + BITS : 1; // 1 bit + BITS GENCALL : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR3 bitfield + + /// register _I2C_SR3 reset value + #define sfr_I2C_SR3_RESET_VALUE ((uint8_t) 0x00) + + } SR3; + + + /** I2C interrupt control register (ITR at 0x521a) */ + union { + + /// bytewise access to ITR + uint8_t byte; + + /// bitwise access to register ITR + struct { + BITS ITERREN : 1; // bit 0 + BITS ITEVTEN : 1; // bit 1 + BITS ITBUFEN : 1; // bit 2 + BITS : 5; // 5 bits + }; // ITR bitfield + + /// register _I2C_ITR reset value + #define sfr_I2C_ITR_RESET_VALUE ((uint8_t) 0x00) + + } ITR; + + + /** I2C clock control register low (CCRL at 0x521b) */ + union { + + /// bytewise access to CCRL + uint8_t byte; + + /// bitwise access to register CCRL + struct { + BITS CCR : 8; // bits 0-7 + }; // CCRL bitfield + + /// register _I2C_CCRL reset value + #define sfr_I2C_CCRL_RESET_VALUE ((uint8_t) 0x00) + + } CCRL; + + + /** I2C clock control register high (CCRH at 0x521c) */ + union { + + /// bytewise access to CCRH + uint8_t byte; + + /// bitwise access to register CCRH + struct { + BITS CCR : 4; // bits 0-3 + BITS : 2; // 2 bits + BITS DUTY : 1; // bit 6 + BITS F_S : 1; // bit 7 + }; // CCRH bitfield + + /// register _I2C_CCRH reset value + #define sfr_I2C_CCRH_RESET_VALUE ((uint8_t) 0x00) + + } CCRH; + + + /** I2C TRISE register (TRISER at 0x521d) */ + union { + + /// bytewise access to TRISER + uint8_t byte; + + /// bitwise access to register TRISER + struct { + BITS TRISE : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // TRISER bitfield + + /// register _I2C_TRISER reset value + #define sfr_I2C_TRISER_RESET_VALUE ((uint8_t) 0x02) + + } TRISER; + + + /** I2C packet error checking register (PECR at 0x521e) */ + union { + + /// bytewise access to PECR + uint8_t byte; + + /// bitwise access to register PECR + struct { + BITS PEC : 8; // bits 0-7 + }; // PECR bitfield + + /// register _I2C_PECR reset value + #define sfr_I2C_PECR_RESET_VALUE ((uint8_t) 0x00) + + } PECR; + +} I2C_t; + +/// access to I2C SFR registers +#define sfr_I2C (*((I2C_t*) 0x5210)) + + +//------------------------ +// Module ITC_EXTI +//------------------------ + +/** struct containing ITC_EXTI module registers */ +typedef struct { + + /** External interrupt control register 1 (CR1 at 0x50a0) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PAIS : 2; // bits 0-1 + BITS PBIS : 2; // bits 2-3 + BITS PCIS : 2; // bits 4-5 + BITS PDIS : 2; // bits 6-7 + }; // CR1 bitfield + + /// register _ITC_EXTI_CR1 reset value + #define sfr_ITC_EXTI_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** External interrupt control register 2 (CR2 at 0x50a1) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PEIS : 2; // bits 0-1 + BITS TLIS : 1; // bit 2 + BITS : 5; // 5 bits + }; // CR2 bitfield + + /// register _ITC_EXTI_CR2 reset value + #define sfr_ITC_EXTI_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + +} ITC_EXTI_t; + +/// access to ITC_EXTI SFR registers +#define sfr_ITC_EXTI (*((ITC_EXTI_t*) 0x50a0)) + + +//------------------------ +// Module ITC_SPR +//------------------------ + +/** struct containing ITC_SPR module registers */ +typedef struct { + + /** Interrupt software priority register 1 (SPR1 at 0x7f70) */ + union { + + /// bytewise access to SPR1 + uint8_t byte; + + /// bitwise access to register SPR1 + struct { + BITS VECT0SPR : 2; // bits 0-1 + BITS VECT1SPR : 2; // bits 2-3 + BITS VECT2SPR : 2; // bits 4-5 + BITS VECT3SPR : 2; // bits 6-7 + }; // SPR1 bitfield + + /// register _ITC_SPR_SPR1 reset value + #define sfr_ITC_SPR_SPR1_RESET_VALUE ((uint8_t) 0xFF) + + } SPR1; + + + /** Interrupt software priority register 2 (SPR2 at 0x7f71) */ + union { + + /// bytewise access to SPR2 + uint8_t byte; + + /// bitwise access to register SPR2 + struct { + BITS VECT4SPR : 2; // bits 0-1 + BITS VECT5SPR : 2; // bits 2-3 + BITS VECT6SPR : 2; // bits 4-5 + BITS VECT7SPR : 2; // bits 6-7 + }; // SPR2 bitfield + + /// register _ITC_SPR_SPR2 reset value + #define sfr_ITC_SPR_SPR2_RESET_VALUE ((uint8_t) 0xFF) + + } SPR2; + + + /** Interrupt software priority register 3 (SPR3 at 0x7f72) */ + union { + + /// bytewise access to SPR3 + uint8_t byte; + + /// bitwise access to register SPR3 + struct { + BITS VECT8SPR : 2; // bits 0-1 + BITS VECT9SPR : 2; // bits 2-3 + BITS VECT10SPR : 2; // bits 4-5 + BITS VECT11SPR : 2; // bits 6-7 + }; // SPR3 bitfield + + /// register _ITC_SPR_SPR3 reset value + #define sfr_ITC_SPR_SPR3_RESET_VALUE ((uint8_t) 0xFF) + + } SPR3; + + + /** Interrupt software priority register 4 (SPR4 at 0x7f73) */ + union { + + /// bytewise access to SPR4 + uint8_t byte; + + /// bitwise access to register SPR4 + struct { + BITS VECT12SPR : 2; // bits 0-1 + BITS VECT13SPR : 2; // bits 2-3 + BITS VECT14SPR : 2; // bits 4-5 + BITS VECT15SPR : 2; // bits 6-7 + }; // SPR4 bitfield + + /// register _ITC_SPR_SPR4 reset value + #define sfr_ITC_SPR_SPR4_RESET_VALUE ((uint8_t) 0xFF) + + } SPR4; + + + /** Interrupt software priority register 5 (SPR5 at 0x7f74) */ + union { + + /// bytewise access to SPR5 + uint8_t byte; + + /// bitwise access to register SPR5 + struct { + BITS VECT16SPR : 2; // bits 0-1 + BITS VECT17SPR : 2; // bits 2-3 + BITS VECT18SPR : 2; // bits 4-5 + BITS VECT19SPR : 2; // bits 6-7 + }; // SPR5 bitfield + + /// register _ITC_SPR_SPR5 reset value + #define sfr_ITC_SPR_SPR5_RESET_VALUE ((uint8_t) 0xFF) + + } SPR5; + + + /** Interrupt software priority register 6 (SPR6 at 0x7f75) */ + union { + + /// bytewise access to SPR6 + uint8_t byte; + + /// bitwise access to register SPR6 + struct { + BITS VECT20SPR : 2; // bits 0-1 + BITS VECT21SPR : 2; // bits 2-3 + BITS VECT22SPR : 2; // bits 4-5 + BITS VECT23SPR : 2; // bits 6-7 + }; // SPR6 bitfield + + /// register _ITC_SPR_SPR6 reset value + #define sfr_ITC_SPR_SPR6_RESET_VALUE ((uint8_t) 0xFF) + + } SPR6; + + + /** Interrupt software priority register 7 (SPR7 at 0x7f76) */ + union { + + /// bytewise access to SPR7 + uint8_t byte; + + /// bitwise access to register SPR7 + struct { + BITS VECT24SPR : 2; // bits 0-1 + BITS VECT25SPR : 2; // bits 2-3 + BITS VECT26SPR : 2; // bits 4-5 + BITS VECT27SPR : 2; // bits 6-7 + }; // SPR7 bitfield + + /// register _ITC_SPR_SPR7 reset value + #define sfr_ITC_SPR_SPR7_RESET_VALUE ((uint8_t) 0xFF) + + } SPR7; + + + /** Interrupt software priority register 8 (SPR8 at 0x7f77) */ + union { + + /// bytewise access to SPR8 + uint8_t byte; + + /// bitwise access to register SPR8 + struct { + BITS VECT28SPR : 2; // bits 0-1 + BITS VECT29SPR : 2; // bits 2-3 + BITS : 4; // 4 bits + }; // SPR8 bitfield + + /// register _ITC_SPR_SPR8 reset value + #define sfr_ITC_SPR_SPR8_RESET_VALUE ((uint8_t) 0xFF) + + } SPR8; + +} ITC_SPR_t; + +/// access to ITC_SPR SFR registers +#define sfr_ITC_SPR (*((ITC_SPR_t*) 0x7f70)) + + +//------------------------ +// Module IWDG +//------------------------ + +/** struct containing IWDG module registers */ +typedef struct { + + /** IWDG key register (KR at 0x50e0) */ + union { + + /// bytewise access to KR + uint8_t byte; + + /// bitwise access to register KR + struct { + BITS KEY : 8; // bits 0-7 + }; // KR bitfield + + /// register _IWDG_KR reset value + #define sfr_IWDG_KR_RESET_VALUE ((uint8_t) 0x00) + + } KR; + + + /** IWDG prescaler register (PR at 0x50e1) */ + union { + + /// bytewise access to PR + uint8_t byte; + + /// bitwise access to register PR + struct { + BITS PR : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PR bitfield + + /// register _IWDG_PR reset value + #define sfr_IWDG_PR_RESET_VALUE ((uint8_t) 0x00) + + } PR; + + + /** IWDG reload register (RLR at 0x50e2) */ + union { + + /// bytewise access to RLR + uint8_t byte; + + /// bitwise access to register RLR + struct { + BITS RL : 8; // bits 0-7 + }; // RLR bitfield + + /// register _IWDG_RLR reset value + #define sfr_IWDG_RLR_RESET_VALUE ((uint8_t) 0xFF) + + } RLR; + +} IWDG_t; + +/// access to IWDG SFR registers +#define sfr_IWDG (*((IWDG_t*) 0x50e0)) + + +//------------------------ +// Module OPT +//------------------------ + +/** struct containing OPT module registers */ +typedef struct { + + /** Read-out protection (ROP) (OPT0 at 0x4800) */ + union { + + /// bytewise access to OPT0 + uint8_t byte; + + /// skip bitwise access to register OPT0 + + /// register _OPT_OPT0 reset value + #define sfr_OPT_OPT0_RESET_VALUE ((uint8_t) 0x00) + + } OPT0; + + + /** User boot code (UBC) (OPT1 at 0x4801) */ + union { + + /// bytewise access to OPT1 + uint8_t byte; + + /// skip bitwise access to register OPT1 + + /// register _OPT_OPT1 reset value + #define sfr_OPT_OPT1_RESET_VALUE ((uint8_t) 0x00) + + } OPT1; + + + /** User boot code (UBC) (complementary byte) (NOPT1 at 0x4802) */ + union { + + /// bytewise access to NOPT1 + uint8_t byte; + + /// skip bitwise access to register NOPT1 + + /// register _OPT_NOPT1 reset value + #define sfr_OPT_NOPT1_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT1; + + + /** Alternate function remapping (AFR) (OPT2 at 0x4803) */ + union { + + /// bytewise access to OPT2 + uint8_t byte; + + /// skip bitwise access to register OPT2 + + /// register _OPT_OPT2 reset value + #define sfr_OPT_OPT2_RESET_VALUE ((uint8_t) 0x00) + + } OPT2; + + + /** Alternate function remapping (AFR) (complementary byte) (NOPT2 at 0x4804) */ + union { + + /// bytewise access to NOPT2 + uint8_t byte; + + /// skip bitwise access to register NOPT2 + + /// register _OPT_NOPT2 reset value + #define sfr_OPT_NOPT2_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT2; + + + /** Misc. option (OPT3 at 0x4805) */ + union { + + /// bytewise access to OPT3 + uint8_t byte; + + /// skip bitwise access to register OPT3 + + /// register _OPT_OPT3 reset value + #define sfr_OPT_OPT3_RESET_VALUE ((uint8_t) 0x00) + + } OPT3; + + + /** Misc. option (complementary byte) (NOPT3 at 0x4806) */ + union { + + /// bytewise access to NOPT3 + uint8_t byte; + + /// skip bitwise access to register NOPT3 + + /// register _OPT_NOPT3 reset value + #define sfr_OPT_NOPT3_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT3; + + + /** Clock option (OPT4 at 0x4807) */ + union { + + /// bytewise access to OPT4 + uint8_t byte; + + /// skip bitwise access to register OPT4 + + /// register _OPT_OPT4 reset value + #define sfr_OPT_OPT4_RESET_VALUE ((uint8_t) 0x00) + + } OPT4; + + + /** Clock option (complementary byte) (NOPT4 at 0x4808) */ + union { + + /// bytewise access to NOPT4 + uint8_t byte; + + /// skip bitwise access to register NOPT4 + + /// register _OPT_NOPT4 reset value + #define sfr_OPT_NOPT4_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT4; + + + /** HSE clock startup (OPT5 at 0x4809) */ + union { + + /// bytewise access to OPT5 + uint8_t byte; + + /// skip bitwise access to register OPT5 + + /// register _OPT_OPT5 reset value + #define sfr_OPT_OPT5_RESET_VALUE ((uint8_t) 0x00) + + } OPT5; + + + /** HSE clock startup (complementary byte) (NOPT5 at 0x480a) */ + union { + + /// bytewise access to NOPT5 + uint8_t byte; + + /// skip bitwise access to register NOPT5 + + /// register _OPT_NOPT5 reset value + #define sfr_OPT_NOPT5_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT5; + + + /// Reserved register (115B) + uint8_t Reserved_1[115]; + + + /** Bootloader (OPTBL at 0x487e) */ + union { + + /// bytewise access to OPTBL + uint8_t byte; + + /// skip bitwise access to register OPTBL + + /// register _OPT_OPTBL reset value + #define sfr_OPT_OPTBL_RESET_VALUE ((uint8_t) 0x00) + + } OPTBL; + + + /** Bootloader (complementary byte) (NOPTBL at 0x487f) */ + union { + + /// bytewise access to NOPTBL + uint8_t byte; + + /// skip bitwise access to register NOPTBL + + /// register _OPT_NOPTBL reset value + #define sfr_OPT_NOPTBL_RESET_VALUE ((uint8_t) 0xFF) + + } NOPTBL; + +} OPT_t; + +/// access to OPT SFR registers +#define sfr_OPT (*((OPT_t*) 0x4800)) + + +//------------------------ +// Module PORT +//------------------------ + +/** struct containing PORTA module registers */ +typedef struct { + + /** Port A data output latch register (ODR at 0x5000) */ + union { + + /// bytewise access to ODR + uint8_t byte; + + /// bitwise access to register ODR + struct { + BITS ODR0 : 1; // bit 0 + BITS ODR1 : 1; // bit 1 + BITS ODR2 : 1; // bit 2 + BITS ODR3 : 1; // bit 3 + BITS ODR4 : 1; // bit 4 + BITS ODR5 : 1; // bit 5 + BITS ODR6 : 1; // bit 6 + BITS ODR7 : 1; // bit 7 + }; // ODR bitfield + + /// register _PORT_ODR reset value + #define sfr_PORT_ODR_RESET_VALUE ((uint8_t) 0x00) + + } ODR; + + + /** Port A input pin value register (IDR at 0x5001) */ + union { + + /// bytewise access to IDR + uint8_t byte; + + /// bitwise access to register IDR + struct { + BITS IDR0 : 1; // bit 0 + BITS IDR1 : 1; // bit 1 + BITS IDR2 : 1; // bit 2 + BITS IDR3 : 1; // bit 3 + BITS IDR4 : 1; // bit 4 + BITS IDR5 : 1; // bit 5 + BITS IDR6 : 1; // bit 6 + BITS IDR7 : 1; // bit 7 + }; // IDR bitfield + + /// register _PORT_IDR reset value + #define sfr_PORT_IDR_RESET_VALUE ((uint8_t) 0x00) + + } IDR; + + + /** Port A data direction register (DDR at 0x5002) */ + union { + + /// bytewise access to DDR + uint8_t byte; + + /// bitwise access to register DDR + struct { + BITS DDR0 : 1; // bit 0 + BITS DDR1 : 1; // bit 1 + BITS DDR2 : 1; // bit 2 + BITS DDR3 : 1; // bit 3 + BITS DDR4 : 1; // bit 4 + BITS DDR5 : 1; // bit 5 + BITS DDR6 : 1; // bit 6 + BITS DDR7 : 1; // bit 7 + }; // DDR bitfield + + /// register _PORT_DDR reset value + #define sfr_PORT_DDR_RESET_VALUE ((uint8_t) 0x00) + + } DDR; + + + /** Port A control register 1 (CR1 at 0x5003) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS C10 : 1; // bit 0 + BITS C11 : 1; // bit 1 + BITS C12 : 1; // bit 2 + BITS C13 : 1; // bit 3 + BITS C14 : 1; // bit 4 + BITS C15 : 1; // bit 5 + BITS C16 : 1; // bit 6 + BITS C17 : 1; // bit 7 + }; // CR1 bitfield + + /// register _PORT_CR1 reset value + #define sfr_PORT_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Port A control register 2 (CR2 at 0x5004) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS C20 : 1; // bit 0 + BITS C21 : 1; // bit 1 + BITS C22 : 1; // bit 2 + BITS C23 : 1; // bit 3 + BITS C24 : 1; // bit 4 + BITS C25 : 1; // bit 5 + BITS C26 : 1; // bit 6 + BITS C27 : 1; // bit 7 + }; // CR2 bitfield + + /// register _PORT_CR2 reset value + #define sfr_PORT_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + +} PORT_t; + +/// access to PORTA SFR registers +#define sfr_PORTA (*((PORT_t*) 0x5000)) + + +/// access to PORTB SFR registers +#define sfr_PORTB (*((PORT_t*) 0x5005)) + + +/// access to PORTC SFR registers +#define sfr_PORTC (*((PORT_t*) 0x500a)) + + +/// access to PORTD SFR registers +#define sfr_PORTD (*((PORT_t*) 0x500f)) + + +/// access to PORTE SFR registers +#define sfr_PORTE (*((PORT_t*) 0x5014)) + + +/// access to PORTF SFR registers +#define sfr_PORTF (*((PORT_t*) 0x5019)) + + +/// access to PORTG SFR registers +#define sfr_PORTG (*((PORT_t*) 0x501e)) + + +/// access to PORTH SFR registers +#define sfr_PORTH (*((PORT_t*) 0x5023)) + + +/// access to PORTI SFR registers +#define sfr_PORTI (*((PORT_t*) 0x5028)) + + +//------------------------ +// Module RST +//------------------------ + +/** struct containing RST module registers */ +typedef struct { + + /** Reset status register (SR at 0x50b3) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS WWDGF : 1; // bit 0 + BITS IWDGF : 1; // bit 1 + BITS ILLOPF : 1; // bit 2 + BITS SWIMF : 1; // bit 3 + BITS EMCF : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR bitfield + + /// register _RST_SR reset value + #define sfr_RST_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + +} RST_t; + +/// access to RST SFR registers +#define sfr_RST (*((RST_t*) 0x50b3)) + + +//------------------------ +// Module SPI +//------------------------ + +/** struct containing SPI module registers */ +typedef struct { + + /** SPI control register 1 (CR1 at 0x5200) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CPHA : 1; // bit 0 + BITS CPOL : 1; // bit 1 + BITS MSTR : 1; // bit 2 + BITS BR : 3; // bits 3-5 + BITS SPE : 1; // bit 6 + BITS LSBFIRST : 1; // bit 7 + }; // CR1 bitfield + + /// register _SPI_CR1 reset value + #define sfr_SPI_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** SPI control register 2 (CR2 at 0x5201) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SSI : 1; // bit 0 + BITS SSM : 1; // bit 1 + BITS RXONLY : 1; // bit 2 + BITS : 1; // 1 bit + BITS CRCNEXT : 1; // bit 4 + BITS CECEN : 1; // bit 5 + BITS BDOE : 1; // bit 6 + BITS BDM : 1; // bit 7 + }; // CR2 bitfield + + /// register _SPI_CR2 reset value + #define sfr_SPI_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** SPI interrupt control register (ICR at 0x5202) */ + union { + + /// bytewise access to ICR + uint8_t byte; + + /// bitwise access to register ICR + struct { + BITS : 4; // 4 bits + BITS WKIE : 1; // bit 4 + BITS ERRIE : 1; // bit 5 + BITS RXIE : 1; // bit 6 + BITS TXIE : 1; // bit 7 + }; // ICR bitfield + + /// register _SPI_ICR reset value + #define sfr_SPI_ICR_RESET_VALUE ((uint8_t) 0x00) + + } ICR; + + + /** SPI status register (SR at 0x5203) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS RXNE : 1; // bit 0 + BITS TXE : 1; // bit 1 + BITS : 1; // 1 bit + BITS WKUP : 1; // bit 3 + BITS CRCERR : 1; // bit 4 + BITS MODF : 1; // bit 5 + BITS OVR : 1; // bit 6 + BITS BSY : 1; // bit 7 + }; // SR bitfield + + /// register _SPI_SR reset value + #define sfr_SPI_SR_RESET_VALUE ((uint8_t) 0x02) + + } SR; + + + /** SPI data register (DR at 0x5204) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _SPI_DR reset value + #define sfr_SPI_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** SPI CRC polynomial register (CRCPR at 0x5205) */ + union { + + /// bytewise access to CRCPR + uint8_t byte; + + /// bitwise access to register CRCPR + struct { + BITS CRCPOLY : 8; // bits 0-7 + }; // CRCPR bitfield + + /// register _SPI_CRCPR reset value + #define sfr_SPI_CRCPR_RESET_VALUE ((uint8_t) 0x07) + + } CRCPR; + + + /** SPI Rx CRC register (RXCRCR at 0x5206) */ + union { + + /// bytewise access to RXCRCR + uint8_t byte; + + /// bitwise access to register RXCRCR + struct { + BITS RXCRC : 8; // bits 0-7 + }; // RXCRCR bitfield + + /// register _SPI_RXCRCR reset value + #define sfr_SPI_RXCRCR_RESET_VALUE ((uint8_t) 0xFF) + + } RXCRCR; + + + /** SPI Tx CRC register (TXCRCR at 0x5207) */ + union { + + /// bytewise access to TXCRCR + uint8_t byte; + + /// bitwise access to register TXCRCR + struct { + BITS TXCRC : 8; // bits 0-7 + }; // TXCRCR bitfield + + /// register _SPI_TXCRCR reset value + #define sfr_SPI_TXCRCR_RESET_VALUE ((uint8_t) 0xFF) + + } TXCRCR; + +} SPI_t; + +/// access to SPI SFR registers +#define sfr_SPI (*((SPI_t*) 0x5200)) + + +//------------------------ +// Module SWIM +//------------------------ + +/** struct containing SWIM module registers */ +typedef struct { + + /** SWIM control status register (CSR at 0x7f80) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// skip bitwise access to register CSR + + /// register _SWIM_CSR reset value + #define sfr_SWIM_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + +} SWIM_t; + +/// access to SWIM SFR registers +#define sfr_SWIM (*((SWIM_t*) 0x7f80)) + + +//------------------------ +// Module TIM1 +//------------------------ + +/** struct containing TIM1 module registers */ +typedef struct { + + /** TIM1 control register 1 (CR1 at 0x5250) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS DIR : 1; // bit 4 + BITS CMS : 2; // bits 5-6 + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM1_CR1 reset value + #define sfr_TIM1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM1 control register 2 (CR2 at 0x5251) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS CCPG : 1; // bit 0 + BITS : 1; // 1 bit + BITS COMS : 1; // bit 2 + BITS : 1; // 1 bit + BITS MMS : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _TIM1_CR2 reset value + #define sfr_TIM1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** TIM1 slave mode control register (SMCR at 0x5252) */ + union { + + /// bytewise access to SMCR + uint8_t byte; + + /// bitwise access to register SMCR + struct { + BITS SMS : 3; // bits 0-2 + BITS : 1; // 1 bit + BITS TS : 3; // bits 4-6 + BITS MSM : 1; // bit 7 + }; // SMCR bitfield + + /// register _TIM1_SMCR reset value + #define sfr_TIM1_SMCR_RESET_VALUE ((uint8_t) 0x00) + + } SMCR; + + + /** TIM1 external trigger register (ETR at 0x5253) */ + union { + + /// bytewise access to ETR + uint8_t byte; + + /// bitwise access to register ETR + struct { + BITS ETF : 4; // bits 0-3 + BITS ETPS : 2; // bits 4-5 + BITS ECE : 1; // bit 6 + BITS ETP : 1; // bit 7 + }; // ETR bitfield + + /// register _TIM1_ETR reset value + #define sfr_TIM1_ETR_RESET_VALUE ((uint8_t) 0x00) + + } ETR; + + + /** TIM1 interrupt enable register (IER at 0x5254) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS CC4IE : 1; // bit 4 + BITS COMIE : 1; // bit 5 + BITS TIE : 1; // bit 6 + BITS BIE : 1; // bit 7 + }; // IER bitfield + + /// register _TIM1_IER reset value + #define sfr_TIM1_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM1 status register 1 (SR1 at 0x5255) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS CC4IF : 1; // bit 4 + BITS COMIF : 1; // bit 5 + BITS TIF : 1; // bit 6 + BITS BIF : 1; // bit 7 + }; // SR1 bitfield + + /// register _TIM1_SR1 reset value + #define sfr_TIM1_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM1 status register 2 (SR2 at 0x5256) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS CC4OF : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR2 bitfield + + /// register _TIM1_SR2 reset value + #define sfr_TIM1_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM1 event generation register (EGR at 0x5257) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS CC4G : 1; // bit 4 + BITS COMG : 1; // bit 5 + BITS TG : 1; // bit 6 + BITS BG : 1; // bit 7 + }; // EGR bitfield + + /// register _TIM1_EGR reset value + #define sfr_TIM1_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM1 capture/compare mode register 1 (CCMR1 at 0x5258) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS OC1FE : 1; // bit 2 + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS OC1CE : 1; // bit 7 + }; // CCMR1 bitfield + + /// register _TIM1_CCMR1 reset value + #define sfr_TIM1_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM1 capture/compare mode register 2 (CCMR2 at 0x5259) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS OC2FE : 1; // bit 2 + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS OC2CE : 1; // bit 7 + }; // CCMR2 bitfield + + /// register _TIM1_CCMR2 reset value + #define sfr_TIM1_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM1 capture/compare mode register 3 (CCMR3 at 0x525a) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS OC3FE : 1; // bit 2 + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS OC3CE : 1; // bit 7 + }; // CCMR3 bitfield + + /// register _TIM1_CCMR3 reset value + #define sfr_TIM1_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM1 capture/compare mode register 4 (CCMR4 at 0x525b) */ + union { + + /// bytewise access to CCMR4 + uint8_t byte; + + /// bitwise access to register CCMR4 + struct { + BITS CC4S : 2; // bits 0-1 + BITS OC4FE : 1; // bit 2 + BITS OC4PE : 1; // bit 3 + BITS OC4M : 3; // bits 4-6 + BITS OC4CE : 1; // bit 7 + }; // CCMR4 bitfield + + /// register _TIM1_CCMR4 reset value + #define sfr_TIM1_CCMR4_RESET_VALUE ((uint8_t) 0x00) + + } CCMR4; + + + /** TIM1 capture/compare enable register 1 (CCER1 at 0x525c) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS CC1NE : 1; // bit 2 + BITS CC1NP : 1; // bit 3 + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS CC2NE : 1; // bit 6 + BITS CC2NP : 1; // bit 7 + }; // CCER1 bitfield + + /// register _TIM1_CCER1 reset value + #define sfr_TIM1_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM1 capture/compare enable register 2 (CCER2 at 0x525d) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS CC3NE : 1; // bit 2 + BITS CC3NP : 1; // bit 3 + BITS CC4E : 1; // bit 4 + BITS CC4P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER2 bitfield + + /// register _TIM1_CCER2 reset value + #define sfr_TIM1_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM1 counter high (CNTRH at 0x525e) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM1_CNTRH reset value + #define sfr_TIM1_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM1 counter low (CNTRL at 0x525f) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM1_CNTRL reset value + #define sfr_TIM1_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM1 prescaler register high (PSCRH at 0x5260) */ + union { + + /// bytewise access to PSCRH + uint8_t byte; + + /// bitwise access to register PSCRH + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCRH bitfield + + /// register _TIM1_PSCRH reset value + #define sfr_TIM1_PSCRH_RESET_VALUE ((uint8_t) 0x00) + + } PSCRH; + + + /** TIM1 prescaler register low (PSCRL at 0x5261) */ + union { + + /// bytewise access to PSCRL + uint8_t byte; + + /// bitwise access to register PSCRL + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCRL bitfield + + /// register _TIM1_PSCRL reset value + #define sfr_TIM1_PSCRL_RESET_VALUE ((uint8_t) 0x00) + + } PSCRL; + + + /** TIM1 auto-reload register high (ARRH at 0x5262) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM1_ARRH reset value + #define sfr_TIM1_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM1 auto-reload register low (ARRL at 0x5263) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM1_ARRL reset value + #define sfr_TIM1_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM1 repetition counter register (RCR at 0x5264) */ + union { + + /// bytewise access to RCR + uint8_t byte; + + /// bitwise access to register RCR + struct { + BITS REP : 8; // bits 0-7 + }; // RCR bitfield + + /// register _TIM1_RCR reset value + #define sfr_TIM1_RCR_RESET_VALUE ((uint8_t) 0x00) + + } RCR; + + + /** TIM1 capture/compare register 1 high (CCR1H at 0x5265) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM1_CCR1H reset value + #define sfr_TIM1_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM1 capture/compare register 1 low (CCR1L at 0x5266) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM1_CCR1L reset value + #define sfr_TIM1_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM1 capture/compare register 2 high (CCR2H at 0x5267) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM1_CCR2H reset value + #define sfr_TIM1_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM1 capture/compare register 2 low (CCR2L at 0x5268) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM1_CCR2L reset value + #define sfr_TIM1_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM1 capture/compare register 3 high (CCR3H at 0x5269) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3H bitfield + + /// register _TIM1_CCR3H reset value + #define sfr_TIM1_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM1 capture/compare register 3 low (CCR3L at 0x526a) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3L bitfield + + /// register _TIM1_CCR3L reset value + #define sfr_TIM1_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + + + /** TIM1 capture/compare register 4 high (CCR4H at 0x526b) */ + union { + + /// bytewise access to CCR4H + uint8_t byte; + + /// bitwise access to register CCR4H + struct { + BITS CCR4 : 8; // bits 0-7 + }; // CCR4H bitfield + + /// register _TIM1_CCR4H reset value + #define sfr_TIM1_CCR4H_RESET_VALUE ((uint8_t) 0x00) + + } CCR4H; + + + /** TIM1 capture/compare register 4 low (CCR4L at 0x526c) */ + union { + + /// bytewise access to CCR4L + uint8_t byte; + + /// bitwise access to register CCR4L + struct { + BITS CCR4 : 8; // bits 0-7 + }; // CCR4L bitfield + + /// register _TIM1_CCR4L reset value + #define sfr_TIM1_CCR4L_RESET_VALUE ((uint8_t) 0x00) + + } CCR4L; + + + /** TIM1 break register (BKR at 0x526d) */ + union { + + /// bytewise access to BKR + uint8_t byte; + + /// bitwise access to register BKR + struct { + BITS LOCK : 2; // bits 0-1 + BITS OSSI : 1; // bit 2 + BITS OSSR : 1; // bit 3 + BITS BKE : 1; // bit 4 + BITS BKP : 1; // bit 5 + BITS AOE : 1; // bit 6 + BITS MOE : 1; // bit 7 + }; // BKR bitfield + + /// register _TIM1_BKR reset value + #define sfr_TIM1_BKR_RESET_VALUE ((uint8_t) 0x00) + + } BKR; + + + /** TIM1 dead-time register (DTR at 0x526e) */ + union { + + /// bytewise access to DTR + uint8_t byte; + + /// bitwise access to register DTR + struct { + BITS DTG : 8; // bits 0-7 + }; // DTR bitfield + + /// register _TIM1_DTR reset value + #define sfr_TIM1_DTR_RESET_VALUE ((uint8_t) 0x00) + + } DTR; + + + /** TIM1 output idle state register (OISR at 0x526f) */ + union { + + /// bytewise access to OISR + uint8_t byte; + + /// bitwise access to register OISR + struct { + BITS OIS1 : 1; // bit 0 + BITS OIS1N : 1; // bit 1 + BITS OIS2 : 1; // bit 2 + BITS OIS2N : 1; // bit 3 + BITS OIS3 : 1; // bit 4 + BITS OIS3N : 1; // bit 5 + BITS OIS4 : 1; // bit 6 + BITS : 1; // 1 bit + }; // OISR bitfield + + /// register _TIM1_OISR reset value + #define sfr_TIM1_OISR_RESET_VALUE ((uint8_t) 0x00) + + } OISR; + +} TIM1_t; + +/// access to TIM1 SFR registers +#define sfr_TIM1 (*((TIM1_t*) 0x5250)) + + +//------------------------ +// Module TIM2 +//------------------------ + +/** struct containing TIM2 module registers */ +typedef struct { + + /** TIM2 control register 1 (CR1 at 0x5300) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM2_CR1 reset value + #define sfr_TIM2_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM2 interrupt enable register (IER at 0x5301) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM2_IER reset value + #define sfr_TIM2_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM2 status register 1 (SR1 at 0x5302) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR1 bitfield + + /// register _TIM2_SR1 reset value + #define sfr_TIM2_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM2 status register 2 (SR2 at 0x5303) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SR2 bitfield + + /// register _TIM2_SR2 reset value + #define sfr_TIM2_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM2 event generation register (EGR at 0x5304) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS : 2; // 2 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM2_EGR reset value + #define sfr_TIM2_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM2 capture/compare mode register 1 (CCMR1 at 0x5305) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM2_CCMR1 reset value + #define sfr_TIM2_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM2 capture/compare mode register 2 (CCMR2 at 0x5306) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM2_CCMR2 reset value + #define sfr_TIM2_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM2 capture/compare mode register 3 (CCMR3 at 0x5307) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR3 bitfield + + /// register _TIM2_CCMR3 reset value + #define sfr_TIM2_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM2 capture/compare enable register 1 (CCER1 at 0x5308) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM2_CCER1 reset value + #define sfr_TIM2_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM2 capture/compare enable register 2 (CCER2 at 0x5309) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS : 6; // 6 bits + }; // CCER2 bitfield + + /// register _TIM2_CCER2 reset value + #define sfr_TIM2_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM2 counter high (CNTRH at 0x530a) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM2_CNTRH reset value + #define sfr_TIM2_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM2 counter low (CNTRL at 0x530b) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM2_CNTRL reset value + #define sfr_TIM2_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM2 prescaler register (PSCR at 0x530c) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // PSCR bitfield + + /// register _TIM2_PSCR reset value + #define sfr_TIM2_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM2 auto-reload register high (ARRH at 0x530d) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM2_ARRH reset value + #define sfr_TIM2_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM2 auto-reload register low (ARRL at 0x530e) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM2_ARRL reset value + #define sfr_TIM2_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM2 capture/compare register 1 high (CCR1H at 0x530f) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM2_CCR1H reset value + #define sfr_TIM2_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM2 capture/compare register 1 low (CCR1L at 0x5310) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM2_CCR1L reset value + #define sfr_TIM2_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM2 capture/compare reg (CCR2H at 0x5311) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM2_CCR2H reset value + #define sfr_TIM2_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM2 capture/compare register 2 low (CCR2L at 0x5312) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM2_CCR2L reset value + #define sfr_TIM2_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM2 capture/compare register 3 high (CCR3H at 0x5313) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3H bitfield + + /// register _TIM2_CCR3H reset value + #define sfr_TIM2_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM2 capture/compare register 3 low (CCR3L at 0x5314) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3L bitfield + + /// register _TIM2_CCR3L reset value + #define sfr_TIM2_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + +} TIM2_t; + +/// access to TIM2 SFR registers +#define sfr_TIM2 (*((TIM2_t*) 0x5300)) + + +//------------------------ +// Module TIM3 +//------------------------ + +/** struct containing TIM3 module registers */ +typedef struct { + + /** TIM3 control register 1 (CR1 at 0x5320) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM3_CR1 reset value + #define sfr_TIM3_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM3 interrupt enable register (IER at 0x5321) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM3_IER reset value + #define sfr_TIM3_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM3 status register 1 (SR1 at 0x5322) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR1 bitfield + + /// register _TIM3_SR1 reset value + #define sfr_TIM3_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM3 status register 2 (SR2 at 0x5323) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SR2 bitfield + + /// register _TIM3_SR2 reset value + #define sfr_TIM3_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM3 event generation register (EGR at 0x5324) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS : 2; // 2 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM3_EGR reset value + #define sfr_TIM3_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM3 capture/compare mode register 1 (CCMR1 at 0x5325) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM3_CCMR1 reset value + #define sfr_TIM3_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM3 capture/compare mode register 2 (CCMR2 at 0x5326) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM3_CCMR2 reset value + #define sfr_TIM3_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM3 capture/compare enable register 1 (CCER1 at 0x5327) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM3_CCER1 reset value + #define sfr_TIM3_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM3 counter high (CNTRH at 0x5328) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM3_CNTRH reset value + #define sfr_TIM3_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM3 counter low (CNTRL at 0x5329) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM3_CNTRL reset value + #define sfr_TIM3_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM3 prescaler register (PSCR at 0x532a) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // PSCR bitfield + + /// register _TIM3_PSCR reset value + #define sfr_TIM3_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM3 auto-reload register high (ARRH at 0x532b) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM3_ARRH reset value + #define sfr_TIM3_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM3 auto-reload register low (ARRL at 0x532c) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM3_ARRL reset value + #define sfr_TIM3_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM3 capture/compare register 1 high (CCR1H at 0x532d) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM3_CCR1H reset value + #define sfr_TIM3_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM3 capture/compare register 1 low (CCR1L at 0x532e) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM3_CCR1L reset value + #define sfr_TIM3_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM3 capture/compare register 2 high (CCR2H at 0x532f) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM3_CCR2H reset value + #define sfr_TIM3_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM3 capture/compare register 2 low (CCR2L at 0x5330) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM3_CCR2L reset value + #define sfr_TIM3_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + +} TIM3_t; + +/// access to TIM3 SFR registers +#define sfr_TIM3 (*((TIM3_t*) 0x5320)) + + +//------------------------ +// Module TIM4 +//------------------------ + +/** struct containing TIM4 module registers */ +typedef struct { + + /** TIM4 control register 1 (CR1 at 0x5340) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM4_CR1 reset value + #define sfr_TIM4_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM4 interrupt enable register (IER at 0x5341) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM4_IER reset value + #define sfr_TIM4_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM4 status register (SR at 0x5342) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS UIF : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR bitfield + + /// register _TIM4_SR reset value + #define sfr_TIM4_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + + + /** TIM4 event generation register (EGR at 0x5343) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS : 5; // 5 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM4_EGR reset value + #define sfr_TIM4_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM4 counter (CNTR at 0x5344) */ + union { + + /// bytewise access to CNTR + uint8_t byte; + + /// bitwise access to register CNTR + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTR bitfield + + /// register _TIM4_CNTR reset value + #define sfr_TIM4_CNTR_RESET_VALUE ((uint8_t) 0x00) + + } CNTR; + + + /** TIM4 prescaler register (PSCR at 0x5345) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PSCR bitfield + + /// register _TIM4_PSCR reset value + #define sfr_TIM4_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM4 auto-reload register (ARR at 0x5346) */ + union { + + /// bytewise access to ARR + uint8_t byte; + + /// bitwise access to register ARR + struct { + BITS ARR : 8; // bits 0-7 + }; // ARR bitfield + + /// register _TIM4_ARR reset value + #define sfr_TIM4_ARR_RESET_VALUE ((uint8_t) 0xFF) + + } ARR; + +} TIM4_t; + +/// access to TIM4 SFR registers +#define sfr_TIM4 (*((TIM4_t*) 0x5340)) + + +//------------------------ +// Module UART2 +//------------------------ + +/** struct containing UART2 module registers */ +typedef struct { + + /** UART2 status register (SR at 0x5240) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS PE : 1; // bit 0 + BITS FE : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS OR_LHE : 1; // bit 3 + BITS IDLE : 1; // bit 4 + BITS RXNE : 1; // bit 5 + BITS TC : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR bitfield + + /// register _UART2_SR reset value + #define sfr_UART2_SR_RESET_VALUE ((uint8_t) 0xC0) + + } SR; + + + /** UART2 data register (DR at 0x5241) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _UART2_DR reset value + #define sfr_UART2_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** UART2 baud rate register 1 (BRR1 at 0x5242) */ + union { + + /// bytewise access to BRR1 + uint8_t byte; + + /// bitwise access to register BRR1 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR1 bitfield + + /// register _UART2_BRR1 reset value + #define sfr_UART2_BRR1_RESET_VALUE ((uint8_t) 0x00) + + } BRR1; + + + /** UART2 baud rate register 2 (BRR2 at 0x5243) */ + union { + + /// bytewise access to BRR2 + uint8_t byte; + + /// bitwise access to register BRR2 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR2 bitfield + + /// register _UART2_BRR2 reset value + #define sfr_UART2_BRR2_RESET_VALUE ((uint8_t) 0x00) + + } BRR2; + + + /** UART2 control register 1 (CR1 at 0x5244) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PIEN : 1; // bit 0 + BITS PS : 1; // bit 1 + BITS PCEN : 1; // bit 2 + BITS WAKE : 1; // bit 3 + BITS M : 1; // bit 4 + BITS UART0 : 1; // bit 5 + BITS T8 : 1; // bit 6 + BITS R8 : 1; // bit 7 + }; // CR1 bitfield + + /// register _UART2_CR1 reset value + #define sfr_UART2_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** UART2 control register 2 (CR2 at 0x5245) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SBK : 1; // bit 0 + BITS RWU : 1; // bit 1 + BITS REN : 1; // bit 2 + BITS TEN : 1; // bit 3 + BITS ILIEN : 1; // bit 4 + BITS RIEN : 1; // bit 5 + BITS TCIEN : 1; // bit 6 + BITS TIEN : 1; // bit 7 + }; // CR2 bitfield + + /// register _UART2_CR2 reset value + #define sfr_UART2_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** UART2 control register 3 (CR3 at 0x5246) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS LBCL : 1; // bit 0 + BITS CPHA : 1; // bit 1 + BITS CPOL : 1; // bit 2 + BITS CKEN : 1; // bit 3 + BITS STOP : 2; // bits 4-5 + BITS : 1; // 1 bit + BITS LINEN : 1; // bit 7 + }; // CR3 bitfield + + /// register _UART2_CR3 reset value + #define sfr_UART2_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** UART2 control register 4 (CR4 at 0x5247) */ + union { + + /// bytewise access to CR4 + uint8_t byte; + + /// bitwise access to register CR4 + struct { + BITS ADD : 4; // bits 0-3 + BITS LBDF : 1; // bit 4 + BITS LBDL : 1; // bit 5 + BITS LBDIEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR4 bitfield + + /// register _UART2_CR4 reset value + #define sfr_UART2_CR4_RESET_VALUE ((uint8_t) 0x00) + + } CR4; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** UART2 control register 6 (CR6 at 0x5249) */ + union { + + /// bytewise access to CR6 + uint8_t byte; + + /// bitwise access to register CR6 + struct { + BITS LSF : 1; // bit 0 + BITS LHDF : 1; // bit 1 + BITS LHDIEN : 1; // bit 2 + BITS : 1; // 1 bit + BITS LASE : 1; // bit 4 + BITS LSLV : 1; // bit 5 + BITS : 1; // 1 bit + BITS LDUM : 1; // bit 7 + }; // CR6 bitfield + + /// register _UART2_CR6 reset value + #define sfr_UART2_CR6_RESET_VALUE ((uint8_t) 0x00) + + } CR6; + + + /** UART2 guard time register (GTR at 0x524a) */ + union { + + /// bytewise access to GTR + uint8_t byte; + + /// bitwise access to register GTR + struct { + BITS GT : 8; // bits 0-7 + }; // GTR bitfield + + /// register _UART2_GTR reset value + #define sfr_UART2_GTR_RESET_VALUE ((uint8_t) 0x00) + + } GTR; + + + /** UART2 prescaler register (PSCR at 0x524b) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCR bitfield + + /// register _UART2_PSCR reset value + #define sfr_UART2_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + +} UART2_t; + +/// access to UART2 SFR registers +#define sfr_UART2 (*((UART2_t*) 0x5240)) + + +//------------------------ +// Module WWDG +//------------------------ + +/** struct containing WWDG module registers */ +typedef struct { + + /** WWDG control register (CR at 0x50d1) */ + union { + + /// bytewise access to CR + uint8_t byte; + + /// bitwise access to register CR + struct { + BITS T0 : 1; // bit 0 + BITS T1 : 1; // bit 1 + BITS T2 : 1; // bit 2 + BITS T3 : 1; // bit 3 + BITS T4 : 1; // bit 4 + BITS T5 : 1; // bit 5 + BITS T6 : 1; // bit 6 + BITS WDGA : 1; // bit 7 + }; // CR bitfield + + /// register _WWDG_CR reset value + #define sfr_WWDG_CR_RESET_VALUE ((uint8_t) 0x7F) + + } CR; + + + /** WWDR window register (WR at 0x50d2) */ + union { + + /// bytewise access to WR + uint8_t byte; + + /// bitwise access to register WR + struct { + BITS W0 : 1; // bit 0 + BITS W1 : 1; // bit 1 + BITS W2 : 1; // bit 2 + BITS W3 : 1; // bit 3 + BITS W4 : 1; // bit 4 + BITS W5 : 1; // bit 5 + BITS W6 : 1; // bit 6 + BITS : 1; // 1 bit + }; // WR bitfield + + /// register _WWDG_WR reset value + #define sfr_WWDG_WR_RESET_VALUE ((uint8_t) 0x7F) + + } WR; + +} WWDG_t; + +/// access to WWDG SFR registers +#define sfr_WWDG (*((WWDG_t*) 0x50d1)) + + +// undefine local macros +#undef BITS + +// required for C++ +#ifdef __cplusplus + } // extern "C" +#endif + +/*------------------------------------------------------------------------- + END OF MODULE DEFINITION FOR MULTIPLE INLUSION +-------------------------------------------------------------------------*/ +#endif // STM8S105C6_H diff --git a/ports/stm8_oss/stm8-include/STM8S105K6.h b/ports/stm8_oss/stm8-include/STM8S105K6.h new file mode 100644 index 00000000..7faf0649 --- /dev/null +++ b/ports/stm8_oss/stm8-include/STM8S105K6.h @@ -0,0 +1,4922 @@ +/*------------------------------------------------------------------------- + + STM8S105K6.h - Device Declarations + + STM8S/STM8AF, medium density with ROM bootloader + + Copyright (C) 2020, Georg Icking-Konert + + Mainstream Access line 8-bit MCU with 32 Kbytes Flash, 16 MHz CPU, integrated EEPROM + + datasheet: https://www.st.com/resource/en/datasheet/stm8s105k6.pdf + reference: RM0016 https://www.st.com/content/ccc/resource/technical/document/reference_manual/9a/1b/85/07/ca/eb/4f/dd/CD00190271.pdf/files/CD00190271.pdf/jcr:content/translations/en.CD00190271.pdf + + MIT License + + Copyright (c) 2020 Georg Icking-Konert + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. + +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- + MODULE DEFINITION FOR MULTIPLE INCLUSION +-------------------------------------------------------------------------*/ +#ifndef STM8S105K6_H +#define STM8S105K6_H + +// DEVICE NAME +#define DEVICE_STM8S105K6 + +// DEVICE FAMILY +#define FAMILY_STM8S + +// required for C++ +#ifdef __cplusplus + extern "C" { +#endif + + +/*------------------------------------------------------------------------- + INCLUDE FILES +-------------------------------------------------------------------------*/ +#include + + +/*------------------------------------------------------------------------- + COMPILER SPECIFIC SETTINGS +-------------------------------------------------------------------------*/ + +// Cosmic compiler +#if defined(__CSMC__) + + // macros to unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) @far @interrupt void func(void) ///< handler for interrupt service routine + #define ISR_HANDLER_TRAP(func) void @far @interrupt func(void) ///< handler for trap service routine + + // definition of inline functions + #define INLINE @inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() _asm("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() _asm("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() _asm("rim") ///< enable interrupt handling + #define TRIGGER_TRAP _asm("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() _asm("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() _asm("halt") ///< put controller to HALT mode + #define SW_RESET() _asm("dc.b $75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + + +// IAR Compiler +#elif defined(__ICCSTM8__) + + // include intrinsic functions + #include + + // macros to unify ISR declaration and implementation + #define STRINGVECTOR(x) #x + #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) + #define ISR_HANDLER( a, b ) \ + _Pragma( VECTOR_ID( (b)+2 ) ) \ + __interrupt void (a)( void ) + #define ISR_HANDLER_TRAP(a) \ + _Pragma( VECTOR_ID( 1 ) ) \ + __interrupt void (a) (void) + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __no_operation() ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __disable_interrupt() ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __enable_interrupt() ///< enable interrupt handling + #define TRIGGER_TRAP __trap() ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __wait_for_interrupt() ///< stop code execution and wait for interrupt + #define ENTER_HALT() __halt() ///< put controller to HALT mode + #define SW_RESET() __asm("dc8 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned char ///< data type in bit structs (deviating from C90 standard) + + +// SDCC compiler +#elif defined(__SDCC) + + // store SDCC version in preprocessor friendly way + #define SDCC_VERSION (__SDCC_VERSION_MAJOR * 10000 \ + + __SDCC_VERSION_MINOR * 100 \ + + __SDCC_VERSION_PATCH) + + // unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) void func(void) __interrupt(irq) ///< handler for interrupt service routine + #if SDCC_VERSION >= 30403 // traps require >=v3.4.3 + #define ISR_HANDLER_TRAP(func) void func() __trap ///< handler for trap service routine + #else + #error traps require SDCC >=3.4.3. Please update! + #endif + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __asm__("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __asm__("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __asm__("rim") ///< enable interrupt handling + #define TRIGGER_TRAP __asm__("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __asm__("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() __asm__("halt") ///< put controller to HALT mode + #define SW_RESET() __asm__(".db 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + +// unsupported compiler -> stop +#else + #error: compiler not supported +#endif + + +/*------------------------------------------------------------------------- + FOR CONVENIENT PIN ACCESS +-------------------------------------------------------------------------*/ + +#define PIN0 0x01 +#define PIN1 0x02 +#define PIN2 0x04 +#define PIN3 0x08 +#define PIN4 0x10 +#define PIN5 0x20 +#define PIN6 0x40 +#define PIN7 0x80 + + +/*------------------------------------------------------------------------- + DEVICE MEMORY (size in bytes) +-------------------------------------------------------------------------*/ + +// RAM +#define RAM_ADDR_START 0x000000 +#define RAM_ADDR_END 0x0007FF +#define RAM_SIZE 2048 + + +// FLASH +#define FLASH_ADDR_START 0x008000 +#define FLASH_ADDR_END 0x00FFFF +#define FLASH_SIZE 32768 + + +// SFR1 +#define SFR1_ADDR_START 0x005000 +#define SFR1_ADDR_END 0x0057FF +#define SFR1_SIZE 2048 + + +// SFR2 +#define SFR2_ADDR_START 0x007F00 +#define SFR2_ADDR_END 0x007FFF +#define SFR2_SIZE 256 + + +// BOOTROM +#define BOOTROM_ADDR_START 0x006000 +#define BOOTROM_ADDR_END 0x0067FF +#define BOOTROM_SIZE 2048 + + +// EEPROM +#define EEPROM_ADDR_START 0x004000 +#define EEPROM_ADDR_END 0x0043FF +#define EEPROM_SIZE 1024 + + +// OPTION +#define OPTION_ADDR_START 0x004800 +#define OPTION_ADDR_END 0x00487F +#define OPTION_SIZE 128 + + +// MEMORY WIDTH (>32kB flash exceeds 16bit, as flash starts at 0x8000) +#define FLASH_ADDR_WIDTH 16 ///< width of address space +#define FLASH_POINTER_T uint16_t ///< address variable type + + +/*------------------------------------------------------------------------- + UNIQUE IDENTIFIER (size in bytes) +-------------------------------------------------------------------------*/ + +#define UID_ADDR_START 0x48CD ///< start address of unique identifier +#define UID_SIZE 12 ///< size of unique identifier [B] +#define UID(N) (*((uint8_t*) (UID_ADDR_START+N))) ///< read unique identifier byte N + + +/*------------------------------------------------------------------------- + ISR Vector Table (SDCC, IAR) + Notes: + - IAR has an IRQ offset of +2 compared to datasheet and below numbers + - Cosmic uses a separate, device specific file 'stm8_interrupt_vector.c' + - different interrupt sources may share the same IRQ +-------------------------------------------------------------------------*/ + +// interrupt IRQ +#define _TLI_VECTOR_ 0 +#define _AWU_VECTOR_ 1 ///< AWU interrupt vector: enable: AWU_CSR1.AWUEN, pending: AWU_CSR1.AWUF, priority: ITC_SPR1.VECT1SPR +#define _CLK_CSS_VECTOR_ 2 ///< CLK_CSS interrupt vector: enable: CLK_CSSR.CSSDIE, pending: CLK_CSSR.CSSD, priority: ITC_SPR1.VECT2SPR +#define _CLK_SWITCH_VECTOR_ 2 ///< CLK_SWITCH interrupt vector: enable: CLK_SWCR.SWIEN, pending: CLK_SWCR.SWIF, priority: ITC_SPR1.VECT2SPR +#define _EXTI0_VECTOR_ 3 ///< EXTI0 interrupt vector: enable: PA_CR2.C20, pending: PA_IDR.IDR0, priority: ITC_SPR1.VECT3SPR +#define _EXTI1_VECTOR_ 4 ///< EXTI1 interrupt vector: enable: PB_CR2.C20, pending: PB_IDR.IDR0, priority: ITC_SPR2.VECT4SPR +#define _EXTI2_VECTOR_ 5 ///< EXTI2 interrupt vector: enable: PC_CR2.C20, pending: PC_IDR.IDR0, priority: ITC_SPR2.VECT5SPR +#define _EXTI3_VECTOR_ 6 ///< EXTI3 interrupt vector: enable: PD_CR2.C20, pending: PD_IDR.IDR0, priority: ITC_SPR2.VECT6SPR +#define _EXTI4_VECTOR_ 7 ///< EXTI4 interrupt vector: enable: PE_CR2.C20, pending: PE_IDR.IDR0, priority: ITC_SPR2.VECT7SPR +#define _SPI_CRCERR_VECTOR_ 10 ///< SPI_CRCERR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.CRCERR, priority: ITC_SPR3.VECT10SPR +#define _SPI_MODF_VECTOR_ 10 ///< SPI_MODF interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.MODF, priority: ITC_SPR3.VECT10SPR +#define _SPI_OVR_VECTOR_ 10 ///< SPI_OVR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.OVR, priority: ITC_SPR3.VECT10SPR +#define _SPI_RXNE_VECTOR_ 10 ///< SPI_RXNE interrupt vector: enable: SPI_ICR.RXIE, pending: SPI_SR.RXNE, priority: ITC_SPR3.VECT10SPR +#define _SPI_TXE_VECTOR_ 10 ///< SPI_TXE interrupt vector: enable: SPI_ICR.TXIE, pending: SPI_SR.TXE, priority: ITC_SPR3.VECT10SPR +#define _SPI_WKUP_VECTOR_ 10 ///< SPI_WKUP interrupt vector: enable: SPI_ICR.WKIE, pending: SPI_SR.WKUP, priority: ITC_SPR3.VECT10SPR +#define _TIM1_OVR_BIF_VECTOR_ 11 ///< TIM1_OVR_BIF interrupt vector: enable: TIM1_IER.BIE, pending: TIM1_SR1.BIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_OVR_TIF_VECTOR_ 11 ///< TIM1_OVR_TIF interrupt vector: enable: TIM1_IER.TIE, pending: TIM1_SR1.TIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_OVR_UIF_VECTOR_ 11 ///< TIM1_OVR_UIF interrupt vector: enable: TIM1_IER.UIE, pending: TIM1_SR1.UIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_CAPCOM_CC1IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC1IF interrupt vector: enable: TIM1_IER.CC1IE, pending: TIM1_SR1.CC1IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC2IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC2IF interrupt vector: enable: TIM1_IER.CC2IE, pending: TIM1_SR1.CC2IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC3IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC3IF interrupt vector: enable: TIM1_IER.CC3IE, pending: TIM1_SR1.CC3IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC4IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC4IF interrupt vector: enable: TIM1_IER.CC4IE, pending: TIM1_SR1.CC4IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_COMIF_VECTOR_ 12 ///< TIM1_CAPCOM_COMIF interrupt vector: enable: TIM1_IER.COMIE, pending: TIM1_SR1.COMIF, priority: ITC_SPR4.VECT12SPR +#define _TIM2_OVR_UIF_VECTOR_ 13 ///< TIM2_OVR_UIF interrupt vector: enable: TIM2_IER.UIE, pending: TIM2_SR1.UIF, priority: ITC_SPR4.VECT13SPR +#define _TIM3_OVR_UIF_VECTOR_ 15 ///< TIM3_OVR_UIF interrupt vector: enable: TIM3_IER.UIE, pending: TIM3_SR1.UIF, priority: ITC_SPR4.VECT15SPR +#define _TIM2_CAPCOM_CC1IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC1IF interrupt vector: enable: TIM2_IER.CC1IE, pending: TIM2_SR1.CC1IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_CC2IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC2IF interrupt vector: enable: TIM2_IER.CC2IE, pending: TIM2_SR1.CC2IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_CC3IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC3IF interrupt vector: enable: TIM2_IER.CC3IE, pending: TIM2_SR1.CC3IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_TIF_VECTOR_ 14 ///< TIM2_CAPCOM_TIF interrupt vector: enable: TIM2_IER.TIE, pending: TIM2_SR1.TIF, priority: ITC_SPR4.VECT14SPR +#define _TIM3_CAPCOM_CC1IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC1IF interrupt vector: enable: TIM3_IER.CC1IE, pending: TIM3_SR1.CC1IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_CC2IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC2IF interrupt vector: enable: TIM3_IER.CC2IE, pending: TIM3_SR1.CC2IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_CC3IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC3IF interrupt vector: enable: TIM3_IER.CC3IE, pending: TIM3_SR1.CC3IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_TIF_VECTOR_ 16 ///< TIM3_CAPCOM_TIF interrupt vector: enable: TIM3_IER.TIE, pending: TIM3_SR1.TIF, priority: ITC_SPR5.VECT16SPR +#define _I2C_ADD10_VECTOR_ 19 ///< I2C_ADD10 interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADD10, priority: ITC_SPR5.VECT19SPR +#define _I2C_ADDR_VECTOR_ 19 ///< I2C_ADDR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADDR, priority: ITC_SPR5.VECT19SPR +#define _I2C_AF_VECTOR_ 19 ///< I2C_AF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.AF, priority: ITC_SPR5.VECT19SPR +#define _I2C_ARLO_VECTOR_ 19 ///< I2C_ARLO interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.ARLO, priority: ITC_SPR5.VECT19SPR +#define _I2C_BERR_VECTOR_ 19 ///< I2C_BERR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.BERR, priority: ITC_SPR5.VECT19SPR +#define _I2C_BTF_VECTOR_ 19 ///< I2C_BTF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.BTF, priority: ITC_SPR5.VECT19SPR +#define _I2C_OVR_VECTOR_ 19 ///< I2C_OVR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.OVR, priority: ITC_SPR5.VECT19SPR +#define _I2C_RXNE_VECTOR_ 19 ///< I2C_RXNE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.RXNE, priority: ITC_SPR5.VECT19SPR +#define _I2C_SB_VECTOR_ 19 ///< I2C_SB interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.SB, priority: ITC_SPR5.VECT19SPR +#define _I2C_STOPF_VECTOR_ 19 ///< I2C_STOPF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.STOPF, priority: ITC_SPR5.VECT19SPR +#define _I2C_TXE_VECTOR_ 19 ///< I2C_TXE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.TXE, priority: ITC_SPR5.VECT19SPR +#define _I2C_WUFH_VECTOR_ 19 ///< I2C_WUFH interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.WUFH, priority: ITC_SPR5.VECT19SPR +#define _UART2_T_TC_VECTOR_ 20 ///< UART2_T_TC interrupt vector: enable: UART2_CR2.TCIEN, pending: UART2_SR.TC, priority: ITC_SPR6.VECT20SPR +#define _UART2_T_TXE_VECTOR_ 20 ///< UART2_T_TXE interrupt vector: enable: UART2_CR2.TIEN, pending: UART2_SR.TXE, priority: ITC_SPR6.VECT20SPR +#define _UART2_R_IDLE_VECTOR_ 21 ///< UART2_R_IDLE interrupt vector: enable: UART2_CR2.ILIEN, pending: UART2_SR.IDLE, priority: ITC_SPR6.VECT21SPR +#define _UART2_R_LBDF_VECTOR_ 21 ///< UART2_R_LBDF interrupt vector: enable: UART2_CR4.LBDIEN, pending: UART2_CR4.LBDF, priority: ITC_SPR6.VECT21SPR +#define _UART2_R_OR_VECTOR_ 21 ///< UART2_R_OR interrupt vector: enable: UART2_CR2.RIEN, pending: UART2_SR.OR_LHE, priority: ITC_SPR6.VECT21SPR +#define _UART2_R_PE_VECTOR_ 21 ///< UART2_R_PE interrupt vector: enable: UART2_CR1.PIEN, pending: UART2_SR.PE, priority: ITC_SPR6.VECT21SPR +#define _UART2_R_RXNE_VECTOR_ 21 ///< UART2_R_RXNE interrupt vector: enable: UART2_CR2.RIEN, pending: UART2_SR.RXNE, priority: ITC_SPR6.VECT21SPR +#define _ADC1_AWDG_VECTOR_ 22 ///< ADC1_AWDG interrupt vector: enable: ADC_CSR.AWDIE, pending: ADC_CSR.AWD, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS0_VECTOR_ 22 ///< ADC1_AWS0 interrupt vector: enable: ADC_AWCRL.AWEN0, pending: ADC_AWSRL.AWS0, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS1_VECTOR_ 22 ///< ADC1_AWS1 interrupt vector: enable: ADC_AWCRL.AWEN1, pending: ADC_AWSRL.AWS1, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS2_VECTOR_ 22 ///< ADC1_AWS2 interrupt vector: enable: ADC_AWCRL.AWEN2, pending: ADC_AWSRL.AWS2, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS3_VECTOR_ 22 ///< ADC1_AWS3 interrupt vector: enable: ADC_AWCRL.AWEN3, pending: ADC_AWSRL.AWS3, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS4_VECTOR_ 22 ///< ADC1_AWS4 interrupt vector: enable: ADC_AWCRL.AWEN4, pending: ADC_AWSRL.AWS4, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS5_VECTOR_ 22 ///< ADC1_AWS5 interrupt vector: enable: ADC_AWCRL.AWEN5, pending: ADC_AWSRL.AWS5, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS6_VECTOR_ 22 ///< ADC1_AWS6 interrupt vector: enable: ADC_AWCRL.AWEN6, pending: ADC_AWSRL.AWS6, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS7_VECTOR_ 22 ///< ADC1_AWS7 interrupt vector: enable: ADC_AWCRL.AWEN7, pending: ADC_AWSRL.AWS7, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS8_VECTOR_ 22 ///< ADC1_AWS8 interrupt vector: enable: ADC_AWCRH.AWEN8, pending: ADC_AWSRH.AWS8, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS9_VECTOR_ 22 ///< ADC1_AWS9 interrupt vector: enable: ADC_AWCRH.AWEN9, pending: ADC_AWSRH.AWS9, priority: ITC_SPR6.VECT22SPR +#define _ADC1_EOC_VECTOR_ 22 ///< ADC1_EOC interrupt vector: enable: ADC_CSR.EOCIE, pending: ADC_CSR.EOC, priority: ITC_SPR6.VECT22SPR +#define _TIM4_OVR_UIF_VECTOR_ 23 ///< TIM4_OVR_UIF interrupt vector: enable: TIM4_IER.UIE, pending: TIM4_SR.UIF, priority: ITC_SPR6.VECT23SPR +#define _FLASH_EOP_VECTOR_ 24 ///< FLASH_EOP interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.EOP, priority: ITC_SPR6.VECT24SPR +#define _FLASH_WR_PG_DIS_VECTOR_ 24 ///< FLASH_WR_PG_DIS interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.WR_PG_DIS, priority: ITC_SPR6.VECT24SPR + + +/*------------------------------------------------------------------------- + DEFINITION OF STM8 PERIPHERAL REGISTERS +-------------------------------------------------------------------------*/ + +//------------------------ +// Module ADC1 +//------------------------ + +/** struct containing ADC1 module registers */ +typedef struct { + + /** ADC data buffer registers (DB0RH at 0x53e0) */ + union { + + /// bytewise access to DB0RH + uint8_t byte; + + /// bitwise access to register DB0RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB0RH bitfield + + /// register _ADC1_DB0RH reset value + #define sfr_ADC1_DB0RH_RESET_VALUE ((uint8_t) 0x00) + + } DB0RH; + + + /** ADC data buffer registers (DB0RL at 0x53e1) */ + union { + + /// bytewise access to DB0RL + uint8_t byte; + + /// bitwise access to register DB0RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB0RL bitfield + + /// register _ADC1_DB0RL reset value + #define sfr_ADC1_DB0RL_RESET_VALUE ((uint8_t) 0x00) + + } DB0RL; + + + /** ADC data buffer registers (DB1RH at 0x53e2) */ + union { + + /// bytewise access to DB1RH + uint8_t byte; + + /// bitwise access to register DB1RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB1RH bitfield + + /// register _ADC1_DB1RH reset value + #define sfr_ADC1_DB1RH_RESET_VALUE ((uint8_t) 0x00) + + } DB1RH; + + + /** ADC data buffer registers (DB1RL at 0x53e3) */ + union { + + /// bytewise access to DB1RL + uint8_t byte; + + /// bitwise access to register DB1RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB1RL bitfield + + /// register _ADC1_DB1RL reset value + #define sfr_ADC1_DB1RL_RESET_VALUE ((uint8_t) 0x00) + + } DB1RL; + + + /** ADC data buffer registers (DB2RH at 0x53e4) */ + union { + + /// bytewise access to DB2RH + uint8_t byte; + + /// bitwise access to register DB2RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB2RH bitfield + + /// register _ADC1_DB2RH reset value + #define sfr_ADC1_DB2RH_RESET_VALUE ((uint8_t) 0x00) + + } DB2RH; + + + /** ADC data buffer registers (DB2RL at 0x53e5) */ + union { + + /// bytewise access to DB2RL + uint8_t byte; + + /// bitwise access to register DB2RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB2RL bitfield + + /// register _ADC1_DB2RL reset value + #define sfr_ADC1_DB2RL_RESET_VALUE ((uint8_t) 0x00) + + } DB2RL; + + + /** ADC data buffer registers (DB3RH at 0x53e6) */ + union { + + /// bytewise access to DB3RH + uint8_t byte; + + /// bitwise access to register DB3RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB3RH bitfield + + /// register _ADC1_DB3RH reset value + #define sfr_ADC1_DB3RH_RESET_VALUE ((uint8_t) 0x00) + + } DB3RH; + + + /** ADC data buffer registers (DB3RL at 0x53e7) */ + union { + + /// bytewise access to DB3RL + uint8_t byte; + + /// bitwise access to register DB3RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB3RL bitfield + + /// register _ADC1_DB3RL reset value + #define sfr_ADC1_DB3RL_RESET_VALUE ((uint8_t) 0x00) + + } DB3RL; + + + /** ADC data buffer registers (DB4RH at 0x53e8) */ + union { + + /// bytewise access to DB4RH + uint8_t byte; + + /// bitwise access to register DB4RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB4RH bitfield + + /// register _ADC1_DB4RH reset value + #define sfr_ADC1_DB4RH_RESET_VALUE ((uint8_t) 0x00) + + } DB4RH; + + + /** ADC data buffer registers (DB4RL at 0x53e9) */ + union { + + /// bytewise access to DB4RL + uint8_t byte; + + /// bitwise access to register DB4RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB4RL bitfield + + /// register _ADC1_DB4RL reset value + #define sfr_ADC1_DB4RL_RESET_VALUE ((uint8_t) 0x00) + + } DB4RL; + + + /** ADC data buffer registers (DB5RH at 0x53ea) */ + union { + + /// bytewise access to DB5RH + uint8_t byte; + + /// bitwise access to register DB5RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB5RH bitfield + + /// register _ADC1_DB5RH reset value + #define sfr_ADC1_DB5RH_RESET_VALUE ((uint8_t) 0x00) + + } DB5RH; + + + /** ADC data buffer registers (DB5RL at 0x53eb) */ + union { + + /// bytewise access to DB5RL + uint8_t byte; + + /// bitwise access to register DB5RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB5RL bitfield + + /// register _ADC1_DB5RL reset value + #define sfr_ADC1_DB5RL_RESET_VALUE ((uint8_t) 0x00) + + } DB5RL; + + + /** ADC data buffer registers (DB6RH at 0x53ec) */ + union { + + /// bytewise access to DB6RH + uint8_t byte; + + /// bitwise access to register DB6RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB6RH bitfield + + /// register _ADC1_DB6RH reset value + #define sfr_ADC1_DB6RH_RESET_VALUE ((uint8_t) 0x00) + + } DB6RH; + + + /** ADC data buffer registers (DB6RL at 0x53ed) */ + union { + + /// bytewise access to DB6RL + uint8_t byte; + + /// bitwise access to register DB6RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB6RL bitfield + + /// register _ADC1_DB6RL reset value + #define sfr_ADC1_DB6RL_RESET_VALUE ((uint8_t) 0x00) + + } DB6RL; + + + /** ADC data buffer registers (DB7RH at 0x53ee) */ + union { + + /// bytewise access to DB7RH + uint8_t byte; + + /// bitwise access to register DB7RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB7RH bitfield + + /// register _ADC1_DB7RH reset value + #define sfr_ADC1_DB7RH_RESET_VALUE ((uint8_t) 0x00) + + } DB7RH; + + + /** ADC data buffer registers (DB7RL at 0x53ef) */ + union { + + /// bytewise access to DB7RL + uint8_t byte; + + /// bitwise access to register DB7RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB7RL bitfield + + /// register _ADC1_DB7RL reset value + #define sfr_ADC1_DB7RL_RESET_VALUE ((uint8_t) 0x00) + + } DB7RL; + + + /** ADC data buffer registers (DB8RH at 0x53f0) */ + union { + + /// bytewise access to DB8RH + uint8_t byte; + + /// bitwise access to register DB8RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB8RH bitfield + + /// register _ADC1_DB8RH reset value + #define sfr_ADC1_DB8RH_RESET_VALUE ((uint8_t) 0x00) + + } DB8RH; + + + /** ADC data buffer registers (DB8RL at 0x53f1) */ + union { + + /// bytewise access to DB8RL + uint8_t byte; + + /// bitwise access to register DB8RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB8RL bitfield + + /// register _ADC1_DB8RL reset value + #define sfr_ADC1_DB8RL_RESET_VALUE ((uint8_t) 0x00) + + } DB8RL; + + + /** ADC data buffer registers (DB9RH at 0x53f2) */ + union { + + /// bytewise access to DB9RH + uint8_t byte; + + /// bitwise access to register DB9RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB9RH bitfield + + /// register _ADC1_DB9RH reset value + #define sfr_ADC1_DB9RH_RESET_VALUE ((uint8_t) 0x00) + + } DB9RH; + + + /** ADC data buffer registers (DB9RL at 0x53f3) */ + union { + + /// bytewise access to DB9RL + uint8_t byte; + + /// bitwise access to register DB9RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB9RL bitfield + + /// register _ADC1_DB9RL reset value + #define sfr_ADC1_DB9RL_RESET_VALUE ((uint8_t) 0x00) + + } DB9RL; + + + /// Reserved register (12B) + uint8_t Reserved_1[12]; + + + /** ADC control/status register (CSR at 0x5400) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// bitwise access to register CSR + struct { + BITS CH : 4; // bits 0-3 + BITS AWDIE : 1; // bit 4 + BITS EOCIE : 1; // bit 5 + BITS AWD : 1; // bit 6 + BITS EOC : 1; // bit 7 + }; // CSR bitfield + + /// register _ADC1_CSR reset value + #define sfr_ADC1_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + + + /** ADC configuration register 1 (CR1 at 0x5401) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS ADON : 1; // bit 0 + BITS CONT : 1; // bit 1 + BITS : 2; // 2 bits + BITS SPSEL : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR1 bitfield + + /// register _ADC1_CR1 reset value + #define sfr_ADC1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** ADC configuration register 2 (CR2 at 0x5402) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS : 1; // 1 bit + BITS SCAN : 1; // bit 1 + BITS : 1; // 1 bit + BITS ALIGN : 1; // bit 3 + BITS EXTSEL : 2; // bits 4-5 + BITS EXTTRIG : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _ADC1_CR2 reset value + #define sfr_ADC1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** ADC configuration register 3 (CR3 at 0x5403) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS : 6; // 6 bits + BITS OVR : 1; // bit 6 + BITS DBUF : 1; // bit 7 + }; // CR3 bitfield + + /// register _ADC1_CR3 reset value + #define sfr_ADC1_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** ADC data register high (DRH at 0x5404) */ + union { + + /// bytewise access to DRH + uint8_t byte; + + /// bitwise access to register DRH + struct { + BITS DH : 8; // bits 0-7 + }; // DRH bitfield + + /// register _ADC1_DRH reset value + #define sfr_ADC1_DRH_RESET_VALUE ((uint8_t) 0x00) + + } DRH; + + + /** ADC data register low (DRL at 0x5405) */ + union { + + /// bytewise access to DRL + uint8_t byte; + + /// bitwise access to register DRL + struct { + BITS DL : 8; // bits 0-7 + }; // DRL bitfield + + /// register _ADC1_DRL reset value + #define sfr_ADC1_DRL_RESET_VALUE ((uint8_t) 0x00) + + } DRL; + + + /** ADC Schmitt trigger disable register high (TDRH at 0x5406) */ + union { + + /// bytewise access to TDRH + uint8_t byte; + + /// bitwise access to register TDRH + struct { + BITS TD : 8; // bits 0-7 + }; // TDRH bitfield + + /// register _ADC1_TDRH reset value + #define sfr_ADC1_TDRH_RESET_VALUE ((uint8_t) 0x00) + + } TDRH; + + + /** ADC Schmitt trigger disable register low (TDRL at 0x5407) */ + union { + + /// bytewise access to TDRL + uint8_t byte; + + /// bitwise access to register TDRL + struct { + BITS TL : 8; // bits 0-7 + }; // TDRL bitfield + + /// register _ADC1_TDRL reset value + #define sfr_ADC1_TDRL_RESET_VALUE ((uint8_t) 0x00) + + } TDRL; + + + /** ADC high threshold register high (HTRH at 0x5408) */ + union { + + /// bytewise access to HTRH + uint8_t byte; + + /// bitwise access to register HTRH + struct { + BITS HT : 8; // bits 0-7 + }; // HTRH bitfield + + /// register _ADC1_HTRH reset value + #define sfr_ADC1_HTRH_RESET_VALUE ((uint8_t) 0x03) + + } HTRH; + + + /** ADC high threshold register low (HTRL at 0x5409) */ + union { + + /// bytewise access to HTRL + uint8_t byte; + + /// bitwise access to register HTRL + struct { + BITS HT : 2; // bits 0-1 + BITS : 6; // 6 bits + }; // HTRL bitfield + + /// register _ADC1_HTRL reset value + #define sfr_ADC1_HTRL_RESET_VALUE ((uint8_t) 0xFF) + + } HTRL; + + + /** ADC low threshold register high (LTRH at 0x540a) */ + union { + + /// bytewise access to LTRH + uint8_t byte; + + /// bitwise access to register LTRH + struct { + BITS LT : 8; // bits 0-7 + }; // LTRH bitfield + + /// register _ADC1_LTRH reset value + #define sfr_ADC1_LTRH_RESET_VALUE ((uint8_t) 0x00) + + } LTRH; + + + /** ADC low threshold register low (LTRL at 0x540b) */ + union { + + /// bytewise access to LTRL + uint8_t byte; + + /// bitwise access to register LTRL + struct { + BITS LT : 2; // bits 0-1 + BITS : 6; // 6 bits + }; // LTRL bitfield + + /// register _ADC1_LTRL reset value + #define sfr_ADC1_LTRL_RESET_VALUE ((uint8_t) 0x00) + + } LTRL; + + + /** ADC analog watchdog status register high (AWSRH at 0x540c) */ + union { + + /// bytewise access to AWSRH + uint8_t byte; + + /// bitwise access to register AWSRH + struct { + BITS AWS8 : 1; // bit 0 + BITS AWS9 : 1; // bit 1 + BITS : 6; // 6 bits + }; // AWSRH bitfield + + /// register _ADC1_AWSRH reset value + #define sfr_ADC1_AWSRH_RESET_VALUE ((uint8_t) 0x00) + + } AWSRH; + + + /** ADC analog watchdog status register low (AWSRL at 0x540d) */ + union { + + /// bytewise access to AWSRL + uint8_t byte; + + /// bitwise access to register AWSRL + struct { + BITS AWS0 : 1; // bit 0 + BITS AWS1 : 1; // bit 1 + BITS AWS2 : 1; // bit 2 + BITS AWS3 : 1; // bit 3 + BITS AWS4 : 1; // bit 4 + BITS AWS5 : 1; // bit 5 + BITS AWS6 : 1; // bit 6 + BITS AWS7 : 1; // bit 7 + }; // AWSRL bitfield + + /// register _ADC1_AWSRL reset value + #define sfr_ADC1_AWSRL_RESET_VALUE ((uint8_t) 0x00) + + } AWSRL; + + + /** ADC analog watchdog control register high (AWCRH at 0x540e) */ + union { + + /// bytewise access to AWCRH + uint8_t byte; + + /// bitwise access to register AWCRH + struct { + BITS AWEN8 : 1; // bit 0 + BITS AWEN9 : 1; // bit 1 + BITS : 6; // 6 bits + }; // AWCRH bitfield + + /// register _ADC1_AWCRH reset value + #define sfr_ADC1_AWCRH_RESET_VALUE ((uint8_t) 0x00) + + } AWCRH; + + + /** ADC analog watchdog control register low (AWCRL at 0x540f) */ + union { + + /// bytewise access to AWCRL + uint8_t byte; + + /// bitwise access to register AWCRL + struct { + BITS AWEN0 : 1; // bit 0 + BITS AWEN1 : 1; // bit 1 + BITS AWEN2 : 1; // bit 2 + BITS AWEN3 : 1; // bit 3 + BITS AWEN4 : 1; // bit 4 + BITS AWEN5 : 1; // bit 5 + BITS AWEN6 : 1; // bit 6 + BITS AWEN7 : 1; // bit 7 + }; // AWCRL bitfield + + /// register _ADC1_AWCRL reset value + #define sfr_ADC1_AWCRL_RESET_VALUE ((uint8_t) 0x00) + + } AWCRL; + +} ADC1_t; + +/// access to ADC1 SFR registers +#define sfr_ADC1 (*((ADC1_t*) 0x53e0)) + + +//------------------------ +// Module AWU +//------------------------ + +/** struct containing AWU module registers */ +typedef struct { + + /** AWU control/status register 1 (CSR1 at 0x50f0) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// bitwise access to register CSR1 + struct { + BITS MSR : 1; // bit 0 + BITS : 3; // 3 bits + BITS AWUEN : 1; // bit 4 + BITS AWUF : 1; // bit 5 + BITS : 2; // 2 bits + }; // CSR1 bitfield + + /// register _AWU_CSR1 reset value + #define sfr_AWU_CSR1_RESET_VALUE ((uint8_t) 0x00) + + } CSR1; + + + /** AWU asynchronous prescaler buffer register (APR at 0x50f1) */ + union { + + /// bytewise access to APR + uint8_t byte; + + /// bitwise access to register APR + struct { + BITS APR : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // APR bitfield + + /// register _AWU_APR reset value + #define sfr_AWU_APR_RESET_VALUE ((uint8_t) 0x3F) + + } APR; + + + /** AWU timebase selection register (TBR at 0x50f2) */ + union { + + /// bytewise access to TBR + uint8_t byte; + + /// bitwise access to register TBR + struct { + BITS AWUTB : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // TBR bitfield + + /// register _AWU_TBR reset value + #define sfr_AWU_TBR_RESET_VALUE ((uint8_t) 0x00) + + } TBR; + +} AWU_t; + +/// access to AWU SFR registers +#define sfr_AWU (*((AWU_t*) 0x50f0)) + + +//------------------------ +// Module BEEP +//------------------------ + +/** struct containing BEEP module registers */ +typedef struct { + + /** BEEP control/status register (CSR at 0x50f3) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// bitwise access to register CSR + struct { + BITS BEEPDIV : 5; // bits 0-4 + BITS BEEPEN : 1; // bit 5 + BITS BEEPSEL : 2; // bits 6-7 + }; // CSR bitfield + + /// register _BEEP_CSR reset value + #define sfr_BEEP_CSR_RESET_VALUE ((uint8_t) 0x1F) + + } CSR; + +} BEEP_t; + +/// access to BEEP SFR registers +#define sfr_BEEP (*((BEEP_t*) 0x50f3)) + + +//------------------------ +// Module CLK +//------------------------ + +/** struct containing CLK module registers */ +typedef struct { + + /** Internal clock control register (ICKR at 0x50c0) */ + union { + + /// bytewise access to ICKR + uint8_t byte; + + /// bitwise access to register ICKR + struct { + BITS HSIEN : 1; // bit 0 + BITS HSIRDY : 1; // bit 1 + BITS FHW : 1; // bit 2 + BITS LSIEN : 1; // bit 3 + BITS LSIRDY : 1; // bit 4 + BITS REGAH : 1; // bit 5 + BITS : 2; // 2 bits + }; // ICKR bitfield + + /// register _CLK_ICKR reset value + #define sfr_CLK_ICKR_RESET_VALUE ((uint8_t) 0x01) + + } ICKR; + + + /** External clock control register (ECKR at 0x50c1) */ + union { + + /// bytewise access to ECKR + uint8_t byte; + + /// bitwise access to register ECKR + struct { + BITS HSEEN : 1; // bit 0 + BITS HSERDY : 1; // bit 1 + BITS : 6; // 6 bits + }; // ECKR bitfield + + /// register _CLK_ECKR reset value + #define sfr_CLK_ECKR_RESET_VALUE ((uint8_t) 0x00) + + } ECKR; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** Clock master status register (CMSR at 0x50c3) */ + union { + + /// bytewise access to CMSR + uint8_t byte; + + /// bitwise access to register CMSR + struct { + BITS CKM : 8; // bits 0-7 + }; // CMSR bitfield + + /// register _CLK_CMSR reset value + #define sfr_CLK_CMSR_RESET_VALUE ((uint8_t) 0xE1) + + } CMSR; + + + /** Clock master switch register (SWR at 0x50c4) */ + union { + + /// bytewise access to SWR + uint8_t byte; + + /// bitwise access to register SWR + struct { + BITS SWI : 8; // bits 0-7 + }; // SWR bitfield + + /// register _CLK_SWR reset value + #define sfr_CLK_SWR_RESET_VALUE ((uint8_t) 0xE1) + + } SWR; + + + /** Clock switch control register (SWCR at 0x50c5) */ + union { + + /// bytewise access to SWCR + uint8_t byte; + + /// bitwise access to register SWCR + struct { + BITS SWBSY : 1; // bit 0 + BITS SWEN : 1; // bit 1 + BITS SWIEN : 1; // bit 2 + BITS SWIF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SWCR bitfield + + /// register _CLK_SWCR reset value + #define sfr_CLK_SWCR_RESET_VALUE ((uint8_t) 0x00) + + } SWCR; + + + /** Clock divider register (CKDIVR at 0x50c6) */ + union { + + /// bytewise access to CKDIVR + uint8_t byte; + + /// bitwise access to register CKDIVR + struct { + BITS CPUDIV : 3; // bits 0-2 + BITS HSIDIV : 2; // bits 3-4 + BITS : 3; // 3 bits + }; // CKDIVR bitfield + + /// register _CLK_CKDIVR reset value + #define sfr_CLK_CKDIVR_RESET_VALUE ((uint8_t) 0x18) + + } CKDIVR; + + + /** Peripheral clock gating register 1 (PCKENR1 at 0x50c7) */ + union { + + /// bytewise access to PCKENR1 + uint8_t byte; + + /// bitwise access to register PCKENR1 + struct { + BITS PCKEN : 8; // bits 0-7 + }; // PCKENR1 bitfield + + /// register _CLK_PCKENR1 reset value + #define sfr_CLK_PCKENR1_RESET_VALUE ((uint8_t) 0xFF) + + } PCKENR1; + + + /** Clock security system register (CSSR at 0x50c8) */ + union { + + /// bytewise access to CSSR + uint8_t byte; + + /// bitwise access to register CSSR + struct { + BITS CSSEN : 1; // bit 0 + BITS AUX : 1; // bit 1 + BITS CSSDIE : 1; // bit 2 + BITS CSSD : 1; // bit 3 + BITS : 4; // 4 bits + }; // CSSR bitfield + + /// register _CLK_CSSR reset value + #define sfr_CLK_CSSR_RESET_VALUE ((uint8_t) 0x00) + + } CSSR; + + + /** Configurable clock control register (CCOR at 0x50c9) */ + union { + + /// bytewise access to CCOR + uint8_t byte; + + /// bitwise access to register CCOR + struct { + BITS CCOEN : 1; // bit 0 + BITS CCOSEL : 4; // bits 1-4 + BITS CCORDY : 1; // bit 5 + BITS CC0BSY : 1; // bit 6 + BITS : 1; // 1 bit + }; // CCOR bitfield + + /// register _CLK_CCOR reset value + #define sfr_CLK_CCOR_RESET_VALUE ((uint8_t) 0x00) + + } CCOR; + + + /** Peripheral clock gating register 2 (PCKENR2 at 0x50ca) */ + union { + + /// bytewise access to PCKENR2 + uint8_t byte; + + /// bitwise access to register PCKENR2 + struct { + BITS PCKEN2 : 8; // bits 0-7 + }; // PCKENR2 bitfield + + /// register _CLK_PCKENR2 reset value + #define sfr_CLK_PCKENR2_RESET_VALUE ((uint8_t) 0xFF) + + } PCKENR2; + + + /** CAN clock control register (CANCCR at 0x50cb) */ + union { + + /// bytewise access to CANCCR + uint8_t byte; + + /// bitwise access to register CANCCR + struct { + BITS CANDIV : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // CANCCR bitfield + + /// register _CLK_CANCCR reset value + #define sfr_CLK_CANCCR_RESET_VALUE ((uint8_t) 0x00) + + } CANCCR; + + + /** HSI clock calibration trimming register (HSITRIMR at 0x50cc) */ + union { + + /// bytewise access to HSITRIMR + uint8_t byte; + + /// bitwise access to register HSITRIMR + struct { + BITS HSITRIM : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // HSITRIMR bitfield + + /// register _CLK_HSITRIMR reset value + #define sfr_CLK_HSITRIMR_RESET_VALUE ((uint8_t) 0x00) + + } HSITRIMR; + + + /** SWIM clock control register (SWIMCCR at 0x50cd) */ + union { + + /// bytewise access to SWIMCCR + uint8_t byte; + + /// bitwise access to register SWIMCCR + struct { + BITS SWIMCLK : 1; // bit 0 + BITS : 7; // 7 bits + }; // SWIMCCR bitfield + + /// register _CLK_SWIMCCR reset value + #define sfr_CLK_SWIMCCR_RESET_VALUE ((uint8_t) 0x00) + + } SWIMCCR; + +} CLK_t; + +/// access to CLK SFR registers +#define sfr_CLK (*((CLK_t*) 0x50c0)) + + +//------------------------ +// Module CPU +//------------------------ + +/** struct containing CPU module registers */ +typedef struct { + + /** Accumulator (A at 0x7f00) */ + union { + + /// bytewise access to A + uint8_t byte; + + /// skip bitwise access to register A + + /// register _CPU_A reset value + #define sfr_CPU_A_RESET_VALUE ((uint8_t) 0x00) + + } A; + + + /** Program counter extended (PCE at 0x7f01) */ + union { + + /// bytewise access to PCE + uint8_t byte; + + /// skip bitwise access to register PCE + + /// register _CPU_PCE reset value + #define sfr_CPU_PCE_RESET_VALUE ((uint8_t) 0x00) + + } PCE; + + + /** Program counter high (PCH at 0x7f02) */ + union { + + /// bytewise access to PCH + uint8_t byte; + + /// skip bitwise access to register PCH + + /// register _CPU_PCH reset value + #define sfr_CPU_PCH_RESET_VALUE ((uint8_t) 0x00) + + } PCH; + + + /** Program counter low (PCL at 0x7f03) */ + union { + + /// bytewise access to PCL + uint8_t byte; + + /// skip bitwise access to register PCL + + /// register _CPU_PCL reset value + #define sfr_CPU_PCL_RESET_VALUE ((uint8_t) 0x00) + + } PCL; + + + /** X index register high (XH at 0x7f04) */ + union { + + /// bytewise access to XH + uint8_t byte; + + /// skip bitwise access to register XH + + /// register _CPU_XH reset value + #define sfr_CPU_XH_RESET_VALUE ((uint8_t) 0x00) + + } XH; + + + /** X index register low (XL at 0x7f05) */ + union { + + /// bytewise access to XL + uint8_t byte; + + /// skip bitwise access to register XL + + /// register _CPU_XL reset value + #define sfr_CPU_XL_RESET_VALUE ((uint8_t) 0x00) + + } XL; + + + /** Y index register high (YH at 0x7f06) */ + union { + + /// bytewise access to YH + uint8_t byte; + + /// skip bitwise access to register YH + + /// register _CPU_YH reset value + #define sfr_CPU_YH_RESET_VALUE ((uint8_t) 0x00) + + } YH; + + + /** Y index register low (YL at 0x7f07) */ + union { + + /// bytewise access to YL + uint8_t byte; + + /// skip bitwise access to register YL + + /// register _CPU_YL reset value + #define sfr_CPU_YL_RESET_VALUE ((uint8_t) 0x00) + + } YL; + + + /** Stack pointer high (SPH at 0x7f08) */ + union { + + /// bytewise access to SPH + uint8_t byte; + + /// skip bitwise access to register SPH + + /// register _CPU_SPH reset value + #define sfr_CPU_SPH_RESET_VALUE ((uint8_t) 0x07) + + } SPH; + + + /** Stack pointer low (SPL at 0x7f09) */ + union { + + /// bytewise access to SPL + uint8_t byte; + + /// skip bitwise access to register SPL + + /// register _CPU_SPL reset value + #define sfr_CPU_SPL_RESET_VALUE ((uint8_t) 0xFF) + + } SPL; + + + /** Condition code register (CCR at 0x7f0a) */ + union { + + /// bytewise access to CCR + uint8_t byte; + + /// bitwise access to register CCR + struct { + BITS C : 1; // bit 0 + BITS Z : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS I0 : 1; // bit 3 + BITS H : 1; // bit 4 + BITS I1 : 1; // bit 5 + BITS : 1; // 1 bit + BITS V : 1; // bit 7 + }; // CCR bitfield + + /// register _CPU_CCR reset value + #define sfr_CPU_CCR_RESET_VALUE ((uint8_t) 0x28) + + } CCR; + + + /// Reserved register (85B) + uint8_t Reserved_1[85]; + + + /** Global configuration register (CFG_GCR at 0x7f60) */ + union { + + /// bytewise access to CFG_GCR + uint8_t byte; + + /// bitwise access to register CFG_GCR + struct { + BITS SWO : 1; // bit 0 + BITS AL : 1; // bit 1 + BITS : 6; // 6 bits + }; // CFG_GCR bitfield + + /// register _CPU_CFG_GCR reset value + #define sfr_CPU_CFG_GCR_RESET_VALUE ((uint8_t) 0x00) + + } CFG_GCR; + +} CPU_t; + +/// access to CPU SFR registers +#define sfr_CPU (*((CPU_t*) 0x7f00)) + + +//------------------------ +// Module DM +//------------------------ + +/** struct containing DM module registers */ +typedef struct { + + /** DM breakpoint 1 register extended byte (BK1RE at 0x7f90) */ + union { + + /// bytewise access to BK1RE + uint8_t byte; + + /// skip bitwise access to register BK1RE + + /// register _DM_BK1RE reset value + #define sfr_DM_BK1RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RE; + + + /** DM breakpoint 1 register high byte (BK1RH at 0x7f91) */ + union { + + /// bytewise access to BK1RH + uint8_t byte; + + /// skip bitwise access to register BK1RH + + /// register _DM_BK1RH reset value + #define sfr_DM_BK1RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RH; + + + /** DM breakpoint 1 register low byte (BK1RL at 0x7f92) */ + union { + + /// bytewise access to BK1RL + uint8_t byte; + + /// skip bitwise access to register BK1RL + + /// register _DM_BK1RL reset value + #define sfr_DM_BK1RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RL; + + + /** DM breakpoint 2 register extended byte (BK2RE at 0x7f93) */ + union { + + /// bytewise access to BK2RE + uint8_t byte; + + /// skip bitwise access to register BK2RE + + /// register _DM_BK2RE reset value + #define sfr_DM_BK2RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RE; + + + /** DM breakpoint 2 register high byte (BK2RH at 0x7f94) */ + union { + + /// bytewise access to BK2RH + uint8_t byte; + + /// skip bitwise access to register BK2RH + + /// register _DM_BK2RH reset value + #define sfr_DM_BK2RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RH; + + + /** DM breakpoint 2 register low byte (BK2RL at 0x7f95) */ + union { + + /// bytewise access to BK2RL + uint8_t byte; + + /// skip bitwise access to register BK2RL + + /// register _DM_BK2RL reset value + #define sfr_DM_BK2RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RL; + + + /** DM debug module control register 1 (CR1 at 0x7f96) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// skip bitwise access to register CR1 + + /// register _DM_CR1 reset value + #define sfr_DM_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** DM debug module control register 2 (CR2 at 0x7f97) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// skip bitwise access to register CR2 + + /// register _DM_CR2 reset value + #define sfr_DM_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** DM debug module control/status register 1 (CSR1 at 0x7f98) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// skip bitwise access to register CSR1 + + /// register _DM_CSR1 reset value + #define sfr_DM_CSR1_RESET_VALUE ((uint8_t) 0x10) + + } CSR1; + + + /** DM debug module control/status register 2 (CSR2 at 0x7f99) */ + union { + + /// bytewise access to CSR2 + uint8_t byte; + + /// skip bitwise access to register CSR2 + + /// register _DM_CSR2 reset value + #define sfr_DM_CSR2_RESET_VALUE ((uint8_t) 0x00) + + } CSR2; + + + /** DM enable function register (ENFCTR at 0x7f9a) */ + union { + + /// bytewise access to ENFCTR + uint8_t byte; + + /// skip bitwise access to register ENFCTR + + /// register _DM_ENFCTR reset value + #define sfr_DM_ENFCTR_RESET_VALUE ((uint8_t) 0xFF) + + } ENFCTR; + +} DM_t; + +/// access to DM SFR registers +#define sfr_DM (*((DM_t*) 0x7f90)) + + +//------------------------ +// Module FLASH +//------------------------ + +/** struct containing FLASH module registers */ +typedef struct { + + /** Flash control register 1 (CR1 at 0x505a) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS FIX : 1; // bit 0 + BITS IE : 1; // bit 1 + BITS AHALT : 1; // bit 2 + BITS HALT : 1; // bit 3 + BITS : 4; // 4 bits + }; // CR1 bitfield + + /// register _FLASH_CR1 reset value + #define sfr_FLASH_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Flash control register 2 (CR2 at 0x505b) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS FPRG : 1; // bit 4 + BITS ERASE : 1; // bit 5 + BITS WPRG : 1; // bit 6 + BITS OPT : 1; // bit 7 + }; // CR2 bitfield + + /// register _FLASH_CR2 reset value + #define sfr_FLASH_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** Flash complementary control register 2 (NCR2 at 0x505c) */ + union { + + /// bytewise access to NCR2 + uint8_t byte; + + /// bitwise access to register NCR2 + struct { + BITS NPRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS NFPRG : 1; // bit 4 + BITS NERASE : 1; // bit 5 + BITS NWPRG : 1; // bit 6 + BITS NOPT : 1; // bit 7 + }; // NCR2 bitfield + + /// register _FLASH_NCR2 reset value + #define sfr_FLASH_NCR2_RESET_VALUE ((uint8_t) 0xFF) + + } NCR2; + + + /** Flash protection register (FPR at 0x505d) */ + union { + + /// bytewise access to FPR + uint8_t byte; + + /// bitwise access to register FPR + struct { + BITS WPB0 : 1; // bit 0 + BITS WPB1 : 1; // bit 1 + BITS WPB2 : 1; // bit 2 + BITS WPB3 : 1; // bit 3 + BITS WPB4 : 1; // bit 4 + BITS WPB5 : 1; // bit 5 + BITS : 2; // 2 bits + }; // FPR bitfield + + /// register _FLASH_FPR reset value + #define sfr_FLASH_FPR_RESET_VALUE ((uint8_t) 0x00) + + } FPR; + + + /** Flash complementary protection register (NFPR at 0x505e) */ + union { + + /// bytewise access to NFPR + uint8_t byte; + + /// bitwise access to register NFPR + struct { + BITS NWPB0 : 1; // bit 0 + BITS NWPB1 : 1; // bit 1 + BITS NWPB2 : 1; // bit 2 + BITS NWPB3 : 1; // bit 3 + BITS NWPB4 : 1; // bit 4 + BITS NWPB5 : 1; // bit 5 + BITS : 2; // 2 bits + }; // NFPR bitfield + + /// register _FLASH_NFPR reset value + #define sfr_FLASH_NFPR_RESET_VALUE ((uint8_t) 0xFF) + + } NFPR; + + + /** Flash in-application programming status register (IAPSR at 0x505f) */ + union { + + /// bytewise access to IAPSR + uint8_t byte; + + /// bitwise access to register IAPSR + struct { + BITS WR_PG_DIS : 1; // bit 0 + BITS PUL : 1; // bit 1 + BITS EOP : 1; // bit 2 + BITS DUL : 1; // bit 3 + BITS : 2; // 2 bits + BITS HVOFF : 1; // bit 6 + BITS : 1; // 1 bit + }; // IAPSR bitfield + + /// register _FLASH_IAPSR reset value + #define sfr_FLASH_IAPSR_RESET_VALUE ((uint8_t) 0x00) + + } IAPSR; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** Flash program memory unprotection register (PUKR at 0x5062) */ + union { + + /// bytewise access to PUKR + uint8_t byte; + + /// bitwise access to register PUKR + struct { + BITS MASS_PRG : 8; // bits 0-7 + }; // PUKR bitfield + + /// register _FLASH_PUKR reset value + #define sfr_FLASH_PUKR_RESET_VALUE ((uint8_t) 0x00) + + } PUKR; + + + /// Reserved register (1B) + uint8_t Reserved_2[1]; + + + /** Data EEPROM unprotection register (DUKR at 0x5064) */ + union { + + /// bytewise access to DUKR + uint8_t byte; + + /// bitwise access to register DUKR + struct { + BITS MASS_DATA : 8; // bits 0-7 + }; // DUKR bitfield + + /// register _FLASH_DUKR reset value + #define sfr_FLASH_DUKR_RESET_VALUE ((uint8_t) 0x00) + + } DUKR; + +} FLASH_t; + +/// access to FLASH SFR registers +#define sfr_FLASH (*((FLASH_t*) 0x505a)) + + +//------------------------ +// Module I2C +//------------------------ + +/** struct containing I2C module registers */ +typedef struct { + + /** I2C control register 1 (CR1 at 0x5210) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PE : 1; // bit 0 + BITS : 5; // 5 bits + BITS ENGC : 1; // bit 6 + BITS NOSTRETCH : 1; // bit 7 + }; // CR1 bitfield + + /// register _I2C_CR1 reset value + #define sfr_I2C_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** I2C control register 2 (CR2 at 0x5211) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS START : 1; // bit 0 + BITS STOP : 1; // bit 1 + BITS ACK : 1; // bit 2 + BITS POS : 1; // bit 3 + BITS : 3; // 3 bits + BITS SWRST : 1; // bit 7 + }; // CR2 bitfield + + /// register _I2C_CR2 reset value + #define sfr_I2C_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** I2C frequency register (FREQR at 0x5212) */ + union { + + /// bytewise access to FREQR + uint8_t byte; + + /// bitwise access to register FREQR + struct { + BITS FREQ : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // FREQR bitfield + + /// register _I2C_FREQR reset value + #define sfr_I2C_FREQR_RESET_VALUE ((uint8_t) 0x00) + + } FREQR; + + + /** I2C Own address register low (OARL at 0x5213) */ + union { + + /// bytewise access to OARL + uint8_t byte; + + /// bitwise access to register OARL + struct { + BITS ADD0 : 1; // bit 0 + BITS ADD : 7; // bits 1-7 + }; // OARL bitfield + + /// register _I2C_OARL reset value + #define sfr_I2C_OARL_RESET_VALUE ((uint8_t) 0x00) + + } OARL; + + + /** I2C own address register high (OARH at 0x5214) */ + union { + + /// bytewise access to OARH + uint8_t byte; + + /// bitwise access to register OARH + struct { + BITS : 1; // 1 bit + BITS ADD : 2; // bits 1-2 + BITS : 3; // 3 bits + BITS ADDCONF : 1; // bit 6 + BITS ADDMODE : 1; // bit 7 + }; // OARH bitfield + + /// register _I2C_OARH reset value + #define sfr_I2C_OARH_RESET_VALUE ((uint8_t) 0x00) + + } OARH; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** I2C data register (DR at 0x5216) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _I2C_DR reset value + #define sfr_I2C_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** I2C status register 1 (SR1 at 0x5217) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS SB : 1; // bit 0 + BITS ADDR : 1; // bit 1 + BITS BTF : 1; // bit 2 + BITS ADD10 : 1; // bit 3 + BITS STOPF : 1; // bit 4 + BITS : 1; // 1 bit + BITS RXNE : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR1 bitfield + + /// register _I2C_SR1 reset value + #define sfr_I2C_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** I2C status register 2 (SR2 at 0x5218) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS BERR : 1; // bit 0 + BITS ARLO : 1; // bit 1 + BITS AF : 1; // bit 2 + BITS OVR : 1; // bit 3 + BITS : 1; // 1 bit + BITS WUFH : 1; // bit 5 + BITS : 2; // 2 bits + }; // SR2 bitfield + + /// register _I2C_SR2 reset value + #define sfr_I2C_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** I2C status register 3 (SR3 at 0x5219) */ + union { + + /// bytewise access to SR3 + uint8_t byte; + + /// bitwise access to register SR3 + struct { + BITS MSL : 1; // bit 0 + BITS BUSY : 1; // bit 1 + BITS TRA : 1; // bit 2 + BITS : 1; // 1 bit + BITS GENCALL : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR3 bitfield + + /// register _I2C_SR3 reset value + #define sfr_I2C_SR3_RESET_VALUE ((uint8_t) 0x00) + + } SR3; + + + /** I2C interrupt control register (ITR at 0x521a) */ + union { + + /// bytewise access to ITR + uint8_t byte; + + /// bitwise access to register ITR + struct { + BITS ITERREN : 1; // bit 0 + BITS ITEVTEN : 1; // bit 1 + BITS ITBUFEN : 1; // bit 2 + BITS : 5; // 5 bits + }; // ITR bitfield + + /// register _I2C_ITR reset value + #define sfr_I2C_ITR_RESET_VALUE ((uint8_t) 0x00) + + } ITR; + + + /** I2C clock control register low (CCRL at 0x521b) */ + union { + + /// bytewise access to CCRL + uint8_t byte; + + /// bitwise access to register CCRL + struct { + BITS CCR : 8; // bits 0-7 + }; // CCRL bitfield + + /// register _I2C_CCRL reset value + #define sfr_I2C_CCRL_RESET_VALUE ((uint8_t) 0x00) + + } CCRL; + + + /** I2C clock control register high (CCRH at 0x521c) */ + union { + + /// bytewise access to CCRH + uint8_t byte; + + /// bitwise access to register CCRH + struct { + BITS CCR : 4; // bits 0-3 + BITS : 2; // 2 bits + BITS DUTY : 1; // bit 6 + BITS F_S : 1; // bit 7 + }; // CCRH bitfield + + /// register _I2C_CCRH reset value + #define sfr_I2C_CCRH_RESET_VALUE ((uint8_t) 0x00) + + } CCRH; + + + /** I2C TRISE register (TRISER at 0x521d) */ + union { + + /// bytewise access to TRISER + uint8_t byte; + + /// bitwise access to register TRISER + struct { + BITS TRISE : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // TRISER bitfield + + /// register _I2C_TRISER reset value + #define sfr_I2C_TRISER_RESET_VALUE ((uint8_t) 0x02) + + } TRISER; + + + /** I2C packet error checking register (PECR at 0x521e) */ + union { + + /// bytewise access to PECR + uint8_t byte; + + /// bitwise access to register PECR + struct { + BITS PEC : 8; // bits 0-7 + }; // PECR bitfield + + /// register _I2C_PECR reset value + #define sfr_I2C_PECR_RESET_VALUE ((uint8_t) 0x00) + + } PECR; + +} I2C_t; + +/// access to I2C SFR registers +#define sfr_I2C (*((I2C_t*) 0x5210)) + + +//------------------------ +// Module ITC_EXTI +//------------------------ + +/** struct containing ITC_EXTI module registers */ +typedef struct { + + /** External interrupt control register 1 (CR1 at 0x50a0) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PAIS : 2; // bits 0-1 + BITS PBIS : 2; // bits 2-3 + BITS PCIS : 2; // bits 4-5 + BITS PDIS : 2; // bits 6-7 + }; // CR1 bitfield + + /// register _ITC_EXTI_CR1 reset value + #define sfr_ITC_EXTI_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** External interrupt control register 2 (CR2 at 0x50a1) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PEIS : 2; // bits 0-1 + BITS TLIS : 1; // bit 2 + BITS : 5; // 5 bits + }; // CR2 bitfield + + /// register _ITC_EXTI_CR2 reset value + #define sfr_ITC_EXTI_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + +} ITC_EXTI_t; + +/// access to ITC_EXTI SFR registers +#define sfr_ITC_EXTI (*((ITC_EXTI_t*) 0x50a0)) + + +//------------------------ +// Module ITC_SPR +//------------------------ + +/** struct containing ITC_SPR module registers */ +typedef struct { + + /** Interrupt software priority register 1 (SPR1 at 0x7f70) */ + union { + + /// bytewise access to SPR1 + uint8_t byte; + + /// bitwise access to register SPR1 + struct { + BITS VECT0SPR : 2; // bits 0-1 + BITS VECT1SPR : 2; // bits 2-3 + BITS VECT2SPR : 2; // bits 4-5 + BITS VECT3SPR : 2; // bits 6-7 + }; // SPR1 bitfield + + /// register _ITC_SPR_SPR1 reset value + #define sfr_ITC_SPR_SPR1_RESET_VALUE ((uint8_t) 0xFF) + + } SPR1; + + + /** Interrupt software priority register 2 (SPR2 at 0x7f71) */ + union { + + /// bytewise access to SPR2 + uint8_t byte; + + /// bitwise access to register SPR2 + struct { + BITS VECT4SPR : 2; // bits 0-1 + BITS VECT5SPR : 2; // bits 2-3 + BITS VECT6SPR : 2; // bits 4-5 + BITS VECT7SPR : 2; // bits 6-7 + }; // SPR2 bitfield + + /// register _ITC_SPR_SPR2 reset value + #define sfr_ITC_SPR_SPR2_RESET_VALUE ((uint8_t) 0xFF) + + } SPR2; + + + /** Interrupt software priority register 3 (SPR3 at 0x7f72) */ + union { + + /// bytewise access to SPR3 + uint8_t byte; + + /// bitwise access to register SPR3 + struct { + BITS VECT8SPR : 2; // bits 0-1 + BITS VECT9SPR : 2; // bits 2-3 + BITS VECT10SPR : 2; // bits 4-5 + BITS VECT11SPR : 2; // bits 6-7 + }; // SPR3 bitfield + + /// register _ITC_SPR_SPR3 reset value + #define sfr_ITC_SPR_SPR3_RESET_VALUE ((uint8_t) 0xFF) + + } SPR3; + + + /** Interrupt software priority register 4 (SPR4 at 0x7f73) */ + union { + + /// bytewise access to SPR4 + uint8_t byte; + + /// bitwise access to register SPR4 + struct { + BITS VECT12SPR : 2; // bits 0-1 + BITS VECT13SPR : 2; // bits 2-3 + BITS VECT14SPR : 2; // bits 4-5 + BITS VECT15SPR : 2; // bits 6-7 + }; // SPR4 bitfield + + /// register _ITC_SPR_SPR4 reset value + #define sfr_ITC_SPR_SPR4_RESET_VALUE ((uint8_t) 0xFF) + + } SPR4; + + + /** Interrupt software priority register 5 (SPR5 at 0x7f74) */ + union { + + /// bytewise access to SPR5 + uint8_t byte; + + /// bitwise access to register SPR5 + struct { + BITS VECT16SPR : 2; // bits 0-1 + BITS VECT17SPR : 2; // bits 2-3 + BITS VECT18SPR : 2; // bits 4-5 + BITS VECT19SPR : 2; // bits 6-7 + }; // SPR5 bitfield + + /// register _ITC_SPR_SPR5 reset value + #define sfr_ITC_SPR_SPR5_RESET_VALUE ((uint8_t) 0xFF) + + } SPR5; + + + /** Interrupt software priority register 6 (SPR6 at 0x7f75) */ + union { + + /// bytewise access to SPR6 + uint8_t byte; + + /// bitwise access to register SPR6 + struct { + BITS VECT20SPR : 2; // bits 0-1 + BITS VECT21SPR : 2; // bits 2-3 + BITS VECT22SPR : 2; // bits 4-5 + BITS VECT23SPR : 2; // bits 6-7 + }; // SPR6 bitfield + + /// register _ITC_SPR_SPR6 reset value + #define sfr_ITC_SPR_SPR6_RESET_VALUE ((uint8_t) 0xFF) + + } SPR6; + + + /** Interrupt software priority register 7 (SPR7 at 0x7f76) */ + union { + + /// bytewise access to SPR7 + uint8_t byte; + + /// bitwise access to register SPR7 + struct { + BITS VECT24SPR : 2; // bits 0-1 + BITS VECT25SPR : 2; // bits 2-3 + BITS VECT26SPR : 2; // bits 4-5 + BITS VECT27SPR : 2; // bits 6-7 + }; // SPR7 bitfield + + /// register _ITC_SPR_SPR7 reset value + #define sfr_ITC_SPR_SPR7_RESET_VALUE ((uint8_t) 0xFF) + + } SPR7; + + + /** Interrupt software priority register 8 (SPR8 at 0x7f77) */ + union { + + /// bytewise access to SPR8 + uint8_t byte; + + /// bitwise access to register SPR8 + struct { + BITS VECT28SPR : 2; // bits 0-1 + BITS VECT29SPR : 2; // bits 2-3 + BITS : 4; // 4 bits + }; // SPR8 bitfield + + /// register _ITC_SPR_SPR8 reset value + #define sfr_ITC_SPR_SPR8_RESET_VALUE ((uint8_t) 0xFF) + + } SPR8; + +} ITC_SPR_t; + +/// access to ITC_SPR SFR registers +#define sfr_ITC_SPR (*((ITC_SPR_t*) 0x7f70)) + + +//------------------------ +// Module IWDG +//------------------------ + +/** struct containing IWDG module registers */ +typedef struct { + + /** IWDG key register (KR at 0x50e0) */ + union { + + /// bytewise access to KR + uint8_t byte; + + /// bitwise access to register KR + struct { + BITS KEY : 8; // bits 0-7 + }; // KR bitfield + + /// register _IWDG_KR reset value + #define sfr_IWDG_KR_RESET_VALUE ((uint8_t) 0x00) + + } KR; + + + /** IWDG prescaler register (PR at 0x50e1) */ + union { + + /// bytewise access to PR + uint8_t byte; + + /// bitwise access to register PR + struct { + BITS PR : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PR bitfield + + /// register _IWDG_PR reset value + #define sfr_IWDG_PR_RESET_VALUE ((uint8_t) 0x00) + + } PR; + + + /** IWDG reload register (RLR at 0x50e2) */ + union { + + /// bytewise access to RLR + uint8_t byte; + + /// bitwise access to register RLR + struct { + BITS RL : 8; // bits 0-7 + }; // RLR bitfield + + /// register _IWDG_RLR reset value + #define sfr_IWDG_RLR_RESET_VALUE ((uint8_t) 0xFF) + + } RLR; + +} IWDG_t; + +/// access to IWDG SFR registers +#define sfr_IWDG (*((IWDG_t*) 0x50e0)) + + +//------------------------ +// Module OPT +//------------------------ + +/** struct containing OPT module registers */ +typedef struct { + + /** Read-out protection (ROP) (OPT0 at 0x4800) */ + union { + + /// bytewise access to OPT0 + uint8_t byte; + + /// skip bitwise access to register OPT0 + + /// register _OPT_OPT0 reset value + #define sfr_OPT_OPT0_RESET_VALUE ((uint8_t) 0x00) + + } OPT0; + + + /** User boot code (UBC) (OPT1 at 0x4801) */ + union { + + /// bytewise access to OPT1 + uint8_t byte; + + /// skip bitwise access to register OPT1 + + /// register _OPT_OPT1 reset value + #define sfr_OPT_OPT1_RESET_VALUE ((uint8_t) 0x00) + + } OPT1; + + + /** User boot code (UBC) (complementary byte) (NOPT1 at 0x4802) */ + union { + + /// bytewise access to NOPT1 + uint8_t byte; + + /// skip bitwise access to register NOPT1 + + /// register _OPT_NOPT1 reset value + #define sfr_OPT_NOPT1_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT1; + + + /** Alternate function remapping (AFR) (OPT2 at 0x4803) */ + union { + + /// bytewise access to OPT2 + uint8_t byte; + + /// skip bitwise access to register OPT2 + + /// register _OPT_OPT2 reset value + #define sfr_OPT_OPT2_RESET_VALUE ((uint8_t) 0x00) + + } OPT2; + + + /** Alternate function remapping (AFR) (complementary byte) (NOPT2 at 0x4804) */ + union { + + /// bytewise access to NOPT2 + uint8_t byte; + + /// skip bitwise access to register NOPT2 + + /// register _OPT_NOPT2 reset value + #define sfr_OPT_NOPT2_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT2; + + + /** Misc. option (OPT3 at 0x4805) */ + union { + + /// bytewise access to OPT3 + uint8_t byte; + + /// skip bitwise access to register OPT3 + + /// register _OPT_OPT3 reset value + #define sfr_OPT_OPT3_RESET_VALUE ((uint8_t) 0x00) + + } OPT3; + + + /** Misc. option (complementary byte) (NOPT3 at 0x4806) */ + union { + + /// bytewise access to NOPT3 + uint8_t byte; + + /// skip bitwise access to register NOPT3 + + /// register _OPT_NOPT3 reset value + #define sfr_OPT_NOPT3_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT3; + + + /** Clock option (OPT4 at 0x4807) */ + union { + + /// bytewise access to OPT4 + uint8_t byte; + + /// skip bitwise access to register OPT4 + + /// register _OPT_OPT4 reset value + #define sfr_OPT_OPT4_RESET_VALUE ((uint8_t) 0x00) + + } OPT4; + + + /** Clock option (complementary byte) (NOPT4 at 0x4808) */ + union { + + /// bytewise access to NOPT4 + uint8_t byte; + + /// skip bitwise access to register NOPT4 + + /// register _OPT_NOPT4 reset value + #define sfr_OPT_NOPT4_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT4; + + + /** HSE clock startup (OPT5 at 0x4809) */ + union { + + /// bytewise access to OPT5 + uint8_t byte; + + /// skip bitwise access to register OPT5 + + /// register _OPT_OPT5 reset value + #define sfr_OPT_OPT5_RESET_VALUE ((uint8_t) 0x00) + + } OPT5; + + + /** HSE clock startup (complementary byte) (NOPT5 at 0x480a) */ + union { + + /// bytewise access to NOPT5 + uint8_t byte; + + /// skip bitwise access to register NOPT5 + + /// register _OPT_NOPT5 reset value + #define sfr_OPT_NOPT5_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT5; + + + /// Reserved register (115B) + uint8_t Reserved_1[115]; + + + /** Bootloader (OPTBL at 0x487e) */ + union { + + /// bytewise access to OPTBL + uint8_t byte; + + /// skip bitwise access to register OPTBL + + /// register _OPT_OPTBL reset value + #define sfr_OPT_OPTBL_RESET_VALUE ((uint8_t) 0x00) + + } OPTBL; + + + /** Bootloader (complementary byte) (NOPTBL at 0x487f) */ + union { + + /// bytewise access to NOPTBL + uint8_t byte; + + /// skip bitwise access to register NOPTBL + + /// register _OPT_NOPTBL reset value + #define sfr_OPT_NOPTBL_RESET_VALUE ((uint8_t) 0xFF) + + } NOPTBL; + +} OPT_t; + +/// access to OPT SFR registers +#define sfr_OPT (*((OPT_t*) 0x4800)) + + +//------------------------ +// Module PORT +//------------------------ + +/** struct containing PORTA module registers */ +typedef struct { + + /** Port A data output latch register (ODR at 0x5000) */ + union { + + /// bytewise access to ODR + uint8_t byte; + + /// bitwise access to register ODR + struct { + BITS ODR0 : 1; // bit 0 + BITS ODR1 : 1; // bit 1 + BITS ODR2 : 1; // bit 2 + BITS ODR3 : 1; // bit 3 + BITS ODR4 : 1; // bit 4 + BITS ODR5 : 1; // bit 5 + BITS ODR6 : 1; // bit 6 + BITS ODR7 : 1; // bit 7 + }; // ODR bitfield + + /// register _PORT_ODR reset value + #define sfr_PORT_ODR_RESET_VALUE ((uint8_t) 0x00) + + } ODR; + + + /** Port A input pin value register (IDR at 0x5001) */ + union { + + /// bytewise access to IDR + uint8_t byte; + + /// bitwise access to register IDR + struct { + BITS IDR0 : 1; // bit 0 + BITS IDR1 : 1; // bit 1 + BITS IDR2 : 1; // bit 2 + BITS IDR3 : 1; // bit 3 + BITS IDR4 : 1; // bit 4 + BITS IDR5 : 1; // bit 5 + BITS IDR6 : 1; // bit 6 + BITS IDR7 : 1; // bit 7 + }; // IDR bitfield + + /// register _PORT_IDR reset value + #define sfr_PORT_IDR_RESET_VALUE ((uint8_t) 0x00) + + } IDR; + + + /** Port A data direction register (DDR at 0x5002) */ + union { + + /// bytewise access to DDR + uint8_t byte; + + /// bitwise access to register DDR + struct { + BITS DDR0 : 1; // bit 0 + BITS DDR1 : 1; // bit 1 + BITS DDR2 : 1; // bit 2 + BITS DDR3 : 1; // bit 3 + BITS DDR4 : 1; // bit 4 + BITS DDR5 : 1; // bit 5 + BITS DDR6 : 1; // bit 6 + BITS DDR7 : 1; // bit 7 + }; // DDR bitfield + + /// register _PORT_DDR reset value + #define sfr_PORT_DDR_RESET_VALUE ((uint8_t) 0x00) + + } DDR; + + + /** Port A control register 1 (CR1 at 0x5003) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS C10 : 1; // bit 0 + BITS C11 : 1; // bit 1 + BITS C12 : 1; // bit 2 + BITS C13 : 1; // bit 3 + BITS C14 : 1; // bit 4 + BITS C15 : 1; // bit 5 + BITS C16 : 1; // bit 6 + BITS C17 : 1; // bit 7 + }; // CR1 bitfield + + /// register _PORT_CR1 reset value + #define sfr_PORT_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Port A control register 2 (CR2 at 0x5004) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS C20 : 1; // bit 0 + BITS C21 : 1; // bit 1 + BITS C22 : 1; // bit 2 + BITS C23 : 1; // bit 3 + BITS C24 : 1; // bit 4 + BITS C25 : 1; // bit 5 + BITS C26 : 1; // bit 6 + BITS C27 : 1; // bit 7 + }; // CR2 bitfield + + /// register _PORT_CR2 reset value + #define sfr_PORT_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + +} PORT_t; + +/// access to PORTA SFR registers +#define sfr_PORTA (*((PORT_t*) 0x5000)) + + +/// access to PORTB SFR registers +#define sfr_PORTB (*((PORT_t*) 0x5005)) + + +/// access to PORTC SFR registers +#define sfr_PORTC (*((PORT_t*) 0x500a)) + + +/// access to PORTD SFR registers +#define sfr_PORTD (*((PORT_t*) 0x500f)) + + +/// access to PORTE SFR registers +#define sfr_PORTE (*((PORT_t*) 0x5014)) + + +/// access to PORTF SFR registers +#define sfr_PORTF (*((PORT_t*) 0x5019)) + + +/// access to PORTG SFR registers +#define sfr_PORTG (*((PORT_t*) 0x501e)) + + +/// access to PORTH SFR registers +#define sfr_PORTH (*((PORT_t*) 0x5023)) + + +/// access to PORTI SFR registers +#define sfr_PORTI (*((PORT_t*) 0x5028)) + + +//------------------------ +// Module RST +//------------------------ + +/** struct containing RST module registers */ +typedef struct { + + /** Reset status register (SR at 0x50b3) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS WWDGF : 1; // bit 0 + BITS IWDGF : 1; // bit 1 + BITS ILLOPF : 1; // bit 2 + BITS SWIMF : 1; // bit 3 + BITS EMCF : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR bitfield + + /// register _RST_SR reset value + #define sfr_RST_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + +} RST_t; + +/// access to RST SFR registers +#define sfr_RST (*((RST_t*) 0x50b3)) + + +//------------------------ +// Module SPI +//------------------------ + +/** struct containing SPI module registers */ +typedef struct { + + /** SPI control register 1 (CR1 at 0x5200) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CPHA : 1; // bit 0 + BITS CPOL : 1; // bit 1 + BITS MSTR : 1; // bit 2 + BITS BR : 3; // bits 3-5 + BITS SPE : 1; // bit 6 + BITS LSBFIRST : 1; // bit 7 + }; // CR1 bitfield + + /// register _SPI_CR1 reset value + #define sfr_SPI_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** SPI control register 2 (CR2 at 0x5201) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SSI : 1; // bit 0 + BITS SSM : 1; // bit 1 + BITS RXONLY : 1; // bit 2 + BITS : 1; // 1 bit + BITS CRCNEXT : 1; // bit 4 + BITS CECEN : 1; // bit 5 + BITS BDOE : 1; // bit 6 + BITS BDM : 1; // bit 7 + }; // CR2 bitfield + + /// register _SPI_CR2 reset value + #define sfr_SPI_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** SPI interrupt control register (ICR at 0x5202) */ + union { + + /// bytewise access to ICR + uint8_t byte; + + /// bitwise access to register ICR + struct { + BITS : 4; // 4 bits + BITS WKIE : 1; // bit 4 + BITS ERRIE : 1; // bit 5 + BITS RXIE : 1; // bit 6 + BITS TXIE : 1; // bit 7 + }; // ICR bitfield + + /// register _SPI_ICR reset value + #define sfr_SPI_ICR_RESET_VALUE ((uint8_t) 0x00) + + } ICR; + + + /** SPI status register (SR at 0x5203) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS RXNE : 1; // bit 0 + BITS TXE : 1; // bit 1 + BITS : 1; // 1 bit + BITS WKUP : 1; // bit 3 + BITS CRCERR : 1; // bit 4 + BITS MODF : 1; // bit 5 + BITS OVR : 1; // bit 6 + BITS BSY : 1; // bit 7 + }; // SR bitfield + + /// register _SPI_SR reset value + #define sfr_SPI_SR_RESET_VALUE ((uint8_t) 0x02) + + } SR; + + + /** SPI data register (DR at 0x5204) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _SPI_DR reset value + #define sfr_SPI_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** SPI CRC polynomial register (CRCPR at 0x5205) */ + union { + + /// bytewise access to CRCPR + uint8_t byte; + + /// bitwise access to register CRCPR + struct { + BITS CRCPOLY : 8; // bits 0-7 + }; // CRCPR bitfield + + /// register _SPI_CRCPR reset value + #define sfr_SPI_CRCPR_RESET_VALUE ((uint8_t) 0x07) + + } CRCPR; + + + /** SPI Rx CRC register (RXCRCR at 0x5206) */ + union { + + /// bytewise access to RXCRCR + uint8_t byte; + + /// bitwise access to register RXCRCR + struct { + BITS RXCRC : 8; // bits 0-7 + }; // RXCRCR bitfield + + /// register _SPI_RXCRCR reset value + #define sfr_SPI_RXCRCR_RESET_VALUE ((uint8_t) 0xFF) + + } RXCRCR; + + + /** SPI Tx CRC register (TXCRCR at 0x5207) */ + union { + + /// bytewise access to TXCRCR + uint8_t byte; + + /// bitwise access to register TXCRCR + struct { + BITS TXCRC : 8; // bits 0-7 + }; // TXCRCR bitfield + + /// register _SPI_TXCRCR reset value + #define sfr_SPI_TXCRCR_RESET_VALUE ((uint8_t) 0xFF) + + } TXCRCR; + +} SPI_t; + +/// access to SPI SFR registers +#define sfr_SPI (*((SPI_t*) 0x5200)) + + +//------------------------ +// Module SWIM +//------------------------ + +/** struct containing SWIM module registers */ +typedef struct { + + /** SWIM control status register (CSR at 0x7f80) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// skip bitwise access to register CSR + + /// register _SWIM_CSR reset value + #define sfr_SWIM_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + +} SWIM_t; + +/// access to SWIM SFR registers +#define sfr_SWIM (*((SWIM_t*) 0x7f80)) + + +//------------------------ +// Module TIM1 +//------------------------ + +/** struct containing TIM1 module registers */ +typedef struct { + + /** TIM1 control register 1 (CR1 at 0x5250) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS DIR : 1; // bit 4 + BITS CMS : 2; // bits 5-6 + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM1_CR1 reset value + #define sfr_TIM1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM1 control register 2 (CR2 at 0x5251) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS CCPG : 1; // bit 0 + BITS : 1; // 1 bit + BITS COMS : 1; // bit 2 + BITS : 1; // 1 bit + BITS MMS : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _TIM1_CR2 reset value + #define sfr_TIM1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** TIM1 slave mode control register (SMCR at 0x5252) */ + union { + + /// bytewise access to SMCR + uint8_t byte; + + /// bitwise access to register SMCR + struct { + BITS SMS : 3; // bits 0-2 + BITS : 1; // 1 bit + BITS TS : 3; // bits 4-6 + BITS MSM : 1; // bit 7 + }; // SMCR bitfield + + /// register _TIM1_SMCR reset value + #define sfr_TIM1_SMCR_RESET_VALUE ((uint8_t) 0x00) + + } SMCR; + + + /** TIM1 external trigger register (ETR at 0x5253) */ + union { + + /// bytewise access to ETR + uint8_t byte; + + /// bitwise access to register ETR + struct { + BITS ETF : 4; // bits 0-3 + BITS ETPS : 2; // bits 4-5 + BITS ECE : 1; // bit 6 + BITS ETP : 1; // bit 7 + }; // ETR bitfield + + /// register _TIM1_ETR reset value + #define sfr_TIM1_ETR_RESET_VALUE ((uint8_t) 0x00) + + } ETR; + + + /** TIM1 interrupt enable register (IER at 0x5254) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS CC4IE : 1; // bit 4 + BITS COMIE : 1; // bit 5 + BITS TIE : 1; // bit 6 + BITS BIE : 1; // bit 7 + }; // IER bitfield + + /// register _TIM1_IER reset value + #define sfr_TIM1_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM1 status register 1 (SR1 at 0x5255) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS CC4IF : 1; // bit 4 + BITS COMIF : 1; // bit 5 + BITS TIF : 1; // bit 6 + BITS BIF : 1; // bit 7 + }; // SR1 bitfield + + /// register _TIM1_SR1 reset value + #define sfr_TIM1_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM1 status register 2 (SR2 at 0x5256) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS CC4OF : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR2 bitfield + + /// register _TIM1_SR2 reset value + #define sfr_TIM1_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM1 event generation register (EGR at 0x5257) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS CC4G : 1; // bit 4 + BITS COMG : 1; // bit 5 + BITS TG : 1; // bit 6 + BITS BG : 1; // bit 7 + }; // EGR bitfield + + /// register _TIM1_EGR reset value + #define sfr_TIM1_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM1 capture/compare mode register 1 (CCMR1 at 0x5258) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS OC1FE : 1; // bit 2 + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS OC1CE : 1; // bit 7 + }; // CCMR1 bitfield + + /// register _TIM1_CCMR1 reset value + #define sfr_TIM1_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM1 capture/compare mode register 2 (CCMR2 at 0x5259) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS OC2FE : 1; // bit 2 + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS OC2CE : 1; // bit 7 + }; // CCMR2 bitfield + + /// register _TIM1_CCMR2 reset value + #define sfr_TIM1_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM1 capture/compare mode register 3 (CCMR3 at 0x525a) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS OC3FE : 1; // bit 2 + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS OC3CE : 1; // bit 7 + }; // CCMR3 bitfield + + /// register _TIM1_CCMR3 reset value + #define sfr_TIM1_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM1 capture/compare mode register 4 (CCMR4 at 0x525b) */ + union { + + /// bytewise access to CCMR4 + uint8_t byte; + + /// bitwise access to register CCMR4 + struct { + BITS CC4S : 2; // bits 0-1 + BITS OC4FE : 1; // bit 2 + BITS OC4PE : 1; // bit 3 + BITS OC4M : 3; // bits 4-6 + BITS OC4CE : 1; // bit 7 + }; // CCMR4 bitfield + + /// register _TIM1_CCMR4 reset value + #define sfr_TIM1_CCMR4_RESET_VALUE ((uint8_t) 0x00) + + } CCMR4; + + + /** TIM1 capture/compare enable register 1 (CCER1 at 0x525c) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS CC1NE : 1; // bit 2 + BITS CC1NP : 1; // bit 3 + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS CC2NE : 1; // bit 6 + BITS CC2NP : 1; // bit 7 + }; // CCER1 bitfield + + /// register _TIM1_CCER1 reset value + #define sfr_TIM1_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM1 capture/compare enable register 2 (CCER2 at 0x525d) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS CC3NE : 1; // bit 2 + BITS CC3NP : 1; // bit 3 + BITS CC4E : 1; // bit 4 + BITS CC4P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER2 bitfield + + /// register _TIM1_CCER2 reset value + #define sfr_TIM1_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM1 counter high (CNTRH at 0x525e) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM1_CNTRH reset value + #define sfr_TIM1_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM1 counter low (CNTRL at 0x525f) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM1_CNTRL reset value + #define sfr_TIM1_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM1 prescaler register high (PSCRH at 0x5260) */ + union { + + /// bytewise access to PSCRH + uint8_t byte; + + /// bitwise access to register PSCRH + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCRH bitfield + + /// register _TIM1_PSCRH reset value + #define sfr_TIM1_PSCRH_RESET_VALUE ((uint8_t) 0x00) + + } PSCRH; + + + /** TIM1 prescaler register low (PSCRL at 0x5261) */ + union { + + /// bytewise access to PSCRL + uint8_t byte; + + /// bitwise access to register PSCRL + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCRL bitfield + + /// register _TIM1_PSCRL reset value + #define sfr_TIM1_PSCRL_RESET_VALUE ((uint8_t) 0x00) + + } PSCRL; + + + /** TIM1 auto-reload register high (ARRH at 0x5262) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM1_ARRH reset value + #define sfr_TIM1_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM1 auto-reload register low (ARRL at 0x5263) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM1_ARRL reset value + #define sfr_TIM1_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM1 repetition counter register (RCR at 0x5264) */ + union { + + /// bytewise access to RCR + uint8_t byte; + + /// bitwise access to register RCR + struct { + BITS REP : 8; // bits 0-7 + }; // RCR bitfield + + /// register _TIM1_RCR reset value + #define sfr_TIM1_RCR_RESET_VALUE ((uint8_t) 0x00) + + } RCR; + + + /** TIM1 capture/compare register 1 high (CCR1H at 0x5265) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM1_CCR1H reset value + #define sfr_TIM1_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM1 capture/compare register 1 low (CCR1L at 0x5266) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM1_CCR1L reset value + #define sfr_TIM1_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM1 capture/compare register 2 high (CCR2H at 0x5267) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM1_CCR2H reset value + #define sfr_TIM1_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM1 capture/compare register 2 low (CCR2L at 0x5268) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM1_CCR2L reset value + #define sfr_TIM1_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM1 capture/compare register 3 high (CCR3H at 0x5269) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3H bitfield + + /// register _TIM1_CCR3H reset value + #define sfr_TIM1_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM1 capture/compare register 3 low (CCR3L at 0x526a) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3L bitfield + + /// register _TIM1_CCR3L reset value + #define sfr_TIM1_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + + + /** TIM1 capture/compare register 4 high (CCR4H at 0x526b) */ + union { + + /// bytewise access to CCR4H + uint8_t byte; + + /// bitwise access to register CCR4H + struct { + BITS CCR4 : 8; // bits 0-7 + }; // CCR4H bitfield + + /// register _TIM1_CCR4H reset value + #define sfr_TIM1_CCR4H_RESET_VALUE ((uint8_t) 0x00) + + } CCR4H; + + + /** TIM1 capture/compare register 4 low (CCR4L at 0x526c) */ + union { + + /// bytewise access to CCR4L + uint8_t byte; + + /// bitwise access to register CCR4L + struct { + BITS CCR4 : 8; // bits 0-7 + }; // CCR4L bitfield + + /// register _TIM1_CCR4L reset value + #define sfr_TIM1_CCR4L_RESET_VALUE ((uint8_t) 0x00) + + } CCR4L; + + + /** TIM1 break register (BKR at 0x526d) */ + union { + + /// bytewise access to BKR + uint8_t byte; + + /// bitwise access to register BKR + struct { + BITS LOCK : 2; // bits 0-1 + BITS OSSI : 1; // bit 2 + BITS OSSR : 1; // bit 3 + BITS BKE : 1; // bit 4 + BITS BKP : 1; // bit 5 + BITS AOE : 1; // bit 6 + BITS MOE : 1; // bit 7 + }; // BKR bitfield + + /// register _TIM1_BKR reset value + #define sfr_TIM1_BKR_RESET_VALUE ((uint8_t) 0x00) + + } BKR; + + + /** TIM1 dead-time register (DTR at 0x526e) */ + union { + + /// bytewise access to DTR + uint8_t byte; + + /// bitwise access to register DTR + struct { + BITS DTG : 8; // bits 0-7 + }; // DTR bitfield + + /// register _TIM1_DTR reset value + #define sfr_TIM1_DTR_RESET_VALUE ((uint8_t) 0x00) + + } DTR; + + + /** TIM1 output idle state register (OISR at 0x526f) */ + union { + + /// bytewise access to OISR + uint8_t byte; + + /// bitwise access to register OISR + struct { + BITS OIS1 : 1; // bit 0 + BITS OIS1N : 1; // bit 1 + BITS OIS2 : 1; // bit 2 + BITS OIS2N : 1; // bit 3 + BITS OIS3 : 1; // bit 4 + BITS OIS3N : 1; // bit 5 + BITS OIS4 : 1; // bit 6 + BITS : 1; // 1 bit + }; // OISR bitfield + + /// register _TIM1_OISR reset value + #define sfr_TIM1_OISR_RESET_VALUE ((uint8_t) 0x00) + + } OISR; + +} TIM1_t; + +/// access to TIM1 SFR registers +#define sfr_TIM1 (*((TIM1_t*) 0x5250)) + + +//------------------------ +// Module TIM2 +//------------------------ + +/** struct containing TIM2 module registers */ +typedef struct { + + /** TIM2 control register 1 (CR1 at 0x5300) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM2_CR1 reset value + #define sfr_TIM2_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM2 interrupt enable register (IER at 0x5301) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM2_IER reset value + #define sfr_TIM2_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM2 status register 1 (SR1 at 0x5302) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR1 bitfield + + /// register _TIM2_SR1 reset value + #define sfr_TIM2_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM2 status register 2 (SR2 at 0x5303) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SR2 bitfield + + /// register _TIM2_SR2 reset value + #define sfr_TIM2_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM2 event generation register (EGR at 0x5304) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS : 2; // 2 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM2_EGR reset value + #define sfr_TIM2_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM2 capture/compare mode register 1 (CCMR1 at 0x5305) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM2_CCMR1 reset value + #define sfr_TIM2_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM2 capture/compare mode register 2 (CCMR2 at 0x5306) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM2_CCMR2 reset value + #define sfr_TIM2_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM2 capture/compare mode register 3 (CCMR3 at 0x5307) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR3 bitfield + + /// register _TIM2_CCMR3 reset value + #define sfr_TIM2_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM2 capture/compare enable register 1 (CCER1 at 0x5308) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM2_CCER1 reset value + #define sfr_TIM2_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM2 capture/compare enable register 2 (CCER2 at 0x5309) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS : 6; // 6 bits + }; // CCER2 bitfield + + /// register _TIM2_CCER2 reset value + #define sfr_TIM2_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM2 counter high (CNTRH at 0x530a) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM2_CNTRH reset value + #define sfr_TIM2_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM2 counter low (CNTRL at 0x530b) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM2_CNTRL reset value + #define sfr_TIM2_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM2 prescaler register (PSCR at 0x530c) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // PSCR bitfield + + /// register _TIM2_PSCR reset value + #define sfr_TIM2_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM2 auto-reload register high (ARRH at 0x530d) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM2_ARRH reset value + #define sfr_TIM2_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM2 auto-reload register low (ARRL at 0x530e) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM2_ARRL reset value + #define sfr_TIM2_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM2 capture/compare register 1 high (CCR1H at 0x530f) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM2_CCR1H reset value + #define sfr_TIM2_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM2 capture/compare register 1 low (CCR1L at 0x5310) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM2_CCR1L reset value + #define sfr_TIM2_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM2 capture/compare reg (CCR2H at 0x5311) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM2_CCR2H reset value + #define sfr_TIM2_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM2 capture/compare register 2 low (CCR2L at 0x5312) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM2_CCR2L reset value + #define sfr_TIM2_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM2 capture/compare register 3 high (CCR3H at 0x5313) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3H bitfield + + /// register _TIM2_CCR3H reset value + #define sfr_TIM2_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM2 capture/compare register 3 low (CCR3L at 0x5314) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3L bitfield + + /// register _TIM2_CCR3L reset value + #define sfr_TIM2_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + +} TIM2_t; + +/// access to TIM2 SFR registers +#define sfr_TIM2 (*((TIM2_t*) 0x5300)) + + +//------------------------ +// Module TIM3 +//------------------------ + +/** struct containing TIM3 module registers */ +typedef struct { + + /** TIM3 control register 1 (CR1 at 0x5320) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM3_CR1 reset value + #define sfr_TIM3_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM3 interrupt enable register (IER at 0x5321) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM3_IER reset value + #define sfr_TIM3_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM3 status register 1 (SR1 at 0x5322) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR1 bitfield + + /// register _TIM3_SR1 reset value + #define sfr_TIM3_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM3 status register 2 (SR2 at 0x5323) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SR2 bitfield + + /// register _TIM3_SR2 reset value + #define sfr_TIM3_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM3 event generation register (EGR at 0x5324) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS : 2; // 2 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM3_EGR reset value + #define sfr_TIM3_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM3 capture/compare mode register 1 (CCMR1 at 0x5325) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM3_CCMR1 reset value + #define sfr_TIM3_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM3 capture/compare mode register 2 (CCMR2 at 0x5326) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM3_CCMR2 reset value + #define sfr_TIM3_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM3 capture/compare enable register 1 (CCER1 at 0x5327) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM3_CCER1 reset value + #define sfr_TIM3_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM3 counter high (CNTRH at 0x5328) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM3_CNTRH reset value + #define sfr_TIM3_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM3 counter low (CNTRL at 0x5329) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM3_CNTRL reset value + #define sfr_TIM3_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM3 prescaler register (PSCR at 0x532a) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // PSCR bitfield + + /// register _TIM3_PSCR reset value + #define sfr_TIM3_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM3 auto-reload register high (ARRH at 0x532b) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM3_ARRH reset value + #define sfr_TIM3_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM3 auto-reload register low (ARRL at 0x532c) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM3_ARRL reset value + #define sfr_TIM3_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM3 capture/compare register 1 high (CCR1H at 0x532d) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM3_CCR1H reset value + #define sfr_TIM3_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM3 capture/compare register 1 low (CCR1L at 0x532e) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM3_CCR1L reset value + #define sfr_TIM3_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM3 capture/compare register 2 high (CCR2H at 0x532f) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM3_CCR2H reset value + #define sfr_TIM3_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM3 capture/compare register 2 low (CCR2L at 0x5330) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM3_CCR2L reset value + #define sfr_TIM3_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + +} TIM3_t; + +/// access to TIM3 SFR registers +#define sfr_TIM3 (*((TIM3_t*) 0x5320)) + + +//------------------------ +// Module TIM4 +//------------------------ + +/** struct containing TIM4 module registers */ +typedef struct { + + /** TIM4 control register 1 (CR1 at 0x5340) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM4_CR1 reset value + #define sfr_TIM4_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM4 interrupt enable register (IER at 0x5341) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM4_IER reset value + #define sfr_TIM4_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM4 status register (SR at 0x5342) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS UIF : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR bitfield + + /// register _TIM4_SR reset value + #define sfr_TIM4_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + + + /** TIM4 event generation register (EGR at 0x5343) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS : 5; // 5 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM4_EGR reset value + #define sfr_TIM4_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM4 counter (CNTR at 0x5344) */ + union { + + /// bytewise access to CNTR + uint8_t byte; + + /// bitwise access to register CNTR + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTR bitfield + + /// register _TIM4_CNTR reset value + #define sfr_TIM4_CNTR_RESET_VALUE ((uint8_t) 0x00) + + } CNTR; + + + /** TIM4 prescaler register (PSCR at 0x5345) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PSCR bitfield + + /// register _TIM4_PSCR reset value + #define sfr_TIM4_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM4 auto-reload register (ARR at 0x5346) */ + union { + + /// bytewise access to ARR + uint8_t byte; + + /// bitwise access to register ARR + struct { + BITS ARR : 8; // bits 0-7 + }; // ARR bitfield + + /// register _TIM4_ARR reset value + #define sfr_TIM4_ARR_RESET_VALUE ((uint8_t) 0xFF) + + } ARR; + +} TIM4_t; + +/// access to TIM4 SFR registers +#define sfr_TIM4 (*((TIM4_t*) 0x5340)) + + +//------------------------ +// Module UART2 +//------------------------ + +/** struct containing UART2 module registers */ +typedef struct { + + /** UART2 status register (SR at 0x5240) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS PE : 1; // bit 0 + BITS FE : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS OR_LHE : 1; // bit 3 + BITS IDLE : 1; // bit 4 + BITS RXNE : 1; // bit 5 + BITS TC : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR bitfield + + /// register _UART2_SR reset value + #define sfr_UART2_SR_RESET_VALUE ((uint8_t) 0xC0) + + } SR; + + + /** UART2 data register (DR at 0x5241) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _UART2_DR reset value + #define sfr_UART2_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** UART2 baud rate register 1 (BRR1 at 0x5242) */ + union { + + /// bytewise access to BRR1 + uint8_t byte; + + /// bitwise access to register BRR1 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR1 bitfield + + /// register _UART2_BRR1 reset value + #define sfr_UART2_BRR1_RESET_VALUE ((uint8_t) 0x00) + + } BRR1; + + + /** UART2 baud rate register 2 (BRR2 at 0x5243) */ + union { + + /// bytewise access to BRR2 + uint8_t byte; + + /// bitwise access to register BRR2 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR2 bitfield + + /// register _UART2_BRR2 reset value + #define sfr_UART2_BRR2_RESET_VALUE ((uint8_t) 0x00) + + } BRR2; + + + /** UART2 control register 1 (CR1 at 0x5244) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PIEN : 1; // bit 0 + BITS PS : 1; // bit 1 + BITS PCEN : 1; // bit 2 + BITS WAKE : 1; // bit 3 + BITS M : 1; // bit 4 + BITS UART0 : 1; // bit 5 + BITS T8 : 1; // bit 6 + BITS R8 : 1; // bit 7 + }; // CR1 bitfield + + /// register _UART2_CR1 reset value + #define sfr_UART2_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** UART2 control register 2 (CR2 at 0x5245) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SBK : 1; // bit 0 + BITS RWU : 1; // bit 1 + BITS REN : 1; // bit 2 + BITS TEN : 1; // bit 3 + BITS ILIEN : 1; // bit 4 + BITS RIEN : 1; // bit 5 + BITS TCIEN : 1; // bit 6 + BITS TIEN : 1; // bit 7 + }; // CR2 bitfield + + /// register _UART2_CR2 reset value + #define sfr_UART2_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** UART2 control register 3 (CR3 at 0x5246) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS LBCL : 1; // bit 0 + BITS CPHA : 1; // bit 1 + BITS CPOL : 1; // bit 2 + BITS CKEN : 1; // bit 3 + BITS STOP : 2; // bits 4-5 + BITS : 1; // 1 bit + BITS LINEN : 1; // bit 7 + }; // CR3 bitfield + + /// register _UART2_CR3 reset value + #define sfr_UART2_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** UART2 control register 4 (CR4 at 0x5247) */ + union { + + /// bytewise access to CR4 + uint8_t byte; + + /// bitwise access to register CR4 + struct { + BITS ADD : 4; // bits 0-3 + BITS LBDF : 1; // bit 4 + BITS LBDL : 1; // bit 5 + BITS LBDIEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR4 bitfield + + /// register _UART2_CR4 reset value + #define sfr_UART2_CR4_RESET_VALUE ((uint8_t) 0x00) + + } CR4; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** UART2 control register 6 (CR6 at 0x5249) */ + union { + + /// bytewise access to CR6 + uint8_t byte; + + /// bitwise access to register CR6 + struct { + BITS LSF : 1; // bit 0 + BITS LHDF : 1; // bit 1 + BITS LHDIEN : 1; // bit 2 + BITS : 1; // 1 bit + BITS LASE : 1; // bit 4 + BITS LSLV : 1; // bit 5 + BITS : 1; // 1 bit + BITS LDUM : 1; // bit 7 + }; // CR6 bitfield + + /// register _UART2_CR6 reset value + #define sfr_UART2_CR6_RESET_VALUE ((uint8_t) 0x00) + + } CR6; + + + /** UART2 guard time register (GTR at 0x524a) */ + union { + + /// bytewise access to GTR + uint8_t byte; + + /// bitwise access to register GTR + struct { + BITS GT : 8; // bits 0-7 + }; // GTR bitfield + + /// register _UART2_GTR reset value + #define sfr_UART2_GTR_RESET_VALUE ((uint8_t) 0x00) + + } GTR; + + + /** UART2 prescaler register (PSCR at 0x524b) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCR bitfield + + /// register _UART2_PSCR reset value + #define sfr_UART2_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + +} UART2_t; + +/// access to UART2 SFR registers +#define sfr_UART2 (*((UART2_t*) 0x5240)) + + +//------------------------ +// Module WWDG +//------------------------ + +/** struct containing WWDG module registers */ +typedef struct { + + /** WWDG control register (CR at 0x50d1) */ + union { + + /// bytewise access to CR + uint8_t byte; + + /// bitwise access to register CR + struct { + BITS T0 : 1; // bit 0 + BITS T1 : 1; // bit 1 + BITS T2 : 1; // bit 2 + BITS T3 : 1; // bit 3 + BITS T4 : 1; // bit 4 + BITS T5 : 1; // bit 5 + BITS T6 : 1; // bit 6 + BITS WDGA : 1; // bit 7 + }; // CR bitfield + + /// register _WWDG_CR reset value + #define sfr_WWDG_CR_RESET_VALUE ((uint8_t) 0x7F) + + } CR; + + + /** WWDR window register (WR at 0x50d2) */ + union { + + /// bytewise access to WR + uint8_t byte; + + /// bitwise access to register WR + struct { + BITS W0 : 1; // bit 0 + BITS W1 : 1; // bit 1 + BITS W2 : 1; // bit 2 + BITS W3 : 1; // bit 3 + BITS W4 : 1; // bit 4 + BITS W5 : 1; // bit 5 + BITS W6 : 1; // bit 6 + BITS : 1; // 1 bit + }; // WR bitfield + + /// register _WWDG_WR reset value + #define sfr_WWDG_WR_RESET_VALUE ((uint8_t) 0x7F) + + } WR; + +} WWDG_t; + +/// access to WWDG SFR registers +#define sfr_WWDG (*((WWDG_t*) 0x50d1)) + + +// undefine local macros +#undef BITS + +// required for C++ +#ifdef __cplusplus + } // extern "C" +#endif + +/*------------------------------------------------------------------------- + END OF MODULE DEFINITION FOR MULTIPLE INLUSION +-------------------------------------------------------------------------*/ +#endif // STM8S105K6_H diff --git a/ports/stm8_oss/stm8-include/STM8S207MB.h b/ports/stm8_oss/stm8-include/STM8S207MB.h new file mode 100644 index 00000000..8a4936fb --- /dev/null +++ b/ports/stm8_oss/stm8-include/STM8S207MB.h @@ -0,0 +1,4640 @@ +/*------------------------------------------------------------------------- + + STM8S207MB.h - Device Declarations + + STM8S/STM8AF, high density with ROM bootloader + + Copyright (C) 2020, Georg Icking-Konert + + Mainstream Performance line 8-bit MCU with 128 Kbytes Flash, 24 MHz CPU, integrated EEPROM + + datasheet: https://www.st.com/resource/en/datasheet/stm8s207mb.pdf + reference: RM0016 https://www.st.com/content/ccc/resource/technical/document/reference_manual/9a/1b/85/07/ca/eb/4f/dd/CD00190271.pdf/files/CD00190271.pdf/jcr:content/translations/en.CD00190271.pdf + + MIT License + + Copyright (c) 2020 Georg Icking-Konert + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. + +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- + MODULE DEFINITION FOR MULTIPLE INCLUSION +-------------------------------------------------------------------------*/ +#ifndef STM8S207MB_H +#define STM8S207MB_H + +// DEVICE NAME +#define DEVICE_STM8S207MB + +// DEVICE FAMILY +#define FAMILY_STM8S + +// required for C++ +#ifdef __cplusplus + extern "C" { +#endif + + +/*------------------------------------------------------------------------- + INCLUDE FILES +-------------------------------------------------------------------------*/ +#include + + +/*------------------------------------------------------------------------- + COMPILER SPECIFIC SETTINGS +-------------------------------------------------------------------------*/ + +// Cosmic compiler +#if defined(__CSMC__) + + // macros to unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) @far @interrupt void func(void) ///< handler for interrupt service routine + #define ISR_HANDLER_TRAP(func) void @far @interrupt func(void) ///< handler for trap service routine + + // definition of inline functions + #define INLINE @inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() _asm("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() _asm("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() _asm("rim") ///< enable interrupt handling + #define TRIGGER_TRAP _asm("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() _asm("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() _asm("halt") ///< put controller to HALT mode + #define SW_RESET() _asm("dc.b $75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + + +// IAR Compiler +#elif defined(__ICCSTM8__) + + // include intrinsic functions + #include + + // macros to unify ISR declaration and implementation + #define STRINGVECTOR(x) #x + #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) + #define ISR_HANDLER( a, b ) \ + _Pragma( VECTOR_ID( (b)+2 ) ) \ + __interrupt void (a)( void ) + #define ISR_HANDLER_TRAP(a) \ + _Pragma( VECTOR_ID( 1 ) ) \ + __interrupt void (a) (void) + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __no_operation() ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __disable_interrupt() ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __enable_interrupt() ///< enable interrupt handling + #define TRIGGER_TRAP __trap() ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __wait_for_interrupt() ///< stop code execution and wait for interrupt + #define ENTER_HALT() __halt() ///< put controller to HALT mode + #define SW_RESET() __asm("dc8 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned char ///< data type in bit structs (deviating from C90 standard) + + +// SDCC compiler +#elif defined(__SDCC) + + // store SDCC version in preprocessor friendly way + #define SDCC_VERSION (__SDCC_VERSION_MAJOR * 10000 \ + + __SDCC_VERSION_MINOR * 100 \ + + __SDCC_VERSION_PATCH) + + // unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) void func(void) __interrupt(irq) ///< handler for interrupt service routine + #if SDCC_VERSION >= 30403 // traps require >=v3.4.3 + #define ISR_HANDLER_TRAP(func) void func() __trap ///< handler for trap service routine + #else + #error traps require SDCC >=3.4.3. Please update! + #endif + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __asm__("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __asm__("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __asm__("rim") ///< enable interrupt handling + #define TRIGGER_TRAP __asm__("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __asm__("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() __asm__("halt") ///< put controller to HALT mode + #define SW_RESET() __asm__(".db 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + +// unsupported compiler -> stop +#else + #error: compiler not supported +#endif + + +/*------------------------------------------------------------------------- + FOR CONVENIENT PIN ACCESS +-------------------------------------------------------------------------*/ + +#define PIN0 0x01 +#define PIN1 0x02 +#define PIN2 0x04 +#define PIN3 0x08 +#define PIN4 0x10 +#define PIN5 0x20 +#define PIN6 0x40 +#define PIN7 0x80 + + +/*------------------------------------------------------------------------- + DEVICE MEMORY (size in bytes) +-------------------------------------------------------------------------*/ + +// RAM +#define RAM_ADDR_START 0x000000 +#define RAM_ADDR_END 0x0017FF +#define RAM_SIZE 6144 + + +// FLASH +#define FLASH_ADDR_START 0x008000 +#define FLASH_ADDR_END 0x027FFF +#define FLASH_SIZE 131072 + + +// SFR1 +#define SFR1_ADDR_START 0x005000 +#define SFR1_ADDR_END 0x0057FF +#define SFR1_SIZE 2048 + + +// SFR2 +#define SFR2_ADDR_START 0x007F00 +#define SFR2_ADDR_END 0x007FFF +#define SFR2_SIZE 256 + + +// BOOTROM +#define BOOTROM_ADDR_START 0x006000 +#define BOOTROM_ADDR_END 0x0067FF +#define BOOTROM_SIZE 2048 + + +// EEPROM +#define EEPROM_ADDR_START 0x004000 +#define EEPROM_ADDR_END 0x0047FF +#define EEPROM_SIZE 2048 + + +// OPTION +#define OPTION_ADDR_START 0x004800 +#define OPTION_ADDR_END 0x00487F +#define OPTION_SIZE 128 + + +// MEMORY WIDTH (>32kB flash exceeds 16bit, as flash starts at 0x8000) +#define FLASH_ADDR_WIDTH 32 ///< width of address space +#define FLASH_POINTER_T uint32_t ///< address variable type + + +/*------------------------------------------------------------------------- + UNIQUE IDENTIFIER (size in bytes) +-------------------------------------------------------------------------*/ + +#define UID_ADDR_START 0x48CD ///< start address of unique identifier +#define UID_SIZE 12 ///< size of unique identifier [B] +#define UID(N) (*((uint8_t*) (UID_ADDR_START+N))) ///< read unique identifier byte N + + +/*------------------------------------------------------------------------- + ISR Vector Table (SDCC, IAR) + Notes: + - IAR has an IRQ offset of +2 compared to datasheet and below numbers + - Cosmic uses a separate, device specific file 'stm8_interrupt_vector.c' + - different interrupt sources may share the same IRQ +-------------------------------------------------------------------------*/ + +// interrupt IRQ +#define _TLI_VECTOR_ 0 +#define _AWU_VECTOR_ 1 ///< AWU interrupt vector: enable: AWU_CSR1.AWUEN, pending: AWU_CSR1.AWUF, priority: ITC_SPR1.VECT1SPR +#define _CLK_CSS_VECTOR_ 2 ///< CLK_CSS interrupt vector: enable: CLK_CSSR.CSSDIE, pending: CLK_CSSR.CSSD, priority: ITC_SPR1.VECT2SPR +#define _CLK_SWITCH_VECTOR_ 2 ///< CLK_SWITCH interrupt vector: enable: CLK_SWCR.SWIEN, pending: CLK_SWCR.SWIF, priority: ITC_SPR1.VECT2SPR +#define _EXTI0_VECTOR_ 3 ///< EXTI0 interrupt vector: enable: PA_CR2.C20, pending: PA_IDR.IDR0, priority: ITC_SPR1.VECT3SPR +#define _EXTI1_VECTOR_ 4 ///< EXTI1 interrupt vector: enable: PB_CR2.C20, pending: PB_IDR.IDR0, priority: ITC_SPR2.VECT4SPR +#define _EXTI2_VECTOR_ 5 ///< EXTI2 interrupt vector: enable: PC_CR2.C20, pending: PC_IDR.IDR0, priority: ITC_SPR2.VECT5SPR +#define _EXTI3_VECTOR_ 6 ///< EXTI3 interrupt vector: enable: PD_CR2.C20, pending: PD_IDR.IDR0, priority: ITC_SPR2.VECT6SPR +#define _EXTI4_VECTOR_ 7 ///< EXTI4 interrupt vector: enable: PE_CR2.C20, pending: PE_IDR.IDR0, priority: ITC_SPR2.VECT7SPR +#define _SPI_CRCERR_VECTOR_ 10 ///< SPI_CRCERR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.CRCERR, priority: ITC_SPR3.VECT10SPR +#define _SPI_MODF_VECTOR_ 10 ///< SPI_MODF interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.MODF, priority: ITC_SPR3.VECT10SPR +#define _SPI_OVR_VECTOR_ 10 ///< SPI_OVR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.OVR, priority: ITC_SPR3.VECT10SPR +#define _SPI_RXNE_VECTOR_ 10 ///< SPI_RXNE interrupt vector: enable: SPI_ICR.RXIE, pending: SPI_SR.RXNE, priority: ITC_SPR3.VECT10SPR +#define _SPI_TXE_VECTOR_ 10 ///< SPI_TXE interrupt vector: enable: SPI_ICR.TXIE, pending: SPI_SR.TXE, priority: ITC_SPR3.VECT10SPR +#define _SPI_WKUP_VECTOR_ 10 ///< SPI_WKUP interrupt vector: enable: SPI_ICR.WKIE, pending: SPI_SR.WKUP, priority: ITC_SPR3.VECT10SPR +#define _TIM1_CAPCOM_BIF_VECTOR_ 11 ///< TIM1_CAPCOM_BIF interrupt vector: enable: TIM1_IER.BIE, pending: TIM1_SR1.BIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_CAPCOM_TIF_VECTOR_ 11 ///< TIM1_CAPCOM_TIF interrupt vector: enable: TIM1_IER.TIE, pending: TIM1_SR1.TIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_OVR_UIF_VECTOR_ 11 ///< TIM1_OVR_UIF interrupt vector: enable: TIM1_IER.UIE, pending: TIM1_SR1.UIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_CAPCOM_CC1IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC1IF interrupt vector: enable: TIM1_IER.CC1IE, pending: TIM1_SR1.CC1IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC2IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC2IF interrupt vector: enable: TIM1_IER.CC2IE, pending: TIM1_SR1.CC2IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC3IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC3IF interrupt vector: enable: TIM1_IER.CC3IE, pending: TIM1_SR1.CC3IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC4IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC4IF interrupt vector: enable: TIM1_IER.CC4IE, pending: TIM1_SR1.CC4IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_COMIF_VECTOR_ 12 ///< TIM1_CAPCOM_COMIF interrupt vector: enable: TIM1_IER.COMIE, pending: TIM1_SR1.COMIF, priority: ITC_SPR4.VECT12SPR +#define _TIM2_OVR_UIF_VECTOR_ 13 ///< TIM2_OVR_UIF interrupt vector: enable: TIM2_IER.UIE, pending: TIM2_SR1.UIF, priority: ITC_SPR4.VECT13SPR +#define _TIM2_CAPCOM_CC1IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC1IF interrupt vector: enable: TIM2_IER.CC1IE, pending: TIM2_SR1.CC1IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_CC2IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC2IF interrupt vector: enable: TIM2_IER.CC2IE, pending: TIM2_SR1.CC2IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_CC3IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC3IF interrupt vector: enable: TIM2_IER.CC3IE, pending: TIM2_SR1.CC3IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_TIF_VECTOR_ 14 ///< TIM2_CAPCOM_TIF interrupt vector: enable: TIM2_IER.TIE, pending: TIM2_SR1.TIF, priority: ITC_SPR4.VECT14SPR +#define _TIM3_OVR_UIF_VECTOR_ 15 ///< TIM3_OVR_UIF interrupt vector: enable: TIM3_IER.UIE, pending: TIM3_SR1.UIF, priority: ITC_SPR4.VECT15SPR +#define _TIM3_CAPCOM_CC1IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC1IF interrupt vector: enable: TIM3_IER.CC1IE, pending: TIM3_SR1.CC1IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_CC2IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC2IF interrupt vector: enable: TIM3_IER.CC2IE, pending: TIM3_SR1.CC2IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_CC3IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC3IF interrupt vector: enable: TIM3_IER.CC3IE, pending: TIM3_SR1.CC3IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_TIF_VECTOR_ 16 ///< TIM3_CAPCOM_TIF interrupt vector: enable: TIM3_IER.TIE, pending: TIM3_SR1.TIF, priority: ITC_SPR5.VECT16SPR +#define _UART1_T_TC_VECTOR_ 17 ///< UART1_T_TC interrupt vector: enable: UART1_CR2.TCIEN, pending: UART1_SR.TC, priority: ITC_SPR5.VECT17SPR +#define _UART1_T_TXE_VECTOR_ 17 ///< UART1_T_TXE interrupt vector: enable: UART1_CR2.TIEN, pending: UART1_SR.TXE, priority: ITC_SPR5.VECT17SPR +#define _UART1_R_IDLE_VECTOR_ 18 ///< UART1_R_IDLE interrupt vector: enable: UART1_CR2.ILIEN, pending: UART1_SR.IDLE, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_LBDF_VECTOR_ 18 ///< UART1_R_LBDF interrupt vector: enable: UART1_CR4.LBDIEN, pending: UART1_CR4.LBDF, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_OR_VECTOR_ 18 ///< UART1_R_OR interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.OR_LHE, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_PE_VECTOR_ 18 ///< UART1_R_PE interrupt vector: enable: UART1_CR1.PIEN, pending: UART1_SR.PE, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_RXNE_VECTOR_ 18 ///< UART1_R_RXNE interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.RXNE, priority: ITC_SPR5.VECT18SPR +#define _I2C_ADD10_VECTOR_ 19 ///< I2C_ADD10 interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADD10, priority: ITC_SPR5.VECT19SPR +#define _I2C_ADDR_VECTOR_ 19 ///< I2C_ADDR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADDR, priority: ITC_SPR5.VECT19SPR +#define _I2C_AF_VECTOR_ 19 ///< I2C_AF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.AF, priority: ITC_SPR5.VECT19SPR +#define _I2C_ARLO_VECTOR_ 19 ///< I2C_ARLO interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.ARLO, priority: ITC_SPR5.VECT19SPR +#define _I2C_BERR_VECTOR_ 19 ///< I2C_BERR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.BERR, priority: ITC_SPR5.VECT19SPR +#define _I2C_BTF_VECTOR_ 19 ///< I2C_BTF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.BTF, priority: ITC_SPR5.VECT19SPR +#define _I2C_OVR_VECTOR_ 19 ///< I2C_OVR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.OVR, priority: ITC_SPR5.VECT19SPR +#define _I2C_RXNE_VECTOR_ 19 ///< I2C_RXNE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.RXNE, priority: ITC_SPR5.VECT19SPR +#define _I2C_SB_VECTOR_ 19 ///< I2C_SB interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.SB, priority: ITC_SPR5.VECT19SPR +#define _I2C_STOPF_VECTOR_ 19 ///< I2C_STOPF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.STOPF, priority: ITC_SPR5.VECT19SPR +#define _I2C_TXE_VECTOR_ 19 ///< I2C_TXE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.TXE, priority: ITC_SPR5.VECT19SPR +#define _I2C_WUFH_VECTOR_ 19 ///< I2C_WUFH interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.WUFH, priority: ITC_SPR5.VECT19SPR +#define _UART3_T_TC_VECTOR_ 20 ///< UART3_T_TC interrupt vector: enable: UART3_CR2.TCIEN, pending: UART3_SR.TC, priority: ITC_SPR6.VECT20SPR +#define _UART3_T_TXE_VECTOR_ 20 ///< UART3_T_TXE interrupt vector: enable: UART3_CR2.TIEN, pending: UART3_SR.TXE, priority: ITC_SPR6.VECT20SPR +#define _UART3_R_IDLE_VECTOR_ 21 ///< UART3_R_IDLE interrupt vector: enable: UART3_CR2.ILIEN, pending: UART3_SR.IDLE, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_LBDF_VECTOR_ 21 ///< UART3_R_LBDF interrupt vector: enable: UART3_CR4.LBDIEN, pending: UART3_CR4.LBDF, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_LHDF_VECTOR_ 21 ///< UART3_R_LHDF interrupt vector: enable: UART3_CR6.LHDIEN, pending: UART3_CR6.LHDF, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_OR_VECTOR_ 21 ///< UART3_R_OR interrupt vector: enable: UART3_CR2.RIEN, pending: UART3_SR.OR, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_PE_VECTOR_ 21 ///< UART3_R_PE interrupt vector: enable: UART3_CR1.PIEN, pending: UART3_SR.PE, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_RXNE_VECTOR_ 21 ///< UART3_R_RXNE interrupt vector: enable: UART3_CR2.RIEN, pending: UART3_SR.RXNE, priority: ITC_SPR6.VECT21SPR +#define _ADC2_AWDG_VECTOR_ 22 ///< ADC2_AWDG interrupt vector: enable: ADC_CSR.AWDIE, pending: ADC_CSR.AWD, priority: ITC_SPR6.VECT22SPR +#define _ADC2_EOC_VECTOR_ 22 ///< ADC2_EOC interrupt vector: enable: ADC_CSR.EOCIE, pending: ADC_CSR.EOC, priority: ITC_SPR6.VECT22SPR +#define _TIM4_OVR_UIF_VECTOR_ 23 ///< TIM4_OVR_UIF interrupt vector: enable: TIM4_IER.UIE, pending: TIM4_SR.UIF, priority: ITC_SPR6.VECT23SPR +#define _FLASH_EOP_VECTOR_ 24 ///< FLASH_EOP interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.EOP, priority: ITC_SPR6.VECT24SPR +#define _FLASH_WR_PG_DIS_VECTOR_ 24 ///< FLASH_WR_PG_DIS interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.WR_PG_DIS, priority: ITC_SPR6.VECT24SPR + + +/*------------------------------------------------------------------------- + DEFINITION OF STM8 PERIPHERAL REGISTERS +-------------------------------------------------------------------------*/ + +//------------------------ +// Module ADC2 +//------------------------ + +/** struct containing ADC2 module registers */ +typedef struct { + + /** ADC control/status register (CSR at 0x5400) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// bitwise access to register CSR + struct { + BITS CH : 4; // bits 0-3 + BITS AWDIE : 1; // bit 4 + BITS EOCIE : 1; // bit 5 + BITS AWD : 1; // bit 6 + BITS EOC : 1; // bit 7 + }; // CSR bitfield + + /// register _ADC2_CSR reset value + #define sfr_ADC2_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + + + /** ADC configuration register 1 (CR1 at 0x5401) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS ADON : 1; // bit 0 + BITS CONT : 1; // bit 1 + BITS : 2; // 2 bits + BITS SPSEL : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR1 bitfield + + /// register _ADC2_CR1 reset value + #define sfr_ADC2_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** ADC configuration register 2 (CR2 at 0x5402) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS : 1; // 1 bit + BITS SCAN : 1; // bit 1 + BITS : 1; // 1 bit + BITS ALIGN : 1; // bit 3 + BITS EXTSEL : 2; // bits 4-5 + BITS EXTTRIG : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _ADC2_CR2 reset value + #define sfr_ADC2_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** ADC configuration register 3 (CR3 at 0x5403) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS : 6; // 6 bits + BITS OVR : 1; // bit 6 + BITS DBUF : 1; // bit 7 + }; // CR3 bitfield + + /// register _ADC2_CR3 reset value + #define sfr_ADC2_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** ADC data register high (DRH at 0x5404) */ + union { + + /// bytewise access to DRH + uint8_t byte; + + /// bitwise access to register DRH + struct { + BITS DH : 8; // bits 0-7 + }; // DRH bitfield + + /// register _ADC2_DRH reset value + #define sfr_ADC2_DRH_RESET_VALUE ((uint8_t) 0x00) + + } DRH; + + + /** ADC data register low (DRL at 0x5405) */ + union { + + /// bytewise access to DRL + uint8_t byte; + + /// bitwise access to register DRL + struct { + BITS DL : 8; // bits 0-7 + }; // DRL bitfield + + /// register _ADC2_DRL reset value + #define sfr_ADC2_DRL_RESET_VALUE ((uint8_t) 0x00) + + } DRL; + + + /** ADC Schmitt trigger disable register high (TDRH at 0x5406) */ + union { + + /// bytewise access to TDRH + uint8_t byte; + + /// bitwise access to register TDRH + struct { + BITS TD : 8; // bits 0-7 + }; // TDRH bitfield + + /// register _ADC2_TDRH reset value + #define sfr_ADC2_TDRH_RESET_VALUE ((uint8_t) 0x00) + + } TDRH; + + + /** ADC Schmitt trigger disable register low (TDRL at 0x5407) */ + union { + + /// bytewise access to TDRL + uint8_t byte; + + /// bitwise access to register TDRL + struct { + BITS TL : 8; // bits 0-7 + }; // TDRL bitfield + + /// register _ADC2_TDRL reset value + #define sfr_ADC2_TDRL_RESET_VALUE ((uint8_t) 0x00) + + } TDRL; + +} ADC2_t; + +/// access to ADC2 SFR registers +#define sfr_ADC2 (*((ADC2_t*) 0x5400)) + + +//------------------------ +// Module AWU +//------------------------ + +/** struct containing AWU module registers */ +typedef struct { + + /** AWU control/status register 1 (CSR1 at 0x50f0) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// bitwise access to register CSR1 + struct { + BITS MSR : 1; // bit 0 + BITS : 3; // 3 bits + BITS AWUEN : 1; // bit 4 + BITS AWUF : 1; // bit 5 + BITS : 2; // 2 bits + }; // CSR1 bitfield + + /// register _AWU_CSR1 reset value + #define sfr_AWU_CSR1_RESET_VALUE ((uint8_t) 0x00) + + } CSR1; + + + /** AWU asynchronous prescaler buffer register (APR at 0x50f1) */ + union { + + /// bytewise access to APR + uint8_t byte; + + /// bitwise access to register APR + struct { + BITS APR : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // APR bitfield + + /// register _AWU_APR reset value + #define sfr_AWU_APR_RESET_VALUE ((uint8_t) 0x3F) + + } APR; + + + /** AWU timebase selection register (TBR at 0x50f2) */ + union { + + /// bytewise access to TBR + uint8_t byte; + + /// bitwise access to register TBR + struct { + BITS AWUTB : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // TBR bitfield + + /// register _AWU_TBR reset value + #define sfr_AWU_TBR_RESET_VALUE ((uint8_t) 0x00) + + } TBR; + +} AWU_t; + +/// access to AWU SFR registers +#define sfr_AWU (*((AWU_t*) 0x50f0)) + + +//------------------------ +// Module BEEP +//------------------------ + +/** struct containing BEEP module registers */ +typedef struct { + + /** BEEP control/status register (CSR at 0x50f3) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// bitwise access to register CSR + struct { + BITS BEEPDIV : 5; // bits 0-4 + BITS BEEPEN : 1; // bit 5 + BITS BEEPSEL : 2; // bits 6-7 + }; // CSR bitfield + + /// register _BEEP_CSR reset value + #define sfr_BEEP_CSR_RESET_VALUE ((uint8_t) 0x1F) + + } CSR; + +} BEEP_t; + +/// access to BEEP SFR registers +#define sfr_BEEP (*((BEEP_t*) 0x50f3)) + + +//------------------------ +// Module CLK +//------------------------ + +/** struct containing CLK module registers */ +typedef struct { + + /** Internal clock control register (ICKR at 0x50c0) */ + union { + + /// bytewise access to ICKR + uint8_t byte; + + /// bitwise access to register ICKR + struct { + BITS HSIEN : 1; // bit 0 + BITS HSIRDY : 1; // bit 1 + BITS FHW : 1; // bit 2 + BITS LSIEN : 1; // bit 3 + BITS LSIRDY : 1; // bit 4 + BITS REGAH : 1; // bit 5 + BITS : 2; // 2 bits + }; // ICKR bitfield + + /// register _CLK_ICKR reset value + #define sfr_CLK_ICKR_RESET_VALUE ((uint8_t) 0x01) + + } ICKR; + + + /** External clock control register (ECKR at 0x50c1) */ + union { + + /// bytewise access to ECKR + uint8_t byte; + + /// bitwise access to register ECKR + struct { + BITS HSEEN : 1; // bit 0 + BITS HSERDY : 1; // bit 1 + BITS : 6; // 6 bits + }; // ECKR bitfield + + /// register _CLK_ECKR reset value + #define sfr_CLK_ECKR_RESET_VALUE ((uint8_t) 0x00) + + } ECKR; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** Clock master status register (CMSR at 0x50c3) */ + union { + + /// bytewise access to CMSR + uint8_t byte; + + /// bitwise access to register CMSR + struct { + BITS CKM : 8; // bits 0-7 + }; // CMSR bitfield + + /// register _CLK_CMSR reset value + #define sfr_CLK_CMSR_RESET_VALUE ((uint8_t) 0xE1) + + } CMSR; + + + /** Clock master switch register (SWR at 0x50c4) */ + union { + + /// bytewise access to SWR + uint8_t byte; + + /// bitwise access to register SWR + struct { + BITS SWI : 8; // bits 0-7 + }; // SWR bitfield + + /// register _CLK_SWR reset value + #define sfr_CLK_SWR_RESET_VALUE ((uint8_t) 0xE1) + + } SWR; + + + /** Clock switch control register (SWCR at 0x50c5) */ + union { + + /// bytewise access to SWCR + uint8_t byte; + + /// bitwise access to register SWCR + struct { + BITS SWBSY : 1; // bit 0 + BITS SWEN : 1; // bit 1 + BITS SWIEN : 1; // bit 2 + BITS SWIF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SWCR bitfield + + /// register _CLK_SWCR reset value + #define sfr_CLK_SWCR_RESET_VALUE ((uint8_t) 0x00) + + } SWCR; + + + /** Clock divider register (CKDIVR at 0x50c6) */ + union { + + /// bytewise access to CKDIVR + uint8_t byte; + + /// bitwise access to register CKDIVR + struct { + BITS CPUDIV : 3; // bits 0-2 + BITS HSIDIV : 2; // bits 3-4 + BITS : 3; // 3 bits + }; // CKDIVR bitfield + + /// register _CLK_CKDIVR reset value + #define sfr_CLK_CKDIVR_RESET_VALUE ((uint8_t) 0x18) + + } CKDIVR; + + + /** Peripheral clock gating register 1 (PCKENR1 at 0x50c7) */ + union { + + /// bytewise access to PCKENR1 + uint8_t byte; + + /// bitwise access to register PCKENR1 + struct { + BITS PCKEN : 8; // bits 0-7 + }; // PCKENR1 bitfield + + /// register _CLK_PCKENR1 reset value + #define sfr_CLK_PCKENR1_RESET_VALUE ((uint8_t) 0xFF) + + } PCKENR1; + + + /** Clock security system register (CSSR at 0x50c8) */ + union { + + /// bytewise access to CSSR + uint8_t byte; + + /// bitwise access to register CSSR + struct { + BITS CSSEN : 1; // bit 0 + BITS AUX : 1; // bit 1 + BITS CSSDIE : 1; // bit 2 + BITS CSSD : 1; // bit 3 + BITS : 4; // 4 bits + }; // CSSR bitfield + + /// register _CLK_CSSR reset value + #define sfr_CLK_CSSR_RESET_VALUE ((uint8_t) 0x00) + + } CSSR; + + + /** Configurable clock control register (CCOR at 0x50c9) */ + union { + + /// bytewise access to CCOR + uint8_t byte; + + /// bitwise access to register CCOR + struct { + BITS CCOEN : 1; // bit 0 + BITS CCOSEL : 4; // bits 1-4 + BITS CCORDY : 1; // bit 5 + BITS CC0BSY : 1; // bit 6 + BITS : 1; // 1 bit + }; // CCOR bitfield + + /// register _CLK_CCOR reset value + #define sfr_CLK_CCOR_RESET_VALUE ((uint8_t) 0x00) + + } CCOR; + + + /** Peripheral clock gating register 2 (PCKENR2 at 0x50ca) */ + union { + + /// bytewise access to PCKENR2 + uint8_t byte; + + /// bitwise access to register PCKENR2 + struct { + BITS PCKEN2 : 8; // bits 0-7 + }; // PCKENR2 bitfield + + /// register _CLK_PCKENR2 reset value + #define sfr_CLK_PCKENR2_RESET_VALUE ((uint8_t) 0xFF) + + } PCKENR2; + + + /** CAN clock control register (CANCCR at 0x50cb) */ + union { + + /// bytewise access to CANCCR + uint8_t byte; + + /// bitwise access to register CANCCR + struct { + BITS CANDIV : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // CANCCR bitfield + + /// register _CLK_CANCCR reset value + #define sfr_CLK_CANCCR_RESET_VALUE ((uint8_t) 0x00) + + } CANCCR; + + + /** HSI clock calibration trimming register (HSITRIMR at 0x50cc) */ + union { + + /// bytewise access to HSITRIMR + uint8_t byte; + + /// bitwise access to register HSITRIMR + struct { + BITS HSITRIM : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // HSITRIMR bitfield + + /// register _CLK_HSITRIMR reset value + #define sfr_CLK_HSITRIMR_RESET_VALUE ((uint8_t) 0x00) + + } HSITRIMR; + + + /** SWIM clock control register (SWIMCCR at 0x50cd) */ + union { + + /// bytewise access to SWIMCCR + uint8_t byte; + + /// bitwise access to register SWIMCCR + struct { + BITS SWIMCLK : 1; // bit 0 + BITS : 7; // 7 bits + }; // SWIMCCR bitfield + + /// register _CLK_SWIMCCR reset value + #define sfr_CLK_SWIMCCR_RESET_VALUE ((uint8_t) 0x00) + + } SWIMCCR; + +} CLK_t; + +/// access to CLK SFR registers +#define sfr_CLK (*((CLK_t*) 0x50c0)) + + +//------------------------ +// Module CPU +//------------------------ + +/** struct containing CPU module registers */ +typedef struct { + + /** Accumulator (A at 0x7f00) */ + union { + + /// bytewise access to A + uint8_t byte; + + /// skip bitwise access to register A + + /// register _CPU_A reset value + #define sfr_CPU_A_RESET_VALUE ((uint8_t) 0x00) + + } A; + + + /** Program counter extended (PCE at 0x7f01) */ + union { + + /// bytewise access to PCE + uint8_t byte; + + /// skip bitwise access to register PCE + + /// register _CPU_PCE reset value + #define sfr_CPU_PCE_RESET_VALUE ((uint8_t) 0x00) + + } PCE; + + + /** Program counter high (PCH at 0x7f02) */ + union { + + /// bytewise access to PCH + uint8_t byte; + + /// skip bitwise access to register PCH + + /// register _CPU_PCH reset value + #define sfr_CPU_PCH_RESET_VALUE ((uint8_t) 0x00) + + } PCH; + + + /** Program counter low (PCL at 0x7f03) */ + union { + + /// bytewise access to PCL + uint8_t byte; + + /// skip bitwise access to register PCL + + /// register _CPU_PCL reset value + #define sfr_CPU_PCL_RESET_VALUE ((uint8_t) 0x00) + + } PCL; + + + /** X index register high (XH at 0x7f04) */ + union { + + /// bytewise access to XH + uint8_t byte; + + /// skip bitwise access to register XH + + /// register _CPU_XH reset value + #define sfr_CPU_XH_RESET_VALUE ((uint8_t) 0x00) + + } XH; + + + /** X index register low (XL at 0x7f05) */ + union { + + /// bytewise access to XL + uint8_t byte; + + /// skip bitwise access to register XL + + /// register _CPU_XL reset value + #define sfr_CPU_XL_RESET_VALUE ((uint8_t) 0x00) + + } XL; + + + /** Y index register high (YH at 0x7f06) */ + union { + + /// bytewise access to YH + uint8_t byte; + + /// skip bitwise access to register YH + + /// register _CPU_YH reset value + #define sfr_CPU_YH_RESET_VALUE ((uint8_t) 0x00) + + } YH; + + + /** Y index register low (YL at 0x7f07) */ + union { + + /// bytewise access to YL + uint8_t byte; + + /// skip bitwise access to register YL + + /// register _CPU_YL reset value + #define sfr_CPU_YL_RESET_VALUE ((uint8_t) 0x00) + + } YL; + + + /** Stack pointer high (SPH at 0x7f08) */ + union { + + /// bytewise access to SPH + uint8_t byte; + + /// skip bitwise access to register SPH + + /// register _CPU_SPH reset value + #define sfr_CPU_SPH_RESET_VALUE ((uint8_t) 0x17) + + } SPH; + + + /** Stack pointer low (SPL at 0x7f09) */ + union { + + /// bytewise access to SPL + uint8_t byte; + + /// skip bitwise access to register SPL + + /// register _CPU_SPL reset value + #define sfr_CPU_SPL_RESET_VALUE ((uint8_t) 0xFF) + + } SPL; + + + /** Condition code register (CCR at 0x7f0a) */ + union { + + /// bytewise access to CCR + uint8_t byte; + + /// bitwise access to register CCR + struct { + BITS C : 1; // bit 0 + BITS Z : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS I0 : 1; // bit 3 + BITS H : 1; // bit 4 + BITS I1 : 1; // bit 5 + BITS : 1; // 1 bit + BITS V : 1; // bit 7 + }; // CCR bitfield + + /// register _CPU_CCR reset value + #define sfr_CPU_CCR_RESET_VALUE ((uint8_t) 0x28) + + } CCR; + + + /// Reserved register (85B) + uint8_t Reserved_1[85]; + + + /** Global configuration register (CFG_GCR at 0x7f60) */ + union { + + /// bytewise access to CFG_GCR + uint8_t byte; + + /// bitwise access to register CFG_GCR + struct { + BITS SWO : 1; // bit 0 + BITS AL : 1; // bit 1 + BITS : 6; // 6 bits + }; // CFG_GCR bitfield + + /// register _CPU_CFG_GCR reset value + #define sfr_CPU_CFG_GCR_RESET_VALUE ((uint8_t) 0x00) + + } CFG_GCR; + +} CPU_t; + +/// access to CPU SFR registers +#define sfr_CPU (*((CPU_t*) 0x7f00)) + + +//------------------------ +// Module DM +//------------------------ + +/** struct containing DM module registers */ +typedef struct { + + /** DM breakpoint 1 register extended byte (BK1RE at 0x7f90) */ + union { + + /// bytewise access to BK1RE + uint8_t byte; + + /// skip bitwise access to register BK1RE + + /// register _DM_BK1RE reset value + #define sfr_DM_BK1RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RE; + + + /** DM breakpoint 1 register high byte (BK1RH at 0x7f91) */ + union { + + /// bytewise access to BK1RH + uint8_t byte; + + /// skip bitwise access to register BK1RH + + /// register _DM_BK1RH reset value + #define sfr_DM_BK1RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RH; + + + /** DM breakpoint 1 register low byte (BK1RL at 0x7f92) */ + union { + + /// bytewise access to BK1RL + uint8_t byte; + + /// skip bitwise access to register BK1RL + + /// register _DM_BK1RL reset value + #define sfr_DM_BK1RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RL; + + + /** DM breakpoint 2 register extended byte (BK2RE at 0x7f93) */ + union { + + /// bytewise access to BK2RE + uint8_t byte; + + /// skip bitwise access to register BK2RE + + /// register _DM_BK2RE reset value + #define sfr_DM_BK2RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RE; + + + /** DM breakpoint 2 register high byte (BK2RH at 0x7f94) */ + union { + + /// bytewise access to BK2RH + uint8_t byte; + + /// skip bitwise access to register BK2RH + + /// register _DM_BK2RH reset value + #define sfr_DM_BK2RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RH; + + + /** DM breakpoint 2 register low byte (BK2RL at 0x7f95) */ + union { + + /// bytewise access to BK2RL + uint8_t byte; + + /// skip bitwise access to register BK2RL + + /// register _DM_BK2RL reset value + #define sfr_DM_BK2RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RL; + + + /** DM debug module control register 1 (CR1 at 0x7f96) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// skip bitwise access to register CR1 + + /// register _DM_CR1 reset value + #define sfr_DM_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** DM debug module control register 2 (CR2 at 0x7f97) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// skip bitwise access to register CR2 + + /// register _DM_CR2 reset value + #define sfr_DM_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** DM debug module control/status register 1 (CSR1 at 0x7f98) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// skip bitwise access to register CSR1 + + /// register _DM_CSR1 reset value + #define sfr_DM_CSR1_RESET_VALUE ((uint8_t) 0x10) + + } CSR1; + + + /** DM debug module control/status register 2 (CSR2 at 0x7f99) */ + union { + + /// bytewise access to CSR2 + uint8_t byte; + + /// skip bitwise access to register CSR2 + + /// register _DM_CSR2 reset value + #define sfr_DM_CSR2_RESET_VALUE ((uint8_t) 0x00) + + } CSR2; + + + /** DM enable function register (ENFCTR at 0x7f9a) */ + union { + + /// bytewise access to ENFCTR + uint8_t byte; + + /// skip bitwise access to register ENFCTR + + /// register _DM_ENFCTR reset value + #define sfr_DM_ENFCTR_RESET_VALUE ((uint8_t) 0xFF) + + } ENFCTR; + +} DM_t; + +/// access to DM SFR registers +#define sfr_DM (*((DM_t*) 0x7f90)) + + +//------------------------ +// Module FLASH +//------------------------ + +/** struct containing FLASH module registers */ +typedef struct { + + /** Flash control register 1 (CR1 at 0x505a) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS FIX : 1; // bit 0 + BITS IE : 1; // bit 1 + BITS AHALT : 1; // bit 2 + BITS HALT : 1; // bit 3 + BITS : 4; // 4 bits + }; // CR1 bitfield + + /// register _FLASH_CR1 reset value + #define sfr_FLASH_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Flash control register 2 (CR2 at 0x505b) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS FPRG : 1; // bit 4 + BITS ERASE : 1; // bit 5 + BITS WPRG : 1; // bit 6 + BITS OPT : 1; // bit 7 + }; // CR2 bitfield + + /// register _FLASH_CR2 reset value + #define sfr_FLASH_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** Flash complementary control register 2 (NCR2 at 0x505c) */ + union { + + /// bytewise access to NCR2 + uint8_t byte; + + /// bitwise access to register NCR2 + struct { + BITS NPRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS NFPRG : 1; // bit 4 + BITS NERASE : 1; // bit 5 + BITS NWPRG : 1; // bit 6 + BITS NOPT : 1; // bit 7 + }; // NCR2 bitfield + + /// register _FLASH_NCR2 reset value + #define sfr_FLASH_NCR2_RESET_VALUE ((uint8_t) 0xFF) + + } NCR2; + + + /** Flash protection register (FPR at 0x505d) */ + union { + + /// bytewise access to FPR + uint8_t byte; + + /// bitwise access to register FPR + struct { + BITS WPB0 : 1; // bit 0 + BITS WPB1 : 1; // bit 1 + BITS WPB2 : 1; // bit 2 + BITS WPB3 : 1; // bit 3 + BITS WPB4 : 1; // bit 4 + BITS WPB5 : 1; // bit 5 + BITS : 2; // 2 bits + }; // FPR bitfield + + /// register _FLASH_FPR reset value + #define sfr_FLASH_FPR_RESET_VALUE ((uint8_t) 0x00) + + } FPR; + + + /** Flash complementary protection register (NFPR at 0x505e) */ + union { + + /// bytewise access to NFPR + uint8_t byte; + + /// bitwise access to register NFPR + struct { + BITS NWPB0 : 1; // bit 0 + BITS NWPB1 : 1; // bit 1 + BITS NWPB2 : 1; // bit 2 + BITS NWPB3 : 1; // bit 3 + BITS NWPB4 : 1; // bit 4 + BITS NWPB5 : 1; // bit 5 + BITS : 2; // 2 bits + }; // NFPR bitfield + + /// register _FLASH_NFPR reset value + #define sfr_FLASH_NFPR_RESET_VALUE ((uint8_t) 0xFF) + + } NFPR; + + + /** Flash in-application programming status register (IAPSR at 0x505f) */ + union { + + /// bytewise access to IAPSR + uint8_t byte; + + /// bitwise access to register IAPSR + struct { + BITS WR_PG_DIS : 1; // bit 0 + BITS PUL : 1; // bit 1 + BITS EOP : 1; // bit 2 + BITS DUL : 1; // bit 3 + BITS : 2; // 2 bits + BITS HVOFF : 1; // bit 6 + BITS : 1; // 1 bit + }; // IAPSR bitfield + + /// register _FLASH_IAPSR reset value + #define sfr_FLASH_IAPSR_RESET_VALUE ((uint8_t) 0x00) + + } IAPSR; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** Flash Program memory unprotection register (PUKR at 0x5062) */ + union { + + /// bytewise access to PUKR + uint8_t byte; + + /// bitwise access to register PUKR + struct { + BITS MASS_PRG : 8; // bits 0-7 + }; // PUKR bitfield + + /// register _FLASH_PUKR reset value + #define sfr_FLASH_PUKR_RESET_VALUE ((uint8_t) 0x00) + + } PUKR; + + + /// Reserved register (1B) + uint8_t Reserved_2[1]; + + + /** Data EEPROM unprotection register (DUKR at 0x5064) */ + union { + + /// bytewise access to DUKR + uint8_t byte; + + /// bitwise access to register DUKR + struct { + BITS MASS_DATA : 8; // bits 0-7 + }; // DUKR bitfield + + /// register _FLASH_DUKR reset value + #define sfr_FLASH_DUKR_RESET_VALUE ((uint8_t) 0x00) + + } DUKR; + +} FLASH_t; + +/// access to FLASH SFR registers +#define sfr_FLASH (*((FLASH_t*) 0x505a)) + + +//------------------------ +// Module I2C +//------------------------ + +/** struct containing I2C module registers */ +typedef struct { + + /** I2C control register 1 (CR1 at 0x5210) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PE : 1; // bit 0 + BITS : 5; // 5 bits + BITS ENGC : 1; // bit 6 + BITS NOSTRETCH : 1; // bit 7 + }; // CR1 bitfield + + /// register _I2C_CR1 reset value + #define sfr_I2C_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** I2C control register 2 (CR2 at 0x5211) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS START : 1; // bit 0 + BITS STOP : 1; // bit 1 + BITS ACK : 1; // bit 2 + BITS POS : 1; // bit 3 + BITS : 3; // 3 bits + BITS SWRST : 1; // bit 7 + }; // CR2 bitfield + + /// register _I2C_CR2 reset value + #define sfr_I2C_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** I2C frequency register (FREQR at 0x5212) */ + union { + + /// bytewise access to FREQR + uint8_t byte; + + /// bitwise access to register FREQR + struct { + BITS FREQ : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // FREQR bitfield + + /// register _I2C_FREQR reset value + #define sfr_I2C_FREQR_RESET_VALUE ((uint8_t) 0x00) + + } FREQR; + + + /** I2C own address register low (OARL at 0x5213) */ + union { + + /// bytewise access to OARL + uint8_t byte; + + /// bitwise access to register OARL + struct { + BITS ADD0 : 1; // bit 0 + BITS ADD : 7; // bits 1-7 + }; // OARL bitfield + + /// register _I2C_OARL reset value + #define sfr_I2C_OARL_RESET_VALUE ((uint8_t) 0x00) + + } OARL; + + + /** I2C own address register high (OARH at 0x5214) */ + union { + + /// bytewise access to OARH + uint8_t byte; + + /// bitwise access to register OARH + struct { + BITS : 1; // 1 bit + BITS ADD : 2; // bits 1-2 + BITS : 3; // 3 bits + BITS ADDCONF : 1; // bit 6 + BITS ADDMODE : 1; // bit 7 + }; // OARH bitfield + + /// register _I2C_OARH reset value + #define sfr_I2C_OARH_RESET_VALUE ((uint8_t) 0x00) + + } OARH; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** I2C data register (DR at 0x5216) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _I2C_DR reset value + #define sfr_I2C_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** I2C status register 1 (SR1 at 0x5217) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS SB : 1; // bit 0 + BITS ADDR : 1; // bit 1 + BITS BTF : 1; // bit 2 + BITS ADD10 : 1; // bit 3 + BITS STOPF : 1; // bit 4 + BITS : 1; // 1 bit + BITS RXNE : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR1 bitfield + + /// register _I2C_SR1 reset value + #define sfr_I2C_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** I2C status register 2 (SR2 at 0x5218) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS BERR : 1; // bit 0 + BITS ARLO : 1; // bit 1 + BITS AF : 1; // bit 2 + BITS OVR : 1; // bit 3 + BITS : 1; // 1 bit + BITS WUFH : 1; // bit 5 + BITS : 2; // 2 bits + }; // SR2 bitfield + + /// register _I2C_SR2 reset value + #define sfr_I2C_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** I2C status register 3 (SR3 at 0x5219) */ + union { + + /// bytewise access to SR3 + uint8_t byte; + + /// bitwise access to register SR3 + struct { + BITS MSL : 1; // bit 0 + BITS BUSY : 1; // bit 1 + BITS TRA : 1; // bit 2 + BITS : 1; // 1 bit + BITS GENCALL : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR3 bitfield + + /// register _I2C_SR3 reset value + #define sfr_I2C_SR3_RESET_VALUE ((uint8_t) 0x00) + + } SR3; + + + /** I2C interrupt control register (ITR at 0x521a) */ + union { + + /// bytewise access to ITR + uint8_t byte; + + /// bitwise access to register ITR + struct { + BITS ITERREN : 1; // bit 0 + BITS ITEVTEN : 1; // bit 1 + BITS ITBUFEN : 1; // bit 2 + BITS : 5; // 5 bits + }; // ITR bitfield + + /// register _I2C_ITR reset value + #define sfr_I2C_ITR_RESET_VALUE ((uint8_t) 0x00) + + } ITR; + + + /** I2C clock control register low (CCRL at 0x521b) */ + union { + + /// bytewise access to CCRL + uint8_t byte; + + /// bitwise access to register CCRL + struct { + BITS CCR : 8; // bits 0-7 + }; // CCRL bitfield + + /// register _I2C_CCRL reset value + #define sfr_I2C_CCRL_RESET_VALUE ((uint8_t) 0x00) + + } CCRL; + + + /** I2C clock control register high (CCRH at 0x521c) */ + union { + + /// bytewise access to CCRH + uint8_t byte; + + /// bitwise access to register CCRH + struct { + BITS CCR : 4; // bits 0-3 + BITS : 2; // 2 bits + BITS DUTY : 1; // bit 6 + BITS F_S : 1; // bit 7 + }; // CCRH bitfield + + /// register _I2C_CCRH reset value + #define sfr_I2C_CCRH_RESET_VALUE ((uint8_t) 0x00) + + } CCRH; + + + /** I2C TRISE register (TRISER at 0x521d) */ + union { + + /// bytewise access to TRISER + uint8_t byte; + + /// bitwise access to register TRISER + struct { + BITS TRISE : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // TRISER bitfield + + /// register _I2C_TRISER reset value + #define sfr_I2C_TRISER_RESET_VALUE ((uint8_t) 0x02) + + } TRISER; + + + /** I2C packet error checking register (PECR at 0x521e) */ + union { + + /// bytewise access to PECR + uint8_t byte; + + /// skip bitwise access to register PECR + + /// register _I2C_PECR reset value + #define sfr_I2C_PECR_RESET_VALUE ((uint8_t) 0x00) + + } PECR; + +} I2C_t; + +/// access to I2C SFR registers +#define sfr_I2C (*((I2C_t*) 0x5210)) + + +//------------------------ +// Module ITC +//------------------------ + +/** struct containing ITC module registers */ +typedef struct { + + /** External interrupt control register 1 (CR1 at 0x50a0) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PAIS : 2; // bits 0-1 + BITS PBIS : 2; // bits 2-3 + BITS PCIS : 2; // bits 4-5 + BITS PDIS : 2; // bits 6-7 + }; // CR1 bitfield + + /// register _ITC_CR1 reset value + #define sfr_ITC_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** External interrupt control register 2 (CR2 at 0x50a1) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PEIS : 2; // bits 0-1 + BITS TLIS : 1; // bit 2 + BITS : 5; // 5 bits + }; // CR2 bitfield + + /// register _ITC_CR2 reset value + #define sfr_ITC_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /// Reserved register (11982B) + uint8_t Reserved_1[11982]; + + + /** Interrupt software priority register 1 (SPR1 at 0x7f70) */ + union { + + /// bytewise access to SPR1 + uint8_t byte; + + /// bitwise access to register SPR1 + struct { + BITS VECT0SPR : 2; // bits 0-1 + BITS VECT1SPR : 2; // bits 2-3 + BITS VECT2SPR : 2; // bits 4-5 + BITS VECT3SPR : 2; // bits 6-7 + }; // SPR1 bitfield + + /// register _ITC_SPR1 reset value + #define sfr_ITC_SPR1_RESET_VALUE ((uint8_t) 0xFF) + + } SPR1; + + + /** Interrupt software priority register 2 (SPR2 at 0x7f71) */ + union { + + /// bytewise access to SPR2 + uint8_t byte; + + /// bitwise access to register SPR2 + struct { + BITS VECT4SPR : 2; // bits 0-1 + BITS VECT5SPR : 2; // bits 2-3 + BITS VECT6SPR : 2; // bits 4-5 + BITS VECT7SPR : 2; // bits 6-7 + }; // SPR2 bitfield + + /// register _ITC_SPR2 reset value + #define sfr_ITC_SPR2_RESET_VALUE ((uint8_t) 0xFF) + + } SPR2; + + + /** Interrupt software priority register 3 (SPR3 at 0x7f72) */ + union { + + /// bytewise access to SPR3 + uint8_t byte; + + /// bitwise access to register SPR3 + struct { + BITS VECT8SPR : 2; // bits 0-1 + BITS VECT9SPR : 2; // bits 2-3 + BITS VECT10SPR : 2; // bits 4-5 + BITS VECT11SPR : 2; // bits 6-7 + }; // SPR3 bitfield + + /// register _ITC_SPR3 reset value + #define sfr_ITC_SPR3_RESET_VALUE ((uint8_t) 0xFF) + + } SPR3; + + + /** Interrupt software priority register 4 (SPR4 at 0x7f73) */ + union { + + /// bytewise access to SPR4 + uint8_t byte; + + /// bitwise access to register SPR4 + struct { + BITS VECT12SPR : 2; // bits 0-1 + BITS VECT13SPR : 2; // bits 2-3 + BITS VECT14SPR : 2; // bits 4-5 + BITS VECT15SPR : 2; // bits 6-7 + }; // SPR4 bitfield + + /// register _ITC_SPR4 reset value + #define sfr_ITC_SPR4_RESET_VALUE ((uint8_t) 0xFF) + + } SPR4; + + + /** Interrupt software priority register 5 (SPR5 at 0x7f74) */ + union { + + /// bytewise access to SPR5 + uint8_t byte; + + /// bitwise access to register SPR5 + struct { + BITS VECT16SPR : 2; // bits 0-1 + BITS VECT17SPR : 2; // bits 2-3 + BITS VECT18SPR : 2; // bits 4-5 + BITS VECT19SPR : 2; // bits 6-7 + }; // SPR5 bitfield + + /// register _ITC_SPR5 reset value + #define sfr_ITC_SPR5_RESET_VALUE ((uint8_t) 0xFF) + + } SPR5; + + + /** Interrupt software priority register 6 (SPR6 at 0x7f75) */ + union { + + /// bytewise access to SPR6 + uint8_t byte; + + /// bitwise access to register SPR6 + struct { + BITS VECT20SPR : 2; // bits 0-1 + BITS VECT21SPR : 2; // bits 2-3 + BITS VECT22SPR : 2; // bits 4-5 + BITS VECT23SPR : 2; // bits 6-7 + }; // SPR6 bitfield + + /// register _ITC_SPR6 reset value + #define sfr_ITC_SPR6_RESET_VALUE ((uint8_t) 0xFF) + + } SPR6; + + + /** Interrupt software priority register 7 (SPR7 at 0x7f76) */ + union { + + /// bytewise access to SPR7 + uint8_t byte; + + /// bitwise access to register SPR7 + struct { + BITS VECT24SPR : 2; // bits 0-1 + BITS VECT25SPR : 2; // bits 2-3 + BITS VECT26SPR : 2; // bits 4-5 + BITS VECT27SPR : 2; // bits 6-7 + }; // SPR7 bitfield + + /// register _ITC_SPR7 reset value + #define sfr_ITC_SPR7_RESET_VALUE ((uint8_t) 0xFF) + + } SPR7; + + + /** Interrupt software priority register 8 (SPR8 at 0x7f77) */ + union { + + /// bytewise access to SPR8 + uint8_t byte; + + /// bitwise access to register SPR8 + struct { + BITS VECT28SPR : 2; // bits 0-1 + BITS VECT29SPR : 2; // bits 2-3 + BITS : 4; // 4 bits + }; // SPR8 bitfield + + /// register _ITC_SPR8 reset value + #define sfr_ITC_SPR8_RESET_VALUE ((uint8_t) 0xFF) + + } SPR8; + +} ITC_t; + +/// access to ITC SFR registers +#define sfr_ITC (*((ITC_t*) 0x50a0)) + + +//------------------------ +// Module IWDG +//------------------------ + +/** struct containing IWDG module registers */ +typedef struct { + + /** IWDG key register (KR at 0x50e0) */ + union { + + /// bytewise access to KR + uint8_t byte; + + /// bitwise access to register KR + struct { + BITS KEY : 8; // bits 0-7 + }; // KR bitfield + + /// register _IWDG_KR reset value + #define sfr_IWDG_KR_RESET_VALUE ((uint8_t) 0x00) + + } KR; + + + /** IWDG prescaler register (PR at 0x50e1) */ + union { + + /// bytewise access to PR + uint8_t byte; + + /// bitwise access to register PR + struct { + BITS PR : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PR bitfield + + /// register _IWDG_PR reset value + #define sfr_IWDG_PR_RESET_VALUE ((uint8_t) 0x00) + + } PR; + + + /** IWDG reload register (RLR at 0x50e2) */ + union { + + /// bytewise access to RLR + uint8_t byte; + + /// bitwise access to register RLR + struct { + BITS RL : 8; // bits 0-7 + }; // RLR bitfield + + /// register _IWDG_RLR reset value + #define sfr_IWDG_RLR_RESET_VALUE ((uint8_t) 0xFF) + + } RLR; + +} IWDG_t; + +/// access to IWDG SFR registers +#define sfr_IWDG (*((IWDG_t*) 0x50e0)) + + +//------------------------ +// Module OPT +//------------------------ + +/** struct containing OPT module registers */ +typedef struct { + + /** Read-out protection (ROP) (OPT0 at 0x4800) */ + union { + + /// bytewise access to OPT0 + uint8_t byte; + + /// skip bitwise access to register OPT0 + + /// register _OPT_OPT0 reset value + #define sfr_OPT_OPT0_RESET_VALUE ((uint8_t) 0x00) + + } OPT0; + + + /** User boot code (UBC) (OPT1 at 0x4801) */ + union { + + /// bytewise access to OPT1 + uint8_t byte; + + /// skip bitwise access to register OPT1 + + /// register _OPT_OPT1 reset value + #define sfr_OPT_OPT1_RESET_VALUE ((uint8_t) 0x00) + + } OPT1; + + + /** User boot code (UBC) (complementary byte) (NOPT1 at 0x4802) */ + union { + + /// bytewise access to NOPT1 + uint8_t byte; + + /// skip bitwise access to register NOPT1 + + /// register _OPT_NOPT1 reset value + #define sfr_OPT_NOPT1_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT1; + + + /** Alternate function remapping (AFR) (OPT2 at 0x4803) */ + union { + + /// bytewise access to OPT2 + uint8_t byte; + + /// skip bitwise access to register OPT2 + + /// register _OPT_OPT2 reset value + #define sfr_OPT_OPT2_RESET_VALUE ((uint8_t) 0x00) + + } OPT2; + + + /** Alternate function remapping (AFR) (complementary byte) (NOPT2 at 0x4804) */ + union { + + /// bytewise access to NOPT2 + uint8_t byte; + + /// skip bitwise access to register NOPT2 + + /// register _OPT_NOPT2 reset value + #define sfr_OPT_NOPT2_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT2; + + + /** Watchdog option (OPT3 at 0x4805) */ + union { + + /// bytewise access to OPT3 + uint8_t byte; + + /// skip bitwise access to register OPT3 + + /// register _OPT_OPT3 reset value + #define sfr_OPT_OPT3_RESET_VALUE ((uint8_t) 0x00) + + } OPT3; + + + /** Watchdog option (complementary byte) (NOPT3 at 0x4806) */ + union { + + /// bytewise access to NOPT3 + uint8_t byte; + + /// skip bitwise access to register NOPT3 + + /// register _OPT_NOPT3 reset value + #define sfr_OPT_NOPT3_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT3; + + + /** Clock option (OPT4 at 0x4807) */ + union { + + /// bytewise access to OPT4 + uint8_t byte; + + /// skip bitwise access to register OPT4 + + /// register _OPT_OPT4 reset value + #define sfr_OPT_OPT4_RESET_VALUE ((uint8_t) 0x00) + + } OPT4; + + + /** Clock option (complementary byte) (NOPT4 at 0x4808) */ + union { + + /// bytewise access to NOPT4 + uint8_t byte; + + /// skip bitwise access to register NOPT4 + + /// register _OPT_NOPT4 reset value + #define sfr_OPT_NOPT4_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT4; + + + /** HSE clock startup (OPT5 at 0x4809) */ + union { + + /// bytewise access to OPT5 + uint8_t byte; + + /// skip bitwise access to register OPT5 + + /// register _OPT_OPT5 reset value + #define sfr_OPT_OPT5_RESET_VALUE ((uint8_t) 0x00) + + } OPT5; + + + /** HSE clock startup (complementary byte) (NOPT5 at 0x480a) */ + union { + + /// bytewise access to NOPT5 + uint8_t byte; + + /// skip bitwise access to register NOPT5 + + /// register _OPT_NOPT5 reset value + #define sfr_OPT_NOPT5_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT5; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** Flash wait states (OPT7 at 0x480d) */ + union { + + /// bytewise access to OPT7 + uint8_t byte; + + /// skip bitwise access to register OPT7 + + /// register _OPT_OPT7 reset value + #define sfr_OPT_OPT7_RESET_VALUE ((uint8_t) 0x00) + + } OPT7; + + + /** Flash wait states (complementary byte) (NOPT7 at 0x480e) */ + union { + + /// bytewise access to NOPT7 + uint8_t byte; + + /// skip bitwise access to register NOPT7 + + /// register _OPT_NOPT7 reset value + #define sfr_OPT_NOPT7_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT7; + + + /// Reserved register (111B) + uint8_t Reserved_2[111]; + + + /** Bootloader (OPTBL at 0x487e) */ + union { + + /// bytewise access to OPTBL + uint8_t byte; + + /// skip bitwise access to register OPTBL + + /// register _OPT_OPTBL reset value + #define sfr_OPT_OPTBL_RESET_VALUE ((uint8_t) 0x00) + + } OPTBL; + + + /** Bootloader (complementary byte) (NOPTBL at 0x487f) */ + union { + + /// bytewise access to NOPTBL + uint8_t byte; + + /// skip bitwise access to register NOPTBL + + /// register _OPT_NOPTBL reset value + #define sfr_OPT_NOPTBL_RESET_VALUE ((uint8_t) 0xFF) + + } NOPTBL; + +} OPT_t; + +/// access to OPT SFR registers +#define sfr_OPT (*((OPT_t*) 0x4800)) + + +//------------------------ +// Module PORT +//------------------------ + +/** struct containing PORTA module registers */ +typedef struct { + + /** Port A data output latch register (ODR at 0x5000) */ + union { + + /// bytewise access to ODR + uint8_t byte; + + /// bitwise access to register ODR + struct { + BITS ODR0 : 1; // bit 0 + BITS ODR1 : 1; // bit 1 + BITS ODR2 : 1; // bit 2 + BITS ODR3 : 1; // bit 3 + BITS ODR4 : 1; // bit 4 + BITS ODR5 : 1; // bit 5 + BITS ODR6 : 1; // bit 6 + BITS ODR7 : 1; // bit 7 + }; // ODR bitfield + + /// register _PORT_ODR reset value + #define sfr_PORT_ODR_RESET_VALUE ((uint8_t) 0x00) + + } ODR; + + + /** Port A input pin value register (IDR at 0x5001) */ + union { + + /// bytewise access to IDR + uint8_t byte; + + /// bitwise access to register IDR + struct { + BITS IDR0 : 1; // bit 0 + BITS IDR1 : 1; // bit 1 + BITS IDR2 : 1; // bit 2 + BITS IDR3 : 1; // bit 3 + BITS IDR4 : 1; // bit 4 + BITS IDR5 : 1; // bit 5 + BITS IDR6 : 1; // bit 6 + BITS IDR7 : 1; // bit 7 + }; // IDR bitfield + + /// register _PORT_IDR reset value + #define sfr_PORT_IDR_RESET_VALUE ((uint8_t) 0x00) + + } IDR; + + + /** Port A data direction register (DDR at 0x5002) */ + union { + + /// bytewise access to DDR + uint8_t byte; + + /// bitwise access to register DDR + struct { + BITS DDR0 : 1; // bit 0 + BITS DDR1 : 1; // bit 1 + BITS DDR2 : 1; // bit 2 + BITS DDR3 : 1; // bit 3 + BITS DDR4 : 1; // bit 4 + BITS DDR5 : 1; // bit 5 + BITS DDR6 : 1; // bit 6 + BITS DDR7 : 1; // bit 7 + }; // DDR bitfield + + /// register _PORT_DDR reset value + #define sfr_PORT_DDR_RESET_VALUE ((uint8_t) 0x00) + + } DDR; + + + /** Port A control register 1 (CR1 at 0x5003) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS C10 : 1; // bit 0 + BITS C11 : 1; // bit 1 + BITS C12 : 1; // bit 2 + BITS C13 : 1; // bit 3 + BITS C14 : 1; // bit 4 + BITS C15 : 1; // bit 5 + BITS C16 : 1; // bit 6 + BITS C17 : 1; // bit 7 + }; // CR1 bitfield + + /// register _PORT_CR1 reset value + #define sfr_PORT_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Port A control register 2 (CR2 at 0x5004) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS C20 : 1; // bit 0 + BITS C21 : 1; // bit 1 + BITS C22 : 1; // bit 2 + BITS C23 : 1; // bit 3 + BITS C24 : 1; // bit 4 + BITS C25 : 1; // bit 5 + BITS C26 : 1; // bit 6 + BITS C27 : 1; // bit 7 + }; // CR2 bitfield + + /// register _PORT_CR2 reset value + #define sfr_PORT_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + +} PORT_t; + +/// access to PORTA SFR registers +#define sfr_PORTA (*((PORT_t*) 0x5000)) + + +/// access to PORTB SFR registers +#define sfr_PORTB (*((PORT_t*) 0x5005)) + + +/// access to PORTC SFR registers +#define sfr_PORTC (*((PORT_t*) 0x500a)) + + +/// access to PORTD SFR registers +#define sfr_PORTD (*((PORT_t*) 0x500f)) + + +/// access to PORTE SFR registers +#define sfr_PORTE (*((PORT_t*) 0x5014)) + + +/// access to PORTF SFR registers +#define sfr_PORTF (*((PORT_t*) 0x5019)) + + +/// access to PORTG SFR registers +#define sfr_PORTG (*((PORT_t*) 0x501e)) + + +/// access to PORTH SFR registers +#define sfr_PORTH (*((PORT_t*) 0x5023)) + + +/// access to PORTI SFR registers +#define sfr_PORTI (*((PORT_t*) 0x5028)) + + +//------------------------ +// Module RST +//------------------------ + +/** struct containing RST module registers */ +typedef struct { + + /** Reset status register (SR at 0x50b3) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS WWDGF : 1; // bit 0 + BITS IWDGF : 1; // bit 1 + BITS ILLOPF : 1; // bit 2 + BITS SWIMF : 1; // bit 3 + BITS EMCF : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR bitfield + + /// register _RST_SR reset value + #define sfr_RST_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + +} RST_t; + +/// access to RST SFR registers +#define sfr_RST (*((RST_t*) 0x50b3)) + + +//------------------------ +// Module SPI +//------------------------ + +/** struct containing SPI module registers */ +typedef struct { + + /** SPI control register 1 (CR1 at 0x5200) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CPHA : 1; // bit 0 + BITS CPOL : 1; // bit 1 + BITS MSTR : 1; // bit 2 + BITS BR : 3; // bits 3-5 + BITS SPE : 1; // bit 6 + BITS LSBFIRST : 1; // bit 7 + }; // CR1 bitfield + + /// register _SPI_CR1 reset value + #define sfr_SPI_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** SPI control register 2 (CR2 at 0x5201) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SSI : 1; // bit 0 + BITS SSM : 1; // bit 1 + BITS RXONLY : 1; // bit 2 + BITS : 1; // 1 bit + BITS CRCNEXT : 1; // bit 4 + BITS CECEN : 1; // bit 5 + BITS BDOE : 1; // bit 6 + BITS BDM : 1; // bit 7 + }; // CR2 bitfield + + /// register _SPI_CR2 reset value + #define sfr_SPI_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** SPI interrupt control register (ICR at 0x5202) */ + union { + + /// bytewise access to ICR + uint8_t byte; + + /// bitwise access to register ICR + struct { + BITS : 4; // 4 bits + BITS WKIE : 1; // bit 4 + BITS ERRIE : 1; // bit 5 + BITS RXIE : 1; // bit 6 + BITS TXIE : 1; // bit 7 + }; // ICR bitfield + + /// register _SPI_ICR reset value + #define sfr_SPI_ICR_RESET_VALUE ((uint8_t) 0x00) + + } ICR; + + + /** SPI status register (SR at 0x5203) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS RXNE : 1; // bit 0 + BITS TXE : 1; // bit 1 + BITS : 1; // 1 bit + BITS WKUP : 1; // bit 3 + BITS CRCERR : 1; // bit 4 + BITS MODF : 1; // bit 5 + BITS OVR : 1; // bit 6 + BITS BSY : 1; // bit 7 + }; // SR bitfield + + /// register _SPI_SR reset value + #define sfr_SPI_SR_RESET_VALUE ((uint8_t) 0x02) + + } SR; + + + /** SPI data register (DR at 0x5204) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _SPI_DR reset value + #define sfr_SPI_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** SPI CRC polynomial register (CRCPR at 0x5205) */ + union { + + /// bytewise access to CRCPR + uint8_t byte; + + /// bitwise access to register CRCPR + struct { + BITS CRCPOLY : 8; // bits 0-7 + }; // CRCPR bitfield + + /// register _SPI_CRCPR reset value + #define sfr_SPI_CRCPR_RESET_VALUE ((uint8_t) 0x07) + + } CRCPR; + + + /** SPI Rx CRC register (RXCRCR at 0x5206) */ + union { + + /// bytewise access to RXCRCR + uint8_t byte; + + /// bitwise access to register RXCRCR + struct { + BITS RXCRC : 8; // bits 0-7 + }; // RXCRCR bitfield + + /// register _SPI_RXCRCR reset value + #define sfr_SPI_RXCRCR_RESET_VALUE ((uint8_t) 0xFF) + + } RXCRCR; + + + /** SPI Tx CRC register (TXCRCR at 0x5207) */ + union { + + /// bytewise access to TXCRCR + uint8_t byte; + + /// bitwise access to register TXCRCR + struct { + BITS TXCRC : 8; // bits 0-7 + }; // TXCRCR bitfield + + /// register _SPI_TXCRCR reset value + #define sfr_SPI_TXCRCR_RESET_VALUE ((uint8_t) 0xFF) + + } TXCRCR; + +} SPI_t; + +/// access to SPI SFR registers +#define sfr_SPI (*((SPI_t*) 0x5200)) + + +//------------------------ +// Module SWIM +//------------------------ + +/** struct containing SWIM module registers */ +typedef struct { + + /** SWIM control status register (CSR at 0x7f80) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// skip bitwise access to register CSR + + /// register _SWIM_CSR reset value + #define sfr_SWIM_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + +} SWIM_t; + +/// access to SWIM SFR registers +#define sfr_SWIM (*((SWIM_t*) 0x7f80)) + + +//------------------------ +// Module TIM1 +//------------------------ + +/** struct containing TIM1 module registers */ +typedef struct { + + /** TIM1 control register 1 (CR1 at 0x5250) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS DIR : 1; // bit 4 + BITS CMS : 2; // bits 5-6 + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM1_CR1 reset value + #define sfr_TIM1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM1 control register 2 (CR2 at 0x5251) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS CCPG : 1; // bit 0 + BITS : 1; // 1 bit + BITS COMS : 1; // bit 2 + BITS : 1; // 1 bit + BITS MMS : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _TIM1_CR2 reset value + #define sfr_TIM1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** TIM1 slave mode control register (SMCR at 0x5252) */ + union { + + /// bytewise access to SMCR + uint8_t byte; + + /// bitwise access to register SMCR + struct { + BITS SMS : 3; // bits 0-2 + BITS : 1; // 1 bit + BITS TS : 3; // bits 4-6 + BITS MSM : 1; // bit 7 + }; // SMCR bitfield + + /// register _TIM1_SMCR reset value + #define sfr_TIM1_SMCR_RESET_VALUE ((uint8_t) 0x00) + + } SMCR; + + + /** TIM1 external trigger register (ETR at 0x5253) */ + union { + + /// bytewise access to ETR + uint8_t byte; + + /// bitwise access to register ETR + struct { + BITS ETF : 4; // bits 0-3 + BITS ETPS : 2; // bits 4-5 + BITS ECE : 1; // bit 6 + BITS ETP : 1; // bit 7 + }; // ETR bitfield + + /// register _TIM1_ETR reset value + #define sfr_TIM1_ETR_RESET_VALUE ((uint8_t) 0x00) + + } ETR; + + + /** TIM1 Interrupt enable register (IER at 0x5254) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS CC4IE : 1; // bit 4 + BITS COMIE : 1; // bit 5 + BITS TIE : 1; // bit 6 + BITS BIE : 1; // bit 7 + }; // IER bitfield + + /// register _TIM1_IER reset value + #define sfr_TIM1_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM1 status register 1 (SR1 at 0x5255) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS CC4IF : 1; // bit 4 + BITS COMIF : 1; // bit 5 + BITS TIF : 1; // bit 6 + BITS BIF : 1; // bit 7 + }; // SR1 bitfield + + /// register _TIM1_SR1 reset value + #define sfr_TIM1_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM1 status register 2 (SR2 at 0x5256) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS CC4OF : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR2 bitfield + + /// register _TIM1_SR2 reset value + #define sfr_TIM1_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM1 event generation register (EGR at 0x5257) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS CC4G : 1; // bit 4 + BITS COMG : 1; // bit 5 + BITS TG : 1; // bit 6 + BITS BG : 1; // bit 7 + }; // EGR bitfield + + /// register _TIM1_EGR reset value + #define sfr_TIM1_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM1 capture/compare mode register 1 (CCMR1 at 0x5258) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS OC1FE : 1; // bit 2 + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS OC1CE : 1; // bit 7 + }; // CCMR1 bitfield + + /// register _TIM1_CCMR1 reset value + #define sfr_TIM1_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM1 capture/compare mode register 2 (CCMR2 at 0x5259) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS OC2FE : 1; // bit 2 + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS OC2CE : 1; // bit 7 + }; // CCMR2 bitfield + + /// register _TIM1_CCMR2 reset value + #define sfr_TIM1_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM1 capture/compare mode register 3 (CCMR3 at 0x525a) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS OC3FE : 1; // bit 2 + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS OC3CE : 1; // bit 7 + }; // CCMR3 bitfield + + /// register _TIM1_CCMR3 reset value + #define sfr_TIM1_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM1 capture/compare mode register 4 (CCMR4 at 0x525b) */ + union { + + /// bytewise access to CCMR4 + uint8_t byte; + + /// bitwise access to register CCMR4 + struct { + BITS CC4S : 2; // bits 0-1 + BITS OC4FE : 1; // bit 2 + BITS OC4PE : 1; // bit 3 + BITS OC4M : 3; // bits 4-6 + BITS OC4CE : 1; // bit 7 + }; // CCMR4 bitfield + + /// register _TIM1_CCMR4 reset value + #define sfr_TIM1_CCMR4_RESET_VALUE ((uint8_t) 0x00) + + } CCMR4; + + + /** TIM1 capture/compare enable register 1 (CCER1 at 0x525c) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS CC1NE : 1; // bit 2 + BITS CC1NP : 1; // bit 3 + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS CC2NE : 1; // bit 6 + BITS CC2NP : 1; // bit 7 + }; // CCER1 bitfield + + /// register _TIM1_CCER1 reset value + #define sfr_TIM1_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM1 capture/compare enable register 2 (CCER2 at 0x525d) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS CC3NE : 1; // bit 2 + BITS CC3NP : 1; // bit 3 + BITS CC4E : 1; // bit 4 + BITS CC4P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER2 bitfield + + /// register _TIM1_CCER2 reset value + #define sfr_TIM1_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM1 counter high (CNTRH at 0x525e) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM1_CNTRH reset value + #define sfr_TIM1_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM1 counter low (CNTRL at 0x525f) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM1_CNTRL reset value + #define sfr_TIM1_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM1 prescaler register high (PSCRH at 0x5260) */ + union { + + /// bytewise access to PSCRH + uint8_t byte; + + /// bitwise access to register PSCRH + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCRH bitfield + + /// register _TIM1_PSCRH reset value + #define sfr_TIM1_PSCRH_RESET_VALUE ((uint8_t) 0x00) + + } PSCRH; + + + /** TIM1 prescaler register low (PSCRL at 0x5261) */ + union { + + /// bytewise access to PSCRL + uint8_t byte; + + /// bitwise access to register PSCRL + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCRL bitfield + + /// register _TIM1_PSCRL reset value + #define sfr_TIM1_PSCRL_RESET_VALUE ((uint8_t) 0x00) + + } PSCRL; + + + /** TIM1 auto-reload register high (ARRH at 0x5262) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM1_ARRH reset value + #define sfr_TIM1_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM1 auto-reload register low (ARRL at 0x5263) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM1_ARRL reset value + #define sfr_TIM1_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM1 repetition counter register (RCR at 0x5264) */ + union { + + /// bytewise access to RCR + uint8_t byte; + + /// bitwise access to register RCR + struct { + BITS REP : 8; // bits 0-7 + }; // RCR bitfield + + /// register _TIM1_RCR reset value + #define sfr_TIM1_RCR_RESET_VALUE ((uint8_t) 0x00) + + } RCR; + + + /** TIM1 capture/compare register 1 high (CCR1H at 0x5265) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM1_CCR1H reset value + #define sfr_TIM1_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM1 capture/compare register 1 low (CCR1L at 0x5266) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM1_CCR1L reset value + #define sfr_TIM1_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM1 capture/compare register 2 high (CCR2H at 0x5267) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM1_CCR2H reset value + #define sfr_TIM1_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM1 capture/compare register 2 low (CCR2L at 0x5268) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM1_CCR2L reset value + #define sfr_TIM1_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM1 capture/compare register 3 high (CCR3H at 0x5269) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3H bitfield + + /// register _TIM1_CCR3H reset value + #define sfr_TIM1_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM1 capture/compare register 3 low (CCR3L at 0x526a) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3L bitfield + + /// register _TIM1_CCR3L reset value + #define sfr_TIM1_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + + + /** TIM1 capture/compare register 4 high (CCR4H at 0x526b) */ + union { + + /// bytewise access to CCR4H + uint8_t byte; + + /// bitwise access to register CCR4H + struct { + BITS CCR4 : 8; // bits 0-7 + }; // CCR4H bitfield + + /// register _TIM1_CCR4H reset value + #define sfr_TIM1_CCR4H_RESET_VALUE ((uint8_t) 0x00) + + } CCR4H; + + + /** TIM1 capture/compare register 4 low (CCR4L at 0x526c) */ + union { + + /// bytewise access to CCR4L + uint8_t byte; + + /// bitwise access to register CCR4L + struct { + BITS CCR4 : 8; // bits 0-7 + }; // CCR4L bitfield + + /// register _TIM1_CCR4L reset value + #define sfr_TIM1_CCR4L_RESET_VALUE ((uint8_t) 0x00) + + } CCR4L; + + + /** TIM1 break register (BKR at 0x526d) */ + union { + + /// bytewise access to BKR + uint8_t byte; + + /// bitwise access to register BKR + struct { + BITS LOCK : 2; // bits 0-1 + BITS OSSI : 1; // bit 2 + BITS OSSR : 1; // bit 3 + BITS BKE : 1; // bit 4 + BITS BKP : 1; // bit 5 + BITS AOE : 1; // bit 6 + BITS MOE : 1; // bit 7 + }; // BKR bitfield + + /// register _TIM1_BKR reset value + #define sfr_TIM1_BKR_RESET_VALUE ((uint8_t) 0x00) + + } BKR; + + + /** TIM1 dead-time register (DTR at 0x526e) */ + union { + + /// bytewise access to DTR + uint8_t byte; + + /// bitwise access to register DTR + struct { + BITS DTG : 8; // bits 0-7 + }; // DTR bitfield + + /// register _TIM1_DTR reset value + #define sfr_TIM1_DTR_RESET_VALUE ((uint8_t) 0x00) + + } DTR; + + + /** TIM1 output idle state register (OISR at 0x526f) */ + union { + + /// bytewise access to OISR + uint8_t byte; + + /// bitwise access to register OISR + struct { + BITS OIS1 : 1; // bit 0 + BITS OIS1N : 1; // bit 1 + BITS OIS2 : 1; // bit 2 + BITS OIS2N : 1; // bit 3 + BITS OIS3 : 1; // bit 4 + BITS OIS3N : 1; // bit 5 + BITS OIS4 : 1; // bit 6 + BITS : 1; // 1 bit + }; // OISR bitfield + + /// register _TIM1_OISR reset value + #define sfr_TIM1_OISR_RESET_VALUE ((uint8_t) 0x00) + + } OISR; + +} TIM1_t; + +/// access to TIM1 SFR registers +#define sfr_TIM1 (*((TIM1_t*) 0x5250)) + + +//------------------------ +// Module TIM2 +//------------------------ + +/** struct containing TIM2 module registers */ +typedef struct { + + /** TIM2 control register 1 (CR1 at 0x5300) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM2_CR1 reset value + #define sfr_TIM2_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM2 interrupt enable register (IER at 0x5301) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM2_IER reset value + #define sfr_TIM2_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM2 status register 1 (SR1 at 0x5302) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR1 bitfield + + /// register _TIM2_SR1 reset value + #define sfr_TIM2_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM2 status register 2 (SR2 at 0x5303) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SR2 bitfield + + /// register _TIM2_SR2 reset value + #define sfr_TIM2_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM2 event generation register (EGR at 0x5304) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS : 2; // 2 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM2_EGR reset value + #define sfr_TIM2_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM2 capture/compare mode register 1 (CCMR1 at 0x5305) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM2_CCMR1 reset value + #define sfr_TIM2_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM2 capture/compare mode register 2 (CCMR2 at 0x5306) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM2_CCMR2 reset value + #define sfr_TIM2_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM2 capture/compare mode register 3 (CCMR3 at 0x5307) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR3 bitfield + + /// register _TIM2_CCMR3 reset value + #define sfr_TIM2_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM2 capture/compare enable register 1 (CCER1 at 0x5308) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM2_CCER1 reset value + #define sfr_TIM2_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM2 capture/compare enable register 2 (CCER2 at 0x5309) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS : 6; // 6 bits + }; // CCER2 bitfield + + /// register _TIM2_CCER2 reset value + #define sfr_TIM2_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM2 counter high (CNTRH at 0x530a) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM2_CNTRH reset value + #define sfr_TIM2_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM2 counter low (CNTRL at 0x530b) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM2_CNTRL reset value + #define sfr_TIM2_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM2 prescaler register (PSCR at 0x530c) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // PSCR bitfield + + /// register _TIM2_PSCR reset value + #define sfr_TIM2_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM2 auto-reload register high (ARRH at 0x530d) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM2_ARRH reset value + #define sfr_TIM2_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM2 auto-reload register low (ARRL at 0x530e) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM2_ARRL reset value + #define sfr_TIM2_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM2 capture/compare register 1 high (CCR1H at 0x530f) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM2_CCR1H reset value + #define sfr_TIM2_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM2 capture/compare register 1 low (CCR1L at 0x5310) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM2_CCR1L reset value + #define sfr_TIM2_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM2 capture/compare reg (CCR2H at 0x5311) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM2_CCR2H reset value + #define sfr_TIM2_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM2 capture/compare register 2 low (CCR2L at 0x5312) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM2_CCR2L reset value + #define sfr_TIM2_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM2 capture/compare register 3 high (CCR3H at 0x5313) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3H bitfield + + /// register _TIM2_CCR3H reset value + #define sfr_TIM2_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM2 capture/compare register 3 low (CCR3L at 0x5314) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3L bitfield + + /// register _TIM2_CCR3L reset value + #define sfr_TIM2_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + +} TIM2_t; + +/// access to TIM2 SFR registers +#define sfr_TIM2 (*((TIM2_t*) 0x5300)) + + +//------------------------ +// Module TIM3 +//------------------------ + +/** struct containing TIM3 module registers */ +typedef struct { + + /** TIM3 control register 1 (CR1 at 0x5320) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM3_CR1 reset value + #define sfr_TIM3_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM3 interrupt enable register (IER at 0x5321) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM3_IER reset value + #define sfr_TIM3_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM3 status register 1 (SR1 at 0x5322) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR1 bitfield + + /// register _TIM3_SR1 reset value + #define sfr_TIM3_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM3 status register 2 (SR2 at 0x5323) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SR2 bitfield + + /// register _TIM3_SR2 reset value + #define sfr_TIM3_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM3 event generation register (EGR at 0x5324) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS : 2; // 2 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM3_EGR reset value + #define sfr_TIM3_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM3 capture/compare mode register 1 (CCMR1 at 0x5325) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM3_CCMR1 reset value + #define sfr_TIM3_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM3 capture/compare mode register 2 (CCMR2 at 0x5326) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM3_CCMR2 reset value + #define sfr_TIM3_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM3 capture/compare enable register 1 (CCER1 at 0x5327) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM3_CCER1 reset value + #define sfr_TIM3_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM3 counter high (CNTRH at 0x5328) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM3_CNTRH reset value + #define sfr_TIM3_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM3 counter low (CNTRL at 0x5329) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM3_CNTRL reset value + #define sfr_TIM3_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM3 prescaler register (PSCR at 0x532a) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // PSCR bitfield + + /// register _TIM3_PSCR reset value + #define sfr_TIM3_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM3 auto-reload register high (ARRH at 0x532b) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM3_ARRH reset value + #define sfr_TIM3_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM3 auto-reload register low (ARRL at 0x532c) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM3_ARRL reset value + #define sfr_TIM3_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM3 capture/compare register 1 high (CCR1H at 0x532d) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM3_CCR1H reset value + #define sfr_TIM3_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM3 capture/compare register 1 low (CCR1L at 0x532e) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM3_CCR1L reset value + #define sfr_TIM3_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM3 capture/compare register 2 high (CCR2H at 0x532f) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM3_CCR2H reset value + #define sfr_TIM3_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM3 capture/compare register 2 low (CCR2L at 0x5330) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM3_CCR2L reset value + #define sfr_TIM3_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + +} TIM3_t; + +/// access to TIM3 SFR registers +#define sfr_TIM3 (*((TIM3_t*) 0x5320)) + + +//------------------------ +// Module TIM4 +//------------------------ + +/** struct containing TIM4 module registers */ +typedef struct { + + /** TIM4 control register 1 (CR1 at 0x5340) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM4_CR1 reset value + #define sfr_TIM4_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM4 interrupt enable register (IER at 0x5341) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM4_IER reset value + #define sfr_TIM4_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM4 status register (SR at 0x5342) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS UIF : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR bitfield + + /// register _TIM4_SR reset value + #define sfr_TIM4_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + + + /** TIM4 event generation register (EGR at 0x5343) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS : 5; // 5 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM4_EGR reset value + #define sfr_TIM4_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM4 counter (CNTR at 0x5344) */ + union { + + /// bytewise access to CNTR + uint8_t byte; + + /// bitwise access to register CNTR + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTR bitfield + + /// register _TIM4_CNTR reset value + #define sfr_TIM4_CNTR_RESET_VALUE ((uint8_t) 0x00) + + } CNTR; + + + /** TIM4 prescaler register (PSCR at 0x5345) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PSCR bitfield + + /// register _TIM4_PSCR reset value + #define sfr_TIM4_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM4 auto-reload register (ARR at 0x5346) */ + union { + + /// bytewise access to ARR + uint8_t byte; + + /// bitwise access to register ARR + struct { + BITS ARR : 8; // bits 0-7 + }; // ARR bitfield + + /// register _TIM4_ARR reset value + #define sfr_TIM4_ARR_RESET_VALUE ((uint8_t) 0xFF) + + } ARR; + +} TIM4_t; + +/// access to TIM4 SFR registers +#define sfr_TIM4 (*((TIM4_t*) 0x5340)) + + +//------------------------ +// Module UART1 +//------------------------ + +/** struct containing UART1 module registers */ +typedef struct { + + /** UART1 status register (SR at 0x5230) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS PE : 1; // bit 0 + BITS FE : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS OR_LHE : 1; // bit 3 + BITS IDLE : 1; // bit 4 + BITS RXNE : 1; // bit 5 + BITS TC : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR bitfield + + /// register _UART1_SR reset value + #define sfr_UART1_SR_RESET_VALUE ((uint8_t) 0xC0) + + } SR; + + + /** UART1 data register (DR at 0x5231) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _UART1_DR reset value + #define sfr_UART1_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** UART1 baud rate register 1 (BRR1 at 0x5232) */ + union { + + /// bytewise access to BRR1 + uint8_t byte; + + /// bitwise access to register BRR1 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR1 bitfield + + /// register _UART1_BRR1 reset value + #define sfr_UART1_BRR1_RESET_VALUE ((uint8_t) 0x00) + + } BRR1; + + + /** UART1 baud rate register 2 (BRR2 at 0x5233) */ + union { + + /// bytewise access to BRR2 + uint8_t byte; + + /// bitwise access to register BRR2 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR2 bitfield + + /// register _UART1_BRR2 reset value + #define sfr_UART1_BRR2_RESET_VALUE ((uint8_t) 0x00) + + } BRR2; + + + /** UART1 control register 1 (CR1 at 0x5234) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PIEN : 1; // bit 0 + BITS PS : 1; // bit 1 + BITS PCEN : 1; // bit 2 + BITS WAKE : 1; // bit 3 + BITS M : 1; // bit 4 + BITS UART0 : 1; // bit 5 + BITS T8 : 1; // bit 6 + BITS R8 : 1; // bit 7 + }; // CR1 bitfield + + /// register _UART1_CR1 reset value + #define sfr_UART1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** UART1 control register 2 (CR2 at 0x5235) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SBK : 1; // bit 0 + BITS RWU : 1; // bit 1 + BITS REN : 1; // bit 2 + BITS TEN : 1; // bit 3 + BITS ILIEN : 1; // bit 4 + BITS RIEN : 1; // bit 5 + BITS TCIEN : 1; // bit 6 + BITS TIEN : 1; // bit 7 + }; // CR2 bitfield + + /// register _UART1_CR2 reset value + #define sfr_UART1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** UART1 control register 3 (CR3 at 0x5236) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS LBCL : 1; // bit 0 + BITS CPHA : 1; // bit 1 + BITS CPOL : 1; // bit 2 + BITS CKEN : 1; // bit 3 + BITS STOP : 2; // bits 4-5 + BITS : 1; // 1 bit + BITS LINEN : 1; // bit 7 + }; // CR3 bitfield + + /// register _UART1_CR3 reset value + #define sfr_UART1_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** UART1 control register 4 (CR4 at 0x5237) */ + union { + + /// bytewise access to CR4 + uint8_t byte; + + /// bitwise access to register CR4 + struct { + BITS ADD : 4; // bits 0-3 + BITS LBDF : 1; // bit 4 + BITS LBDL : 1; // bit 5 + BITS LBDIEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR4 bitfield + + /// register _UART1_CR4 reset value + #define sfr_UART1_CR4_RESET_VALUE ((uint8_t) 0x00) + + } CR4; + + + /** UART1 control register 5 (CR5 at 0x5238) */ + union { + + /// bytewise access to CR5 + uint8_t byte; + + /// bitwise access to register CR5 + struct { + BITS : 1; // 1 bit + BITS IREN : 1; // bit 1 + BITS IRLP : 1; // bit 2 + BITS HDSEL : 1; // bit 3 + BITS NACK : 1; // bit 4 + BITS SCEN : 1; // bit 5 + BITS : 2; // 2 bits + }; // CR5 bitfield + + /// register _UART1_CR5 reset value + #define sfr_UART1_CR5_RESET_VALUE ((uint8_t) 0x00) + + } CR5; + + + /** UART1 guard time register (GTR at 0x5239) */ + union { + + /// bytewise access to GTR + uint8_t byte; + + /// bitwise access to register GTR + struct { + BITS GT : 8; // bits 0-7 + }; // GTR bitfield + + /// register _UART1_GTR reset value + #define sfr_UART1_GTR_RESET_VALUE ((uint8_t) 0x00) + + } GTR; + + + /** UART1 prescaler register (PSCR at 0x523a) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCR bitfield + + /// register _UART1_PSCR reset value + #define sfr_UART1_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + +} UART1_t; + +/// access to UART1 SFR registers +#define sfr_UART1 (*((UART1_t*) 0x5230)) + + +//------------------------ +// Module UART3 +//------------------------ + +/** struct containing UART3 module registers */ +typedef struct { + + /** UART3 status register (SR at 0x5240) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS PE : 1; // bit 0 + BITS FE : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS OR : 1; // bit 3 + BITS IDLE : 1; // bit 4 + BITS RXNE : 1; // bit 5 + BITS TC : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR bitfield + + /// register _UART3_SR reset value + #define sfr_UART3_SR_RESET_VALUE ((uint8_t) 0xC0) + + } SR; + + + /** UART3 data register (DR at 0x5241) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _UART3_DR reset value + #define sfr_UART3_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** UART3 baud rate register 1 (BRR1 at 0x5242) */ + union { + + /// bytewise access to BRR1 + uint8_t byte; + + /// bitwise access to register BRR1 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR1 bitfield + + /// register _UART3_BRR1 reset value + #define sfr_UART3_BRR1_RESET_VALUE ((uint8_t) 0x00) + + } BRR1; + + + /** UART3 baud rate register 2 (BRR2 at 0x5243) */ + union { + + /// bytewise access to BRR2 + uint8_t byte; + + /// bitwise access to register BRR2 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR2 bitfield + + /// register _UART3_BRR2 reset value + #define sfr_UART3_BRR2_RESET_VALUE ((uint8_t) 0x00) + + } BRR2; + + + /** UART3 control register 1 (CR1 at 0x5244) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PIEN : 1; // bit 0 + BITS PS : 1; // bit 1 + BITS PCEN : 1; // bit 2 + BITS WAKE : 1; // bit 3 + BITS M : 1; // bit 4 + BITS UARTD : 1; // bit 5 + BITS T8 : 1; // bit 6 + BITS R8 : 1; // bit 7 + }; // CR1 bitfield + + /// register _UART3_CR1 reset value + #define sfr_UART3_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** UART3 control register 2 (CR2 at 0x5245) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SBK : 1; // bit 0 + BITS RWU : 1; // bit 1 + BITS REN : 1; // bit 2 + BITS TEN : 1; // bit 3 + BITS ILIEN : 1; // bit 4 + BITS RIEN : 1; // bit 5 + BITS TCIEN : 1; // bit 6 + BITS TIEN : 1; // bit 7 + }; // CR2 bitfield + + /// register _UART3_CR2 reset value + #define sfr_UART3_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** UART3 control register 3 (CR3 at 0x5246) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS : 4; // 4 bits + BITS STOP : 2; // bits 4-5 + BITS LINEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR3 bitfield + + /// register _UART3_CR3 reset value + #define sfr_UART3_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** UART3 control register 4 (CR4 at 0x5247) */ + union { + + /// bytewise access to CR4 + uint8_t byte; + + /// bitwise access to register CR4 + struct { + BITS ADD : 4; // bits 0-3 + BITS LBDF : 1; // bit 4 + BITS LBDL : 1; // bit 5 + BITS LBDIEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR4 bitfield + + /// register _UART3_CR4 reset value + #define sfr_UART3_CR4_RESET_VALUE ((uint8_t) 0x00) + + } CR4; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** UART3 control register 6 (CR6 at 0x5249) */ + union { + + /// bytewise access to CR6 + uint8_t byte; + + /// bitwise access to register CR6 + struct { + BITS LSF : 1; // bit 0 + BITS LHDF : 1; // bit 1 + BITS LHDIEN : 1; // bit 2 + BITS : 1; // 1 bit + BITS LASE : 1; // bit 4 + BITS LSLV : 1; // bit 5 + BITS : 1; // 1 bit + BITS LDUM : 1; // bit 7 + }; // CR6 bitfield + + /// register _UART3_CR6 reset value + #define sfr_UART3_CR6_RESET_VALUE ((uint8_t) 0x00) + + } CR6; + +} UART3_t; + +/// access to UART3 SFR registers +#define sfr_UART3 (*((UART3_t*) 0x5240)) + + +//------------------------ +// Module WWDG +//------------------------ + +/** struct containing WWDG module registers */ +typedef struct { + + /** WWDG control register (CR at 0x50d1) */ + union { + + /// bytewise access to CR + uint8_t byte; + + /// bitwise access to register CR + struct { + BITS T0 : 1; // bit 0 + BITS T1 : 1; // bit 1 + BITS T2 : 1; // bit 2 + BITS T3 : 1; // bit 3 + BITS T4 : 1; // bit 4 + BITS T5 : 1; // bit 5 + BITS T6 : 1; // bit 6 + BITS WDGA : 1; // bit 7 + }; // CR bitfield + + /// register _WWDG_CR reset value + #define sfr_WWDG_CR_RESET_VALUE ((uint8_t) 0x7F) + + } CR; + + + /** WWDR window register (WR at 0x50d2) */ + union { + + /// bytewise access to WR + uint8_t byte; + + /// bitwise access to register WR + struct { + BITS W0 : 1; // bit 0 + BITS W1 : 1; // bit 1 + BITS W2 : 1; // bit 2 + BITS W3 : 1; // bit 3 + BITS W4 : 1; // bit 4 + BITS W5 : 1; // bit 5 + BITS W6 : 1; // bit 6 + BITS : 1; // 1 bit + }; // WR bitfield + + /// register _WWDG_WR reset value + #define sfr_WWDG_WR_RESET_VALUE ((uint8_t) 0x7F) + + } WR; + +} WWDG_t; + +/// access to WWDG SFR registers +#define sfr_WWDG (*((WWDG_t*) 0x50d1)) + + +// undefine local macros +#undef BITS + +// required for C++ +#ifdef __cplusplus + } // extern "C" +#endif + +/*------------------------------------------------------------------------- + END OF MODULE DEFINITION FOR MULTIPLE INLUSION +-------------------------------------------------------------------------*/ +#endif // STM8S207MB_H diff --git a/ports/stm8_oss/stm8-include/config.h b/ports/stm8_oss/stm8-include/config.h new file mode 100644 index 00000000..50c69003 --- /dev/null +++ b/ports/stm8_oss/stm8-include/config.h @@ -0,0 +1,85 @@ +/** + \file config.h + + \brief set project configurations + + set project configurations like used device or board etc. +*/ + +/*----------------------------------------------------------------------------- + MODULE DEFINITION FOR MULTIPLE INCLUSION +-----------------------------------------------------------------------------*/ +#ifndef _CONFIG_H_ +#define _CONFIG_H_ + +/*---------------------------------------------------------- + SELECT BOARD +----------------------------------------------------------*/ +#define STM8S_DISCOVERY +//#define STM8L_DISCOVERY +//#define SDUINO +//#define MUBOARD + + +/*---------------------------------------------------------- + INCLUDE FILES +----------------------------------------------------------*/ +#if defined(STM8S_DISCOVERY) + #include "STM8S105C6.h" + #define LED_PORT sfr_PORTD // port of LED pin + #define LED_PIN PIN0 // bitmask for LED pin + #define USE_TIM2 // TIM2(16bit) or TIM4(8bit). TIM2 requires less tweaking + #define TIM2_ISR_VECTOR _TIM2_OVR_UIF_VECTOR_ // TIM2 update interrupt vector + #define TIM4_ISR_VECTOR _TIM4_OVR_UIF_VECTOR_ // TIM4 update interrupt vector + #define TIM2_ISR_UIF sfr_TIM2.SR1.UIF // TIM2 clear interrupt flag + #define TIM4_ISR_UIF sfr_TIM4.SR.UIF // TIM4 clear interrupt flag + #define USE_UART2 // UART for logging +#elif defined(STM8L_DISCOVERY) + #include "STM8L152C6.h" + #define LED_PORT sfr_PORTE + #define LED_PIN PIN7 + #define USE_TIM2 + #define TIM2_ISR_VECTOR _TIM2_OVR_UIF_VECTOR_ + #define TIM4_ISR_VECTOR _TIM4_UIF_VECTOR_ + #define TIM2_ISR_UIF sfr_TIM2.SR1.UIF + #define TIM4_ISR_UIF sfr_TIM4.SR1.UIF + #define USE_USART1 +#elif defined(SDUINO) + #include "STM8S105K6.h" + #define LED_PORT sfr_PORTC + #define LED_PIN PIN5 + #define USE_TIM2 + #define TIM2_ISR_VECTOR _TIM2_OVR_UIF_VECTOR_ + #define TIM4_ISR_VECTOR _TIM4_OVR_UIF_VECTOR_ + #define TIM2_ISR_UIF sfr_TIM2.SR1.UIF + #define TIM4_ISR_UIF sfr_TIM4.SR.UIF + #define USE_UART2 +#elif defined(MUBOARD) + #include "STM8AF52AA.h" + #define LED_PORT sfr_PORTH + #define LED_PIN PIN2 + #define USE_TIM2 + #define TIM2_ISR_VECTOR _TIM2_OVR_UIF_VECTOR_ + #define TIM4_ISR_VECTOR _TIM4_OVR_UIF_VECTOR_ + #define TIM2_ISR_UIF sfr_TIM2.SR1.UIF + #define TIM4_ISR_UIF sfr_TIM4.SR.UIF +#else + #error undefined board +#endif + + +/*---------------------------------------------------------- + MACROS/DEFINES +----------------------------------------------------------*/ + +// system clock frequency [Hz]. Currently 16MHz, 20MHh, 24MHz (see atomport.c) +#define FSYS_FREQ 16000000L + +// base timeslice for atomthreads [ms] +#define PERIOD_THREADS 10 + + +/*----------------------------------------------------------------------------- + END OF MODULE DEFINITION FOR MULTIPLE INLUSION +-----------------------------------------------------------------------------*/ +#endif // _CONFIG_H_ diff --git a/ports/stm8_oss/stm8_interrupt_vector.c b/ports/stm8_oss/stm8_interrupt_vector.c new file mode 100644 index 00000000..142efa3a --- /dev/null +++ b/ports/stm8_oss/stm8_interrupt_vector.c @@ -0,0 +1,73 @@ +/* BASIC INTERRUPT VECTOR TABLE FOR STM8 devices + * Copyright (c) 2007 STMicroelectronics + */ + + +/* COSMIC: Requires interrupt vector table */ +#if defined(__CSMC__) + +/* Import Atomthreads system tick ISR prototype */ +#include "atomport-private.h" + + +typedef void @far (*interrupt_handler_t)(void); + +struct interrupt_vector { + unsigned char interrupt_instruction; + interrupt_handler_t interrupt_handler; +}; + +@far @interrupt void NonHandledInterrupt (void) +{ + /* in order to detect unexpected events during development, + it is recommended to set a breakpoint on the following instruction + */ + return; +} + +extern void _stext(); /* startup routine */ + +struct interrupt_vector const _vectab[] = { + {0x82, (interrupt_handler_t)_stext}, /* reset */ + {0x82, NonHandledInterrupt}, /* trap */ + {0x82, NonHandledInterrupt}, /* irq0 */ + {0x82, NonHandledInterrupt}, /* irq1 */ + {0x82, NonHandledInterrupt}, /* irq2 */ + {0x82, NonHandledInterrupt}, /* irq3 */ + {0x82, NonHandledInterrupt}, /* irq4 */ + {0x82, NonHandledInterrupt}, /* irq5 */ + {0x82, NonHandledInterrupt}, /* irq6 */ + {0x82, NonHandledInterrupt}, /* irq7 */ + {0x82, NonHandledInterrupt}, /* irq8 */ + {0x82, NonHandledInterrupt}, /* irq9 */ + {0x82, NonHandledInterrupt}, /* irq10 */ + {0x82, NonHandledInterrupt}, /* irq11 */ + {0x82, NonHandledInterrupt}, /* irq12 */ +#if defined(USE_TIM2) + {0x82, TIM2_SystemTickISR}, /* irq13 */ +#else + {0x82, NonHandledInterrupt}, /* irq13 */ +#endif + {0x82, NonHandledInterrupt}, /* irq14 */ + {0x82, NonHandledInterrupt}, /* irq15 */ + {0x82, NonHandledInterrupt}, /* irq16 */ + {0x82, NonHandledInterrupt}, /* irq17 */ + {0x82, NonHandledInterrupt}, /* irq18 */ + {0x82, NonHandledInterrupt}, /* irq19 */ + {0x82, NonHandledInterrupt}, /* irq20 */ + {0x82, NonHandledInterrupt}, /* irq21 */ + {0x82, NonHandledInterrupt}, /* irq22 */ +#if defined(USE_TIM4) + {0x82, TIM4_SystemTickISR}, /* irq23 */ +#else + {0x82, NonHandledInterrupt}, /* irq23 */ +#endif + {0x82, NonHandledInterrupt}, /* irq24 */ + {0x82, NonHandledInterrupt}, /* irq25 */ + {0x82, NonHandledInterrupt}, /* irq26 */ + {0x82, NonHandledInterrupt}, /* irq27 */ + {0x82, NonHandledInterrupt}, /* irq28 */ + {0x82, NonHandledInterrupt}, /* irq29 */ +}; + +#endif /* __CSMC__ */ diff --git a/ports/stm8_oss/test-matrix.ods b/ports/stm8_oss/test-matrix.ods new file mode 100644 index 00000000..b1ed23b3 Binary files /dev/null and b/ports/stm8_oss/test-matrix.ods differ diff --git a/ports/stm8_oss/tests-main.c b/ports/stm8_oss/tests-main.c new file mode 100644 index 00000000..6f92ca9f --- /dev/null +++ b/ports/stm8_oss/tests-main.c @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include + +#include "atom.h" +#include "atomport-private.h" +#include "atomport-tests.h" +#include "atomtests.h" +#include "atomtimer.h" +#include "uart.h" +#include "config.h" + + +/* Constants */ + +/* + * Idle thread stack size + * + * This needs to be large enough to handle any interrupt handlers + * and callbacks called by interrupt handlers (e.g. user-created + * timer callbacks) as well as the saving of all context when + * switching away from this thread. + * + * In this case, the idle stack is allocated on the BSS via the + * idle_thread_stack[] byte array. + */ +#define IDLE_STACK_SIZE_BYTES 128 + + +/* + * Main thread stack size + * + * Note that this is not a required OS kernel thread - you will replace + * this with your own application thread. + * + * In this case the Main thread is responsible for calling out to the + * test routines. Once a test routine has finished, the test status is + * printed out on the UART and the thread remains running in a loop + * flashing a LED. + * + * The Main thread stack generally needs to be larger than the idle + * thread stack, as not only does it need to store interrupt handler + * stack saves and context switch saves, but the application main thread + * will generally be carrying out more nested function calls and require + * stack for application code local variables etc. + * + * With all OS tests implemented to date on the STM8, the Main thread + * stack has not exceeded 384 bytes. To allow all tests to run we set + * a minimum main thread stack size of 204 bytes. This may increase in + * future as the codebase changes but for the time being is enough to + * cope with all of the automated tests. + */ +#define MAIN_STACK_SIZE_BYTES 384 + + +/* + * Startup code stack + * + * Some stack space is required at initial startup for running the main() + * routine. This stack space is only temporarily required at first bootup + * and is no longer required as soon as the OS is started. By default + * Cosmic sets this to the top of RAM and it grows down from there. + * + * Because we only need this temporarily you may reuse the area once the + * OS is started, and are free to use some area other than the top of RAM. + * For convenience we just use the default region here. + */ + + +/* Local data */ + +/* Application threads' TCBs */ +static ATOM_TCB main_tcb; + +/* Main thread's stack area (large so place outside of the small page0 area on STM8) */ +NEAR static uint8_t main_thread_stack[MAIN_STACK_SIZE_BYTES]; + +/* Idle thread's stack area (large so place outside of the small page0 area on STM8) */ +NEAR static uint8_t idle_thread_stack[IDLE_STACK_SIZE_BYTES]; + + +/* Forward declarations */ +static void main_thread_func (uint32_t param); + + +/** + * \b main + * + * Program entry point. + * + * Sets up the STM8 hardware resources (system tick timer interrupt) necessary + * for the OS to be started. Creates an application thread and starts the OS. + * + * If the compiler supports it, stack space can be saved by preventing + * the function from saving registers on entry. This is because we + * are called directly by the C startup assembler, and know that we will + * never return from here. The NO_REG_SAVE macro is used to denote such + * functions in a compiler-agnostic way, though not all compilers support it. + * + */ +NO_REG_SAVE void main ( void ) +{ + int8_t status; + + /** + * Note: to protect OS structures and data during initialisation, + * interrupts must remain disabled until the first thread + * has been restored. They are reenabled at the very end of + * the first thread restore, at which point it is safe for a + * reschedule to take place. + */ + + /* Initialise the OS before creating our threads */ + status = atomOSInit(&idle_thread_stack[0], IDLE_STACK_SIZE_BYTES, TRUE); + if (status == ATOM_OK) + { + /* Enable the system tick timer */ + archInitSystemTickTimer(); + + /* Create an application thread */ + status = atomThreadCreate(&main_tcb, + TEST_THREAD_PRIO, main_thread_func, 0, + &main_thread_stack[0], + MAIN_STACK_SIZE_BYTES, + TRUE); + if (status == ATOM_OK) + { + /** + * First application thread successfully created. It is + * now possible to start the OS. Execution will not return + * from atomOSStart(), which will restore the context of + * our application thread and start executing it. + * + * Note that interrupts are still disabled at this point. + * They will be enabled as we restore and execute our first + * thread in archFirstThreadRestore(). + */ + atomOSStart(); + } + } + + /* There was an error starting the OS if we reach here */ + while (1) + { + } + +} + + +/** + * \b main_thread_func + * + * Entry point for main application thread. + * + * This is the first thread that will be executed when the OS is started. + * + * @param[in] param Unused (optional thread entry parameter) + * + * @return None + */ +static void main_thread_func (uint32_t param) +{ + uint32_t test_status; + int sleep_ticks; + + /* Compiler warnings */ + param = param; + + /* set fMaster prescaler to 1 (default is 8) */ + sfr_CLK.CKDIVR.byte = 0x00; + + /* Initialise UART (9600bps) */ + if (uart_init(9600) != 0) + { + /* Error initialising UART */ + } + + /* Put a message out on the UART */ + printf ("Go\n"); + + /* Start test. All tests use the same start API. */ + test_status = test_start(); + + /* Check main thread stack usage (if enabled) */ +#ifdef ATOM_STACK_CHECKING + if (test_status == 0) + { + uint32_t used_bytes, free_bytes; + + /* Check idle thread stack usage */ + if (atomThreadStackCheck (&main_tcb, &used_bytes, &free_bytes) == ATOM_OK) + { + /* Check the thread did not use up to the end of stack */ + if (free_bytes == 0) + { + printf ("Main stack overflow\n"); + test_status++; + } + + /* Log the stack usage */ +#ifdef TESTS_LOG_STACK_USAGE + printf ("MainUse:%d\n", (int)used_bytes); +#endif + } + + } +#endif + + /* Log final status */ + if (test_status == 0) + { + printf ("Pass\n"); + } + else + { + printf ("Fail(%d)\n", (int)test_status); + } + + /* Flash LED once per second if passed, very quickly if failed */ + sleep_ticks = (test_status == 0) ? SYSTEM_TICKS_PER_SEC : (SYSTEM_TICKS_PER_SEC/8); + + /* Configure GPIO for flashing the board LED (select port&pin in config.h) */ + LED_PORT.DDR.byte |= LED_PIN; // input(=0) or output(=1) + LED_PORT.CR1.byte |= LED_PIN; // input: 0=float, 1=pull-up; output: 0=open-drain, 1=push-pull + LED_PORT.CR2.byte |= LED_PIN; // input: 0=no exint, 1=exint; output: 0=2MHz slope, 1=10MHz slope + + /* Test finished, flash slowly for pass, fast for fail */ + while (1) + { + /* Toggle board LED (select port&pin in config.h) */ + LED_PORT.ODR.byte ^= LED_PIN; + + /* Sleep then toggle LED again */ + atomTimerDelay (sleep_ticks); + } +} diff --git a/ports/stm8_oss/uart.c b/ports/stm8_oss/uart.c new file mode 100644 index 00000000..7eac7cb7 --- /dev/null +++ b/ports/stm8_oss/uart.c @@ -0,0 +1,148 @@ +#include + +// device selection and project settings +#include "config.h" + +#include "atom.h" +#include "atommutex.h" +#include "uart.h" + + +/* + * Semaphore for single-threaded access to UART device + */ +static ATOM_MUTEX uart_mutex; + + +/* + * Initialize the UART to requested baudrate, tx/rx, 8N1. + */ +int uart_init(uint32_t baudrate) +{ + uint16_t tmp_u16; + int status; + + /** + * Set up UART for putting out debug messages, change if required. + */ + + #if defined(USE_USART1) + + // for low-power device enable clock gating to USART1 + #if defined(FAMILY_STM8L) + sfr_CLK.PCKENR1.PCKEN15 = 1; + #endif + + // set UART behaviour + sfr_USART1.CR1.byte = sfr_USART1_CR1_RESET_VALUE; // enable UART2, 8 data bits, no parity control + sfr_USART1.CR2.byte = sfr_USART1_CR2_RESET_VALUE; // no interrupts, disable sender/receiver + sfr_USART1.CR3.byte = sfr_USART1_CR3_RESET_VALUE; // no LIN support, 1 stop bit, no clock output(?) + + // set baudrate (note: BRR2 must be written before BRR1!) + tmp_u16 = (uint16_t) (((uint32_t) 16000000L)/baudrate); + sfr_USART1.BRR2.byte = (uint8_t) (((tmp_u16 & 0xF000) >> 8) | (tmp_u16 & 0x000F)); + sfr_USART1.BRR1.byte = (uint8_t) ((tmp_u16 & 0x0FF0) >> 4); + + // enable transmission, no transmission + sfr_USART1.CR2.REN = 1; // enable receiver + sfr_USART1.CR2.TEN = 1; // enable sender + //sfr_USART1.CR2.TIEN = 1; // enable transmit interrupt + sfr_USART1.CR2.RIEN = 1; // enable receive interrupt + + #elif defined(USE_UART2) + + // set UART2 behaviour + sfr_UART2.CR1.byte = sfr_UART2_CR1_RESET_VALUE; // enable UART2, 8 data bits, no parity control + sfr_UART2.CR2.byte = sfr_UART2_CR2_RESET_VALUE; // no interrupts, disable sender/receiver + sfr_UART2.CR3.byte = sfr_UART2_CR3_RESET_VALUE; // no LIN support, 1 stop bit, no clock output(?) + + // set baudrate (note: BRR2 must be written before BRR1!) + tmp_u16 = (uint16_t) (((uint32_t) 16000000L)/baudrate); + sfr_UART2.BRR2.byte = (uint8_t) (((tmp_u16 & 0xF000) >> 8) | (tmp_u16 & 0x000F)); + sfr_UART2.BRR1.byte = (uint8_t) ((tmp_u16 & 0x0FF0) >> 4); + + // enable transmission, no transmission + sfr_UART2.CR2.REN = 1; // enable receiver + sfr_UART2.CR2.TEN = 1; // enable sender + //sfr_UART2.CR2.TIEN = 1; // enable transmit interrupt + sfr_UART2.CR2.RIEN = 1; // enable receive interrupt + + // error + #else + #error selected UART in config.h not yet supported + #endif + + + /* Create a mutex for single-threaded putchar() access */ + if (atomMutexCreate (&uart_mutex) != ATOM_OK) + { + status = -1; + } + else + { + status = 0; + } + + /* Finished */ + return (status); +} + + +/** + * \b uart_putchar + * + * Write a char out via UART2 + * + * @param[in] c Character to send + * + * @return Character sent + */ +char uart_putchar (char c) +{ + /* Block on private access to the UART */ + if (atomMutexGet(&uart_mutex, 0) == ATOM_OK) + { + /* Convert \n to \r\n */ + if (c == '\n') + putchar('\r'); + + #if defined(USE_USART1) + /* Write a character to the UART */ + sfr_USART1.DR.byte = c; + + /* Loop until the end of transmission */ + while (!(sfr_USART1.SR.TXE)) + ; + + // STM8S + #elif defined(USE_UART2) + /* Write a character to the UART */ + sfr_UART2.DR.byte = c; + + /* Loop until the end of transmission */ + while (!(sfr_UART2.SR.TXE)) + ; + + // error + #else + #error selected UART in config.h not yet supported + #endif + + /* Return mutex access */ + atomMutexPut(&uart_mutex); + + } + + return (c); +} + + +/* Implement putchar() routine for stdio */ +#if defined(__CSMC__) + char putchar(char c) +#else // Standard C + int putchar(int c) +#endif +{ + return (uart_putchar(c)); +} diff --git a/ports/stm8_oss/uart.h b/ports/stm8_oss/uart.h new file mode 100644 index 00000000..75079270 --- /dev/null +++ b/ports/stm8_oss/uart.h @@ -0,0 +1,9 @@ + +#include "atom.h" + + +/* + * Perform UART startup initialization. + */ +int uart_init(uint32_t baudrate); +